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b43/b43legacy: Wake queues in wireless_core_start
[net-next-2.6.git] / drivers / net / wireless / b43 / main.c
CommitLineData
e4d6b795
MB		 1/*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
1f21ad2a 6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
060210f9 7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
e4d6b795
MB		 8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
3dbba8e2
AH		 11 SDIO support
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
13
e4d6b795
MB		 14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
16
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
21
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
26
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
31
32*/
33
34#include <linux/delay.h>
35#include <linux/init.h>
36#include <linux/moduleparam.h>
37#include <linux/if_arp.h>
38#include <linux/etherdevice.h>
e4d6b795
MB		 39#include <linux/firmware.h>
40#include <linux/wireless.h>
41#include <linux/workqueue.h>
42#include <linux/skbuff.h>
96cf49a2 43#include <linux/io.h>
e4d6b795
MB		 44#include <linux/dma-mapping.h>
45#include <asm/unaligned.h>
46
47#include "b43.h"
48#include "main.h"
49#include "debugfs.h"
ef1a628d
MB		 50#include "phy_common.h"
51#include "phy_g.h"
3d0da751 52#include "phy_n.h"
e4d6b795 53#include "dma.h"
5100d5ac 54#include "pio.h"
e4d6b795
MB		 55#include "sysfs.h"
56#include "xmit.h"
e4d6b795
MB		 57#include "lo.h"
58#include "pcmcia.h"
3dbba8e2
AH		 59#include "sdio.h"
60#include <linux/mmc/sdio_func.h>
e4d6b795
MB		 61
62MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63MODULE_AUTHOR("Martin Langer");
64MODULE_AUTHOR("Stefano Brivio");
65MODULE_AUTHOR("Michael Buesch");
0136e51e 66MODULE_AUTHOR("Gábor Stefanik");
e4d6b795
MB		 67MODULE_LICENSE("GPL");
68
9c7d99d6 69MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
6021e08d
TG		 70MODULE_FIRMWARE("b43/ucode11.fw");
71MODULE_FIRMWARE("b43/ucode13.fw");
72MODULE_FIRMWARE("b43/ucode14.fw");
73MODULE_FIRMWARE("b43/ucode15.fw");
74MODULE_FIRMWARE("b43/ucode5.fw");
75MODULE_FIRMWARE("b43/ucode9.fw");
e4d6b795
MB		 76
77static int modparam_bad_frames_preempt;
78module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
79MODULE_PARM_DESC(bad_frames_preempt,
80 "enable(1) / disable(0) Bad Frames Preemption");
81
e4d6b795
MB		 82static char modparam_fwpostfix[16];
83module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
84MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
85
e4d6b795
MB		 86static int modparam_hwpctl;
87module_param_named(hwpctl, modparam_hwpctl, int, 0444);
88MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
89
90static int modparam_nohwcrypt;
91module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
92MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
93
035d0243 94static int modparam_hwtkip;
95module_param_named(hwtkip, modparam_hwtkip, int, 0444);
96MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
97
403a3a13
MB		 98static int modparam_qos = 1;
99module_param_named(qos, modparam_qos, int, 0444);
e6f5b934
MB		 100MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
101
1855ba78
MB		 102static int modparam_btcoex = 1;
103module_param_named(btcoex, modparam_btcoex, int, 0444);
c71dbd33 104MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
1855ba78 105
060210f9
MB		 106int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
107module_param_named(verbose, b43_modparam_verbose, int, 0644);
108MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
109
b02914af
LF		 110static int modparam_pio;
111module_param_named(pio, modparam_pio, int, 0444);
112MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
e6f5b934 113
e4d6b795
MB		 114static const struct ssb_device_id b43_ssb_tbl[] = {
115 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
116 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
117 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
118 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
119 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
d5c71e46 120 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
003d6d27 121 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
013978b6 122 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
6b1c7c67 123 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
92d6128e 124 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
e4d6b795
MB		 125 SSB_DEVTABLE_END
126};
127
128MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
129
130/* Channel and ratetables are shared for all devices.
131 * They can't be const, because ieee80211 puts some precalculated
132 * data in there. This data is the same for all devices, so we don't
133 * get concurrency issues */
134#define RATETAB_ENT(_rateid, _flags) \
8318d78a
JB		 135 { \
136 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
137 .hw_value = (_rateid), \
138 .flags = (_flags), \
e4d6b795 139 }
8318d78a
JB		 140
141/*
142 * NOTE: When changing this, sync with xmit.c's
143 * b43_plcp_get_bitrate_idx_* functions!
144 */
e4d6b795 145static struct ieee80211_rate __b43_ratetable[] = {
8318d78a
JB		 146 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
147 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
148 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
149 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
150 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
151 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
152 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
153 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
154 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
155 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
156 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
157 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
e4d6b795
MB		 158};
159
160#define b43_a_ratetable (__b43_ratetable + 4)
161#define b43_a_ratetable_size 8
162#define b43_b_ratetable (__b43_ratetable + 0)
163#define b43_b_ratetable_size 4
164#define b43_g_ratetable (__b43_ratetable + 0)
165#define b43_g_ratetable_size 12
166
bb1eeff1
MB		 167#define CHAN4G(_channel, _freq, _flags) { \
168 .band = IEEE80211_BAND_2GHZ, \
169 .center_freq = (_freq), \
170 .hw_value = (_channel), \
171 .flags = (_flags), \
172 .max_antenna_gain = 0, \
173 .max_power = 30, \
174}
96c755a3 175static struct ieee80211_channel b43_2ghz_chantable[] = {
bb1eeff1
MB		 176 CHAN4G(1, 2412, 0),
177 CHAN4G(2, 2417, 0),
178 CHAN4G(3, 2422, 0),
179 CHAN4G(4, 2427, 0),
180 CHAN4G(5, 2432, 0),
181 CHAN4G(6, 2437, 0),
182 CHAN4G(7, 2442, 0),
183 CHAN4G(8, 2447, 0),
184 CHAN4G(9, 2452, 0),
185 CHAN4G(10, 2457, 0),
186 CHAN4G(11, 2462, 0),
187 CHAN4G(12, 2467, 0),
188 CHAN4G(13, 2472, 0),
189 CHAN4G(14, 2484, 0),
190};
191#undef CHAN4G
192
193#define CHAN5G(_channel, _flags) { \
194 .band = IEEE80211_BAND_5GHZ, \
195 .center_freq = 5000 + (5 * (_channel)), \
196 .hw_value = (_channel), \
197 .flags = (_flags), \
198 .max_antenna_gain = 0, \
199 .max_power = 30, \
200}
201static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
202 CHAN5G(32, 0), CHAN5G(34, 0),
203 CHAN5G(36, 0), CHAN5G(38, 0),
204 CHAN5G(40, 0), CHAN5G(42, 0),
205 CHAN5G(44, 0), CHAN5G(46, 0),
206 CHAN5G(48, 0), CHAN5G(50, 0),
207 CHAN5G(52, 0), CHAN5G(54, 0),
208 CHAN5G(56, 0), CHAN5G(58, 0),
209 CHAN5G(60, 0), CHAN5G(62, 0),
210 CHAN5G(64, 0), CHAN5G(66, 0),
211 CHAN5G(68, 0), CHAN5G(70, 0),
212 CHAN5G(72, 0), CHAN5G(74, 0),
213 CHAN5G(76, 0), CHAN5G(78, 0),
214 CHAN5G(80, 0), CHAN5G(82, 0),
215 CHAN5G(84, 0), CHAN5G(86, 0),
216 CHAN5G(88, 0), CHAN5G(90, 0),
217 CHAN5G(92, 0), CHAN5G(94, 0),
218 CHAN5G(96, 0), CHAN5G(98, 0),
219 CHAN5G(100, 0), CHAN5G(102, 0),
220 CHAN5G(104, 0), CHAN5G(106, 0),
221 CHAN5G(108, 0), CHAN5G(110, 0),
222 CHAN5G(112, 0), CHAN5G(114, 0),
223 CHAN5G(116, 0), CHAN5G(118, 0),
224 CHAN5G(120, 0), CHAN5G(122, 0),
225 CHAN5G(124, 0), CHAN5G(126, 0),
226 CHAN5G(128, 0), CHAN5G(130, 0),
227 CHAN5G(132, 0), CHAN5G(134, 0),
228 CHAN5G(136, 0), CHAN5G(138, 0),
229 CHAN5G(140, 0), CHAN5G(142, 0),
230 CHAN5G(144, 0), CHAN5G(145, 0),
231 CHAN5G(146, 0), CHAN5G(147, 0),
232 CHAN5G(148, 0), CHAN5G(149, 0),
233 CHAN5G(150, 0), CHAN5G(151, 0),
234 CHAN5G(152, 0), CHAN5G(153, 0),
235 CHAN5G(154, 0), CHAN5G(155, 0),
236 CHAN5G(156, 0), CHAN5G(157, 0),
237 CHAN5G(158, 0), CHAN5G(159, 0),
238 CHAN5G(160, 0), CHAN5G(161, 0),
239 CHAN5G(162, 0), CHAN5G(163, 0),
240 CHAN5G(164, 0), CHAN5G(165, 0),
241 CHAN5G(166, 0), CHAN5G(168, 0),
242 CHAN5G(170, 0), CHAN5G(172, 0),
243 CHAN5G(174, 0), CHAN5G(176, 0),
244 CHAN5G(178, 0), CHAN5G(180, 0),
245 CHAN5G(182, 0), CHAN5G(184, 0),
246 CHAN5G(186, 0), CHAN5G(188, 0),
247 CHAN5G(190, 0), CHAN5G(192, 0),
248 CHAN5G(194, 0), CHAN5G(196, 0),
249 CHAN5G(198, 0), CHAN5G(200, 0),
250 CHAN5G(202, 0), CHAN5G(204, 0),
251 CHAN5G(206, 0), CHAN5G(208, 0),
252 CHAN5G(210, 0), CHAN5G(212, 0),
253 CHAN5G(214, 0), CHAN5G(216, 0),
254 CHAN5G(218, 0), CHAN5G(220, 0),
255 CHAN5G(222, 0), CHAN5G(224, 0),
256 CHAN5G(226, 0), CHAN5G(228, 0),
e4d6b795
MB		 257};
258
bb1eeff1
MB		 259static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
260 CHAN5G(34, 0), CHAN5G(36, 0),
261 CHAN5G(38, 0), CHAN5G(40, 0),
262 CHAN5G(42, 0), CHAN5G(44, 0),
263 CHAN5G(46, 0), CHAN5G(48, 0),
264 CHAN5G(52, 0), CHAN5G(56, 0),
265 CHAN5G(60, 0), CHAN5G(64, 0),
266 CHAN5G(100, 0), CHAN5G(104, 0),
267 CHAN5G(108, 0), CHAN5G(112, 0),
268 CHAN5G(116, 0), CHAN5G(120, 0),
269 CHAN5G(124, 0), CHAN5G(128, 0),
270 CHAN5G(132, 0), CHAN5G(136, 0),
271 CHAN5G(140, 0), CHAN5G(149, 0),
272 CHAN5G(153, 0), CHAN5G(157, 0),
273 CHAN5G(161, 0), CHAN5G(165, 0),
274 CHAN5G(184, 0), CHAN5G(188, 0),
275 CHAN5G(192, 0), CHAN5G(196, 0),
276 CHAN5G(200, 0), CHAN5G(204, 0),
277 CHAN5G(208, 0), CHAN5G(212, 0),
278 CHAN5G(216, 0),
279};
280#undef CHAN5G
281
282static struct ieee80211_supported_band b43_band_5GHz_nphy = {
283 .band = IEEE80211_BAND_5GHZ,
284 .channels = b43_5ghz_nphy_chantable,
285 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
286 .bitrates = b43_a_ratetable,
287 .n_bitrates = b43_a_ratetable_size,
e4d6b795 288};
8318d78a 289
bb1eeff1
MB		 290static struct ieee80211_supported_band b43_band_5GHz_aphy = {
291 .band = IEEE80211_BAND_5GHZ,
292 .channels = b43_5ghz_aphy_chantable,
293 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
294 .bitrates = b43_a_ratetable,
295 .n_bitrates = b43_a_ratetable_size,
8318d78a 296};
e4d6b795 297
8318d78a 298static struct ieee80211_supported_band b43_band_2GHz = {
bb1eeff1
MB		 299 .band = IEEE80211_BAND_2GHZ,
300 .channels = b43_2ghz_chantable,
301 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
302 .bitrates = b43_g_ratetable,
303 .n_bitrates = b43_g_ratetable_size,
8318d78a
JB		 304};
305
e4d6b795
MB		 306static void b43_wireless_core_exit(struct b43_wldev *dev);
307static int b43_wireless_core_init(struct b43_wldev *dev);
36dbd954 308static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
e4d6b795
MB		 309static int b43_wireless_core_start(struct b43_wldev *dev);
310
311static int b43_ratelimit(struct b43_wl *wl)
312{
313 if (!wl || !wl->current_dev)
314 return 1;
315 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
316 return 1;
317 /* We are up and running.
318 * Ratelimit the messages to avoid DoS over the net. */
319 return net_ratelimit();
320}
321
322void b43info(struct b43_wl *wl, const char *fmt, ...)
323{
324 va_list args;
325
060210f9
MB		 326 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
327 return;
e4d6b795
MB		 328 if (!b43_ratelimit(wl))
329 return;
330 va_start(args, fmt);
331 printk(KERN_INFO "b43-%s: ",
332 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
333 vprintk(fmt, args);
334 va_end(args);
335}
336
337void b43err(struct b43_wl *wl, const char *fmt, ...)
338{
339 va_list args;
340
060210f9
MB		 341 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
342 return;
e4d6b795
MB		 343 if (!b43_ratelimit(wl))
344 return;
345 va_start(args, fmt);
346 printk(KERN_ERR "b43-%s ERROR: ",
347 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
348 vprintk(fmt, args);
349 va_end(args);
350}
351
352void b43warn(struct b43_wl *wl, const char *fmt, ...)
353{
354 va_list args;
355
060210f9
MB		 356 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
357 return;
e4d6b795
MB		 358 if (!b43_ratelimit(wl))
359 return;
360 va_start(args, fmt);
361 printk(KERN_WARNING "b43-%s warning: ",
362 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
363 vprintk(fmt, args);
364 va_end(args);
365}
366
e4d6b795
MB		 367void b43dbg(struct b43_wl *wl, const char *fmt, ...)
368{
369 va_list args;
370
060210f9
MB		 371 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
372 return;
e4d6b795
MB		 373 va_start(args, fmt);
374 printk(KERN_DEBUG "b43-%s debug: ",
375 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
376 vprintk(fmt, args);
377 va_end(args);
378}
e4d6b795
MB		 379
380static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
381{
382 u32 macctl;
383
384 B43_WARN_ON(offset % 4 != 0);
385
386 macctl = b43_read32(dev, B43_MMIO_MACCTL);
387 if (macctl & B43_MACCTL_BE)
388 val = swab32(val);
389
390 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
391 mmiowb();
392 b43_write32(dev, B43_MMIO_RAM_DATA, val);
393}
394
280d0e16
MB		 395static inline void b43_shm_control_word(struct b43_wldev *dev,
396 u16 routing, u16 offset)
e4d6b795
MB		 397{
398 u32 control;
399
400 /* "offset" is the WORD offset. */
e4d6b795
MB		 401 control = routing;
402 control <<= 16;
403 control |= offset;
404 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
405}
406
69eddc8a 407u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
e4d6b795
MB		 408{
409 u32 ret;
410
411 if (routing == B43_SHM_SHARED) {
412 B43_WARN_ON(offset & 0x0001);
413 if (offset & 0x0003) {
414 /* Unaligned access */
415 b43_shm_control_word(dev, routing, offset >> 2);
416 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
e4d6b795 417 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd 418 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
e4d6b795 419
280d0e16 420 goto out;
e4d6b795
MB		 421 }
422 offset >>= 2;
423 }
424 b43_shm_control_word(dev, routing, offset);
425 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
280d0e16 426out:
e4d6b795
MB		 427 return ret;
428}
429
69eddc8a 430u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
6bbc321a
MB		 431{
432 u16 ret;
433
e4d6b795
MB		 434 if (routing == B43_SHM_SHARED) {
435 B43_WARN_ON(offset & 0x0001);
436 if (offset & 0x0003) {
437 /* Unaligned access */
438 b43_shm_control_word(dev, routing, offset >> 2);
439 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
440
280d0e16 441 goto out;
e4d6b795
MB		 442 }
443 offset >>= 2;
444 }
445 b43_shm_control_word(dev, routing, offset);
446 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
280d0e16 447out:
e4d6b795
MB		 448 return ret;
449}
450
69eddc8a 451void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
6bbc321a 452{
e4d6b795
MB		 453 if (routing == B43_SHM_SHARED) {
454 B43_WARN_ON(offset & 0x0001);
455 if (offset & 0x0003) {
456 /* Unaligned access */
457 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 458 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
f62ae6cd 459 value & 0xFFFF);
e4d6b795 460 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
f62ae6cd
MB		 461 b43_write16(dev, B43_MMIO_SHM_DATA,
462 (value >> 16) & 0xFFFF);
6bbc321a 463 return;
e4d6b795
MB		 464 }
465 offset >>= 2;
466 }
467 b43_shm_control_word(dev, routing, offset);
e4d6b795
MB		 468 b43_write32(dev, B43_MMIO_SHM_DATA, value);
469}
470
69eddc8a 471void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
6bbc321a 472{
e4d6b795
MB		 473 if (routing == B43_SHM_SHARED) {
474 B43_WARN_ON(offset & 0x0001);
475 if (offset & 0x0003) {
476 /* Unaligned access */
477 b43_shm_control_word(dev, routing, offset >> 2);
e4d6b795 478 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
6bbc321a 479 return;
e4d6b795
MB		 480 }
481 offset >>= 2;
482 }
483 b43_shm_control_word(dev, routing, offset);
e4d6b795 484 b43_write16(dev, B43_MMIO_SHM_DATA, value);
6bbc321a
MB		 485}
486
e4d6b795 487/* Read HostFlags */
99da185a 488u64 b43_hf_read(struct b43_wldev *dev)
e4d6b795 489{
35f0d354 490 u64 ret;
e4d6b795
MB		 491
492 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
493 ret <<= 16;
35f0d354
MB		 494 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
495 ret <<= 16;
e4d6b795
MB		 496 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
497
498 return ret;
499}
500
501/* Write HostFlags */
35f0d354 502void b43_hf_write(struct b43_wldev *dev, u64 value)
e4d6b795 503{
35f0d354
MB		 504 u16 lo, mi, hi;
505
506 lo = (value & 0x00000000FFFFULL);
507 mi = (value & 0x0000FFFF0000ULL) >> 16;
508 hi = (value & 0xFFFF00000000ULL) >> 32;
509 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
510 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
511 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
e4d6b795
MB		 512}
513
403a3a13
MB		 514/* Read the firmware capabilities bitmask (Opensource firmware only) */
515static u16 b43_fwcapa_read(struct b43_wldev *dev)
516{
517 B43_WARN_ON(!dev->fw.opensource);
518 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
519}
520
3ebbbb56 521void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
e4d6b795 522{
3ebbbb56
MB		 523 u32 low, high;
524
525 B43_WARN_ON(dev->dev->id.revision < 3);
526
527 /* The hardware guarantees us an atomic read, if we
528 * read the low register first. */
529 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
530 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
531
532 *tsf = high;
533 *tsf <<= 32;
534 *tsf |= low;
e4d6b795
MB		 535}
536
537static void b43_time_lock(struct b43_wldev *dev)
538{
539 u32 macctl;
540
541 macctl = b43_read32(dev, B43_MMIO_MACCTL);
542 macctl |= B43_MACCTL_TBTTHOLD;
543 b43_write32(dev, B43_MMIO_MACCTL, macctl);
544 /* Commit the write */
545 b43_read32(dev, B43_MMIO_MACCTL);
546}
547
548static void b43_time_unlock(struct b43_wldev *dev)
549{
550 u32 macctl;
551
552 macctl = b43_read32(dev, B43_MMIO_MACCTL);
553 macctl &= ~B43_MACCTL_TBTTHOLD;
554 b43_write32(dev, B43_MMIO_MACCTL, macctl);
555 /* Commit the write */
556 b43_read32(dev, B43_MMIO_MACCTL);
557}
558
559static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
560{
3ebbbb56
MB		 561 u32 low, high;
562
563 B43_WARN_ON(dev->dev->id.revision < 3);
564
565 low = tsf;
566 high = (tsf >> 32);
567 /* The hardware guarantees us an atomic write, if we
568 * write the low register first. */
569 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
570 mmiowb();
571 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
572 mmiowb();
e4d6b795
MB		 573}
574
575void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
576{
577 b43_time_lock(dev);
578 b43_tsf_write_locked(dev, tsf);
579 b43_time_unlock(dev);
580}
581
582static
99da185a 583void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
e4d6b795
MB		 584{
585 static const u8 zero_addr[ETH_ALEN] = { 0 };
586 u16 data;
587
588 if (!mac)
589 mac = zero_addr;
590
591 offset |= 0x0020;
592 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
593
594 data = mac[0];
595 data |= mac[1] << 8;
596 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
597 data = mac[2];
598 data |= mac[3] << 8;
599 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
600 data = mac[4];
601 data |= mac[5] << 8;
602 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
603}
604
605static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
606{
607 const u8 *mac;
608 const u8 *bssid;
609 u8 mac_bssid[ETH_ALEN * 2];
610 int i;
611 u32 tmp;
612
613 bssid = dev->wl->bssid;
614 mac = dev->wl->mac_addr;
615
616 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
617
618 memcpy(mac_bssid, mac, ETH_ALEN);
619 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
620
621 /* Write our MAC address and BSSID to template ram */
622 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
623 tmp = (u32) (mac_bssid[i + 0]);
624 tmp |= (u32) (mac_bssid[i + 1]) << 8;
625 tmp |= (u32) (mac_bssid[i + 2]) << 16;
626 tmp |= (u32) (mac_bssid[i + 3]) << 24;
627 b43_ram_write(dev, 0x20 + i, tmp);
628 }
629}
630
4150c572 631static void b43_upload_card_macaddress(struct b43_wldev *dev)
e4d6b795 632{
e4d6b795 633 b43_write_mac_bssid_templates(dev);
4150c572 634 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
e4d6b795
MB		 635}
636
637static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
638{
639 /* slot_time is in usec. */
b6c3f5be
LF		 640 /* This test used to exit for all but a G PHY. */
641 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
e4d6b795 642 return;
b6c3f5be
LF		 643 b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
644 /* Shared memory location 0x0010 is the slot time and should be
645 * set to slot_time; however, this register is initially 0 and changing
646 * the value adversely affects the transmit rate for BCM4311
647 * devices. Until this behavior is unterstood, delete this step
648 *
649 * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
650 */
e4d6b795
MB		 651}
652
653static void b43_short_slot_timing_enable(struct b43_wldev *dev)
654{
655 b43_set_slot_time(dev, 9);
e4d6b795
MB		 656}
657
658static void b43_short_slot_timing_disable(struct b43_wldev *dev)
659{
660 b43_set_slot_time(dev, 20);
e4d6b795
MB		 661}
662
e4d6b795 663/* DummyTransmission function, as documented on
2f19c287 664 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
e4d6b795 665 */
2f19c287 666void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
e4d6b795
MB		 667{
668 struct b43_phy *phy = &dev->phy;
669 unsigned int i, max_loop;
670 u16 value;
671 u32 buffer[5] = {
672 0x00000000,
673 0x00D40000,
674 0x00000000,
675 0x01000000,
676 0x00000000,
677 };
678
2f19c287 679 if (ofdm) {
e4d6b795
MB		 680 max_loop = 0x1E;
681 buffer[0] = 0x000201CC;
2f19c287 682 } else {
e4d6b795
MB		 683 max_loop = 0xFA;
684 buffer[0] = 0x000B846E;
e4d6b795
MB		 685 }
686
687 for (i = 0; i < 5; i++)
688 b43_ram_write(dev, i * 4, buffer[i]);
689
e4d6b795 690 b43_write16(dev, 0x0568, 0x0000);
2f19c287
GS		 691 if (dev->dev->id.revision < 11)
692 b43_write16(dev, 0x07C0, 0x0000);
693 else
694 b43_write16(dev, 0x07C0, 0x0100);
695 value = (ofdm ? 0x41 : 0x40);
e4d6b795 696 b43_write16(dev, 0x050C, value);
2f19c287
GS		 697 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
698 b43_write16(dev, 0x0514, 0x1A02);
e4d6b795
MB		 699 b43_write16(dev, 0x0508, 0x0000);
700 b43_write16(dev, 0x050A, 0x0000);
701 b43_write16(dev, 0x054C, 0x0000);
702 b43_write16(dev, 0x056A, 0x0014);
703 b43_write16(dev, 0x0568, 0x0826);
704 b43_write16(dev, 0x0500, 0x0000);
2f19c287
GS		 705 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
706 //SPEC TODO
707 }
708
709 switch (phy->type) {
710 case B43_PHYTYPE_N:
711 b43_write16(dev, 0x0502, 0x00D0);
712 break;
713 case B43_PHYTYPE_LP:
714 b43_write16(dev, 0x0502, 0x0050);
715 break;
716 default:
717 b43_write16(dev, 0x0502, 0x0030);
718 }
e4d6b795
MB		 719
720 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
721 b43_radio_write16(dev, 0x0051, 0x0017);
722 for (i = 0x00; i < max_loop; i++) {
723 value = b43_read16(dev, 0x050E);
724 if (value & 0x0080)
725 break;
726 udelay(10);
727 }
728 for (i = 0x00; i < 0x0A; i++) {
729 value = b43_read16(dev, 0x050E);
730 if (value & 0x0400)
731 break;
732 udelay(10);
733 }
1d280ddc 734 for (i = 0x00; i < 0x19; i++) {
e4d6b795
MB		 735 value = b43_read16(dev, 0x0690);
736 if (!(value & 0x0100))
737 break;
738 udelay(10);
739 }
740 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
741 b43_radio_write16(dev, 0x0051, 0x0037);
742}
743
744static void key_write(struct b43_wldev *dev,
99da185a 745 u8 index, u8 algorithm, const u8 *key)
e4d6b795
MB		 746{
747 unsigned int i;
748 u32 offset;
749 u16 value;
750 u16 kidx;
751
752 /* Key index/algo block */
753 kidx = b43_kidx_to_fw(dev, index);
754 value = ((kidx << 4) | algorithm);
755 b43_shm_write16(dev, B43_SHM_SHARED,
756 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
757
758 /* Write the key to the Key Table Pointer offset */
759 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
760 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
761 value = key[i];
762 value |= (u16) (key[i + 1]) << 8;
763 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
764 }
765}
766
99da185a 767static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
e4d6b795
MB		 768{
769 u32 addrtmp[2] = { 0, 0, };
66d2d089 770 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 771
772 if (b43_new_kidx_api(dev))
66d2d089 773 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 774
66d2d089
MB		 775 B43_WARN_ON(index < pairwise_keys_start);
776 /* We have four default TX keys and possibly four default RX keys.
e4d6b795
MB		 777 * Physical mac 0 is mapped to physical key 4 or 8, depending
778 * on the firmware version.
779 * So we must adjust the index here.
780 */
66d2d089
MB		 781 index -= pairwise_keys_start;
782 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
e4d6b795
MB		 783
784 if (addr) {
785 addrtmp[0] = addr[0];
786 addrtmp[0] |= ((u32) (addr[1]) << 8);
787 addrtmp[0] |= ((u32) (addr[2]) << 16);
788 addrtmp[0] |= ((u32) (addr[3]) << 24);
789 addrtmp[1] = addr[4];
790 addrtmp[1] |= ((u32) (addr[5]) << 8);
791 }
792
66d2d089
MB		 793 /* Receive match transmitter address (RCMTA) mechanism */
794 b43_shm_write32(dev, B43_SHM_RCMTA,
795 (index * 2) + 0, addrtmp[0]);
796 b43_shm_write16(dev, B43_SHM_RCMTA,
797 (index * 2) + 1, addrtmp[1]);
e4d6b795
MB		 798}
799
035d0243 800/* The ucode will use phase1 key with TEK key to decrypt rx packets.
801 * When a packet is received, the iv32 is checked.
802 * - if it doesn't the packet is returned without modification (and software
803 * decryption can be done). That's what happen when iv16 wrap.
804 * - if it does, the rc4 key is computed, and decryption is tried.
805 * Either it will success and B43_RX_MAC_DEC is returned,
806 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
807 * and the packet is not usable (it got modified by the ucode).
808 * So in order to never have B43_RX_MAC_DECERR, we should provide
809 * a iv32 and phase1key that match. Because we drop packets in case of
810 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
811 * packets will be lost without higher layer knowing (ie no resync possible
812 * until next wrap).
813 *
814 * NOTE : this should support 50 key like RCMTA because
815 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
816 */
817static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
818 u16 *phase1key)
819{
820 unsigned int i;
821 u32 offset;
822 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
823
824 if (!modparam_hwtkip)
825 return;
826
827 if (b43_new_kidx_api(dev))
828 pairwise_keys_start = B43_NR_GROUP_KEYS;
829
830 B43_WARN_ON(index < pairwise_keys_start);
831 /* We have four default TX keys and possibly four default RX keys.
832 * Physical mac 0 is mapped to physical key 4 or 8, depending
833 * on the firmware version.
834 * So we must adjust the index here.
835 */
836 index -= pairwise_keys_start;
837 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
838
839 if (b43_debug(dev, B43_DBG_KEYS)) {
840 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
841 index, iv32);
842 }
843 /* Write the key to the RX tkip shared mem */
844 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
845 for (i = 0; i < 10; i += 2) {
846 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
847 phase1key ? phase1key[i / 2] : 0);
848 }
849 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
850 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
851}
852
853static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
b3fbdcf4
JB		 854 struct ieee80211_vif *vif,
855 struct ieee80211_key_conf *keyconf,
856 struct ieee80211_sta *sta,
857 u32 iv32, u16 *phase1key)
035d0243 858{
859 struct b43_wl *wl = hw_to_b43_wl(hw);
860 struct b43_wldev *dev;
861 int index = keyconf->hw_key_idx;
862
863 if (B43_WARN_ON(!modparam_hwtkip))
864 return;
865
96869a39
MB		 866 /* This is only called from the RX path through mac80211, where
867 * our mutex is already locked. */
868 B43_WARN_ON(!mutex_is_locked(&wl->mutex));
035d0243 869 dev = wl->current_dev;
96869a39 870 B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
035d0243 871
872 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
873
874 rx_tkip_phase1_write(dev, index, iv32, phase1key);
b3fbdcf4
JB		 875 /* only pairwise TKIP keys are supported right now */
876 if (WARN_ON(!sta))
96869a39 877 return;
b3fbdcf4 878 keymac_write(dev, index, sta->addr);
035d0243 879}
880
e4d6b795
MB		 881static void do_key_write(struct b43_wldev *dev,
882 u8 index, u8 algorithm,
99da185a 883 const u8 *key, size_t key_len, const u8 *mac_addr)
e4d6b795
MB		 884{
885 u8 buf[B43_SEC_KEYSIZE] = { 0, };
66d2d089 886 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
e4d6b795
MB		 887
888 if (b43_new_kidx_api(dev))
66d2d089 889 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 890
66d2d089 891 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 892 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
893
66d2d089 894 if (index >= pairwise_keys_start)
e4d6b795 895 keymac_write(dev, index, NULL); /* First zero out mac. */
035d0243 896 if (algorithm == B43_SEC_ALGO_TKIP) {
897 /*
898 * We should provide an initial iv32, phase1key pair.
899 * We could start with iv32=0 and compute the corresponding
900 * phase1key, but this means calling ieee80211_get_tkip_key
901 * with a fake skb (or export other tkip function).
902 * Because we are lazy we hope iv32 won't start with
903 * 0xffffffff and let's b43_op_update_tkip_key provide a
904 * correct pair.
905 */
906 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
907 } else if (index >= pairwise_keys_start) /* clear it */
908 rx_tkip_phase1_write(dev, index, 0, NULL);
e4d6b795
MB		 909 if (key)
910 memcpy(buf, key, key_len);
911 key_write(dev, index, algorithm, buf);
66d2d089 912 if (index >= pairwise_keys_start)
e4d6b795
MB		 913 keymac_write(dev, index, mac_addr);
914
915 dev->key[index].algorithm = algorithm;
916}
917
918static int b43_key_write(struct b43_wldev *dev,
919 int index, u8 algorithm,
99da185a
JD		 920 const u8 *key, size_t key_len,
921 const u8 *mac_addr,
e4d6b795
MB		 922 struct ieee80211_key_conf *keyconf)
923{
924 int i;
66d2d089 925 int pairwise_keys_start;
e4d6b795 926
035d0243 927 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
928 * - Temporal Encryption Key (128 bits)
929 * - Temporal Authenticator Tx MIC Key (64 bits)
930 * - Temporal Authenticator Rx MIC Key (64 bits)
931 *
932 * Hardware only store TEK
933 */
934 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
935 key_len = 16;
e4d6b795
MB		 936 if (key_len > B43_SEC_KEYSIZE)
937 return -EINVAL;
66d2d089 938 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
e4d6b795
MB		 939 /* Check that we don't already have this key. */
940 B43_WARN_ON(dev->key[i].keyconf == keyconf);
941 }
942 if (index < 0) {
e808e586 943 /* Pairwise key. Get an empty slot for the key. */
e4d6b795 944 if (b43_new_kidx_api(dev))
66d2d089 945 pairwise_keys_start = B43_NR_GROUP_KEYS;
e4d6b795 946 else
66d2d089
MB		 947 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
948 for (i = pairwise_keys_start;
949 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
950 i++) {
951 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
e4d6b795
MB		 952 if (!dev->key[i].keyconf) {
953 /* found empty */
954 index = i;
955 break;
956 }
957 }
958 if (index < 0) {
e808e586 959 b43warn(dev->wl, "Out of hardware key memory\n");
e4d6b795
MB		 960 return -ENOSPC;
961 }
962 } else
963 B43_WARN_ON(index > 3);
964
965 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
966 if ((index <= 3) && !b43_new_kidx_api(dev)) {
967 /* Default RX key */
968 B43_WARN_ON(mac_addr);
969 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
970 }
971 keyconf->hw_key_idx = index;
972 dev->key[index].keyconf = keyconf;
973
974 return 0;
975}
976
977static int b43_key_clear(struct b43_wldev *dev, int index)
978{
66d2d089 979 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
e4d6b795
MB		 980 return -EINVAL;
981 do_key_write(dev, index, B43_SEC_ALGO_NONE,
982 NULL, B43_SEC_KEYSIZE, NULL);
983 if ((index <= 3) && !b43_new_kidx_api(dev)) {
984 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
985 NULL, B43_SEC_KEYSIZE, NULL);
986 }
987 dev->key[index].keyconf = NULL;
988
989 return 0;
990}
991
992static void b43_clear_keys(struct b43_wldev *dev)
993{
66d2d089 994 int i, count;
e4d6b795 995
66d2d089
MB		 996 if (b43_new_kidx_api(dev))
997 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
998 else
999 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1000 for (i = 0; i < count; i++)
e4d6b795
MB		 1001 b43_key_clear(dev, i);
1002}
1003
9cf7f247
MB		 1004static void b43_dump_keymemory(struct b43_wldev *dev)
1005{
66d2d089 1006 unsigned int i, index, count, offset, pairwise_keys_start;
9cf7f247
MB		 1007 u8 mac[ETH_ALEN];
1008 u16 algo;
1009 u32 rcmta0;
1010 u16 rcmta1;
1011 u64 hf;
1012 struct b43_key *key;
1013
1014 if (!b43_debug(dev, B43_DBG_KEYS))
1015 return;
1016
1017 hf = b43_hf_read(dev);
1018 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1019 !!(hf & B43_HF_USEDEFKEYS));
66d2d089
MB		 1020 if (b43_new_kidx_api(dev)) {
1021 pairwise_keys_start = B43_NR_GROUP_KEYS;
1022 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1023 } else {
1024 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1025 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1026 }
1027 for (index = 0; index < count; index++) {
9cf7f247
MB		 1028 key = &(dev->key[index]);
1029 printk(KERN_DEBUG "Key slot %02u: %s",
1030 index, (key->keyconf == NULL) ? " " : "*");
1031 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1032 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1033 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1034 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1035 }
1036
1037 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1038 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1039 printk(" Algo: %04X/%02X", algo, key->algorithm);
1040
66d2d089 1041 if (index >= pairwise_keys_start) {
035d0243 1042 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1043 printk(" TKIP: ");
1044 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1045 for (i = 0; i < 14; i += 2) {
1046 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1047 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1048 }
1049 }
9cf7f247 1050 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
66d2d089 1051 ((index - pairwise_keys_start) * 2) + 0);
9cf7f247 1052 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
66d2d089 1053 ((index - pairwise_keys_start) * 2) + 1);
9cf7f247
MB		 1054 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1055 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
e91d8334 1056 printk(" MAC: %pM", mac);
9cf7f247
MB		 1057 } else
1058 printk(" DEFAULT KEY");
1059 printk("\n");
1060 }
1061}
1062
e4d6b795
MB		 1063void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1064{
1065 u32 macctl;
1066 u16 ucstat;
1067 bool hwps;
1068 bool awake;
1069 int i;
1070
1071 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1072 (ps_flags & B43_PS_DISABLED));
1073 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1074
1075 if (ps_flags & B43_PS_ENABLED) {
1076 hwps = 1;
1077 } else if (ps_flags & B43_PS_DISABLED) {
1078 hwps = 0;
1079 } else {
1080 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1081 // and thus is not an AP and we are associated, set bit 25
1082 }
1083 if (ps_flags & B43_PS_AWAKE) {
1084 awake = 1;
1085 } else if (ps_flags & B43_PS_ASLEEP) {
1086 awake = 0;
1087 } else {
1088 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1089 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1090 // successful, set bit26
1091 }
1092
1093/* FIXME: For now we force awake-on and hwps-off */
1094 hwps = 0;
1095 awake = 1;
1096
1097 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1098 if (hwps)
1099 macctl |= B43_MACCTL_HWPS;
1100 else
1101 macctl &= ~B43_MACCTL_HWPS;
1102 if (awake)
1103 macctl |= B43_MACCTL_AWAKE;
1104 else
1105 macctl &= ~B43_MACCTL_AWAKE;
1106 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1107 /* Commit write */
1108 b43_read32(dev, B43_MMIO_MACCTL);
1109 if (awake && dev->dev->id.revision >= 5) {
1110 /* Wait for the microcode to wake up. */
1111 for (i = 0; i < 100; i++) {
1112 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1113 B43_SHM_SH_UCODESTAT);
1114 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1115 break;
1116 udelay(10);
1117 }
1118 }
1119}
1120
e4d6b795
MB		 1121void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1122{
1123 u32 tmslow;
1124 u32 macctl;
1125
1126 flags |= B43_TMSLOW_PHYCLKEN;
1127 flags |= B43_TMSLOW_PHYRESET;
1128 ssb_device_enable(dev->dev, flags);
1129 msleep(2); /* Wait for the PLL to turn on. */
1130
1131 /* Now take the PHY out of Reset again */
1132 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1133 tmslow |= SSB_TMSLOW_FGC;
1134 tmslow &= ~B43_TMSLOW_PHYRESET;
1135 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1136 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1137 msleep(1);
1138 tmslow &= ~SSB_TMSLOW_FGC;
1139 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1140 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1141 msleep(1);
1142
fb11137a
MB		 1143 /* Turn Analog ON, but only if we already know the PHY-type.
1144 * This protects against very early setup where we don't know the
1145 * PHY-type, yet. wireless_core_reset will be called once again later,
1146 * when we know the PHY-type. */
1147 if (dev->phy.ops)
cb24f57f 1148 dev->phy.ops->switch_analog(dev, 1);
e4d6b795
MB		 1149
1150 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1151 macctl &= ~B43_MACCTL_GMODE;
1152 if (flags & B43_TMSLOW_GMODE)
1153 macctl |= B43_MACCTL_GMODE;
1154 macctl |= B43_MACCTL_IHR_ENABLED;
1155 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1156}
1157
1158static void handle_irq_transmit_status(struct b43_wldev *dev)
1159{
1160 u32 v0, v1;
1161 u16 tmp;
1162 struct b43_txstatus stat;
1163
1164 while (1) {
1165 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1166 if (!(v0 & 0x00000001))
1167 break;
1168 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1169
1170 stat.cookie = (v0 >> 16);
1171 stat.seq = (v1 & 0x0000FFFF);
1172 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1173 tmp = (v0 & 0x0000FFFF);
1174 stat.frame_count = ((tmp & 0xF000) >> 12);
1175 stat.rts_count = ((tmp & 0x0F00) >> 8);
1176 stat.supp_reason = ((tmp & 0x001C) >> 2);
1177 stat.pm_indicated = !!(tmp & 0x0080);
1178 stat.intermediate = !!(tmp & 0x0040);
1179 stat.for_ampdu = !!(tmp & 0x0020);
1180 stat.acked = !!(tmp & 0x0002);
1181
1182 b43_handle_txstatus(dev, &stat);
1183 }
1184}
1185
1186static void drain_txstatus_queue(struct b43_wldev *dev)
1187{
1188 u32 dummy;
1189
1190 if (dev->dev->id.revision < 5)
1191 return;
1192 /* Read all entries from the microcode TXstatus FIFO
1193 * and throw them away.
1194 */
1195 while (1) {
1196 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1197 if (!(dummy & 0x00000001))
1198 break;
1199 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1200 }
1201}
1202
1203static u32 b43_jssi_read(struct b43_wldev *dev)
1204{
1205 u32 val = 0;
1206
1207 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1208 val <<= 16;
1209 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1210
1211 return val;
1212}
1213
1214static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1215{
1216 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1217 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1218}
1219
1220static void b43_generate_noise_sample(struct b43_wldev *dev)
1221{
1222 b43_jssi_write(dev, 0x7F7F7F7F);
aa6c7ae2
MB		 1223 b43_write32(dev, B43_MMIO_MACCMD,
1224 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
e4d6b795
MB		 1225}
1226
1227static void b43_calculate_link_quality(struct b43_wldev *dev)
1228{
1229 /* Top half of Link Quality calculation. */
1230
ef1a628d
MB		 1231 if (dev->phy.type != B43_PHYTYPE_G)
1232 return;
e4d6b795
MB		 1233 if (dev->noisecalc.calculation_running)
1234 return;
e4d6b795
MB		 1235 dev->noisecalc.calculation_running = 1;
1236 dev->noisecalc.nr_samples = 0;
1237
1238 b43_generate_noise_sample(dev);
1239}
1240
1241static void handle_irq_noise(struct b43_wldev *dev)
1242{
ef1a628d 1243 struct b43_phy_g *phy = dev->phy.g;
e4d6b795
MB		 1244 u16 tmp;
1245 u8 noise[4];
1246 u8 i, j;
1247 s32 average;
1248
1249 /* Bottom half of Link Quality calculation. */
1250
ef1a628d
MB		 1251 if (dev->phy.type != B43_PHYTYPE_G)
1252 return;
1253
98a3b2fe
MB		 1254 /* Possible race condition: It might be possible that the user
1255 * changed to a different channel in the meantime since we
1256 * started the calculation. We ignore that fact, since it's
1257 * not really that much of a problem. The background noise is
1258 * an estimation only anyway. Slightly wrong results will get damped
1259 * by the averaging of the 8 sample rounds. Additionally the
1260 * value is shortlived. So it will be replaced by the next noise
1261 * calculation round soon. */
1262
e4d6b795 1263 B43_WARN_ON(!dev->noisecalc.calculation_running);
1a09404a 1264 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
e4d6b795
MB		 1265 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1266 noise[2] == 0x7F || noise[3] == 0x7F)
1267 goto generate_new;
1268
1269 /* Get the noise samples. */
1270 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1271 i = dev->noisecalc.nr_samples;
cdbf0846
HH		 1272 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1273 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1274 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1275 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
e4d6b795
MB		 1276 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1277 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1278 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1279 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1280 dev->noisecalc.nr_samples++;
1281 if (dev->noisecalc.nr_samples == 8) {
1282 /* Calculate the Link Quality by the noise samples. */
1283 average = 0;
1284 for (i = 0; i < 8; i++) {
1285 for (j = 0; j < 4; j++)
1286 average += dev->noisecalc.samples[i][j];
1287 }
1288 average /= (8 * 4);
1289 average *= 125;
1290 average += 64;
1291 average /= 128;
1292 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1293 tmp = (tmp / 128) & 0x1F;
1294 if (tmp >= 8)
1295 average += 2;
1296 else
1297 average -= 25;
1298 if (tmp == 8)
1299 average -= 72;
1300 else
1301 average -= 48;
1302
1303 dev->stats.link_noise = average;
e4d6b795
MB		 1304 dev->noisecalc.calculation_running = 0;
1305 return;
1306 }
98a3b2fe 1307generate_new:
e4d6b795
MB		 1308 b43_generate_noise_sample(dev);
1309}
1310
1311static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1312{
05c914fe 1313 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
e4d6b795
MB		 1314 ///TODO: PS TBTT
1315 } else {
1316 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1317 b43_power_saving_ctl_bits(dev, 0);
1318 }
05c914fe 1319 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
aa6c7ae2 1320 dev->dfq_valid = 1;
e4d6b795
MB		 1321}
1322
1323static void handle_irq_atim_end(struct b43_wldev *dev)
1324{
aa6c7ae2
MB		 1325 if (dev->dfq_valid) {
1326 b43_write32(dev, B43_MMIO_MACCMD,
1327 b43_read32(dev, B43_MMIO_MACCMD)
1328 | B43_MACCMD_DFQ_VALID);
1329 dev->dfq_valid = 0;
1330 }
e4d6b795
MB		 1331}
1332
1333static void handle_irq_pmq(struct b43_wldev *dev)
1334{
1335 u32 tmp;
1336
1337 //TODO: AP mode.
1338
1339 while (1) {
1340 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1341 if (!(tmp & 0x00000008))
1342 break;
1343 }
1344 /* 16bit write is odd, but correct. */
1345 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1346}
1347
1348static void b43_write_template_common(struct b43_wldev *dev,
99da185a 1349 const u8 *data, u16 size,
e4d6b795
MB		 1350 u16 ram_offset,
1351 u16 shm_size_offset, u8 rate)
1352{
1353 u32 i, tmp;
1354 struct b43_plcp_hdr4 plcp;
1355
1356 plcp.data = 0;
1357 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1358 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1359 ram_offset += sizeof(u32);
1360 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1361 * So leave the first two bytes of the next write blank.
1362 */
1363 tmp = (u32) (data[0]) << 16;
1364 tmp |= (u32) (data[1]) << 24;
1365 b43_ram_write(dev, ram_offset, tmp);
1366 ram_offset += sizeof(u32);
1367 for (i = 2; i < size; i += sizeof(u32)) {
1368 tmp = (u32) (data[i + 0]);
1369 if (i + 1 < size)
1370 tmp |= (u32) (data[i + 1]) << 8;
1371 if (i + 2 < size)
1372 tmp |= (u32) (data[i + 2]) << 16;
1373 if (i + 3 < size)
1374 tmp |= (u32) (data[i + 3]) << 24;
1375 b43_ram_write(dev, ram_offset + i - 2, tmp);
1376 }
1377 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1378 size + sizeof(struct b43_plcp_hdr6));
1379}
1380
5042c507
MB		 1381/* Check if the use of the antenna that ieee80211 told us to
1382 * use is possible. This will fall back to DEFAULT.
1383 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1384u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1385 u8 antenna_nr)
1386{
1387 u8 antenna_mask;
1388
1389 if (antenna_nr == 0) {
1390 /* Zero means "use default antenna". That's always OK. */
1391 return 0;
1392 }
1393
1394 /* Get the mask of available antennas. */
1395 if (dev->phy.gmode)
1396 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1397 else
1398 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1399
1400 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1401 /* This antenna is not available. Fall back to default. */
1402 return 0;
1403 }
1404
1405 return antenna_nr;
1406}
1407
5042c507
MB		 1408/* Convert a b43 antenna number value to the PHY TX control value. */
1409static u16 b43_antenna_to_phyctl(int antenna)
1410{
1411 switch (antenna) {
1412 case B43_ANTENNA0:
1413 return B43_TXH_PHY_ANT0;
1414 case B43_ANTENNA1:
1415 return B43_TXH_PHY_ANT1;
1416 case B43_ANTENNA2:
1417 return B43_TXH_PHY_ANT2;
1418 case B43_ANTENNA3:
1419 return B43_TXH_PHY_ANT3;
64e368bf
GS		 1420 case B43_ANTENNA_AUTO0:
1421 case B43_ANTENNA_AUTO1:
5042c507
MB		 1422 return B43_TXH_PHY_ANT01AUTO;
1423 }
1424 B43_WARN_ON(1);
1425 return 0;
1426}
1427
e4d6b795
MB		 1428static void b43_write_beacon_template(struct b43_wldev *dev,
1429 u16 ram_offset,
5042c507 1430 u16 shm_size_offset)
e4d6b795 1431{
47f76ca3 1432 unsigned int i, len, variable_len;
e66fee6a
MB		 1433 const struct ieee80211_mgmt *bcn;
1434 const u8 *ie;
1435 bool tim_found = 0;
5042c507
MB		 1436 unsigned int rate;
1437 u16 ctl;
1438 int antenna;
e039fa4a 1439 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
e4d6b795 1440
e66fee6a
MB		 1441 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1442 len = min((size_t) dev->wl->current_beacon->len,
e4d6b795 1443 0x200 - sizeof(struct b43_plcp_hdr6));
e039fa4a 1444 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
e66fee6a
MB		 1445
1446 b43_write_template_common(dev, (const u8 *)bcn,
e4d6b795 1447 len, ram_offset, shm_size_offset, rate);
e66fee6a 1448
5042c507 1449 /* Write the PHY TX control parameters. */
0f4ac38b 1450 antenna = B43_ANTENNA_DEFAULT;
5042c507
MB		 1451 antenna = b43_antenna_to_phyctl(antenna);
1452 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1453 /* We can't send beacons with short preamble. Would get PHY errors. */
1454 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1455 ctl &= ~B43_TXH_PHY_ANT;
1456 ctl &= ~B43_TXH_PHY_ENC;
1457 ctl |= antenna;
1458 if (b43_is_cck_rate(rate))
1459 ctl |= B43_TXH_PHY_ENC_CCK;
1460 else
1461 ctl |= B43_TXH_PHY_ENC_OFDM;
1462 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1463
e66fee6a
MB		 1464 /* Find the position of the TIM and the DTIM_period value
1465 * and write them to SHM. */
1466 ie = bcn->u.beacon.variable;
47f76ca3
MB		 1467 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1468 for (i = 0; i < variable_len - 2; ) {
e66fee6a
MB		 1469 uint8_t ie_id, ie_len;
1470
1471 ie_id = ie[i];
1472 ie_len = ie[i + 1];
1473 if (ie_id == 5) {
1474 u16 tim_position;
1475 u16 dtim_period;
1476 /* This is the TIM Information Element */
1477
1478 /* Check whether the ie_len is in the beacon data range. */
47f76ca3 1479 if (variable_len < ie_len + 2 + i)
e66fee6a
MB		 1480 break;
1481 /* A valid TIM is at least 4 bytes long. */
1482 if (ie_len < 4)
1483 break;
1484 tim_found = 1;
1485
1486 tim_position = sizeof(struct b43_plcp_hdr6);
1487 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1488 tim_position += i;
1489
1490 dtim_period = ie[i + 3];
1491
1492 b43_shm_write16(dev, B43_SHM_SHARED,
1493 B43_SHM_SH_TIMBPOS, tim_position);
1494 b43_shm_write16(dev, B43_SHM_SHARED,
1495 B43_SHM_SH_DTIMPER, dtim_period);
1496 break;
1497 }
1498 i += ie_len + 2;
1499 }
1500 if (!tim_found) {
04dea136
JB		 1501 /*
1502 * If ucode wants to modify TIM do it behind the beacon, this
1503 * will happen, for example, when doing mesh networking.
1504 */
1505 b43_shm_write16(dev, B43_SHM_SHARED,
1506 B43_SHM_SH_TIMBPOS,
1507 len + sizeof(struct b43_plcp_hdr6));
1508 b43_shm_write16(dev, B43_SHM_SHARED,
1509 B43_SHM_SH_DTIMPER, 0);
1510 }
1511 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
e4d6b795
MB		 1512}
1513
6b4bec01
MB		 1514static void b43_upload_beacon0(struct b43_wldev *dev)
1515{
1516 struct b43_wl *wl = dev->wl;
1517
1518 if (wl->beacon0_uploaded)
1519 return;
1520 b43_write_beacon_template(dev, 0x68, 0x18);
6b4bec01
MB		 1521 wl->beacon0_uploaded = 1;
1522}
1523
1524static void b43_upload_beacon1(struct b43_wldev *dev)
1525{
1526 struct b43_wl *wl = dev->wl;
1527
1528 if (wl->beacon1_uploaded)
1529 return;
1530 b43_write_beacon_template(dev, 0x468, 0x1A);
1531 wl->beacon1_uploaded = 1;
1532}
1533
c97a4ccc
MB		 1534static void handle_irq_beacon(struct b43_wldev *dev)
1535{
1536 struct b43_wl *wl = dev->wl;
1537 u32 cmd, beacon0_valid, beacon1_valid;
1538
05c914fe
JB		 1539 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1540 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
c97a4ccc
MB		 1541 return;
1542
1543 /* This is the bottom half of the asynchronous beacon update. */
1544
1545 /* Ignore interrupt in the future. */
13790728 1546 dev->irq_mask &= ~B43_IRQ_BEACON;
c97a4ccc
MB		 1547
1548 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1549 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1550 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1551
1552 /* Schedule interrupt manually, if busy. */
1553 if (beacon0_valid && beacon1_valid) {
1554 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
13790728 1555 dev->irq_mask |= B43_IRQ_BEACON;
c97a4ccc
MB		 1556 return;
1557 }
1558
6b4bec01
MB		 1559 if (unlikely(wl->beacon_templates_virgin)) {
1560 /* We never uploaded a beacon before.
1561 * Upload both templates now, but only mark one valid. */
1562 wl->beacon_templates_virgin = 0;
1563 b43_upload_beacon0(dev);
1564 b43_upload_beacon1(dev);
c97a4ccc
MB		 1565 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1566 cmd |= B43_MACCMD_BEACON0_VALID;
1567 b43_write32(dev, B43_MMIO_MACCMD, cmd);
6b4bec01
MB		 1568 } else {
1569 if (!beacon0_valid) {
1570 b43_upload_beacon0(dev);
1571 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1572 cmd |= B43_MACCMD_BEACON0_VALID;
1573 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1574 } else if (!beacon1_valid) {
1575 b43_upload_beacon1(dev);
1576 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1577 cmd |= B43_MACCMD_BEACON1_VALID;
1578 b43_write32(dev, B43_MMIO_MACCMD, cmd);
c97a4ccc 1579 }
c97a4ccc
MB		 1580 }
1581}
1582
36dbd954
MB		 1583static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1584{
1585 u32 old_irq_mask = dev->irq_mask;
1586
1587 /* update beacon right away or defer to irq */
1588 handle_irq_beacon(dev);
1589 if (old_irq_mask != dev->irq_mask) {
1590 /* The handler updated the IRQ mask. */
1591 B43_WARN_ON(!dev->irq_mask);
1592 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1593 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1594 } else {
1595 /* Device interrupts are currently disabled. That means
1596 * we just ran the hardirq handler and scheduled the
1597 * IRQ thread. The thread will write the IRQ mask when
1598 * it finished, so there's nothing to do here. Writing
1599 * the mask _here_ would incorrectly re-enable IRQs. */
1600 }
1601 }
1602}
1603
a82d9922
MB		 1604static void b43_beacon_update_trigger_work(struct work_struct *work)
1605{
1606 struct b43_wl *wl = container_of(work, struct b43_wl,
1607 beacon_update_trigger);
1608 struct b43_wldev *dev;
1609
1610 mutex_lock(&wl->mutex);
1611 dev = wl->current_dev;
1612 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
3dbba8e2 1613 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
36dbd954
MB		 1614 /* wl->mutex is enough. */
1615 b43_do_beacon_update_trigger_work(dev);
1616 mmiowb();
1617 } else {
1618 spin_lock_irq(&wl->hardirq_lock);
1619 b43_do_beacon_update_trigger_work(dev);
1620 mmiowb();
1621 spin_unlock_irq(&wl->hardirq_lock);
1622 }
a82d9922
MB		 1623 }
1624 mutex_unlock(&wl->mutex);
1625}
1626
d4df6f1a 1627/* Asynchronously update the packet templates in template RAM.
36dbd954 1628 * Locking: Requires wl->mutex to be locked. */
9d139c81 1629static void b43_update_templates(struct b43_wl *wl)
e4d6b795 1630{
9d139c81
JB		 1631 struct sk_buff *beacon;
1632
e66fee6a
MB		 1633 /* This is the top half of the ansynchronous beacon update.
1634 * The bottom half is the beacon IRQ.
1635 * Beacon update must be asynchronous to avoid sending an
1636 * invalid beacon. This can happen for example, if the firmware
1637 * transmits a beacon while we are updating it. */
e4d6b795 1638
9d139c81
JB		 1639 /* We could modify the existing beacon and set the aid bit in
1640 * the TIM field, but that would probably require resizing and
1641 * moving of data within the beacon template.
1642 * Simply request a new beacon and let mac80211 do the hard work. */
1643 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1644 if (unlikely(!beacon))
1645 return;
1646
e66fee6a
MB		 1647 if (wl->current_beacon)
1648 dev_kfree_skb_any(wl->current_beacon);
1649 wl->current_beacon = beacon;
1650 wl->beacon0_uploaded = 0;
1651 wl->beacon1_uploaded = 0;
42935eca 1652 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
e4d6b795
MB		 1653}
1654
e4d6b795
MB		 1655static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1656{
1657 b43_time_lock(dev);
1658 if (dev->dev->id.revision >= 3) {
a82d9922
MB		 1659 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1660 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
e4d6b795
MB		 1661 } else {
1662 b43_write16(dev, 0x606, (beacon_int >> 6));
1663 b43_write16(dev, 0x610, beacon_int);
1664 }
1665 b43_time_unlock(dev);
a82d9922 1666 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
e4d6b795
MB		 1667}
1668
afa83e23
MB		 1669static void b43_handle_firmware_panic(struct b43_wldev *dev)
1670{
1671 u16 reason;
1672
1673 /* Read the register that contains the reason code for the panic. */
1674 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1675 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1676
1677 switch (reason) {
1678 default:
1679 b43dbg(dev->wl, "The panic reason is unknown.\n");
1680 /* fallthrough */
1681 case B43_FWPANIC_DIE:
1682 /* Do not restart the controller or firmware.
1683 * The device is nonfunctional from now on.
1684 * Restarting would result in this panic to trigger again,
1685 * so we avoid that recursion. */
1686 break;
1687 case B43_FWPANIC_RESTART:
1688 b43_controller_restart(dev, "Microcode panic");
1689 break;
1690 }
1691}
1692
e4d6b795
MB		 1693static void handle_irq_ucode_debug(struct b43_wldev *dev)
1694{
e48b0eeb 1695 unsigned int i, cnt;
53c06856 1696 u16 reason, marker_id, marker_line;
e48b0eeb
MB		 1697 __le16 *buf;
1698
1699 /* The proprietary firmware doesn't have this IRQ. */
1700 if (!dev->fw.opensource)
1701 return;
1702
afa83e23
MB		 1703 /* Read the register that contains the reason code for this IRQ. */
1704 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1705
e48b0eeb
MB		 1706 switch (reason) {
1707 case B43_DEBUGIRQ_PANIC:
afa83e23 1708 b43_handle_firmware_panic(dev);
e48b0eeb
MB		 1709 break;
1710 case B43_DEBUGIRQ_DUMP_SHM:
1711 if (!B43_DEBUG)
1712 break; /* Only with driver debugging enabled. */
1713 buf = kmalloc(4096, GFP_ATOMIC);
1714 if (!buf) {
1715 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1716 goto out;
1717 }
1718 for (i = 0; i < 4096; i += 2) {
1719 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1720 buf[i / 2] = cpu_to_le16(tmp);
1721 }
1722 b43info(dev->wl, "Shared memory dump:\n");
1723 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1724 16, 2, buf, 4096, 1);
1725 kfree(buf);
1726 break;
1727 case B43_DEBUGIRQ_DUMP_REGS:
1728 if (!B43_DEBUG)
1729 break; /* Only with driver debugging enabled. */
1730 b43info(dev->wl, "Microcode register dump:\n");
1731 for (i = 0, cnt = 0; i < 64; i++) {
1732 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1733 if (cnt == 0)
1734 printk(KERN_INFO);
1735 printk("r%02u: 0x%04X ", i, tmp);
1736 cnt++;
1737 if (cnt == 6) {
1738 printk("\n");
1739 cnt = 0;
1740 }
1741 }
1742 printk("\n");
1743 break;
53c06856
MB		 1744 case B43_DEBUGIRQ_MARKER:
1745 if (!B43_DEBUG)
1746 break; /* Only with driver debugging enabled. */
1747 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1748 B43_MARKER_ID_REG);
1749 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1750 B43_MARKER_LINE_REG);
1751 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1752 "at line number %u\n",
1753 marker_id, marker_line);
1754 break;
e48b0eeb
MB		 1755 default:
1756 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1757 reason);
1758 }
1759out:
afa83e23
MB		 1760 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1761 b43_shm_write16(dev, B43_SHM_SCRATCH,
1762 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
e4d6b795
MB		 1763}
1764
36dbd954 1765static void b43_do_interrupt_thread(struct b43_wldev *dev)
e4d6b795
MB		 1766{
1767 u32 reason;
1768 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1769 u32 merged_dma_reason = 0;
21954c36 1770 int i;
e4d6b795 1771
36dbd954
MB		 1772 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1773 return;
e4d6b795
MB		 1774
1775 reason = dev->irq_reason;
1776 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1777 dma_reason[i] = dev->dma_reason[i];
1778 merged_dma_reason |= dma_reason[i];
1779 }
1780
1781 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1782 b43err(dev->wl, "MAC transmission error\n");
1783
00e0b8cb 1784 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
e4d6b795 1785 b43err(dev->wl, "PHY transmission error\n");
00e0b8cb
SB		 1786 rmb();
1787 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1788 atomic_set(&dev->phy.txerr_cnt,
1789 B43_PHY_TX_BADNESS_LIMIT);
1790 b43err(dev->wl, "Too many PHY TX errors, "
1791 "restarting the controller\n");
1792 b43_controller_restart(dev, "PHY TX errors");
1793 }
1794 }
e4d6b795
MB		 1795
1796 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1797 B43_DMAIRQ_NONFATALMASK))) {
1798 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1799 b43err(dev->wl, "Fatal DMA error: "
1800 "0x%08X, 0x%08X, 0x%08X, "
1801 "0x%08X, 0x%08X, 0x%08X\n",
1802 dma_reason[0], dma_reason[1],
1803 dma_reason[2], dma_reason[3],
1804 dma_reason[4], dma_reason[5]);
214ac9a4
LF		 1805 b43err(dev->wl, "This device does not support DMA "
1806 "on your system. Please use PIO instead.\n");
b02914af
LF		 1807 b43err(dev->wl, "Unload the b43 module and reload "
1808 "with 'pio=1'\n");
e4d6b795
MB		 1809 return;
1810 }
1811 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1812 b43err(dev->wl, "DMA error: "
1813 "0x%08X, 0x%08X, 0x%08X, "
1814 "0x%08X, 0x%08X, 0x%08X\n",
1815 dma_reason[0], dma_reason[1],
1816 dma_reason[2], dma_reason[3],
1817 dma_reason[4], dma_reason[5]);
1818 }
1819 }
1820
1821 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1822 handle_irq_ucode_debug(dev);
1823 if (reason & B43_IRQ_TBTT_INDI)
1824 handle_irq_tbtt_indication(dev);
1825 if (reason & B43_IRQ_ATIM_END)
1826 handle_irq_atim_end(dev);
1827 if (reason & B43_IRQ_BEACON)
1828 handle_irq_beacon(dev);
1829 if (reason & B43_IRQ_PMQ)
1830 handle_irq_pmq(dev);
21954c36
MB		 1831 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1832 ;/* TODO */
1833 if (reason & B43_IRQ_NOISESAMPLE_OK)
e4d6b795
MB		 1834 handle_irq_noise(dev);
1835
1836 /* Check the DMA reason registers for received data. */
5100d5ac
MB		 1837 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1838 if (b43_using_pio_transfers(dev))
1839 b43_pio_rx(dev->pio.rx_queue);
1840 else
1841 b43_dma_rx(dev->dma.rx_ring);
1842 }
e4d6b795
MB		 1843 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1844 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
b27faf8e 1845 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
e4d6b795
MB		 1846 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1847 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1848
21954c36 1849 if (reason & B43_IRQ_TX_OK)
e4d6b795 1850 handle_irq_transmit_status(dev);
e4d6b795 1851
36dbd954 1852 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
13790728 1853 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
990b86f4
MB		 1854
1855#if B43_DEBUG
1856 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
1857 dev->irq_count++;
1858 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
1859 if (reason & (1 << i))
1860 dev->irq_bit_count[i]++;
1861 }
1862 }
1863#endif
e4d6b795
MB		 1864}
1865
36dbd954
MB		 1866/* Interrupt thread handler. Handles device interrupts in thread context. */
1867static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
e4d6b795 1868{
36dbd954 1869 struct b43_wldev *dev = dev_id;
e4d6b795 1870
36dbd954
MB		 1871 mutex_lock(&dev->wl->mutex);
1872 b43_do_interrupt_thread(dev);
1873 mmiowb();
1874 mutex_unlock(&dev->wl->mutex);
1875
1876 return IRQ_HANDLED;
e4d6b795
MB		 1877}
1878
36dbd954 1879static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
e4d6b795 1880{
e4d6b795
MB		 1881 u32 reason;
1882
36dbd954
MB		 1883 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1884 * On SDIO, this runs under wl->mutex. */
e4d6b795 1885
e4d6b795
MB		 1886 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1887 if (reason == 0xffffffff) /* shared IRQ */
36dbd954 1888 return IRQ_NONE;
13790728 1889 reason &= dev->irq_mask;
e4d6b795 1890 if (!reason)
36dbd954 1891 return IRQ_HANDLED;
e4d6b795
MB		 1892
1893 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1894 & 0x0001DC00;
1895 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1896 & 0x0000DC00;
1897 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1898 & 0x0000DC00;
1899 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1900 & 0x0001DC00;
1901 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1902 & 0x0000DC00;
13790728 1903/* Unused ring
e4d6b795
MB		 1904 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1905 & 0x0000DC00;
13790728 1906*/
e4d6b795 1907
36dbd954
MB		 1908 /* ACK the interrupt. */
1909 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1910 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1911 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1912 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1913 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1914 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1915/* Unused ring
1916 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1917*/
1918
1919 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
13790728 1920 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
36dbd954 1921 /* Save the reason bitmasks for the IRQ thread handler. */
e4d6b795 1922 dev->irq_reason = reason;
36dbd954
MB		 1923
1924 return IRQ_WAKE_THREAD;
1925}
1926
1927/* Interrupt handler top-half. This runs with interrupts disabled. */
1928static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1929{
1930 struct b43_wldev *dev = dev_id;
1931 irqreturn_t ret;
1932
1933 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1934 return IRQ_NONE;
1935
1936 spin_lock(&dev->wl->hardirq_lock);
1937 ret = b43_do_interrupt(dev);
e4d6b795 1938 mmiowb();
36dbd954 1939 spin_unlock(&dev->wl->hardirq_lock);
e4d6b795
MB		 1940
1941 return ret;
1942}
1943
3dbba8e2
AH		 1944/* SDIO interrupt handler. This runs in process context. */
1945static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
1946{
1947 struct b43_wl *wl = dev->wl;
3dbba8e2
AH		 1948 irqreturn_t ret;
1949
3dbba8e2 1950 mutex_lock(&wl->mutex);
3dbba8e2
AH		 1951
1952 ret = b43_do_interrupt(dev);
1953 if (ret == IRQ_WAKE_THREAD)
1954 b43_do_interrupt_thread(dev);
1955
3dbba8e2
AH		 1956 mutex_unlock(&wl->mutex);
1957}
1958
1a9f5093 1959void b43_do_release_fw(struct b43_firmware_file *fw)
61cb5dd6
MB		 1960{
1961 release_firmware(fw->data);
1962 fw->data = NULL;
1963 fw->filename = NULL;
1964}
1965
e4d6b795
MB		 1966static void b43_release_firmware(struct b43_wldev *dev)
1967{
1a9f5093
MB		 1968 b43_do_release_fw(&dev->fw.ucode);
1969 b43_do_release_fw(&dev->fw.pcm);
1970 b43_do_release_fw(&dev->fw.initvals);
1971 b43_do_release_fw(&dev->fw.initvals_band);
e4d6b795
MB		 1972}
1973
eb189d8b 1974static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
e4d6b795 1975{
fc68ed4f
HE		 1976 const char text[] =
1977 "You must go to " \
1978 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1979 "and download the correct firmware for this driver version. " \
1980 "Please carefully read all instructions on this website.\n";
eb189d8b 1981
eb189d8b
MB		 1982 if (error)
1983 b43err(wl, text);
1984 else
1985 b43warn(wl, text);
e4d6b795
MB		 1986}
1987
1a9f5093
MB		 1988int b43_do_request_fw(struct b43_request_fw_context *ctx,
1989 const char *name,
1990 struct b43_firmware_file *fw)
e4d6b795 1991{
61cb5dd6 1992 const struct firmware *blob;
e4d6b795
MB		 1993 struct b43_fw_header *hdr;
1994 u32 size;
1995 int err;
1996
61cb5dd6
MB		 1997 if (!name) {
1998 /* Don't fetch anything. Free possibly cached firmware. */
1a9f5093
MB		 1999 /* FIXME: We should probably keep it anyway, to save some headache
2000 * on suspend/resume with multiband devices. */
2001 b43_do_release_fw(fw);
e4d6b795 2002 return 0;
61cb5dd6
MB		 2003 }
2004 if (fw->filename) {
1a9f5093
MB		 2005 if ((fw->type == ctx->req_type) &&
2006 (strcmp(fw->filename, name) == 0))
61cb5dd6
MB		 2007 return 0; /* Already have this fw. */
2008 /* Free the cached firmware first. */
1a9f5093
MB		 2009 /* FIXME: We should probably do this later after we successfully
2010 * got the new fw. This could reduce headache with multiband devices.
2011 * We could also redesign this to cache the firmware for all possible
2012 * bands all the time. */
2013 b43_do_release_fw(fw);
61cb5dd6 2014 }
e4d6b795 2015
1a9f5093
MB		 2016 switch (ctx->req_type) {
2017 case B43_FWTYPE_PROPRIETARY:
2018 snprintf(ctx->fwname, sizeof(ctx->fwname),
2019 "b43%s/%s.fw",
2020 modparam_fwpostfix, name);
2021 break;
2022 case B43_FWTYPE_OPENSOURCE:
2023 snprintf(ctx->fwname, sizeof(ctx->fwname),
2024 "b43-open%s/%s.fw",
2025 modparam_fwpostfix, name);
2026 break;
2027 default:
2028 B43_WARN_ON(1);
2029 return -ENOSYS;
2030 }
2031 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
68217832 2032 if (err == -ENOENT) {
1a9f5093
MB		 2033 snprintf(ctx->errors[ctx->req_type],
2034 sizeof(ctx->errors[ctx->req_type]),
2035 "Firmware file \"%s\" not found\n", ctx->fwname);
68217832
MB		 2036 return err;
2037 } else if (err) {
1a9f5093
MB		 2038 snprintf(ctx->errors[ctx->req_type],
2039 sizeof(ctx->errors[ctx->req_type]),
2040 "Firmware file \"%s\" request failed (err=%d)\n",
2041 ctx->fwname, err);
e4d6b795
MB		 2042 return err;
2043 }
61cb5dd6 2044 if (blob->size < sizeof(struct b43_fw_header))
e4d6b795 2045 goto err_format;
61cb5dd6 2046 hdr = (struct b43_fw_header *)(blob->data);
e4d6b795
MB		 2047 switch (hdr->type) {
2048 case B43_FW_TYPE_UCODE:
2049 case B43_FW_TYPE_PCM:
2050 size = be32_to_cpu(hdr->size);
61cb5dd6 2051 if (size != blob->size - sizeof(struct b43_fw_header))
e4d6b795
MB		 2052 goto err_format;
2053 /* fallthrough */
2054 case B43_FW_TYPE_IV:
2055 if (hdr->ver != 1)
2056 goto err_format;
2057 break;
2058 default:
2059 goto err_format;
2060 }
2061
61cb5dd6
MB		 2062 fw->data = blob;
2063 fw->filename = name;
1a9f5093 2064 fw->type = ctx->req_type;
61cb5dd6
MB		 2065
2066 return 0;
e4d6b795
MB		 2067
2068err_format:
1a9f5093
MB		 2069 snprintf(ctx->errors[ctx->req_type],
2070 sizeof(ctx->errors[ctx->req_type]),
2071 "Firmware file \"%s\" format error.\n", ctx->fwname);
61cb5dd6
MB		 2072 release_firmware(blob);
2073
e4d6b795
MB		 2074 return -EPROTO;
2075}
2076
1a9f5093 2077static int b43_try_request_fw(struct b43_request_fw_context *ctx)
e4d6b795 2078{
1a9f5093
MB		 2079 struct b43_wldev *dev = ctx->dev;
2080 struct b43_firmware *fw = &ctx->dev->fw;
2081 const u8 rev = ctx->dev->dev->id.revision;
e4d6b795
MB		 2082 const char *filename;
2083 u32 tmshigh;
2084 int err;
2085
61cb5dd6 2086 /* Get microcode */
e4d6b795 2087 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
61cb5dd6
MB		 2088 if ((rev >= 5) && (rev <= 10))
2089 filename = "ucode5";
2090 else if ((rev >= 11) && (rev <= 12))
2091 filename = "ucode11";
759b973b 2092 else if (rev == 13)
61cb5dd6 2093 filename = "ucode13";
759b973b
GS		 2094 else if (rev == 14)
2095 filename = "ucode14";
2096 else if (rev >= 15)
2097 filename = "ucode15";
61cb5dd6
MB		 2098 else
2099 goto err_no_ucode;
1a9f5093 2100 err = b43_do_request_fw(ctx, filename, &fw->ucode);
61cb5dd6
MB		 2101 if (err)
2102 goto err_load;
2103
2104 /* Get PCM code */
2105 if ((rev >= 5) && (rev <= 10))
2106 filename = "pcm5";
2107 else if (rev >= 11)
2108 filename = NULL;
2109 else
2110 goto err_no_pcm;
68217832 2111 fw->pcm_request_failed = 0;
1a9f5093 2112 err = b43_do_request_fw(ctx, filename, &fw->pcm);
68217832
MB		 2113 if (err == -ENOENT) {
2114 /* We did not find a PCM file? Not fatal, but
2115 * core rev <= 10 must do without hwcrypto then. */
2116 fw->pcm_request_failed = 1;
2117 } else if (err)
61cb5dd6
MB		 2118 goto err_load;
2119
2120 /* Get initvals */
2121 switch (dev->phy.type) {
2122 case B43_PHYTYPE_A:
2123 if ((rev >= 5) && (rev <= 10)) {
2124 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2125 filename = "a0g1initvals5";
2126 else
2127 filename = "a0g0initvals5";
2128 } else
2129 goto err_no_initvals;
2130 break;
2131 case B43_PHYTYPE_G:
e4d6b795 2132 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2133 filename = "b0g0initvals5";
e4d6b795 2134 else if (rev >= 13)
e9304882 2135 filename = "b0g0initvals13";
e4d6b795 2136 else
61cb5dd6
MB		 2137 goto err_no_initvals;
2138 break;
2139 case B43_PHYTYPE_N:
2140 if ((rev >= 11) && (rev <= 12))
2141 filename = "n0initvals11";
2142 else
2143 goto err_no_initvals;
2144 break;
759b973b
GS		 2145 case B43_PHYTYPE_LP:
2146 if (rev == 13)
2147 filename = "lp0initvals13";
2148 else if (rev == 14)
2149 filename = "lp0initvals14";
2150 else if (rev >= 15)
2151 filename = "lp0initvals15";
2152 else
2153 goto err_no_initvals;
2154 break;
61cb5dd6
MB		 2155 default:
2156 goto err_no_initvals;
e4d6b795 2157 }
1a9f5093 2158 err = b43_do_request_fw(ctx, filename, &fw->initvals);
61cb5dd6
MB		 2159 if (err)
2160 goto err_load;
2161
2162 /* Get bandswitch initvals */
2163 switch (dev->phy.type) {
2164 case B43_PHYTYPE_A:
2165 if ((rev >= 5) && (rev <= 10)) {
2166 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2167 filename = "a0g1bsinitvals5";
2168 else
2169 filename = "a0g0bsinitvals5";
2170 } else if (rev >= 11)
2171 filename = NULL;
2172 else
2173 goto err_no_initvals;
2174 break;
2175 case B43_PHYTYPE_G:
e4d6b795 2176 if ((rev >= 5) && (rev <= 10))
61cb5dd6 2177 filename = "b0g0bsinitvals5";
e4d6b795
MB		 2178 else if (rev >= 11)
2179 filename = NULL;
2180 else
e4d6b795 2181 goto err_no_initvals;
61cb5dd6
MB		 2182 break;
2183 case B43_PHYTYPE_N:
2184 if ((rev >= 11) && (rev <= 12))
2185 filename = "n0bsinitvals11";
2186 else
e4d6b795 2187 goto err_no_initvals;
61cb5dd6 2188 break;
759b973b
GS		 2189 case B43_PHYTYPE_LP:
2190 if (rev == 13)
2191 filename = "lp0bsinitvals13";
2192 else if (rev == 14)
2193 filename = "lp0bsinitvals14";
2194 else if (rev >= 15)
2195 filename = "lp0bsinitvals15";
2196 else
2197 goto err_no_initvals;
2198 break;
61cb5dd6
MB		 2199 default:
2200 goto err_no_initvals;
e4d6b795 2201 }
1a9f5093 2202 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
61cb5dd6
MB		 2203 if (err)
2204 goto err_load;
e4d6b795
MB		 2205
2206 return 0;
2207
e4d6b795 2208err_no_ucode:
1a9f5093
MB		 2209 err = ctx->fatal_failure = -EOPNOTSUPP;
2210 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2211 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2212 goto error;
2213
2214err_no_pcm:
1a9f5093
MB		 2215 err = ctx->fatal_failure = -EOPNOTSUPP;
2216 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2217 "is required for your device (wl-core rev %u)\n", rev);
e4d6b795
MB		 2218 goto error;
2219
2220err_no_initvals:
1a9f5093
MB		 2221 err = ctx->fatal_failure = -EOPNOTSUPP;
2222 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2223 "is required for your device (wl-core rev %u)\n", rev);
2224 goto error;
2225
2226err_load:
2227 /* We failed to load this firmware image. The error message
2228 * already is in ctx->errors. Return and let our caller decide
2229 * what to do. */
e4d6b795
MB		 2230 goto error;
2231
2232error:
2233 b43_release_firmware(dev);
2234 return err;
2235}
2236
1a9f5093
MB		 2237static int b43_request_firmware(struct b43_wldev *dev)
2238{
2239 struct b43_request_fw_context *ctx;
2240 unsigned int i;
2241 int err;
2242 const char *errmsg;
2243
2244 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2245 if (!ctx)
2246 return -ENOMEM;
2247 ctx->dev = dev;
2248
2249 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2250 err = b43_try_request_fw(ctx);
2251 if (!err)
2252 goto out; /* Successfully loaded it. */
2253 err = ctx->fatal_failure;
2254 if (err)
2255 goto out;
2256
2257 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2258 err = b43_try_request_fw(ctx);
2259 if (!err)
2260 goto out; /* Successfully loaded it. */
2261 err = ctx->fatal_failure;
2262 if (err)
2263 goto out;
2264
2265 /* Could not find a usable firmware. Print the errors. */
2266 for (i = 0; i < B43_NR_FWTYPES; i++) {
2267 errmsg = ctx->errors[i];
2268 if (strlen(errmsg))
2269 b43err(dev->wl, errmsg);
2270 }
2271 b43_print_fw_helptext(dev->wl, 1);
2272 err = -ENOENT;
2273
2274out:
2275 kfree(ctx);
2276 return err;
2277}
2278
e4d6b795
MB		 2279static int b43_upload_microcode(struct b43_wldev *dev)
2280{
2281 const size_t hdr_len = sizeof(struct b43_fw_header);
2282 const __be32 *data;
2283 unsigned int i, len;
2284 u16 fwrev, fwpatch, fwdate, fwtime;
1f7d87b0 2285 u32 tmp, macctl;
e4d6b795
MB		 2286 int err = 0;
2287
1f7d87b0
MB		 2288 /* Jump the microcode PSM to offset 0 */
2289 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2290 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2291 macctl |= B43_MACCTL_PSM_JMP0;
2292 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2293 /* Zero out all microcode PSM registers and shared memory. */
2294 for (i = 0; i < 64; i++)
2295 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2296 for (i = 0; i < 4096; i += 2)
2297 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2298
e4d6b795 2299 /* Upload Microcode. */
61cb5dd6
MB		 2300 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2301 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2302 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2303 for (i = 0; i < len; i++) {
2304 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2305 udelay(10);
2306 }
2307
61cb5dd6 2308 if (dev->fw.pcm.data) {
e4d6b795 2309 /* Upload PCM data. */
61cb5dd6
MB		 2310 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2311 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
e4d6b795
MB		 2312 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2313 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2314 /* No need for autoinc bit in SHM_HW */
2315 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2316 for (i = 0; i < len; i++) {
2317 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2318 udelay(10);
2319 }
2320 }
2321
2322 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1f7d87b0
MB		 2323
2324 /* Start the microcode PSM */
2325 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2326 macctl &= ~B43_MACCTL_PSM_JMP0;
2327 macctl |= B43_MACCTL_PSM_RUN;
2328 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2329
2330 /* Wait for the microcode to load and respond */
2331 i = 0;
2332 while (1) {
2333 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2334 if (tmp == B43_IRQ_MAC_SUSPENDED)
2335 break;
2336 i++;
1f7d87b0 2337 if (i >= 20) {
e4d6b795 2338 b43err(dev->wl, "Microcode not responding\n");
eb189d8b 2339 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2340 err = -ENODEV;
1f7d87b0
MB		 2341 goto error;
2342 }
e175e996 2343 msleep(50);
e4d6b795
MB		 2344 }
2345 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2346
2347 /* Get and check the revisions. */
2348 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2349 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2350 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2351 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2352
2353 if (fwrev <= 0x128) {
2354 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2355 "binary drivers older than version 4.x is unsupported. "
2356 "You must upgrade your firmware files.\n");
eb189d8b 2357 b43_print_fw_helptext(dev->wl, 1);
e4d6b795 2358 err = -EOPNOTSUPP;
1f7d87b0 2359 goto error;
e4d6b795 2360 }
e4d6b795
MB		 2361 dev->fw.rev = fwrev;
2362 dev->fw.patch = fwpatch;
e48b0eeb
MB		 2363 dev->fw.opensource = (fwdate == 0xFFFF);
2364
403a3a13
MB		 2365 /* Default to use-all-queues. */
2366 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2367 dev->qos_enabled = !!modparam_qos;
2368 /* Default to firmware/hardware crypto acceleration. */
2369 dev->hwcrypto_enabled = 1;
2370
e48b0eeb 2371 if (dev->fw.opensource) {
403a3a13
MB		 2372 u16 fwcapa;
2373
e48b0eeb
MB		 2374 /* Patchlevel info is encoded in the "time" field. */
2375 dev->fw.patch = fwtime;
403a3a13
MB		 2376 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2377 dev->fw.rev, dev->fw.patch);
2378
2379 fwcapa = b43_fwcapa_read(dev);
2380 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2381 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2382 /* Disable hardware crypto and fall back to software crypto. */
2383 dev->hwcrypto_enabled = 0;
2384 }
2385 if (!(fwcapa & B43_FWCAPA_QOS)) {
2386 b43info(dev->wl, "QoS not supported by firmware\n");
2387 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2388 * ieee80211_unregister to make sure the networking core can
2389 * properly free possible resources. */
2390 dev->wl->hw->queues = 1;
2391 dev->qos_enabled = 0;
2392 }
e48b0eeb
MB		 2393 } else {
2394 b43info(dev->wl, "Loading firmware version %u.%u "
2395 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2396 fwrev, fwpatch,
2397 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2398 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
68217832
MB		 2399 if (dev->fw.pcm_request_failed) {
2400 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2401 "Hardware accelerated cryptography is disabled.\n");
2402 b43_print_fw_helptext(dev->wl, 0);
2403 }
e48b0eeb 2404 }
e4d6b795 2405
eb189d8b 2406 if (b43_is_old_txhdr_format(dev)) {
c557289c
MB		 2407 /* We're over the deadline, but we keep support for old fw
2408 * until it turns out to be in major conflict with something new. */
eb189d8b 2409 b43warn(dev->wl, "You are using an old firmware image. "
c557289c
MB		 2410 "Support for old firmware will be removed soon "
2411 "(official deadline was July 2008).\n");
eb189d8b
MB		 2412 b43_print_fw_helptext(dev->wl, 0);
2413 }
2414
1f7d87b0
MB		 2415 return 0;
2416
2417error:
2418 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2419 macctl &= ~B43_MACCTL_PSM_RUN;
2420 macctl |= B43_MACCTL_PSM_JMP0;
2421 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2422
e4d6b795
MB		 2423 return err;
2424}
2425
2426static int b43_write_initvals(struct b43_wldev *dev,
2427 const struct b43_iv *ivals,
2428 size_t count,
2429 size_t array_size)
2430{
2431 const struct b43_iv *iv;
2432 u16 offset;
2433 size_t i;
2434 bool bit32;
2435
2436 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2437 iv = ivals;
2438 for (i = 0; i < count; i++) {
2439 if (array_size < sizeof(iv->offset_size))
2440 goto err_format;
2441 array_size -= sizeof(iv->offset_size);
2442 offset = be16_to_cpu(iv->offset_size);
2443 bit32 = !!(offset & B43_IV_32BIT);
2444 offset &= B43_IV_OFFSET_MASK;
2445 if (offset >= 0x1000)
2446 goto err_format;
2447 if (bit32) {
2448 u32 value;
2449
2450 if (array_size < sizeof(iv->data.d32))
2451 goto err_format;
2452 array_size -= sizeof(iv->data.d32);
2453
533dd1b0 2454 value = get_unaligned_be32(&iv->data.d32);
e4d6b795
MB		 2455 b43_write32(dev, offset, value);
2456
2457 iv = (const struct b43_iv *)((const uint8_t *)iv +
2458 sizeof(__be16) +
2459 sizeof(__be32));
2460 } else {
2461 u16 value;
2462
2463 if (array_size < sizeof(iv->data.d16))
2464 goto err_format;
2465 array_size -= sizeof(iv->data.d16);
2466
2467 value = be16_to_cpu(iv->data.d16);
2468 b43_write16(dev, offset, value);
2469
2470 iv = (const struct b43_iv *)((const uint8_t *)iv +
2471 sizeof(__be16) +
2472 sizeof(__be16));
2473 }
2474 }
2475 if (array_size)
2476 goto err_format;
2477
2478 return 0;
2479
2480err_format:
2481 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
eb189d8b 2482 b43_print_fw_helptext(dev->wl, 1);
e4d6b795
MB		 2483
2484 return -EPROTO;
2485}
2486
2487static int b43_upload_initvals(struct b43_wldev *dev)
2488{
2489 const size_t hdr_len = sizeof(struct b43_fw_header);
2490 const struct b43_fw_header *hdr;
2491 struct b43_firmware *fw = &dev->fw;
2492 const struct b43_iv *ivals;
2493 size_t count;
2494 int err;
2495
61cb5dd6
MB		 2496 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2497 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
e4d6b795
MB		 2498 count = be32_to_cpu(hdr->size);
2499 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2500 fw->initvals.data->size - hdr_len);
e4d6b795
MB		 2501 if (err)
2502 goto out;
61cb5dd6
MB		 2503 if (fw->initvals_band.data) {
2504 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2505 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
e4d6b795
MB		 2506 count = be32_to_cpu(hdr->size);
2507 err = b43_write_initvals(dev, ivals, count,
61cb5dd6 2508 fw->initvals_band.data->size - hdr_len);
e4d6b795
MB		 2509 if (err)
2510 goto out;
2511 }
2512out:
2513
2514 return err;
2515}
2516
2517/* Initialize the GPIOs
2518 * http://bcm-specs.sipsolutions.net/GPIO
2519 */
2520static int b43_gpio_init(struct b43_wldev *dev)
2521{
2522 struct ssb_bus *bus = dev->dev->bus;
2523 struct ssb_device *gpiodev, *pcidev = NULL;
2524 u32 mask, set;
2525
2526 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2527 & ~B43_MACCTL_GPOUTSMSK);
2528
e4d6b795
MB		 2529 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2530 | 0x000F);
2531
2532 mask = 0x0000001F;
2533 set = 0x0000000F;
2534 if (dev->dev->bus->chip_id == 0x4301) {
2535 mask |= 0x0060;
2536 set |= 0x0060;
2537 }
2538 if (0 /* FIXME: conditional unknown */ ) {
2539 b43_write16(dev, B43_MMIO_GPIO_MASK,
2540 b43_read16(dev, B43_MMIO_GPIO_MASK)
2541 | 0x0100);
2542 mask |= 0x0180;
2543 set |= 0x0180;
2544 }
95de2841 2545 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
e4d6b795
MB		 2546 b43_write16(dev, B43_MMIO_GPIO_MASK,
2547 b43_read16(dev, B43_MMIO_GPIO_MASK)
2548 | 0x0200);
2549 mask |= 0x0200;
2550 set |= 0x0200;
2551 }
2552 if (dev->dev->id.revision >= 2)
2553 mask |= 0x0010; /* FIXME: This is redundant. */
2554
2555#ifdef CONFIG_SSB_DRIVER_PCICORE
2556 pcidev = bus->pcicore.dev;
2557#endif
2558 gpiodev = bus->chipco.dev ? : pcidev;
2559 if (!gpiodev)
2560 return 0;
2561 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2562 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2563 & mask) | set);
2564
2565 return 0;
2566}
2567
2568/* Turn off all GPIO stuff. Call this on module unload, for example. */
2569static void b43_gpio_cleanup(struct b43_wldev *dev)
2570{
2571 struct ssb_bus *bus = dev->dev->bus;
2572 struct ssb_device *gpiodev, *pcidev = NULL;
2573
2574#ifdef CONFIG_SSB_DRIVER_PCICORE
2575 pcidev = bus->pcicore.dev;
2576#endif
2577 gpiodev = bus->chipco.dev ? : pcidev;
2578 if (!gpiodev)
2579 return;
2580 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2581}
2582
2583/* http://bcm-specs.sipsolutions.net/EnableMac */
f5eda47f 2584void b43_mac_enable(struct b43_wldev *dev)
e4d6b795 2585{
923fd703
MB		 2586 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2587 u16 fwstate;
2588
2589 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2590 B43_SHM_SH_UCODESTAT);
2591 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2592 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2593 b43err(dev->wl, "b43_mac_enable(): The firmware "
2594 "should be suspended, but current state is %u\n",
2595 fwstate);
2596 }
2597 }
2598
e4d6b795
MB		 2599 dev->mac_suspended--;
2600 B43_WARN_ON(dev->mac_suspended < 0);
2601 if (dev->mac_suspended == 0) {
2602 b43_write32(dev, B43_MMIO_MACCTL,
2603 b43_read32(dev, B43_MMIO_MACCTL)
2604 | B43_MACCTL_ENABLED);
2605 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2606 B43_IRQ_MAC_SUSPENDED);
2607 /* Commit writes */
2608 b43_read32(dev, B43_MMIO_MACCTL);
2609 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2610 b43_power_saving_ctl_bits(dev, 0);
2611 }
2612}
2613
2614/* http://bcm-specs.sipsolutions.net/SuspendMAC */
f5eda47f 2615void b43_mac_suspend(struct b43_wldev *dev)
e4d6b795
MB		 2616{
2617 int i;
2618 u32 tmp;
2619
05b64b36 2620 might_sleep();
e4d6b795 2621 B43_WARN_ON(dev->mac_suspended < 0);
05b64b36 2622
e4d6b795
MB		 2623 if (dev->mac_suspended == 0) {
2624 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2625 b43_write32(dev, B43_MMIO_MACCTL,
2626 b43_read32(dev, B43_MMIO_MACCTL)
2627 & ~B43_MACCTL_ENABLED);
2628 /* force pci to flush the write */
2629 b43_read32(dev, B43_MMIO_MACCTL);
ba380013
MB		 2630 for (i = 35; i; i--) {
2631 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2632 if (tmp & B43_IRQ_MAC_SUSPENDED)
2633 goto out;
2634 udelay(10);
2635 }
2636 /* Hm, it seems this will take some time. Use msleep(). */
05b64b36 2637 for (i = 40; i; i--) {
e4d6b795
MB		 2638 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2639 if (tmp & B43_IRQ_MAC_SUSPENDED)
2640 goto out;
05b64b36 2641 msleep(1);
e4d6b795
MB		 2642 }
2643 b43err(dev->wl, "MAC suspend failed\n");
2644 }
05b64b36 2645out:
e4d6b795
MB		 2646 dev->mac_suspended++;
2647}
2648
2649static void b43_adjust_opmode(struct b43_wldev *dev)
2650{
2651 struct b43_wl *wl = dev->wl;
2652 u32 ctl;
2653 u16 cfp_pretbtt;
2654
2655 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2656 /* Reset status to STA infrastructure mode. */
2657 ctl &= ~B43_MACCTL_AP;
2658 ctl &= ~B43_MACCTL_KEEP_CTL;
2659 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2660 ctl &= ~B43_MACCTL_KEEP_BAD;
2661 ctl &= ~B43_MACCTL_PROMISC;
4150c572 2662 ctl &= ~B43_MACCTL_BEACPROMISC;
e4d6b795
MB		 2663 ctl |= B43_MACCTL_INFRA;
2664
05c914fe
JB		 2665 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2666 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
4150c572 2667 ctl |= B43_MACCTL_AP;
05c914fe 2668 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
4150c572
JB		 2669 ctl &= ~B43_MACCTL_INFRA;
2670
2671 if (wl->filter_flags & FIF_CONTROL)
e4d6b795 2672 ctl |= B43_MACCTL_KEEP_CTL;
4150c572
JB		 2673 if (wl->filter_flags & FIF_FCSFAIL)
2674 ctl |= B43_MACCTL_KEEP_BAD;
2675 if (wl->filter_flags & FIF_PLCPFAIL)
2676 ctl |= B43_MACCTL_KEEP_BADPLCP;
2677 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
e4d6b795 2678 ctl |= B43_MACCTL_PROMISC;
4150c572
JB		 2679 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2680 ctl |= B43_MACCTL_BEACPROMISC;
2681
e4d6b795
MB		 2682 /* Workaround: On old hardware the HW-MAC-address-filter
2683 * doesn't work properly, so always run promisc in filter
2684 * it in software. */
2685 if (dev->dev->id.revision <= 4)
2686 ctl |= B43_MACCTL_PROMISC;
2687
2688 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2689
2690 cfp_pretbtt = 2;
2691 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2692 if (dev->dev->bus->chip_id == 0x4306 &&
2693 dev->dev->bus->chip_rev == 3)
2694 cfp_pretbtt = 100;
2695 else
2696 cfp_pretbtt = 50;
2697 }
2698 b43_write16(dev, 0x612, cfp_pretbtt);
09ebe2f9
MB		 2699
2700 /* FIXME: We don't currently implement the PMQ mechanism,
2701 * so always disable it. If we want to implement PMQ,
2702 * we need to enable it here (clear DISCPMQ) in AP mode.
2703 */
2704 if (0 /* ctl & B43_MACCTL_AP */) {
2705 b43_write32(dev, B43_MMIO_MACCTL,
2706 b43_read32(dev, B43_MMIO_MACCTL)
2707 & ~B43_MACCTL_DISCPMQ);
2708 } else {
2709 b43_write32(dev, B43_MMIO_MACCTL,
2710 b43_read32(dev, B43_MMIO_MACCTL)
2711 | B43_MACCTL_DISCPMQ);
2712 }
e4d6b795
MB		 2713}
2714
2715static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2716{
2717 u16 offset;
2718
2719 if (is_ofdm) {
2720 offset = 0x480;
2721 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2722 } else {
2723 offset = 0x4C0;
2724 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2725 }
2726 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2727 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2728}
2729
2730static void b43_rate_memory_init(struct b43_wldev *dev)
2731{
2732 switch (dev->phy.type) {
2733 case B43_PHYTYPE_A:
2734 case B43_PHYTYPE_G:
53a6e234 2735 case B43_PHYTYPE_N:
9d86a2d5 2736 case B43_PHYTYPE_LP:
e4d6b795
MB		 2737 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2738 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2739 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2740 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2741 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2742 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2743 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2744 if (dev->phy.type == B43_PHYTYPE_A)
2745 break;
2746 /* fallthrough */
2747 case B43_PHYTYPE_B:
2748 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2749 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2750 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2751 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2752 break;
2753 default:
2754 B43_WARN_ON(1);
2755 }
2756}
2757
5042c507
MB		 2758/* Set the default values for the PHY TX Control Words. */
2759static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2760{
2761 u16 ctl = 0;
2762
2763 ctl |= B43_TXH_PHY_ENC_CCK;
2764 ctl |= B43_TXH_PHY_ANT01AUTO;
2765 ctl |= B43_TXH_PHY_TXPWR;
2766
2767 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2768 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2769 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2770}
2771
e4d6b795
MB		 2772/* Set the TX-Antenna for management frames sent by firmware. */
2773static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2774{
5042c507 2775 u16 ant;
e4d6b795
MB		 2776 u16 tmp;
2777
5042c507 2778 ant = b43_antenna_to_phyctl(antenna);
e4d6b795 2779
e4d6b795
MB		 2780 /* For ACK/CTS */
2781 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
eb189d8b 2782 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2783 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2784 /* For Probe Resposes */
2785 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
eb189d8b 2786 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
e4d6b795
MB		 2787 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2788}
2789
2790/* This is the opposite of b43_chip_init() */
2791static void b43_chip_exit(struct b43_wldev *dev)
2792{
fb11137a 2793 b43_phy_exit(dev);
e4d6b795
MB		 2794 b43_gpio_cleanup(dev);
2795 /* firmware is released later */
2796}
2797
2798/* Initialize the chip
2799 * http://bcm-specs.sipsolutions.net/ChipInit
2800 */
2801static int b43_chip_init(struct b43_wldev *dev)
2802{
2803 struct b43_phy *phy = &dev->phy;
ef1a628d 2804 int err;
1f7d87b0 2805 u32 value32, macctl;
e4d6b795
MB		 2806 u16 value16;
2807
1f7d87b0
MB		 2808 /* Initialize the MAC control */
2809 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2810 if (dev->phy.gmode)
2811 macctl |= B43_MACCTL_GMODE;
2812 macctl |= B43_MACCTL_INFRA;
2813 b43_write32(dev, B43_MMIO_MACCTL, macctl);
e4d6b795
MB		 2814
2815 err = b43_request_firmware(dev);
2816 if (err)
2817 goto out;
2818 err = b43_upload_microcode(dev);
2819 if (err)
2820 goto out; /* firmware is released later */
2821
2822 err = b43_gpio_init(dev);
2823 if (err)
2824 goto out; /* firmware is released later */
21954c36 2825
e4d6b795
MB		 2826 err = b43_upload_initvals(dev);
2827 if (err)
1a8d1227 2828 goto err_gpio_clean;
e4d6b795 2829
0b7dcd96
MB		 2830 /* Turn the Analog on and initialize the PHY. */
2831 phy->ops->switch_analog(dev, 1);
e4d6b795
MB		 2832 err = b43_phy_init(dev);
2833 if (err)
ef1a628d 2834 goto err_gpio_clean;
e4d6b795 2835
ef1a628d
MB		 2836 /* Disable Interference Mitigation. */
2837 if (phy->ops->interf_mitigation)
2838 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
e4d6b795 2839
ef1a628d
MB		 2840 /* Select the antennae */
2841 if (phy->ops->set_rx_antenna)
2842 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
e4d6b795
MB		 2843 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2844
2845 if (phy->type == B43_PHYTYPE_B) {
2846 value16 = b43_read16(dev, 0x005E);
2847 value16 |= 0x0004;
2848 b43_write16(dev, 0x005E, value16);
2849 }
2850 b43_write32(dev, 0x0100, 0x01000000);
2851 if (dev->dev->id.revision < 5)
2852 b43_write32(dev, 0x010C, 0x01000000);
2853
2854 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2855 & ~B43_MACCTL_INFRA);
2856 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2857 | B43_MACCTL_INFRA);
e4d6b795 2858
e4d6b795
MB		 2859 /* Probe Response Timeout value */
2860 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2861 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2862
2863 /* Initially set the wireless operation mode. */
2864 b43_adjust_opmode(dev);
2865
2866 if (dev->dev->id.revision < 3) {
2867 b43_write16(dev, 0x060E, 0x0000);
2868 b43_write16(dev, 0x0610, 0x8000);
2869 b43_write16(dev, 0x0604, 0x0000);
2870 b43_write16(dev, 0x0606, 0x0200);
2871 } else {
2872 b43_write32(dev, 0x0188, 0x80000000);
2873 b43_write32(dev, 0x018C, 0x02000000);
2874 }
2875 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2876 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2877 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2878 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2879 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2880 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2881 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2882
2883 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2884 value32 |= 0x00100000;
2885 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2886
2887 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2888 dev->dev->bus->chipco.fast_pwrup_delay);
2889
2890 err = 0;
2891 b43dbg(dev->wl, "Chip initialized\n");
21954c36 2892out:
e4d6b795
MB		 2893 return err;
2894
1a8d1227 2895err_gpio_clean:
e4d6b795 2896 b43_gpio_cleanup(dev);
21954c36 2897 return err;
e4d6b795
MB		 2898}
2899
e4d6b795
MB		 2900static void b43_periodic_every60sec(struct b43_wldev *dev)
2901{
ef1a628d 2902 const struct b43_phy_operations *ops = dev->phy.ops;
e4d6b795 2903
ef1a628d
MB		 2904 if (ops->pwork_60sec)
2905 ops->pwork_60sec(dev);
18c8adeb
MB		 2906
2907 /* Force check the TX power emission now. */
2908 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
e4d6b795
MB		 2909}
2910
2911static void b43_periodic_every30sec(struct b43_wldev *dev)
2912{
2913 /* Update device statistics. */
2914 b43_calculate_link_quality(dev);
2915}
2916
2917static void b43_periodic_every15sec(struct b43_wldev *dev)
2918{
2919 struct b43_phy *phy = &dev->phy;
9b839a74
MB		 2920 u16 wdr;
2921
2922 if (dev->fw.opensource) {
2923 /* Check if the firmware is still alive.
2924 * It will reset the watchdog counter to 0 in its idle loop. */
2925 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2926 if (unlikely(wdr)) {
2927 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2928 b43_controller_restart(dev, "Firmware watchdog");
2929 return;
2930 } else {
2931 b43_shm_write16(dev, B43_SHM_SCRATCH,
2932 B43_WATCHDOG_REG, 1);
2933 }
2934 }
e4d6b795 2935
ef1a628d
MB		 2936 if (phy->ops->pwork_15sec)
2937 phy->ops->pwork_15sec(dev);
2938
00e0b8cb
SB		 2939 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2940 wmb();
990b86f4
MB		 2941
2942#if B43_DEBUG
2943 if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
2944 unsigned int i;
2945
2946 b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
2947 dev->irq_count / 15,
2948 dev->tx_count / 15,
2949 dev->rx_count / 15);
2950 dev->irq_count = 0;
2951 dev->tx_count = 0;
2952 dev->rx_count = 0;
2953 for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
2954 if (dev->irq_bit_count[i]) {
2955 b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
2956 dev->irq_bit_count[i] / 15, i, (1 << i));
2957 dev->irq_bit_count[i] = 0;
2958 }
2959 }
2960 }
2961#endif
e4d6b795
MB		 2962}
2963
e4d6b795
MB		 2964static void do_periodic_work(struct b43_wldev *dev)
2965{
2966 unsigned int state;
2967
2968 state = dev->periodic_state;
42bb4cd5 2969 if (state % 4 == 0)
e4d6b795 2970 b43_periodic_every60sec(dev);
42bb4cd5 2971 if (state % 2 == 0)
e4d6b795 2972 b43_periodic_every30sec(dev);
42bb4cd5 2973 b43_periodic_every15sec(dev);
e4d6b795
MB		 2974}
2975
05b64b36
MB		 2976/* Periodic work locking policy:
2977 * The whole periodic work handler is protected by
2978 * wl->mutex. If another lock is needed somewhere in the
2979 * pwork callchain, it's aquired in-place, where it's needed.
e4d6b795 2980 */
e4d6b795
MB		 2981static void b43_periodic_work_handler(struct work_struct *work)
2982{
05b64b36
MB		 2983 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2984 periodic_work.work);
2985 struct b43_wl *wl = dev->wl;
2986 unsigned long delay;
e4d6b795 2987
05b64b36 2988 mutex_lock(&wl->mutex);
e4d6b795
MB		 2989
2990 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2991 goto out;
2992 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2993 goto out_requeue;
2994
05b64b36 2995 do_periodic_work(dev);
e4d6b795 2996
e4d6b795 2997 dev->periodic_state++;
42bb4cd5 2998out_requeue:
e4d6b795
MB		 2999 if (b43_debug(dev, B43_DBG_PWORK_FAST))
3000 delay = msecs_to_jiffies(50);
3001 else
82cd682d 3002 delay = round_jiffies_relative(HZ * 15);
42935eca 3003 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
42bb4cd5 3004out:
05b64b36 3005 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3006}
3007
3008static void b43_periodic_tasks_setup(struct b43_wldev *dev)
3009{
3010 struct delayed_work *work = &dev->periodic_work;
3011
3012 dev->periodic_state = 0;
3013 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
42935eca 3014 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
e4d6b795
MB		 3015}
3016
f3dd3fcc 3017/* Check if communication with the device works correctly. */
e4d6b795
MB		 3018static int b43_validate_chipaccess(struct b43_wldev *dev)
3019{
f62ae6cd 3020 u32 v, backup0, backup4;
e4d6b795 3021
f62ae6cd
MB		 3022 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
3023 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
f3dd3fcc
MB		 3024
3025 /* Check for read/write and endianness problems. */
e4d6b795
MB		 3026 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
3027 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
3028 goto error;
f3dd3fcc
MB		 3029 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
3030 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
e4d6b795
MB		 3031 goto error;
3032
f62ae6cd
MB		 3033 /* Check if unaligned 32bit SHM_SHARED access works properly.
3034 * However, don't bail out on failure, because it's noncritical. */
3035 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3036 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3037 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3038 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3039 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3040 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3041 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3042 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3043 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3044 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3045 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3046 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3047
3048 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3049 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
f3dd3fcc
MB		 3050
3051 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3052 /* The 32bit register shadows the two 16bit registers
3053 * with update sideeffects. Validate this. */
3054 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3055 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3056 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3057 goto error;
3058 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3059 goto error;
3060 }
3061 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3062
3063 v = b43_read32(dev, B43_MMIO_MACCTL);
3064 v |= B43_MACCTL_GMODE;
3065 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
e4d6b795
MB		 3066 goto error;
3067
3068 return 0;
f3dd3fcc 3069error:
e4d6b795
MB		 3070 b43err(dev->wl, "Failed to validate the chipaccess\n");
3071 return -ENODEV;
3072}
3073
3074static void b43_security_init(struct b43_wldev *dev)
3075{
e4d6b795
MB		 3076 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3077 /* KTP is a word address, but we address SHM bytewise.
3078 * So multiply by two.
3079 */
3080 dev->ktp *= 2;
66d2d089
MB		 3081 /* Number of RCMTA address slots */
3082 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3083 /* Clear the key memory. */
e4d6b795
MB		 3084 b43_clear_keys(dev);
3085}
3086
616de35d 3087#ifdef CONFIG_B43_HWRNG
99da185a 3088static int b43_rng_read(struct hwrng *rng, u32 *data)
e4d6b795
MB		 3089{
3090 struct b43_wl *wl = (struct b43_wl *)rng->priv;
a78b3bb2
MB		 3091 struct b43_wldev *dev;
3092 int count = -ENODEV;
e4d6b795 3093
a78b3bb2
MB		 3094 mutex_lock(&wl->mutex);
3095 dev = wl->current_dev;
3096 if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
3097 *data = b43_read16(dev, B43_MMIO_RNG);
3098 count = sizeof(u16);
3099 }
3100 mutex_unlock(&wl->mutex);
e4d6b795 3101
a78b3bb2 3102 return count;
e4d6b795 3103}
616de35d 3104#endif /* CONFIG_B43_HWRNG */
e4d6b795 3105
b844eba2 3106static void b43_rng_exit(struct b43_wl *wl)
e4d6b795 3107{
616de35d 3108#ifdef CONFIG_B43_HWRNG
e4d6b795 3109 if (wl->rng_initialized)
b844eba2 3110 hwrng_unregister(&wl->rng);
616de35d 3111#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3112}
3113
3114static int b43_rng_init(struct b43_wl *wl)
3115{
616de35d 3116 int err = 0;
e4d6b795 3117
616de35d 3118#ifdef CONFIG_B43_HWRNG
e4d6b795
MB		 3119 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3120 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3121 wl->rng.name = wl->rng_name;
3122 wl->rng.data_read = b43_rng_read;
3123 wl->rng.priv = (unsigned long)wl;
3124 wl->rng_initialized = 1;
3125 err = hwrng_register(&wl->rng);
3126 if (err) {
3127 wl->rng_initialized = 0;
3128 b43err(wl, "Failed to register the random "
3129 "number generator (%d)\n", err);
3130 }
616de35d 3131#endif /* CONFIG_B43_HWRNG */
e4d6b795
MB		 3132
3133 return err;
3134}
3135
f5d40eed 3136static void b43_tx_work(struct work_struct *work)
e4d6b795 3137{
f5d40eed
MB		 3138 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3139 struct b43_wldev *dev;
3140 struct sk_buff *skb;
3141 int err = 0;
e4d6b795 3142
f5d40eed
MB		 3143 mutex_lock(&wl->mutex);
3144 dev = wl->current_dev;
3145 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3146 mutex_unlock(&wl->mutex);
3147 return;
5100d5ac 3148 }
21a75d77 3149
f5d40eed
MB		 3150 while (skb_queue_len(&wl->tx_queue)) {
3151 skb = skb_dequeue(&wl->tx_queue);
21a75d77 3152
21a75d77 3153 if (b43_using_pio_transfers(dev))
e039fa4a 3154 err = b43_pio_tx(dev, skb);
21a75d77 3155 else
e039fa4a 3156 err = b43_dma_tx(dev, skb);
f5d40eed
MB		 3157 if (unlikely(err))
3158 dev_kfree_skb(skb); /* Drop it */
21a75d77
MB		 3159 }
3160
990b86f4
MB		 3161#if B43_DEBUG
3162 dev->tx_count++;
3163#endif
f5d40eed
MB		 3164 mutex_unlock(&wl->mutex);
3165}
21a75d77 3166
f5d40eed
MB		 3167static int b43_op_tx(struct ieee80211_hw *hw,
3168 struct sk_buff *skb)
3169{
3170 struct b43_wl *wl = hw_to_b43_wl(hw);
3171
3172 if (unlikely(skb->len < 2 + 2 + 6)) {
3173 /* Too short, this can't be a valid frame. */
3174 dev_kfree_skb_any(skb);
3175 return NETDEV_TX_OK;
3176 }
3177 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3178
3179 skb_queue_tail(&wl->tx_queue, skb);
3180 ieee80211_queue_work(wl->hw, &wl->tx_work);
c9e8eae0 3181
e4d6b795
MB		 3182 return NETDEV_TX_OK;
3183}
3184
e6f5b934
MB		 3185static void b43_qos_params_upload(struct b43_wldev *dev,
3186 const struct ieee80211_tx_queue_params *p,
3187 u16 shm_offset)
3188{
3189 u16 params[B43_NR_QOSPARAMS];
0b57664c 3190 int bslots, tmp;
e6f5b934
MB		 3191 unsigned int i;
3192
b0544eb6
MB		 3193 if (!dev->qos_enabled)
3194 return;
3195
0b57664c 3196 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
e6f5b934
MB		 3197
3198 memset(&params, 0, sizeof(params));
3199
3200 params[B43_QOSPARAM_TXOP] = p->txop * 32;
0b57664c
JB		 3201 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3202 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3203 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3204 params[B43_QOSPARAM_AIFS] = p->aifs;
e6f5b934 3205 params[B43_QOSPARAM_BSLOTS] = bslots;
0b57664c 3206 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
e6f5b934
MB		 3207
3208 for (i = 0; i < ARRAY_SIZE(params); i++) {
3209 if (i == B43_QOSPARAM_STATUS) {
3210 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3211 shm_offset + (i * 2));
3212 /* Mark the parameters as updated. */
3213 tmp |= 0x100;
3214 b43_shm_write16(dev, B43_SHM_SHARED,
3215 shm_offset + (i * 2),
3216 tmp);
3217 } else {
3218 b43_shm_write16(dev, B43_SHM_SHARED,
3219 shm_offset + (i * 2),
3220 params[i]);
3221 }
3222 }
3223}
3224
c40c1129
MB		 3225/* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3226static const u16 b43_qos_shm_offsets[] = {
3227 /* [mac80211-queue-nr] = SHM_OFFSET, */
3228 [0] = B43_QOS_VOICE,
3229 [1] = B43_QOS_VIDEO,
3230 [2] = B43_QOS_BESTEFFORT,
3231 [3] = B43_QOS_BACKGROUND,
3232};
3233
5a5f3b40
MB		 3234/* Update all QOS parameters in hardware. */
3235static void b43_qos_upload_all(struct b43_wldev *dev)
e6f5b934
MB		 3236{
3237 struct b43_wl *wl = dev->wl;
3238 struct b43_qos_params *params;
e6f5b934
MB		 3239 unsigned int i;
3240
b0544eb6
MB		 3241 if (!dev->qos_enabled)
3242 return;
3243
c40c1129
MB		 3244 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3245 ARRAY_SIZE(wl->qos_params));
e6f5b934
MB		 3246
3247 b43_mac_suspend(dev);
e6f5b934
MB		 3248 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3249 params = &(wl->qos_params[i]);
5a5f3b40
MB		 3250 b43_qos_params_upload(dev, &(params->p),
3251 b43_qos_shm_offsets[i]);
e6f5b934 3252 }
e6f5b934
MB		 3253 b43_mac_enable(dev);
3254}
3255
3256static void b43_qos_clear(struct b43_wl *wl)
3257{
3258 struct b43_qos_params *params;
3259 unsigned int i;
3260
c40c1129
MB		 3261 /* Initialize QoS parameters to sane defaults. */
3262
3263 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3264 ARRAY_SIZE(wl->qos_params));
3265
e6f5b934
MB		 3266 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3267 params = &(wl->qos_params[i]);
3268
c40c1129
MB		 3269 switch (b43_qos_shm_offsets[i]) {
3270 case B43_QOS_VOICE:
3271 params->p.txop = 0;
3272 params->p.aifs = 2;
3273 params->p.cw_min = 0x0001;
3274 params->p.cw_max = 0x0001;
3275 break;
3276 case B43_QOS_VIDEO:
3277 params->p.txop = 0;
3278 params->p.aifs = 2;
3279 params->p.cw_min = 0x0001;
3280 params->p.cw_max = 0x0001;
3281 break;
3282 case B43_QOS_BESTEFFORT:
3283 params->p.txop = 0;
3284 params->p.aifs = 3;
3285 params->p.cw_min = 0x0001;
3286 params->p.cw_max = 0x03FF;
3287 break;
3288 case B43_QOS_BACKGROUND:
3289 params->p.txop = 0;
3290 params->p.aifs = 7;
3291 params->p.cw_min = 0x0001;
3292 params->p.cw_max = 0x03FF;
3293 break;
3294 default:
3295 B43_WARN_ON(1);
3296 }
e6f5b934
MB		 3297 }
3298}
3299
3300/* Initialize the core's QOS capabilities */
3301static void b43_qos_init(struct b43_wldev *dev)
3302{
b0544eb6
MB		 3303 if (!dev->qos_enabled) {
3304 /* Disable QOS support. */
3305 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
3306 b43_write16(dev, B43_MMIO_IFSCTL,
3307 b43_read16(dev, B43_MMIO_IFSCTL)
3308 & ~B43_MMIO_IFSCTL_USE_EDCF);
3309 b43dbg(dev->wl, "QoS disabled\n");
3310 return;
3311 }
3312
e6f5b934 3313 /* Upload the current QOS parameters. */
5a5f3b40 3314 b43_qos_upload_all(dev);
e6f5b934
MB		 3315
3316 /* Enable QOS support. */
3317 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3318 b43_write16(dev, B43_MMIO_IFSCTL,
3319 b43_read16(dev, B43_MMIO_IFSCTL)
3320 | B43_MMIO_IFSCTL_USE_EDCF);
b0544eb6 3321 b43dbg(dev->wl, "QoS enabled\n");
e6f5b934
MB		 3322}
3323
e100bb64 3324static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
40faacc4 3325 const struct ieee80211_tx_queue_params *params)
e4d6b795 3326{
e6f5b934 3327 struct b43_wl *wl = hw_to_b43_wl(hw);
5a5f3b40 3328 struct b43_wldev *dev;
e6f5b934 3329 unsigned int queue = (unsigned int)_queue;
5a5f3b40 3330 int err = -ENODEV;
e6f5b934
MB		 3331
3332 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3333 /* Queue not available or don't support setting
3334 * params on this queue. Return success to not
3335 * confuse mac80211. */
3336 return 0;
3337 }
5a5f3b40
MB		 3338 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3339 ARRAY_SIZE(wl->qos_params));
e6f5b934 3340
5a5f3b40
MB		 3341 mutex_lock(&wl->mutex);
3342 dev = wl->current_dev;
3343 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3344 goto out_unlock;
e6f5b934 3345
5a5f3b40
MB		 3346 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3347 b43_mac_suspend(dev);
3348 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3349 b43_qos_shm_offsets[queue]);
3350 b43_mac_enable(dev);
3351 err = 0;
e6f5b934 3352
5a5f3b40
MB		 3353out_unlock:
3354 mutex_unlock(&wl->mutex);
3355
3356 return err;
e4d6b795
MB		 3357}
3358
40faacc4
MB		 3359static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3360 struct ieee80211_tx_queue_stats *stats)
e4d6b795
MB		 3361{
3362 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3363 struct b43_wldev *dev;
e4d6b795
MB		 3364 int err = -ENODEV;
3365
36dbd954
MB		 3366 mutex_lock(&wl->mutex);
3367 dev = wl->current_dev;
3368 if (dev && b43_status(dev) >= B43_STAT_STARTED) {
5100d5ac
MB		 3369 if (b43_using_pio_transfers(dev))
3370 b43_pio_get_tx_stats(dev, stats);
3371 else
3372 b43_dma_get_tx_stats(dev, stats);
e4d6b795
MB		 3373 err = 0;
3374 }
36dbd954
MB		 3375 mutex_unlock(&wl->mutex);
3376
e4d6b795
MB		 3377 return err;
3378}
3379
40faacc4
MB		 3380static int b43_op_get_stats(struct ieee80211_hw *hw,
3381 struct ieee80211_low_level_stats *stats)
e4d6b795
MB		 3382{
3383 struct b43_wl *wl = hw_to_b43_wl(hw);
e4d6b795 3384
36dbd954 3385 mutex_lock(&wl->mutex);
e4d6b795 3386 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
36dbd954 3387 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3388
3389 return 0;
3390}
3391
08e87a83
AF		 3392static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3393{
3394 struct b43_wl *wl = hw_to_b43_wl(hw);
3395 struct b43_wldev *dev;
3396 u64 tsf;
3397
3398 mutex_lock(&wl->mutex);
08e87a83
AF		 3399 dev = wl->current_dev;
3400
3401 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3402 b43_tsf_read(dev, &tsf);
3403 else
3404 tsf = 0;
3405
08e87a83
AF		 3406 mutex_unlock(&wl->mutex);
3407
3408 return tsf;
3409}
3410
3411static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3412{
3413 struct b43_wl *wl = hw_to_b43_wl(hw);
3414 struct b43_wldev *dev;
3415
3416 mutex_lock(&wl->mutex);
08e87a83
AF		 3417 dev = wl->current_dev;
3418
3419 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3420 b43_tsf_write(dev, tsf);
3421
08e87a83
AF		 3422 mutex_unlock(&wl->mutex);
3423}
3424
e4d6b795
MB		 3425static void b43_put_phy_into_reset(struct b43_wldev *dev)
3426{
3427 struct ssb_device *sdev = dev->dev;
3428 u32 tmslow;
3429
3430 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3431 tmslow &= ~B43_TMSLOW_GMODE;
3432 tmslow |= B43_TMSLOW_PHYRESET;
3433 tmslow |= SSB_TMSLOW_FGC;
3434 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3435 msleep(1);
3436
3437 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3438 tmslow &= ~SSB_TMSLOW_FGC;
3439 tmslow |= B43_TMSLOW_PHYRESET;
3440 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3441 msleep(1);
3442}
3443
99da185a 3444static const char *band_to_string(enum ieee80211_band band)
bb1eeff1
MB		 3445{
3446 switch (band) {
3447 case IEEE80211_BAND_5GHZ:
3448 return "5";
3449 case IEEE80211_BAND_2GHZ:
3450 return "2.4";
3451 default:
3452 break;
3453 }
3454 B43_WARN_ON(1);
3455 return "";
3456}
3457
e4d6b795 3458/* Expects wl->mutex locked */
bb1eeff1 3459static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
e4d6b795 3460{
bb1eeff1 3461 struct b43_wldev *up_dev = NULL;
e4d6b795 3462 struct b43_wldev *down_dev;
bb1eeff1 3463 struct b43_wldev *d;
e4d6b795 3464 int err;
922d8a0b 3465 bool uninitialized_var(gmode);
e4d6b795
MB		 3466 int prev_status;
3467
bb1eeff1
MB		 3468 /* Find a device and PHY which supports the band. */
3469 list_for_each_entry(d, &wl->devlist, list) {
3470 switch (chan->band) {
3471 case IEEE80211_BAND_5GHZ:
3472 if (d->phy.supports_5ghz) {
3473 up_dev = d;
3474 gmode = 0;
3475 }
3476 break;
3477 case IEEE80211_BAND_2GHZ:
3478 if (d->phy.supports_2ghz) {
3479 up_dev = d;
3480 gmode = 1;
3481 }
3482 break;
3483 default:
3484 B43_WARN_ON(1);
3485 return -EINVAL;
3486 }
3487 if (up_dev)
3488 break;
3489 }
3490 if (!up_dev) {
3491 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3492 band_to_string(chan->band));
3493 return -ENODEV;
e4d6b795
MB		 3494 }
3495 if ((up_dev == wl->current_dev) &&
3496 (!!wl->current_dev->phy.gmode == !!gmode)) {
3497 /* This device is already running. */
3498 return 0;
3499 }
bb1eeff1
MB		 3500 b43dbg(wl, "Switching to %s-GHz band\n",
3501 band_to_string(chan->band));
e4d6b795
MB		 3502 down_dev = wl->current_dev;
3503
3504 prev_status = b43_status(down_dev);
3505 /* Shutdown the currently running core. */
3506 if (prev_status >= B43_STAT_STARTED)
36dbd954 3507 down_dev = b43_wireless_core_stop(down_dev);
e4d6b795
MB		 3508 if (prev_status >= B43_STAT_INITIALIZED)
3509 b43_wireless_core_exit(down_dev);
3510
3511 if (down_dev != up_dev) {
3512 /* We switch to a different core, so we put PHY into
3513 * RESET on the old core. */
3514 b43_put_phy_into_reset(down_dev);
3515 }
3516
3517 /* Now start the new core. */
3518 up_dev->phy.gmode = gmode;
3519 if (prev_status >= B43_STAT_INITIALIZED) {
3520 err = b43_wireless_core_init(up_dev);
3521 if (err) {
3522 b43err(wl, "Fatal: Could not initialize device for "
bb1eeff1
MB		 3523 "selected %s-GHz band\n",
3524 band_to_string(chan->band));
e4d6b795
MB		 3525 goto init_failure;
3526 }
3527 }
3528 if (prev_status >= B43_STAT_STARTED) {
3529 err = b43_wireless_core_start(up_dev);
3530 if (err) {
3531 b43err(wl, "Fatal: Coult not start device for "
bb1eeff1
MB		 3532 "selected %s-GHz band\n",
3533 band_to_string(chan->band));
e4d6b795
MB		 3534 b43_wireless_core_exit(up_dev);
3535 goto init_failure;
3536 }
3537 }
3538 B43_WARN_ON(b43_status(up_dev) != prev_status);
3539
3540 wl->current_dev = up_dev;
3541
3542 return 0;
bb1eeff1 3543init_failure:
e4d6b795
MB		 3544 /* Whoops, failed to init the new core. No core is operating now. */
3545 wl->current_dev = NULL;
3546 return err;
3547}
3548
9124b077
JB		 3549/* Write the short and long frame retry limit values. */
3550static void b43_set_retry_limits(struct b43_wldev *dev,
3551 unsigned int short_retry,
3552 unsigned int long_retry)
3553{
3554 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3555 * the chip-internal counter. */
3556 short_retry = min(short_retry, (unsigned int)0xF);
3557 long_retry = min(long_retry, (unsigned int)0xF);
3558
3559 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3560 short_retry);
3561 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3562 long_retry);
3563}
3564
e8975581 3565static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
e4d6b795
MB		 3566{
3567 struct b43_wl *wl = hw_to_b43_wl(hw);
3568 struct b43_wldev *dev;
3569 struct b43_phy *phy;
e8975581 3570 struct ieee80211_conf *conf = &hw->conf;
9db1f6d7 3571 int antenna;
e4d6b795 3572 int err = 0;
e4d6b795 3573
e4d6b795
MB		 3574 mutex_lock(&wl->mutex);
3575
bb1eeff1
MB		 3576 /* Switch the band (if necessary). This might change the active core. */
3577 err = b43_switch_band(wl, conf->channel);
e4d6b795
MB		 3578 if (err)
3579 goto out_unlock_mutex;
3580 dev = wl->current_dev;
3581 phy = &dev->phy;
3582
aa4c7b2a
RM		 3583 if (conf_is_ht(conf))
3584 phy->is_40mhz =
3585 (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
3586 else
3587 phy->is_40mhz = false;
3588
d10d0e57
MB		 3589 b43_mac_suspend(dev);
3590
9124b077
JB		 3591 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3592 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3593 conf->long_frame_max_tx_count);
3594 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3595 if (!changed)
d10d0e57 3596 goto out_mac_enable;
e4d6b795
MB		 3597
3598 /* Switch to the requested channel.
3599 * The firmware takes care of races with the TX handler. */
8318d78a 3600 if (conf->channel->hw_value != phy->channel)
ef1a628d 3601 b43_switch_channel(dev, conf->channel->hw_value);
e4d6b795 3602
0869aea0 3603 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
d42ce84a 3604
e4d6b795
MB		 3605 /* Adjust the desired TX power level. */
3606 if (conf->power_level != 0) {
18c8adeb
MB		 3607 if (conf->power_level != phy->desired_txpower) {
3608 phy->desired_txpower = conf->power_level;
3609 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3610 B43_TXPWR_IGNORE_TSSI);
e4d6b795
MB		 3611 }
3612 }
3613
3614 /* Antennas for RX and management frame TX. */
0f4ac38b 3615 antenna = B43_ANTENNA_DEFAULT;
9db1f6d7 3616 b43_mgmtframe_txantenna(dev, antenna);
0f4ac38b 3617 antenna = B43_ANTENNA_DEFAULT;
ef1a628d
MB		 3618 if (phy->ops->set_rx_antenna)
3619 phy->ops->set_rx_antenna(dev, antenna);
e4d6b795 3620
fd4973c5
LF		 3621 if (wl->radio_enabled != phy->radio_on) {
3622 if (wl->radio_enabled) {
19d337df 3623 b43_software_rfkill(dev, false);
fda9abcf
MB		 3624 b43info(dev->wl, "Radio turned on by software\n");
3625 if (!dev->radio_hw_enable) {
3626 b43info(dev->wl, "The hardware RF-kill button "
3627 "still turns the radio physically off. "
3628 "Press the button to turn it on.\n");
3629 }
3630 } else {
19d337df 3631 b43_software_rfkill(dev, true);
fda9abcf
MB		 3632 b43info(dev->wl, "Radio turned off by software\n");
3633 }
3634 }
3635
d10d0e57
MB		 3636out_mac_enable:
3637 b43_mac_enable(dev);
3638out_unlock_mutex:
e4d6b795
MB		 3639 mutex_unlock(&wl->mutex);
3640
3641 return err;
3642}
3643
881d948c 3644static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
c7ab5ef9
JB		 3645{
3646 struct ieee80211_supported_band *sband =
3647 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3648 struct ieee80211_rate *rate;
3649 int i;
3650 u16 basic, direct, offset, basic_offset, rateptr;
3651
3652 for (i = 0; i < sband->n_bitrates; i++) {
3653 rate = &sband->bitrates[i];
3654
3655 if (b43_is_cck_rate(rate->hw_value)) {
3656 direct = B43_SHM_SH_CCKDIRECT;
3657 basic = B43_SHM_SH_CCKBASIC;
3658 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3659 offset &= 0xF;
3660 } else {
3661 direct = B43_SHM_SH_OFDMDIRECT;
3662 basic = B43_SHM_SH_OFDMBASIC;
3663 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3664 offset &= 0xF;
3665 }
3666
3667 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3668
3669 if (b43_is_cck_rate(rate->hw_value)) {
3670 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3671 basic_offset &= 0xF;
3672 } else {
3673 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3674 basic_offset &= 0xF;
3675 }
3676
3677 /*
3678 * Get the pointer that we need to point to
3679 * from the direct map
3680 */
3681 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3682 direct + 2 * basic_offset);
3683 /* and write it to the basic map */
3684 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3685 rateptr);
3686 }
3687}
3688
3689static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3690 struct ieee80211_vif *vif,
3691 struct ieee80211_bss_conf *conf,
3692 u32 changed)
3693{
3694 struct b43_wl *wl = hw_to_b43_wl(hw);
3695 struct b43_wldev *dev;
c7ab5ef9
JB		 3696
3697 mutex_lock(&wl->mutex);
3698
3699 dev = wl->current_dev;
d10d0e57 3700 if (!dev || b43_status(dev) < B43_STAT_STARTED)
c7ab5ef9 3701 goto out_unlock_mutex;
2d0ddec5
JB		 3702
3703 B43_WARN_ON(wl->vif != vif);
3704
3705 if (changed & BSS_CHANGED_BSSID) {
2d0ddec5
JB		 3706 if (conf->bssid)
3707 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3708 else
3709 memset(wl->bssid, 0, ETH_ALEN);
3f0d843b 3710 }
2d0ddec5 3711
3f0d843b
JB		 3712 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3713 if (changed & BSS_CHANGED_BEACON &&
3714 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3715 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3716 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3717 b43_update_templates(wl);
3718
3719 if (changed & BSS_CHANGED_BSSID)
2d0ddec5 3720 b43_write_mac_bssid_templates(dev);
2d0ddec5
JB		 3721 }
3722
c7ab5ef9
JB		 3723 b43_mac_suspend(dev);
3724
57c4d7b4
JB		 3725 /* Update templates for AP/mesh mode. */
3726 if (changed & BSS_CHANGED_BEACON_INT &&
3727 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3728 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3729 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3730 b43_set_beacon_int(dev, conf->beacon_int);
3731
c7ab5ef9
JB		 3732 if (changed & BSS_CHANGED_BASIC_RATES)
3733 b43_update_basic_rates(dev, conf->basic_rates);
3734
3735 if (changed & BSS_CHANGED_ERP_SLOT) {
3736 if (conf->use_short_slot)
3737 b43_short_slot_timing_enable(dev);
3738 else
3739 b43_short_slot_timing_disable(dev);
3740 }
3741
3742 b43_mac_enable(dev);
d10d0e57 3743out_unlock_mutex:
c7ab5ef9 3744 mutex_unlock(&wl->mutex);
c7ab5ef9
JB		 3745}
3746
40faacc4 3747static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3748 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3749 struct ieee80211_key_conf *key)
e4d6b795
MB		 3750{
3751 struct b43_wl *wl = hw_to_b43_wl(hw);
c6dfc9a8 3752 struct b43_wldev *dev;
e4d6b795
MB		 3753 u8 algorithm;
3754 u8 index;
c6dfc9a8 3755 int err;
060210f9 3756 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
e4d6b795
MB		 3757
3758 if (modparam_nohwcrypt)
3759 return -ENOSPC; /* User disabled HW-crypto */
3760
c6dfc9a8 3761 mutex_lock(&wl->mutex);
c6dfc9a8
MB		 3762
3763 dev = wl->current_dev;
3764 err = -ENODEV;
3765 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3766 goto out_unlock;
3767
403a3a13 3768 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
68217832
MB		 3769 /* We don't have firmware for the crypto engine.
3770 * Must use software-crypto. */
3771 err = -EOPNOTSUPP;
3772 goto out_unlock;
3773 }
3774
c6dfc9a8 3775 err = -EINVAL;
e4d6b795 3776 switch (key->alg) {
e4d6b795 3777 case ALG_WEP:
e31a16d6 3778 if (key->keylen == WLAN_KEY_LEN_WEP40)
e4d6b795
MB		 3779 algorithm = B43_SEC_ALGO_WEP40;
3780 else
3781 algorithm = B43_SEC_ALGO_WEP104;
3782 break;
3783 case ALG_TKIP:
3784 algorithm = B43_SEC_ALGO_TKIP;
3785 break;
3786 case ALG_CCMP:
3787 algorithm = B43_SEC_ALGO_AES;
3788 break;
3789 default:
3790 B43_WARN_ON(1);
c6dfc9a8 3791 goto out_unlock;
e4d6b795 3792 }
e4d6b795
MB		 3793 index = (u8) (key->keyidx);
3794 if (index > 3)
e4d6b795 3795 goto out_unlock;
e4d6b795
MB		 3796
3797 switch (cmd) {
3798 case SET_KEY:
035d0243 3799 if (algorithm == B43_SEC_ALGO_TKIP &&
3800 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3801 !modparam_hwtkip)) {
3802 /* We support only pairwise key */
e4d6b795
MB		 3803 err = -EOPNOTSUPP;
3804 goto out_unlock;
3805 }
3806
e808e586 3807 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
dc822b5d
JB		 3808 if (WARN_ON(!sta)) {
3809 err = -EOPNOTSUPP;
3810 goto out_unlock;
3811 }
e808e586 3812 /* Pairwise key with an assigned MAC address. */
e4d6b795 3813 err = b43_key_write(dev, -1, algorithm,
dc822b5d
JB		 3814 key->key, key->keylen,
3815 sta->addr, key);
e808e586
MB		 3816 } else {
3817 /* Group key */
3818 err = b43_key_write(dev, index, algorithm,
3819 key->key, key->keylen, NULL, key);
e4d6b795
MB		 3820 }
3821 if (err)
3822 goto out_unlock;
3823
3824 if (algorithm == B43_SEC_ALGO_WEP40 ||
3825 algorithm == B43_SEC_ALGO_WEP104) {
3826 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3827 } else {
3828 b43_hf_write(dev,
3829 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3830 }
3831 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
035d0243 3832 if (algorithm == B43_SEC_ALGO_TKIP)
3833 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
e4d6b795
MB		 3834 break;
3835 case DISABLE_KEY: {
3836 err = b43_key_clear(dev, key->hw_key_idx);
3837 if (err)
3838 goto out_unlock;
3839 break;
3840 }
3841 default:
3842 B43_WARN_ON(1);
3843 }
9cf7f247 3844
e4d6b795 3845out_unlock:
e4d6b795
MB		 3846 if (!err) {
3847 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
e174961c 3848 "mac: %pM\n",
e4d6b795 3849 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
a1d88210 3850 sta ? sta->addr : bcast_addr);
9cf7f247 3851 b43_dump_keymemory(dev);
e4d6b795 3852 }
9cf7f247
MB		 3853 mutex_unlock(&wl->mutex);
3854
e4d6b795
MB		 3855 return err;
3856}
3857
40faacc4
MB		 3858static void b43_op_configure_filter(struct ieee80211_hw *hw,
3859 unsigned int changed, unsigned int *fflags,
3ac64bee 3860 u64 multicast)
e4d6b795
MB		 3861{
3862 struct b43_wl *wl = hw_to_b43_wl(hw);
36dbd954 3863 struct b43_wldev *dev;
e4d6b795 3864
36dbd954
MB		 3865 mutex_lock(&wl->mutex);
3866 dev = wl->current_dev;
4150c572
JB		 3867 if (!dev) {
3868 *fflags = 0;
36dbd954 3869 goto out_unlock;
e4d6b795 3870 }
4150c572 3871
4150c572
JB		 3872 *fflags &= FIF_PROMISC_IN_BSS |
3873 FIF_ALLMULTI |
3874 FIF_FCSFAIL |
3875 FIF_PLCPFAIL |
3876 FIF_CONTROL |
3877 FIF_OTHER_BSS |
3878 FIF_BCN_PRBRESP_PROMISC;
3879
3880 changed &= FIF_PROMISC_IN_BSS |
3881 FIF_ALLMULTI |
3882 FIF_FCSFAIL |
3883 FIF_PLCPFAIL |
3884 FIF_CONTROL |
3885 FIF_OTHER_BSS |
3886 FIF_BCN_PRBRESP_PROMISC;
3887
3888 wl->filter_flags = *fflags;
3889
3890 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3891 b43_adjust_opmode(dev);
36dbd954
MB		 3892
3893out_unlock:
3894 mutex_unlock(&wl->mutex);
e4d6b795
MB		 3895}
3896
36dbd954
MB		 3897/* Locking: wl->mutex
3898 * Returns the current dev. This might be different from the passed in dev,
3899 * because the core might be gone away while we unlocked the mutex. */
3900static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
e4d6b795
MB		 3901{
3902 struct b43_wl *wl = dev->wl;
36dbd954 3903 struct b43_wldev *orig_dev;
49d965c8 3904 u32 mask;
e4d6b795 3905
36dbd954
MB		 3906redo:
3907 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3908 return dev;
a19d12d7 3909
f5d40eed 3910 /* Cancel work. Unlock to avoid deadlocks. */
36dbd954
MB		 3911 mutex_unlock(&wl->mutex);
3912 cancel_delayed_work_sync(&dev->periodic_work);
f5d40eed 3913 cancel_work_sync(&wl->tx_work);
36dbd954
MB		 3914 mutex_lock(&wl->mutex);
3915 dev = wl->current_dev;
3916 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3917 /* Whoops, aliens ate up the device while we were unlocked. */
3918 return dev;
3919 }
a19d12d7 3920
36dbd954 3921 /* Disable interrupts on the device. */
e4d6b795 3922 b43_set_status(dev, B43_STAT_INITIALIZED);
3dbba8e2 3923 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
36dbd954
MB		 3924 /* wl->mutex is locked. That is enough. */
3925 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3926 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3927 } else {
3928 spin_lock_irq(&wl->hardirq_lock);
3929 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3930 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3931 spin_unlock_irq(&wl->hardirq_lock);
3932 }
176e9f6a 3933 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
36dbd954 3934 orig_dev = dev;
e4d6b795 3935 mutex_unlock(&wl->mutex);
176e9f6a
MB		 3936 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3937 b43_sdio_free_irq(dev);
3938 } else {
3939 synchronize_irq(dev->dev->irq);
3940 free_irq(dev->dev->irq, dev);
3941 }
e4d6b795 3942 mutex_lock(&wl->mutex);
36dbd954
MB		 3943 dev = wl->current_dev;
3944 if (!dev)
3945 return dev;
3946 if (dev != orig_dev) {
3947 if (b43_status(dev) >= B43_STAT_STARTED)
3948 goto redo;
3949 return dev;
3950 }
49d965c8
MB		 3951 mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
3952 B43_WARN_ON(mask != 0xFFFFFFFF && mask);
e4d6b795 3953
f5d40eed
MB		 3954 /* Drain the TX queue */
3955 while (skb_queue_len(&wl->tx_queue))
3956 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3957
e4d6b795 3958 b43_mac_suspend(dev);
a78b3bb2 3959 b43_leds_exit(dev);
e4d6b795 3960 b43dbg(wl, "Wireless interface stopped\n");
36dbd954
MB		 3961
3962 return dev;
e4d6b795
MB		 3963}
3964
3965/* Locking: wl->mutex */
3966static int b43_wireless_core_start(struct b43_wldev *dev)
3967{
3968 int err;
3969
3970 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3971
3972 drain_txstatus_queue(dev);
3dbba8e2
AH		 3973 if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
3974 err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
3975 if (err) {
3976 b43err(dev->wl, "Cannot request SDIO IRQ\n");
3977 goto out;
3978 }
3979 } else {
3980 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3981 b43_interrupt_thread_handler,
3982 IRQF_SHARED, KBUILD_MODNAME, dev);
3983 if (err) {
3984 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3985 goto out;
3986 }
e4d6b795
MB		 3987 }
3988
3989 /* We are ready to run. */
0866b03c 3990 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 3991 b43_set_status(dev, B43_STAT_STARTED);
3992
3993 /* Start data flow (TX/RX). */
3994 b43_mac_enable(dev);
13790728 3995 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
e4d6b795
MB		 3996
3997 /* Start maintainance work */
3998 b43_periodic_tasks_setup(dev);
3999
a78b3bb2
MB		 4000 b43_leds_init(dev);
4001
e4d6b795 4002 b43dbg(dev->wl, "Wireless interface started\n");
a78b3bb2 4003out:
e4d6b795
MB		 4004 return err;
4005}
4006
4007/* Get PHY and RADIO versioning numbers */
4008static int b43_phy_versioning(struct b43_wldev *dev)
4009{
4010 struct b43_phy *phy = &dev->phy;
4011 u32 tmp;
4012 u8 analog_type;
4013 u8 phy_type;
4014 u8 phy_rev;
4015 u16 radio_manuf;
4016 u16 radio_ver;
4017 u16 radio_rev;
4018 int unsupported = 0;
4019
4020 /* Get PHY versioning */
4021 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
4022 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
4023 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
4024 phy_rev = (tmp & B43_PHYVER_VERSION);
4025 switch (phy_type) {
4026 case B43_PHYTYPE_A:
4027 if (phy_rev >= 4)
4028 unsupported = 1;
4029 break;
4030 case B43_PHYTYPE_B:
4031 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
4032 && phy_rev != 7)
4033 unsupported = 1;
4034 break;
4035 case B43_PHYTYPE_G:
013978b6 4036 if (phy_rev > 9)
e4d6b795
MB		 4037 unsupported = 1;
4038 break;
d5c71e46
MB		 4039#ifdef CONFIG_B43_NPHY
4040 case B43_PHYTYPE_N:
bb519bee 4041 if (phy_rev > 4)
d5c71e46
MB		 4042 unsupported = 1;
4043 break;
6b1c7c67
MB		 4044#endif
4045#ifdef CONFIG_B43_PHY_LP
4046 case B43_PHYTYPE_LP:
9d86a2d5 4047 if (phy_rev > 2)
6b1c7c67
MB		 4048 unsupported = 1;
4049 break;
d5c71e46 4050#endif
e4d6b795
MB		 4051 default:
4052 unsupported = 1;
4053 };
4054 if (unsupported) {
4055 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
4056 "(Analog %u, Type %u, Revision %u)\n",
4057 analog_type, phy_type, phy_rev);
4058 return -EOPNOTSUPP;
4059 }
4060 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
4061 analog_type, phy_type, phy_rev);
4062
4063 /* Get RADIO versioning */
4064 if (dev->dev->bus->chip_id == 0x4317) {
4065 if (dev->dev->bus->chip_rev == 0)
4066 tmp = 0x3205017F;
4067 else if (dev->dev->bus->chip_rev == 1)
4068 tmp = 0x4205017F;
4069 else
4070 tmp = 0x5205017F;
4071 } else {
4072 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 4073 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
e4d6b795 4074 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
243dcfcc 4075 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
e4d6b795
MB		 4076 }
4077 radio_manuf = (tmp & 0x00000FFF);
4078 radio_ver = (tmp & 0x0FFFF000) >> 12;
4079 radio_rev = (tmp & 0xF0000000) >> 28;
96c755a3
MB		 4080 if (radio_manuf != 0x17F /* Broadcom */)
4081 unsupported = 1;
e4d6b795
MB		 4082 switch (phy_type) {
4083 case B43_PHYTYPE_A:
4084 if (radio_ver != 0x2060)
4085 unsupported = 1;
4086 if (radio_rev != 1)
4087 unsupported = 1;
4088 if (radio_manuf != 0x17F)
4089 unsupported = 1;
4090 break;
4091 case B43_PHYTYPE_B:
4092 if ((radio_ver & 0xFFF0) != 0x2050)
4093 unsupported = 1;
4094 break;
4095 case B43_PHYTYPE_G:
4096 if (radio_ver != 0x2050)
4097 unsupported = 1;
4098 break;
96c755a3 4099 case B43_PHYTYPE_N:
bb519bee 4100 if (radio_ver != 0x2055 && radio_ver != 0x2056)
96c755a3
MB		 4101 unsupported = 1;
4102 break;
6b1c7c67 4103 case B43_PHYTYPE_LP:
9d86a2d5 4104 if (radio_ver != 0x2062 && radio_ver != 0x2063)
6b1c7c67
MB		 4105 unsupported = 1;
4106 break;
e4d6b795
MB		 4107 default:
4108 B43_WARN_ON(1);
4109 }
4110 if (unsupported) {
4111 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4112 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4113 radio_manuf, radio_ver, radio_rev);
4114 return -EOPNOTSUPP;
4115 }
4116 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4117 radio_manuf, radio_ver, radio_rev);
4118
4119 phy->radio_manuf = radio_manuf;
4120 phy->radio_ver = radio_ver;
4121 phy->radio_rev = radio_rev;
4122
4123 phy->analog = analog_type;
4124 phy->type = phy_type;
4125 phy->rev = phy_rev;
4126
4127 return 0;
4128}
4129
4130static void setup_struct_phy_for_init(struct b43_wldev *dev,
4131 struct b43_phy *phy)
4132{
e4d6b795 4133 phy->hardware_power_control = !!modparam_hwpctl;
18c8adeb 4134 phy->next_txpwr_check_time = jiffies;
8ed7fc48
MB		 4135 /* PHY TX errors counter. */
4136 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
591f3dc2
MB		 4137
4138#if B43_DEBUG
4139 phy->phy_locked = 0;
4140 phy->radio_locked = 0;
4141#endif
e4d6b795
MB		 4142}
4143
4144static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4145{
aa6c7ae2
MB		 4146 dev->dfq_valid = 0;
4147
6a724d68
MB		 4148 /* Assume the radio is enabled. If it's not enabled, the state will
4149 * immediately get fixed on the first periodic work run. */
4150 dev->radio_hw_enable = 1;
e4d6b795
MB		 4151
4152 /* Stats */
4153 memset(&dev->stats, 0, sizeof(dev->stats));
4154
4155 setup_struct_phy_for_init(dev, &dev->phy);
4156
4157 /* IRQ related flags */
4158 dev->irq_reason = 0;
4159 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
13790728 4160 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
3e3ccb3d 4161 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
13790728 4162 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
e4d6b795
MB		 4163
4164 dev->mac_suspended = 1;
4165
4166 /* Noise calculation context */
4167 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4168}
4169
4170static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4171{
4172 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
a259d6a4 4173 u64 hf;
e4d6b795 4174
1855ba78
MB		 4175 if (!modparam_btcoex)
4176 return;
95de2841 4177 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
e4d6b795
MB		 4178 return;
4179 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4180 return;
4181
4182 hf = b43_hf_read(dev);
95de2841 4183 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
e4d6b795
MB		 4184 hf |= B43_HF_BTCOEXALT;
4185 else
4186 hf |= B43_HF_BTCOEX;
4187 b43_hf_write(dev, hf);
e4d6b795
MB		 4188}
4189
4190static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
1855ba78
MB		 4191{
4192 if (!modparam_btcoex)
4193 return;
4194 //TODO
e4d6b795
MB		 4195}
4196
4197static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4198{
4199#ifdef CONFIG_SSB_DRIVER_PCICORE
4200 struct ssb_bus *bus = dev->dev->bus;
4201 u32 tmp;
4202
4203 if (bus->pcicore.dev &&
4204 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4205 bus->pcicore.dev->id.revision <= 5) {
4206 /* IMCFGLO timeouts workaround. */
4207 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
e4d6b795
MB		 4208 switch (bus->bustype) {
4209 case SSB_BUSTYPE_PCI:
4210 case SSB_BUSTYPE_PCMCIA:
98a1e2a9
MB		 4211 tmp &= ~SSB_IMCFGLO_REQTO;
4212 tmp &= ~SSB_IMCFGLO_SERTO;
e4d6b795
MB		 4213 tmp |= 0x32;
4214 break;
4215 case SSB_BUSTYPE_SSB:
98a1e2a9
MB		 4216 tmp &= ~SSB_IMCFGLO_REQTO;
4217 tmp &= ~SSB_IMCFGLO_SERTO;
e4d6b795
MB		 4218 tmp |= 0x53;
4219 break;
98a1e2a9
MB		 4220 default:
4221 break;
e4d6b795
MB		 4222 }
4223 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4224 }
4225#endif /* CONFIG_SSB_DRIVER_PCICORE */
4226}
4227
d59f720d
MB		 4228static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4229{
4230 u16 pu_delay;
4231
4232 /* The time value is in microseconds. */
4233 if (dev->phy.type == B43_PHYTYPE_A)
4234 pu_delay = 3700;
4235 else
4236 pu_delay = 1050;
05c914fe 4237 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
d59f720d
MB		 4238 pu_delay = 500;
4239 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4240 pu_delay = max(pu_delay, (u16)2400);
4241
4242 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4243}
4244
4245/* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4246static void b43_set_pretbtt(struct b43_wldev *dev)
4247{
4248 u16 pretbtt;
4249
4250 /* The time value is in microseconds. */
05c914fe 4251 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
d59f720d
MB		 4252 pretbtt = 2;
4253 } else {
4254 if (dev->phy.type == B43_PHYTYPE_A)
4255 pretbtt = 120;
4256 else
4257 pretbtt = 250;
4258 }
4259 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4260 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4261}
4262
e4d6b795
MB		 4263/* Shutdown a wireless core */
4264/* Locking: wl->mutex */
4265static void b43_wireless_core_exit(struct b43_wldev *dev)
4266{
1f7d87b0 4267 u32 macctl;
e4d6b795 4268
36dbd954
MB		 4269 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4270 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
e4d6b795
MB		 4271 return;
4272 b43_set_status(dev, B43_STAT_UNINIT);
4273
1f7d87b0
MB		 4274 /* Stop the microcode PSM. */
4275 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4276 macctl &= ~B43_MACCTL_PSM_RUN;
4277 macctl |= B43_MACCTL_PSM_JMP0;
4278 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4279
e4d6b795 4280 b43_dma_free(dev);
5100d5ac 4281 b43_pio_free(dev);
e4d6b795 4282 b43_chip_exit(dev);
cb24f57f 4283 dev->phy.ops->switch_analog(dev, 0);
e66fee6a
MB		 4284 if (dev->wl->current_beacon) {
4285 dev_kfree_skb_any(dev->wl->current_beacon);
4286 dev->wl->current_beacon = NULL;
4287 }
4288
e4d6b795
MB		 4289 ssb_device_disable(dev->dev, 0);
4290 ssb_bus_may_powerdown(dev->dev->bus);
4291}
4292
4293/* Initialize a wireless core */
4294static int b43_wireless_core_init(struct b43_wldev *dev)
4295{
e4d6b795
MB		 4296 struct ssb_bus *bus = dev->dev->bus;
4297 struct ssb_sprom *sprom = &bus->sprom;
4298 struct b43_phy *phy = &dev->phy;
4299 int err;
a259d6a4
MB		 4300 u64 hf;
4301 u32 tmp;
e4d6b795
MB		 4302
4303 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4304
4305 err = ssb_bus_powerup(bus, 0);
4306 if (err)
4307 goto out;
4308 if (!ssb_device_is_enabled(dev->dev)) {
4309 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4310 b43_wireless_core_reset(dev, tmp);
4311 }
4312
fb11137a 4313 /* Reset all data structures. */
e4d6b795 4314 setup_struct_wldev_for_init(dev);
fb11137a 4315 phy->ops->prepare_structs(dev);
e4d6b795
MB		 4316
4317 /* Enable IRQ routing to this device. */
4318 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4319
4320 b43_imcfglo_timeouts_workaround(dev);
4321 b43_bluetooth_coext_disable(dev);
fb11137a
MB		 4322 if (phy->ops->prepare_hardware) {
4323 err = phy->ops->prepare_hardware(dev);
ef1a628d 4324 if (err)
fb11137a 4325 goto err_busdown;
ef1a628d 4326 }
e4d6b795
MB		 4327 err = b43_chip_init(dev);
4328 if (err)
fb11137a 4329 goto err_busdown;
e4d6b795
MB		 4330 b43_shm_write16(dev, B43_SHM_SHARED,
4331 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4332 hf = b43_hf_read(dev);
4333 if (phy->type == B43_PHYTYPE_G) {
4334 hf |= B43_HF_SYMW;
4335 if (phy->rev == 1)
4336 hf |= B43_HF_GDCW;
95de2841 4337 if (sprom->boardflags_lo & B43_BFL_PACTRL)
e4d6b795 4338 hf |= B43_HF_OFDMPABOOST;
969d15cf
MB		 4339 }
4340 if (phy->radio_ver == 0x2050) {
4341 if (phy->radio_rev == 6)
4342 hf |= B43_HF_4318TSSI;
4343 if (phy->radio_rev < 6)
4344 hf |= B43_HF_VCORECALC;
e4d6b795 4345 }
1cc8f476
MB		 4346 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4347 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
1a77733c 4348#ifdef CONFIG_SSB_DRIVER_PCICORE
8821905c
MB		 4349 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4350 (bus->pcicore.dev->id.revision <= 10))
4351 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
1a77733c 4352#endif
25d3ef59 4353 hf &= ~B43_HF_SKCFPUP;
e4d6b795
MB		 4354 b43_hf_write(dev, hf);
4355
74cfdba7
MB		 4356 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4357 B43_DEFAULT_LONG_RETRY_LIMIT);
e4d6b795
MB		 4358 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4359 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4360
4361 /* Disable sending probe responses from firmware.
4362 * Setting the MaxTime to one usec will always trigger
4363 * a timeout, so we never send any probe resp.
4364 * A timeout of zero is infinite. */
4365 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4366
4367 b43_rate_memory_init(dev);
5042c507 4368 b43_set_phytxctl_defaults(dev);
e4d6b795
MB		 4369
4370 /* Minimum Contention Window */
4371 if (phy->type == B43_PHYTYPE_B) {
4372 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4373 } else {
4374 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4375 }
4376 /* Maximum Contention Window */
4377 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4378
3dbba8e2
AH		 4379 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
4380 (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) ||
b02914af 4381 modparam_pio) {
5100d5ac
MB		 4382 dev->__using_pio_transfers = 1;
4383 err = b43_pio_init(dev);
4384 } else {
4385 dev->__using_pio_transfers = 0;
4386 err = b43_dma_init(dev);
4387 }
e4d6b795
MB		 4388 if (err)
4389 goto err_chip_exit;
03b29773 4390 b43_qos_init(dev);
d59f720d 4391 b43_set_synth_pu_delay(dev, 1);
e4d6b795
MB		 4392 b43_bluetooth_coext_enable(dev);
4393
1cc8f476 4394 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4150c572 4395 b43_upload_card_macaddress(dev);
e4d6b795 4396 b43_security_init(dev);
e4d6b795 4397
5ab9549a 4398 ieee80211_wake_queues(dev->wl->hw);
e4d6b795
MB		 4399
4400 b43_set_status(dev, B43_STAT_INITIALIZED);
4401
1a8d1227 4402out:
e4d6b795
MB		 4403 return err;
4404
ef1a628d 4405err_chip_exit:
e4d6b795 4406 b43_chip_exit(dev);
ef1a628d 4407err_busdown:
e4d6b795
MB		 4408 ssb_bus_may_powerdown(bus);
4409 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4410 return err;
4411}
4412
40faacc4 4413static int b43_op_add_interface(struct ieee80211_hw *hw,
1ed32e4f 4414 struct ieee80211_vif *vif)
e4d6b795
MB		 4415{
4416 struct b43_wl *wl = hw_to_b43_wl(hw);
4417 struct b43_wldev *dev;
e4d6b795 4418 int err = -EOPNOTSUPP;
4150c572
JB		 4419
4420 /* TODO: allow WDS/AP devices to coexist */
4421
1ed32e4f
JB		 4422 if (vif->type != NL80211_IFTYPE_AP &&
4423 vif->type != NL80211_IFTYPE_MESH_POINT &&
4424 vif->type != NL80211_IFTYPE_STATION &&
4425 vif->type != NL80211_IFTYPE_WDS &&
4426 vif->type != NL80211_IFTYPE_ADHOC)
4150c572 4427 return -EOPNOTSUPP;
e4d6b795
MB		 4428
4429 mutex_lock(&wl->mutex);
4150c572 4430 if (wl->operating)
e4d6b795
MB		 4431 goto out_mutex_unlock;
4432
1ed32e4f 4433 b43dbg(wl, "Adding Interface type %d\n", vif->type);
e4d6b795
MB		 4434
4435 dev = wl->current_dev;
4150c572 4436 wl->operating = 1;
1ed32e4f
JB		 4437 wl->vif = vif;
4438 wl->if_type = vif->type;
4439 memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
4150c572 4440
4150c572 4441 b43_adjust_opmode(dev);
d59f720d
MB		 4442 b43_set_pretbtt(dev);
4443 b43_set_synth_pu_delay(dev, 0);
4150c572 4444 b43_upload_card_macaddress(dev);
4150c572
JB		 4445
4446 err = 0;
4447 out_mutex_unlock:
4448 mutex_unlock(&wl->mutex);
4449
4450 return err;
4451}
4452
40faacc4 4453static void b43_op_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 4454 struct ieee80211_vif *vif)
4150c572
JB		 4455{
4456 struct b43_wl *wl = hw_to_b43_wl(hw);
4457 struct b43_wldev *dev = wl->current_dev;
4150c572 4458
1ed32e4f 4459 b43dbg(wl, "Removing Interface type %d\n", vif->type);
4150c572
JB		 4460
4461 mutex_lock(&wl->mutex);
4462
4463 B43_WARN_ON(!wl->operating);
1ed32e4f 4464 B43_WARN_ON(wl->vif != vif);
32bfd35d 4465 wl->vif = NULL;
4150c572
JB		 4466
4467 wl->operating = 0;
4468
4150c572
JB		 4469 b43_adjust_opmode(dev);
4470 memset(wl->mac_addr, 0, ETH_ALEN);
4471 b43_upload_card_macaddress(dev);
4150c572
JB		 4472
4473 mutex_unlock(&wl->mutex);
4474}
4475
40faacc4 4476static int b43_op_start(struct ieee80211_hw *hw)
4150c572
JB		 4477{
4478 struct b43_wl *wl = hw_to_b43_wl(hw);
4479 struct b43_wldev *dev = wl->current_dev;
4480 int did_init = 0;
923403b8 4481 int err = 0;
4150c572 4482
7be1bb6b
MB		 4483 /* Kill all old instance specific information to make sure
4484 * the card won't use it in the short timeframe between start
4485 * and mac80211 reconfiguring it. */
4486 memset(wl->bssid, 0, ETH_ALEN);
4487 memset(wl->mac_addr, 0, ETH_ALEN);
4488 wl->filter_flags = 0;
4489 wl->radiotap_enabled = 0;
e6f5b934 4490 b43_qos_clear(wl);
6b4bec01
MB		 4491 wl->beacon0_uploaded = 0;
4492 wl->beacon1_uploaded = 0;
4493 wl->beacon_templates_virgin = 1;
fd4973c5 4494 wl->radio_enabled = 1;
7be1bb6b 4495
4150c572
JB		 4496 mutex_lock(&wl->mutex);
4497
e4d6b795
MB		 4498 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4499 err = b43_wireless_core_init(dev);
f41f3f37 4500 if (err)
e4d6b795
MB		 4501 goto out_mutex_unlock;
4502 did_init = 1;
4503 }
4150c572 4504
e4d6b795
MB		 4505 if (b43_status(dev) < B43_STAT_STARTED) {
4506 err = b43_wireless_core_start(dev);
4507 if (err) {
4508 if (did_init)
4509 b43_wireless_core_exit(dev);
4510 goto out_mutex_unlock;
4511 }
4512 }
4513
f41f3f37
JB		 4514 /* XXX: only do if device doesn't support rfkill irq */
4515 wiphy_rfkill_start_polling(hw->wiphy);
4516
4150c572 4517 out_mutex_unlock:
e4d6b795
MB		 4518 mutex_unlock(&wl->mutex);
4519
4520 return err;
4521}
4522
40faacc4 4523static void b43_op_stop(struct ieee80211_hw *hw)
e4d6b795
MB		 4524{
4525 struct b43_wl *wl = hw_to_b43_wl(hw);
4150c572 4526 struct b43_wldev *dev = wl->current_dev;
e4d6b795 4527
a82d9922 4528 cancel_work_sync(&(wl->beacon_update_trigger));
1a8d1227 4529
e4d6b795 4530 mutex_lock(&wl->mutex);
36dbd954
MB		 4531 if (b43_status(dev) >= B43_STAT_STARTED) {
4532 dev = b43_wireless_core_stop(dev);
4533 if (!dev)
4534 goto out_unlock;
4535 }
4150c572 4536 b43_wireless_core_exit(dev);
fd4973c5 4537 wl->radio_enabled = 0;
36dbd954
MB		 4538
4539out_unlock:
e4d6b795 4540 mutex_unlock(&wl->mutex);
18c8adeb
MB		 4541
4542 cancel_work_sync(&(wl->txpower_adjust_work));
e4d6b795
MB		 4543}
4544
17741cdc
JB		 4545static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4546 struct ieee80211_sta *sta, bool set)
e66fee6a
MB		 4547{
4548 struct b43_wl *wl = hw_to_b43_wl(hw);
4549
8f611288 4550 /* FIXME: add locking */
9d139c81 4551 b43_update_templates(wl);
e66fee6a
MB		 4552
4553 return 0;
4554}
4555
38968d09
JB		 4556static void b43_op_sta_notify(struct ieee80211_hw *hw,
4557 struct ieee80211_vif *vif,
4558 enum sta_notify_cmd notify_cmd,
17741cdc 4559 struct ieee80211_sta *sta)
38968d09
JB		 4560{
4561 struct b43_wl *wl = hw_to_b43_wl(hw);
4562
4563 B43_WARN_ON(!vif || wl->vif != vif);
4564}
4565
25d3ef59
MB		 4566static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4567{
4568 struct b43_wl *wl = hw_to_b43_wl(hw);
4569 struct b43_wldev *dev;
4570
4571 mutex_lock(&wl->mutex);
4572 dev = wl->current_dev;
4573 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4574 /* Disable CFP update during scan on other channels. */
4575 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4576 }
4577 mutex_unlock(&wl->mutex);
4578}
4579
4580static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4581{
4582 struct b43_wl *wl = hw_to_b43_wl(hw);
4583 struct b43_wldev *dev;
4584
4585 mutex_lock(&wl->mutex);
4586 dev = wl->current_dev;
4587 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4588 /* Re-enable CFP update. */
4589 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4590 }
4591 mutex_unlock(&wl->mutex);
4592}
4593
e4d6b795 4594static const struct ieee80211_ops b43_hw_ops = {
40faacc4
MB		 4595 .tx = b43_op_tx,
4596 .conf_tx = b43_op_conf_tx,
4597 .add_interface = b43_op_add_interface,
4598 .remove_interface = b43_op_remove_interface,
4599 .config = b43_op_config,
c7ab5ef9 4600 .bss_info_changed = b43_op_bss_info_changed,
40faacc4
MB		 4601 .configure_filter = b43_op_configure_filter,
4602 .set_key = b43_op_set_key,
035d0243 4603 .update_tkip_key = b43_op_update_tkip_key,
40faacc4
MB		 4604 .get_stats = b43_op_get_stats,
4605 .get_tx_stats = b43_op_get_tx_stats,
08e87a83
AF		 4606 .get_tsf = b43_op_get_tsf,
4607 .set_tsf = b43_op_set_tsf,
40faacc4
MB		 4608 .start = b43_op_start,
4609 .stop = b43_op_stop,
e66fee6a 4610 .set_tim = b43_op_beacon_set_tim,
38968d09 4611 .sta_notify = b43_op_sta_notify,
25d3ef59
MB		 4612 .sw_scan_start = b43_op_sw_scan_start_notifier,
4613 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
f41f3f37 4614 .rfkill_poll = b43_rfkill_poll,
e4d6b795
MB		 4615};
4616
4617/* Hard-reset the chip. Do not call this directly.
4618 * Use b43_controller_restart()
4619 */
4620static void b43_chip_reset(struct work_struct *work)
4621{
4622 struct b43_wldev *dev =
4623 container_of(work, struct b43_wldev, restart_work);
4624 struct b43_wl *wl = dev->wl;
4625 int err = 0;
4626 int prev_status;
4627
4628 mutex_lock(&wl->mutex);
4629
4630 prev_status = b43_status(dev);
4631 /* Bring the device down... */
36dbd954
MB		 4632 if (prev_status >= B43_STAT_STARTED) {
4633 dev = b43_wireless_core_stop(dev);
4634 if (!dev) {
4635 err = -ENODEV;
4636 goto out;
4637 }
4638 }
e4d6b795
MB		 4639 if (prev_status >= B43_STAT_INITIALIZED)
4640 b43_wireless_core_exit(dev);
4641
4642 /* ...and up again. */
4643 if (prev_status >= B43_STAT_INITIALIZED) {
4644 err = b43_wireless_core_init(dev);
4645 if (err)
4646 goto out;
4647 }
4648 if (prev_status >= B43_STAT_STARTED) {
4649 err = b43_wireless_core_start(dev);
4650 if (err) {
4651 b43_wireless_core_exit(dev);
4652 goto out;
4653 }
4654 }
3bf0a32e
MB		 4655out:
4656 if (err)
4657 wl->current_dev = NULL; /* Failed to init the dev. */
e4d6b795
MB		 4658 mutex_unlock(&wl->mutex);
4659 if (err)
4660 b43err(wl, "Controller restart FAILED\n");
4661 else
4662 b43info(wl, "Controller restarted\n");
4663}
4664
bb1eeff1 4665static int b43_setup_bands(struct b43_wldev *dev,
96c755a3 4666 bool have_2ghz_phy, bool have_5ghz_phy)
e4d6b795
MB		 4667{
4668 struct ieee80211_hw *hw = dev->wl->hw;
e4d6b795 4669
bb1eeff1
MB		 4670 if (have_2ghz_phy)
4671 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4672 if (dev->phy.type == B43_PHYTYPE_N) {
4673 if (have_5ghz_phy)
4674 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4675 } else {
4676 if (have_5ghz_phy)
4677 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4678 }
96c755a3 4679
bb1eeff1
MB		 4680 dev->phy.supports_2ghz = have_2ghz_phy;
4681 dev->phy.supports_5ghz = have_5ghz_phy;
e4d6b795
MB		 4682
4683 return 0;
4684}
4685
4686static void b43_wireless_core_detach(struct b43_wldev *dev)
4687{
4688 /* We release firmware that late to not be required to re-request
4689 * is all the time when we reinit the core. */
4690 b43_release_firmware(dev);
fb11137a 4691 b43_phy_free(dev);
e4d6b795
MB		 4692}
4693
4694static int b43_wireless_core_attach(struct b43_wldev *dev)
4695{
4696 struct b43_wl *wl = dev->wl;
4697 struct ssb_bus *bus = dev->dev->bus;
899110fe 4698 struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
e4d6b795 4699 int err;
96c755a3 4700 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
e4d6b795
MB		 4701 u32 tmp;
4702
4703 /* Do NOT do any device initialization here.
4704 * Do it in wireless_core_init() instead.
4705 * This function is for gathering basic information about the HW, only.
4706 * Also some structs may be set up here. But most likely you want to have
4707 * that in core_init(), too.
4708 */
4709
4710 err = ssb_bus_powerup(bus, 0);
4711 if (err) {
4712 b43err(wl, "Bus powerup failed\n");
4713 goto out;
4714 }
4715 /* Get the PHY type. */
4716 if (dev->dev->id.revision >= 5) {
4717 u32 tmshigh;
4718
4719 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
96c755a3
MB		 4720 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4721 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
e4d6b795 4722 } else
96c755a3 4723 B43_WARN_ON(1);
e4d6b795 4724
96c755a3 4725 dev->phy.gmode = have_2ghz_phy;
fd4973c5 4726 dev->phy.radio_on = 1;
e4d6b795
MB		 4727 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4728 b43_wireless_core_reset(dev, tmp);
4729
4730 err = b43_phy_versioning(dev);
4731 if (err)
21954c36 4732 goto err_powerdown;
e4d6b795
MB		 4733 /* Check if this device supports multiband. */
4734 if (!pdev ||
4735 (pdev->device != 0x4312 &&
4736 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4737 /* No multiband support. */
96c755a3
MB		 4738 have_2ghz_phy = 0;
4739 have_5ghz_phy = 0;
e4d6b795
MB		 4740 switch (dev->phy.type) {
4741 case B43_PHYTYPE_A:
96c755a3 4742 have_5ghz_phy = 1;
e4d6b795 4743 break;
9d86a2d5 4744 case B43_PHYTYPE_LP: //FIXME not always!
86b2892a 4745#if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
9d86a2d5 4746 have_5ghz_phy = 1;
86b2892a 4747#endif
e4d6b795 4748 case B43_PHYTYPE_G:
96c755a3
MB		 4749 case B43_PHYTYPE_N:
4750 have_2ghz_phy = 1;
e4d6b795
MB		 4751 break;
4752 default:
4753 B43_WARN_ON(1);
4754 }
4755 }
96c755a3
MB		 4756 if (dev->phy.type == B43_PHYTYPE_A) {
4757 /* FIXME */
4758 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4759 err = -EOPNOTSUPP;
4760 goto err_powerdown;
4761 }
2e35af14
MB		 4762 if (1 /* disable A-PHY */) {
4763 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
9d86a2d5
GS		 4764 if (dev->phy.type != B43_PHYTYPE_N &&
4765 dev->phy.type != B43_PHYTYPE_LP) {
2e35af14
MB		 4766 have_2ghz_phy = 1;
4767 have_5ghz_phy = 0;
4768 }
4769 }
4770
fb11137a
MB		 4771 err = b43_phy_allocate(dev);
4772 if (err)
4773 goto err_powerdown;
4774
96c755a3 4775 dev->phy.gmode = have_2ghz_phy;
e4d6b795
MB		 4776 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4777 b43_wireless_core_reset(dev, tmp);
4778
4779 err = b43_validate_chipaccess(dev);
4780 if (err)
fb11137a 4781 goto err_phy_free;
bb1eeff1 4782 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
e4d6b795 4783 if (err)
fb11137a 4784 goto err_phy_free;
e4d6b795
MB		 4785
4786 /* Now set some default "current_dev" */
4787 if (!wl->current_dev)
4788 wl->current_dev = dev;
4789 INIT_WORK(&dev->restart_work, b43_chip_reset);
4790
cb24f57f 4791 dev->phy.ops->switch_analog(dev, 0);
e4d6b795
MB		 4792 ssb_device_disable(dev->dev, 0);
4793 ssb_bus_may_powerdown(bus);
4794
4795out:
4796 return err;
4797
fb11137a
MB		 4798err_phy_free:
4799 b43_phy_free(dev);
e4d6b795
MB		 4800err_powerdown:
4801 ssb_bus_may_powerdown(bus);
4802 return err;
4803}
4804
4805static void b43_one_core_detach(struct ssb_device *dev)
4806{
4807 struct b43_wldev *wldev;
4808 struct b43_wl *wl;
4809
3bf0a32e
MB		 4810 /* Do not cancel ieee80211-workqueue based work here.
4811 * See comment in b43_remove(). */
4812
e4d6b795
MB		 4813 wldev = ssb_get_drvdata(dev);
4814 wl = wldev->wl;
e4d6b795
MB		 4815 b43_debugfs_remove_device(wldev);
4816 b43_wireless_core_detach(wldev);
4817 list_del(&wldev->list);
4818 wl->nr_devs--;
4819 ssb_set_drvdata(dev, NULL);
4820 kfree(wldev);
4821}
4822
4823static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4824{
4825 struct b43_wldev *wldev;
4826 struct pci_dev *pdev;
4827 int err = -ENOMEM;
4828
4829 if (!list_empty(&wl->devlist)) {
4830 /* We are not the first core on this chip. */
899110fe 4831 pdev = (dev->bus->bustype == SSB_BUSTYPE_PCI) ? dev->bus->host_pci : NULL;
e4d6b795
MB		 4832 /* Only special chips support more than one wireless
4833 * core, although some of the other chips have more than
4834 * one wireless core as well. Check for this and
4835 * bail out early.
4836 */
4837 if (!pdev ||
4838 ((pdev->device != 0x4321) &&
4839 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4840 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4841 return -ENODEV;
4842 }
4843 }
4844
4845 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4846 if (!wldev)
4847 goto out;
4848
4849 wldev->dev = dev;
4850 wldev->wl = wl;
4851 b43_set_status(wldev, B43_STAT_UNINIT);
4852 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
e4d6b795
MB		 4853 INIT_LIST_HEAD(&wldev->list);
4854
4855 err = b43_wireless_core_attach(wldev);
4856 if (err)
4857 goto err_kfree_wldev;
4858
4859 list_add(&wldev->list, &wl->devlist);
4860 wl->nr_devs++;
4861 ssb_set_drvdata(dev, wldev);
4862 b43_debugfs_add_device(wldev);
4863
4864 out:
4865 return err;
4866
4867 err_kfree_wldev:
4868 kfree(wldev);
4869 return err;
4870}
4871
9fc38458
MB		 4872#define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4873 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4874 (pdev->device == _device) && \
4875 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4876 (pdev->subsystem_device == _subdevice) )
4877
e4d6b795
MB		 4878static void b43_sprom_fixup(struct ssb_bus *bus)
4879{
1855ba78
MB		 4880 struct pci_dev *pdev;
4881
e4d6b795
MB		 4882 /* boardflags workarounds */
4883 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4884 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
95de2841 4885 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
e4d6b795
MB		 4886 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4887 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
95de2841 4888 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
1855ba78
MB		 4889 if (bus->bustype == SSB_BUSTYPE_PCI) {
4890 pdev = bus->host_pci;
9fc38458 4891 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
430cd47f 4892 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
570bdfb1 4893 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
9fc38458 4894 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
a58d4522 4895 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
3bb91bff
LF		 4896 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4897 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
1855ba78
MB		 4898 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4899 }
e4d6b795
MB		 4900}
4901
4902static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4903{
4904 struct ieee80211_hw *hw = wl->hw;
4905
4906 ssb_set_devtypedata(dev, NULL);
4907 ieee80211_free_hw(hw);
4908}
4909
4910static int b43_wireless_init(struct ssb_device *dev)
4911{
4912 struct ssb_sprom *sprom = &dev->bus->sprom;
4913 struct ieee80211_hw *hw;
4914 struct b43_wl *wl;
4915 int err = -ENOMEM;
4916
4917 b43_sprom_fixup(dev->bus);
4918
4919 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4920 if (!hw) {
4921 b43err(NULL, "Could not allocate ieee80211 device\n");
4922 goto out;
4923 }
403a3a13 4924 wl = hw_to_b43_wl(hw);
e4d6b795
MB		 4925
4926 /* fill hw info */
605a0bd6 4927 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
566bfe5a
BR		 4928 IEEE80211_HW_SIGNAL_DBM |
4929 IEEE80211_HW_NOISE_DBM;
4930
f59ac048
LR		 4931 hw->wiphy->interface_modes =
4932 BIT(NL80211_IFTYPE_AP) |
4933 BIT(NL80211_IFTYPE_MESH_POINT) |
4934 BIT(NL80211_IFTYPE_STATION) |
4935 BIT(NL80211_IFTYPE_WDS) |
4936 BIT(NL80211_IFTYPE_ADHOC);
4937
403a3a13
MB		 4938 hw->queues = modparam_qos ? 4 : 1;
4939 wl->mac80211_initially_registered_queues = hw->queues;
e6a9854b 4940 hw->max_rates = 2;
e4d6b795 4941 SET_IEEE80211_DEV(hw, dev->dev);
95de2841
LF		 4942 if (is_valid_ether_addr(sprom->et1mac))
4943 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
e4d6b795 4944 else
95de2841 4945 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
e4d6b795 4946
403a3a13 4947 /* Initialize struct b43_wl */
e4d6b795 4948 wl->hw = hw;
e4d6b795 4949 mutex_init(&wl->mutex);
36dbd954 4950 spin_lock_init(&wl->hardirq_lock);
e4d6b795 4951 INIT_LIST_HEAD(&wl->devlist);
a82d9922 4952 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
18c8adeb 4953 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
f5d40eed
MB		 4954 INIT_WORK(&wl->tx_work, b43_tx_work);
4955 skb_queue_head_init(&wl->tx_queue);
e4d6b795
MB		 4956
4957 ssb_set_devtypedata(dev, wl);
060210f9
MB		 4958 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4959 dev->bus->chip_id, dev->id.revision);
e4d6b795 4960 err = 0;
060210f9 4961out:
e4d6b795
MB		 4962 return err;
4963}
4964
4965static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4966{
4967 struct b43_wl *wl;
4968 int err;
4969 int first = 0;
4970
4971 wl = ssb_get_devtypedata(dev);
4972 if (!wl) {
4973 /* Probing the first core. Must setup common struct b43_wl */
4974 first = 1;
4975 err = b43_wireless_init(dev);
4976 if (err)
4977 goto out;
4978 wl = ssb_get_devtypedata(dev);
4979 B43_WARN_ON(!wl);
4980 }
4981 err = b43_one_core_attach(dev, wl);
4982 if (err)
4983 goto err_wireless_exit;
4984
4985 if (first) {
4986 err = ieee80211_register_hw(wl->hw);
4987 if (err)
4988 goto err_one_core_detach;
a78b3bb2
MB		 4989 b43_leds_register(wl->current_dev);
4990 b43_rng_init(wl);
e4d6b795
MB		 4991 }
4992
4993 out:
4994 return err;
4995
4996 err_one_core_detach:
4997 b43_one_core_detach(dev);
4998 err_wireless_exit:
4999 if (first)
5000 b43_wireless_exit(dev, wl);
5001 return err;
5002}
5003
5004static void b43_remove(struct ssb_device *dev)
5005{
5006 struct b43_wl *wl = ssb_get_devtypedata(dev);
5007 struct b43_wldev *wldev = ssb_get_drvdata(dev);
5008
3bf0a32e
MB		 5009 /* We must cancel any work here before unregistering from ieee80211,
5010 * as the ieee80211 unreg will destroy the workqueue. */
5011 cancel_work_sync(&wldev->restart_work);
5012
e4d6b795 5013 B43_WARN_ON(!wl);
403a3a13
MB		 5014 if (wl->current_dev == wldev) {
5015 /* Restore the queues count before unregistering, because firmware detect
5016 * might have modified it. Restoring is important, so the networking
5017 * stack can properly free resources. */
5018 wl->hw->queues = wl->mac80211_initially_registered_queues;
82905ace 5019 b43_leds_stop(wldev);
e4d6b795 5020 ieee80211_unregister_hw(wl->hw);
403a3a13 5021 }
e4d6b795
MB		 5022
5023 b43_one_core_detach(dev);
5024
5025 if (list_empty(&wl->devlist)) {
a78b3bb2 5026 b43_rng_exit(wl);
727c9885 5027 b43_leds_unregister(wl);
e4d6b795
MB		 5028 /* Last core on the chip unregistered.
5029 * We can destroy common struct b43_wl.
5030 */
5031 b43_wireless_exit(dev, wl);
5032 }
5033}
5034
5035/* Perform a hardware reset. This can be called from any context. */
5036void b43_controller_restart(struct b43_wldev *dev, const char *reason)
5037{
5038 /* Must avoid requeueing, if we are in shutdown. */
5039 if (b43_status(dev) < B43_STAT_INITIALIZED)
5040 return;
5041 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
42935eca 5042 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
e4d6b795
MB		 5043}
5044
e4d6b795
MB		 5045static struct ssb_driver b43_ssb_driver = {
5046 .name = KBUILD_MODNAME,
5047 .id_table = b43_ssb_tbl,
5048 .probe = b43_probe,
5049 .remove = b43_remove,
e4d6b795
MB		 5050};
5051
26bc783f
MB		 5052static void b43_print_driverinfo(void)
5053{
5054 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
3dbba8e2 5055 *feat_leds = "", *feat_sdio = "";
26bc783f
MB		 5056
5057#ifdef CONFIG_B43_PCI_AUTOSELECT
5058 feat_pci = "P";
5059#endif
5060#ifdef CONFIG_B43_PCMCIA
5061 feat_pcmcia = "M";
5062#endif
5063#ifdef CONFIG_B43_NPHY
5064 feat_nphy = "N";
5065#endif
5066#ifdef CONFIG_B43_LEDS
5067 feat_leds = "L";
3dbba8e2
AH		 5068#endif
5069#ifdef CONFIG_B43_SDIO
5070 feat_sdio = "S";
26bc783f
MB		 5071#endif
5072 printk(KERN_INFO "Broadcom 43xx driver loaded "
3dbba8e2 5073 "[ Features: %s%s%s%s%s, Firmware-ID: "
26bc783f
MB		 5074 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5075 feat_pci, feat_pcmcia, feat_nphy,
3dbba8e2 5076 feat_leds, feat_sdio);
26bc783f
MB		 5077}
5078
e4d6b795
MB		 5079static int __init b43_init(void)
5080{
5081 int err;
5082
5083 b43_debugfs_init();
5084 err = b43_pcmcia_init();
5085 if (err)
5086 goto err_dfs_exit;
3dbba8e2 5087 err = b43_sdio_init();
e4d6b795
MB		 5088 if (err)
5089 goto err_pcmcia_exit;
3dbba8e2
AH		 5090 err = ssb_driver_register(&b43_ssb_driver);
5091 if (err)
5092 goto err_sdio_exit;
26bc783f 5093 b43_print_driverinfo();
e4d6b795
MB		 5094
5095 return err;
5096
3dbba8e2
AH		 5097err_sdio_exit:
5098 b43_sdio_exit();
e4d6b795
MB		 5099err_pcmcia_exit:
5100 b43_pcmcia_exit();
5101err_dfs_exit:
5102 b43_debugfs_exit();
5103 return err;
5104}
5105
5106static void __exit b43_exit(void)
5107{
5108 ssb_driver_unregister(&b43_ssb_driver);
3dbba8e2 5109 b43_sdio_exit();
e4d6b795
MB		 5110 b43_pcmcia_exit();
5111 b43_debugfs_exit();
5112}
5113
5114module_init(b43_init)
5115module_exit(b43_exit)
Clone of davem's net-next-2.6 tree