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Commit | Line | Data |
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f078f209 LR |
1 | /* |
2 | * Copyright (c) 2008 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
394cf0a1 | 17 | #include "ath9k.h" |
f078f209 | 18 | |
bce048d7 JM |
19 | static struct ieee80211_hw * ath_get_virt_hw(struct ath_softc *sc, |
20 | struct ieee80211_hdr *hdr) | |
21 | { | |
c52f33d0 JM |
22 | struct ieee80211_hw *hw = sc->pri_wiphy->hw; |
23 | int i; | |
24 | ||
25 | spin_lock_bh(&sc->wiphy_lock); | |
26 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
27 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
28 | if (aphy == NULL) | |
29 | continue; | |
30 | if (compare_ether_addr(hdr->addr1, aphy->hw->wiphy->perm_addr) | |
31 | == 0) { | |
32 | hw = aphy->hw; | |
33 | break; | |
34 | } | |
35 | } | |
36 | spin_unlock_bh(&sc->wiphy_lock); | |
37 | return hw; | |
bce048d7 JM |
38 | } |
39 | ||
f078f209 LR |
40 | /* |
41 | * Setup and link descriptors. | |
42 | * | |
43 | * 11N: we can no longer afford to self link the last descriptor. | |
44 | * MAC acknowledges BA status as long as it copies frames to host | |
45 | * buffer (or rx fifo). This can incorrectly acknowledge packets | |
46 | * to a sender if last desc is self-linked. | |
f078f209 | 47 | */ |
f078f209 LR |
48 | static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf) |
49 | { | |
cbe61d8a | 50 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
51 | struct ath_desc *ds; |
52 | struct sk_buff *skb; | |
53 | ||
54 | ATH_RXBUF_RESET(bf); | |
55 | ||
56 | ds = bf->bf_desc; | |
be0418ad | 57 | ds->ds_link = 0; /* link to null */ |
f078f209 LR |
58 | ds->ds_data = bf->bf_buf_addr; |
59 | ||
be0418ad | 60 | /* virtual addr of the beginning of the buffer. */ |
f078f209 LR |
61 | skb = bf->bf_mpdu; |
62 | ASSERT(skb != NULL); | |
63 | ds->ds_vdata = skb->data; | |
64 | ||
b77f483f | 65 | /* setup rx descriptors. The rx.bufsize here tells the harware |
b4b6cda2 LR |
66 | * how much data it can DMA to us and that we are prepared |
67 | * to process */ | |
b77f483f S |
68 | ath9k_hw_setuprxdesc(ah, ds, |
69 | sc->rx.bufsize, | |
f078f209 LR |
70 | 0); |
71 | ||
b77f483f | 72 | if (sc->rx.rxlink == NULL) |
f078f209 LR |
73 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
74 | else | |
b77f483f | 75 | *sc->rx.rxlink = bf->bf_daddr; |
f078f209 | 76 | |
b77f483f | 77 | sc->rx.rxlink = &ds->ds_link; |
f078f209 LR |
78 | ath9k_hw_rxena(ah); |
79 | } | |
80 | ||
ff37e337 S |
81 | static void ath_setdefantenna(struct ath_softc *sc, u32 antenna) |
82 | { | |
83 | /* XXX block beacon interrupts */ | |
84 | ath9k_hw_setantenna(sc->sc_ah, antenna); | |
b77f483f S |
85 | sc->rx.defant = antenna; |
86 | sc->rx.rxotherant = 0; | |
ff37e337 S |
87 | } |
88 | ||
89 | /* | |
90 | * Extend 15-bit time stamp from rx descriptor to | |
91 | * a full 64-bit TSF using the current h/w TSF. | |
92 | */ | |
93 | static u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp) | |
94 | { | |
95 | u64 tsf; | |
96 | ||
97 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
98 | if ((tsf & 0x7fff) < rstamp) | |
99 | tsf -= 0x8000; | |
100 | return (tsf & ~0x7fff) | rstamp; | |
101 | } | |
102 | ||
be0418ad | 103 | static struct sk_buff *ath_rxbuf_alloc(struct ath_softc *sc, u32 len) |
f078f209 LR |
104 | { |
105 | struct sk_buff *skb; | |
106 | u32 off; | |
107 | ||
108 | /* | |
109 | * Cache-line-align. This is important (for the | |
110 | * 5210 at least) as not doing so causes bogus data | |
111 | * in rx'd frames. | |
112 | */ | |
113 | ||
b4b6cda2 LR |
114 | /* Note: the kernel can allocate a value greater than |
115 | * what we ask it to give us. We really only need 4 KB as that | |
116 | * is this hardware supports and in fact we need at least 3849 | |
117 | * as that is the MAX AMSDU size this hardware supports. | |
118 | * Unfortunately this means we may get 8 KB here from the | |
119 | * kernel... and that is actually what is observed on some | |
120 | * systems :( */ | |
17d7904d | 121 | skb = dev_alloc_skb(len + sc->cachelsz - 1); |
f078f209 | 122 | if (skb != NULL) { |
17d7904d | 123 | off = ((unsigned long) skb->data) % sc->cachelsz; |
f078f209 | 124 | if (off != 0) |
17d7904d | 125 | skb_reserve(skb, sc->cachelsz - off); |
f078f209 LR |
126 | } else { |
127 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 128 | "skbuff alloc of size %u failed\n", len); |
f078f209 LR |
129 | return NULL; |
130 | } | |
131 | ||
132 | return skb; | |
133 | } | |
134 | ||
f078f209 | 135 | /* |
be0418ad S |
136 | * For Decrypt or Demic errors, we only mark packet status here and always push |
137 | * up the frame up to let mac80211 handle the actual error case, be it no | |
138 | * decryption key or real decryption error. This let us keep statistics there. | |
f078f209 | 139 | */ |
be0418ad S |
140 | static int ath_rx_prepare(struct sk_buff *skb, struct ath_desc *ds, |
141 | struct ieee80211_rx_status *rx_status, bool *decrypt_error, | |
142 | struct ath_softc *sc) | |
f078f209 | 143 | { |
be0418ad | 144 | struct ieee80211_hdr *hdr; |
be0418ad S |
145 | u8 ratecode; |
146 | __le16 fc; | |
bce048d7 | 147 | struct ieee80211_hw *hw; |
be0418ad S |
148 | |
149 | hdr = (struct ieee80211_hdr *)skb->data; | |
150 | fc = hdr->frame_control; | |
151 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); | |
bce048d7 | 152 | hw = ath_get_virt_hw(sc, hdr); |
be0418ad S |
153 | |
154 | if (ds->ds_rxstat.rs_more) { | |
155 | /* | |
156 | * Frame spans multiple descriptors; this cannot happen yet | |
157 | * as we don't support jumbograms. If not in monitor mode, | |
158 | * discard the frame. Enable this if you want to see | |
159 | * error frames in Monitor mode. | |
160 | */ | |
2660b81a | 161 | if (sc->sc_ah->opmode != NL80211_IFTYPE_MONITOR) |
be0418ad S |
162 | goto rx_next; |
163 | } else if (ds->ds_rxstat.rs_status != 0) { | |
164 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_CRC) | |
165 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; | |
166 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_PHY) | |
167 | goto rx_next; | |
f078f209 | 168 | |
be0418ad S |
169 | if (ds->ds_rxstat.rs_status & ATH9K_RXERR_DECRYPT) { |
170 | *decrypt_error = true; | |
171 | } else if (ds->ds_rxstat.rs_status & ATH9K_RXERR_MIC) { | |
172 | if (ieee80211_is_ctl(fc)) | |
173 | /* | |
174 | * Sometimes, we get invalid | |
175 | * MIC failures on valid control frames. | |
176 | * Remove these mic errors. | |
177 | */ | |
178 | ds->ds_rxstat.rs_status &= ~ATH9K_RXERR_MIC; | |
179 | else | |
180 | rx_status->flag |= RX_FLAG_MMIC_ERROR; | |
181 | } | |
182 | /* | |
183 | * Reject error frames with the exception of | |
184 | * decryption and MIC failures. For monitor mode, | |
185 | * we also ignore the CRC error. | |
186 | */ | |
2660b81a | 187 | if (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR) { |
be0418ad S |
188 | if (ds->ds_rxstat.rs_status & |
189 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC | | |
190 | ATH9K_RXERR_CRC)) | |
191 | goto rx_next; | |
192 | } else { | |
193 | if (ds->ds_rxstat.rs_status & | |
194 | ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) { | |
195 | goto rx_next; | |
196 | } | |
197 | } | |
f078f209 LR |
198 | } |
199 | ||
be0418ad | 200 | ratecode = ds->ds_rxstat.rs_rate; |
be0418ad | 201 | |
be0418ad | 202 | if (ratecode & 0x80) { |
baad1d92 JM |
203 | /* HT rate */ |
204 | rx_status->flag |= RX_FLAG_HT; | |
be0418ad | 205 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_2040) |
baad1d92 | 206 | rx_status->flag |= RX_FLAG_40MHZ; |
be0418ad | 207 | if (ds->ds_rxstat.rs_flags & ATH9K_RX_GI) |
baad1d92 JM |
208 | rx_status->flag |= RX_FLAG_SHORT_GI; |
209 | rx_status->rate_idx = ratecode & 0x7f; | |
210 | } else { | |
211 | int i = 0, cur_band, n_rates; | |
baad1d92 JM |
212 | |
213 | cur_band = hw->conf.channel->band; | |
214 | n_rates = sc->sbands[cur_band].n_bitrates; | |
215 | ||
216 | for (i = 0; i < n_rates; i++) { | |
217 | if (sc->sbands[cur_band].bitrates[i].hw_value == | |
218 | ratecode) { | |
219 | rx_status->rate_idx = i; | |
220 | break; | |
221 | } | |
222 | ||
223 | if (sc->sbands[cur_band].bitrates[i].hw_value_short == | |
224 | ratecode) { | |
225 | rx_status->rate_idx = i; | |
226 | rx_status->flag |= RX_FLAG_SHORTPRE; | |
227 | break; | |
228 | } | |
229 | } | |
be0418ad S |
230 | } |
231 | ||
232 | rx_status->mactime = ath_extend_tsf(sc, ds->ds_rxstat.rs_tstamp); | |
bce048d7 JM |
233 | rx_status->band = hw->conf.channel->band; |
234 | rx_status->freq = hw->conf.channel->center_freq; | |
17d7904d | 235 | rx_status->noise = sc->ani.noise_floor; |
be0418ad | 236 | rx_status->signal = rx_status->noise + ds->ds_rxstat.rs_rssi; |
be0418ad S |
237 | rx_status->antenna = ds->ds_rxstat.rs_antenna; |
238 | ||
239 | /* at 45 you will be able to use MCS 15 reliably. A more elaborate | |
240 | * scheme can be used here but it requires tables of SNR/throughput for | |
241 | * each possible mode used. */ | |
242 | rx_status->qual = ds->ds_rxstat.rs_rssi * 100 / 45; | |
243 | ||
244 | /* rssi can be more than 45 though, anything above that | |
245 | * should be considered at 100% */ | |
246 | if (rx_status->qual > 100) | |
247 | rx_status->qual = 100; | |
248 | ||
249 | rx_status->flag |= RX_FLAG_TSFT; | |
250 | ||
251 | return 1; | |
252 | rx_next: | |
253 | return 0; | |
f078f209 LR |
254 | } |
255 | ||
256 | static void ath_opmode_init(struct ath_softc *sc) | |
257 | { | |
cbe61d8a | 258 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
259 | u32 rfilt, mfilt[2]; |
260 | ||
261 | /* configure rx filter */ | |
262 | rfilt = ath_calcrxfilter(sc); | |
263 | ath9k_hw_setrxfilter(ah, rfilt); | |
264 | ||
265 | /* configure bssid mask */ | |
2660b81a | 266 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
ba52da58 | 267 | ath9k_hw_setbssidmask(sc); |
f078f209 LR |
268 | |
269 | /* configure operational mode */ | |
270 | ath9k_hw_setopmode(ah); | |
271 | ||
272 | /* Handle any link-level address change. */ | |
ba52da58 | 273 | ath9k_hw_setmac(ah, sc->sc_ah->macaddr); |
f078f209 LR |
274 | |
275 | /* calculate and install multicast filter */ | |
276 | mfilt[0] = mfilt[1] = ~0; | |
f078f209 | 277 | ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]); |
f078f209 LR |
278 | } |
279 | ||
280 | int ath_rx_init(struct ath_softc *sc, int nbufs) | |
281 | { | |
282 | struct sk_buff *skb; | |
283 | struct ath_buf *bf; | |
284 | int error = 0; | |
285 | ||
286 | do { | |
b77f483f | 287 | spin_lock_init(&sc->rx.rxflushlock); |
98deeea0 | 288 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 289 | spin_lock_init(&sc->rx.rxbuflock); |
f078f209 | 290 | |
b77f483f | 291 | sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, |
17d7904d | 292 | min(sc->cachelsz, |
f078f209 LR |
293 | (u16)64)); |
294 | ||
04bd4638 | 295 | DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", |
17d7904d | 296 | sc->cachelsz, sc->rx.bufsize); |
f078f209 LR |
297 | |
298 | /* Initialize rx descriptors */ | |
299 | ||
b77f483f | 300 | error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, |
f078f209 LR |
301 | "rx", nbufs, 1); |
302 | if (error != 0) { | |
303 | DPRINTF(sc, ATH_DBG_FATAL, | |
04bd4638 | 304 | "failed to allocate rx descriptors: %d\n", error); |
f078f209 LR |
305 | break; |
306 | } | |
307 | ||
b77f483f S |
308 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
309 | skb = ath_rxbuf_alloc(sc, sc->rx.bufsize); | |
f078f209 LR |
310 | if (skb == NULL) { |
311 | error = -ENOMEM; | |
312 | break; | |
313 | } | |
314 | ||
315 | bf->bf_mpdu = skb; | |
7da3c55c | 316 | bf->bf_buf_addr = dma_map_single(sc->dev, skb->data, |
b77f483f | 317 | sc->rx.bufsize, |
7da3c55c GJ |
318 | DMA_FROM_DEVICE); |
319 | if (unlikely(dma_mapping_error(sc->dev, | |
f8316df1 LR |
320 | bf->bf_buf_addr))) { |
321 | dev_kfree_skb_any(skb); | |
322 | bf->bf_mpdu = NULL; | |
323 | DPRINTF(sc, ATH_DBG_CONFIG, | |
7da3c55c | 324 | "dma_mapping_error() on RX init\n"); |
f8316df1 LR |
325 | error = -ENOMEM; |
326 | break; | |
327 | } | |
927e70e9 | 328 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 | 329 | } |
b77f483f | 330 | sc->rx.rxlink = NULL; |
f078f209 LR |
331 | |
332 | } while (0); | |
333 | ||
334 | if (error) | |
335 | ath_rx_cleanup(sc); | |
336 | ||
337 | return error; | |
338 | } | |
339 | ||
f078f209 LR |
340 | void ath_rx_cleanup(struct ath_softc *sc) |
341 | { | |
342 | struct sk_buff *skb; | |
343 | struct ath_buf *bf; | |
344 | ||
b77f483f | 345 | list_for_each_entry(bf, &sc->rx.rxbuf, list) { |
f078f209 LR |
346 | skb = bf->bf_mpdu; |
347 | if (skb) | |
348 | dev_kfree_skb(skb); | |
349 | } | |
350 | ||
b77f483f S |
351 | if (sc->rx.rxdma.dd_desc_len != 0) |
352 | ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf); | |
f078f209 LR |
353 | } |
354 | ||
355 | /* | |
356 | * Calculate the receive filter according to the | |
357 | * operating mode and state: | |
358 | * | |
359 | * o always accept unicast, broadcast, and multicast traffic | |
360 | * o maintain current state of phy error reception (the hal | |
361 | * may enable phy error frames for noise immunity work) | |
362 | * o probe request frames are accepted only when operating in | |
363 | * hostap, adhoc, or monitor modes | |
364 | * o enable promiscuous mode according to the interface state | |
365 | * o accept beacons: | |
366 | * - when operating in adhoc mode so the 802.11 layer creates | |
367 | * node table entries for peers, | |
368 | * - when operating in station mode for collecting rssi data when | |
369 | * the station is otherwise quiet, or | |
370 | * - when operating as a repeater so we see repeater-sta beacons | |
371 | * - when scanning | |
372 | */ | |
373 | ||
374 | u32 ath_calcrxfilter(struct ath_softc *sc) | |
375 | { | |
376 | #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR) | |
7dcfdcd9 | 377 | |
f078f209 LR |
378 | u32 rfilt; |
379 | ||
380 | rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE) | |
381 | | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST | |
382 | | ATH9K_RX_FILTER_MCAST; | |
383 | ||
384 | /* If not a STA, enable processing of Probe Requests */ | |
2660b81a | 385 | if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION) |
f078f209 LR |
386 | rfilt |= ATH9K_RX_FILTER_PROBEREQ; |
387 | ||
388 | /* Can't set HOSTAP into promiscous mode */ | |
2660b81a | 389 | if (((sc->sc_ah->opmode != NL80211_IFTYPE_AP) && |
b77f483f | 390 | (sc->rx.rxfilter & FIF_PROMISC_IN_BSS)) || |
2660b81a | 391 | (sc->sc_ah->opmode == NL80211_IFTYPE_MONITOR)) { |
f078f209 LR |
392 | rfilt |= ATH9K_RX_FILTER_PROM; |
393 | /* ??? To prevent from sending ACK */ | |
394 | rfilt &= ~ATH9K_RX_FILTER_UCAST; | |
395 | } | |
396 | ||
d42c6b71 S |
397 | if (sc->rx.rxfilter & FIF_CONTROL) |
398 | rfilt |= ATH9K_RX_FILTER_CONTROL; | |
399 | ||
dbaaa147 VT |
400 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) && |
401 | !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)) | |
402 | rfilt |= ATH9K_RX_FILTER_MYBEACON; | |
403 | else | |
f078f209 LR |
404 | rfilt |= ATH9K_RX_FILTER_BEACON; |
405 | ||
dbaaa147 | 406 | /* If in HOSTAP mode, want to enable reception of PSPOLL frames */ |
2660b81a | 407 | if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) |
dbaaa147 | 408 | rfilt |= ATH9K_RX_FILTER_PSPOLL; |
be0418ad | 409 | |
f078f209 | 410 | return rfilt; |
7dcfdcd9 | 411 | |
f078f209 LR |
412 | #undef RX_FILTER_PRESERVE |
413 | } | |
414 | ||
f078f209 LR |
415 | int ath_startrecv(struct ath_softc *sc) |
416 | { | |
cbe61d8a | 417 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
418 | struct ath_buf *bf, *tbf; |
419 | ||
b77f483f S |
420 | spin_lock_bh(&sc->rx.rxbuflock); |
421 | if (list_empty(&sc->rx.rxbuf)) | |
f078f209 LR |
422 | goto start_recv; |
423 | ||
b77f483f S |
424 | sc->rx.rxlink = NULL; |
425 | list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) { | |
f078f209 LR |
426 | ath_rx_buf_link(sc, bf); |
427 | } | |
428 | ||
429 | /* We could have deleted elements so the list may be empty now */ | |
b77f483f | 430 | if (list_empty(&sc->rx.rxbuf)) |
f078f209 LR |
431 | goto start_recv; |
432 | ||
b77f483f | 433 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 434 | ath9k_hw_putrxbuf(ah, bf->bf_daddr); |
be0418ad | 435 | ath9k_hw_rxena(ah); |
f078f209 LR |
436 | |
437 | start_recv: | |
b77f483f | 438 | spin_unlock_bh(&sc->rx.rxbuflock); |
be0418ad S |
439 | ath_opmode_init(sc); |
440 | ath9k_hw_startpcureceive(ah); | |
441 | ||
f078f209 LR |
442 | return 0; |
443 | } | |
444 | ||
f078f209 LR |
445 | bool ath_stoprecv(struct ath_softc *sc) |
446 | { | |
cbe61d8a | 447 | struct ath_hw *ah = sc->sc_ah; |
f078f209 LR |
448 | bool stopped; |
449 | ||
be0418ad S |
450 | ath9k_hw_stoppcurecv(ah); |
451 | ath9k_hw_setrxfilter(ah, 0); | |
452 | stopped = ath9k_hw_stopdmarecv(ah); | |
b77f483f | 453 | sc->rx.rxlink = NULL; |
be0418ad | 454 | |
f078f209 LR |
455 | return stopped; |
456 | } | |
457 | ||
f078f209 LR |
458 | void ath_flushrecv(struct ath_softc *sc) |
459 | { | |
b77f483f | 460 | spin_lock_bh(&sc->rx.rxflushlock); |
98deeea0 | 461 | sc->sc_flags |= SC_OP_RXFLUSH; |
f078f209 | 462 | ath_rx_tasklet(sc, 1); |
98deeea0 | 463 | sc->sc_flags &= ~SC_OP_RXFLUSH; |
b77f483f | 464 | spin_unlock_bh(&sc->rx.rxflushlock); |
f078f209 LR |
465 | } |
466 | ||
f078f209 LR |
467 | int ath_rx_tasklet(struct ath_softc *sc, int flush) |
468 | { | |
469 | #define PA2DESC(_sc, _pa) \ | |
b77f483f S |
470 | ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \ |
471 | ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr))) | |
f078f209 | 472 | |
be0418ad | 473 | struct ath_buf *bf; |
f078f209 | 474 | struct ath_desc *ds; |
cb71d9ba | 475 | struct sk_buff *skb = NULL, *requeue_skb; |
be0418ad | 476 | struct ieee80211_rx_status rx_status; |
cbe61d8a | 477 | struct ath_hw *ah = sc->sc_ah; |
be0418ad S |
478 | struct ieee80211_hdr *hdr; |
479 | int hdrlen, padsize, retval; | |
480 | bool decrypt_error = false; | |
481 | u8 keyix; | |
482 | ||
b77f483f | 483 | spin_lock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
484 | |
485 | do { | |
486 | /* If handling rx interrupt and flush is in progress => exit */ | |
98deeea0 | 487 | if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0)) |
f078f209 LR |
488 | break; |
489 | ||
b77f483f S |
490 | if (list_empty(&sc->rx.rxbuf)) { |
491 | sc->rx.rxlink = NULL; | |
f078f209 LR |
492 | break; |
493 | } | |
494 | ||
b77f483f | 495 | bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list); |
f078f209 | 496 | ds = bf->bf_desc; |
f078f209 LR |
497 | |
498 | /* | |
499 | * Must provide the virtual address of the current | |
500 | * descriptor, the physical address, and the virtual | |
501 | * address of the next descriptor in the h/w chain. | |
502 | * This allows the HAL to look ahead to see if the | |
503 | * hardware is done with a descriptor by checking the | |
504 | * done bit in the following descriptor and the address | |
505 | * of the current descriptor the DMA engine is working | |
506 | * on. All this is necessary because of our use of | |
507 | * a self-linked list to avoid rx overruns. | |
508 | */ | |
be0418ad | 509 | retval = ath9k_hw_rxprocdesc(ah, ds, |
f078f209 LR |
510 | bf->bf_daddr, |
511 | PA2DESC(sc, ds->ds_link), | |
512 | 0); | |
513 | if (retval == -EINPROGRESS) { | |
514 | struct ath_buf *tbf; | |
515 | struct ath_desc *tds; | |
516 | ||
b77f483f S |
517 | if (list_is_last(&bf->list, &sc->rx.rxbuf)) { |
518 | sc->rx.rxlink = NULL; | |
f078f209 LR |
519 | break; |
520 | } | |
521 | ||
522 | tbf = list_entry(bf->list.next, struct ath_buf, list); | |
523 | ||
524 | /* | |
525 | * On some hardware the descriptor status words could | |
526 | * get corrupted, including the done bit. Because of | |
527 | * this, check if the next descriptor's done bit is | |
528 | * set or not. | |
529 | * | |
530 | * If the next descriptor's done bit is set, the current | |
531 | * descriptor has been corrupted. Force s/w to discard | |
532 | * this descriptor and continue... | |
533 | */ | |
534 | ||
535 | tds = tbf->bf_desc; | |
be0418ad S |
536 | retval = ath9k_hw_rxprocdesc(ah, tds, tbf->bf_daddr, |
537 | PA2DESC(sc, tds->ds_link), 0); | |
f078f209 | 538 | if (retval == -EINPROGRESS) { |
f078f209 LR |
539 | break; |
540 | } | |
541 | } | |
542 | ||
f078f209 | 543 | skb = bf->bf_mpdu; |
be0418ad | 544 | if (!skb) |
f078f209 | 545 | continue; |
f078f209 | 546 | |
9bf9fca8 VT |
547 | /* |
548 | * Synchronize the DMA transfer with CPU before | |
549 | * 1. accessing the frame | |
550 | * 2. requeueing the same buffer to h/w | |
551 | */ | |
7da3c55c | 552 | dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr, |
9bf9fca8 | 553 | sc->rx.bufsize, |
7da3c55c | 554 | DMA_FROM_DEVICE); |
9bf9fca8 | 555 | |
f078f209 | 556 | /* |
be0418ad S |
557 | * If we're asked to flush receive queue, directly |
558 | * chain it back at the queue without processing it. | |
f078f209 | 559 | */ |
be0418ad | 560 | if (flush) |
cb71d9ba | 561 | goto requeue; |
f078f209 | 562 | |
be0418ad | 563 | if (!ds->ds_rxstat.rs_datalen) |
cb71d9ba | 564 | goto requeue; |
f078f209 | 565 | |
be0418ad | 566 | /* The status portion of the descriptor could get corrupted. */ |
b77f483f | 567 | if (sc->rx.bufsize < ds->ds_rxstat.rs_datalen) |
cb71d9ba | 568 | goto requeue; |
f078f209 | 569 | |
be0418ad | 570 | if (!ath_rx_prepare(skb, ds, &rx_status, &decrypt_error, sc)) |
cb71d9ba LR |
571 | goto requeue; |
572 | ||
573 | /* Ensure we always have an skb to requeue once we are done | |
574 | * processing the current buffer's skb */ | |
b77f483f | 575 | requeue_skb = ath_rxbuf_alloc(sc, sc->rx.bufsize); |
cb71d9ba LR |
576 | |
577 | /* If there is no memory we ignore the current RX'd frame, | |
578 | * tell hardware it can give us a new frame using the old | |
b77f483f | 579 | * skb and put it at the tail of the sc->rx.rxbuf list for |
cb71d9ba LR |
580 | * processing. */ |
581 | if (!requeue_skb) | |
582 | goto requeue; | |
f078f209 | 583 | |
9bf9fca8 | 584 | /* Unmap the frame */ |
7da3c55c | 585 | dma_unmap_single(sc->dev, bf->bf_buf_addr, |
b77f483f | 586 | sc->rx.bufsize, |
7da3c55c | 587 | DMA_FROM_DEVICE); |
f078f209 | 588 | |
be0418ad S |
589 | skb_put(skb, ds->ds_rxstat.rs_datalen); |
590 | skb->protocol = cpu_to_be16(ETH_P_CONTROL); | |
591 | ||
592 | /* see if any padding is done by the hw and remove it */ | |
593 | hdr = (struct ieee80211_hdr *)skb->data; | |
594 | hdrlen = ieee80211_get_hdrlen_from_skb(skb); | |
595 | ||
9c5f89b3 JM |
596 | /* The MAC header is padded to have 32-bit boundary if the |
597 | * packet payload is non-zero. The general calculation for | |
598 | * padsize would take into account odd header lengths: | |
599 | * padsize = (4 - hdrlen % 4) % 4; However, since only | |
600 | * even-length headers are used, padding can only be 0 or 2 | |
601 | * bytes and we can optimize this a bit. In addition, we must | |
602 | * not try to remove padding from short control frames that do | |
603 | * not have payload. */ | |
604 | padsize = hdrlen & 3; | |
605 | if (padsize && hdrlen >= 24) { | |
be0418ad S |
606 | memmove(skb->data + padsize, skb->data, hdrlen); |
607 | skb_pull(skb, padsize); | |
f078f209 LR |
608 | } |
609 | ||
be0418ad | 610 | keyix = ds->ds_rxstat.rs_keyix; |
f078f209 | 611 | |
be0418ad S |
612 | if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error) { |
613 | rx_status.flag |= RX_FLAG_DECRYPTED; | |
614 | } else if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) | |
615 | && !decrypt_error && skb->len >= hdrlen + 4) { | |
616 | keyix = skb->data[hdrlen + 3] >> 6; | |
617 | ||
17d7904d | 618 | if (test_bit(keyix, sc->keymap)) |
be0418ad S |
619 | rx_status.flag |= RX_FLAG_DECRYPTED; |
620 | } | |
0ced0e17 JM |
621 | if (ah->sw_mgmt_crypto && |
622 | (rx_status.flag & RX_FLAG_DECRYPTED) && | |
623 | ieee80211_is_mgmt(hdr->frame_control)) { | |
624 | /* Use software decrypt for management frames. */ | |
625 | rx_status.flag &= ~RX_FLAG_DECRYPTED; | |
626 | } | |
be0418ad S |
627 | |
628 | /* Send the frame to mac80211 */ | |
c52f33d0 JM |
629 | if (hdr->addr1[5] & 0x01) { |
630 | int i; | |
631 | /* | |
632 | * Deliver broadcast/multicast frames to all suitable | |
633 | * virtual wiphys. | |
634 | */ | |
635 | /* TODO: filter based on channel configuration */ | |
636 | for (i = 0; i < sc->num_sec_wiphy; i++) { | |
637 | struct ath_wiphy *aphy = sc->sec_wiphy[i]; | |
638 | struct sk_buff *nskb; | |
639 | if (aphy == NULL) | |
640 | continue; | |
641 | nskb = skb_copy(skb, GFP_ATOMIC); | |
642 | if (nskb) | |
643 | __ieee80211_rx(aphy->hw, nskb, | |
644 | &rx_status); | |
645 | } | |
646 | __ieee80211_rx(sc->hw, skb, &rx_status); | |
647 | } else { | |
648 | /* Deliver unicast frames based on receiver address */ | |
649 | __ieee80211_rx(ath_get_virt_hw(sc, hdr), skb, | |
650 | &rx_status); | |
651 | } | |
cb71d9ba LR |
652 | |
653 | /* We will now give hardware our shiny new allocated skb */ | |
654 | bf->bf_mpdu = requeue_skb; | |
7da3c55c | 655 | bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data, |
b77f483f | 656 | sc->rx.bufsize, |
7da3c55c GJ |
657 | DMA_FROM_DEVICE); |
658 | if (unlikely(dma_mapping_error(sc->dev, | |
f8316df1 LR |
659 | bf->bf_buf_addr))) { |
660 | dev_kfree_skb_any(requeue_skb); | |
661 | bf->bf_mpdu = NULL; | |
662 | DPRINTF(sc, ATH_DBG_CONFIG, | |
7da3c55c | 663 | "dma_mapping_error() on RX\n"); |
f8316df1 LR |
664 | break; |
665 | } | |
cb71d9ba | 666 | bf->bf_dmacontext = bf->bf_buf_addr; |
f078f209 LR |
667 | |
668 | /* | |
669 | * change the default rx antenna if rx diversity chooses the | |
670 | * other antenna 3 times in a row. | |
671 | */ | |
b77f483f S |
672 | if (sc->rx.defant != ds->ds_rxstat.rs_antenna) { |
673 | if (++sc->rx.rxotherant >= 3) | |
be0418ad | 674 | ath_setdefantenna(sc, ds->ds_rxstat.rs_antenna); |
f078f209 | 675 | } else { |
b77f483f | 676 | sc->rx.rxotherant = 0; |
f078f209 | 677 | } |
3cbb5dd7 VN |
678 | |
679 | if (ieee80211_is_beacon(hdr->frame_control) && | |
680 | (sc->sc_flags & SC_OP_WAIT_FOR_BEACON)) { | |
681 | sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON; | |
682 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); | |
683 | } | |
cb71d9ba | 684 | requeue: |
b77f483f | 685 | list_move_tail(&bf->list, &sc->rx.rxbuf); |
cb71d9ba | 686 | ath_rx_buf_link(sc, bf); |
be0418ad S |
687 | } while (1); |
688 | ||
b77f483f | 689 | spin_unlock_bh(&sc->rx.rxbuflock); |
f078f209 LR |
690 | |
691 | return 0; | |
692 | #undef PA2DESC | |
693 | } |