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[net-next-2.6.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f
JS		 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65/******************\
66* Internal defines *
67\******************/
68
69/* Module info */
70MODULE_AUTHOR("Jiri Slaby");
71MODULE_AUTHOR("Nick Kossifidis");
72MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74MODULE_LICENSE("Dual BSD/GPL");
400ec45a 75MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 76
77
78/* Known PCI ids */
79static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
fa1c114f
JS		 97 { 0 }
98};
99MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
100
101/* Known SREVs */
102static struct ath5k_srev_name srev_names[] = {
103 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
104 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
105 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
106 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
107 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
108 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
109 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
110 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
bb0c9dc2
NK		 111 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
112 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
fa1c114f
JS		 113 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
114 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
115 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
116 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
117 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
118 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
136bfc79 119 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
fa1c114f
JS		 120 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
121 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
122 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
123 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
124 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
125 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
bb0c9dc2 128 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
fa1c114f
JS		 129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
131 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
132 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
133};
134
63266a65
BR		 135static struct ieee80211_rate ath5k_rates[] = {
136 { .bitrate = 10,
137 .hw_value = ATH5K_RATE_CODE_1M, },
138 { .bitrate = 20,
139 .hw_value = ATH5K_RATE_CODE_2M,
140 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
141 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
142 { .bitrate = 55,
143 .hw_value = ATH5K_RATE_CODE_5_5M,
144 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
145 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
146 { .bitrate = 110,
147 .hw_value = ATH5K_RATE_CODE_11M,
148 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
149 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
150 { .bitrate = 60,
151 .hw_value = ATH5K_RATE_CODE_6M,
152 .flags = 0 },
153 { .bitrate = 90,
154 .hw_value = ATH5K_RATE_CODE_9M,
155 .flags = 0 },
156 { .bitrate = 120,
157 .hw_value = ATH5K_RATE_CODE_12M,
158 .flags = 0 },
159 { .bitrate = 180,
160 .hw_value = ATH5K_RATE_CODE_18M,
161 .flags = 0 },
162 { .bitrate = 240,
163 .hw_value = ATH5K_RATE_CODE_24M,
164 .flags = 0 },
165 { .bitrate = 360,
166 .hw_value = ATH5K_RATE_CODE_36M,
167 .flags = 0 },
168 { .bitrate = 480,
169 .hw_value = ATH5K_RATE_CODE_48M,
170 .flags = 0 },
171 { .bitrate = 540,
172 .hw_value = ATH5K_RATE_CODE_54M,
173 .flags = 0 },
174 /* XR missing */
175};
176
fa1c114f
JS		 177/*
178 * Prototypes - PCI stack related functions
179 */
180static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
181 const struct pci_device_id *id);
182static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
183#ifdef CONFIG_PM
184static int ath5k_pci_suspend(struct pci_dev *pdev,
185 pm_message_t state);
186static int ath5k_pci_resume(struct pci_dev *pdev);
187#else
188#define ath5k_pci_suspend NULL
189#define ath5k_pci_resume NULL
190#endif /* CONFIG_PM */
191
04a9e451 192static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 193 .name = "ath5k_pci",
194 .id_table = ath5k_pci_id_table,
195 .probe = ath5k_pci_probe,
196 .remove = __devexit_p(ath5k_pci_remove),
197 .suspend = ath5k_pci_suspend,
198 .resume = ath5k_pci_resume,
199};
200
201
202
203/*
204 * Prototypes - MAC 802.11 stack related functions
205 */
e039fa4a 206static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 207static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
208static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 209static int ath5k_start(struct ieee80211_hw *hw);
210static void ath5k_stop(struct ieee80211_hw *hw);
211static int ath5k_add_interface(struct ieee80211_hw *hw,
212 struct ieee80211_if_init_conf *conf);
213static void ath5k_remove_interface(struct ieee80211_hw *hw,
214 struct ieee80211_if_init_conf *conf);
215static int ath5k_config(struct ieee80211_hw *hw,
216 struct ieee80211_conf *conf);
32bfd35d
JB		 217static int ath5k_config_interface(struct ieee80211_hw *hw,
218 struct ieee80211_vif *vif,
fa1c114f
JS		 219 struct ieee80211_if_conf *conf);
220static void ath5k_configure_filter(struct ieee80211_hw *hw,
221 unsigned int changed_flags,
222 unsigned int *new_flags,
223 int mc_count, struct dev_mc_list *mclist);
224static int ath5k_set_key(struct ieee80211_hw *hw,
225 enum set_key_cmd cmd,
226 const u8 *local_addr, const u8 *addr,
227 struct ieee80211_key_conf *key);
228static int ath5k_get_stats(struct ieee80211_hw *hw,
229 struct ieee80211_low_level_stats *stats);
230static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
231 struct ieee80211_tx_queue_stats *stats);
232static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
233static void ath5k_reset_tsf(struct ieee80211_hw *hw);
234static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 235 struct sk_buff *skb);
fa1c114f
JS		 236
237static struct ieee80211_ops ath5k_hw_ops = {
238 .tx = ath5k_tx,
239 .start = ath5k_start,
240 .stop = ath5k_stop,
241 .add_interface = ath5k_add_interface,
242 .remove_interface = ath5k_remove_interface,
243 .config = ath5k_config,
244 .config_interface = ath5k_config_interface,
245 .configure_filter = ath5k_configure_filter,
246 .set_key = ath5k_set_key,
247 .get_stats = ath5k_get_stats,
248 .conf_tx = NULL,
249 .get_tx_stats = ath5k_get_tx_stats,
250 .get_tsf = ath5k_get_tsf,
251 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 252};
253
254/*
255 * Prototypes - Internal functions
256 */
257/* Attach detach */
258static int ath5k_attach(struct pci_dev *pdev,
259 struct ieee80211_hw *hw);
260static void ath5k_detach(struct pci_dev *pdev,
261 struct ieee80211_hw *hw);
262/* Channel/mode setup */
263static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 264static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
265 struct ieee80211_channel *channels,
266 unsigned int mode,
267 unsigned int max);
63266a65 268static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 269static int ath5k_chan_set(struct ath5k_softc *sc,
270 struct ieee80211_channel *chan);
271static void ath5k_setcurmode(struct ath5k_softc *sc,
272 unsigned int mode);
273static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 274
fa1c114f
JS		 275/* Descriptor setup */
276static int ath5k_desc_alloc(struct ath5k_softc *sc,
277 struct pci_dev *pdev);
278static void ath5k_desc_free(struct ath5k_softc *sc,
279 struct pci_dev *pdev);
280/* Buffers setup */
281static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
282 struct ath5k_buf *bf);
283static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 284 struct ath5k_buf *bf);
fa1c114f
JS		 285static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
286 struct ath5k_buf *bf)
287{
288 BUG_ON(!bf);
289 if (!bf->skb)
290 return;
291 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
292 PCI_DMA_TODEVICE);
00482973 293 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 294 bf->skb = NULL;
295}
296
297/* Queues setup */
298static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
299 int qtype, int subtype);
300static int ath5k_beaconq_setup(struct ath5k_hw *ah);
301static int ath5k_beaconq_config(struct ath5k_softc *sc);
302static void ath5k_txq_drainq(struct ath5k_softc *sc,
303 struct ath5k_txq *txq);
304static void ath5k_txq_cleanup(struct ath5k_softc *sc);
305static void ath5k_txq_release(struct ath5k_softc *sc);
306/* Rx handling */
307static int ath5k_rx_start(struct ath5k_softc *sc);
308static void ath5k_rx_stop(struct ath5k_softc *sc);
309static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
310 struct ath5k_desc *ds,
b47f407b
BR		 311 struct sk_buff *skb,
312 struct ath5k_rx_status *rs);
fa1c114f
JS		 313static void ath5k_tasklet_rx(unsigned long data);
314/* Tx handling */
315static void ath5k_tx_processq(struct ath5k_softc *sc,
316 struct ath5k_txq *txq);
317static void ath5k_tasklet_tx(unsigned long data);
318/* Beacon handling */
319static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 320 struct ath5k_buf *bf);
fa1c114f
JS		 321static void ath5k_beacon_send(struct ath5k_softc *sc);
322static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 323static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 324
325static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
326{
327 u64 tsf = ath5k_hw_get_tsf64(ah);
328
329 if ((tsf & 0x7fff) < rstamp)
330 tsf -= 0x8000;
331
332 return (tsf & ~0x7fff) | rstamp;
333}
334
335/* Interrupt handling */
336static int ath5k_init(struct ath5k_softc *sc);
337static int ath5k_stop_locked(struct ath5k_softc *sc);
338static int ath5k_stop_hw(struct ath5k_softc *sc);
339static irqreturn_t ath5k_intr(int irq, void *dev_id);
340static void ath5k_tasklet_reset(unsigned long data);
341
342static void ath5k_calibrate(unsigned long data);
343/* LED functions */
3a078876
BC		 344static int ath5k_init_leds(struct ath5k_softc *sc);
345static void ath5k_led_enable(struct ath5k_softc *sc);
346static void ath5k_led_off(struct ath5k_softc *sc);
347static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 348
349/*
350 * Module init/exit functions
351 */
352static int __init
353init_ath5k_pci(void)
354{
355 int ret;
356
357 ath5k_debug_init();
358
04a9e451 359 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 360 if (ret) {
361 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
362 return ret;
363 }
364
365 return 0;
366}
367
368static void __exit
369exit_ath5k_pci(void)
370{
04a9e451 371 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 372
373 ath5k_debug_finish();
374}
375
376module_init(init_ath5k_pci);
377module_exit(exit_ath5k_pci);
378
379
380/********************\
381* PCI Initialization *
382\********************/
383
384static const char *
385ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
386{
387 const char *name = "xxxxx";
388 unsigned int i;
389
390 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
391 if (srev_names[i].sr_type != type)
392 continue;
393 if ((val & 0xff) < srev_names[i + 1].sr_val) {
394 name = srev_names[i].sr_name;
395 break;
396 }
397 }
398
399 return name;
400}
401
402static int __devinit
403ath5k_pci_probe(struct pci_dev *pdev,
404 const struct pci_device_id *id)
405{
406 void __iomem *mem;
407 struct ath5k_softc *sc;
408 struct ieee80211_hw *hw;
409 int ret;
410 u8 csz;
411
412 ret = pci_enable_device(pdev);
413 if (ret) {
414 dev_err(&pdev->dev, "can't enable device\n");
415 goto err;
416 }
417
418 /* XXX 32-bit addressing only */
419 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
420 if (ret) {
421 dev_err(&pdev->dev, "32-bit DMA not available\n");
422 goto err_dis;
423 }
424
425 /*
426 * Cache line size is used to size and align various
427 * structures used to communicate with the hardware.
428 */
429 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
430 if (csz == 0) {
431 /*
432 * Linux 2.4.18 (at least) writes the cache line size
433 * register as a 16-bit wide register which is wrong.
434 * We must have this setup properly for rx buffer
435 * DMA to work so force a reasonable value here if it
436 * comes up zero.
437 */
438 csz = L1_CACHE_BYTES / sizeof(u32);
439 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
440 }
441 /*
442 * The default setting of latency timer yields poor results,
443 * set it to the value used by other systems. It may be worth
444 * tweaking this setting more.
445 */
446 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
447
448 /* Enable bus mastering */
449 pci_set_master(pdev);
450
451 /*
452 * Disable the RETRY_TIMEOUT register (0x41) to keep
453 * PCI Tx retries from interfering with C3 CPU state.
454 */
455 pci_write_config_byte(pdev, 0x41, 0);
456
457 ret = pci_request_region(pdev, 0, "ath5k");
458 if (ret) {
459 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
460 goto err_dis;
461 }
462
463 mem = pci_iomap(pdev, 0, 0);
464 if (!mem) {
465 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
466 ret = -EIO;
467 goto err_reg;
468 }
469
470 /*
471 * Allocate hw (mac80211 main struct)
472 * and hw->priv (driver private data)
473 */
474 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
475 if (hw == NULL) {
476 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
477 ret = -ENOMEM;
478 goto err_map;
479 }
480
481 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
482
483 /* Initialize driver private data */
484 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 485 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
486 IEEE80211_HW_SIGNAL_DBM |
487 IEEE80211_HW_NOISE_DBM;
fa1c114f
JS		 488 hw->extra_tx_headroom = 2;
489 hw->channel_change_time = 5000;
fa1c114f
JS		 490 sc = hw->priv;
491 sc->hw = hw;
492 sc->pdev = pdev;
493
494 ath5k_debug_init_device(sc);
495
496 /*
497 * Mark the device as detached to avoid processing
498 * interrupts until setup is complete.
499 */
500 __set_bit(ATH_STAT_INVALID, sc->status);
501
502 sc->iobase = mem; /* So we can unmap it on detach */
503 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
504 sc->opmode = IEEE80211_IF_TYPE_STA;
505 mutex_init(&sc->lock);
506 spin_lock_init(&sc->rxbuflock);
507 spin_lock_init(&sc->txbuflock);
00482973 508 spin_lock_init(&sc->block);
fa1c114f
JS		 509
510 /* Set private data */
511 pci_set_drvdata(pdev, hw);
512
fa1c114f
JS		 513 /* Setup interrupt handler */
514 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
515 if (ret) {
516 ATH5K_ERR(sc, "request_irq failed\n");
517 goto err_free;
518 }
519
520 /* Initialize device */
521 sc->ah = ath5k_hw_attach(sc, id->driver_data);
522 if (IS_ERR(sc->ah)) {
523 ret = PTR_ERR(sc->ah);
524 goto err_irq;
525 }
526
527 /* Finish private driver data initialization */
528 ret = ath5k_attach(pdev, hw);
529 if (ret)
530 goto err_ah;
531
532 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
533 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
534 sc->ah->ah_mac_srev,
535 sc->ah->ah_phy_revision);
536
400ec45a 537 if (!sc->ah->ah_single_chip) {
fa1c114f 538 /* Single chip radio (!RF5111) */
400ec45a
LR		 539 if (sc->ah->ah_radio_5ghz_revision &&
540 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 541 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 542 if (!test_bit(AR5K_MODE_11A,
543 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 544 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 545 ath5k_chip_name(AR5K_VERSION_RAD,
546 sc->ah->ah_radio_5ghz_revision),
547 sc->ah->ah_radio_5ghz_revision);
548 /* No 2GHz support (5110 and some
549 * 5Ghz only cards) -> report 5Ghz radio */
550 } else if (!test_bit(AR5K_MODE_11B,
551 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 552 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 553 ath5k_chip_name(AR5K_VERSION_RAD,
554 sc->ah->ah_radio_5ghz_revision),
555 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 556 /* Multiband radio */
557 } else {
558 ATH5K_INFO(sc, "RF%s multiband radio found"
559 " (0x%x)\n",
400ec45a
LR		 560 ath5k_chip_name(AR5K_VERSION_RAD,
561 sc->ah->ah_radio_5ghz_revision),
562 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 563 }
564 }
400ec45a
LR		 565 /* Multi chip radio (RF5111 - RF2111) ->
566 * report both 2GHz/5GHz radios */
567 else if (sc->ah->ah_radio_5ghz_revision &&
568 sc->ah->ah_radio_2ghz_revision){
fa1c114f 569 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 570 ath5k_chip_name(AR5K_VERSION_RAD,
571 sc->ah->ah_radio_5ghz_revision),
572 sc->ah->ah_radio_5ghz_revision);
fa1c114f 573 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 574 ath5k_chip_name(AR5K_VERSION_RAD,
575 sc->ah->ah_radio_2ghz_revision),
576 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 577 }
578 }
579
580
581 /* ready to process interrupts */
582 __clear_bit(ATH_STAT_INVALID, sc->status);
583
584 return 0;
585err_ah:
586 ath5k_hw_detach(sc->ah);
587err_irq:
588 free_irq(pdev->irq, sc);
589err_free:
fa1c114f
JS		 590 ieee80211_free_hw(hw);
591err_map:
592 pci_iounmap(pdev, mem);
593err_reg:
594 pci_release_region(pdev, 0);
595err_dis:
596 pci_disable_device(pdev);
597err:
598 return ret;
599}
600
601static void __devexit
602ath5k_pci_remove(struct pci_dev *pdev)
603{
604 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
605 struct ath5k_softc *sc = hw->priv;
606
607 ath5k_debug_finish_device(sc);
608 ath5k_detach(pdev, hw);
609 ath5k_hw_detach(sc->ah);
610 free_irq(pdev->irq, sc);
fa1c114f
JS		 611 pci_iounmap(pdev, sc->iobase);
612 pci_release_region(pdev, 0);
613 pci_disable_device(pdev);
614 ieee80211_free_hw(hw);
615}
616
617#ifdef CONFIG_PM
618static int
619ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
620{
621 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
622 struct ath5k_softc *sc = hw->priv;
623
3a078876 624 ath5k_led_off(sc);
fa1c114f
JS		 625
626 ath5k_stop_hw(sc);
3e4242b9
JS		 627
628 free_irq(pdev->irq, sc);
fa1c114f
JS		 629 pci_save_state(pdev);
630 pci_disable_device(pdev);
631 pci_set_power_state(pdev, PCI_D3hot);
632
633 return 0;
634}
635
636static int
637ath5k_pci_resume(struct pci_dev *pdev)
638{
639 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
640 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 641 struct ath5k_hw *ah = sc->ah;
642 int i, err;
fa1c114f 643
3e4242b9 644 pci_restore_state(pdev);
fa1c114f
JS		 645
646 err = pci_enable_device(pdev);
647 if (err)
648 return err;
649
fa1c114f
JS		 650 /*
651 * Suspend/Resume resets the PCI configuration space, so we have to
652 * re-disable the RETRY_TIMEOUT register (0x41) to keep
653 * PCI Tx retries from interfering with C3 CPU state
654 */
655 pci_write_config_byte(pdev, 0x41, 0);
656
3e4242b9
JS		 657 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
658 if (err) {
659 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 660 goto err_no_irq;
3e4242b9
JS		 661 }
662
663 err = ath5k_init(sc);
664 if (err)
665 goto err_irq;
3a078876 666 ath5k_led_enable(sc);
fa1c114f 667
247ae449
JL		 668 /*
669 * Reset the key cache since some parts do not
670 * reset the contents on initial power up or resume.
671 *
672 * FIXME: This may need to be revisited when mac80211 becomes
673 * aware of suspend/resume.
674 */
675 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
676 ath5k_hw_reset_key(ah, i);
677
fa1c114f 678 return 0;
3e4242b9
JS		 679err_irq:
680 free_irq(pdev->irq, sc);
37465c8a 681err_no_irq:
3e4242b9
JS		 682 pci_disable_device(pdev);
683 return err;
fa1c114f
JS		 684}
685#endif /* CONFIG_PM */
686
687
fa1c114f
JS		 688/***********************\
689* Driver Initialization *
690\***********************/
691
692static int
693ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
694{
695 struct ath5k_softc *sc = hw->priv;
696 struct ath5k_hw *ah = sc->ah;
697 u8 mac[ETH_ALEN];
698 unsigned int i;
699 int ret;
700
701 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
702
703 /*
704 * Check if the MAC has multi-rate retry support.
705 * We do this by trying to setup a fake extended
706 * descriptor. MAC's that don't have support will
707 * return false w/o doing anything. MAC's that do
708 * support it will return true w/o doing anything.
709 */
b9887638
JS		 710 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
711 if (ret < 0)
712 goto err;
713 if (ret > 0)
fa1c114f
JS		 714 __set_bit(ATH_STAT_MRRETRY, sc->status);
715
716 /*
717 * Reset the key cache since some parts do not
718 * reset the contents on initial power up.
719 */
c65638a7 720 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 721 ath5k_hw_reset_key(ah, i);
722
723 /*
724 * Collect the channel list. The 802.11 layer
725 * is resposible for filtering this list based
726 * on settings like the phy mode and regulatory
727 * domain restrictions.
728 */
63266a65 729 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 730 if (ret) {
731 ATH5K_ERR(sc, "can't get channels\n");
732 goto err;
733 }
734
735 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 736 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
737 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 738 else
d8ee398d 739 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 740
741 /*
742 * Allocate tx+rx descriptors and populate the lists.
743 */
744 ret = ath5k_desc_alloc(sc, pdev);
745 if (ret) {
746 ATH5K_ERR(sc, "can't allocate descriptors\n");
747 goto err;
748 }
749
750 /*
751 * Allocate hardware transmit queues: one queue for
752 * beacon frames and one data queue for each QoS
753 * priority. Note that hw functions handle reseting
754 * these queues at the needed time.
755 */
756 ret = ath5k_beaconq_setup(ah);
757 if (ret < 0) {
758 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
759 goto err_desc;
760 }
761 sc->bhalq = ret;
762
763 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
764 if (IS_ERR(sc->txq)) {
765 ATH5K_ERR(sc, "can't setup xmit queue\n");
766 ret = PTR_ERR(sc->txq);
767 goto err_bhal;
768 }
769
770 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
771 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
772 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
773 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 774
775 ath5k_hw_get_lladdr(ah, mac);
776 SET_IEEE80211_PERM_ADDR(hw, mac);
777 /* All MAC address bits matter for ACKs */
778 memset(sc->bssidmask, 0xff, ETH_ALEN);
779 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
780
781 ret = ieee80211_register_hw(hw);
782 if (ret) {
783 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
784 goto err_queues;
785 }
786
3a078876
BC		 787 ath5k_init_leds(sc);
788
fa1c114f
JS		 789 return 0;
790err_queues:
791 ath5k_txq_release(sc);
792err_bhal:
793 ath5k_hw_release_tx_queue(ah, sc->bhalq);
794err_desc:
795 ath5k_desc_free(sc, pdev);
796err:
797 return ret;
798}
799
800static void
801ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
802{
803 struct ath5k_softc *sc = hw->priv;
804
805 /*
806 * NB: the order of these is important:
807 * o call the 802.11 layer before detaching ath5k_hw to
808 * insure callbacks into the driver to delete global
809 * key cache entries can be handled
810 * o reclaim the tx queue data structures after calling
811 * the 802.11 layer as we'll get called back to reclaim
812 * node state and potentially want to use them
813 * o to cleanup the tx queues the hal is called, so detach
814 * it last
815 * XXX: ??? detach ath5k_hw ???
816 * Other than that, it's straightforward...
817 */
818 ieee80211_unregister_hw(hw);
819 ath5k_desc_free(sc, pdev);
820 ath5k_txq_release(sc);
821 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 822 ath5k_unregister_leds(sc);
fa1c114f
JS		 823
824 /*
825 * NB: can't reclaim these until after ieee80211_ifdetach
826 * returns because we'll get called back to reclaim node
827 * state and potentially want to use them.
828 */
829}
830
831
832
833
834/********************\
835* Channel/mode setup *
836\********************/
837
838/*
839 * Convert IEEE channel number to MHz frequency.
840 */
841static inline short
842ath5k_ieee2mhz(short chan)
843{
844 if (chan <= 14 || chan >= 27)
845 return ieee80211chan2mhz(chan);
846 else
847 return 2212 + chan * 20;
848}
849
fa1c114f
JS		 850static unsigned int
851ath5k_copy_channels(struct ath5k_hw *ah,
852 struct ieee80211_channel *channels,
853 unsigned int mode,
854 unsigned int max)
855{
d8ee398d 856 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 857
858 if (!test_bit(mode, ah->ah_modes))
859 return 0;
860
fa1c114f 861 switch (mode) {
d8ee398d
LR		 862 case AR5K_MODE_11A:
863 case AR5K_MODE_11A_TURBO:
fa1c114f 864 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 865 size = 220 ;
fa1c114f
JS		 866 chfreq = CHANNEL_5GHZ;
867 break;
d8ee398d
LR		 868 case AR5K_MODE_11B:
869 case AR5K_MODE_11G:
870 case AR5K_MODE_11G_TURBO:
871 size = 26;
fa1c114f
JS		 872 chfreq = CHANNEL_2GHZ;
873 break;
874 default:
875 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
876 return 0;
877 }
878
879 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 880 ch = i + 1 ;
881 freq = ath5k_ieee2mhz(ch);
fa1c114f 882
d8ee398d
LR		 883 /* Check if channel is supported by the chipset */
884 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 885 continue;
886
d8ee398d
LR		 887 /* Write channel info and increment counter */
888 channels[count].center_freq = freq;
a3f4b914
LR		 889 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
890 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 891 switch (mode) {
892 case AR5K_MODE_11A:
893 case AR5K_MODE_11G:
894 channels[count].hw_value = chfreq | CHANNEL_OFDM;
895 break;
896 case AR5K_MODE_11A_TURBO:
897 case AR5K_MODE_11G_TURBO:
898 channels[count].hw_value = chfreq |
899 CHANNEL_OFDM | CHANNEL_TURBO;
900 break;
901 case AR5K_MODE_11B:
d8ee398d
LR		 902 channels[count].hw_value = CHANNEL_B;
903 }
fa1c114f 904
fa1c114f
JS		 905 count++;
906 max--;
907 }
908
909 return count;
910}
911
63266a65
BR		 912static void
913ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
914{
915 u8 i;
916
917 for (i = 0; i < AR5K_MAX_RATES; i++)
918 sc->rate_idx[b->band][i] = -1;
919
920 for (i = 0; i < b->n_bitrates; i++) {
921 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
922 if (b->bitrates[i].hw_value_short)
923 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
924 }
925}
926
d8ee398d 927static int
63266a65 928ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 929{
930 struct ath5k_softc *sc = hw->priv;
d8ee398d 931 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 932 struct ieee80211_supported_band *sband;
933 int max_c, count_c = 0;
934 int i;
fa1c114f 935
d8ee398d 936 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 937 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 938
939 /* 2GHz band */
63266a65
BR		 940 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
941 sband->band = IEEE80211_BAND_2GHZ;
942 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 943
63266a65
BR		 944 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
945 /* G mode */
946 memcpy(sband->bitrates, &ath5k_rates[0],
947 sizeof(struct ieee80211_rate) * 12);
948 sband->n_bitrates = 12;
fa1c114f 949
d8ee398d 950 sband->channels = sc->channels;
d8ee398d 951 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 952 AR5K_MODE_11G, max_c);
fa1c114f 953
63266a65 954 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 955 count_c = sband->n_channels;
63266a65
BR		 956 max_c -= count_c;
957 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
958 /* B mode */
959 memcpy(sband->bitrates, &ath5k_rates[0],
960 sizeof(struct ieee80211_rate) * 4);
961 sband->n_bitrates = 4;
962
963 /* 5211 only supports B rates and uses 4bit rate codes
964 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
965 * fix them up here:
966 */
967 if (ah->ah_version == AR5K_AR5211) {
968 for (i = 0; i < 4; i++) {
969 sband->bitrates[i].hw_value =
970 sband->bitrates[i].hw_value & 0xF;
971 sband->bitrates[i].hw_value_short =
972 sband->bitrates[i].hw_value_short & 0xF;
973 }
974 }
fa1c114f 975
63266a65
BR		 976 sband->channels = sc->channels;
977 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
978 AR5K_MODE_11B, max_c);
d8ee398d 979
63266a65
BR		 980 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
981 count_c = sband->n_channels;
d8ee398d 982 max_c -= count_c;
fa1c114f 983 }
63266a65 984 ath5k_setup_rate_idx(sc, sband);
fa1c114f 985
63266a65 986 /* 5GHz band, A mode */
400ec45a 987 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 988 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
989 sband->band = IEEE80211_BAND_5GHZ;
990 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 991
63266a65
BR		 992 memcpy(sband->bitrates, &ath5k_rates[4],
993 sizeof(struct ieee80211_rate) * 8);
994 sband->n_bitrates = 8;
fa1c114f 995
63266a65 996 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 997 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
998 AR5K_MODE_11A, max_c);
999
d8ee398d
LR		 1000 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1001 }
63266a65 1002 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1003
b446197c 1004 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1005
1006 return 0;
fa1c114f
JS		 1007}
1008
1009/*
1010 * Set/change channels. If the channel is really being changed,
1011 * it's done by reseting the chip. To accomplish this we must
1012 * first cleanup any pending DMA, then restart stuff after a la
1013 * ath5k_init.
1014 */
1015static int
1016ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1017{
d8ee398d
LR		 1018 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1019 sc->curchan->center_freq, chan->center_freq);
1020
1021 if (chan->center_freq != sc->curchan->center_freq ||
1022 chan->hw_value != sc->curchan->hw_value) {
1023
1024 sc->curchan = chan;
1025 sc->curband = &sc->sbands[chan->band];
fa1c114f 1026
fa1c114f
JS		 1027 /*
1028 * To switch channels clear any pending DMA operations;
1029 * wait long enough for the RX fifo to drain, reset the
1030 * hardware at the new frequency, and then re-enable
1031 * the relevant bits of the h/w.
1032 */
d7dc1003 1033 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1034 }
1035
1036 return 0;
1037}
1038
1039static void
1040ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1041{
fa1c114f 1042 sc->curmode = mode;
d8ee398d 1043
400ec45a 1044 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1045 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1046 } else {
1047 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1048 }
fa1c114f
JS		 1049}
1050
1051static void
1052ath5k_mode_setup(struct ath5k_softc *sc)
1053{
1054 struct ath5k_hw *ah = sc->ah;
1055 u32 rfilt;
1056
1057 /* configure rx filter */
1058 rfilt = sc->filter_flags;
1059 ath5k_hw_set_rx_filter(ah, rfilt);
1060
1061 if (ath5k_hw_hasbssidmask(ah))
1062 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1063
1064 /* configure operational mode */
1065 ath5k_hw_set_opmode(ah);
1066
1067 ath5k_hw_set_mcast_filter(ah, 0, 0);
1068 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1069}
1070
d8ee398d 1071static inline int
63266a65
BR		 1072ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1073{
1074 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1075 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1076}
1077
fa1c114f
JS		 1078/***************\
1079* Buffers setup *
1080\***************/
1081
1082static int
1083ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1084{
1085 struct ath5k_hw *ah = sc->ah;
1086 struct sk_buff *skb = bf->skb;
1087 struct ath5k_desc *ds;
1088
1089 if (likely(skb == NULL)) {
1090 unsigned int off;
1091
1092 /*
1093 * Allocate buffer with headroom_needed space for the
1094 * fake physical layer header at the start.
1095 */
1096 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1097 if (unlikely(skb == NULL)) {
1098 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1099 sc->rxbufsize + sc->cachelsz - 1);
1100 return -ENOMEM;
1101 }
1102 /*
1103 * Cache-line-align. This is important (for the
1104 * 5210 at least) as not doing so causes bogus data
1105 * in rx'd frames.
1106 */
1107 off = ((unsigned long)skb->data) % sc->cachelsz;
1108 if (off != 0)
1109 skb_reserve(skb, sc->cachelsz - off);
1110
1111 bf->skb = skb;
1112 bf->skbaddr = pci_map_single(sc->pdev,
1113 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1114 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1115 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1116 dev_kfree_skb(skb);
1117 bf->skb = NULL;
1118 return -ENOMEM;
1119 }
1120 }
1121
1122 /*
1123 * Setup descriptors. For receive we always terminate
1124 * the descriptor list with a self-linked entry so we'll
1125 * not get overrun under high load (as can happen with a
1126 * 5212 when ANI processing enables PHY error frames).
1127 *
1128 * To insure the last descriptor is self-linked we create
1129 * each descriptor as self-linked and add it to the end. As
1130 * each additional descriptor is added the previous self-linked
1131 * entry is ``fixed'' naturally. This should be safe even
1132 * if DMA is happening. When processing RX interrupts we
1133 * never remove/process the last, self-linked, entry on the
1134 * descriptor list. This insures the hardware always has
1135 * someplace to write a new frame.
1136 */
1137 ds = bf->desc;
1138 ds->ds_link = bf->daddr; /* link to self */
1139 ds->ds_data = bf->skbaddr;
1140 ath5k_hw_setup_rx_desc(ah, ds,
1141 skb_tailroom(skb), /* buffer size */
1142 0);
1143
1144 if (sc->rxlink != NULL)
1145 *sc->rxlink = bf->daddr;
1146 sc->rxlink = &ds->ds_link;
1147 return 0;
1148}
1149
1150static int
e039fa4a 1151ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1152{
1153 struct ath5k_hw *ah = sc->ah;
1154 struct ath5k_txq *txq = sc->txq;
1155 struct ath5k_desc *ds = bf->desc;
1156 struct sk_buff *skb = bf->skb;
a888d52d 1157 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1158 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1159 int ret;
1160
1161 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1162
fa1c114f
JS		 1163 /* XXX endianness */
1164 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1165 PCI_DMA_TODEVICE);
1166
e039fa4a 1167 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1168 flags |= AR5K_TXDESC_NOACK;
1169
281c56dd 1170 pktlen = skb->len;
fa1c114f 1171
d0f09804 1172 if (info->control.hw_key) {
e039fa4a
JB		 1173 keyidx = info->control.hw_key->hw_key_idx;
1174 pktlen += info->control.icv_len;
fa1c114f 1175 }
fa1c114f
JS		 1176 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1177 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1178 (sc->power_level * 2),
e039fa4a
JB		 1179 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1180 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1181 if (ret)
1182 goto err_unmap;
1183
1184 ds->ds_link = 0;
1185 ds->ds_data = bf->skbaddr;
1186
1187 spin_lock_bh(&txq->lock);
1188 list_add_tail(&bf->list, &txq->q);
57ffc589 1189 sc->tx_stats[txq->qnum].len++;
fa1c114f
JS		 1190 if (txq->link == NULL) /* is this first packet? */
1191 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1192 else /* no, so only link it */
1193 *txq->link = bf->daddr;
1194
1195 txq->link = &ds->ds_link;
1196 ath5k_hw_tx_start(ah, txq->qnum);
274c7c36 1197 mmiowb();
fa1c114f
JS		 1198 spin_unlock_bh(&txq->lock);
1199
1200 return 0;
1201err_unmap:
1202 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1203 return ret;
1204}
1205
1206/*******************\
1207* Descriptors setup *
1208\*******************/
1209
1210static int
1211ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1212{
1213 struct ath5k_desc *ds;
1214 struct ath5k_buf *bf;
1215 dma_addr_t da;
1216 unsigned int i;
1217 int ret;
1218
1219 /* allocate descriptors */
1220 sc->desc_len = sizeof(struct ath5k_desc) *
1221 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1222 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1223 if (sc->desc == NULL) {
1224 ATH5K_ERR(sc, "can't allocate descriptors\n");
1225 ret = -ENOMEM;
1226 goto err;
1227 }
1228 ds = sc->desc;
1229 da = sc->desc_daddr;
1230 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1231 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1232
1233 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1234 sizeof(struct ath5k_buf), GFP_KERNEL);
1235 if (bf == NULL) {
1236 ATH5K_ERR(sc, "can't allocate bufptr\n");
1237 ret = -ENOMEM;
1238 goto err_free;
1239 }
1240 sc->bufptr = bf;
1241
1242 INIT_LIST_HEAD(&sc->rxbuf);
1243 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1244 bf->desc = ds;
1245 bf->daddr = da;
1246 list_add_tail(&bf->list, &sc->rxbuf);
1247 }
1248
1249 INIT_LIST_HEAD(&sc->txbuf);
1250 sc->txbuf_len = ATH_TXBUF;
1251 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1252 da += sizeof(*ds)) {
1253 bf->desc = ds;
1254 bf->daddr = da;
1255 list_add_tail(&bf->list, &sc->txbuf);
1256 }
1257
1258 /* beacon buffer */
1259 bf->desc = ds;
1260 bf->daddr = da;
1261 sc->bbuf = bf;
1262
1263 return 0;
1264err_free:
1265 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1266err:
1267 sc->desc = NULL;
1268 return ret;
1269}
1270
1271static void
1272ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1273{
1274 struct ath5k_buf *bf;
1275
1276 ath5k_txbuf_free(sc, sc->bbuf);
1277 list_for_each_entry(bf, &sc->txbuf, list)
1278 ath5k_txbuf_free(sc, bf);
1279 list_for_each_entry(bf, &sc->rxbuf, list)
1280 ath5k_txbuf_free(sc, bf);
1281
1282 /* Free memory associated with all descriptors */
1283 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1284
1285 kfree(sc->bufptr);
1286 sc->bufptr = NULL;
1287}
1288
1289
1290
1291
1292
1293/**************\
1294* Queues setup *
1295\**************/
1296
1297static struct ath5k_txq *
1298ath5k_txq_setup(struct ath5k_softc *sc,
1299 int qtype, int subtype)
1300{
1301 struct ath5k_hw *ah = sc->ah;
1302 struct ath5k_txq *txq;
1303 struct ath5k_txq_info qi = {
1304 .tqi_subtype = subtype,
1305 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1306 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1307 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1308 };
1309 int qnum;
1310
1311 /*
1312 * Enable interrupts only for EOL and DESC conditions.
1313 * We mark tx descriptors to receive a DESC interrupt
1314 * when a tx queue gets deep; otherwise waiting for the
1315 * EOL to reap descriptors. Note that this is done to
1316 * reduce interrupt load and this only defers reaping
1317 * descriptors, never transmitting frames. Aside from
1318 * reducing interrupts this also permits more concurrency.
1319 * The only potential downside is if the tx queue backs
1320 * up in which case the top half of the kernel may backup
1321 * due to a lack of tx descriptors.
1322 */
1323 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1324 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1325 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1326 if (qnum < 0) {
1327 /*
1328 * NB: don't print a message, this happens
1329 * normally on parts with too few tx queues
1330 */
1331 return ERR_PTR(qnum);
1332 }
1333 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1334 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1335 qnum, ARRAY_SIZE(sc->txqs));
1336 ath5k_hw_release_tx_queue(ah, qnum);
1337 return ERR_PTR(-EINVAL);
1338 }
1339 txq = &sc->txqs[qnum];
1340 if (!txq->setup) {
1341 txq->qnum = qnum;
1342 txq->link = NULL;
1343 INIT_LIST_HEAD(&txq->q);
1344 spin_lock_init(&txq->lock);
1345 txq->setup = true;
1346 }
1347 return &sc->txqs[qnum];
1348}
1349
1350static int
1351ath5k_beaconq_setup(struct ath5k_hw *ah)
1352{
1353 struct ath5k_txq_info qi = {
1354 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1355 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1356 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1357 /* NB: for dynamic turbo, don't enable any other interrupts */
1358 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1359 };
1360
1361 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1362}
1363
1364static int
1365ath5k_beaconq_config(struct ath5k_softc *sc)
1366{
1367 struct ath5k_hw *ah = sc->ah;
1368 struct ath5k_txq_info qi;
1369 int ret;
1370
1371 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1372 if (ret)
1373 return ret;
8e5f3d0a
AY		 1374 if (sc->opmode == IEEE80211_IF_TYPE_AP ||
1375 sc->opmode == IEEE80211_IF_TYPE_MESH_POINT) {
fa1c114f
JS		 1376 /*
1377 * Always burst out beacon and CAB traffic
1378 * (aifs = cwmin = cwmax = 0)
1379 */
1380 qi.tqi_aifs = 0;
1381 qi.tqi_cw_min = 0;
1382 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1383 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1384 /*
1385 * Adhoc mode; backoff between 0 and (2 * cw_min).
1386 */
1387 qi.tqi_aifs = 0;
1388 qi.tqi_cw_min = 0;
1389 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1390 }
1391
6d91e1d8
BR		 1392 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1393 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1394 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1395
fa1c114f
JS		 1396 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1397 if (ret) {
1398 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1399 "hardware queue!\n", __func__);
1400 return ret;
1401 }
1402
1403 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1404}
1405
1406static void
1407ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1408{
1409 struct ath5k_buf *bf, *bf0;
1410
1411 /*
1412 * NB: this assumes output has been stopped and
1413 * we do not need to block ath5k_tx_tasklet
1414 */
1415 spin_lock_bh(&txq->lock);
1416 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1417 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1418
1419 ath5k_txbuf_free(sc, bf);
1420
1421 spin_lock_bh(&sc->txbuflock);
57ffc589 1422 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1423 list_move_tail(&bf->list, &sc->txbuf);
1424 sc->txbuf_len++;
1425 spin_unlock_bh(&sc->txbuflock);
1426 }
1427 txq->link = NULL;
1428 spin_unlock_bh(&txq->lock);
1429}
1430
1431/*
1432 * Drain the transmit queues and reclaim resources.
1433 */
1434static void
1435ath5k_txq_cleanup(struct ath5k_softc *sc)
1436{
1437 struct ath5k_hw *ah = sc->ah;
1438 unsigned int i;
1439
1440 /* XXX return value */
1441 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1442 /* don't touch the hardware if marked invalid */
1443 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1444 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1445 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1446 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1447 if (sc->txqs[i].setup) {
1448 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1449 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1450 "link %p\n",
1451 sc->txqs[i].qnum,
1452 ath5k_hw_get_tx_buf(ah,
1453 sc->txqs[i].qnum),
1454 sc->txqs[i].link);
1455 }
1456 }
36d6825b 1457 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1458
1459 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1460 if (sc->txqs[i].setup)
1461 ath5k_txq_drainq(sc, &sc->txqs[i]);
1462}
1463
1464static void
1465ath5k_txq_release(struct ath5k_softc *sc)
1466{
1467 struct ath5k_txq *txq = sc->txqs;
1468 unsigned int i;
1469
1470 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1471 if (txq->setup) {
1472 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1473 txq->setup = false;
1474 }
1475}
1476
1477
1478
1479
1480/*************\
1481* RX Handling *
1482\*************/
1483
1484/*
1485 * Enable the receive h/w following a reset.
1486 */
1487static int
1488ath5k_rx_start(struct ath5k_softc *sc)
1489{
1490 struct ath5k_hw *ah = sc->ah;
1491 struct ath5k_buf *bf;
1492 int ret;
1493
1494 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1495
1496 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1497 sc->cachelsz, sc->rxbufsize);
1498
1499 sc->rxlink = NULL;
1500
1501 spin_lock_bh(&sc->rxbuflock);
1502 list_for_each_entry(bf, &sc->rxbuf, list) {
1503 ret = ath5k_rxbuf_setup(sc, bf);
1504 if (ret != 0) {
1505 spin_unlock_bh(&sc->rxbuflock);
1506 goto err;
1507 }
1508 }
1509 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1510 spin_unlock_bh(&sc->rxbuflock);
1511
1512 ath5k_hw_put_rx_buf(ah, bf->daddr);
1513 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1514 ath5k_mode_setup(sc); /* set filters, etc. */
1515 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1516
1517 return 0;
1518err:
1519 return ret;
1520}
1521
1522/*
1523 * Disable the receive h/w in preparation for a reset.
1524 */
1525static void
1526ath5k_rx_stop(struct ath5k_softc *sc)
1527{
1528 struct ath5k_hw *ah = sc->ah;
1529
1530 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1531 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1532 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1533
1534 ath5k_debug_printrxbuffs(sc, ah);
1535
1536 sc->rxlink = NULL; /* just in case */
1537}
1538
1539static unsigned int
1540ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1541 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1542{
1543 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1544 unsigned int keyix, hlen;
fa1c114f 1545
b47f407b
BR		 1546 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1547 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1548 return RX_FLAG_DECRYPTED;
1549
1550 /* Apparently when a default key is used to decrypt the packet
1551 the hw does not set the index used to decrypt. In such cases
1552 get the index from the packet. */
798ee985 1553 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1554 if (ieee80211_has_protected(hdr->frame_control) &&
1555 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1556 skb->len >= hlen + 4) {
fa1c114f
JS		 1557 keyix = skb->data[hlen + 3] >> 6;
1558
1559 if (test_bit(keyix, sc->keymap))
1560 return RX_FLAG_DECRYPTED;
1561 }
1562
1563 return 0;
1564}
1565
036cd1ec
BR		 1566
1567static void
6ba81c2c
BR		 1568ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1569 struct ieee80211_rx_status *rxs)
036cd1ec 1570{
6ba81c2c 1571 u64 tsf, bc_tstamp;
036cd1ec
BR		 1572 u32 hw_tu;
1573 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1574
24b56e70 1575 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1576 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1577 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1578 /*
6ba81c2c
BR		 1579 * Received an IBSS beacon with the same BSSID. Hardware *must*
1580 * have updated the local TSF. We have to work around various
1581 * hardware bugs, though...
036cd1ec 1582 */
6ba81c2c
BR		 1583 tsf = ath5k_hw_get_tsf64(sc->ah);
1584 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1585 hw_tu = TSF_TO_TU(tsf);
1586
1587 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1588 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1589 (unsigned long long)bc_tstamp,
1590 (unsigned long long)rxs->mactime,
1591 (unsigned long long)(rxs->mactime - bc_tstamp),
1592 (unsigned long long)tsf);
6ba81c2c
BR		 1593
1594 /*
1595 * Sometimes the HW will give us a wrong tstamp in the rx
1596 * status, causing the timestamp extension to go wrong.
1597 * (This seems to happen especially with beacon frames bigger
1598 * than 78 byte (incl. FCS))
1599 * But we know that the receive timestamp must be later than the
1600 * timestamp of the beacon since HW must have synced to that.
1601 *
1602 * NOTE: here we assume mactime to be after the frame was
1603 * received, not like mac80211 which defines it at the start.
1604 */
1605 if (bc_tstamp > rxs->mactime) {
036cd1ec 1606 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1607 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1608 (unsigned long long)rxs->mactime,
1609 (unsigned long long)tsf);
6ba81c2c 1610 rxs->mactime = tsf;
036cd1ec 1611 }
6ba81c2c
BR		 1612
1613 /*
1614 * Local TSF might have moved higher than our beacon timers,
1615 * in that case we have to update them to continue sending
1616 * beacons. This also takes care of synchronizing beacon sending
1617 * times with other stations.
1618 */
1619 if (hw_tu >= sc->nexttbtt)
1620 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1621 }
1622}
1623
1624
fa1c114f
JS		 1625static void
1626ath5k_tasklet_rx(unsigned long data)
1627{
1628 struct ieee80211_rx_status rxs = {};
b47f407b 1629 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1630 struct sk_buff *skb;
1631 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1632 struct ath5k_buf *bf, *bf_last;
fa1c114f 1633 struct ath5k_desc *ds;
fa1c114f
JS		 1634 int ret;
1635 int hdrlen;
1636 int pad;
1637
1638 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1639 if (list_empty(&sc->rxbuf)) {
1640 ATH5K_WARN(sc, "empty rx buf pool\n");
1641 goto unlock;
1642 }
1643 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1644 do {
d6894b5b
BC		 1645 rxs.flag = 0;
1646
fa1c114f
JS		 1647 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1648 BUG_ON(bf->skb == NULL);
1649 skb = bf->skb;
1650 ds = bf->desc;
1651
3a0f2c87
JS		 1652 /*
1653 * last buffer must not be freed to ensure proper hardware
1654 * function. When the hardware finishes also a packet next to
1655 * it, we are sure, it doesn't use it anymore and we can go on.
1656 */
1657 if (bf_last == bf)
1658 bf->flags |= 1;
1659 if (bf->flags) {
1660 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1661 struct ath5k_buf, list);
1662 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1663 &rs);
1664 if (ret)
1665 break;
1666 bf->flags &= ~1;
1667 /* skip the overwritten one (even status is martian) */
1668 goto next;
1669 }
fa1c114f 1670
b47f407b 1671 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1672 if (unlikely(ret == -EINPROGRESS))
1673 break;
1674 else if (unlikely(ret)) {
1675 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1676 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1677 return;
1678 }
1679
b47f407b 1680 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1681 ATH5K_WARN(sc, "unsupported jumbo\n");
1682 goto next;
1683 }
1684
b47f407b
BR		 1685 if (unlikely(rs.rs_status)) {
1686 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1687 goto next;
b47f407b 1688 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1689 /*
1690 * Decrypt error. If the error occurred
1691 * because there was no hardware key, then
1692 * let the frame through so the upper layers
1693 * can process it. This is necessary for 5210
1694 * parts which have no way to setup a ``clear''
1695 * key cache entry.
1696 *
1697 * XXX do key cache faulting
1698 */
b47f407b
BR		 1699 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1700 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1701 goto accept;
1702 }
b47f407b 1703 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1704 rxs.flag |= RX_FLAG_MMIC_ERROR;
1705 goto accept;
1706 }
1707
1708 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1709 if ((rs.rs_status &
1710 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
fa1c114f
JS		 1711 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1712 goto next;
1713 }
1714accept:
fa1c114f
JS		 1715 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1716 PCI_DMA_FROMDEVICE);
1717 bf->skb = NULL;
1718
b47f407b 1719 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1720
1721 /*
1722 * the hardware adds a padding to 4 byte boundaries between
1723 * the header and the payload data if the header length is
1724 * not multiples of 4 - remove it
1725 */
1726 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1727 if (hdrlen & 3) {
1728 pad = hdrlen % 4;
1729 memmove(skb->data + pad, skb->data, hdrlen);
1730 skb_pull(skb, pad);
1731 }
1732
c0e1899b
BR		 1733 /*
1734 * always extend the mac timestamp, since this information is
1735 * also needed for proper IBSS merging.
1736 *
1737 * XXX: it might be too late to do it here, since rs_tstamp is
1738 * 15bit only. that means TSF extension has to be done within
1739 * 32768usec (about 32ms). it might be necessary to move this to
1740 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1741 *
1742 * Unfortunately we don't know when the hardware takes the rx
1743 * timestamp (beginning of phy frame, data frame, end of rx?).
1744 * The only thing we know is that it is hardware specific...
1745 * On AR5213 it seems the rx timestamp is at the end of the
1746 * frame, but i'm not sure.
1747 *
1748 * NOTE: mac80211 defines mactime at the beginning of the first
1749 * data symbol. Since we don't have any time references it's
1750 * impossible to comply to that. This affects IBSS merge only
1751 * right now, so it's not too bad...
c0e1899b 1752 */
b47f407b 1753 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1754 rxs.flag |= RX_FLAG_TSFT;
1755
d8ee398d
LR		 1756 rxs.freq = sc->curchan->center_freq;
1757 rxs.band = sc->curband->band;
fa1c114f 1758
fa1c114f 1759 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1760 rxs.signal = rxs.noise + rs.rs_rssi;
1761 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1762
b47f407b
BR		 1763 rxs.antenna = rs.rs_antenna;
1764 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1765 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1766
06303352
BR		 1767 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1768 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1769 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1770
fa1c114f
JS		 1771 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1772
036cd1ec
BR		 1773 /* check beacons in IBSS mode */
1774 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
6ba81c2c 1775 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1776
fa1c114f 1777 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1778next:
1779 list_move_tail(&bf->list, &sc->rxbuf);
1780 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1781unlock:
fa1c114f
JS		 1782 spin_unlock(&sc->rxbuflock);
1783}
1784
1785
1786
1787
1788/*************\
1789* TX Handling *
1790\*************/
1791
1792static void
1793ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1794{
b47f407b 1795 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1796 struct ath5k_buf *bf, *bf0;
1797 struct ath5k_desc *ds;
1798 struct sk_buff *skb;
e039fa4a 1799 struct ieee80211_tx_info *info;
fa1c114f
JS		 1800 int ret;
1801
1802 spin_lock(&txq->lock);
1803 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1804 ds = bf->desc;
1805
b47f407b 1806 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1807 if (unlikely(ret == -EINPROGRESS))
1808 break;
1809 else if (unlikely(ret)) {
1810 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1811 ret, txq->qnum);
1812 break;
1813 }
1814
1815 skb = bf->skb;
a888d52d 1816 info = IEEE80211_SKB_CB(skb);
fa1c114f 1817 bf->skb = NULL;
e039fa4a 1818
fa1c114f
JS		 1819 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1820 PCI_DMA_TODEVICE);
1821
e039fa4a 1822 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1823 if (unlikely(ts.ts_status)) {
fa1c114f 1824 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1825 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1826 info->status.excessive_retries = 1;
b47f407b 1827 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1828 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1829 } else {
e039fa4a
JB		 1830 info->flags |= IEEE80211_TX_STAT_ACK;
1831 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1832 }
1833
e039fa4a 1834 ieee80211_tx_status(sc->hw, skb);
57ffc589 1835 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1836
1837 spin_lock(&sc->txbuflock);
57ffc589 1838 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1839 list_move_tail(&bf->list, &sc->txbuf);
1840 sc->txbuf_len++;
1841 spin_unlock(&sc->txbuflock);
1842 }
1843 if (likely(list_empty(&txq->q)))
1844 txq->link = NULL;
1845 spin_unlock(&txq->lock);
1846 if (sc->txbuf_len > ATH_TXBUF / 5)
1847 ieee80211_wake_queues(sc->hw);
1848}
1849
1850static void
1851ath5k_tasklet_tx(unsigned long data)
1852{
1853 struct ath5k_softc *sc = (void *)data;
1854
1855 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1856}
1857
1858
fa1c114f
JS		 1859/*****************\
1860* Beacon handling *
1861\*****************/
1862
1863/*
1864 * Setup the beacon frame for transmit.
1865 */
1866static int
e039fa4a 1867ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1868{
1869 struct sk_buff *skb = bf->skb;
a888d52d 1870 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1871 struct ath5k_hw *ah = sc->ah;
1872 struct ath5k_desc *ds;
1873 int ret, antenna = 0;
1874 u32 flags;
1875
1876 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1877 PCI_DMA_TODEVICE);
1878 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1879 "skbaddr %llx\n", skb, skb->data, skb->len,
1880 (unsigned long long)bf->skbaddr);
8d8bb39b 1881 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1882 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1883 return -EIO;
1884 }
1885
1886 ds = bf->desc;
1887
1888 flags = AR5K_TXDESC_NOACK;
1889 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1890 ds->ds_link = bf->daddr; /* self-linked */
1891 flags |= AR5K_TXDESC_VEOL;
1892 /*
1893 * Let hardware handle antenna switching if txantenna is not set
1894 */
1895 } else {
1896 ds->ds_link = 0;
1897 /*
1898 * Switch antenna every 4 beacons if txantenna is not set
1899 * XXX assumes two antennas
1900 */
1901 if (antenna == 0)
1902 antenna = sc->bsent & 4 ? 2 : 1;
1903 }
1904
1905 ds->ds_data = bf->skbaddr;
281c56dd 1906 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1907 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1908 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1909 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1910 1, AR5K_TXKEYIX_INVALID,
400ec45a 1911 antenna, flags, 0, 0);
fa1c114f
JS		 1912 if (ret)
1913 goto err_unmap;
1914
1915 return 0;
1916err_unmap:
1917 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1918 return ret;
1919}
1920
1921/*
1922 * Transmit a beacon frame at SWBA. Dynamic updates to the
1923 * frame contents are done as needed and the slot time is
1924 * also adjusted based on current state.
1925 *
1926 * this is usually called from interrupt context (ath5k_intr())
1927 * but also from ath5k_beacon_config() in IBSS mode which in turn
1928 * can be called from a tasklet and user context
1929 */
1930static void
1931ath5k_beacon_send(struct ath5k_softc *sc)
1932{
1933 struct ath5k_buf *bf = sc->bbuf;
1934 struct ath5k_hw *ah = sc->ah;
1935
be9b7259 1936 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 1937
1938 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1939 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1940 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1941 return;
1942 }
1943 /*
1944 * Check if the previous beacon has gone out. If
1945 * not don't don't try to post another, skip this
1946 * period and wait for the next. Missed beacons
1947 * indicate a problem and should not occur. If we
1948 * miss too many consecutive beacons reset the device.
1949 */
1950 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1951 sc->bmisscount++;
be9b7259 1952 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1953 "missed %u consecutive beacons\n", sc->bmisscount);
1954 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 1955 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1956 "stuck beacon time (%u missed)\n",
1957 sc->bmisscount);
1958 tasklet_schedule(&sc->restq);
1959 }
1960 return;
1961 }
1962 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1963 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1964 "resume beacon xmit after %u misses\n",
1965 sc->bmisscount);
1966 sc->bmisscount = 0;
1967 }
1968
1969 /*
1970 * Stop any current dma and put the new frame on the queue.
1971 * This should never fail since we check above that no frames
1972 * are still pending on the queue.
1973 */
1974 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1975 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1976 /* NB: hw still stops DMA, so proceed */
1977 }
fa1c114f
JS		 1978
1979 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
1980 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 1981 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1982 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1983
1984 sc->bsent++;
1985}
1986
1987
9804b98d
BR		 1988/**
1989 * ath5k_beacon_update_timers - update beacon timers
1990 *
1991 * @sc: struct ath5k_softc pointer we are operating on
1992 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1993 * beacon timer update based on the current HW TSF.
1994 *
1995 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1996 * of a received beacon or the current local hardware TSF and write it to the
1997 * beacon timer registers.
1998 *
1999 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2000 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2001 * when we otherwise know we have to update the timers, but we keep it in this
2002 * function to have it all together in one place.
2003 */
fa1c114f 2004static void
9804b98d 2005ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2006{
2007 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2008 u32 nexttbtt, intval, hw_tu, bc_tu;
2009 u64 hw_tsf;
fa1c114f
JS		 2010
2011 intval = sc->bintval & AR5K_BEACON_PERIOD;
2012 if (WARN_ON(!intval))
2013 return;
2014
9804b98d
BR		 2015 /* beacon TSF converted to TU */
2016 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2017
9804b98d
BR		 2018 /* current TSF converted to TU */
2019 hw_tsf = ath5k_hw_get_tsf64(ah);
2020 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2021
9804b98d
BR		 2022#define FUDGE 3
2023 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2024 if (bc_tsf == -1) {
2025 /*
2026 * no beacons received, called internally.
2027 * just need to refresh timers based on HW TSF.
2028 */
2029 nexttbtt = roundup(hw_tu + FUDGE, intval);
2030 } else if (bc_tsf == 0) {
2031 /*
2032 * no beacon received, probably called by ath5k_reset_tsf().
2033 * reset TSF to start with 0.
2034 */
2035 nexttbtt = intval;
2036 intval |= AR5K_BEACON_RESET_TSF;
2037 } else if (bc_tsf > hw_tsf) {
2038 /*
2039 * beacon received, SW merge happend but HW TSF not yet updated.
2040 * not possible to reconfigure timers yet, but next time we
2041 * receive a beacon with the same BSSID, the hardware will
2042 * automatically update the TSF and then we need to reconfigure
2043 * the timers.
2044 */
2045 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2046 "need to wait for HW TSF sync\n");
2047 return;
2048 } else {
2049 /*
2050 * most important case for beacon synchronization between STA.
2051 *
2052 * beacon received and HW TSF has been already updated by HW.
2053 * update next TBTT based on the TSF of the beacon, but make
2054 * sure it is ahead of our local TSF timer.
2055 */
2056 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2057 }
2058#undef FUDGE
fa1c114f 2059
036cd1ec
BR		 2060 sc->nexttbtt = nexttbtt;
2061
fa1c114f 2062 intval |= AR5K_BEACON_ENA;
fa1c114f 2063 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2064
2065 /*
2066 * debugging output last in order to preserve the time critical aspect
2067 * of this function
2068 */
2069 if (bc_tsf == -1)
2070 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2071 "reconfigured timers based on HW TSF\n");
2072 else if (bc_tsf == 0)
2073 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2074 "reset HW TSF and timers\n");
2075 else
2076 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2077 "updated timers based on beacon TSF\n");
2078
2079 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2080 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2081 (unsigned long long) bc_tsf,
2082 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2083 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2084 intval & AR5K_BEACON_PERIOD,
2085 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2086 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2087}
2088
2089
036cd1ec
BR		 2090/**
2091 * ath5k_beacon_config - Configure the beacon queues and interrupts
2092 *
2093 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2094 *
2095 * When operating in station mode we want to receive a BMISS interrupt when we
2096 * stop seeing beacons from the AP we've associated with so we can look for
2097 * another AP to associate with.
2098 *
036cd1ec 2099 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2100 * interrupts to detect TSF updates only.
036cd1ec
BR		 2101 *
2102 * AP mode is missing.
fa1c114f
JS		 2103 */
2104static void
2105ath5k_beacon_config(struct ath5k_softc *sc)
2106{
2107 struct ath5k_hw *ah = sc->ah;
2108
2109 ath5k_hw_set_intr(ah, 0);
2110 sc->bmisscount = 0;
dc1968e7 2111 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f
JS		 2112
2113 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2114 sc->imask |= AR5K_INT_BMISS;
2115 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2116 /*
036cd1ec
BR		 2117 * In IBSS mode we use a self-linked tx descriptor and let the
2118 * hardware send the beacons automatically. We have to load it
fa1c114f 2119 * only once here.
036cd1ec 2120 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2121 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2122 */
2123 ath5k_beaconq_config(sc);
fa1c114f 2124
036cd1ec
BR		 2125 sc->imask |= AR5K_INT_SWBA;
2126
00482973
JS		 2127 if (ath5k_hw_hasveol(ah)) {
2128 spin_lock(&sc->block);
fa1c114f 2129 ath5k_beacon_send(sc);
00482973
JS		 2130 spin_unlock(&sc->block);
2131 }
fa1c114f
JS		 2132 }
2133 /* TODO else AP */
2134
2135 ath5k_hw_set_intr(ah, sc->imask);
2136}
2137
2138
2139/********************\
2140* Interrupt handling *
2141\********************/
2142
2143static int
2144ath5k_init(struct ath5k_softc *sc)
2145{
2146 int ret;
2147
2148 mutex_lock(&sc->lock);
2149
2150 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2151
2152 /*
2153 * Stop anything previously setup. This is safe
2154 * no matter this is the first time through or not.
2155 */
2156 ath5k_stop_locked(sc);
2157
2158 /*
2159 * The basic interface to setting the hardware in a good
2160 * state is ``reset''. On return the hardware is known to
2161 * be powered up and with interrupts disabled. This must
2162 * be followed by initialization of the appropriate bits
2163 * and then setup of the interrupt mask.
2164 */
d8ee398d
LR		 2165 sc->curchan = sc->hw->conf.channel;
2166 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f 2167 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2168 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2169 AR5K_INT_MIB;
d7dc1003
JS		 2170 ret = ath5k_reset(sc, false, false);
2171 if (ret)
2172 goto done;
fa1c114f 2173
fa1c114f
JS		 2174 /* Set ack to be sent at low bit-rates */
2175 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2176
2177 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2178 msecs_to_jiffies(ath5k_calinterval * 1000)));
2179
2180 ret = 0;
2181done:
274c7c36 2182 mmiowb();
fa1c114f
JS		 2183 mutex_unlock(&sc->lock);
2184 return ret;
2185}
2186
2187static int
2188ath5k_stop_locked(struct ath5k_softc *sc)
2189{
2190 struct ath5k_hw *ah = sc->ah;
2191
2192 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2193 test_bit(ATH_STAT_INVALID, sc->status));
2194
2195 /*
2196 * Shutdown the hardware and driver:
2197 * stop output from above
2198 * disable interrupts
2199 * turn off timers
2200 * turn off the radio
2201 * clear transmit machinery
2202 * clear receive machinery
2203 * drain and release tx queues
2204 * reclaim beacon resources
2205 * power down hardware
2206 *
2207 * Note that some of this work is not possible if the
2208 * hardware is gone (invalid).
2209 */
2210 ieee80211_stop_queues(sc->hw);
2211
2212 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2213 ath5k_led_off(sc);
fa1c114f 2214 ath5k_hw_set_intr(ah, 0);
274c7c36 2215 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2216 }
2217 ath5k_txq_cleanup(sc);
2218 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2219 ath5k_rx_stop(sc);
2220 ath5k_hw_phy_disable(ah);
2221 } else
2222 sc->rxlink = NULL;
2223
2224 return 0;
2225}
2226
2227/*
2228 * Stop the device, grabbing the top-level lock to protect
2229 * against concurrent entry through ath5k_init (which can happen
2230 * if another thread does a system call and the thread doing the
2231 * stop is preempted).
2232 */
2233static int
2234ath5k_stop_hw(struct ath5k_softc *sc)
2235{
2236 int ret;
2237
2238 mutex_lock(&sc->lock);
2239 ret = ath5k_stop_locked(sc);
2240 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2241 /*
2242 * Set the chip in full sleep mode. Note that we are
2243 * careful to do this only when bringing the interface
2244 * completely to a stop. When the chip is in this state
2245 * it must be carefully woken up or references to
2246 * registers in the PCI clock domain may freeze the bus
2247 * (and system). This varies by chip and is mostly an
2248 * issue with newer parts that go to sleep more quickly.
2249 */
2250 if (sc->ah->ah_mac_srev >= 0x78) {
2251 /*
2252 * XXX
2253 * don't put newer MAC revisions > 7.8 to sleep because
2254 * of the above mentioned problems
2255 */
2256 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2257 "not putting device to sleep\n");
2258 } else {
2259 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2260 "putting device to full sleep\n");
2261 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2262 }
2263 }
2264 ath5k_txbuf_free(sc, sc->bbuf);
274c7c36 2265 mmiowb();
fa1c114f
JS		 2266 mutex_unlock(&sc->lock);
2267
2268 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2269 tasklet_kill(&sc->rxtq);
2270 tasklet_kill(&sc->txtq);
2271 tasklet_kill(&sc->restq);
fa1c114f
JS		 2272
2273 return ret;
2274}
2275
2276static irqreturn_t
2277ath5k_intr(int irq, void *dev_id)
2278{
2279 struct ath5k_softc *sc = dev_id;
2280 struct ath5k_hw *ah = sc->ah;
2281 enum ath5k_int status;
2282 unsigned int counter = 1000;
2283
2284 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2285 !ath5k_hw_is_intr_pending(ah)))
2286 return IRQ_NONE;
2287
2288 do {
2289 /*
2290 * Figure out the reason(s) for the interrupt. Note
2291 * that get_isr returns a pseudo-ISR that may include
2292 * bits we haven't explicitly enabled so we mask the
2293 * value to insure we only process bits we requested.
2294 */
2295 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2296 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2297 status, sc->imask);
2298 status &= sc->imask; /* discard unasked for bits */
2299 if (unlikely(status & AR5K_INT_FATAL)) {
2300 /*
2301 * Fatal errors are unrecoverable.
2302 * Typically these are caused by DMA errors.
2303 */
2304 tasklet_schedule(&sc->restq);
2305 } else if (unlikely(status & AR5K_INT_RXORN)) {
2306 tasklet_schedule(&sc->restq);
2307 } else {
2308 if (status & AR5K_INT_SWBA) {
2309 /*
2310 * Software beacon alert--time to send a beacon.
2311 * Handle beacon transmission directly; deferring
2312 * this is too slow to meet timing constraints
2313 * under load.
036cd1ec
BR		 2314 *
2315 * In IBSS mode we use this interrupt just to
2316 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2317 * transmission time) in order to detect wether
2318 * automatic TSF updates happened.
fa1c114f 2319 */
036cd1ec
BR		 2320 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2321 /* XXX: only if VEOL suppported */
2322 u64 tsf = ath5k_hw_get_tsf64(ah);
2323 sc->nexttbtt += sc->bintval;
2324 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2325 "SWBA nexttbtt: %x hw_tu: %x "
2326 "TSF: %llx\n",
2327 sc->nexttbtt,
2328 TSF_TO_TU(tsf),
2329 (unsigned long long) tsf);
036cd1ec 2330 } else {
00482973 2331 spin_lock(&sc->block);
036cd1ec 2332 ath5k_beacon_send(sc);
00482973 2333 spin_unlock(&sc->block);
036cd1ec 2334 }
fa1c114f
JS		 2335 }
2336 if (status & AR5K_INT_RXEOL) {
2337 /*
2338 * NB: the hardware should re-read the link when
2339 * RXE bit is written, but it doesn't work at
2340 * least on older hardware revs.
2341 */
2342 sc->rxlink = NULL;
2343 }
2344 if (status & AR5K_INT_TXURN) {
2345 /* bump tx trigger level */
2346 ath5k_hw_update_tx_triglevel(ah, true);
2347 }
2348 if (status & AR5K_INT_RX)
2349 tasklet_schedule(&sc->rxtq);
2350 if (status & AR5K_INT_TX)
2351 tasklet_schedule(&sc->txtq);
2352 if (status & AR5K_INT_BMISS) {
2353 }
2354 if (status & AR5K_INT_MIB) {
194828a2
NK		 2355 /*
2356 * These stats are also used for ANI i think
2357 * so how about updating them more often ?
2358 */
2359 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2360 }
2361 }
2362 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2363
2364 if (unlikely(!counter))
2365 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2366
2367 return IRQ_HANDLED;
2368}
2369
2370static void
2371ath5k_tasklet_reset(unsigned long data)
2372{
2373 struct ath5k_softc *sc = (void *)data;
2374
d7dc1003 2375 ath5k_reset_wake(sc);
fa1c114f
JS		 2376}
2377
2378/*
2379 * Periodically recalibrate the PHY to account
2380 * for temperature/environment changes.
2381 */
2382static void
2383ath5k_calibrate(unsigned long data)
2384{
2385 struct ath5k_softc *sc = (void *)data;
2386 struct ath5k_hw *ah = sc->ah;
2387
2388 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2389 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2390 sc->curchan->hw_value);
fa1c114f
JS		 2391
2392 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2393 /*
2394 * Rfgain is out of bounds, reset the chip
2395 * to load new gain values.
2396 */
2397 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2398 ath5k_reset_wake(sc);
fa1c114f
JS		 2399 }
2400 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2401 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2402 ieee80211_frequency_to_channel(
2403 sc->curchan->center_freq));
fa1c114f
JS		 2404
2405 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2406 msecs_to_jiffies(ath5k_calinterval * 1000)));
2407}
2408
2409
2410
2411/***************\
2412* LED functions *
2413\***************/
2414
2415static void
3a078876 2416ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2417{
3a078876
BC		 2418 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2419 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2420 ath5k_led_off(sc);
fa1c114f
JS		 2421 }
2422}
2423
fa1c114f 2424static void
3a078876 2425ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2426{
3a078876
BC		 2427 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2428 return;
fa1c114f 2429 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2430}
2431
2432static void
3a078876 2433ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2434{
3a078876 2435 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2436 return;
3a078876
BC		 2437 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2438}
2439
2440static void
2441ath5k_led_brightness_set(struct led_classdev *led_dev,
2442 enum led_brightness brightness)
2443{
2444 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2445 led_dev);
2446
2447 if (brightness == LED_OFF)
2448 ath5k_led_off(led->sc);
2449 else
2450 ath5k_led_on(led->sc);
2451}
2452
2453static int
2454ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2455 const char *name, char *trigger)
2456{
2457 int err;
2458
2459 led->sc = sc;
2460 strncpy(led->name, name, sizeof(led->name));
2461 led->led_dev.name = led->name;
2462 led->led_dev.default_trigger = trigger;
2463 led->led_dev.brightness_set = ath5k_led_brightness_set;
2464
2465 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2466 if (err)
2467 {
2468 ATH5K_WARN(sc, "could not register LED %s\n", name);
2469 led->sc = NULL;
fa1c114f 2470 }
3a078876 2471 return err;
fa1c114f
JS		 2472}
2473
3a078876
BC		 2474static void
2475ath5k_unregister_led(struct ath5k_led *led)
2476{
2477 if (!led->sc)
2478 return;
2479 led_classdev_unregister(&led->led_dev);
2480 ath5k_led_off(led->sc);
2481 led->sc = NULL;
2482}
2483
2484static void
2485ath5k_unregister_leds(struct ath5k_softc *sc)
2486{
2487 ath5k_unregister_led(&sc->rx_led);
2488 ath5k_unregister_led(&sc->tx_led);
2489}
2490
2491
2492static int
2493ath5k_init_leds(struct ath5k_softc *sc)
2494{
2495 int ret = 0;
2496 struct ieee80211_hw *hw = sc->hw;
2497 struct pci_dev *pdev = sc->pdev;
2498 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2499
3a078876
BC		 2500 /*
2501 * Auto-enable soft led processing for IBM cards and for
2502 * 5211 minipci cards.
2503 */
2504 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2505 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2506 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2507 sc->led_pin = 0;
734b5aa9 2508 sc->led_on = 0; /* active low */
3a078876
BC		 2509 }
2510 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2511 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2512 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2513 sc->led_pin = 1;
734b5aa9 2514 sc->led_on = 1; /* active high */
3a078876
BC		 2515 }
2516 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2517 goto out;
2518
2519 ath5k_led_enable(sc);
2520
2521 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2522 ret = ath5k_register_led(sc, &sc->rx_led, name,
2523 ieee80211_get_rx_led_name(hw));
2524 if (ret)
2525 goto out;
2526
2527 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2528 ret = ath5k_register_led(sc, &sc->tx_led, name,
2529 ieee80211_get_tx_led_name(hw));
2530out:
2531 return ret;
2532}
fa1c114f
JS		 2533
2534
2535/********************\
2536* Mac80211 functions *
2537\********************/
2538
2539static int
e039fa4a 2540ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2541{
2542 struct ath5k_softc *sc = hw->priv;
2543 struct ath5k_buf *bf;
2544 unsigned long flags;
2545 int hdrlen;
2546 int pad;
2547
2548 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2549
2550 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2551 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2552
2553 /*
2554 * the hardware expects the header padded to 4 byte boundaries
2555 * if this is not the case we add the padding after the header
2556 */
2557 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2558 if (hdrlen & 3) {
2559 pad = hdrlen % 4;
2560 if (skb_headroom(skb) < pad) {
2561 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2562 " headroom to pad %d\n", hdrlen, pad);
2563 return -1;
2564 }
2565 skb_push(skb, pad);
2566 memmove(skb->data, skb->data+pad, hdrlen);
2567 }
2568
fa1c114f
JS		 2569 spin_lock_irqsave(&sc->txbuflock, flags);
2570 if (list_empty(&sc->txbuf)) {
2571 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2572 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2573 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2574 return -1;
2575 }
2576 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2577 list_del(&bf->list);
2578 sc->txbuf_len--;
2579 if (list_empty(&sc->txbuf))
2580 ieee80211_stop_queues(hw);
2581 spin_unlock_irqrestore(&sc->txbuflock, flags);
2582
2583 bf->skb = skb;
2584
e039fa4a 2585 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2586 bf->skb = NULL;
2587 spin_lock_irqsave(&sc->txbuflock, flags);
2588 list_add_tail(&bf->list, &sc->txbuf);
2589 sc->txbuf_len++;
2590 spin_unlock_irqrestore(&sc->txbuflock, flags);
2591 dev_kfree_skb_any(skb);
2592 return 0;
2593 }
2594
2595 return 0;
2596}
2597
2598static int
d7dc1003 2599ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2600{
fa1c114f
JS		 2601 struct ath5k_hw *ah = sc->ah;
2602 int ret;
2603
2604 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2605
d7dc1003
JS		 2606 if (stop) {
2607 ath5k_hw_set_intr(ah, 0);
2608 ath5k_txq_cleanup(sc);
2609 ath5k_rx_stop(sc);
2610 }
fa1c114f 2611 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2612 if (ret) {
fa1c114f
JS		 2613 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2614 goto err;
2615 }
d7dc1003
JS		 2616
2617 /*
2618 * This is needed only to setup initial state
2619 * but it's best done after a reset.
2620 */
fa1c114f
JS		 2621 ath5k_hw_set_txpower_limit(sc->ah, 0);
2622
2623 ret = ath5k_rx_start(sc);
d7dc1003 2624 if (ret) {
fa1c114f
JS		 2625 ATH5K_ERR(sc, "can't start recv logic\n");
2626 goto err;
2627 }
d7dc1003 2628
fa1c114f 2629 /*
d7dc1003
JS		 2630 * Change channels and update the h/w rate map if we're switching;
2631 * e.g. 11a to 11b/g.
2632 *
2633 * We may be doing a reset in response to an ioctl that changes the
2634 * channel so update any state that might change as a result.
fa1c114f
JS		 2635 *
2636 * XXX needed?
2637 */
2638/* ath5k_chan_change(sc, c); */
fa1c114f 2639
d7dc1003
JS		 2640 ath5k_beacon_config(sc);
2641 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2642
2643 return 0;
2644err:
2645 return ret;
2646}
2647
d7dc1003
JS		 2648static int
2649ath5k_reset_wake(struct ath5k_softc *sc)
2650{
2651 int ret;
2652
2653 ret = ath5k_reset(sc, true, true);
2654 if (!ret)
2655 ieee80211_wake_queues(sc->hw);
2656
2657 return ret;
2658}
2659
fa1c114f
JS		 2660static int ath5k_start(struct ieee80211_hw *hw)
2661{
2662 return ath5k_init(hw->priv);
2663}
2664
2665static void ath5k_stop(struct ieee80211_hw *hw)
2666{
2667 ath5k_stop_hw(hw->priv);
2668}
2669
2670static int ath5k_add_interface(struct ieee80211_hw *hw,
2671 struct ieee80211_if_init_conf *conf)
2672{
2673 struct ath5k_softc *sc = hw->priv;
2674 int ret;
2675
2676 mutex_lock(&sc->lock);
32bfd35d 2677 if (sc->vif) {
fa1c114f
JS		 2678 ret = 0;
2679 goto end;
2680 }
2681
32bfd35d 2682 sc->vif = conf->vif;
fa1c114f
JS		 2683
2684 switch (conf->type) {
2685 case IEEE80211_IF_TYPE_STA:
2686 case IEEE80211_IF_TYPE_IBSS:
2687 case IEEE80211_IF_TYPE_MNTR:
2688 sc->opmode = conf->type;
2689 break;
2690 default:
2691 ret = -EOPNOTSUPP;
2692 goto end;
2693 }
67d2e2df
JS		 2694
2695 /* Set to a reasonable value. Note that this will
2696 * be set to mac80211's value at ath5k_config(). */
2697 sc->bintval = 1000;
2698
fa1c114f
JS		 2699 ret = 0;
2700end:
2701 mutex_unlock(&sc->lock);
2702 return ret;
2703}
2704
2705static void
2706ath5k_remove_interface(struct ieee80211_hw *hw,
2707 struct ieee80211_if_init_conf *conf)
2708{
2709 struct ath5k_softc *sc = hw->priv;
2710
2711 mutex_lock(&sc->lock);
32bfd35d 2712 if (sc->vif != conf->vif)
fa1c114f
JS		 2713 goto end;
2714
32bfd35d 2715 sc->vif = NULL;
fa1c114f
JS		 2716end:
2717 mutex_unlock(&sc->lock);
2718}
2719
d8ee398d
LR		 2720/*
2721 * TODO: Phy disable/diversity etc
2722 */
fa1c114f
JS		 2723static int
2724ath5k_config(struct ieee80211_hw *hw,
2725 struct ieee80211_conf *conf)
2726{
2727 struct ath5k_softc *sc = hw->priv;
2728
e535c1ac 2729 sc->bintval = conf->beacon_int;
d8ee398d 2730 sc->power_level = conf->power_level;
fa1c114f 2731
d8ee398d 2732 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2733}
2734
2735static int
32bfd35d 2736ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2737 struct ieee80211_if_conf *conf)
2738{
2739 struct ath5k_softc *sc = hw->priv;
2740 struct ath5k_hw *ah = sc->ah;
2741 int ret;
2742
fa1c114f 2743 mutex_lock(&sc->lock);
32bfd35d 2744 if (sc->vif != vif) {
fa1c114f
JS		 2745 ret = -EIO;
2746 goto unlock;
2747 }
2748 if (conf->bssid) {
2749 /* Cache for later use during resets */
2750 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2751 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2752 * a clean way of letting us retrieve this yet. */
2753 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2754 mmiowb();
fa1c114f 2755 }
9d139c81
JB		 2756
2757 if (conf->changed & IEEE80211_IFCC_BEACON &&
2758 vif->type == IEEE80211_IF_TYPE_IBSS) {
2759 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2760 if (!beacon) {
2761 ret = -ENOMEM;
2762 goto unlock;
2763 }
2764 /* call old handler for now */
2765 ath5k_beacon_update(hw, beacon);
2766 }
2767
fa1c114f
JS		 2768 mutex_unlock(&sc->lock);
2769
d7dc1003 2770 return ath5k_reset_wake(sc);
fa1c114f
JS		 2771unlock:
2772 mutex_unlock(&sc->lock);
2773 return ret;
2774}
2775
2776#define SUPPORTED_FIF_FLAGS \
2777 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2778 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2779 FIF_BCN_PRBRESP_PROMISC
2780/*
2781 * o always accept unicast, broadcast, and multicast traffic
2782 * o multicast traffic for all BSSIDs will be enabled if mac80211
2783 * says it should be
2784 * o maintain current state of phy ofdm or phy cck error reception.
2785 * If the hardware detects any of these type of errors then
2786 * ath5k_hw_get_rx_filter() will pass to us the respective
2787 * hardware filters to be able to receive these type of frames.
2788 * o probe request frames are accepted only when operating in
2789 * hostap, adhoc, or monitor modes
2790 * o enable promiscuous mode according to the interface state
2791 * o accept beacons:
2792 * - when operating in adhoc mode so the 802.11 layer creates
2793 * node table entries for peers,
2794 * - when operating in station mode for collecting rssi data when
2795 * the station is otherwise quiet, or
2796 * - when scanning
2797 */
2798static void ath5k_configure_filter(struct ieee80211_hw *hw,
2799 unsigned int changed_flags,
2800 unsigned int *new_flags,
2801 int mc_count, struct dev_mc_list *mclist)
2802{
2803 struct ath5k_softc *sc = hw->priv;
2804 struct ath5k_hw *ah = sc->ah;
2805 u32 mfilt[2], val, rfilt;
2806 u8 pos;
2807 int i;
2808
2809 mfilt[0] = 0;
2810 mfilt[1] = 0;
2811
2812 /* Only deal with supported flags */
2813 changed_flags &= SUPPORTED_FIF_FLAGS;
2814 *new_flags &= SUPPORTED_FIF_FLAGS;
2815
2816 /* If HW detects any phy or radar errors, leave those filters on.
2817 * Also, always enable Unicast, Broadcasts and Multicast
2818 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2819 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2820 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2821 AR5K_RX_FILTER_MCAST);
2822
2823 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2824 if (*new_flags & FIF_PROMISC_IN_BSS) {
2825 rfilt |= AR5K_RX_FILTER_PROM;
2826 __set_bit(ATH_STAT_PROMISC, sc->status);
2827 }
2828 else
2829 __clear_bit(ATH_STAT_PROMISC, sc->status);
2830 }
2831
2832 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2833 if (*new_flags & FIF_ALLMULTI) {
2834 mfilt[0] = ~0;
2835 mfilt[1] = ~0;
2836 } else {
2837 for (i = 0; i < mc_count; i++) {
2838 if (!mclist)
2839 break;
2840 /* calculate XOR of eight 6-bit values */
533dd1b0 2841 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2842 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2843 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2844 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2845 pos &= 0x3f;
2846 mfilt[pos / 32] |= (1 << (pos % 32));
2847 /* XXX: we might be able to just do this instead,
2848 * but not sure, needs testing, if we do use this we'd
2849 * neet to inform below to not reset the mcast */
2850 /* ath5k_hw_set_mcast_filterindex(ah,
2851 * mclist->dmi_addr[5]); */
2852 mclist = mclist->next;
2853 }
2854 }
2855
2856 /* This is the best we can do */
2857 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2858 rfilt |= AR5K_RX_FILTER_PHYERR;
2859
2860 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2861 * and probes for any BSSID, this needs testing */
2862 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2863 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2864
2865 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2866 * set we should only pass on control frames for this
2867 * station. This needs testing. I believe right now this
2868 * enables *all* control frames, which is OK.. but
2869 * but we should see if we can improve on granularity */
2870 if (*new_flags & FIF_CONTROL)
2871 rfilt |= AR5K_RX_FILTER_CONTROL;
2872
2873 /* Additional settings per mode -- this is per ath5k */
2874
2875 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2876
2877 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2878 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2879 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2880 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2881 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2882 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
8e5f3d0a 2883 sc->opmode != IEEE80211_IF_TYPE_MESH_POINT &&
fa1c114f
JS		 2884 test_bit(ATH_STAT_PROMISC, sc->status))
2885 rfilt |= AR5K_RX_FILTER_PROM;
2886 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2887 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2888 rfilt |= AR5K_RX_FILTER_BEACON;
2889 }
2890
2891 /* Set filters */
2892 ath5k_hw_set_rx_filter(ah,rfilt);
2893
2894 /* Set multicast bits */
2895 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2896 /* Set the cached hw filter flags, this will alter actually
2897 * be set in HW */
2898 sc->filter_flags = rfilt;
2899}
2900
2901static int
2902ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2903 const u8 *local_addr, const u8 *addr,
2904 struct ieee80211_key_conf *key)
2905{
2906 struct ath5k_softc *sc = hw->priv;
2907 int ret = 0;
2908
2909 switch(key->alg) {
2910 case ALG_WEP:
6844e63a
LR		 2911 /* XXX: fix hardware encryption, its not working. For now
2912 * allow software encryption */
2913 /* break; */
fa1c114f
JS		 2914 case ALG_TKIP:
2915 case ALG_CCMP:
2916 return -EOPNOTSUPP;
2917 default:
2918 WARN_ON(1);
2919 return -EINVAL;
2920 }
2921
2922 mutex_lock(&sc->lock);
2923
2924 switch (cmd) {
2925 case SET_KEY:
2926 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2927 if (ret) {
2928 ATH5K_ERR(sc, "can't set the key\n");
2929 goto unlock;
2930 }
2931 __set_bit(key->keyidx, sc->keymap);
2932 key->hw_key_idx = key->keyidx;
2933 break;
2934 case DISABLE_KEY:
2935 ath5k_hw_reset_key(sc->ah, key->keyidx);
2936 __clear_bit(key->keyidx, sc->keymap);
2937 break;
2938 default:
2939 ret = -EINVAL;
2940 goto unlock;
2941 }
2942
2943unlock:
274c7c36 2944 mmiowb();
fa1c114f
JS		 2945 mutex_unlock(&sc->lock);
2946 return ret;
2947}
2948
2949static int
2950ath5k_get_stats(struct ieee80211_hw *hw,
2951 struct ieee80211_low_level_stats *stats)
2952{
2953 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2954 struct ath5k_hw *ah = sc->ah;
2955
2956 /* Force update */
2957 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2958
2959 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2960
2961 return 0;
2962}
2963
2964static int
2965ath5k_get_tx_stats(struct ieee80211_hw *hw,
2966 struct ieee80211_tx_queue_stats *stats)
2967{
2968 struct ath5k_softc *sc = hw->priv;
2969
2970 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2971
2972 return 0;
2973}
2974
2975static u64
2976ath5k_get_tsf(struct ieee80211_hw *hw)
2977{
2978 struct ath5k_softc *sc = hw->priv;
2979
2980 return ath5k_hw_get_tsf64(sc->ah);
2981}
2982
2983static void
2984ath5k_reset_tsf(struct ieee80211_hw *hw)
2985{
2986 struct ath5k_softc *sc = hw->priv;
2987
9804b98d
BR		 2988 /*
2989 * in IBSS mode we need to update the beacon timers too.
2990 * this will also reset the TSF if we call it with 0
2991 */
2992 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
2993 ath5k_beacon_update_timers(sc, 0);
2994 else
2995 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 2996}
2997
2998static int
e039fa4a 2999ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3000{
3001 struct ath5k_softc *sc = hw->priv;
00482973 3002 unsigned long flags;
fa1c114f
JS		 3003 int ret;
3004
3005 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3006
fa1c114f
JS		 3007 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3008 ret = -EIO;
3009 goto end;
3010 }
3011
00482973 3012 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3013 ath5k_txbuf_free(sc, sc->bbuf);
3014 sc->bbuf->skb = skb;
e039fa4a 3015 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3016 if (ret)
3017 sc->bbuf->skb = NULL;
00482973
JS		 3018 spin_unlock_irqrestore(&sc->block, flags);
3019 if (!ret) {
fa1c114f 3020 ath5k_beacon_config(sc);
274c7c36
JS		 3021 mmiowb();
3022 }
fa1c114f
JS		 3023
3024end:
fa1c114f
JS		 3025 return ret;
3026}
3027
Clone of davem's net-next-2.6 tree