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ath5k: Update reset code
[net-next-2.6.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f
JS		 66
67
68/******************\
69* Internal defines *
70\******************/
71
72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 78MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 79
80
81/* Known PCI ids */
82static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 101 { 0 }
102};
103MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105/* Known SREVs */
106static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143};
144
63266a65
BR		 145static struct ieee80211_rate ath5k_rates[] = {
146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185};
186
fa1c114f
JS		 187/*
188 * Prototypes - PCI stack related functions
189 */
190static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193#ifdef CONFIG_PM
194static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196static int ath5k_pci_resume(struct pci_dev *pdev);
197#else
198#define ath5k_pci_suspend NULL
199#define ath5k_pci_resume NULL
200#endif /* CONFIG_PM */
201
04a9e451 202static struct pci_driver ath5k_pci_driver = {
9764f3f9 203 .name = KBUILD_MODNAME,
fa1c114f
JS		 204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209};
210
211
212
213/*
214 * Prototypes - MAC 802.11 stack related functions
215 */
e039fa4a 216static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 217static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 219static int ath5k_start(struct ieee80211_hw *hw);
220static void ath5k_stop(struct ieee80211_hw *hw);
221static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
e8975581 225static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 226static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
fa1c114f
JS		 228 struct ieee80211_if_conf *conf);
229static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
dc822b5d 235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 236 struct ieee80211_key_conf *key);
237static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 242static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 243static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 244static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 245 struct sk_buff *skb);
02969b38
MX		 246static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
249 u32 changes);
fa1c114f
JS		 250
251static struct ieee80211_ops ath5k_hw_ops = {
252 .tx = ath5k_tx,
253 .start = ath5k_start,
254 .stop = ath5k_stop,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
3b5d665b 265 .set_tsf = ath5k_set_tsf,
fa1c114f 266 .reset_tsf = ath5k_reset_tsf,
02969b38 267 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 268};
269
270/*
271 * Prototypes - Internal functions
272 */
273/* Attach detach */
274static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278/* Channel/mode setup */
279static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 280static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
63266a65 284static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 285static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 290
fa1c114f
JS		 291/* Descriptor setup */
292static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296/* Buffers setup */
297static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 300 struct ath5k_buf *bf);
fa1c114f
JS		 301static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303{
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
00482973 309 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 310 bf->skb = NULL;
311}
312
a6c8d375
FF		 313static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
315{
316 BUG_ON(!bf);
317 if (!bf->skb)
318 return;
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
320 PCI_DMA_FROMDEVICE);
321 dev_kfree_skb_any(bf->skb);
322 bf->skb = NULL;
323}
324
325
fa1c114f
JS		 326/* Queues setup */
327static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330static int ath5k_beaconq_config(struct ath5k_softc *sc);
331static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334static void ath5k_txq_release(struct ath5k_softc *sc);
335/* Rx handling */
336static int ath5k_rx_start(struct ath5k_softc *sc);
337static void ath5k_rx_stop(struct ath5k_softc *sc);
338static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
b47f407b
BR		 340 struct sk_buff *skb,
341 struct ath5k_rx_status *rs);
fa1c114f
JS		 342static void ath5k_tasklet_rx(unsigned long data);
343/* Tx handling */
344static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346static void ath5k_tasklet_tx(unsigned long data);
347/* Beacon handling */
348static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 349 struct ath5k_buf *bf);
fa1c114f
JS		 350static void ath5k_beacon_send(struct ath5k_softc *sc);
351static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 352static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 353
354static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
355{
356 u64 tsf = ath5k_hw_get_tsf64(ah);
357
358 if ((tsf & 0x7fff) < rstamp)
359 tsf -= 0x8000;
360
361 return (tsf & ~0x7fff) | rstamp;
362}
363
364/* Interrupt handling */
bb2becac 365static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 366static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 367static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 368static irqreturn_t ath5k_intr(int irq, void *dev_id);
369static void ath5k_tasklet_reset(unsigned long data);
370
371static void ath5k_calibrate(unsigned long data);
372/* LED functions */
3a078876
BC		 373static int ath5k_init_leds(struct ath5k_softc *sc);
374static void ath5k_led_enable(struct ath5k_softc *sc);
375static void ath5k_led_off(struct ath5k_softc *sc);
376static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 377
378/*
379 * Module init/exit functions
380 */
381static int __init
382init_ath5k_pci(void)
383{
384 int ret;
385
386 ath5k_debug_init();
387
04a9e451 388 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 389 if (ret) {
390 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
391 return ret;
392 }
393
394 return 0;
395}
396
397static void __exit
398exit_ath5k_pci(void)
399{
04a9e451 400 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 401
402 ath5k_debug_finish();
403}
404
405module_init(init_ath5k_pci);
406module_exit(exit_ath5k_pci);
407
408
409/********************\
410* PCI Initialization *
411\********************/
412
413static const char *
414ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
415{
416 const char *name = "xxxxx";
417 unsigned int i;
418
419 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
420 if (srev_names[i].sr_type != type)
421 continue;
75d0edb8
NK		 422
423 if ((val & 0xf0) == srev_names[i].sr_val)
424 name = srev_names[i].sr_name;
425
426 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 427 name = srev_names[i].sr_name;
428 break;
429 }
430 }
431
432 return name;
433}
434
435static int __devinit
436ath5k_pci_probe(struct pci_dev *pdev,
437 const struct pci_device_id *id)
438{
439 void __iomem *mem;
440 struct ath5k_softc *sc;
441 struct ieee80211_hw *hw;
442 int ret;
443 u8 csz;
444
445 ret = pci_enable_device(pdev);
446 if (ret) {
447 dev_err(&pdev->dev, "can't enable device\n");
448 goto err;
449 }
450
451 /* XXX 32-bit addressing only */
452 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
453 if (ret) {
454 dev_err(&pdev->dev, "32-bit DMA not available\n");
455 goto err_dis;
456 }
457
458 /*
459 * Cache line size is used to size and align various
460 * structures used to communicate with the hardware.
461 */
462 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
463 if (csz == 0) {
464 /*
465 * Linux 2.4.18 (at least) writes the cache line size
466 * register as a 16-bit wide register which is wrong.
467 * We must have this setup properly for rx buffer
468 * DMA to work so force a reasonable value here if it
469 * comes up zero.
470 */
471 csz = L1_CACHE_BYTES / sizeof(u32);
472 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
473 }
474 /*
475 * The default setting of latency timer yields poor results,
476 * set it to the value used by other systems. It may be worth
477 * tweaking this setting more.
478 */
479 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
480
481 /* Enable bus mastering */
482 pci_set_master(pdev);
483
484 /*
485 * Disable the RETRY_TIMEOUT register (0x41) to keep
486 * PCI Tx retries from interfering with C3 CPU state.
487 */
488 pci_write_config_byte(pdev, 0x41, 0);
489
490 ret = pci_request_region(pdev, 0, "ath5k");
491 if (ret) {
492 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
493 goto err_dis;
494 }
495
496 mem = pci_iomap(pdev, 0, 0);
497 if (!mem) {
498 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
499 ret = -EIO;
500 goto err_reg;
501 }
502
503 /*
504 * Allocate hw (mac80211 main struct)
505 * and hw->priv (driver private data)
506 */
507 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
508 if (hw == NULL) {
509 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
510 ret = -ENOMEM;
511 goto err_map;
512 }
513
514 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
515
516 /* Initialize driver private data */
517 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 518 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
519 IEEE80211_HW_SIGNAL_DBM |
520 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 521
522 hw->wiphy->interface_modes =
523 BIT(NL80211_IFTYPE_STATION) |
524 BIT(NL80211_IFTYPE_ADHOC) |
525 BIT(NL80211_IFTYPE_MESH_POINT);
526
fa1c114f
JS		 527 hw->extra_tx_headroom = 2;
528 hw->channel_change_time = 5000;
fa1c114f
JS		 529 sc = hw->priv;
530 sc->hw = hw;
531 sc->pdev = pdev;
532
533 ath5k_debug_init_device(sc);
534
535 /*
536 * Mark the device as detached to avoid processing
537 * interrupts until setup is complete.
538 */
539 __set_bit(ATH_STAT_INVALID, sc->status);
540
541 sc->iobase = mem; /* So we can unmap it on detach */
542 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 543 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 544 mutex_init(&sc->lock);
545 spin_lock_init(&sc->rxbuflock);
546 spin_lock_init(&sc->txbuflock);
00482973 547 spin_lock_init(&sc->block);
fa1c114f
JS		 548
549 /* Set private data */
550 pci_set_drvdata(pdev, hw);
551
fa1c114f
JS		 552 /* Setup interrupt handler */
553 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
554 if (ret) {
555 ATH5K_ERR(sc, "request_irq failed\n");
556 goto err_free;
557 }
558
559 /* Initialize device */
560 sc->ah = ath5k_hw_attach(sc, id->driver_data);
561 if (IS_ERR(sc->ah)) {
562 ret = PTR_ERR(sc->ah);
563 goto err_irq;
564 }
565
2f7fe870
FF		 566 /* set up multi-rate retry capabilities */
567 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 568 hw->max_rates = 4;
569 hw->max_rate_tries = 11;
2f7fe870
FF		 570 }
571
fa1c114f
JS		 572 /* Finish private driver data initialization */
573 ret = ath5k_attach(pdev, hw);
574 if (ret)
575 goto err_ah;
576
577 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 578 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 579 sc->ah->ah_mac_srev,
580 sc->ah->ah_phy_revision);
581
400ec45a 582 if (!sc->ah->ah_single_chip) {
fa1c114f 583 /* Single chip radio (!RF5111) */
400ec45a
LR		 584 if (sc->ah->ah_radio_5ghz_revision &&
585 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 586 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 587 if (!test_bit(AR5K_MODE_11A,
588 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 589 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 590 ath5k_chip_name(AR5K_VERSION_RAD,
591 sc->ah->ah_radio_5ghz_revision),
592 sc->ah->ah_radio_5ghz_revision);
593 /* No 2GHz support (5110 and some
594 * 5Ghz only cards) -> report 5Ghz radio */
595 } else if (!test_bit(AR5K_MODE_11B,
596 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 597 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 598 ath5k_chip_name(AR5K_VERSION_RAD,
599 sc->ah->ah_radio_5ghz_revision),
600 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 601 /* Multiband radio */
602 } else {
603 ATH5K_INFO(sc, "RF%s multiband radio found"
604 " (0x%x)\n",
400ec45a
LR		 605 ath5k_chip_name(AR5K_VERSION_RAD,
606 sc->ah->ah_radio_5ghz_revision),
607 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 608 }
609 }
400ec45a
LR		 610 /* Multi chip radio (RF5111 - RF2111) ->
611 * report both 2GHz/5GHz radios */
612 else if (sc->ah->ah_radio_5ghz_revision &&
613 sc->ah->ah_radio_2ghz_revision){
fa1c114f 614 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 615 ath5k_chip_name(AR5K_VERSION_RAD,
616 sc->ah->ah_radio_5ghz_revision),
617 sc->ah->ah_radio_5ghz_revision);
fa1c114f 618 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 619 ath5k_chip_name(AR5K_VERSION_RAD,
620 sc->ah->ah_radio_2ghz_revision),
621 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 622 }
623 }
624
625
626 /* ready to process interrupts */
627 __clear_bit(ATH_STAT_INVALID, sc->status);
628
629 return 0;
630err_ah:
631 ath5k_hw_detach(sc->ah);
632err_irq:
633 free_irq(pdev->irq, sc);
634err_free:
fa1c114f
JS		 635 ieee80211_free_hw(hw);
636err_map:
637 pci_iounmap(pdev, mem);
638err_reg:
639 pci_release_region(pdev, 0);
640err_dis:
641 pci_disable_device(pdev);
642err:
643 return ret;
644}
645
646static void __devexit
647ath5k_pci_remove(struct pci_dev *pdev)
648{
649 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
650 struct ath5k_softc *sc = hw->priv;
651
652 ath5k_debug_finish_device(sc);
653 ath5k_detach(pdev, hw);
654 ath5k_hw_detach(sc->ah);
655 free_irq(pdev->irq, sc);
fa1c114f
JS		 656 pci_iounmap(pdev, sc->iobase);
657 pci_release_region(pdev, 0);
658 pci_disable_device(pdev);
659 ieee80211_free_hw(hw);
660}
661
662#ifdef CONFIG_PM
663static int
664ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
665{
666 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
667 struct ath5k_softc *sc = hw->priv;
668
3a078876 669 ath5k_led_off(sc);
fa1c114f 670
3e4242b9 671 free_irq(pdev->irq, sc);
fa1c114f
JS		 672 pci_save_state(pdev);
673 pci_disable_device(pdev);
674 pci_set_power_state(pdev, PCI_D3hot);
675
676 return 0;
677}
678
679static int
680ath5k_pci_resume(struct pci_dev *pdev)
681{
682 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
683 struct ath5k_softc *sc = hw->priv;
bc1b32d6 684 int err;
fa1c114f 685
3e4242b9 686 pci_restore_state(pdev);
fa1c114f
JS		 687
688 err = pci_enable_device(pdev);
689 if (err)
690 return err;
691
fa1c114f
JS		 692 /*
693 * Suspend/Resume resets the PCI configuration space, so we have to
694 * re-disable the RETRY_TIMEOUT register (0x41) to keep
695 * PCI Tx retries from interfering with C3 CPU state
696 */
697 pci_write_config_byte(pdev, 0x41, 0);
698
3e4242b9
JS		 699 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
700 if (err) {
701 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 702 goto err_no_irq;
3e4242b9
JS		 703 }
704
3a078876 705 ath5k_led_enable(sc);
fa1c114f 706 return 0;
bb2becac 707
37465c8a 708err_no_irq:
3e4242b9
JS		 709 pci_disable_device(pdev);
710 return err;
fa1c114f
JS		 711}
712#endif /* CONFIG_PM */
713
714
fa1c114f
JS		 715/***********************\
716* Driver Initialization *
717\***********************/
718
719static int
720ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
721{
722 struct ath5k_softc *sc = hw->priv;
723 struct ath5k_hw *ah = sc->ah;
0e149cf5 724 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 725 int ret;
726
727 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
728
729 /*
730 * Check if the MAC has multi-rate retry support.
731 * We do this by trying to setup a fake extended
732 * descriptor. MAC's that don't have support will
733 * return false w/o doing anything. MAC's that do
734 * support it will return true w/o doing anything.
735 */
c6e387a2 736 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 737 if (ret < 0)
738 goto err;
739 if (ret > 0)
fa1c114f
JS		 740 __set_bit(ATH_STAT_MRRETRY, sc->status);
741
fa1c114f
JS		 742 /*
743 * Collect the channel list. The 802.11 layer
744 * is resposible for filtering this list based
745 * on settings like the phy mode and regulatory
746 * domain restrictions.
747 */
63266a65 748 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 749 if (ret) {
750 ATH5K_ERR(sc, "can't get channels\n");
751 goto err;
752 }
753
754 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 755 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
756 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 757 else
d8ee398d 758 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 759
760 /*
761 * Allocate tx+rx descriptors and populate the lists.
762 */
763 ret = ath5k_desc_alloc(sc, pdev);
764 if (ret) {
765 ATH5K_ERR(sc, "can't allocate descriptors\n");
766 goto err;
767 }
768
769 /*
770 * Allocate hardware transmit queues: one queue for
771 * beacon frames and one data queue for each QoS
772 * priority. Note that hw functions handle reseting
773 * these queues at the needed time.
774 */
775 ret = ath5k_beaconq_setup(ah);
776 if (ret < 0) {
777 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
778 goto err_desc;
779 }
780 sc->bhalq = ret;
781
782 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
783 if (IS_ERR(sc->txq)) {
784 ATH5K_ERR(sc, "can't setup xmit queue\n");
785 ret = PTR_ERR(sc->txq);
786 goto err_bhal;
787 }
788
789 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
790 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
791 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
792 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 793
0e149cf5
BC		 794 ret = ath5k_eeprom_read_mac(ah, mac);
795 if (ret) {
796 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
797 sc->pdev->device);
798 goto err_queues;
799 }
800
fa1c114f
JS		 801 SET_IEEE80211_PERM_ADDR(hw, mac);
802 /* All MAC address bits matter for ACKs */
803 memset(sc->bssidmask, 0xff, ETH_ALEN);
804 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
805
806 ret = ieee80211_register_hw(hw);
807 if (ret) {
808 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
809 goto err_queues;
810 }
811
3a078876
BC		 812 ath5k_init_leds(sc);
813
fa1c114f
JS		 814 return 0;
815err_queues:
816 ath5k_txq_release(sc);
817err_bhal:
818 ath5k_hw_release_tx_queue(ah, sc->bhalq);
819err_desc:
820 ath5k_desc_free(sc, pdev);
821err:
822 return ret;
823}
824
825static void
826ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
827{
828 struct ath5k_softc *sc = hw->priv;
829
830 /*
831 * NB: the order of these is important:
832 * o call the 802.11 layer before detaching ath5k_hw to
833 * insure callbacks into the driver to delete global
834 * key cache entries can be handled
835 * o reclaim the tx queue data structures after calling
836 * the 802.11 layer as we'll get called back to reclaim
837 * node state and potentially want to use them
838 * o to cleanup the tx queues the hal is called, so detach
839 * it last
840 * XXX: ??? detach ath5k_hw ???
841 * Other than that, it's straightforward...
842 */
843 ieee80211_unregister_hw(hw);
844 ath5k_desc_free(sc, pdev);
845 ath5k_txq_release(sc);
846 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 847 ath5k_unregister_leds(sc);
fa1c114f
JS		 848
849 /*
850 * NB: can't reclaim these until after ieee80211_ifdetach
851 * returns because we'll get called back to reclaim node
852 * state and potentially want to use them.
853 */
854}
855
856
857
858
859/********************\
860* Channel/mode setup *
861\********************/
862
863/*
864 * Convert IEEE channel number to MHz frequency.
865 */
866static inline short
867ath5k_ieee2mhz(short chan)
868{
869 if (chan <= 14 || chan >= 27)
870 return ieee80211chan2mhz(chan);
871 else
872 return 2212 + chan * 20;
873}
874
fa1c114f
JS		 875static unsigned int
876ath5k_copy_channels(struct ath5k_hw *ah,
877 struct ieee80211_channel *channels,
878 unsigned int mode,
879 unsigned int max)
880{
d8ee398d 881 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 882
883 if (!test_bit(mode, ah->ah_modes))
884 return 0;
885
fa1c114f 886 switch (mode) {
d8ee398d
LR		 887 case AR5K_MODE_11A:
888 case AR5K_MODE_11A_TURBO:
fa1c114f 889 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 890 size = 220 ;
fa1c114f
JS		 891 chfreq = CHANNEL_5GHZ;
892 break;
d8ee398d
LR		 893 case AR5K_MODE_11B:
894 case AR5K_MODE_11G:
895 case AR5K_MODE_11G_TURBO:
896 size = 26;
fa1c114f
JS		 897 chfreq = CHANNEL_2GHZ;
898 break;
899 default:
900 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
901 return 0;
902 }
903
904 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 905 ch = i + 1 ;
906 freq = ath5k_ieee2mhz(ch);
fa1c114f 907
d8ee398d
LR		 908 /* Check if channel is supported by the chipset */
909 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 910 continue;
911
d8ee398d
LR		 912 /* Write channel info and increment counter */
913 channels[count].center_freq = freq;
a3f4b914
LR		 914 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
915 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 916 switch (mode) {
917 case AR5K_MODE_11A:
918 case AR5K_MODE_11G:
919 channels[count].hw_value = chfreq | CHANNEL_OFDM;
920 break;
921 case AR5K_MODE_11A_TURBO:
922 case AR5K_MODE_11G_TURBO:
923 channels[count].hw_value = chfreq |
924 CHANNEL_OFDM | CHANNEL_TURBO;
925 break;
926 case AR5K_MODE_11B:
d8ee398d
LR		 927 channels[count].hw_value = CHANNEL_B;
928 }
fa1c114f 929
fa1c114f
JS		 930 count++;
931 max--;
932 }
933
934 return count;
935}
936
63266a65
BR		 937static void
938ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
939{
940 u8 i;
941
942 for (i = 0; i < AR5K_MAX_RATES; i++)
943 sc->rate_idx[b->band][i] = -1;
944
945 for (i = 0; i < b->n_bitrates; i++) {
946 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
947 if (b->bitrates[i].hw_value_short)
948 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
949 }
950}
951
d8ee398d 952static int
63266a65 953ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 954{
955 struct ath5k_softc *sc = hw->priv;
d8ee398d 956 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 957 struct ieee80211_supported_band *sband;
958 int max_c, count_c = 0;
959 int i;
fa1c114f 960
d8ee398d 961 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 962 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 963
964 /* 2GHz band */
63266a65
BR		 965 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
966 sband->band = IEEE80211_BAND_2GHZ;
967 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 968
63266a65
BR		 969 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
970 /* G mode */
971 memcpy(sband->bitrates, &ath5k_rates[0],
972 sizeof(struct ieee80211_rate) * 12);
973 sband->n_bitrates = 12;
fa1c114f 974
d8ee398d 975 sband->channels = sc->channels;
d8ee398d 976 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 977 AR5K_MODE_11G, max_c);
fa1c114f 978
63266a65 979 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 980 count_c = sband->n_channels;
63266a65
BR		 981 max_c -= count_c;
982 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
983 /* B mode */
984 memcpy(sband->bitrates, &ath5k_rates[0],
985 sizeof(struct ieee80211_rate) * 4);
986 sband->n_bitrates = 4;
987
988 /* 5211 only supports B rates and uses 4bit rate codes
989 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
990 * fix them up here:
991 */
992 if (ah->ah_version == AR5K_AR5211) {
993 for (i = 0; i < 4; i++) {
994 sband->bitrates[i].hw_value =
995 sband->bitrates[i].hw_value & 0xF;
996 sband->bitrates[i].hw_value_short =
997 sband->bitrates[i].hw_value_short & 0xF;
998 }
999 }
fa1c114f 1000
63266a65
BR		 1001 sband->channels = sc->channels;
1002 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1003 AR5K_MODE_11B, max_c);
d8ee398d 1004
63266a65
BR		 1005 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1006 count_c = sband->n_channels;
d8ee398d 1007 max_c -= count_c;
fa1c114f 1008 }
63266a65 1009 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1010
63266a65 1011 /* 5GHz band, A mode */
400ec45a 1012 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1013 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1014 sband->band = IEEE80211_BAND_5GHZ;
1015 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1016
63266a65
BR		 1017 memcpy(sband->bitrates, &ath5k_rates[4],
1018 sizeof(struct ieee80211_rate) * 8);
1019 sband->n_bitrates = 8;
fa1c114f 1020
63266a65 1021 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1022 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1023 AR5K_MODE_11A, max_c);
1024
d8ee398d
LR		 1025 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1026 }
63266a65 1027 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1028
b446197c 1029 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1030
1031 return 0;
fa1c114f
JS		 1032}
1033
1034/*
1035 * Set/change channels. If the channel is really being changed,
1036 * it's done by reseting the chip. To accomplish this we must
1037 * first cleanup any pending DMA, then restart stuff after a la
1038 * ath5k_init.
be009370
BC		 1039 *
1040 * Called with sc->lock.
fa1c114f
JS		 1041 */
1042static int
1043ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1044{
d8ee398d
LR		 1045 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1046 sc->curchan->center_freq, chan->center_freq);
1047
1048 if (chan->center_freq != sc->curchan->center_freq ||
1049 chan->hw_value != sc->curchan->hw_value) {
1050
1051 sc->curchan = chan;
1052 sc->curband = &sc->sbands[chan->band];
fa1c114f 1053
fa1c114f
JS		 1054 /*
1055 * To switch channels clear any pending DMA operations;
1056 * wait long enough for the RX fifo to drain, reset the
1057 * hardware at the new frequency, and then re-enable
1058 * the relevant bits of the h/w.
1059 */
d7dc1003 1060 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1061 }
1062
1063 return 0;
1064}
1065
1066static void
1067ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1068{
fa1c114f 1069 sc->curmode = mode;
d8ee398d 1070
400ec45a 1071 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1072 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1073 } else {
1074 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1075 }
fa1c114f
JS		 1076}
1077
1078static void
1079ath5k_mode_setup(struct ath5k_softc *sc)
1080{
1081 struct ath5k_hw *ah = sc->ah;
1082 u32 rfilt;
1083
1084 /* configure rx filter */
1085 rfilt = sc->filter_flags;
1086 ath5k_hw_set_rx_filter(ah, rfilt);
1087
1088 if (ath5k_hw_hasbssidmask(ah))
1089 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1090
1091 /* configure operational mode */
1092 ath5k_hw_set_opmode(ah);
1093
1094 ath5k_hw_set_mcast_filter(ah, 0, 0);
1095 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1096}
1097
d8ee398d 1098static inline int
63266a65
BR		 1099ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1100{
1101 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1102 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1103}
1104
fa1c114f
JS		 1105/***************\
1106* Buffers setup *
1107\***************/
1108
b6ea0356
BC		 1109static
1110struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1111{
1112 struct sk_buff *skb;
1113 unsigned int off;
1114
1115 /*
1116 * Allocate buffer with headroom_needed space for the
1117 * fake physical layer header at the start.
1118 */
1119 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1120
1121 if (!skb) {
1122 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1123 sc->rxbufsize + sc->cachelsz - 1);
1124 return NULL;
1125 }
1126 /*
1127 * Cache-line-align. This is important (for the
1128 * 5210 at least) as not doing so causes bogus data
1129 * in rx'd frames.
1130 */
1131 off = ((unsigned long)skb->data) % sc->cachelsz;
1132 if (off != 0)
1133 skb_reserve(skb, sc->cachelsz - off);
1134
1135 *skb_addr = pci_map_single(sc->pdev,
1136 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1137 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1138 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1139 dev_kfree_skb(skb);
1140 return NULL;
1141 }
1142 return skb;
1143}
1144
fa1c114f
JS		 1145static int
1146ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1147{
1148 struct ath5k_hw *ah = sc->ah;
1149 struct sk_buff *skb = bf->skb;
1150 struct ath5k_desc *ds;
1151
b6ea0356
BC		 1152 if (!skb) {
1153 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1154 if (!skb)
fa1c114f 1155 return -ENOMEM;
fa1c114f 1156 bf->skb = skb;
fa1c114f
JS		 1157 }
1158
1159 /*
1160 * Setup descriptors. For receive we always terminate
1161 * the descriptor list with a self-linked entry so we'll
1162 * not get overrun under high load (as can happen with a
1163 * 5212 when ANI processing enables PHY error frames).
1164 *
1165 * To insure the last descriptor is self-linked we create
1166 * each descriptor as self-linked and add it to the end. As
1167 * each additional descriptor is added the previous self-linked
1168 * entry is ``fixed'' naturally. This should be safe even
1169 * if DMA is happening. When processing RX interrupts we
1170 * never remove/process the last, self-linked, entry on the
1171 * descriptor list. This insures the hardware always has
1172 * someplace to write a new frame.
1173 */
1174 ds = bf->desc;
1175 ds->ds_link = bf->daddr; /* link to self */
1176 ds->ds_data = bf->skbaddr;
c6e387a2 1177 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1178 skb_tailroom(skb), /* buffer size */
1179 0);
1180
1181 if (sc->rxlink != NULL)
1182 *sc->rxlink = bf->daddr;
1183 sc->rxlink = &ds->ds_link;
1184 return 0;
1185}
1186
1187static int
e039fa4a 1188ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1189{
1190 struct ath5k_hw *ah = sc->ah;
1191 struct ath5k_txq *txq = sc->txq;
1192 struct ath5k_desc *ds = bf->desc;
1193 struct sk_buff *skb = bf->skb;
a888d52d 1194 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1195 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1196 struct ieee80211_rate *rate;
1197 unsigned int mrr_rate[3], mrr_tries[3];
1198 int i, ret;
8902ff4e 1199 u16 hw_rate;
07c1e852
BC		 1200 u16 cts_rate = 0;
1201 u16 duration = 0;
8902ff4e 1202 u8 rc_flags;
fa1c114f
JS		 1203
1204 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1205
fa1c114f
JS		 1206 /* XXX endianness */
1207 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1208 PCI_DMA_TODEVICE);
1209
8902ff4e
BC		 1210 rate = ieee80211_get_tx_rate(sc->hw, info);
1211
e039fa4a 1212 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1213 flags |= AR5K_TXDESC_NOACK;
1214
8902ff4e
BC		 1215 rc_flags = info->control.rates[0].flags;
1216 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1217 rate->hw_value_short : rate->hw_value;
1218
281c56dd 1219 pktlen = skb->len;
fa1c114f 1220
07c1e852
BC		 1221 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1222 flags |= AR5K_TXDESC_RTSENA;
1223 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1224 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1225 sc->vif, pktlen, info));
1226 }
1227 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1228 flags |= AR5K_TXDESC_CTSENA;
1229 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1230 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1231 sc->vif, pktlen, info));
1232 }
1233
d0f09804 1234 if (info->control.hw_key) {
e039fa4a 1235 keyidx = info->control.hw_key->hw_key_idx;
76708dee 1236 pktlen += info->control.hw_key->icv_len;
fa1c114f 1237 }
fa1c114f
JS		 1238 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1239 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1240 (sc->power_level * 2),
8902ff4e 1241 hw_rate,
07c1e852
BC		 1242 info->control.rates[0].count, keyidx, 0, flags,
1243 cts_rate, duration);
fa1c114f
JS		 1244 if (ret)
1245 goto err_unmap;
1246
2f7fe870
FF		 1247 memset(mrr_rate, 0, sizeof(mrr_rate));
1248 memset(mrr_tries, 0, sizeof(mrr_tries));
1249 for (i = 0; i < 3; i++) {
1250 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1251 if (!rate)
1252 break;
1253
1254 mrr_rate[i] = rate->hw_value;
e6a9854b 1255 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1256 }
1257
1258 ah->ah_setup_mrr_tx_desc(ah, ds,
1259 mrr_rate[0], mrr_tries[0],
1260 mrr_rate[1], mrr_tries[1],
1261 mrr_rate[2], mrr_tries[2]);
1262
fa1c114f
JS		 1263 ds->ds_link = 0;
1264 ds->ds_data = bf->skbaddr;
1265
1266 spin_lock_bh(&txq->lock);
1267 list_add_tail(&bf->list, &txq->q);
57ffc589 1268 sc->tx_stats[txq->qnum].len++;
fa1c114f 1269 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1270 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1271 else /* no, so only link it */
1272 *txq->link = bf->daddr;
1273
1274 txq->link = &ds->ds_link;
c6e387a2 1275 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1276 mmiowb();
fa1c114f
JS		 1277 spin_unlock_bh(&txq->lock);
1278
1279 return 0;
1280err_unmap:
1281 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1282 return ret;
1283}
1284
1285/*******************\
1286* Descriptors setup *
1287\*******************/
1288
1289static int
1290ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1291{
1292 struct ath5k_desc *ds;
1293 struct ath5k_buf *bf;
1294 dma_addr_t da;
1295 unsigned int i;
1296 int ret;
1297
1298 /* allocate descriptors */
1299 sc->desc_len = sizeof(struct ath5k_desc) *
1300 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1301 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1302 if (sc->desc == NULL) {
1303 ATH5K_ERR(sc, "can't allocate descriptors\n");
1304 ret = -ENOMEM;
1305 goto err;
1306 }
1307 ds = sc->desc;
1308 da = sc->desc_daddr;
1309 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1310 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1311
1312 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1313 sizeof(struct ath5k_buf), GFP_KERNEL);
1314 if (bf == NULL) {
1315 ATH5K_ERR(sc, "can't allocate bufptr\n");
1316 ret = -ENOMEM;
1317 goto err_free;
1318 }
1319 sc->bufptr = bf;
1320
1321 INIT_LIST_HEAD(&sc->rxbuf);
1322 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1323 bf->desc = ds;
1324 bf->daddr = da;
1325 list_add_tail(&bf->list, &sc->rxbuf);
1326 }
1327
1328 INIT_LIST_HEAD(&sc->txbuf);
1329 sc->txbuf_len = ATH_TXBUF;
1330 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1331 da += sizeof(*ds)) {
1332 bf->desc = ds;
1333 bf->daddr = da;
1334 list_add_tail(&bf->list, &sc->txbuf);
1335 }
1336
1337 /* beacon buffer */
1338 bf->desc = ds;
1339 bf->daddr = da;
1340 sc->bbuf = bf;
1341
1342 return 0;
1343err_free:
1344 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1345err:
1346 sc->desc = NULL;
1347 return ret;
1348}
1349
1350static void
1351ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1352{
1353 struct ath5k_buf *bf;
1354
1355 ath5k_txbuf_free(sc, sc->bbuf);
1356 list_for_each_entry(bf, &sc->txbuf, list)
1357 ath5k_txbuf_free(sc, bf);
1358 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1359 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1360
1361 /* Free memory associated with all descriptors */
1362 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1363
1364 kfree(sc->bufptr);
1365 sc->bufptr = NULL;
1366}
1367
1368
1369
1370
1371
1372/**************\
1373* Queues setup *
1374\**************/
1375
1376static struct ath5k_txq *
1377ath5k_txq_setup(struct ath5k_softc *sc,
1378 int qtype, int subtype)
1379{
1380 struct ath5k_hw *ah = sc->ah;
1381 struct ath5k_txq *txq;
1382 struct ath5k_txq_info qi = {
1383 .tqi_subtype = subtype,
1384 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1385 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1386 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1387 };
1388 int qnum;
1389
1390 /*
1391 * Enable interrupts only for EOL and DESC conditions.
1392 * We mark tx descriptors to receive a DESC interrupt
1393 * when a tx queue gets deep; otherwise waiting for the
1394 * EOL to reap descriptors. Note that this is done to
1395 * reduce interrupt load and this only defers reaping
1396 * descriptors, never transmitting frames. Aside from
1397 * reducing interrupts this also permits more concurrency.
1398 * The only potential downside is if the tx queue backs
1399 * up in which case the top half of the kernel may backup
1400 * due to a lack of tx descriptors.
1401 */
1402 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1403 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1404 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1405 if (qnum < 0) {
1406 /*
1407 * NB: don't print a message, this happens
1408 * normally on parts with too few tx queues
1409 */
1410 return ERR_PTR(qnum);
1411 }
1412 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1413 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1414 qnum, ARRAY_SIZE(sc->txqs));
1415 ath5k_hw_release_tx_queue(ah, qnum);
1416 return ERR_PTR(-EINVAL);
1417 }
1418 txq = &sc->txqs[qnum];
1419 if (!txq->setup) {
1420 txq->qnum = qnum;
1421 txq->link = NULL;
1422 INIT_LIST_HEAD(&txq->q);
1423 spin_lock_init(&txq->lock);
1424 txq->setup = true;
1425 }
1426 return &sc->txqs[qnum];
1427}
1428
1429static int
1430ath5k_beaconq_setup(struct ath5k_hw *ah)
1431{
1432 struct ath5k_txq_info qi = {
1433 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1434 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1435 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1436 /* NB: for dynamic turbo, don't enable any other interrupts */
1437 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1438 };
1439
1440 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1441}
1442
1443static int
1444ath5k_beaconq_config(struct ath5k_softc *sc)
1445{
1446 struct ath5k_hw *ah = sc->ah;
1447 struct ath5k_txq_info qi;
1448 int ret;
1449
1450 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1451 if (ret)
1452 return ret;
05c914fe
JB		 1453 if (sc->opmode == NL80211_IFTYPE_AP ||
1454 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1455 /*
1456 * Always burst out beacon and CAB traffic
1457 * (aifs = cwmin = cwmax = 0)
1458 */
1459 qi.tqi_aifs = 0;
1460 qi.tqi_cw_min = 0;
1461 qi.tqi_cw_max = 0;
05c914fe 1462 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1463 /*
1464 * Adhoc mode; backoff between 0 and (2 * cw_min).
1465 */
1466 qi.tqi_aifs = 0;
1467 qi.tqi_cw_min = 0;
1468 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1469 }
1470
6d91e1d8
BR		 1471 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1472 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1473 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1474
c6e387a2 1475 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1476 if (ret) {
1477 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1478 "hardware queue!\n", __func__);
1479 return ret;
1480 }
1481
1482 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1483}
1484
1485static void
1486ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1487{
1488 struct ath5k_buf *bf, *bf0;
1489
1490 /*
1491 * NB: this assumes output has been stopped and
1492 * we do not need to block ath5k_tx_tasklet
1493 */
1494 spin_lock_bh(&txq->lock);
1495 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1496 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1497
1498 ath5k_txbuf_free(sc, bf);
1499
1500 spin_lock_bh(&sc->txbuflock);
57ffc589 1501 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1502 list_move_tail(&bf->list, &sc->txbuf);
1503 sc->txbuf_len++;
1504 spin_unlock_bh(&sc->txbuflock);
1505 }
1506 txq->link = NULL;
1507 spin_unlock_bh(&txq->lock);
1508}
1509
1510/*
1511 * Drain the transmit queues and reclaim resources.
1512 */
1513static void
1514ath5k_txq_cleanup(struct ath5k_softc *sc)
1515{
1516 struct ath5k_hw *ah = sc->ah;
1517 unsigned int i;
1518
1519 /* XXX return value */
1520 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1521 /* don't touch the hardware if marked invalid */
1522 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1523 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1524 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1525 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1526 if (sc->txqs[i].setup) {
1527 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1528 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1529 "link %p\n",
1530 sc->txqs[i].qnum,
c6e387a2 1531 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1532 sc->txqs[i].qnum),
1533 sc->txqs[i].link);
1534 }
1535 }
36d6825b 1536 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1537
1538 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1539 if (sc->txqs[i].setup)
1540 ath5k_txq_drainq(sc, &sc->txqs[i]);
1541}
1542
1543static void
1544ath5k_txq_release(struct ath5k_softc *sc)
1545{
1546 struct ath5k_txq *txq = sc->txqs;
1547 unsigned int i;
1548
1549 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1550 if (txq->setup) {
1551 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1552 txq->setup = false;
1553 }
1554}
1555
1556
1557
1558
1559/*************\
1560* RX Handling *
1561\*************/
1562
1563/*
1564 * Enable the receive h/w following a reset.
1565 */
1566static int
1567ath5k_rx_start(struct ath5k_softc *sc)
1568{
1569 struct ath5k_hw *ah = sc->ah;
1570 struct ath5k_buf *bf;
1571 int ret;
1572
1573 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1574
1575 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1576 sc->cachelsz, sc->rxbufsize);
1577
1578 sc->rxlink = NULL;
1579
1580 spin_lock_bh(&sc->rxbuflock);
1581 list_for_each_entry(bf, &sc->rxbuf, list) {
1582 ret = ath5k_rxbuf_setup(sc, bf);
1583 if (ret != 0) {
1584 spin_unlock_bh(&sc->rxbuflock);
1585 goto err;
1586 }
1587 }
1588 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1589 spin_unlock_bh(&sc->rxbuflock);
1590
c6e387a2
NK		 1591 ath5k_hw_set_rxdp(ah, bf->daddr);
1592 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1593 ath5k_mode_setup(sc); /* set filters, etc. */
1594 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1595
1596 return 0;
1597err:
1598 return ret;
1599}
1600
1601/*
1602 * Disable the receive h/w in preparation for a reset.
1603 */
1604static void
1605ath5k_rx_stop(struct ath5k_softc *sc)
1606{
1607 struct ath5k_hw *ah = sc->ah;
1608
c6e387a2 1609 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1610 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1611 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1612
1613 ath5k_debug_printrxbuffs(sc, ah);
1614
1615 sc->rxlink = NULL; /* just in case */
1616}
1617
1618static unsigned int
1619ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1620 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1621{
1622 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1623 unsigned int keyix, hlen;
fa1c114f 1624
b47f407b
BR		 1625 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1626 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1627 return RX_FLAG_DECRYPTED;
1628
1629 /* Apparently when a default key is used to decrypt the packet
1630 the hw does not set the index used to decrypt. In such cases
1631 get the index from the packet. */
798ee985 1632 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1633 if (ieee80211_has_protected(hdr->frame_control) &&
1634 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1635 skb->len >= hlen + 4) {
fa1c114f
JS		 1636 keyix = skb->data[hlen + 3] >> 6;
1637
1638 if (test_bit(keyix, sc->keymap))
1639 return RX_FLAG_DECRYPTED;
1640 }
1641
1642 return 0;
1643}
1644
036cd1ec
BR		 1645
1646static void
6ba81c2c
BR		 1647ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1648 struct ieee80211_rx_status *rxs)
036cd1ec 1649{
6ba81c2c 1650 u64 tsf, bc_tstamp;
036cd1ec
BR		 1651 u32 hw_tu;
1652 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1653
24b56e70 1654 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1655 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1656 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1657 /*
6ba81c2c
BR		 1658 * Received an IBSS beacon with the same BSSID. Hardware *must*
1659 * have updated the local TSF. We have to work around various
1660 * hardware bugs, though...
036cd1ec 1661 */
6ba81c2c
BR		 1662 tsf = ath5k_hw_get_tsf64(sc->ah);
1663 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1664 hw_tu = TSF_TO_TU(tsf);
1665
1666 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1667 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1668 (unsigned long long)bc_tstamp,
1669 (unsigned long long)rxs->mactime,
1670 (unsigned long long)(rxs->mactime - bc_tstamp),
1671 (unsigned long long)tsf);
6ba81c2c
BR		 1672
1673 /*
1674 * Sometimes the HW will give us a wrong tstamp in the rx
1675 * status, causing the timestamp extension to go wrong.
1676 * (This seems to happen especially with beacon frames bigger
1677 * than 78 byte (incl. FCS))
1678 * But we know that the receive timestamp must be later than the
1679 * timestamp of the beacon since HW must have synced to that.
1680 *
1681 * NOTE: here we assume mactime to be after the frame was
1682 * received, not like mac80211 which defines it at the start.
1683 */
1684 if (bc_tstamp > rxs->mactime) {
036cd1ec 1685 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1686 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1687 (unsigned long long)rxs->mactime,
1688 (unsigned long long)tsf);
6ba81c2c 1689 rxs->mactime = tsf;
036cd1ec 1690 }
6ba81c2c
BR		 1691
1692 /*
1693 * Local TSF might have moved higher than our beacon timers,
1694 * in that case we have to update them to continue sending
1695 * beacons. This also takes care of synchronizing beacon sending
1696 * times with other stations.
1697 */
1698 if (hw_tu >= sc->nexttbtt)
1699 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1700 }
1701}
1702
1703
fa1c114f
JS		 1704static void
1705ath5k_tasklet_rx(unsigned long data)
1706{
1707 struct ieee80211_rx_status rxs = {};
b47f407b 1708 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1709 struct sk_buff *skb, *next_skb;
1710 dma_addr_t next_skb_addr;
fa1c114f 1711 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1712 struct ath5k_buf *bf, *bf_last;
fa1c114f 1713 struct ath5k_desc *ds;
fa1c114f
JS		 1714 int ret;
1715 int hdrlen;
0fe45b1d 1716 int padsize;
fa1c114f
JS		 1717
1718 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1719 if (list_empty(&sc->rxbuf)) {
1720 ATH5K_WARN(sc, "empty rx buf pool\n");
1721 goto unlock;
1722 }
1723 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1724 do {
d6894b5b
BC		 1725 rxs.flag = 0;
1726
fa1c114f
JS		 1727 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1728 BUG_ON(bf->skb == NULL);
1729 skb = bf->skb;
1730 ds = bf->desc;
1731
3a0f2c87
JS		 1732 /*
1733 * last buffer must not be freed to ensure proper hardware
1734 * function. When the hardware finishes also a packet next to
1735 * it, we are sure, it doesn't use it anymore and we can go on.
1736 */
1737 if (bf_last == bf)
1738 bf->flags |= 1;
1739 if (bf->flags) {
1740 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1741 struct ath5k_buf, list);
1742 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1743 &rs);
1744 if (ret)
1745 break;
1746 bf->flags &= ~1;
1747 /* skip the overwritten one (even status is martian) */
1748 goto next;
1749 }
fa1c114f 1750
b47f407b 1751 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1752 if (unlikely(ret == -EINPROGRESS))
1753 break;
1754 else if (unlikely(ret)) {
1755 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1756 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1757 return;
1758 }
1759
b47f407b 1760 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1761 ATH5K_WARN(sc, "unsupported jumbo\n");
1762 goto next;
1763 }
1764
b47f407b
BR		 1765 if (unlikely(rs.rs_status)) {
1766 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1767 goto next;
b47f407b 1768 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1769 /*
1770 * Decrypt error. If the error occurred
1771 * because there was no hardware key, then
1772 * let the frame through so the upper layers
1773 * can process it. This is necessary for 5210
1774 * parts which have no way to setup a ``clear''
1775 * key cache entry.
1776 *
1777 * XXX do key cache faulting
1778 */
b47f407b
BR		 1779 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1780 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1781 goto accept;
1782 }
b47f407b 1783 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1784 rxs.flag |= RX_FLAG_MMIC_ERROR;
1785 goto accept;
1786 }
1787
1788 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1789 if ((rs.rs_status &
1790 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1791 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1792 goto next;
1793 }
1794accept:
b6ea0356
BC		 1795 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1796
1797 /*
1798 * If we can't replace bf->skb with a new skb under memory
1799 * pressure, just skip this packet
1800 */
1801 if (!next_skb)
1802 goto next;
1803
fa1c114f
JS		 1804 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1805 PCI_DMA_FROMDEVICE);
b47f407b 1806 skb_put(skb, rs.rs_datalen);
fa1c114f 1807
0fe45b1d
BP		 1808 /* The MAC header is padded to have 32-bit boundary if the
1809 * packet payload is non-zero. The general calculation for
1810 * padsize would take into account odd header lengths:
1811 * padsize = (4 - hdrlen % 4) % 4; However, since only
1812 * even-length headers are used, padding can only be 0 or 2
1813 * bytes and we can optimize this a bit. In addition, we must
1814 * not try to remove padding from short control frames that do
1815 * not have payload. */
fa1c114f 1816 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1817 padsize = ath5k_pad_size(hdrlen);
1818 if (padsize) {
0fe45b1d
BP		 1819 memmove(skb->data + padsize, skb->data, hdrlen);
1820 skb_pull(skb, padsize);
fa1c114f
JS		 1821 }
1822
c0e1899b
BR		 1823 /*
1824 * always extend the mac timestamp, since this information is
1825 * also needed for proper IBSS merging.
1826 *
1827 * XXX: it might be too late to do it here, since rs_tstamp is
1828 * 15bit only. that means TSF extension has to be done within
1829 * 32768usec (about 32ms). it might be necessary to move this to
1830 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1831 *
1832 * Unfortunately we don't know when the hardware takes the rx
1833 * timestamp (beginning of phy frame, data frame, end of rx?).
1834 * The only thing we know is that it is hardware specific...
1835 * On AR5213 it seems the rx timestamp is at the end of the
1836 * frame, but i'm not sure.
1837 *
1838 * NOTE: mac80211 defines mactime at the beginning of the first
1839 * data symbol. Since we don't have any time references it's
1840 * impossible to comply to that. This affects IBSS merge only
1841 * right now, so it's not too bad...
c0e1899b 1842 */
b47f407b 1843 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1844 rxs.flag |= RX_FLAG_TSFT;
1845
d8ee398d
LR		 1846 rxs.freq = sc->curchan->center_freq;
1847 rxs.band = sc->curband->band;
fa1c114f 1848
fa1c114f 1849 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1850 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1851
1852 /* An rssi of 35 indicates you should be able use
1853 * 54 Mbps reliably. A more elaborate scheme can be used
1854 * here but it requires a map of SNR/throughput for each
1855 * possible mode used */
1856 rxs.qual = rs.rs_rssi * 100 / 35;
1857
1858 /* rssi can be more than 35 though, anything above that
1859 * should be considered at 100% */
1860 if (rxs.qual > 100)
1861 rxs.qual = 100;
fa1c114f 1862
b47f407b
BR		 1863 rxs.antenna = rs.rs_antenna;
1864 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1865 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1866
06303352
BR		 1867 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1868 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1869 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1870
fa1c114f
JS		 1871 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1872
036cd1ec 1873 /* check beacons in IBSS mode */
05c914fe 1874 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1875 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1876
fa1c114f 1877 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1878
1879 bf->skb = next_skb;
1880 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1881next:
1882 list_move_tail(&bf->list, &sc->rxbuf);
1883 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1884unlock:
fa1c114f
JS		 1885 spin_unlock(&sc->rxbuflock);
1886}
1887
1888
1889
1890
1891/*************\
1892* TX Handling *
1893\*************/
1894
1895static void
1896ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1897{
b47f407b 1898 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1899 struct ath5k_buf *bf, *bf0;
1900 struct ath5k_desc *ds;
1901 struct sk_buff *skb;
e039fa4a 1902 struct ieee80211_tx_info *info;
2f7fe870 1903 int i, ret;
fa1c114f
JS		 1904
1905 spin_lock(&txq->lock);
1906 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1907 ds = bf->desc;
1908
b47f407b 1909 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1910 if (unlikely(ret == -EINPROGRESS))
1911 break;
1912 else if (unlikely(ret)) {
1913 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1914 ret, txq->qnum);
1915 break;
1916 }
1917
1918 skb = bf->skb;
a888d52d 1919 info = IEEE80211_SKB_CB(skb);
fa1c114f 1920 bf->skb = NULL;
e039fa4a 1921
fa1c114f
JS		 1922 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1923 PCI_DMA_TODEVICE);
1924
e6a9854b 1925 ieee80211_tx_info_clear_status(info);
2f7fe870 1926 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1927 struct ieee80211_tx_rate *r =
1928 &info->status.rates[i];
2f7fe870
FF		 1929
1930 if (ts.ts_rate[i]) {
e6a9854b
JB		 1931 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1932 r->count = ts.ts_retry[i];
2f7fe870 1933 } else {
e6a9854b
JB		 1934 r->idx = -1;
1935 r->count = 0;
2f7fe870
FF		 1936 }
1937 }
1938
e6a9854b
JB		 1939 /* count the successful attempt as well */
1940 info->status.rates[ts.ts_final_idx].count++;
1941
b47f407b 1942 if (unlikely(ts.ts_status)) {
fa1c114f 1943 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1944 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1945 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1946 } else {
e039fa4a
JB		 1947 info->flags |= IEEE80211_TX_STAT_ACK;
1948 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1949 }
1950
e039fa4a 1951 ieee80211_tx_status(sc->hw, skb);
57ffc589 1952 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1953
1954 spin_lock(&sc->txbuflock);
57ffc589 1955 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1956 list_move_tail(&bf->list, &sc->txbuf);
1957 sc->txbuf_len++;
1958 spin_unlock(&sc->txbuflock);
1959 }
1960 if (likely(list_empty(&txq->q)))
1961 txq->link = NULL;
1962 spin_unlock(&txq->lock);
1963 if (sc->txbuf_len > ATH_TXBUF / 5)
1964 ieee80211_wake_queues(sc->hw);
1965}
1966
1967static void
1968ath5k_tasklet_tx(unsigned long data)
1969{
1970 struct ath5k_softc *sc = (void *)data;
1971
1972 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1973}
1974
1975
fa1c114f
JS		 1976/*****************\
1977* Beacon handling *
1978\*****************/
1979
1980/*
1981 * Setup the beacon frame for transmit.
1982 */
1983static int
e039fa4a 1984ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1985{
1986 struct sk_buff *skb = bf->skb;
a888d52d 1987 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1988 struct ath5k_hw *ah = sc->ah;
1989 struct ath5k_desc *ds;
1990 int ret, antenna = 0;
1991 u32 flags;
1992
1993 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1994 PCI_DMA_TODEVICE);
1995 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1996 "skbaddr %llx\n", skb, skb->data, skb->len,
1997 (unsigned long long)bf->skbaddr);
8d8bb39b 1998 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1999 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2000 return -EIO;
2001 }
2002
2003 ds = bf->desc;
2004
2005 flags = AR5K_TXDESC_NOACK;
05c914fe 2006 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2007 ds->ds_link = bf->daddr; /* self-linked */
2008 flags |= AR5K_TXDESC_VEOL;
2009 /*
2010 * Let hardware handle antenna switching if txantenna is not set
2011 */
2012 } else {
2013 ds->ds_link = 0;
2014 /*
2015 * Switch antenna every 4 beacons if txantenna is not set
2016 * XXX assumes two antennas
2017 */
2018 if (antenna == 0)
2019 antenna = sc->bsent & 4 ? 2 : 1;
2020 }
2021
2022 ds->ds_data = bf->skbaddr;
281c56dd 2023 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2024 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2025 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2026 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2027 1, AR5K_TXKEYIX_INVALID,
400ec45a 2028 antenna, flags, 0, 0);
fa1c114f
JS		 2029 if (ret)
2030 goto err_unmap;
2031
2032 return 0;
2033err_unmap:
2034 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2035 return ret;
2036}
2037
2038/*
2039 * Transmit a beacon frame at SWBA. Dynamic updates to the
2040 * frame contents are done as needed and the slot time is
2041 * also adjusted based on current state.
2042 *
2043 * this is usually called from interrupt context (ath5k_intr())
2044 * but also from ath5k_beacon_config() in IBSS mode which in turn
2045 * can be called from a tasklet and user context
2046 */
2047static void
2048ath5k_beacon_send(struct ath5k_softc *sc)
2049{
2050 struct ath5k_buf *bf = sc->bbuf;
2051 struct ath5k_hw *ah = sc->ah;
2052
be9b7259 2053 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2054
05c914fe
JB		 2055 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2056 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2057 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2058 return;
2059 }
2060 /*
2061 * Check if the previous beacon has gone out. If
2062 * not don't don't try to post another, skip this
2063 * period and wait for the next. Missed beacons
2064 * indicate a problem and should not occur. If we
2065 * miss too many consecutive beacons reset the device.
2066 */
2067 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2068 sc->bmisscount++;
be9b7259 2069 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2070 "missed %u consecutive beacons\n", sc->bmisscount);
2071 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2072 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2073 "stuck beacon time (%u missed)\n",
2074 sc->bmisscount);
2075 tasklet_schedule(&sc->restq);
2076 }
2077 return;
2078 }
2079 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2080 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2081 "resume beacon xmit after %u misses\n",
2082 sc->bmisscount);
2083 sc->bmisscount = 0;
2084 }
2085
2086 /*
2087 * Stop any current dma and put the new frame on the queue.
2088 * This should never fail since we check above that no frames
2089 * are still pending on the queue.
2090 */
2091 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2092 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2093 /* NB: hw still stops DMA, so proceed */
2094 }
fa1c114f 2095
c6e387a2
NK		 2096 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2097 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2098 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2099 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2100
2101 sc->bsent++;
2102}
2103
2104
9804b98d
BR		 2105/**
2106 * ath5k_beacon_update_timers - update beacon timers
2107 *
2108 * @sc: struct ath5k_softc pointer we are operating on
2109 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2110 * beacon timer update based on the current HW TSF.
2111 *
2112 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2113 * of a received beacon or the current local hardware TSF and write it to the
2114 * beacon timer registers.
2115 *
2116 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2117 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2118 * when we otherwise know we have to update the timers, but we keep it in this
2119 * function to have it all together in one place.
2120 */
fa1c114f 2121static void
9804b98d 2122ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2123{
2124 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2125 u32 nexttbtt, intval, hw_tu, bc_tu;
2126 u64 hw_tsf;
fa1c114f
JS		 2127
2128 intval = sc->bintval & AR5K_BEACON_PERIOD;
2129 if (WARN_ON(!intval))
2130 return;
2131
9804b98d
BR		 2132 /* beacon TSF converted to TU */
2133 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2134
9804b98d
BR		 2135 /* current TSF converted to TU */
2136 hw_tsf = ath5k_hw_get_tsf64(ah);
2137 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2138
9804b98d
BR		 2139#define FUDGE 3
2140 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2141 if (bc_tsf == -1) {
2142 /*
2143 * no beacons received, called internally.
2144 * just need to refresh timers based on HW TSF.
2145 */
2146 nexttbtt = roundup(hw_tu + FUDGE, intval);
2147 } else if (bc_tsf == 0) {
2148 /*
2149 * no beacon received, probably called by ath5k_reset_tsf().
2150 * reset TSF to start with 0.
2151 */
2152 nexttbtt = intval;
2153 intval |= AR5K_BEACON_RESET_TSF;
2154 } else if (bc_tsf > hw_tsf) {
2155 /*
2156 * beacon received, SW merge happend but HW TSF not yet updated.
2157 * not possible to reconfigure timers yet, but next time we
2158 * receive a beacon with the same BSSID, the hardware will
2159 * automatically update the TSF and then we need to reconfigure
2160 * the timers.
2161 */
2162 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2163 "need to wait for HW TSF sync\n");
2164 return;
2165 } else {
2166 /*
2167 * most important case for beacon synchronization between STA.
2168 *
2169 * beacon received and HW TSF has been already updated by HW.
2170 * update next TBTT based on the TSF of the beacon, but make
2171 * sure it is ahead of our local TSF timer.
2172 */
2173 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2174 }
2175#undef FUDGE
fa1c114f 2176
036cd1ec
BR		 2177 sc->nexttbtt = nexttbtt;
2178
fa1c114f 2179 intval |= AR5K_BEACON_ENA;
fa1c114f 2180 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2181
2182 /*
2183 * debugging output last in order to preserve the time critical aspect
2184 * of this function
2185 */
2186 if (bc_tsf == -1)
2187 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2188 "reconfigured timers based on HW TSF\n");
2189 else if (bc_tsf == 0)
2190 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2191 "reset HW TSF and timers\n");
2192 else
2193 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2194 "updated timers based on beacon TSF\n");
2195
2196 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2197 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2198 (unsigned long long) bc_tsf,
2199 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2200 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2201 intval & AR5K_BEACON_PERIOD,
2202 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2203 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2204}
2205
2206
036cd1ec
BR		 2207/**
2208 * ath5k_beacon_config - Configure the beacon queues and interrupts
2209 *
2210 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2211 *
2212 * When operating in station mode we want to receive a BMISS interrupt when we
2213 * stop seeing beacons from the AP we've associated with so we can look for
2214 * another AP to associate with.
2215 *
036cd1ec 2216 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2217 * interrupts to detect TSF updates only.
fa1c114f
JS		 2218 */
2219static void
2220ath5k_beacon_config(struct ath5k_softc *sc)
2221{
2222 struct ath5k_hw *ah = sc->ah;
2223
c6e387a2 2224 ath5k_hw_set_imr(ah, 0);
fa1c114f 2225 sc->bmisscount = 0;
dc1968e7 2226 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2227
05c914fe 2228 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2229 sc->imask |= AR5K_INT_BMISS;
da966bca 2230 } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2231 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2232 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2233 /*
036cd1ec
BR		 2234 * In IBSS mode we use a self-linked tx descriptor and let the
2235 * hardware send the beacons automatically. We have to load it
fa1c114f 2236 * only once here.
036cd1ec 2237 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2238 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2239 */
2240 ath5k_beaconq_config(sc);
fa1c114f 2241
036cd1ec
BR		 2242 sc->imask |= AR5K_INT_SWBA;
2243
da966bca
JS		 2244 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2245 if (ath5k_hw_hasveol(ah)) {
2246 spin_lock(&sc->block);
2247 ath5k_beacon_send(sc);
2248 spin_unlock(&sc->block);
2249 }
2250 } else
2251 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2252 }
fa1c114f 2253
c6e387a2 2254 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2255}
2256
2257
2258/********************\
2259* Interrupt handling *
2260\********************/
2261
2262static int
bb2becac 2263ath5k_init(struct ath5k_softc *sc)
fa1c114f 2264{
bc1b32d6
EO		 2265 struct ath5k_hw *ah = sc->ah;
2266 int ret, i;
fa1c114f
JS		 2267
2268 mutex_lock(&sc->lock);
2269
2270 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2271
2272 /*
2273 * Stop anything previously setup. This is safe
2274 * no matter this is the first time through or not.
2275 */
2276 ath5k_stop_locked(sc);
2277
2278 /*
2279 * The basic interface to setting the hardware in a good
2280 * state is ``reset''. On return the hardware is known to
2281 * be powered up and with interrupts disabled. This must
2282 * be followed by initialization of the appropriate bits
2283 * and then setup of the interrupt mask.
2284 */
d8ee398d
LR		 2285 sc->curchan = sc->hw->conf.channel;
2286 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2287 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2288 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2289 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
d7dc1003
JS		 2290 ret = ath5k_reset(sc, false, false);
2291 if (ret)
2292 goto done;
fa1c114f 2293
bc1b32d6
EO		 2294 /*
2295 * Reset the key cache since some parts do not reset the
2296 * contents on initial power up or resume from suspend.
2297 */
2298 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2299 ath5k_hw_reset_key(ah, i);
2300
fa1c114f 2301 /* Set ack to be sent at low bit-rates */
bc1b32d6 2302 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2303
2304 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2305 msecs_to_jiffies(ath5k_calinterval * 1000)));
2306
2307 ret = 0;
2308done:
274c7c36 2309 mmiowb();
fa1c114f
JS		 2310 mutex_unlock(&sc->lock);
2311 return ret;
2312}
2313
2314static int
2315ath5k_stop_locked(struct ath5k_softc *sc)
2316{
2317 struct ath5k_hw *ah = sc->ah;
2318
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2320 test_bit(ATH_STAT_INVALID, sc->status));
2321
2322 /*
2323 * Shutdown the hardware and driver:
2324 * stop output from above
2325 * disable interrupts
2326 * turn off timers
2327 * turn off the radio
2328 * clear transmit machinery
2329 * clear receive machinery
2330 * drain and release tx queues
2331 * reclaim beacon resources
2332 * power down hardware
2333 *
2334 * Note that some of this work is not possible if the
2335 * hardware is gone (invalid).
2336 */
2337 ieee80211_stop_queues(sc->hw);
2338
2339 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2340 ath5k_led_off(sc);
c6e387a2 2341 ath5k_hw_set_imr(ah, 0);
274c7c36 2342 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2343 }
2344 ath5k_txq_cleanup(sc);
2345 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2346 ath5k_rx_stop(sc);
2347 ath5k_hw_phy_disable(ah);
2348 } else
2349 sc->rxlink = NULL;
2350
2351 return 0;
2352}
2353
2354/*
2355 * Stop the device, grabbing the top-level lock to protect
2356 * against concurrent entry through ath5k_init (which can happen
2357 * if another thread does a system call and the thread doing the
2358 * stop is preempted).
2359 */
2360static int
bb2becac 2361ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2362{
2363 int ret;
2364
2365 mutex_lock(&sc->lock);
2366 ret = ath5k_stop_locked(sc);
2367 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2368 /*
2369 * Set the chip in full sleep mode. Note that we are
2370 * careful to do this only when bringing the interface
2371 * completely to a stop. When the chip is in this state
2372 * it must be carefully woken up or references to
2373 * registers in the PCI clock domain may freeze the bus
2374 * (and system). This varies by chip and is mostly an
2375 * issue with newer parts that go to sleep more quickly.
2376 */
2377 if (sc->ah->ah_mac_srev >= 0x78) {
2378 /*
2379 * XXX
2380 * don't put newer MAC revisions > 7.8 to sleep because
2381 * of the above mentioned problems
2382 */
2383 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2384 "not putting device to sleep\n");
2385 } else {
2386 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2387 "putting device to full sleep\n");
2388 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2389 }
2390 }
2391 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2392
274c7c36 2393 mmiowb();
fa1c114f
JS		 2394 mutex_unlock(&sc->lock);
2395
2396 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2397 tasklet_kill(&sc->rxtq);
2398 tasklet_kill(&sc->txtq);
2399 tasklet_kill(&sc->restq);
fa1c114f
JS		 2400
2401 return ret;
2402}
2403
2404static irqreturn_t
2405ath5k_intr(int irq, void *dev_id)
2406{
2407 struct ath5k_softc *sc = dev_id;
2408 struct ath5k_hw *ah = sc->ah;
2409 enum ath5k_int status;
2410 unsigned int counter = 1000;
2411
2412 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2413 !ath5k_hw_is_intr_pending(ah)))
2414 return IRQ_NONE;
2415
2416 do {
2417 /*
2418 * Figure out the reason(s) for the interrupt. Note
2419 * that get_isr returns a pseudo-ISR that may include
2420 * bits we haven't explicitly enabled so we mask the
2421 * value to insure we only process bits we requested.
2422 */
2423 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2424 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2425 status, sc->imask);
2426 status &= sc->imask; /* discard unasked for bits */
2427 if (unlikely(status & AR5K_INT_FATAL)) {
2428 /*
2429 * Fatal errors are unrecoverable.
2430 * Typically these are caused by DMA errors.
2431 */
2432 tasklet_schedule(&sc->restq);
2433 } else if (unlikely(status & AR5K_INT_RXORN)) {
2434 tasklet_schedule(&sc->restq);
2435 } else {
2436 if (status & AR5K_INT_SWBA) {
2437 /*
2438 * Software beacon alert--time to send a beacon.
2439 * Handle beacon transmission directly; deferring
2440 * this is too slow to meet timing constraints
2441 * under load.
036cd1ec
BR		 2442 *
2443 * In IBSS mode we use this interrupt just to
2444 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2445 * transmission time) in order to detect wether
2446 * automatic TSF updates happened.
fa1c114f 2447 */
05c914fe 2448 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2449 /* XXX: only if VEOL suppported */
2450 u64 tsf = ath5k_hw_get_tsf64(ah);
2451 sc->nexttbtt += sc->bintval;
2452 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2453 "SWBA nexttbtt: %x hw_tu: %x "
2454 "TSF: %llx\n",
2455 sc->nexttbtt,
2456 TSF_TO_TU(tsf),
2457 (unsigned long long) tsf);
036cd1ec 2458 } else {
00482973 2459 spin_lock(&sc->block);
036cd1ec 2460 ath5k_beacon_send(sc);
00482973 2461 spin_unlock(&sc->block);
036cd1ec 2462 }
fa1c114f
JS		 2463 }
2464 if (status & AR5K_INT_RXEOL) {
2465 /*
2466 * NB: the hardware should re-read the link when
2467 * RXE bit is written, but it doesn't work at
2468 * least on older hardware revs.
2469 */
2470 sc->rxlink = NULL;
2471 }
2472 if (status & AR5K_INT_TXURN) {
2473 /* bump tx trigger level */
2474 ath5k_hw_update_tx_triglevel(ah, true);
2475 }
4c674c60 2476 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2477 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2478 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2479 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2480 tasklet_schedule(&sc->txtq);
2481 if (status & AR5K_INT_BMISS) {
2482 }
2483 if (status & AR5K_INT_MIB) {
194828a2
NK		 2484 /*
2485 * These stats are also used for ANI i think
2486 * so how about updating them more often ?
2487 */
2488 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2489 }
2490 }
2491 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2492
2493 if (unlikely(!counter))
2494 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2495
2496 return IRQ_HANDLED;
2497}
2498
2499static void
2500ath5k_tasklet_reset(unsigned long data)
2501{
2502 struct ath5k_softc *sc = (void *)data;
2503
d7dc1003 2504 ath5k_reset_wake(sc);
fa1c114f
JS		 2505}
2506
2507/*
2508 * Periodically recalibrate the PHY to account
2509 * for temperature/environment changes.
2510 */
2511static void
2512ath5k_calibrate(unsigned long data)
2513{
2514 struct ath5k_softc *sc = (void *)data;
2515 struct ath5k_hw *ah = sc->ah;
2516
2517 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2518 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2519 sc->curchan->hw_value);
fa1c114f 2520
6f3b414a 2521 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2522 /*
2523 * Rfgain is out of bounds, reset the chip
2524 * to load new gain values.
2525 */
2526 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2527 ath5k_reset_wake(sc);
fa1c114f
JS		 2528 }
2529 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2530 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2531 ieee80211_frequency_to_channel(
2532 sc->curchan->center_freq));
fa1c114f
JS		 2533
2534 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2535 msecs_to_jiffies(ath5k_calinterval * 1000)));
2536}
2537
2538
2539
2540/***************\
2541* LED functions *
2542\***************/
2543
2544static void
3a078876 2545ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2546{
3a078876
BC		 2547 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2548 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2549 ath5k_led_off(sc);
fa1c114f
JS		 2550 }
2551}
2552
fa1c114f 2553static void
3a078876 2554ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2555{
3a078876
BC		 2556 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2557 return;
fa1c114f 2558 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2559}
2560
2561static void
3a078876 2562ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2563{
3a078876 2564 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2565 return;
3a078876
BC		 2566 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2567}
2568
2569static void
2570ath5k_led_brightness_set(struct led_classdev *led_dev,
2571 enum led_brightness brightness)
2572{
2573 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2574 led_dev);
2575
2576 if (brightness == LED_OFF)
2577 ath5k_led_off(led->sc);
2578 else
2579 ath5k_led_on(led->sc);
2580}
2581
2582static int
2583ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2584 const char *name, char *trigger)
2585{
2586 int err;
2587
2588 led->sc = sc;
2589 strncpy(led->name, name, sizeof(led->name));
2590 led->led_dev.name = led->name;
2591 led->led_dev.default_trigger = trigger;
2592 led->led_dev.brightness_set = ath5k_led_brightness_set;
2593
2594 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
0bbac08f 2595 if (err) {
3a078876
BC		 2596 ATH5K_WARN(sc, "could not register LED %s\n", name);
2597 led->sc = NULL;
fa1c114f 2598 }
3a078876 2599 return err;
fa1c114f
JS		 2600}
2601
3a078876
BC		 2602static void
2603ath5k_unregister_led(struct ath5k_led *led)
2604{
2605 if (!led->sc)
2606 return;
2607 led_classdev_unregister(&led->led_dev);
2608 ath5k_led_off(led->sc);
2609 led->sc = NULL;
2610}
2611
2612static void
2613ath5k_unregister_leds(struct ath5k_softc *sc)
2614{
2615 ath5k_unregister_led(&sc->rx_led);
2616 ath5k_unregister_led(&sc->tx_led);
2617}
2618
2619
2620static int
2621ath5k_init_leds(struct ath5k_softc *sc)
2622{
2623 int ret = 0;
2624 struct ieee80211_hw *hw = sc->hw;
2625 struct pci_dev *pdev = sc->pdev;
2626 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2627
3a078876
BC		 2628 /*
2629 * Auto-enable soft led processing for IBM cards and for
2630 * 5211 minipci cards.
2631 */
2632 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2633 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2634 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2635 sc->led_pin = 0;
734b5aa9 2636 sc->led_on = 0; /* active low */
3a078876
BC		 2637 }
2638 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2639 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2640 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2641 sc->led_pin = 1;
734b5aa9 2642 sc->led_on = 1; /* active high */
3a078876 2643 }
f677d770
TMQMF		 2644 /*
2645 * Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) and
2646 * in emachines notebooks with AMBIT subsystem.
2647 */
2648 if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN ||
2649 pdev->subsystem_vendor == PCI_VENDOR_ID_AMBIT) {
63649b6c
BC		 2650 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2651 sc->led_pin = 3;
2652 sc->led_on = 0; /* active low */
2653 }
2654
3a078876
BC		 2655 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2656 goto out;
2657
2658 ath5k_led_enable(sc);
2659
2660 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2661 ret = ath5k_register_led(sc, &sc->rx_led, name,
2662 ieee80211_get_rx_led_name(hw));
2663 if (ret)
2664 goto out;
2665
2666 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2667 ret = ath5k_register_led(sc, &sc->tx_led, name,
2668 ieee80211_get_tx_led_name(hw));
2669out:
2670 return ret;
2671}
fa1c114f
JS		 2672
2673
2674/********************\
2675* Mac80211 functions *
2676\********************/
2677
2678static int
e039fa4a 2679ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2680{
2681 struct ath5k_softc *sc = hw->priv;
2682 struct ath5k_buf *bf;
2683 unsigned long flags;
2684 int hdrlen;
0fe45b1d 2685 int padsize;
fa1c114f
JS		 2686
2687 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2688
05c914fe 2689 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2690 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2691
2692 /*
2693 * the hardware expects the header padded to 4 byte boundaries
2694 * if this is not the case we add the padding after the header
2695 */
2696 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2697 padsize = ath5k_pad_size(hdrlen);
2698 if (padsize) {
0fe45b1d
BP		 2699
2700 if (skb_headroom(skb) < padsize) {
fa1c114f 2701 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2702 " headroom to pad %d\n", hdrlen, padsize);
71ef99c8 2703 return NETDEV_TX_BUSY;
fa1c114f 2704 }
0fe45b1d
BP		 2705 skb_push(skb, padsize);
2706 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2707 }
2708
fa1c114f
JS		 2709 spin_lock_irqsave(&sc->txbuflock, flags);
2710 if (list_empty(&sc->txbuf)) {
2711 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2712 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2713 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
71ef99c8 2714 return NETDEV_TX_BUSY;
fa1c114f
JS		 2715 }
2716 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2717 list_del(&bf->list);
2718 sc->txbuf_len--;
2719 if (list_empty(&sc->txbuf))
2720 ieee80211_stop_queues(hw);
2721 spin_unlock_irqrestore(&sc->txbuflock, flags);
2722
2723 bf->skb = skb;
2724
e039fa4a 2725 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2726 bf->skb = NULL;
2727 spin_lock_irqsave(&sc->txbuflock, flags);
2728 list_add_tail(&bf->list, &sc->txbuf);
2729 sc->txbuf_len++;
2730 spin_unlock_irqrestore(&sc->txbuflock, flags);
2731 dev_kfree_skb_any(skb);
71ef99c8 2732 return NETDEV_TX_OK;
fa1c114f
JS		 2733 }
2734
71ef99c8 2735 return NETDEV_TX_OK;
fa1c114f
JS		 2736}
2737
2738static int
d7dc1003 2739ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2740{
fa1c114f
JS		 2741 struct ath5k_hw *ah = sc->ah;
2742 int ret;
2743
2744 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2745
d7dc1003 2746 if (stop) {
c6e387a2 2747 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2748 ath5k_txq_cleanup(sc);
2749 ath5k_rx_stop(sc);
2750 }
fa1c114f 2751 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2752 if (ret) {
fa1c114f
JS		 2753 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2754 goto err;
2755 }
d7dc1003
JS		 2756
2757 /*
2758 * This is needed only to setup initial state
2759 * but it's best done after a reset.
2760 */
fa1c114f
JS		 2761 ath5k_hw_set_txpower_limit(sc->ah, 0);
2762
2763 ret = ath5k_rx_start(sc);
d7dc1003 2764 if (ret) {
fa1c114f
JS		 2765 ATH5K_ERR(sc, "can't start recv logic\n");
2766 goto err;
2767 }
d7dc1003 2768
fa1c114f 2769 /*
d7dc1003
JS		 2770 * Change channels and update the h/w rate map if we're switching;
2771 * e.g. 11a to 11b/g.
2772 *
2773 * We may be doing a reset in response to an ioctl that changes the
2774 * channel so update any state that might change as a result.
fa1c114f
JS		 2775 *
2776 * XXX needed?
2777 */
2778/* ath5k_chan_change(sc, c); */
fa1c114f 2779
d7dc1003
JS		 2780 ath5k_beacon_config(sc);
2781 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2782
2783 return 0;
2784err:
2785 return ret;
2786}
2787
d7dc1003
JS		 2788static int
2789ath5k_reset_wake(struct ath5k_softc *sc)
2790{
2791 int ret;
2792
2793 ret = ath5k_reset(sc, true, true);
2794 if (!ret)
2795 ieee80211_wake_queues(sc->hw);
2796
2797 return ret;
2798}
2799
fa1c114f
JS		 2800static int ath5k_start(struct ieee80211_hw *hw)
2801{
bb2becac 2802 return ath5k_init(hw->priv);
fa1c114f
JS		 2803}
2804
2805static void ath5k_stop(struct ieee80211_hw *hw)
2806{
bb2becac 2807 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2808}
2809
2810static int ath5k_add_interface(struct ieee80211_hw *hw,
2811 struct ieee80211_if_init_conf *conf)
2812{
2813 struct ath5k_softc *sc = hw->priv;
2814 int ret;
2815
2816 mutex_lock(&sc->lock);
32bfd35d 2817 if (sc->vif) {
fa1c114f
JS		 2818 ret = 0;
2819 goto end;
2820 }
2821
32bfd35d 2822 sc->vif = conf->vif;
fa1c114f
JS		 2823
2824 switch (conf->type) {
da966bca 2825 case NL80211_IFTYPE_AP:
05c914fe
JB		 2826 case NL80211_IFTYPE_STATION:
2827 case NL80211_IFTYPE_ADHOC:
b706e65b 2828 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2829 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2830 sc->opmode = conf->type;
2831 break;
2832 default:
2833 ret = -EOPNOTSUPP;
2834 goto end;
2835 }
67d2e2df
JS		 2836
2837 /* Set to a reasonable value. Note that this will
2838 * be set to mac80211's value at ath5k_config(). */
2839 sc->bintval = 1000;
0e149cf5 2840 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2841
fa1c114f
JS		 2842 ret = 0;
2843end:
2844 mutex_unlock(&sc->lock);
2845 return ret;
2846}
2847
2848static void
2849ath5k_remove_interface(struct ieee80211_hw *hw,
2850 struct ieee80211_if_init_conf *conf)
2851{
2852 struct ath5k_softc *sc = hw->priv;
0e149cf5 2853 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2854
2855 mutex_lock(&sc->lock);
32bfd35d 2856 if (sc->vif != conf->vif)
fa1c114f
JS		 2857 goto end;
2858
0e149cf5 2859 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2860 sc->vif = NULL;
fa1c114f
JS		 2861end:
2862 mutex_unlock(&sc->lock);
2863}
2864
d8ee398d
LR		 2865/*
2866 * TODO: Phy disable/diversity etc
2867 */
fa1c114f 2868static int
e8975581 2869ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2870{
2871 struct ath5k_softc *sc = hw->priv;
e8975581 2872 struct ieee80211_conf *conf = &hw->conf;
be009370
BC		 2873 int ret;
2874
2875 mutex_lock(&sc->lock);
fa1c114f 2876
e535c1ac 2877 sc->bintval = conf->beacon_int;
d8ee398d 2878 sc->power_level = conf->power_level;
fa1c114f 2879
be009370
BC		 2880 ret = ath5k_chan_set(sc, conf->channel);
2881
2882 mutex_unlock(&sc->lock);
2883 return ret;
fa1c114f
JS		 2884}
2885
2886static int
32bfd35d 2887ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2888 struct ieee80211_if_conf *conf)
2889{
2890 struct ath5k_softc *sc = hw->priv;
2891 struct ath5k_hw *ah = sc->ah;
2892 int ret;
2893
fa1c114f 2894 mutex_lock(&sc->lock);
32bfd35d 2895 if (sc->vif != vif) {
fa1c114f
JS		 2896 ret = -EIO;
2897 goto unlock;
2898 }
da966bca 2899 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2900 /* Cache for later use during resets */
2901 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2902 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2903 * a clean way of letting us retrieve this yet. */
2904 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2905 mmiowb();
fa1c114f 2906 }
9d139c81 2907 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2908 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2909 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2910 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2911 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2912 if (!beacon) {
2913 ret = -ENOMEM;
2914 goto unlock;
2915 }
da966bca 2916 ath5k_beacon_update(sc, beacon);
9d139c81 2917 }
fa1c114f
JS		 2918 mutex_unlock(&sc->lock);
2919
d7dc1003 2920 return ath5k_reset_wake(sc);
fa1c114f
JS		 2921unlock:
2922 mutex_unlock(&sc->lock);
2923 return ret;
2924}
2925
2926#define SUPPORTED_FIF_FLAGS \
2927 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2928 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2929 FIF_BCN_PRBRESP_PROMISC
2930/*
2931 * o always accept unicast, broadcast, and multicast traffic
2932 * o multicast traffic for all BSSIDs will be enabled if mac80211
2933 * says it should be
2934 * o maintain current state of phy ofdm or phy cck error reception.
2935 * If the hardware detects any of these type of errors then
2936 * ath5k_hw_get_rx_filter() will pass to us the respective
2937 * hardware filters to be able to receive these type of frames.
2938 * o probe request frames are accepted only when operating in
2939 * hostap, adhoc, or monitor modes
2940 * o enable promiscuous mode according to the interface state
2941 * o accept beacons:
2942 * - when operating in adhoc mode so the 802.11 layer creates
2943 * node table entries for peers,
2944 * - when operating in station mode for collecting rssi data when
2945 * the station is otherwise quiet, or
2946 * - when scanning
2947 */
2948static void ath5k_configure_filter(struct ieee80211_hw *hw,
2949 unsigned int changed_flags,
2950 unsigned int *new_flags,
2951 int mc_count, struct dev_mc_list *mclist)
2952{
2953 struct ath5k_softc *sc = hw->priv;
2954 struct ath5k_hw *ah = sc->ah;
2955 u32 mfilt[2], val, rfilt;
2956 u8 pos;
2957 int i;
2958
2959 mfilt[0] = 0;
2960 mfilt[1] = 0;
2961
2962 /* Only deal with supported flags */
2963 changed_flags &= SUPPORTED_FIF_FLAGS;
2964 *new_flags &= SUPPORTED_FIF_FLAGS;
2965
2966 /* If HW detects any phy or radar errors, leave those filters on.
2967 * Also, always enable Unicast, Broadcasts and Multicast
2968 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2969 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2970 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2971 AR5K_RX_FILTER_MCAST);
2972
2973 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2974 if (*new_flags & FIF_PROMISC_IN_BSS) {
2975 rfilt |= AR5K_RX_FILTER_PROM;
2976 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2977 } else {
fa1c114f 2978 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2979 }
fa1c114f
JS		 2980 }
2981
2982 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2983 if (*new_flags & FIF_ALLMULTI) {
2984 mfilt[0] = ~0;
2985 mfilt[1] = ~0;
2986 } else {
2987 for (i = 0; i < mc_count; i++) {
2988 if (!mclist)
2989 break;
2990 /* calculate XOR of eight 6-bit values */
533dd1b0 2991 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2992 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2993 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2994 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2995 pos &= 0x3f;
2996 mfilt[pos / 32] |= (1 << (pos % 32));
2997 /* XXX: we might be able to just do this instead,
2998 * but not sure, needs testing, if we do use this we'd
2999 * neet to inform below to not reset the mcast */
3000 /* ath5k_hw_set_mcast_filterindex(ah,
3001 * mclist->dmi_addr[5]); */
3002 mclist = mclist->next;
3003 }
3004 }
3005
3006 /* This is the best we can do */
3007 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3008 rfilt |= AR5K_RX_FILTER_PHYERR;
3009
3010 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3011 * and probes for any BSSID, this needs testing */
3012 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3013 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3014
3015 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3016 * set we should only pass on control frames for this
3017 * station. This needs testing. I believe right now this
3018 * enables *all* control frames, which is OK.. but
3019 * but we should see if we can improve on granularity */
3020 if (*new_flags & FIF_CONTROL)
3021 rfilt |= AR5K_RX_FILTER_CONTROL;
3022
3023 /* Additional settings per mode -- this is per ath5k */
3024
3025 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3026
05c914fe 3027 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 3028 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3029 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 3030 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 3031 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 3032 if (sc->opmode != NL80211_IFTYPE_AP &&
3033 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 3034 test_bit(ATH_STAT_PROMISC, sc->status))
3035 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 3036 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 3037 sc->opmode == NL80211_IFTYPE_ADHOC ||
3038 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 3039 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 3040 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
3041 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3042 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 3043
3044 /* Set filters */
0bbac08f 3045 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3046
3047 /* Set multicast bits */
3048 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3049 /* Set the cached hw filter flags, this will alter actually
3050 * be set in HW */
3051 sc->filter_flags = rfilt;
3052}
3053
3054static int
3055ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3056 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3057 struct ieee80211_key_conf *key)
fa1c114f
JS		 3058{
3059 struct ath5k_softc *sc = hw->priv;
3060 int ret = 0;
3061
9ad9a26e
BC		 3062 if (modparam_nohwcrypt)
3063 return -EOPNOTSUPP;
3064
0bbac08f 3065 switch (key->alg) {
fa1c114f 3066 case ALG_WEP:
fa1c114f 3067 case ALG_TKIP:
3f64b435 3068 break;
fa1c114f
JS		 3069 case ALG_CCMP:
3070 return -EOPNOTSUPP;
3071 default:
3072 WARN_ON(1);
3073 return -EINVAL;
3074 }
3075
3076 mutex_lock(&sc->lock);
3077
3078 switch (cmd) {
3079 case SET_KEY:
dc822b5d
JB		 3080 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3081 sta ? sta->addr : NULL);
fa1c114f
JS		 3082 if (ret) {
3083 ATH5K_ERR(sc, "can't set the key\n");
3084 goto unlock;
3085 }
3086 __set_bit(key->keyidx, sc->keymap);
3087 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3088 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3089 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3090 break;
3091 case DISABLE_KEY:
3092 ath5k_hw_reset_key(sc->ah, key->keyidx);
3093 __clear_bit(key->keyidx, sc->keymap);
3094 break;
3095 default:
3096 ret = -EINVAL;
3097 goto unlock;
3098 }
3099
3100unlock:
274c7c36 3101 mmiowb();
fa1c114f
JS		 3102 mutex_unlock(&sc->lock);
3103 return ret;
3104}
3105
3106static int
3107ath5k_get_stats(struct ieee80211_hw *hw,
3108 struct ieee80211_low_level_stats *stats)
3109{
3110 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3111 struct ath5k_hw *ah = sc->ah;
3112
3113 /* Force update */
3114 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3115
3116 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3117
3118 return 0;
3119}
3120
3121static int
3122ath5k_get_tx_stats(struct ieee80211_hw *hw,
3123 struct ieee80211_tx_queue_stats *stats)
3124{
3125 struct ath5k_softc *sc = hw->priv;
3126
3127 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3128
3129 return 0;
3130}
3131
3132static u64
3133ath5k_get_tsf(struct ieee80211_hw *hw)
3134{
3135 struct ath5k_softc *sc = hw->priv;
3136
3137 return ath5k_hw_get_tsf64(sc->ah);
3138}
3139
3b5d665b
AF		 3140static void
3141ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3142{
3143 struct ath5k_softc *sc = hw->priv;
3144
3145 ath5k_hw_set_tsf64(sc->ah, tsf);
3146}
3147
fa1c114f
JS		 3148static void
3149ath5k_reset_tsf(struct ieee80211_hw *hw)
3150{
3151 struct ath5k_softc *sc = hw->priv;
3152
9804b98d
BR		 3153 /*
3154 * in IBSS mode we need to update the beacon timers too.
3155 * this will also reset the TSF if we call it with 0
3156 */
05c914fe 3157 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3158 ath5k_beacon_update_timers(sc, 0);
3159 else
3160 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3161}
3162
3163static int
da966bca 3164ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3165{
00482973 3166 unsigned long flags;
fa1c114f
JS		 3167 int ret;
3168
3169 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3170
00482973 3171 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3172 ath5k_txbuf_free(sc, sc->bbuf);
3173 sc->bbuf->skb = skb;
e039fa4a 3174 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3175 if (ret)
3176 sc->bbuf->skb = NULL;
00482973
JS		 3177 spin_unlock_irqrestore(&sc->block, flags);
3178 if (!ret) {
fa1c114f 3179 ath5k_beacon_config(sc);
274c7c36
JS		 3180 mmiowb();
3181 }
fa1c114f 3182
fa1c114f
JS		 3183 return ret;
3184}
02969b38
MX		 3185static void
3186set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3187{
3188 struct ath5k_softc *sc = hw->priv;
3189 struct ath5k_hw *ah = sc->ah;
3190 u32 rfilt;
3191 rfilt = ath5k_hw_get_rx_filter(ah);
3192 if (enable)
3193 rfilt |= AR5K_RX_FILTER_BEACON;
3194 else
3195 rfilt &= ~AR5K_RX_FILTER_BEACON;
3196 ath5k_hw_set_rx_filter(ah, rfilt);
3197 sc->filter_flags = rfilt;
3198}
fa1c114f 3199
02969b38
MX		 3200static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3201 struct ieee80211_vif *vif,
3202 struct ieee80211_bss_conf *bss_conf,
3203 u32 changes)
3204{
3205 struct ath5k_softc *sc = hw->priv;
3206 if (changes & BSS_CHANGED_ASSOC) {
3207 mutex_lock(&sc->lock);
3208 sc->assoc = bss_conf->assoc;
3209 if (sc->opmode == NL80211_IFTYPE_STATION)
3210 set_beacon_filter(hw, sc->assoc);
3211 mutex_unlock(&sc->lock);
3212 }
3213}
Clone of davem's net-next-2.6 tree