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[net-next-2.6.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43#include <linux/version.h>
44#include <linux/module.h>
45#include <linux/delay.h>
46#include <linux/if.h>
47#include <linux/netdevice.h>
48#include <linux/cache.h>
49#include <linux/pci.h>
50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
52
53#include <net/ieee80211_radiotap.h>
54
55#include <asm/unaligned.h>
56
57#include "base.h"
58#include "reg.h"
59#include "debug.h"
60
61/* unaligned little endian access */
62#define LE_READ_2(_p) (le16_to_cpu(get_unaligned((__le16 *)(_p))))
63#define LE_READ_4(_p) (le32_to_cpu(get_unaligned((__le32 *)(_p))))
64
65enum {
66 ATH_LED_TX,
67 ATH_LED_RX,
68};
69
70static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
71
72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
83MODULE_VERSION("0.1.1 (EXPERIMENTAL)");
84
85
86/* Known PCI ids */
87static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
88 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
105 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
106 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
107 { 0 }
108};
109MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111/* Known SREVs */
112static struct ath5k_srev_name srev_names[] = {
113 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
114 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
115 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
116 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
117 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
118 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
119 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
120 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
121 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
122 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
123 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
124 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
125 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
126 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
127 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
128 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
129 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
130 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
131 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
132 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
136 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
139};
140
141/*
142 * Prototypes - PCI stack related functions
143 */
144static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
145 const struct pci_device_id *id);
146static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
147#ifdef CONFIG_PM
148static int ath5k_pci_suspend(struct pci_dev *pdev,
149 pm_message_t state);
150static int ath5k_pci_resume(struct pci_dev *pdev);
151#else
152#define ath5k_pci_suspend NULL
153#define ath5k_pci_resume NULL
154#endif /* CONFIG_PM */
155
04a9e451 156static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 157 .name = "ath5k_pci",
158 .id_table = ath5k_pci_id_table,
159 .probe = ath5k_pci_probe,
160 .remove = __devexit_p(ath5k_pci_remove),
161 .suspend = ath5k_pci_suspend,
162 .resume = ath5k_pci_resume,
163};
164
165
166
167/*
168 * Prototypes - MAC 802.11 stack related functions
169 */
170static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
171 struct ieee80211_tx_control *ctl);
172static int ath5k_reset(struct ieee80211_hw *hw);
173static int ath5k_start(struct ieee80211_hw *hw);
174static void ath5k_stop(struct ieee80211_hw *hw);
175static int ath5k_add_interface(struct ieee80211_hw *hw,
176 struct ieee80211_if_init_conf *conf);
177static void ath5k_remove_interface(struct ieee80211_hw *hw,
178 struct ieee80211_if_init_conf *conf);
179static int ath5k_config(struct ieee80211_hw *hw,
180 struct ieee80211_conf *conf);
32bfd35d
JB		 181static int ath5k_config_interface(struct ieee80211_hw *hw,
182 struct ieee80211_vif *vif,
fa1c114f
JS		 183 struct ieee80211_if_conf *conf);
184static void ath5k_configure_filter(struct ieee80211_hw *hw,
185 unsigned int changed_flags,
186 unsigned int *new_flags,
187 int mc_count, struct dev_mc_list *mclist);
188static int ath5k_set_key(struct ieee80211_hw *hw,
189 enum set_key_cmd cmd,
190 const u8 *local_addr, const u8 *addr,
191 struct ieee80211_key_conf *key);
192static int ath5k_get_stats(struct ieee80211_hw *hw,
193 struct ieee80211_low_level_stats *stats);
194static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
195 struct ieee80211_tx_queue_stats *stats);
196static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
197static void ath5k_reset_tsf(struct ieee80211_hw *hw);
198static int ath5k_beacon_update(struct ieee80211_hw *hw,
199 struct sk_buff *skb,
200 struct ieee80211_tx_control *ctl);
201
202static struct ieee80211_ops ath5k_hw_ops = {
203 .tx = ath5k_tx,
204 .start = ath5k_start,
205 .stop = ath5k_stop,
206 .add_interface = ath5k_add_interface,
207 .remove_interface = ath5k_remove_interface,
208 .config = ath5k_config,
209 .config_interface = ath5k_config_interface,
210 .configure_filter = ath5k_configure_filter,
211 .set_key = ath5k_set_key,
212 .get_stats = ath5k_get_stats,
213 .conf_tx = NULL,
214 .get_tx_stats = ath5k_get_tx_stats,
215 .get_tsf = ath5k_get_tsf,
216 .reset_tsf = ath5k_reset_tsf,
217 .beacon_update = ath5k_beacon_update,
218};
219
220/*
221 * Prototypes - Internal functions
222 */
223/* Attach detach */
224static int ath5k_attach(struct pci_dev *pdev,
225 struct ieee80211_hw *hw);
226static void ath5k_detach(struct pci_dev *pdev,
227 struct ieee80211_hw *hw);
228/* Channel/mode setup */
229static inline short ath5k_ieee2mhz(short chan);
230static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
231 const struct ath5k_rate_table *rt,
232 unsigned int max);
233static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
234 struct ieee80211_channel *channels,
235 unsigned int mode,
236 unsigned int max);
237static int ath5k_getchannels(struct ieee80211_hw *hw);
238static int ath5k_chan_set(struct ath5k_softc *sc,
239 struct ieee80211_channel *chan);
240static void ath5k_setcurmode(struct ath5k_softc *sc,
241 unsigned int mode);
242static void ath5k_mode_setup(struct ath5k_softc *sc);
243/* Descriptor setup */
244static int ath5k_desc_alloc(struct ath5k_softc *sc,
245 struct pci_dev *pdev);
246static void ath5k_desc_free(struct ath5k_softc *sc,
247 struct pci_dev *pdev);
248/* Buffers setup */
249static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
250 struct ath5k_buf *bf);
251static int ath5k_txbuf_setup(struct ath5k_softc *sc,
252 struct ath5k_buf *bf,
253 struct ieee80211_tx_control *ctl);
254
255static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
256 struct ath5k_buf *bf)
257{
258 BUG_ON(!bf);
259 if (!bf->skb)
260 return;
261 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
262 PCI_DMA_TODEVICE);
263 dev_kfree_skb(bf->skb);
264 bf->skb = NULL;
265}
266
267/* Queues setup */
268static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
269 int qtype, int subtype);
270static int ath5k_beaconq_setup(struct ath5k_hw *ah);
271static int ath5k_beaconq_config(struct ath5k_softc *sc);
272static void ath5k_txq_drainq(struct ath5k_softc *sc,
273 struct ath5k_txq *txq);
274static void ath5k_txq_cleanup(struct ath5k_softc *sc);
275static void ath5k_txq_release(struct ath5k_softc *sc);
276/* Rx handling */
277static int ath5k_rx_start(struct ath5k_softc *sc);
278static void ath5k_rx_stop(struct ath5k_softc *sc);
279static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
280 struct ath5k_desc *ds,
281 struct sk_buff *skb);
282static void ath5k_tasklet_rx(unsigned long data);
283/* Tx handling */
284static void ath5k_tx_processq(struct ath5k_softc *sc,
285 struct ath5k_txq *txq);
286static void ath5k_tasklet_tx(unsigned long data);
287/* Beacon handling */
288static int ath5k_beacon_setup(struct ath5k_softc *sc,
289 struct ath5k_buf *bf,
290 struct ieee80211_tx_control *ctl);
291static void ath5k_beacon_send(struct ath5k_softc *sc);
292static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 293static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 294
295static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
296{
297 u64 tsf = ath5k_hw_get_tsf64(ah);
298
299 if ((tsf & 0x7fff) < rstamp)
300 tsf -= 0x8000;
301
302 return (tsf & ~0x7fff) | rstamp;
303}
304
305/* Interrupt handling */
306static int ath5k_init(struct ath5k_softc *sc);
307static int ath5k_stop_locked(struct ath5k_softc *sc);
308static int ath5k_stop_hw(struct ath5k_softc *sc);
309static irqreturn_t ath5k_intr(int irq, void *dev_id);
310static void ath5k_tasklet_reset(unsigned long data);
311
312static void ath5k_calibrate(unsigned long data);
313/* LED functions */
314static void ath5k_led_off(unsigned long data);
315static void ath5k_led_blink(struct ath5k_softc *sc,
316 unsigned int on,
317 unsigned int off);
318static void ath5k_led_event(struct ath5k_softc *sc,
319 int event);
320
321
322/*
323 * Module init/exit functions
324 */
325static int __init
326init_ath5k_pci(void)
327{
328 int ret;
329
330 ath5k_debug_init();
331
04a9e451 332 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 333 if (ret) {
334 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
335 return ret;
336 }
337
338 return 0;
339}
340
341static void __exit
342exit_ath5k_pci(void)
343{
04a9e451 344 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 345
346 ath5k_debug_finish();
347}
348
349module_init(init_ath5k_pci);
350module_exit(exit_ath5k_pci);
351
352
353/********************\
354* PCI Initialization *
355\********************/
356
357static const char *
358ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
359{
360 const char *name = "xxxxx";
361 unsigned int i;
362
363 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
364 if (srev_names[i].sr_type != type)
365 continue;
366 if ((val & 0xff) < srev_names[i + 1].sr_val) {
367 name = srev_names[i].sr_name;
368 break;
369 }
370 }
371
372 return name;
373}
374
375static int __devinit
376ath5k_pci_probe(struct pci_dev *pdev,
377 const struct pci_device_id *id)
378{
379 void __iomem *mem;
380 struct ath5k_softc *sc;
381 struct ieee80211_hw *hw;
382 int ret;
383 u8 csz;
384
385 ret = pci_enable_device(pdev);
386 if (ret) {
387 dev_err(&pdev->dev, "can't enable device\n");
388 goto err;
389 }
390
391 /* XXX 32-bit addressing only */
392 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
393 if (ret) {
394 dev_err(&pdev->dev, "32-bit DMA not available\n");
395 goto err_dis;
396 }
397
398 /*
399 * Cache line size is used to size and align various
400 * structures used to communicate with the hardware.
401 */
402 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
403 if (csz == 0) {
404 /*
405 * Linux 2.4.18 (at least) writes the cache line size
406 * register as a 16-bit wide register which is wrong.
407 * We must have this setup properly for rx buffer
408 * DMA to work so force a reasonable value here if it
409 * comes up zero.
410 */
411 csz = L1_CACHE_BYTES / sizeof(u32);
412 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
413 }
414 /*
415 * The default setting of latency timer yields poor results,
416 * set it to the value used by other systems. It may be worth
417 * tweaking this setting more.
418 */
419 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
420
421 /* Enable bus mastering */
422 pci_set_master(pdev);
423
424 /*
425 * Disable the RETRY_TIMEOUT register (0x41) to keep
426 * PCI Tx retries from interfering with C3 CPU state.
427 */
428 pci_write_config_byte(pdev, 0x41, 0);
429
430 ret = pci_request_region(pdev, 0, "ath5k");
431 if (ret) {
432 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
433 goto err_dis;
434 }
435
436 mem = pci_iomap(pdev, 0, 0);
437 if (!mem) {
438 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
439 ret = -EIO;
440 goto err_reg;
441 }
442
443 /*
444 * Allocate hw (mac80211 main struct)
445 * and hw->priv (driver private data)
446 */
447 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
448 if (hw == NULL) {
449 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
450 ret = -ENOMEM;
451 goto err_map;
452 }
453
454 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
455
456 /* Initialize driver private data */
457 SET_IEEE80211_DEV(hw, &pdev->dev);
458 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS;
459 hw->extra_tx_headroom = 2;
460 hw->channel_change_time = 5000;
461 /* these names are misleading */
462 hw->max_rssi = -110; /* signal in dBm */
463 hw->max_noise = -110; /* noise in dBm */
464 hw->max_signal = 100; /* we will provide a percentage based on rssi */
465 sc = hw->priv;
466 sc->hw = hw;
467 sc->pdev = pdev;
468
469 ath5k_debug_init_device(sc);
470
471 /*
472 * Mark the device as detached to avoid processing
473 * interrupts until setup is complete.
474 */
475 __set_bit(ATH_STAT_INVALID, sc->status);
476
477 sc->iobase = mem; /* So we can unmap it on detach */
478 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
479 sc->opmode = IEEE80211_IF_TYPE_STA;
480 mutex_init(&sc->lock);
481 spin_lock_init(&sc->rxbuflock);
482 spin_lock_init(&sc->txbuflock);
483
484 /* Set private data */
485 pci_set_drvdata(pdev, hw);
486
487 /* Enable msi for devices that support it */
488 pci_enable_msi(pdev);
489
490 /* Setup interrupt handler */
491 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
492 if (ret) {
493 ATH5K_ERR(sc, "request_irq failed\n");
494 goto err_free;
495 }
496
497 /* Initialize device */
498 sc->ah = ath5k_hw_attach(sc, id->driver_data);
499 if (IS_ERR(sc->ah)) {
500 ret = PTR_ERR(sc->ah);
501 goto err_irq;
502 }
503
504 /* Finish private driver data initialization */
505 ret = ath5k_attach(pdev, hw);
506 if (ret)
507 goto err_ah;
508
509 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
510 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
511 sc->ah->ah_mac_srev,
512 sc->ah->ah_phy_revision);
513
514 if(!sc->ah->ah_single_chip){
515 /* Single chip radio (!RF5111) */
516 if(sc->ah->ah_radio_5ghz_revision && !sc->ah->ah_radio_2ghz_revision) {
517 /* No 5GHz support -> report 2GHz radio */
518 if(!test_bit(MODE_IEEE80211A, sc->ah->ah_capabilities.cap_mode)){
519 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
520 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
521 sc->ah->ah_radio_5ghz_revision);
522 /* No 2GHz support (5110 and some 5Ghz only cards) -> report 5Ghz radio */
523 } else if(!test_bit(MODE_IEEE80211B, sc->ah->ah_capabilities.cap_mode)){
524 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
525 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
526 sc->ah->ah_radio_5ghz_revision);
527 /* Multiband radio */
528 } else {
529 ATH5K_INFO(sc, "RF%s multiband radio found"
530 " (0x%x)\n",
531 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
532 sc->ah->ah_radio_5ghz_revision);
533 }
534 }
535 /* Multi chip radio (RF5111 - RF2111) -> report both 2GHz/5GHz radios */
536 else if(sc->ah->ah_radio_5ghz_revision && sc->ah->ah_radio_2ghz_revision){
537 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
538 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_5ghz_revision),
539 sc->ah->ah_radio_5ghz_revision);
540 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
541 ath5k_chip_name(AR5K_VERSION_RAD,sc->ah->ah_radio_2ghz_revision),
542 sc->ah->ah_radio_2ghz_revision);
543 }
544 }
545
546
547 /* ready to process interrupts */
548 __clear_bit(ATH_STAT_INVALID, sc->status);
549
550 return 0;
551err_ah:
552 ath5k_hw_detach(sc->ah);
553err_irq:
554 free_irq(pdev->irq, sc);
555err_free:
556 pci_disable_msi(pdev);
557 ieee80211_free_hw(hw);
558err_map:
559 pci_iounmap(pdev, mem);
560err_reg:
561 pci_release_region(pdev, 0);
562err_dis:
563 pci_disable_device(pdev);
564err:
565 return ret;
566}
567
568static void __devexit
569ath5k_pci_remove(struct pci_dev *pdev)
570{
571 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
572 struct ath5k_softc *sc = hw->priv;
573
574 ath5k_debug_finish_device(sc);
575 ath5k_detach(pdev, hw);
576 ath5k_hw_detach(sc->ah);
577 free_irq(pdev->irq, sc);
578 pci_disable_msi(pdev);
579 pci_iounmap(pdev, sc->iobase);
580 pci_release_region(pdev, 0);
581 pci_disable_device(pdev);
582 ieee80211_free_hw(hw);
583}
584
585#ifdef CONFIG_PM
586static int
587ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
588{
589 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
590 struct ath5k_softc *sc = hw->priv;
591
592 if (test_bit(ATH_STAT_LEDSOFT, sc->status))
593 ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
594
595 ath5k_stop_hw(sc);
596 pci_save_state(pdev);
597 pci_disable_device(pdev);
598 pci_set_power_state(pdev, PCI_D3hot);
599
600 return 0;
601}
602
603static int
604ath5k_pci_resume(struct pci_dev *pdev)
605{
606 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
607 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 608 struct ath5k_hw *ah = sc->ah;
609 int i, err;
fa1c114f
JS		 610
611 err = pci_set_power_state(pdev, PCI_D0);
612 if (err)
613 return err;
614
615 err = pci_enable_device(pdev);
616 if (err)
617 return err;
618
619 pci_restore_state(pdev);
620 /*
621 * Suspend/Resume resets the PCI configuration space, so we have to
622 * re-disable the RETRY_TIMEOUT register (0x41) to keep
623 * PCI Tx retries from interfering with C3 CPU state
624 */
625 pci_write_config_byte(pdev, 0x41, 0);
626
627 ath5k_init(sc);
628 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
247ae449
JL		 629 ath5k_hw_set_gpio_output(ah, sc->led_pin);
630 ath5k_hw_set_gpio(ah, sc->led_pin, 0);
fa1c114f
JS		 631 }
632
247ae449
JL		 633 /*
634 * Reset the key cache since some parts do not
635 * reset the contents on initial power up or resume.
636 *
637 * FIXME: This may need to be revisited when mac80211 becomes
638 * aware of suspend/resume.
639 */
640 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
641 ath5k_hw_reset_key(ah, i);
642
fa1c114f
JS		 643 return 0;
644}
645#endif /* CONFIG_PM */
646
647
648
649/***********************\
650* Driver Initialization *
651\***********************/
652
653static int
654ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
655{
656 struct ath5k_softc *sc = hw->priv;
657 struct ath5k_hw *ah = sc->ah;
658 u8 mac[ETH_ALEN];
659 unsigned int i;
660 int ret;
661
662 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
663
664 /*
665 * Check if the MAC has multi-rate retry support.
666 * We do this by trying to setup a fake extended
667 * descriptor. MAC's that don't have support will
668 * return false w/o doing anything. MAC's that do
669 * support it will return true w/o doing anything.
670 */
b9887638
JS		 671 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
672 if (ret < 0)
673 goto err;
674 if (ret > 0)
fa1c114f
JS		 675 __set_bit(ATH_STAT_MRRETRY, sc->status);
676
677 /*
678 * Reset the key cache since some parts do not
679 * reset the contents on initial power up.
680 */
c65638a7 681 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 682 ath5k_hw_reset_key(ah, i);
683
684 /*
685 * Collect the channel list. The 802.11 layer
686 * is resposible for filtering this list based
687 * on settings like the phy mode and regulatory
688 * domain restrictions.
689 */
690 ret = ath5k_getchannels(hw);
691 if (ret) {
692 ATH5K_ERR(sc, "can't get channels\n");
693 goto err;
694 }
695
696 /* NB: setup here so ath5k_rate_update is happy */
697 if (test_bit(MODE_IEEE80211A, ah->ah_modes))
698 ath5k_setcurmode(sc, MODE_IEEE80211A);
699 else
700 ath5k_setcurmode(sc, MODE_IEEE80211B);
701
702 /*
703 * Allocate tx+rx descriptors and populate the lists.
704 */
705 ret = ath5k_desc_alloc(sc, pdev);
706 if (ret) {
707 ATH5K_ERR(sc, "can't allocate descriptors\n");
708 goto err;
709 }
710
711 /*
712 * Allocate hardware transmit queues: one queue for
713 * beacon frames and one data queue for each QoS
714 * priority. Note that hw functions handle reseting
715 * these queues at the needed time.
716 */
717 ret = ath5k_beaconq_setup(ah);
718 if (ret < 0) {
719 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
720 goto err_desc;
721 }
722 sc->bhalq = ret;
723
724 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
725 if (IS_ERR(sc->txq)) {
726 ATH5K_ERR(sc, "can't setup xmit queue\n");
727 ret = PTR_ERR(sc->txq);
728 goto err_bhal;
729 }
730
731 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
732 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
733 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
734 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
735 setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
736
737 sc->led_on = 0; /* low true */
738 /*
739 * Auto-enable soft led processing for IBM cards and for
740 * 5211 minipci cards.
741 */
742 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
743 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
744 __set_bit(ATH_STAT_LEDSOFT, sc->status);
745 sc->led_pin = 0;
746 }
747 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
748 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
749 __set_bit(ATH_STAT_LEDSOFT, sc->status);
750 sc->led_pin = 0;
751 }
752 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
753 ath5k_hw_set_gpio_output(ah, sc->led_pin);
754 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
755 }
756
757 ath5k_hw_get_lladdr(ah, mac);
758 SET_IEEE80211_PERM_ADDR(hw, mac);
759 /* All MAC address bits matter for ACKs */
760 memset(sc->bssidmask, 0xff, ETH_ALEN);
761 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
762
763 ret = ieee80211_register_hw(hw);
764 if (ret) {
765 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
766 goto err_queues;
767 }
768
769 return 0;
770err_queues:
771 ath5k_txq_release(sc);
772err_bhal:
773 ath5k_hw_release_tx_queue(ah, sc->bhalq);
774err_desc:
775 ath5k_desc_free(sc, pdev);
776err:
777 return ret;
778}
779
780static void
781ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
782{
783 struct ath5k_softc *sc = hw->priv;
784
785 /*
786 * NB: the order of these is important:
787 * o call the 802.11 layer before detaching ath5k_hw to
788 * insure callbacks into the driver to delete global
789 * key cache entries can be handled
790 * o reclaim the tx queue data structures after calling
791 * the 802.11 layer as we'll get called back to reclaim
792 * node state and potentially want to use them
793 * o to cleanup the tx queues the hal is called, so detach
794 * it last
795 * XXX: ??? detach ath5k_hw ???
796 * Other than that, it's straightforward...
797 */
798 ieee80211_unregister_hw(hw);
799 ath5k_desc_free(sc, pdev);
800 ath5k_txq_release(sc);
801 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
802
803 /*
804 * NB: can't reclaim these until after ieee80211_ifdetach
805 * returns because we'll get called back to reclaim node
806 * state and potentially want to use them.
807 */
808}
809
810
811
812
813/********************\
814* Channel/mode setup *
815\********************/
816
817/*
818 * Convert IEEE channel number to MHz frequency.
819 */
820static inline short
821ath5k_ieee2mhz(short chan)
822{
823 if (chan <= 14 || chan >= 27)
824 return ieee80211chan2mhz(chan);
825 else
826 return 2212 + chan * 20;
827}
828
829static unsigned int
830ath5k_copy_rates(struct ieee80211_rate *rates,
831 const struct ath5k_rate_table *rt,
832 unsigned int max)
833{
834 unsigned int i, count;
835
836 if (rt == NULL)
837 return 0;
838
839 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
840 if (!rt->rates[i].valid)
841 continue;
842 rates->rate = rt->rates[i].rate_kbps / 100;
843 rates->val = rt->rates[i].rate_code;
844 rates->flags = rt->rates[i].modulation;
845 rates++;
846 count++;
847 max--;
848 }
849
850 return count;
851}
852
853static unsigned int
854ath5k_copy_channels(struct ath5k_hw *ah,
855 struct ieee80211_channel *channels,
856 unsigned int mode,
857 unsigned int max)
858{
859 static const struct { unsigned int mode, mask, chan; } map[] = {
860 [MODE_IEEE80211A] = { CHANNEL_OFDM, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_A },
861 [MODE_ATHEROS_TURBO] = { CHANNEL_OFDM|CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_T },
862 [MODE_IEEE80211B] = { CHANNEL_CCK, CHANNEL_CCK, CHANNEL_B },
863 [MODE_IEEE80211G] = { CHANNEL_OFDM, CHANNEL_OFDM, CHANNEL_G },
864 [MODE_ATHEROS_TURBOG] = { CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_OFDM | CHANNEL_TURBO, CHANNEL_TG },
865 };
866 static const struct ath5k_regchannel chans_2ghz[] =
867 IEEE80211_CHANNELS_2GHZ;
868 static const struct ath5k_regchannel chans_5ghz[] =
869 IEEE80211_CHANNELS_5GHZ;
870 const struct ath5k_regchannel *chans;
871 enum ath5k_regdom dmn;
872 unsigned int i, count, size, chfreq, all, f, ch;
873
874 if (!test_bit(mode, ah->ah_modes))
875 return 0;
876
877 all = ah->ah_regdomain == DMN_DEFAULT || CHAN_DEBUG == 1;
878
879 switch (mode) {
880 case MODE_IEEE80211A:
881 case MODE_ATHEROS_TURBO:
882 /* 1..220, but 2GHz frequencies are filtered by check_channel */
883 size = all ? 220 : ARRAY_SIZE(chans_5ghz);
884 chans = chans_5ghz;
885 dmn = ath5k_regdom2flag(ah->ah_regdomain,
886 IEEE80211_CHANNELS_5GHZ_MIN);
887 chfreq = CHANNEL_5GHZ;
888 break;
889 case MODE_IEEE80211B:
890 case MODE_IEEE80211G:
891 case MODE_ATHEROS_TURBOG:
892 size = all ? 26 : ARRAY_SIZE(chans_2ghz);
893 chans = chans_2ghz;
894 dmn = ath5k_regdom2flag(ah->ah_regdomain,
895 IEEE80211_CHANNELS_2GHZ_MIN);
896 chfreq = CHANNEL_2GHZ;
897 break;
898 default:
899 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
900 return 0;
901 }
902
903 for (i = 0, count = 0; i < size && max > 0; i++) {
904 ch = all ? i + 1 : chans[i].chan;
905 f = ath5k_ieee2mhz(ch);
906 /* Check if channel is supported by the chipset */
907 if (!ath5k_channel_ok(ah, f, chfreq))
908 continue;
909
910 /* Match regulation domain */
911 if (!all && !(IEEE80211_DMN(chans[i].domain) &
912 IEEE80211_DMN(dmn)))
913 continue;
914
915 if (!all && (chans[i].mode & map[mode].mask) != map[mode].mode)
916 continue;
917
918 /* Write channel and increment counter */
919 channels->chan = ch;
920 channels->freq = f;
921 channels->val = map[mode].chan;
922 channels++;
923 count++;
924 max--;
925 }
926
927 return count;
928}
929
930/* Only tries to register modes our EEPROM says it can support */
931#define REGISTER_MODE(m) do { \
932 ret = ath5k_register_mode(hw, m); \
933 if (ret) \
934 return ret; \
935} while (0) \
936
937static inline int
938ath5k_register_mode(struct ieee80211_hw *hw, u8 m)
939{
940 struct ath5k_softc *sc = hw->priv;
941 struct ieee80211_hw_mode *modes = sc->modes;
942 unsigned int i;
943 int ret;
944
945 if (!test_bit(m, sc->ah->ah_capabilities.cap_mode))
946 return 0;
947
948 for (i = 0; i < NUM_DRIVER_MODES; i++) {
949 if (modes[i].mode != m || !modes[i].num_channels)
950 continue;
951 ret = ieee80211_register_hwmode(hw, &modes[i]);
952 if (ret) {
953 ATH5K_ERR(sc, "can't register hwmode %u\n", m);
954 return ret;
955 }
956 return 0;
957 }
958 BUG();
959}
960
961static int
962ath5k_getchannels(struct ieee80211_hw *hw)
963{
964 struct ath5k_softc *sc = hw->priv;
965 struct ath5k_hw *ah = sc->ah;
966 struct ieee80211_hw_mode *modes = sc->modes;
967 unsigned int i, max_r, max_c;
968 int ret;
969
970 BUILD_BUG_ON(ARRAY_SIZE(sc->modes) < 3);
971
972 /* The order here does not matter */
973 modes[0].mode = MODE_IEEE80211G;
974 modes[1].mode = MODE_IEEE80211B;
975 modes[2].mode = MODE_IEEE80211A;
976
977 max_r = ARRAY_SIZE(sc->rates);
978 max_c = ARRAY_SIZE(sc->channels);
979
980 for (i = 0; i < NUM_DRIVER_MODES; i++) {
981 struct ieee80211_hw_mode *mode = &modes[i];
982 const struct ath5k_rate_table *hw_rates;
983
984 if (i == 0) {
985 modes[0].rates = sc->rates;
986 modes->channels = sc->channels;
987 } else {
988 struct ieee80211_hw_mode *prev_mode = &modes[i-1];
989 int prev_num_r = prev_mode->num_rates;
990 int prev_num_c = prev_mode->num_channels;
991 mode->rates = &prev_mode->rates[prev_num_r];
992 mode->channels = &prev_mode->channels[prev_num_c];
993 }
994
995 hw_rates = ath5k_hw_get_rate_table(ah, mode->mode);
996 mode->num_rates = ath5k_copy_rates(mode->rates, hw_rates,
997 max_r);
998 mode->num_channels = ath5k_copy_channels(ah, mode->channels,
999 mode->mode, max_c);
1000 max_r -= mode->num_rates;
1001 max_c -= mode->num_channels;
1002 }
1003
1004 /* We try to register all modes this driver supports. We don't bother
1005 * with MODE_IEEE80211B for AR5212 as MODE_IEEE80211G already accounts
1006 * for that as per mac80211. Then, REGISTER_MODE() will will actually
1007 * check the eeprom reading for more reliable capability information.
1008 * Order matters here as per mac80211's latest preference. This will
1009 * all hopefullly soon go away. */
1010
1011 REGISTER_MODE(MODE_IEEE80211G);
1012 if (ah->ah_version != AR5K_AR5212)
1013 REGISTER_MODE(MODE_IEEE80211B);
1014 REGISTER_MODE(MODE_IEEE80211A);
1015
1016 ath5k_debug_dump_modes(sc, modes);
1017
1018 return ret;
1019}
1020
1021/*
1022 * Set/change channels. If the channel is really being changed,
1023 * it's done by reseting the chip. To accomplish this we must
1024 * first cleanup any pending DMA, then restart stuff after a la
1025 * ath5k_init.
1026 */
1027static int
1028ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1029{
1030 struct ath5k_hw *ah = sc->ah;
1031 int ret;
1032
1033 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "%u (%u MHz) -> %u (%u MHz)\n",
1034 sc->curchan->chan, sc->curchan->freq,
1035 chan->chan, chan->freq);
1036
1037 if (chan->freq != sc->curchan->freq || chan->val != sc->curchan->val) {
1038 /*
1039 * To switch channels clear any pending DMA operations;
1040 * wait long enough for the RX fifo to drain, reset the
1041 * hardware at the new frequency, and then re-enable
1042 * the relevant bits of the h/w.
1043 */
1044 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
1045 ath5k_txq_cleanup(sc); /* clear pending tx frames */
1046 ath5k_rx_stop(sc); /* turn off frame recv */
1047 ret = ath5k_hw_reset(ah, sc->opmode, chan, true);
1048 if (ret) {
1049 ATH5K_ERR(sc, "%s: unable to reset channel %u "
1050 "(%u Mhz)\n", __func__, chan->chan, chan->freq);
1051 return ret;
1052 }
1053 sc->curchan = chan;
1054 ath5k_hw_set_txpower_limit(sc->ah, 0);
1055
1056 /*
1057 * Re-enable rx framework.
1058 */
1059 ret = ath5k_rx_start(sc);
1060 if (ret) {
1061 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1062 __func__);
1063 return ret;
1064 }
1065
1066 /*
1067 * Change channels and update the h/w rate map
1068 * if we're switching; e.g. 11a to 11b/g.
1069 *
1070 * XXX needed?
1071 */
1072/* ath5k_chan_change(sc, chan); */
1073
1074 ath5k_beacon_config(sc);
1075 /*
1076 * Re-enable interrupts.
1077 */
1078 ath5k_hw_set_intr(ah, sc->imask);
1079 }
1080
1081 return 0;
1082}
1083
1084static void
1085ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1086{
1087 if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
1088 /* from Atheros NDIS driver, w/ permission */
1089 static const struct {
1090 u16 rate; /* tx/rx 802.11 rate */
1091 u16 timeOn; /* LED on time (ms) */
1092 u16 timeOff; /* LED off time (ms) */
1093 } blinkrates[] = {
1094 { 108, 40, 10 },
1095 { 96, 44, 11 },
1096 { 72, 50, 13 },
1097 { 48, 57, 14 },
1098 { 36, 67, 16 },
1099 { 24, 80, 20 },
1100 { 22, 100, 25 },
1101 { 18, 133, 34 },
1102 { 12, 160, 40 },
1103 { 10, 200, 50 },
1104 { 6, 240, 58 },
1105 { 4, 267, 66 },
1106 { 2, 400, 100 },
1107 { 0, 500, 130 }
1108 };
1109 const struct ath5k_rate_table *rt =
1110 ath5k_hw_get_rate_table(sc->ah, mode);
1111 unsigned int i, j;
1112
1113 BUG_ON(rt == NULL);
1114
1115 memset(sc->hwmap, 0, sizeof(sc->hwmap));
1116 for (i = 0; i < 32; i++) {
1117 u8 ix = rt->rate_code_to_index[i];
1118 if (ix == 0xff) {
1119 sc->hwmap[i].ledon = msecs_to_jiffies(500);
1120 sc->hwmap[i].ledoff = msecs_to_jiffies(130);
1121 continue;
1122 }
1123 sc->hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
1124 if (SHPREAMBLE_FLAG(ix) || rt->rates[ix].modulation ==
1125 IEEE80211_RATE_OFDM)
1126 sc->hwmap[i].txflags |=
1127 IEEE80211_RADIOTAP_F_SHORTPRE;
1128 /* receive frames include FCS */
1129 sc->hwmap[i].rxflags = sc->hwmap[i].txflags |
1130 IEEE80211_RADIOTAP_F_FCS;
1131 /* setup blink rate table to avoid per-packet lookup */
1132 for (j = 0; j < ARRAY_SIZE(blinkrates) - 1; j++)
1133 if (blinkrates[j].rate == /* XXX why 7f? */
1134 (rt->rates[ix].dot11_rate&0x7f))
1135 break;
1136
1137 sc->hwmap[i].ledon = msecs_to_jiffies(blinkrates[j].
1138 timeOn);
1139 sc->hwmap[i].ledoff = msecs_to_jiffies(blinkrates[j].
1140 timeOff);
1141 }
1142 }
1143
1144 sc->curmode = mode;
1145}
1146
1147static void
1148ath5k_mode_setup(struct ath5k_softc *sc)
1149{
1150 struct ath5k_hw *ah = sc->ah;
1151 u32 rfilt;
1152
1153 /* configure rx filter */
1154 rfilt = sc->filter_flags;
1155 ath5k_hw_set_rx_filter(ah, rfilt);
1156
1157 if (ath5k_hw_hasbssidmask(ah))
1158 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1159
1160 /* configure operational mode */
1161 ath5k_hw_set_opmode(ah);
1162
1163 ath5k_hw_set_mcast_filter(ah, 0, 0);
1164 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1165}
1166
1167
1168
1169
1170/***************\
1171* Buffers setup *
1172\***************/
1173
1174static int
1175ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1176{
1177 struct ath5k_hw *ah = sc->ah;
1178 struct sk_buff *skb = bf->skb;
1179 struct ath5k_desc *ds;
1180
1181 if (likely(skb == NULL)) {
1182 unsigned int off;
1183
1184 /*
1185 * Allocate buffer with headroom_needed space for the
1186 * fake physical layer header at the start.
1187 */
1188 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1189 if (unlikely(skb == NULL)) {
1190 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1191 sc->rxbufsize + sc->cachelsz - 1);
1192 return -ENOMEM;
1193 }
1194 /*
1195 * Cache-line-align. This is important (for the
1196 * 5210 at least) as not doing so causes bogus data
1197 * in rx'd frames.
1198 */
1199 off = ((unsigned long)skb->data) % sc->cachelsz;
1200 if (off != 0)
1201 skb_reserve(skb, sc->cachelsz - off);
1202
1203 bf->skb = skb;
1204 bf->skbaddr = pci_map_single(sc->pdev,
1205 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1206 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1207 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1208 dev_kfree_skb(skb);
1209 bf->skb = NULL;
1210 return -ENOMEM;
1211 }
1212 }
1213
1214 /*
1215 * Setup descriptors. For receive we always terminate
1216 * the descriptor list with a self-linked entry so we'll
1217 * not get overrun under high load (as can happen with a
1218 * 5212 when ANI processing enables PHY error frames).
1219 *
1220 * To insure the last descriptor is self-linked we create
1221 * each descriptor as self-linked and add it to the end. As
1222 * each additional descriptor is added the previous self-linked
1223 * entry is ``fixed'' naturally. This should be safe even
1224 * if DMA is happening. When processing RX interrupts we
1225 * never remove/process the last, self-linked, entry on the
1226 * descriptor list. This insures the hardware always has
1227 * someplace to write a new frame.
1228 */
1229 ds = bf->desc;
1230 ds->ds_link = bf->daddr; /* link to self */
1231 ds->ds_data = bf->skbaddr;
1232 ath5k_hw_setup_rx_desc(ah, ds,
1233 skb_tailroom(skb), /* buffer size */
1234 0);
1235
1236 if (sc->rxlink != NULL)
1237 *sc->rxlink = bf->daddr;
1238 sc->rxlink = &ds->ds_link;
1239 return 0;
1240}
1241
1242static int
1243ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1244 struct ieee80211_tx_control *ctl)
1245{
1246 struct ath5k_hw *ah = sc->ah;
1247 struct ath5k_txq *txq = sc->txq;
1248 struct ath5k_desc *ds = bf->desc;
1249 struct sk_buff *skb = bf->skb;
1250 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1251 int ret;
1252
1253 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1254 bf->ctl = *ctl;
1255 /* XXX endianness */
1256 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1257 PCI_DMA_TODEVICE);
1258
1259 if (ctl->flags & IEEE80211_TXCTL_NO_ACK)
1260 flags |= AR5K_TXDESC_NOACK;
1261
281c56dd 1262 pktlen = skb->len;
fa1c114f
JS		 1263
1264 if (!(ctl->flags & IEEE80211_TXCTL_DO_NOT_ENCRYPT)) {
1265 keyidx = ctl->key_idx;
1266 pktlen += ctl->icv_len;
1267 }
1268
1269 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1270 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1271 (ctl->power_level * 2), ctl->tx_rate, ctl->retry_limit, keyidx, 0, flags, 0, 0);
1272 if (ret)
1273 goto err_unmap;
1274
1275 ds->ds_link = 0;
1276 ds->ds_data = bf->skbaddr;
1277
1278 spin_lock_bh(&txq->lock);
1279 list_add_tail(&bf->list, &txq->q);
1280 sc->tx_stats.data[txq->qnum].len++;
1281 if (txq->link == NULL) /* is this first packet? */
1282 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1283 else /* no, so only link it */
1284 *txq->link = bf->daddr;
1285
1286 txq->link = &ds->ds_link;
1287 ath5k_hw_tx_start(ah, txq->qnum);
1288 spin_unlock_bh(&txq->lock);
1289
1290 return 0;
1291err_unmap:
1292 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1293 return ret;
1294}
1295
1296/*******************\
1297* Descriptors setup *
1298\*******************/
1299
1300static int
1301ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1302{
1303 struct ath5k_desc *ds;
1304 struct ath5k_buf *bf;
1305 dma_addr_t da;
1306 unsigned int i;
1307 int ret;
1308
1309 /* allocate descriptors */
1310 sc->desc_len = sizeof(struct ath5k_desc) *
1311 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1312 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1313 if (sc->desc == NULL) {
1314 ATH5K_ERR(sc, "can't allocate descriptors\n");
1315 ret = -ENOMEM;
1316 goto err;
1317 }
1318 ds = sc->desc;
1319 da = sc->desc_daddr;
1320 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1321 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1322
1323 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1324 sizeof(struct ath5k_buf), GFP_KERNEL);
1325 if (bf == NULL) {
1326 ATH5K_ERR(sc, "can't allocate bufptr\n");
1327 ret = -ENOMEM;
1328 goto err_free;
1329 }
1330 sc->bufptr = bf;
1331
1332 INIT_LIST_HEAD(&sc->rxbuf);
1333 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1334 bf->desc = ds;
1335 bf->daddr = da;
1336 list_add_tail(&bf->list, &sc->rxbuf);
1337 }
1338
1339 INIT_LIST_HEAD(&sc->txbuf);
1340 sc->txbuf_len = ATH_TXBUF;
1341 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1342 da += sizeof(*ds)) {
1343 bf->desc = ds;
1344 bf->daddr = da;
1345 list_add_tail(&bf->list, &sc->txbuf);
1346 }
1347
1348 /* beacon buffer */
1349 bf->desc = ds;
1350 bf->daddr = da;
1351 sc->bbuf = bf;
1352
1353 return 0;
1354err_free:
1355 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1356err:
1357 sc->desc = NULL;
1358 return ret;
1359}
1360
1361static void
1362ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1363{
1364 struct ath5k_buf *bf;
1365
1366 ath5k_txbuf_free(sc, sc->bbuf);
1367 list_for_each_entry(bf, &sc->txbuf, list)
1368 ath5k_txbuf_free(sc, bf);
1369 list_for_each_entry(bf, &sc->rxbuf, list)
1370 ath5k_txbuf_free(sc, bf);
1371
1372 /* Free memory associated with all descriptors */
1373 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1374
1375 kfree(sc->bufptr);
1376 sc->bufptr = NULL;
1377}
1378
1379
1380
1381
1382
1383/**************\
1384* Queues setup *
1385\**************/
1386
1387static struct ath5k_txq *
1388ath5k_txq_setup(struct ath5k_softc *sc,
1389 int qtype, int subtype)
1390{
1391 struct ath5k_hw *ah = sc->ah;
1392 struct ath5k_txq *txq;
1393 struct ath5k_txq_info qi = {
1394 .tqi_subtype = subtype,
1395 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1396 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1397 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1398 };
1399 int qnum;
1400
1401 /*
1402 * Enable interrupts only for EOL and DESC conditions.
1403 * We mark tx descriptors to receive a DESC interrupt
1404 * when a tx queue gets deep; otherwise waiting for the
1405 * EOL to reap descriptors. Note that this is done to
1406 * reduce interrupt load and this only defers reaping
1407 * descriptors, never transmitting frames. Aside from
1408 * reducing interrupts this also permits more concurrency.
1409 * The only potential downside is if the tx queue backs
1410 * up in which case the top half of the kernel may backup
1411 * due to a lack of tx descriptors.
1412 */
1413 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1414 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1415 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1416 if (qnum < 0) {
1417 /*
1418 * NB: don't print a message, this happens
1419 * normally on parts with too few tx queues
1420 */
1421 return ERR_PTR(qnum);
1422 }
1423 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1424 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1425 qnum, ARRAY_SIZE(sc->txqs));
1426 ath5k_hw_release_tx_queue(ah, qnum);
1427 return ERR_PTR(-EINVAL);
1428 }
1429 txq = &sc->txqs[qnum];
1430 if (!txq->setup) {
1431 txq->qnum = qnum;
1432 txq->link = NULL;
1433 INIT_LIST_HEAD(&txq->q);
1434 spin_lock_init(&txq->lock);
1435 txq->setup = true;
1436 }
1437 return &sc->txqs[qnum];
1438}
1439
1440static int
1441ath5k_beaconq_setup(struct ath5k_hw *ah)
1442{
1443 struct ath5k_txq_info qi = {
1444 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1445 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1446 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1447 /* NB: for dynamic turbo, don't enable any other interrupts */
1448 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1449 };
1450
1451 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1452}
1453
1454static int
1455ath5k_beaconq_config(struct ath5k_softc *sc)
1456{
1457 struct ath5k_hw *ah = sc->ah;
1458 struct ath5k_txq_info qi;
1459 int ret;
1460
1461 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1462 if (ret)
1463 return ret;
6d91e1d8 1464 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
fa1c114f
JS		 1465 /*
1466 * Always burst out beacon and CAB traffic
1467 * (aifs = cwmin = cwmax = 0)
1468 */
1469 qi.tqi_aifs = 0;
1470 qi.tqi_cw_min = 0;
1471 qi.tqi_cw_max = 0;
6d91e1d8
BR		 1472 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1473 /*
1474 * Adhoc mode; backoff between 0 and (2 * cw_min).
1475 */
1476 qi.tqi_aifs = 0;
1477 qi.tqi_cw_min = 0;
1478 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1479 }
1480
6d91e1d8
BR		 1481 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1482 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1483 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1484
fa1c114f
JS		 1485 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1486 if (ret) {
1487 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1488 "hardware queue!\n", __func__);
1489 return ret;
1490 }
1491
1492 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1493}
1494
1495static void
1496ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1497{
1498 struct ath5k_buf *bf, *bf0;
1499
1500 /*
1501 * NB: this assumes output has been stopped and
1502 * we do not need to block ath5k_tx_tasklet
1503 */
1504 spin_lock_bh(&txq->lock);
1505 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1506 ath5k_debug_printtxbuf(sc, bf, !sc->ah->ah_proc_tx_desc(sc->ah,
1507 bf->desc));
1508
1509 ath5k_txbuf_free(sc, bf);
1510
1511 spin_lock_bh(&sc->txbuflock);
1512 sc->tx_stats.data[txq->qnum].len--;
1513 list_move_tail(&bf->list, &sc->txbuf);
1514 sc->txbuf_len++;
1515 spin_unlock_bh(&sc->txbuflock);
1516 }
1517 txq->link = NULL;
1518 spin_unlock_bh(&txq->lock);
1519}
1520
1521/*
1522 * Drain the transmit queues and reclaim resources.
1523 */
1524static void
1525ath5k_txq_cleanup(struct ath5k_softc *sc)
1526{
1527 struct ath5k_hw *ah = sc->ah;
1528 unsigned int i;
1529
1530 /* XXX return value */
1531 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1532 /* don't touch the hardware if marked invalid */
1533 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1534 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1535 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1536 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1537 if (sc->txqs[i].setup) {
1538 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1539 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1540 "link %p\n",
1541 sc->txqs[i].qnum,
1542 ath5k_hw_get_tx_buf(ah,
1543 sc->txqs[i].qnum),
1544 sc->txqs[i].link);
1545 }
1546 }
1547 ieee80211_start_queues(sc->hw); /* XXX move to callers */
1548
1549 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1550 if (sc->txqs[i].setup)
1551 ath5k_txq_drainq(sc, &sc->txqs[i]);
1552}
1553
1554static void
1555ath5k_txq_release(struct ath5k_softc *sc)
1556{
1557 struct ath5k_txq *txq = sc->txqs;
1558 unsigned int i;
1559
1560 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1561 if (txq->setup) {
1562 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1563 txq->setup = false;
1564 }
1565}
1566
1567
1568
1569
1570/*************\
1571* RX Handling *
1572\*************/
1573
1574/*
1575 * Enable the receive h/w following a reset.
1576 */
1577static int
1578ath5k_rx_start(struct ath5k_softc *sc)
1579{
1580 struct ath5k_hw *ah = sc->ah;
1581 struct ath5k_buf *bf;
1582 int ret;
1583
1584 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1585
1586 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1587 sc->cachelsz, sc->rxbufsize);
1588
1589 sc->rxlink = NULL;
1590
1591 spin_lock_bh(&sc->rxbuflock);
1592 list_for_each_entry(bf, &sc->rxbuf, list) {
1593 ret = ath5k_rxbuf_setup(sc, bf);
1594 if (ret != 0) {
1595 spin_unlock_bh(&sc->rxbuflock);
1596 goto err;
1597 }
1598 }
1599 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1600 spin_unlock_bh(&sc->rxbuflock);
1601
1602 ath5k_hw_put_rx_buf(ah, bf->daddr);
1603 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1604 ath5k_mode_setup(sc); /* set filters, etc. */
1605 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1606
1607 return 0;
1608err:
1609 return ret;
1610}
1611
1612/*
1613 * Disable the receive h/w in preparation for a reset.
1614 */
1615static void
1616ath5k_rx_stop(struct ath5k_softc *sc)
1617{
1618 struct ath5k_hw *ah = sc->ah;
1619
1620 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1621 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1622 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1623 mdelay(3); /* 3ms is long enough for 1 frame */
1624
1625 ath5k_debug_printrxbuffs(sc, ah);
1626
1627 sc->rxlink = NULL; /* just in case */
1628}
1629
1630static unsigned int
1631ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1632 struct sk_buff *skb)
1633{
1634 struct ieee80211_hdr *hdr = (void *)skb->data;
1635 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1636
1637 if (!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1638 ds->ds_rxstat.rs_keyix != AR5K_RXKEYIX_INVALID)
1639 return RX_FLAG_DECRYPTED;
1640
1641 /* Apparently when a default key is used to decrypt the packet
1642 the hw does not set the index used to decrypt. In such cases
1643 get the index from the packet. */
1644 if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
1645 !(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
1646 skb->len >= hlen + 4) {
1647 keyix = skb->data[hlen + 3] >> 6;
1648
1649 if (test_bit(keyix, sc->keymap))
1650 return RX_FLAG_DECRYPTED;
1651 }
1652
1653 return 0;
1654}
1655
036cd1ec
BR		 1656
1657static void
1658ath5k_check_ibss_hw_merge(struct ath5k_softc *sc, struct sk_buff *skb)
1659{
1660 u32 hw_tu;
1661 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1662
1663 if ((mgmt->frame_control & IEEE80211_FCTL_FTYPE) ==
1664 IEEE80211_FTYPE_MGMT &&
1665 (mgmt->frame_control & IEEE80211_FCTL_STYPE) ==
1666 IEEE80211_STYPE_BEACON &&
1667 mgmt->u.beacon.capab_info & WLAN_CAPABILITY_IBSS &&
1668 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1669 /*
1670 * Received an IBSS beacon with the same BSSID. Hardware might
1671 * have updated the TSF, check if we need to update timers.
1672 */
1673 hw_tu = TSF_TO_TU(ath5k_hw_get_tsf64(sc->ah));
1674 if (hw_tu >= sc->nexttbtt) {
1675 ath5k_beacon_update_timers(sc,
1676 mgmt->u.beacon.timestamp);
1677 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1678 "detected HW merge from received beacon\n");
1679 }
1680 }
1681}
1682
1683
fa1c114f
JS		 1684static void
1685ath5k_tasklet_rx(unsigned long data)
1686{
1687 struct ieee80211_rx_status rxs = {};
1688 struct sk_buff *skb;
1689 struct ath5k_softc *sc = (void *)data;
1690 struct ath5k_buf *bf;
1691 struct ath5k_desc *ds;
1692 u16 len;
1693 u8 stat;
1694 int ret;
1695 int hdrlen;
1696 int pad;
1697
1698 spin_lock(&sc->rxbuflock);
1699 do {
1700 if (unlikely(list_empty(&sc->rxbuf))) {
1701 ATH5K_WARN(sc, "empty rx buf pool\n");
1702 break;
1703 }
1704 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1705 BUG_ON(bf->skb == NULL);
1706 skb = bf->skb;
1707 ds = bf->desc;
1708
1709 /* TODO only one segment */
1710 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1711 sc->desc_len, PCI_DMA_FROMDEVICE);
1712
1713 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1714 break;
1715
1716 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds);
1717 if (unlikely(ret == -EINPROGRESS))
1718 break;
1719 else if (unlikely(ret)) {
1720 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1721 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1722 return;
1723 }
1724
1725 if (unlikely(ds->ds_rxstat.rs_more)) {
1726 ATH5K_WARN(sc, "unsupported jumbo\n");
1727 goto next;
1728 }
1729
1730 stat = ds->ds_rxstat.rs_status;
1731 if (unlikely(stat)) {
1732 if (stat & AR5K_RXERR_PHY)
1733 goto next;
1734 if (stat & AR5K_RXERR_DECRYPT) {
1735 /*
1736 * Decrypt error. If the error occurred
1737 * because there was no hardware key, then
1738 * let the frame through so the upper layers
1739 * can process it. This is necessary for 5210
1740 * parts which have no way to setup a ``clear''
1741 * key cache entry.
1742 *
1743 * XXX do key cache faulting
1744 */
1745 if (ds->ds_rxstat.rs_keyix ==
1746 AR5K_RXKEYIX_INVALID &&
1747 !(stat & AR5K_RXERR_CRC))
1748 goto accept;
1749 }
1750 if (stat & AR5K_RXERR_MIC) {
1751 rxs.flag |= RX_FLAG_MMIC_ERROR;
1752 goto accept;
1753 }
1754
1755 /* let crypto-error packets fall through in MNTR */
1756 if ((stat & ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1757 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1758 goto next;
1759 }
1760accept:
1761 len = ds->ds_rxstat.rs_datalen;
1762 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, len,
1763 PCI_DMA_FROMDEVICE);
1764 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1765 PCI_DMA_FROMDEVICE);
1766 bf->skb = NULL;
1767
1768 skb_put(skb, len);
1769
1770 /*
1771 * the hardware adds a padding to 4 byte boundaries between
1772 * the header and the payload data if the header length is
1773 * not multiples of 4 - remove it
1774 */
1775 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1776 if (hdrlen & 3) {
1777 pad = hdrlen % 4;
1778 memmove(skb->data + pad, skb->data, hdrlen);
1779 skb_pull(skb, pad);
1780 }
1781
c0e1899b
BR		 1782 /*
1783 * always extend the mac timestamp, since this information is
1784 * also needed for proper IBSS merging.
1785 *
1786 * XXX: it might be too late to do it here, since rs_tstamp is
1787 * 15bit only. that means TSF extension has to be done within
1788 * 32768usec (about 32ms). it might be necessary to move this to
1789 * the interrupt handler, like it is done in madwifi.
1790 */
1791 rxs.mactime = ath5k_extend_tsf(sc->ah, ds->ds_rxstat.rs_tstamp);
1792 rxs.flag |= RX_FLAG_TSFT;
1793
fa1c114f
JS		 1794 rxs.freq = sc->curchan->freq;
1795 rxs.channel = sc->curchan->chan;
1796 rxs.phymode = sc->curmode;
1797
1798 /*
1799 * signal quality:
1800 * the names here are misleading and the usage of these
1801 * values by iwconfig makes it even worse
1802 */
1803 /* noise floor in dBm, from the last noise calibration */
1804 rxs.noise = sc->ah->ah_noise_floor;
1805 /* signal level in dBm */
1806 rxs.ssi = rxs.noise + ds->ds_rxstat.rs_rssi;
1807 /*
1808 * "signal" is actually displayed as Link Quality by iwconfig
1809 * we provide a percentage based on rssi (assuming max rssi 64)
1810 */
1811 rxs.signal = ds->ds_rxstat.rs_rssi * 100 / 64;
1812
1813 rxs.antenna = ds->ds_rxstat.rs_antenna;
1814 rxs.rate = ds->ds_rxstat.rs_rate;
1815 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
1816
1817 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1818
036cd1ec
BR		 1819 /* check beacons in IBSS mode */
1820 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1821 ath5k_check_ibss_hw_merge(sc, skb);
1822
fa1c114f
JS		 1823 __ieee80211_rx(sc->hw, skb, &rxs);
1824 sc->led_rxrate = ds->ds_rxstat.rs_rate;
1825 ath5k_led_event(sc, ATH_LED_RX);
1826next:
1827 list_move_tail(&bf->list, &sc->rxbuf);
1828 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1829 spin_unlock(&sc->rxbuflock);
1830}
1831
1832
1833
1834
1835/*************\
1836* TX Handling *
1837\*************/
1838
1839static void
1840ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1841{
1842 struct ieee80211_tx_status txs = {};
1843 struct ath5k_buf *bf, *bf0;
1844 struct ath5k_desc *ds;
1845 struct sk_buff *skb;
1846 int ret;
1847
1848 spin_lock(&txq->lock);
1849 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1850 ds = bf->desc;
1851
1852 /* TODO only one segment */
1853 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1854 sc->desc_len, PCI_DMA_FROMDEVICE);
1855 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds);
1856 if (unlikely(ret == -EINPROGRESS))
1857 break;
1858 else if (unlikely(ret)) {
1859 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1860 ret, txq->qnum);
1861 break;
1862 }
1863
1864 skb = bf->skb;
1865 bf->skb = NULL;
1866 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1867 PCI_DMA_TODEVICE);
1868
1869 txs.control = bf->ctl;
1870 txs.retry_count = ds->ds_txstat.ts_shortretry +
1871 ds->ds_txstat.ts_longretry / 6;
1872 if (unlikely(ds->ds_txstat.ts_status)) {
1873 sc->ll_stats.dot11ACKFailureCount++;
1874 if (ds->ds_txstat.ts_status & AR5K_TXERR_XRETRY)
1875 txs.excessive_retries = 1;
1876 else if (ds->ds_txstat.ts_status & AR5K_TXERR_FILT)
1877 txs.flags |= IEEE80211_TX_STATUS_TX_FILTERED;
1878 } else {
1879 txs.flags |= IEEE80211_TX_STATUS_ACK;
1880 txs.ack_signal = ds->ds_txstat.ts_rssi;
1881 }
1882
1883 ieee80211_tx_status(sc->hw, skb, &txs);
1884 sc->tx_stats.data[txq->qnum].count++;
1885
1886 spin_lock(&sc->txbuflock);
1887 sc->tx_stats.data[txq->qnum].len--;
1888 list_move_tail(&bf->list, &sc->txbuf);
1889 sc->txbuf_len++;
1890 spin_unlock(&sc->txbuflock);
1891 }
1892 if (likely(list_empty(&txq->q)))
1893 txq->link = NULL;
1894 spin_unlock(&txq->lock);
1895 if (sc->txbuf_len > ATH_TXBUF / 5)
1896 ieee80211_wake_queues(sc->hw);
1897}
1898
1899static void
1900ath5k_tasklet_tx(unsigned long data)
1901{
1902 struct ath5k_softc *sc = (void *)data;
1903
1904 ath5k_tx_processq(sc, sc->txq);
1905
1906 ath5k_led_event(sc, ATH_LED_TX);
1907}
1908
1909
1910
1911
1912/*****************\
1913* Beacon handling *
1914\*****************/
1915
1916/*
1917 * Setup the beacon frame for transmit.
1918 */
1919static int
1920ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1921 struct ieee80211_tx_control *ctl)
1922{
1923 struct sk_buff *skb = bf->skb;
1924 struct ath5k_hw *ah = sc->ah;
1925 struct ath5k_desc *ds;
1926 int ret, antenna = 0;
1927 u32 flags;
1928
1929 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1930 PCI_DMA_TODEVICE);
1931 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1932 "skbaddr %llx\n", skb, skb->data, skb->len,
1933 (unsigned long long)bf->skbaddr);
1934 if (pci_dma_mapping_error(bf->skbaddr)) {
1935 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1936 return -EIO;
1937 }
1938
1939 ds = bf->desc;
1940
1941 flags = AR5K_TXDESC_NOACK;
1942 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1943 ds->ds_link = bf->daddr; /* self-linked */
1944 flags |= AR5K_TXDESC_VEOL;
1945 /*
1946 * Let hardware handle antenna switching if txantenna is not set
1947 */
1948 } else {
1949 ds->ds_link = 0;
1950 /*
1951 * Switch antenna every 4 beacons if txantenna is not set
1952 * XXX assumes two antennas
1953 */
1954 if (antenna == 0)
1955 antenna = sc->bsent & 4 ? 2 : 1;
1956 }
1957
1958 ds->ds_data = bf->skbaddr;
281c56dd 1959 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f
JS		 1960 ieee80211_get_hdrlen_from_skb(skb),
1961 AR5K_PKT_TYPE_BEACON, (ctl->power_level * 2), ctl->tx_rate, 1,
1962 AR5K_TXKEYIX_INVALID, antenna, flags, 0, 0);
1963 if (ret)
1964 goto err_unmap;
1965
1966 return 0;
1967err_unmap:
1968 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1969 return ret;
1970}
1971
1972/*
1973 * Transmit a beacon frame at SWBA. Dynamic updates to the
1974 * frame contents are done as needed and the slot time is
1975 * also adjusted based on current state.
1976 *
1977 * this is usually called from interrupt context (ath5k_intr())
1978 * but also from ath5k_beacon_config() in IBSS mode which in turn
1979 * can be called from a tasklet and user context
1980 */
1981static void
1982ath5k_beacon_send(struct ath5k_softc *sc)
1983{
1984 struct ath5k_buf *bf = sc->bbuf;
1985 struct ath5k_hw *ah = sc->ah;
1986
be9b7259 1987 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f
JS		 1988
1989 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1990 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1991 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1992 return;
1993 }
1994 /*
1995 * Check if the previous beacon has gone out. If
1996 * not don't don't try to post another, skip this
1997 * period and wait for the next. Missed beacons
1998 * indicate a problem and should not occur. If we
1999 * miss too many consecutive beacons reset the device.
2000 */
2001 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2002 sc->bmisscount++;
be9b7259 2003 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2004 "missed %u consecutive beacons\n", sc->bmisscount);
2005 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2006 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2007 "stuck beacon time (%u missed)\n",
2008 sc->bmisscount);
2009 tasklet_schedule(&sc->restq);
2010 }
2011 return;
2012 }
2013 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2014 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2015 "resume beacon xmit after %u misses\n",
2016 sc->bmisscount);
2017 sc->bmisscount = 0;
2018 }
2019
2020 /*
2021 * Stop any current dma and put the new frame on the queue.
2022 * This should never fail since we check above that no frames
2023 * are still pending on the queue.
2024 */
2025 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2026 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2027 /* NB: hw still stops DMA, so proceed */
2028 }
2029 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2030 PCI_DMA_TODEVICE);
2031
2032 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2033 ath5k_hw_tx_start(ah, sc->bhalq);
be9b7259 2034 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2035 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2036
2037 sc->bsent++;
2038}
2039
2040
9804b98d
BR		 2041/**
2042 * ath5k_beacon_update_timers - update beacon timers
2043 *
2044 * @sc: struct ath5k_softc pointer we are operating on
2045 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2046 * beacon timer update based on the current HW TSF.
2047 *
2048 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2049 * of a received beacon or the current local hardware TSF and write it to the
2050 * beacon timer registers.
2051 *
2052 * This is called in a variety of situations, e.g. when a beacon is received,
2053 * when a HW merge has been detected, but also when an new IBSS is created or
2054 * when we otherwise know we have to update the timers, but we keep it in this
2055 * function to have it all together in one place.
2056 */
fa1c114f 2057static void
9804b98d 2058ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2059{
2060 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2061 u32 nexttbtt, intval, hw_tu, bc_tu;
2062 u64 hw_tsf;
fa1c114f
JS		 2063
2064 intval = sc->bintval & AR5K_BEACON_PERIOD;
2065 if (WARN_ON(!intval))
2066 return;
2067
9804b98d
BR		 2068 /* beacon TSF converted to TU */
2069 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2070
9804b98d
BR		 2071 /* current TSF converted to TU */
2072 hw_tsf = ath5k_hw_get_tsf64(ah);
2073 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2074
9804b98d
BR		 2075#define FUDGE 3
2076 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2077 if (bc_tsf == -1) {
2078 /*
2079 * no beacons received, called internally.
2080 * just need to refresh timers based on HW TSF.
2081 */
2082 nexttbtt = roundup(hw_tu + FUDGE, intval);
2083 } else if (bc_tsf == 0) {
2084 /*
2085 * no beacon received, probably called by ath5k_reset_tsf().
2086 * reset TSF to start with 0.
2087 */
2088 nexttbtt = intval;
2089 intval |= AR5K_BEACON_RESET_TSF;
2090 } else if (bc_tsf > hw_tsf) {
2091 /*
2092 * beacon received, SW merge happend but HW TSF not yet updated.
2093 * not possible to reconfigure timers yet, but next time we
2094 * receive a beacon with the same BSSID, the hardware will
2095 * automatically update the TSF and then we need to reconfigure
2096 * the timers.
2097 */
2098 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2099 "need to wait for HW TSF sync\n");
2100 return;
2101 } else {
2102 /*
2103 * most important case for beacon synchronization between STA.
2104 *
2105 * beacon received and HW TSF has been already updated by HW.
2106 * update next TBTT based on the TSF of the beacon, but make
2107 * sure it is ahead of our local TSF timer.
2108 */
2109 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2110 }
2111#undef FUDGE
fa1c114f 2112
036cd1ec
BR		 2113 sc->nexttbtt = nexttbtt;
2114
fa1c114f 2115 intval |= AR5K_BEACON_ENA;
fa1c114f 2116 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2117
2118 /*
2119 * debugging output last in order to preserve the time critical aspect
2120 * of this function
2121 */
2122 if (bc_tsf == -1)
2123 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2124 "reconfigured timers based on HW TSF\n");
2125 else if (bc_tsf == 0)
2126 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2127 "reset HW TSF and timers\n");
2128 else
2129 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2130 "updated timers based on beacon TSF\n");
2131
2132 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2133 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2134 bc_tsf, hw_tsf, bc_tu, hw_tu, nexttbtt);
2135 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2136 intval & AR5K_BEACON_PERIOD,
2137 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2138 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2139}
2140
2141
036cd1ec
BR		 2142/**
2143 * ath5k_beacon_config - Configure the beacon queues and interrupts
2144 *
2145 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2146 *
2147 * When operating in station mode we want to receive a BMISS interrupt when we
2148 * stop seeing beacons from the AP we've associated with so we can look for
2149 * another AP to associate with.
2150 *
036cd1ec
BR		 2151 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2152 * interrupts to detect HW merges only.
2153 *
2154 * AP mode is missing.
fa1c114f
JS		 2155 */
2156static void
2157ath5k_beacon_config(struct ath5k_softc *sc)
2158{
2159 struct ath5k_hw *ah = sc->ah;
2160
2161 ath5k_hw_set_intr(ah, 0);
2162 sc->bmisscount = 0;
2163
2164 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2165 sc->imask |= AR5K_INT_BMISS;
2166 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2167 /*
036cd1ec
BR		 2168 * In IBSS mode we use a self-linked tx descriptor and let the
2169 * hardware send the beacons automatically. We have to load it
fa1c114f 2170 * only once here.
036cd1ec
BR		 2171 * We use the SWBA interrupt only to keep track of the beacon
2172 * timers in order to detect HW merges (automatic TSF updates).
fa1c114f
JS		 2173 */
2174 ath5k_beaconq_config(sc);
fa1c114f 2175
036cd1ec
BR		 2176 sc->imask |= AR5K_INT_SWBA;
2177
2178 if (ath5k_hw_hasveol(ah))
fa1c114f
JS		 2179 ath5k_beacon_send(sc);
2180 }
2181 /* TODO else AP */
2182
2183 ath5k_hw_set_intr(ah, sc->imask);
2184}
2185
2186
2187/********************\
2188* Interrupt handling *
2189\********************/
2190
2191static int
2192ath5k_init(struct ath5k_softc *sc)
2193{
2194 int ret;
2195
2196 mutex_lock(&sc->lock);
2197
2198 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2199
2200 /*
2201 * Stop anything previously setup. This is safe
2202 * no matter this is the first time through or not.
2203 */
2204 ath5k_stop_locked(sc);
2205
2206 /*
2207 * The basic interface to setting the hardware in a good
2208 * state is ``reset''. On return the hardware is known to
2209 * be powered up and with interrupts disabled. This must
2210 * be followed by initialization of the appropriate bits
2211 * and then setup of the interrupt mask.
2212 */
2213 sc->curchan = sc->hw->conf.chan;
2214 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2215 if (ret) {
2216 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2217 goto done;
2218 }
2219 /*
2220 * This is needed only to setup initial state
2221 * but it's best done after a reset.
2222 */
2223 ath5k_hw_set_txpower_limit(sc->ah, 0);
2224
2225 /*
2226 * Setup the hardware after reset: the key cache
2227 * is filled as needed and the receive engine is
2228 * set going. Frame transmit is handled entirely
2229 * in the frame output path; there's nothing to do
2230 * here except setup the interrupt mask.
2231 */
2232 ret = ath5k_rx_start(sc);
2233 if (ret)
2234 goto done;
2235
2236 /*
2237 * Enable interrupts.
2238 */
2239 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2240 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2241
2242 ath5k_hw_set_intr(sc->ah, sc->imask);
2243 /* Set ack to be sent at low bit-rates */
2244 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2245
2246 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2247 msecs_to_jiffies(ath5k_calinterval * 1000)));
2248
2249 ret = 0;
2250done:
2251 mutex_unlock(&sc->lock);
2252 return ret;
2253}
2254
2255static int
2256ath5k_stop_locked(struct ath5k_softc *sc)
2257{
2258 struct ath5k_hw *ah = sc->ah;
2259
2260 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2261 test_bit(ATH_STAT_INVALID, sc->status));
2262
2263 /*
2264 * Shutdown the hardware and driver:
2265 * stop output from above
2266 * disable interrupts
2267 * turn off timers
2268 * turn off the radio
2269 * clear transmit machinery
2270 * clear receive machinery
2271 * drain and release tx queues
2272 * reclaim beacon resources
2273 * power down hardware
2274 *
2275 * Note that some of this work is not possible if the
2276 * hardware is gone (invalid).
2277 */
2278 ieee80211_stop_queues(sc->hw);
2279
2280 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2281 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2282 del_timer_sync(&sc->led_tim);
2283 ath5k_hw_set_gpio(ah, sc->led_pin, !sc->led_on);
2284 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2285 }
2286 ath5k_hw_set_intr(ah, 0);
2287 }
2288 ath5k_txq_cleanup(sc);
2289 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2290 ath5k_rx_stop(sc);
2291 ath5k_hw_phy_disable(ah);
2292 } else
2293 sc->rxlink = NULL;
2294
2295 return 0;
2296}
2297
2298/*
2299 * Stop the device, grabbing the top-level lock to protect
2300 * against concurrent entry through ath5k_init (which can happen
2301 * if another thread does a system call and the thread doing the
2302 * stop is preempted).
2303 */
2304static int
2305ath5k_stop_hw(struct ath5k_softc *sc)
2306{
2307 int ret;
2308
2309 mutex_lock(&sc->lock);
2310 ret = ath5k_stop_locked(sc);
2311 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2312 /*
2313 * Set the chip in full sleep mode. Note that we are
2314 * careful to do this only when bringing the interface
2315 * completely to a stop. When the chip is in this state
2316 * it must be carefully woken up or references to
2317 * registers in the PCI clock domain may freeze the bus
2318 * (and system). This varies by chip and is mostly an
2319 * issue with newer parts that go to sleep more quickly.
2320 */
2321 if (sc->ah->ah_mac_srev >= 0x78) {
2322 /*
2323 * XXX
2324 * don't put newer MAC revisions > 7.8 to sleep because
2325 * of the above mentioned problems
2326 */
2327 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2328 "not putting device to sleep\n");
2329 } else {
2330 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2331 "putting device to full sleep\n");
2332 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2333 }
2334 }
2335 ath5k_txbuf_free(sc, sc->bbuf);
2336 mutex_unlock(&sc->lock);
2337
2338 del_timer_sync(&sc->calib_tim);
2339
2340 return ret;
2341}
2342
2343static irqreturn_t
2344ath5k_intr(int irq, void *dev_id)
2345{
2346 struct ath5k_softc *sc = dev_id;
2347 struct ath5k_hw *ah = sc->ah;
2348 enum ath5k_int status;
2349 unsigned int counter = 1000;
2350
2351 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2352 !ath5k_hw_is_intr_pending(ah)))
2353 return IRQ_NONE;
2354
2355 do {
2356 /*
2357 * Figure out the reason(s) for the interrupt. Note
2358 * that get_isr returns a pseudo-ISR that may include
2359 * bits we haven't explicitly enabled so we mask the
2360 * value to insure we only process bits we requested.
2361 */
2362 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2363 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2364 status, sc->imask);
2365 status &= sc->imask; /* discard unasked for bits */
2366 if (unlikely(status & AR5K_INT_FATAL)) {
2367 /*
2368 * Fatal errors are unrecoverable.
2369 * Typically these are caused by DMA errors.
2370 */
2371 tasklet_schedule(&sc->restq);
2372 } else if (unlikely(status & AR5K_INT_RXORN)) {
2373 tasklet_schedule(&sc->restq);
2374 } else {
2375 if (status & AR5K_INT_SWBA) {
2376 /*
2377 * Software beacon alert--time to send a beacon.
2378 * Handle beacon transmission directly; deferring
2379 * this is too slow to meet timing constraints
2380 * under load.
036cd1ec
BR		 2381 *
2382 * In IBSS mode we use this interrupt just to
2383 * keep track of the next TBTT (target beacon
2384 * transmission time) in order to detect hardware
2385 * merges (TSF updates).
fa1c114f 2386 */
036cd1ec
BR		 2387 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2388 /* XXX: only if VEOL suppported */
2389 u64 tsf = ath5k_hw_get_tsf64(ah);
2390 sc->nexttbtt += sc->bintval;
2391 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2392 "SWBA nexttbtt: %x hw_tu: %x "
2393 "TSF: %llx\n",
2394 sc->nexttbtt,
2395 TSF_TO_TU(tsf), tsf);
2396 } else {
2397 ath5k_beacon_send(sc);
2398 }
fa1c114f
JS		 2399 }
2400 if (status & AR5K_INT_RXEOL) {
2401 /*
2402 * NB: the hardware should re-read the link when
2403 * RXE bit is written, but it doesn't work at
2404 * least on older hardware revs.
2405 */
2406 sc->rxlink = NULL;
2407 }
2408 if (status & AR5K_INT_TXURN) {
2409 /* bump tx trigger level */
2410 ath5k_hw_update_tx_triglevel(ah, true);
2411 }
2412 if (status & AR5K_INT_RX)
2413 tasklet_schedule(&sc->rxtq);
2414 if (status & AR5K_INT_TX)
2415 tasklet_schedule(&sc->txtq);
2416 if (status & AR5K_INT_BMISS) {
2417 }
2418 if (status & AR5K_INT_MIB) {
2419 /* TODO */
2420 }
2421 }
2422 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2423
2424 if (unlikely(!counter))
2425 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2426
2427 return IRQ_HANDLED;
2428}
2429
2430static void
2431ath5k_tasklet_reset(unsigned long data)
2432{
2433 struct ath5k_softc *sc = (void *)data;
2434
2435 ath5k_reset(sc->hw);
2436}
2437
2438/*
2439 * Periodically recalibrate the PHY to account
2440 * for temperature/environment changes.
2441 */
2442static void
2443ath5k_calibrate(unsigned long data)
2444{
2445 struct ath5k_softc *sc = (void *)data;
2446 struct ath5k_hw *ah = sc->ah;
2447
2448 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2449 sc->curchan->chan, sc->curchan->val);
2450
2451 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2452 /*
2453 * Rfgain is out of bounds, reset the chip
2454 * to load new gain values.
2455 */
2456 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2457 ath5k_reset(sc->hw);
2458 }
2459 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2460 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2461 sc->curchan->chan);
2462
2463 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2464 msecs_to_jiffies(ath5k_calinterval * 1000)));
2465}
2466
2467
2468
2469/***************\
2470* LED functions *
2471\***************/
2472
2473static void
2474ath5k_led_off(unsigned long data)
2475{
2476 struct ath5k_softc *sc = (void *)data;
2477
2478 if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
2479 __clear_bit(ATH_STAT_LEDBLINKING, sc->status);
2480 else {
2481 __set_bit(ATH_STAT_LEDENDBLINK, sc->status);
2482 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2483 mod_timer(&sc->led_tim, jiffies + sc->led_off);
2484 }
2485}
2486
2487/*
2488 * Blink the LED according to the specified on/off times.
2489 */
2490static void
2491ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
2492 unsigned int off)
2493{
2494 ATH5K_DBG(sc, ATH5K_DEBUG_LED, "on %u off %u\n", on, off);
2495 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2496 __set_bit(ATH_STAT_LEDBLINKING, sc->status);
2497 __clear_bit(ATH_STAT_LEDENDBLINK, sc->status);
2498 sc->led_off = off;
2499 mod_timer(&sc->led_tim, jiffies + on);
2500}
2501
2502static void
2503ath5k_led_event(struct ath5k_softc *sc, int event)
2504{
2505 if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
2506 return;
2507 if (unlikely(test_bit(ATH_STAT_LEDBLINKING, sc->status)))
2508 return; /* don't interrupt active blink */
2509 switch (event) {
2510 case ATH_LED_TX:
2511 ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
2512 sc->hwmap[sc->led_txrate].ledoff);
2513 break;
2514 case ATH_LED_RX:
2515 ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
2516 sc->hwmap[sc->led_rxrate].ledoff);
2517 break;
2518 }
2519}
2520
2521
2522
2523
2524/********************\
2525* Mac80211 functions *
2526\********************/
2527
2528static int
2529ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2530 struct ieee80211_tx_control *ctl)
2531{
2532 struct ath5k_softc *sc = hw->priv;
2533 struct ath5k_buf *bf;
2534 unsigned long flags;
2535 int hdrlen;
2536 int pad;
2537
2538 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2539
2540 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2541 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2542
2543 /*
2544 * the hardware expects the header padded to 4 byte boundaries
2545 * if this is not the case we add the padding after the header
2546 */
2547 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2548 if (hdrlen & 3) {
2549 pad = hdrlen % 4;
2550 if (skb_headroom(skb) < pad) {
2551 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2552 " headroom to pad %d\n", hdrlen, pad);
2553 return -1;
2554 }
2555 skb_push(skb, pad);
2556 memmove(skb->data, skb->data+pad, hdrlen);
2557 }
2558
2559 sc->led_txrate = ctl->tx_rate;
2560
2561 spin_lock_irqsave(&sc->txbuflock, flags);
2562 if (list_empty(&sc->txbuf)) {
2563 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2564 spin_unlock_irqrestore(&sc->txbuflock, flags);
2565 ieee80211_stop_queue(hw, ctl->queue);
2566 return -1;
2567 }
2568 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2569 list_del(&bf->list);
2570 sc->txbuf_len--;
2571 if (list_empty(&sc->txbuf))
2572 ieee80211_stop_queues(hw);
2573 spin_unlock_irqrestore(&sc->txbuflock, flags);
2574
2575 bf->skb = skb;
2576
2577 if (ath5k_txbuf_setup(sc, bf, ctl)) {
2578 bf->skb = NULL;
2579 spin_lock_irqsave(&sc->txbuflock, flags);
2580 list_add_tail(&bf->list, &sc->txbuf);
2581 sc->txbuf_len++;
2582 spin_unlock_irqrestore(&sc->txbuflock, flags);
2583 dev_kfree_skb_any(skb);
2584 return 0;
2585 }
2586
2587 return 0;
2588}
2589
2590static int
2591ath5k_reset(struct ieee80211_hw *hw)
2592{
2593 struct ath5k_softc *sc = hw->priv;
2594 struct ath5k_hw *ah = sc->ah;
2595 int ret;
2596
2597 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2598 /*
2599 * Convert to a hw channel description with the flags
2600 * constrained to reflect the current operating mode.
2601 */
2602 sc->curchan = hw->conf.chan;
2603
2604 ath5k_hw_set_intr(ah, 0);
2605 ath5k_txq_cleanup(sc);
2606 ath5k_rx_stop(sc);
2607
2608 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2609 if (unlikely(ret)) {
2610 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2611 goto err;
2612 }
2613 ath5k_hw_set_txpower_limit(sc->ah, 0);
2614
2615 ret = ath5k_rx_start(sc);
2616 if (unlikely(ret)) {
2617 ATH5K_ERR(sc, "can't start recv logic\n");
2618 goto err;
2619 }
2620 /*
2621 * We may be doing a reset in response to an ioctl
2622 * that changes the channel so update any state that
2623 * might change as a result.
2624 *
2625 * XXX needed?
2626 */
2627/* ath5k_chan_change(sc, c); */
2628 ath5k_beacon_config(sc);
2629 /* intrs are started by ath5k_beacon_config */
2630
2631 ieee80211_wake_queues(hw);
2632
2633 return 0;
2634err:
2635 return ret;
2636}
2637
2638static int ath5k_start(struct ieee80211_hw *hw)
2639{
2640 return ath5k_init(hw->priv);
2641}
2642
2643static void ath5k_stop(struct ieee80211_hw *hw)
2644{
2645 ath5k_stop_hw(hw->priv);
2646}
2647
2648static int ath5k_add_interface(struct ieee80211_hw *hw,
2649 struct ieee80211_if_init_conf *conf)
2650{
2651 struct ath5k_softc *sc = hw->priv;
2652 int ret;
2653
2654 mutex_lock(&sc->lock);
32bfd35d 2655 if (sc->vif) {
fa1c114f
JS		 2656 ret = 0;
2657 goto end;
2658 }
2659
32bfd35d 2660 sc->vif = conf->vif;
fa1c114f
JS		 2661
2662 switch (conf->type) {
2663 case IEEE80211_IF_TYPE_STA:
2664 case IEEE80211_IF_TYPE_IBSS:
2665 case IEEE80211_IF_TYPE_MNTR:
2666 sc->opmode = conf->type;
2667 break;
2668 default:
2669 ret = -EOPNOTSUPP;
2670 goto end;
2671 }
2672 ret = 0;
2673end:
2674 mutex_unlock(&sc->lock);
2675 return ret;
2676}
2677
2678static void
2679ath5k_remove_interface(struct ieee80211_hw *hw,
2680 struct ieee80211_if_init_conf *conf)
2681{
2682 struct ath5k_softc *sc = hw->priv;
2683
2684 mutex_lock(&sc->lock);
32bfd35d 2685 if (sc->vif != conf->vif)
fa1c114f
JS		 2686 goto end;
2687
32bfd35d 2688 sc->vif = NULL;
fa1c114f
JS		 2689end:
2690 mutex_unlock(&sc->lock);
2691}
2692
2693static int
2694ath5k_config(struct ieee80211_hw *hw,
2695 struct ieee80211_conf *conf)
2696{
2697 struct ath5k_softc *sc = hw->priv;
2698
e535c1ac 2699 sc->bintval = conf->beacon_int;
fa1c114f
JS		 2700 ath5k_setcurmode(sc, conf->phymode);
2701
2702 return ath5k_chan_set(sc, conf->chan);
2703}
2704
2705static int
32bfd35d 2706ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2707 struct ieee80211_if_conf *conf)
2708{
2709 struct ath5k_softc *sc = hw->priv;
2710 struct ath5k_hw *ah = sc->ah;
2711 int ret;
2712
2713 /* Set to a reasonable value. Note that this will
2714 * be set to mac80211's value at ath5k_config(). */
e535c1ac 2715 sc->bintval = 1000;
fa1c114f 2716 mutex_lock(&sc->lock);
32bfd35d 2717 if (sc->vif != vif) {
fa1c114f
JS		 2718 ret = -EIO;
2719 goto unlock;
2720 }
2721 if (conf->bssid) {
2722 /* Cache for later use during resets */
2723 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2724 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2725 * a clean way of letting us retrieve this yet. */
2726 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2727 }
2728 mutex_unlock(&sc->lock);
2729
2730 return ath5k_reset(hw);
2731unlock:
2732 mutex_unlock(&sc->lock);
2733 return ret;
2734}
2735
2736#define SUPPORTED_FIF_FLAGS \
2737 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2738 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2739 FIF_BCN_PRBRESP_PROMISC
2740/*
2741 * o always accept unicast, broadcast, and multicast traffic
2742 * o multicast traffic for all BSSIDs will be enabled if mac80211
2743 * says it should be
2744 * o maintain current state of phy ofdm or phy cck error reception.
2745 * If the hardware detects any of these type of errors then
2746 * ath5k_hw_get_rx_filter() will pass to us the respective
2747 * hardware filters to be able to receive these type of frames.
2748 * o probe request frames are accepted only when operating in
2749 * hostap, adhoc, or monitor modes
2750 * o enable promiscuous mode according to the interface state
2751 * o accept beacons:
2752 * - when operating in adhoc mode so the 802.11 layer creates
2753 * node table entries for peers,
2754 * - when operating in station mode for collecting rssi data when
2755 * the station is otherwise quiet, or
2756 * - when scanning
2757 */
2758static void ath5k_configure_filter(struct ieee80211_hw *hw,
2759 unsigned int changed_flags,
2760 unsigned int *new_flags,
2761 int mc_count, struct dev_mc_list *mclist)
2762{
2763 struct ath5k_softc *sc = hw->priv;
2764 struct ath5k_hw *ah = sc->ah;
2765 u32 mfilt[2], val, rfilt;
2766 u8 pos;
2767 int i;
2768
2769 mfilt[0] = 0;
2770 mfilt[1] = 0;
2771
2772 /* Only deal with supported flags */
2773 changed_flags &= SUPPORTED_FIF_FLAGS;
2774 *new_flags &= SUPPORTED_FIF_FLAGS;
2775
2776 /* If HW detects any phy or radar errors, leave those filters on.
2777 * Also, always enable Unicast, Broadcasts and Multicast
2778 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2779 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2780 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2781 AR5K_RX_FILTER_MCAST);
2782
2783 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2784 if (*new_flags & FIF_PROMISC_IN_BSS) {
2785 rfilt |= AR5K_RX_FILTER_PROM;
2786 __set_bit(ATH_STAT_PROMISC, sc->status);
2787 }
2788 else
2789 __clear_bit(ATH_STAT_PROMISC, sc->status);
2790 }
2791
2792 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2793 if (*new_flags & FIF_ALLMULTI) {
2794 mfilt[0] = ~0;
2795 mfilt[1] = ~0;
2796 } else {
2797 for (i = 0; i < mc_count; i++) {
2798 if (!mclist)
2799 break;
2800 /* calculate XOR of eight 6-bit values */
2801 val = LE_READ_4(mclist->dmi_addr + 0);
2802 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2803 val = LE_READ_4(mclist->dmi_addr + 3);
2804 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2805 pos &= 0x3f;
2806 mfilt[pos / 32] |= (1 << (pos % 32));
2807 /* XXX: we might be able to just do this instead,
2808 * but not sure, needs testing, if we do use this we'd
2809 * neet to inform below to not reset the mcast */
2810 /* ath5k_hw_set_mcast_filterindex(ah,
2811 * mclist->dmi_addr[5]); */
2812 mclist = mclist->next;
2813 }
2814 }
2815
2816 /* This is the best we can do */
2817 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2818 rfilt |= AR5K_RX_FILTER_PHYERR;
2819
2820 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2821 * and probes for any BSSID, this needs testing */
2822 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2823 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2824
2825 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2826 * set we should only pass on control frames for this
2827 * station. This needs testing. I believe right now this
2828 * enables *all* control frames, which is OK.. but
2829 * but we should see if we can improve on granularity */
2830 if (*new_flags & FIF_CONTROL)
2831 rfilt |= AR5K_RX_FILTER_CONTROL;
2832
2833 /* Additional settings per mode -- this is per ath5k */
2834
2835 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2836
2837 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2838 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2839 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2840 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2841 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2842 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2843 test_bit(ATH_STAT_PROMISC, sc->status))
2844 rfilt |= AR5K_RX_FILTER_PROM;
2845 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2846 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2847 rfilt |= AR5K_RX_FILTER_BEACON;
2848 }
2849
2850 /* Set filters */
2851 ath5k_hw_set_rx_filter(ah,rfilt);
2852
2853 /* Set multicast bits */
2854 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2855 /* Set the cached hw filter flags, this will alter actually
2856 * be set in HW */
2857 sc->filter_flags = rfilt;
2858}
2859
2860static int
2861ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2862 const u8 *local_addr, const u8 *addr,
2863 struct ieee80211_key_conf *key)
2864{
2865 struct ath5k_softc *sc = hw->priv;
2866 int ret = 0;
2867
2868 switch(key->alg) {
2869 case ALG_WEP:
2870 break;
2871 case ALG_TKIP:
2872 case ALG_CCMP:
2873 return -EOPNOTSUPP;
2874 default:
2875 WARN_ON(1);
2876 return -EINVAL;
2877 }
2878
2879 mutex_lock(&sc->lock);
2880
2881 switch (cmd) {
2882 case SET_KEY:
2883 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2884 if (ret) {
2885 ATH5K_ERR(sc, "can't set the key\n");
2886 goto unlock;
2887 }
2888 __set_bit(key->keyidx, sc->keymap);
2889 key->hw_key_idx = key->keyidx;
2890 break;
2891 case DISABLE_KEY:
2892 ath5k_hw_reset_key(sc->ah, key->keyidx);
2893 __clear_bit(key->keyidx, sc->keymap);
2894 break;
2895 default:
2896 ret = -EINVAL;
2897 goto unlock;
2898 }
2899
2900unlock:
2901 mutex_unlock(&sc->lock);
2902 return ret;
2903}
2904
2905static int
2906ath5k_get_stats(struct ieee80211_hw *hw,
2907 struct ieee80211_low_level_stats *stats)
2908{
2909 struct ath5k_softc *sc = hw->priv;
2910
2911 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2912
2913 return 0;
2914}
2915
2916static int
2917ath5k_get_tx_stats(struct ieee80211_hw *hw,
2918 struct ieee80211_tx_queue_stats *stats)
2919{
2920 struct ath5k_softc *sc = hw->priv;
2921
2922 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2923
2924 return 0;
2925}
2926
2927static u64
2928ath5k_get_tsf(struct ieee80211_hw *hw)
2929{
2930 struct ath5k_softc *sc = hw->priv;
2931
2932 return ath5k_hw_get_tsf64(sc->ah);
2933}
2934
2935static void
2936ath5k_reset_tsf(struct ieee80211_hw *hw)
2937{
2938 struct ath5k_softc *sc = hw->priv;
2939
9804b98d
BR		 2940 /*
2941 * in IBSS mode we need to update the beacon timers too.
2942 * this will also reset the TSF if we call it with 0
2943 */
2944 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
2945 ath5k_beacon_update_timers(sc, 0);
2946 else
2947 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 2948}
2949
2950static int
2951ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2952 struct ieee80211_tx_control *ctl)
2953{
2954 struct ath5k_softc *sc = hw->priv;
2955 int ret;
2956
2957 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
2958
2959 mutex_lock(&sc->lock);
2960
2961 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
2962 ret = -EIO;
2963 goto end;
2964 }
2965
2966 ath5k_txbuf_free(sc, sc->bbuf);
2967 sc->bbuf->skb = skb;
2968 ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
2969 if (ret)
2970 sc->bbuf->skb = NULL;
2971 else
2972 ath5k_beacon_config(sc);
2973
2974end:
2975 mutex_unlock(&sc->lock);
2976 return ret;
2977}
2978
Clone of davem's net-next-2.6 tree