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ath5k: enable hardware encryption for WEP
[net-next-2.6.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f
JS		 66
67
68/******************\
69* Internal defines *
70\******************/
71
72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 78MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 79
80
81/* Known PCI ids */
82static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 101 { 0 }
102};
103MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105/* Known SREVs */
106static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143};
144
63266a65
BR		 145static struct ieee80211_rate ath5k_rates[] = {
146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185};
186
fa1c114f
JS		 187/*
188 * Prototypes - PCI stack related functions
189 */
190static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193#ifdef CONFIG_PM
194static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196static int ath5k_pci_resume(struct pci_dev *pdev);
197#else
198#define ath5k_pci_suspend NULL
199#define ath5k_pci_resume NULL
200#endif /* CONFIG_PM */
201
04a9e451 202static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 203 .name = "ath5k_pci",
204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209};
210
211
212
213/*
214 * Prototypes - MAC 802.11 stack related functions
215 */
e039fa4a 216static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 217static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 219static int ath5k_start(struct ieee80211_hw *hw);
220static void ath5k_stop(struct ieee80211_hw *hw);
221static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
e8975581 225static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 226static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
fa1c114f
JS		 228 struct ieee80211_if_conf *conf);
229static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
235 const u8 *local_addr, const u8 *addr,
236 struct ieee80211_key_conf *key);
237static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
242static void ath5k_reset_tsf(struct ieee80211_hw *hw);
da966bca 243static int ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb);
fa1c114f
JS		 244
245static struct ieee80211_ops ath5k_hw_ops = {
246 .tx = ath5k_tx,
247 .start = ath5k_start,
248 .stop = ath5k_stop,
249 .add_interface = ath5k_add_interface,
250 .remove_interface = ath5k_remove_interface,
251 .config = ath5k_config,
252 .config_interface = ath5k_config_interface,
253 .configure_filter = ath5k_configure_filter,
254 .set_key = ath5k_set_key,
255 .get_stats = ath5k_get_stats,
256 .conf_tx = NULL,
257 .get_tx_stats = ath5k_get_tx_stats,
258 .get_tsf = ath5k_get_tsf,
259 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 260};
261
262/*
263 * Prototypes - Internal functions
264 */
265/* Attach detach */
266static int ath5k_attach(struct pci_dev *pdev,
267 struct ieee80211_hw *hw);
268static void ath5k_detach(struct pci_dev *pdev,
269 struct ieee80211_hw *hw);
270/* Channel/mode setup */
271static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 272static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
273 struct ieee80211_channel *channels,
274 unsigned int mode,
275 unsigned int max);
63266a65 276static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 277static int ath5k_chan_set(struct ath5k_softc *sc,
278 struct ieee80211_channel *chan);
279static void ath5k_setcurmode(struct ath5k_softc *sc,
280 unsigned int mode);
281static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 282
fa1c114f
JS		 283/* Descriptor setup */
284static int ath5k_desc_alloc(struct ath5k_softc *sc,
285 struct pci_dev *pdev);
286static void ath5k_desc_free(struct ath5k_softc *sc,
287 struct pci_dev *pdev);
288/* Buffers setup */
289static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
290 struct ath5k_buf *bf);
291static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 292 struct ath5k_buf *bf);
fa1c114f
JS		 293static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
294 struct ath5k_buf *bf)
295{
296 BUG_ON(!bf);
297 if (!bf->skb)
298 return;
299 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
300 PCI_DMA_TODEVICE);
00482973 301 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 302 bf->skb = NULL;
303}
304
305/* Queues setup */
306static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
307 int qtype, int subtype);
308static int ath5k_beaconq_setup(struct ath5k_hw *ah);
309static int ath5k_beaconq_config(struct ath5k_softc *sc);
310static void ath5k_txq_drainq(struct ath5k_softc *sc,
311 struct ath5k_txq *txq);
312static void ath5k_txq_cleanup(struct ath5k_softc *sc);
313static void ath5k_txq_release(struct ath5k_softc *sc);
314/* Rx handling */
315static int ath5k_rx_start(struct ath5k_softc *sc);
316static void ath5k_rx_stop(struct ath5k_softc *sc);
317static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
318 struct ath5k_desc *ds,
b47f407b
BR		 319 struct sk_buff *skb,
320 struct ath5k_rx_status *rs);
fa1c114f
JS		 321static void ath5k_tasklet_rx(unsigned long data);
322/* Tx handling */
323static void ath5k_tx_processq(struct ath5k_softc *sc,
324 struct ath5k_txq *txq);
325static void ath5k_tasklet_tx(unsigned long data);
326/* Beacon handling */
327static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 328 struct ath5k_buf *bf);
fa1c114f
JS		 329static void ath5k_beacon_send(struct ath5k_softc *sc);
330static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 331static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 332
333static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
334{
335 u64 tsf = ath5k_hw_get_tsf64(ah);
336
337 if ((tsf & 0x7fff) < rstamp)
338 tsf -= 0x8000;
339
340 return (tsf & ~0x7fff) | rstamp;
341}
342
343/* Interrupt handling */
8bdd5b9c 344static int ath5k_init(struct ath5k_softc *sc, bool is_resume);
fa1c114f 345static int ath5k_stop_locked(struct ath5k_softc *sc);
8bdd5b9c 346static int ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
fa1c114f
JS		 347static irqreturn_t ath5k_intr(int irq, void *dev_id);
348static void ath5k_tasklet_reset(unsigned long data);
349
350static void ath5k_calibrate(unsigned long data);
351/* LED functions */
3a078876
BC		 352static int ath5k_init_leds(struct ath5k_softc *sc);
353static void ath5k_led_enable(struct ath5k_softc *sc);
354static void ath5k_led_off(struct ath5k_softc *sc);
355static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 356
357/*
358 * Module init/exit functions
359 */
360static int __init
361init_ath5k_pci(void)
362{
363 int ret;
364
365 ath5k_debug_init();
366
04a9e451 367 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 368 if (ret) {
369 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
370 return ret;
371 }
372
373 return 0;
374}
375
376static void __exit
377exit_ath5k_pci(void)
378{
04a9e451 379 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 380
381 ath5k_debug_finish();
382}
383
384module_init(init_ath5k_pci);
385module_exit(exit_ath5k_pci);
386
387
388/********************\
389* PCI Initialization *
390\********************/
391
392static const char *
393ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
394{
395 const char *name = "xxxxx";
396 unsigned int i;
397
398 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
399 if (srev_names[i].sr_type != type)
400 continue;
75d0edb8
NK		 401
402 if ((val & 0xf0) == srev_names[i].sr_val)
403 name = srev_names[i].sr_name;
404
405 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 406 name = srev_names[i].sr_name;
407 break;
408 }
409 }
410
411 return name;
412}
413
414static int __devinit
415ath5k_pci_probe(struct pci_dev *pdev,
416 const struct pci_device_id *id)
417{
418 void __iomem *mem;
419 struct ath5k_softc *sc;
420 struct ieee80211_hw *hw;
421 int ret;
422 u8 csz;
423
424 ret = pci_enable_device(pdev);
425 if (ret) {
426 dev_err(&pdev->dev, "can't enable device\n");
427 goto err;
428 }
429
430 /* XXX 32-bit addressing only */
431 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
432 if (ret) {
433 dev_err(&pdev->dev, "32-bit DMA not available\n");
434 goto err_dis;
435 }
436
437 /*
438 * Cache line size is used to size and align various
439 * structures used to communicate with the hardware.
440 */
441 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
442 if (csz == 0) {
443 /*
444 * Linux 2.4.18 (at least) writes the cache line size
445 * register as a 16-bit wide register which is wrong.
446 * We must have this setup properly for rx buffer
447 * DMA to work so force a reasonable value here if it
448 * comes up zero.
449 */
450 csz = L1_CACHE_BYTES / sizeof(u32);
451 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
452 }
453 /*
454 * The default setting of latency timer yields poor results,
455 * set it to the value used by other systems. It may be worth
456 * tweaking this setting more.
457 */
458 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
459
460 /* Enable bus mastering */
461 pci_set_master(pdev);
462
463 /*
464 * Disable the RETRY_TIMEOUT register (0x41) to keep
465 * PCI Tx retries from interfering with C3 CPU state.
466 */
467 pci_write_config_byte(pdev, 0x41, 0);
468
469 ret = pci_request_region(pdev, 0, "ath5k");
470 if (ret) {
471 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
472 goto err_dis;
473 }
474
475 mem = pci_iomap(pdev, 0, 0);
476 if (!mem) {
477 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
478 ret = -EIO;
479 goto err_reg;
480 }
481
482 /*
483 * Allocate hw (mac80211 main struct)
484 * and hw->priv (driver private data)
485 */
486 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
487 if (hw == NULL) {
488 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
489 ret = -ENOMEM;
490 goto err_map;
491 }
492
493 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
494
495 /* Initialize driver private data */
496 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 497 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
498 IEEE80211_HW_SIGNAL_DBM |
499 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 500
501 hw->wiphy->interface_modes =
502 BIT(NL80211_IFTYPE_STATION) |
503 BIT(NL80211_IFTYPE_ADHOC) |
504 BIT(NL80211_IFTYPE_MESH_POINT);
505
fa1c114f
JS		 506 hw->extra_tx_headroom = 2;
507 hw->channel_change_time = 5000;
fa1c114f
JS		 508 sc = hw->priv;
509 sc->hw = hw;
510 sc->pdev = pdev;
511
512 ath5k_debug_init_device(sc);
513
514 /*
515 * Mark the device as detached to avoid processing
516 * interrupts until setup is complete.
517 */
518 __set_bit(ATH_STAT_INVALID, sc->status);
519
520 sc->iobase = mem; /* So we can unmap it on detach */
521 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 522 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 523 mutex_init(&sc->lock);
524 spin_lock_init(&sc->rxbuflock);
525 spin_lock_init(&sc->txbuflock);
00482973 526 spin_lock_init(&sc->block);
fa1c114f
JS		 527
528 /* Set private data */
529 pci_set_drvdata(pdev, hw);
530
fa1c114f
JS		 531 /* Setup interrupt handler */
532 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
533 if (ret) {
534 ATH5K_ERR(sc, "request_irq failed\n");
535 goto err_free;
536 }
537
538 /* Initialize device */
539 sc->ah = ath5k_hw_attach(sc, id->driver_data);
540 if (IS_ERR(sc->ah)) {
541 ret = PTR_ERR(sc->ah);
542 goto err_irq;
543 }
544
2f7fe870
FF		 545 /* set up multi-rate retry capabilities */
546 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 547 hw->max_rates = 4;
548 hw->max_rate_tries = 11;
2f7fe870
FF		 549 }
550
fa1c114f
JS		 551 /* Finish private driver data initialization */
552 ret = ath5k_attach(pdev, hw);
553 if (ret)
554 goto err_ah;
555
556 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 557 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 558 sc->ah->ah_mac_srev,
559 sc->ah->ah_phy_revision);
560
400ec45a 561 if (!sc->ah->ah_single_chip) {
fa1c114f 562 /* Single chip radio (!RF5111) */
400ec45a
LR		 563 if (sc->ah->ah_radio_5ghz_revision &&
564 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 565 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 566 if (!test_bit(AR5K_MODE_11A,
567 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 568 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 569 ath5k_chip_name(AR5K_VERSION_RAD,
570 sc->ah->ah_radio_5ghz_revision),
571 sc->ah->ah_radio_5ghz_revision);
572 /* No 2GHz support (5110 and some
573 * 5Ghz only cards) -> report 5Ghz radio */
574 } else if (!test_bit(AR5K_MODE_11B,
575 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 576 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 577 ath5k_chip_name(AR5K_VERSION_RAD,
578 sc->ah->ah_radio_5ghz_revision),
579 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 580 /* Multiband radio */
581 } else {
582 ATH5K_INFO(sc, "RF%s multiband radio found"
583 " (0x%x)\n",
400ec45a
LR		 584 ath5k_chip_name(AR5K_VERSION_RAD,
585 sc->ah->ah_radio_5ghz_revision),
586 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 587 }
588 }
400ec45a
LR		 589 /* Multi chip radio (RF5111 - RF2111) ->
590 * report both 2GHz/5GHz radios */
591 else if (sc->ah->ah_radio_5ghz_revision &&
592 sc->ah->ah_radio_2ghz_revision){
fa1c114f 593 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 594 ath5k_chip_name(AR5K_VERSION_RAD,
595 sc->ah->ah_radio_5ghz_revision),
596 sc->ah->ah_radio_5ghz_revision);
fa1c114f 597 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 598 ath5k_chip_name(AR5K_VERSION_RAD,
599 sc->ah->ah_radio_2ghz_revision),
600 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 601 }
602 }
603
604
605 /* ready to process interrupts */
606 __clear_bit(ATH_STAT_INVALID, sc->status);
607
608 return 0;
609err_ah:
610 ath5k_hw_detach(sc->ah);
611err_irq:
612 free_irq(pdev->irq, sc);
613err_free:
fa1c114f
JS		 614 ieee80211_free_hw(hw);
615err_map:
616 pci_iounmap(pdev, mem);
617err_reg:
618 pci_release_region(pdev, 0);
619err_dis:
620 pci_disable_device(pdev);
621err:
622 return ret;
623}
624
625static void __devexit
626ath5k_pci_remove(struct pci_dev *pdev)
627{
628 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
629 struct ath5k_softc *sc = hw->priv;
630
631 ath5k_debug_finish_device(sc);
632 ath5k_detach(pdev, hw);
633 ath5k_hw_detach(sc->ah);
634 free_irq(pdev->irq, sc);
fa1c114f
JS		 635 pci_iounmap(pdev, sc->iobase);
636 pci_release_region(pdev, 0);
637 pci_disable_device(pdev);
638 ieee80211_free_hw(hw);
639}
640
641#ifdef CONFIG_PM
642static int
643ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
644{
645 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
646 struct ath5k_softc *sc = hw->priv;
647
3a078876 648 ath5k_led_off(sc);
fa1c114f 649
8bdd5b9c 650 ath5k_stop_hw(sc, true);
3e4242b9
JS		 651
652 free_irq(pdev->irq, sc);
fa1c114f
JS		 653 pci_save_state(pdev);
654 pci_disable_device(pdev);
655 pci_set_power_state(pdev, PCI_D3hot);
656
657 return 0;
658}
659
660static int
661ath5k_pci_resume(struct pci_dev *pdev)
662{
663 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
664 struct ath5k_softc *sc = hw->priv;
bc1b32d6 665 int err;
fa1c114f 666
3e4242b9 667 pci_restore_state(pdev);
fa1c114f
JS		 668
669 err = pci_enable_device(pdev);
670 if (err)
671 return err;
672
fa1c114f
JS		 673 /*
674 * Suspend/Resume resets the PCI configuration space, so we have to
675 * re-disable the RETRY_TIMEOUT register (0x41) to keep
676 * PCI Tx retries from interfering with C3 CPU state
677 */
678 pci_write_config_byte(pdev, 0x41, 0);
679
3e4242b9
JS		 680 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
681 if (err) {
682 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 683 goto err_no_irq;
3e4242b9
JS		 684 }
685
8bdd5b9c 686 err = ath5k_init(sc, true);
3e4242b9
JS		 687 if (err)
688 goto err_irq;
3a078876 689 ath5k_led_enable(sc);
fa1c114f
JS		 690
691 return 0;
3e4242b9
JS		 692err_irq:
693 free_irq(pdev->irq, sc);
37465c8a 694err_no_irq:
3e4242b9
JS		 695 pci_disable_device(pdev);
696 return err;
fa1c114f
JS		 697}
698#endif /* CONFIG_PM */
699
700
fa1c114f
JS		 701/***********************\
702* Driver Initialization *
703\***********************/
704
705static int
706ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
707{
708 struct ath5k_softc *sc = hw->priv;
709 struct ath5k_hw *ah = sc->ah;
710 u8 mac[ETH_ALEN];
fa1c114f
JS		 711 int ret;
712
713 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
714
715 /*
716 * Check if the MAC has multi-rate retry support.
717 * We do this by trying to setup a fake extended
718 * descriptor. MAC's that don't have support will
719 * return false w/o doing anything. MAC's that do
720 * support it will return true w/o doing anything.
721 */
c6e387a2 722 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 723 if (ret < 0)
724 goto err;
725 if (ret > 0)
fa1c114f
JS		 726 __set_bit(ATH_STAT_MRRETRY, sc->status);
727
fa1c114f
JS		 728 /*
729 * Collect the channel list. The 802.11 layer
730 * is resposible for filtering this list based
731 * on settings like the phy mode and regulatory
732 * domain restrictions.
733 */
63266a65 734 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 735 if (ret) {
736 ATH5K_ERR(sc, "can't get channels\n");
737 goto err;
738 }
739
740 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 741 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
742 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 743 else
d8ee398d 744 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 745
746 /*
747 * Allocate tx+rx descriptors and populate the lists.
748 */
749 ret = ath5k_desc_alloc(sc, pdev);
750 if (ret) {
751 ATH5K_ERR(sc, "can't allocate descriptors\n");
752 goto err;
753 }
754
755 /*
756 * Allocate hardware transmit queues: one queue for
757 * beacon frames and one data queue for each QoS
758 * priority. Note that hw functions handle reseting
759 * these queues at the needed time.
760 */
761 ret = ath5k_beaconq_setup(ah);
762 if (ret < 0) {
763 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
764 goto err_desc;
765 }
766 sc->bhalq = ret;
767
768 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
769 if (IS_ERR(sc->txq)) {
770 ATH5K_ERR(sc, "can't setup xmit queue\n");
771 ret = PTR_ERR(sc->txq);
772 goto err_bhal;
773 }
774
775 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
776 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
777 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
778 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 779
780 ath5k_hw_get_lladdr(ah, mac);
781 SET_IEEE80211_PERM_ADDR(hw, mac);
782 /* All MAC address bits matter for ACKs */
783 memset(sc->bssidmask, 0xff, ETH_ALEN);
784 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
785
786 ret = ieee80211_register_hw(hw);
787 if (ret) {
788 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
789 goto err_queues;
790 }
791
3a078876
BC		 792 ath5k_init_leds(sc);
793
fa1c114f
JS		 794 return 0;
795err_queues:
796 ath5k_txq_release(sc);
797err_bhal:
798 ath5k_hw_release_tx_queue(ah, sc->bhalq);
799err_desc:
800 ath5k_desc_free(sc, pdev);
801err:
802 return ret;
803}
804
805static void
806ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
807{
808 struct ath5k_softc *sc = hw->priv;
809
810 /*
811 * NB: the order of these is important:
812 * o call the 802.11 layer before detaching ath5k_hw to
813 * insure callbacks into the driver to delete global
814 * key cache entries can be handled
815 * o reclaim the tx queue data structures after calling
816 * the 802.11 layer as we'll get called back to reclaim
817 * node state and potentially want to use them
818 * o to cleanup the tx queues the hal is called, so detach
819 * it last
820 * XXX: ??? detach ath5k_hw ???
821 * Other than that, it's straightforward...
822 */
823 ieee80211_unregister_hw(hw);
824 ath5k_desc_free(sc, pdev);
825 ath5k_txq_release(sc);
826 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 827 ath5k_unregister_leds(sc);
fa1c114f
JS		 828
829 /*
830 * NB: can't reclaim these until after ieee80211_ifdetach
831 * returns because we'll get called back to reclaim node
832 * state and potentially want to use them.
833 */
834}
835
836
837
838
839/********************\
840* Channel/mode setup *
841\********************/
842
843/*
844 * Convert IEEE channel number to MHz frequency.
845 */
846static inline short
847ath5k_ieee2mhz(short chan)
848{
849 if (chan <= 14 || chan >= 27)
850 return ieee80211chan2mhz(chan);
851 else
852 return 2212 + chan * 20;
853}
854
fa1c114f
JS		 855static unsigned int
856ath5k_copy_channels(struct ath5k_hw *ah,
857 struct ieee80211_channel *channels,
858 unsigned int mode,
859 unsigned int max)
860{
d8ee398d 861 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 862
863 if (!test_bit(mode, ah->ah_modes))
864 return 0;
865
fa1c114f 866 switch (mode) {
d8ee398d
LR		 867 case AR5K_MODE_11A:
868 case AR5K_MODE_11A_TURBO:
fa1c114f 869 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 870 size = 220 ;
fa1c114f
JS		 871 chfreq = CHANNEL_5GHZ;
872 break;
d8ee398d
LR		 873 case AR5K_MODE_11B:
874 case AR5K_MODE_11G:
875 case AR5K_MODE_11G_TURBO:
876 size = 26;
fa1c114f
JS		 877 chfreq = CHANNEL_2GHZ;
878 break;
879 default:
880 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
881 return 0;
882 }
883
884 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 885 ch = i + 1 ;
886 freq = ath5k_ieee2mhz(ch);
fa1c114f 887
d8ee398d
LR		 888 /* Check if channel is supported by the chipset */
889 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 890 continue;
891
d8ee398d
LR		 892 /* Write channel info and increment counter */
893 channels[count].center_freq = freq;
a3f4b914
LR		 894 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
895 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 896 switch (mode) {
897 case AR5K_MODE_11A:
898 case AR5K_MODE_11G:
899 channels[count].hw_value = chfreq | CHANNEL_OFDM;
900 break;
901 case AR5K_MODE_11A_TURBO:
902 case AR5K_MODE_11G_TURBO:
903 channels[count].hw_value = chfreq |
904 CHANNEL_OFDM | CHANNEL_TURBO;
905 break;
906 case AR5K_MODE_11B:
d8ee398d
LR		 907 channels[count].hw_value = CHANNEL_B;
908 }
fa1c114f 909
fa1c114f
JS		 910 count++;
911 max--;
912 }
913
914 return count;
915}
916
63266a65
BR		 917static void
918ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
919{
920 u8 i;
921
922 for (i = 0; i < AR5K_MAX_RATES; i++)
923 sc->rate_idx[b->band][i] = -1;
924
925 for (i = 0; i < b->n_bitrates; i++) {
926 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
927 if (b->bitrates[i].hw_value_short)
928 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
929 }
930}
931
d8ee398d 932static int
63266a65 933ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 934{
935 struct ath5k_softc *sc = hw->priv;
d8ee398d 936 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 937 struct ieee80211_supported_band *sband;
938 int max_c, count_c = 0;
939 int i;
fa1c114f 940
d8ee398d 941 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 942 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 943
944 /* 2GHz band */
63266a65
BR		 945 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
946 sband->band = IEEE80211_BAND_2GHZ;
947 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 948
63266a65
BR		 949 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
950 /* G mode */
951 memcpy(sband->bitrates, &ath5k_rates[0],
952 sizeof(struct ieee80211_rate) * 12);
953 sband->n_bitrates = 12;
fa1c114f 954
d8ee398d 955 sband->channels = sc->channels;
d8ee398d 956 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 957 AR5K_MODE_11G, max_c);
fa1c114f 958
63266a65 959 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 960 count_c = sband->n_channels;
63266a65
BR		 961 max_c -= count_c;
962 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
963 /* B mode */
964 memcpy(sband->bitrates, &ath5k_rates[0],
965 sizeof(struct ieee80211_rate) * 4);
966 sband->n_bitrates = 4;
967
968 /* 5211 only supports B rates and uses 4bit rate codes
969 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
970 * fix them up here:
971 */
972 if (ah->ah_version == AR5K_AR5211) {
973 for (i = 0; i < 4; i++) {
974 sband->bitrates[i].hw_value =
975 sband->bitrates[i].hw_value & 0xF;
976 sband->bitrates[i].hw_value_short =
977 sband->bitrates[i].hw_value_short & 0xF;
978 }
979 }
fa1c114f 980
63266a65
BR		 981 sband->channels = sc->channels;
982 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
983 AR5K_MODE_11B, max_c);
d8ee398d 984
63266a65
BR		 985 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
986 count_c = sband->n_channels;
d8ee398d 987 max_c -= count_c;
fa1c114f 988 }
63266a65 989 ath5k_setup_rate_idx(sc, sband);
fa1c114f 990
63266a65 991 /* 5GHz band, A mode */
400ec45a 992 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 993 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
994 sband->band = IEEE80211_BAND_5GHZ;
995 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 996
63266a65
BR		 997 memcpy(sband->bitrates, &ath5k_rates[4],
998 sizeof(struct ieee80211_rate) * 8);
999 sband->n_bitrates = 8;
fa1c114f 1000
63266a65 1001 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1002 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1003 AR5K_MODE_11A, max_c);
1004
d8ee398d
LR		 1005 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1006 }
63266a65 1007 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1008
b446197c 1009 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1010
1011 return 0;
fa1c114f
JS		 1012}
1013
1014/*
1015 * Set/change channels. If the channel is really being changed,
1016 * it's done by reseting the chip. To accomplish this we must
1017 * first cleanup any pending DMA, then restart stuff after a la
1018 * ath5k_init.
1019 */
1020static int
1021ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1022{
d8ee398d
LR		 1023 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1024 sc->curchan->center_freq, chan->center_freq);
1025
1026 if (chan->center_freq != sc->curchan->center_freq ||
1027 chan->hw_value != sc->curchan->hw_value) {
1028
1029 sc->curchan = chan;
1030 sc->curband = &sc->sbands[chan->band];
fa1c114f 1031
fa1c114f
JS		 1032 /*
1033 * To switch channels clear any pending DMA operations;
1034 * wait long enough for the RX fifo to drain, reset the
1035 * hardware at the new frequency, and then re-enable
1036 * the relevant bits of the h/w.
1037 */
d7dc1003 1038 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1039 }
1040
1041 return 0;
1042}
1043
1044static void
1045ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1046{
fa1c114f 1047 sc->curmode = mode;
d8ee398d 1048
400ec45a 1049 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1050 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1051 } else {
1052 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1053 }
fa1c114f
JS		 1054}
1055
1056static void
1057ath5k_mode_setup(struct ath5k_softc *sc)
1058{
1059 struct ath5k_hw *ah = sc->ah;
1060 u32 rfilt;
1061
1062 /* configure rx filter */
1063 rfilt = sc->filter_flags;
1064 ath5k_hw_set_rx_filter(ah, rfilt);
1065
1066 if (ath5k_hw_hasbssidmask(ah))
1067 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1068
1069 /* configure operational mode */
1070 ath5k_hw_set_opmode(ah);
1071
1072 ath5k_hw_set_mcast_filter(ah, 0, 0);
1073 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1074}
1075
d8ee398d 1076static inline int
63266a65
BR		 1077ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1078{
1079 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1080 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1081}
1082
fa1c114f
JS		 1083/***************\
1084* Buffers setup *
1085\***************/
1086
1087static int
1088ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1089{
1090 struct ath5k_hw *ah = sc->ah;
1091 struct sk_buff *skb = bf->skb;
1092 struct ath5k_desc *ds;
1093
1094 if (likely(skb == NULL)) {
1095 unsigned int off;
1096
1097 /*
1098 * Allocate buffer with headroom_needed space for the
1099 * fake physical layer header at the start.
1100 */
1101 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1102 if (unlikely(skb == NULL)) {
1103 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1104 sc->rxbufsize + sc->cachelsz - 1);
1105 return -ENOMEM;
1106 }
1107 /*
1108 * Cache-line-align. This is important (for the
1109 * 5210 at least) as not doing so causes bogus data
1110 * in rx'd frames.
1111 */
1112 off = ((unsigned long)skb->data) % sc->cachelsz;
1113 if (off != 0)
1114 skb_reserve(skb, sc->cachelsz - off);
1115
1116 bf->skb = skb;
1117 bf->skbaddr = pci_map_single(sc->pdev,
1118 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1119 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1120 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1121 dev_kfree_skb(skb);
1122 bf->skb = NULL;
1123 return -ENOMEM;
1124 }
1125 }
1126
1127 /*
1128 * Setup descriptors. For receive we always terminate
1129 * the descriptor list with a self-linked entry so we'll
1130 * not get overrun under high load (as can happen with a
1131 * 5212 when ANI processing enables PHY error frames).
1132 *
1133 * To insure the last descriptor is self-linked we create
1134 * each descriptor as self-linked and add it to the end. As
1135 * each additional descriptor is added the previous self-linked
1136 * entry is ``fixed'' naturally. This should be safe even
1137 * if DMA is happening. When processing RX interrupts we
1138 * never remove/process the last, self-linked, entry on the
1139 * descriptor list. This insures the hardware always has
1140 * someplace to write a new frame.
1141 */
1142 ds = bf->desc;
1143 ds->ds_link = bf->daddr; /* link to self */
1144 ds->ds_data = bf->skbaddr;
c6e387a2 1145 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1146 skb_tailroom(skb), /* buffer size */
1147 0);
1148
1149 if (sc->rxlink != NULL)
1150 *sc->rxlink = bf->daddr;
1151 sc->rxlink = &ds->ds_link;
1152 return 0;
1153}
1154
1155static int
e039fa4a 1156ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1157{
1158 struct ath5k_hw *ah = sc->ah;
1159 struct ath5k_txq *txq = sc->txq;
1160 struct ath5k_desc *ds = bf->desc;
1161 struct sk_buff *skb = bf->skb;
a888d52d 1162 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1163 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1164 struct ieee80211_rate *rate;
1165 unsigned int mrr_rate[3], mrr_tries[3];
1166 int i, ret;
fa1c114f
JS		 1167
1168 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1169
fa1c114f
JS		 1170 /* XXX endianness */
1171 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1172 PCI_DMA_TODEVICE);
1173
e039fa4a 1174 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1175 flags |= AR5K_TXDESC_NOACK;
1176
281c56dd 1177 pktlen = skb->len;
fa1c114f 1178
d0f09804 1179 if (info->control.hw_key) {
e039fa4a 1180 keyidx = info->control.hw_key->hw_key_idx;
76708dee 1181 pktlen += info->control.hw_key->icv_len;
fa1c114f 1182 }
fa1c114f
JS		 1183 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1184 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1185 (sc->power_level * 2),
e039fa4a 1186 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
e6a9854b 1187 info->control.rates[0].count, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1188 if (ret)
1189 goto err_unmap;
1190
2f7fe870
FF		 1191 memset(mrr_rate, 0, sizeof(mrr_rate));
1192 memset(mrr_tries, 0, sizeof(mrr_tries));
1193 for (i = 0; i < 3; i++) {
1194 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1195 if (!rate)
1196 break;
1197
1198 mrr_rate[i] = rate->hw_value;
e6a9854b 1199 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1200 }
1201
1202 ah->ah_setup_mrr_tx_desc(ah, ds,
1203 mrr_rate[0], mrr_tries[0],
1204 mrr_rate[1], mrr_tries[1],
1205 mrr_rate[2], mrr_tries[2]);
1206
fa1c114f
JS		 1207 ds->ds_link = 0;
1208 ds->ds_data = bf->skbaddr;
1209
1210 spin_lock_bh(&txq->lock);
1211 list_add_tail(&bf->list, &txq->q);
57ffc589 1212 sc->tx_stats[txq->qnum].len++;
fa1c114f 1213 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1214 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1215 else /* no, so only link it */
1216 *txq->link = bf->daddr;
1217
1218 txq->link = &ds->ds_link;
c6e387a2 1219 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1220 mmiowb();
fa1c114f
JS		 1221 spin_unlock_bh(&txq->lock);
1222
1223 return 0;
1224err_unmap:
1225 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1226 return ret;
1227}
1228
1229/*******************\
1230* Descriptors setup *
1231\*******************/
1232
1233static int
1234ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1235{
1236 struct ath5k_desc *ds;
1237 struct ath5k_buf *bf;
1238 dma_addr_t da;
1239 unsigned int i;
1240 int ret;
1241
1242 /* allocate descriptors */
1243 sc->desc_len = sizeof(struct ath5k_desc) *
1244 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1245 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1246 if (sc->desc == NULL) {
1247 ATH5K_ERR(sc, "can't allocate descriptors\n");
1248 ret = -ENOMEM;
1249 goto err;
1250 }
1251 ds = sc->desc;
1252 da = sc->desc_daddr;
1253 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1254 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1255
1256 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1257 sizeof(struct ath5k_buf), GFP_KERNEL);
1258 if (bf == NULL) {
1259 ATH5K_ERR(sc, "can't allocate bufptr\n");
1260 ret = -ENOMEM;
1261 goto err_free;
1262 }
1263 sc->bufptr = bf;
1264
1265 INIT_LIST_HEAD(&sc->rxbuf);
1266 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1267 bf->desc = ds;
1268 bf->daddr = da;
1269 list_add_tail(&bf->list, &sc->rxbuf);
1270 }
1271
1272 INIT_LIST_HEAD(&sc->txbuf);
1273 sc->txbuf_len = ATH_TXBUF;
1274 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1275 da += sizeof(*ds)) {
1276 bf->desc = ds;
1277 bf->daddr = da;
1278 list_add_tail(&bf->list, &sc->txbuf);
1279 }
1280
1281 /* beacon buffer */
1282 bf->desc = ds;
1283 bf->daddr = da;
1284 sc->bbuf = bf;
1285
1286 return 0;
1287err_free:
1288 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1289err:
1290 sc->desc = NULL;
1291 return ret;
1292}
1293
1294static void
1295ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1296{
1297 struct ath5k_buf *bf;
1298
1299 ath5k_txbuf_free(sc, sc->bbuf);
1300 list_for_each_entry(bf, &sc->txbuf, list)
1301 ath5k_txbuf_free(sc, bf);
1302 list_for_each_entry(bf, &sc->rxbuf, list)
1303 ath5k_txbuf_free(sc, bf);
1304
1305 /* Free memory associated with all descriptors */
1306 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1307
1308 kfree(sc->bufptr);
1309 sc->bufptr = NULL;
1310}
1311
1312
1313
1314
1315
1316/**************\
1317* Queues setup *
1318\**************/
1319
1320static struct ath5k_txq *
1321ath5k_txq_setup(struct ath5k_softc *sc,
1322 int qtype, int subtype)
1323{
1324 struct ath5k_hw *ah = sc->ah;
1325 struct ath5k_txq *txq;
1326 struct ath5k_txq_info qi = {
1327 .tqi_subtype = subtype,
1328 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1329 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1330 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1331 };
1332 int qnum;
1333
1334 /*
1335 * Enable interrupts only for EOL and DESC conditions.
1336 * We mark tx descriptors to receive a DESC interrupt
1337 * when a tx queue gets deep; otherwise waiting for the
1338 * EOL to reap descriptors. Note that this is done to
1339 * reduce interrupt load and this only defers reaping
1340 * descriptors, never transmitting frames. Aside from
1341 * reducing interrupts this also permits more concurrency.
1342 * The only potential downside is if the tx queue backs
1343 * up in which case the top half of the kernel may backup
1344 * due to a lack of tx descriptors.
1345 */
1346 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1347 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1348 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1349 if (qnum < 0) {
1350 /*
1351 * NB: don't print a message, this happens
1352 * normally on parts with too few tx queues
1353 */
1354 return ERR_PTR(qnum);
1355 }
1356 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1357 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1358 qnum, ARRAY_SIZE(sc->txqs));
1359 ath5k_hw_release_tx_queue(ah, qnum);
1360 return ERR_PTR(-EINVAL);
1361 }
1362 txq = &sc->txqs[qnum];
1363 if (!txq->setup) {
1364 txq->qnum = qnum;
1365 txq->link = NULL;
1366 INIT_LIST_HEAD(&txq->q);
1367 spin_lock_init(&txq->lock);
1368 txq->setup = true;
1369 }
1370 return &sc->txqs[qnum];
1371}
1372
1373static int
1374ath5k_beaconq_setup(struct ath5k_hw *ah)
1375{
1376 struct ath5k_txq_info qi = {
1377 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1378 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1379 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1380 /* NB: for dynamic turbo, don't enable any other interrupts */
1381 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1382 };
1383
1384 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1385}
1386
1387static int
1388ath5k_beaconq_config(struct ath5k_softc *sc)
1389{
1390 struct ath5k_hw *ah = sc->ah;
1391 struct ath5k_txq_info qi;
1392 int ret;
1393
1394 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1395 if (ret)
1396 return ret;
05c914fe
JB		 1397 if (sc->opmode == NL80211_IFTYPE_AP ||
1398 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1399 /*
1400 * Always burst out beacon and CAB traffic
1401 * (aifs = cwmin = cwmax = 0)
1402 */
1403 qi.tqi_aifs = 0;
1404 qi.tqi_cw_min = 0;
1405 qi.tqi_cw_max = 0;
05c914fe 1406 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1407 /*
1408 * Adhoc mode; backoff between 0 and (2 * cw_min).
1409 */
1410 qi.tqi_aifs = 0;
1411 qi.tqi_cw_min = 0;
1412 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1413 }
1414
6d91e1d8
BR		 1415 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1416 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1417 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1418
c6e387a2 1419 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1420 if (ret) {
1421 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1422 "hardware queue!\n", __func__);
1423 return ret;
1424 }
1425
1426 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1427}
1428
1429static void
1430ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1431{
1432 struct ath5k_buf *bf, *bf0;
1433
1434 /*
1435 * NB: this assumes output has been stopped and
1436 * we do not need to block ath5k_tx_tasklet
1437 */
1438 spin_lock_bh(&txq->lock);
1439 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1440 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1441
1442 ath5k_txbuf_free(sc, bf);
1443
1444 spin_lock_bh(&sc->txbuflock);
57ffc589 1445 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1446 list_move_tail(&bf->list, &sc->txbuf);
1447 sc->txbuf_len++;
1448 spin_unlock_bh(&sc->txbuflock);
1449 }
1450 txq->link = NULL;
1451 spin_unlock_bh(&txq->lock);
1452}
1453
1454/*
1455 * Drain the transmit queues and reclaim resources.
1456 */
1457static void
1458ath5k_txq_cleanup(struct ath5k_softc *sc)
1459{
1460 struct ath5k_hw *ah = sc->ah;
1461 unsigned int i;
1462
1463 /* XXX return value */
1464 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1465 /* don't touch the hardware if marked invalid */
1466 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1467 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1468 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1469 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1470 if (sc->txqs[i].setup) {
1471 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1472 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1473 "link %p\n",
1474 sc->txqs[i].qnum,
c6e387a2 1475 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1476 sc->txqs[i].qnum),
1477 sc->txqs[i].link);
1478 }
1479 }
36d6825b 1480 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1481
1482 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1483 if (sc->txqs[i].setup)
1484 ath5k_txq_drainq(sc, &sc->txqs[i]);
1485}
1486
1487static void
1488ath5k_txq_release(struct ath5k_softc *sc)
1489{
1490 struct ath5k_txq *txq = sc->txqs;
1491 unsigned int i;
1492
1493 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1494 if (txq->setup) {
1495 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1496 txq->setup = false;
1497 }
1498}
1499
1500
1501
1502
1503/*************\
1504* RX Handling *
1505\*************/
1506
1507/*
1508 * Enable the receive h/w following a reset.
1509 */
1510static int
1511ath5k_rx_start(struct ath5k_softc *sc)
1512{
1513 struct ath5k_hw *ah = sc->ah;
1514 struct ath5k_buf *bf;
1515 int ret;
1516
1517 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1518
1519 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1520 sc->cachelsz, sc->rxbufsize);
1521
1522 sc->rxlink = NULL;
1523
1524 spin_lock_bh(&sc->rxbuflock);
1525 list_for_each_entry(bf, &sc->rxbuf, list) {
1526 ret = ath5k_rxbuf_setup(sc, bf);
1527 if (ret != 0) {
1528 spin_unlock_bh(&sc->rxbuflock);
1529 goto err;
1530 }
1531 }
1532 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1533 spin_unlock_bh(&sc->rxbuflock);
1534
c6e387a2
NK		 1535 ath5k_hw_set_rxdp(ah, bf->daddr);
1536 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1537 ath5k_mode_setup(sc); /* set filters, etc. */
1538 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1539
1540 return 0;
1541err:
1542 return ret;
1543}
1544
1545/*
1546 * Disable the receive h/w in preparation for a reset.
1547 */
1548static void
1549ath5k_rx_stop(struct ath5k_softc *sc)
1550{
1551 struct ath5k_hw *ah = sc->ah;
1552
c6e387a2 1553 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1554 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1555 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1556
1557 ath5k_debug_printrxbuffs(sc, ah);
1558
1559 sc->rxlink = NULL; /* just in case */
1560}
1561
1562static unsigned int
1563ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1564 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1565{
1566 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1567 unsigned int keyix, hlen;
fa1c114f 1568
b47f407b
BR		 1569 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1570 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1571 return RX_FLAG_DECRYPTED;
1572
1573 /* Apparently when a default key is used to decrypt the packet
1574 the hw does not set the index used to decrypt. In such cases
1575 get the index from the packet. */
798ee985 1576 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1577 if (ieee80211_has_protected(hdr->frame_control) &&
1578 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1579 skb->len >= hlen + 4) {
fa1c114f
JS		 1580 keyix = skb->data[hlen + 3] >> 6;
1581
1582 if (test_bit(keyix, sc->keymap))
1583 return RX_FLAG_DECRYPTED;
1584 }
1585
1586 return 0;
1587}
1588
036cd1ec
BR		 1589
1590static void
6ba81c2c
BR		 1591ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1592 struct ieee80211_rx_status *rxs)
036cd1ec 1593{
6ba81c2c 1594 u64 tsf, bc_tstamp;
036cd1ec
BR		 1595 u32 hw_tu;
1596 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1597
24b56e70 1598 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1599 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1600 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1601 /*
6ba81c2c
BR		 1602 * Received an IBSS beacon with the same BSSID. Hardware *must*
1603 * have updated the local TSF. We have to work around various
1604 * hardware bugs, though...
036cd1ec 1605 */
6ba81c2c
BR		 1606 tsf = ath5k_hw_get_tsf64(sc->ah);
1607 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1608 hw_tu = TSF_TO_TU(tsf);
1609
1610 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1611 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1612 (unsigned long long)bc_tstamp,
1613 (unsigned long long)rxs->mactime,
1614 (unsigned long long)(rxs->mactime - bc_tstamp),
1615 (unsigned long long)tsf);
6ba81c2c
BR		 1616
1617 /*
1618 * Sometimes the HW will give us a wrong tstamp in the rx
1619 * status, causing the timestamp extension to go wrong.
1620 * (This seems to happen especially with beacon frames bigger
1621 * than 78 byte (incl. FCS))
1622 * But we know that the receive timestamp must be later than the
1623 * timestamp of the beacon since HW must have synced to that.
1624 *
1625 * NOTE: here we assume mactime to be after the frame was
1626 * received, not like mac80211 which defines it at the start.
1627 */
1628 if (bc_tstamp > rxs->mactime) {
036cd1ec 1629 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1630 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1631 (unsigned long long)rxs->mactime,
1632 (unsigned long long)tsf);
6ba81c2c 1633 rxs->mactime = tsf;
036cd1ec 1634 }
6ba81c2c
BR		 1635
1636 /*
1637 * Local TSF might have moved higher than our beacon timers,
1638 * in that case we have to update them to continue sending
1639 * beacons. This also takes care of synchronizing beacon sending
1640 * times with other stations.
1641 */
1642 if (hw_tu >= sc->nexttbtt)
1643 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1644 }
1645}
1646
1647
fa1c114f
JS		 1648static void
1649ath5k_tasklet_rx(unsigned long data)
1650{
1651 struct ieee80211_rx_status rxs = {};
b47f407b 1652 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1653 struct sk_buff *skb;
1654 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1655 struct ath5k_buf *bf, *bf_last;
fa1c114f 1656 struct ath5k_desc *ds;
fa1c114f
JS		 1657 int ret;
1658 int hdrlen;
1659 int pad;
1660
1661 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1662 if (list_empty(&sc->rxbuf)) {
1663 ATH5K_WARN(sc, "empty rx buf pool\n");
1664 goto unlock;
1665 }
1666 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1667 do {
d6894b5b
BC		 1668 rxs.flag = 0;
1669
fa1c114f
JS		 1670 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1671 BUG_ON(bf->skb == NULL);
1672 skb = bf->skb;
1673 ds = bf->desc;
1674
3a0f2c87
JS		 1675 /*
1676 * last buffer must not be freed to ensure proper hardware
1677 * function. When the hardware finishes also a packet next to
1678 * it, we are sure, it doesn't use it anymore and we can go on.
1679 */
1680 if (bf_last == bf)
1681 bf->flags |= 1;
1682 if (bf->flags) {
1683 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1684 struct ath5k_buf, list);
1685 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1686 &rs);
1687 if (ret)
1688 break;
1689 bf->flags &= ~1;
1690 /* skip the overwritten one (even status is martian) */
1691 goto next;
1692 }
fa1c114f 1693
b47f407b 1694 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1695 if (unlikely(ret == -EINPROGRESS))
1696 break;
1697 else if (unlikely(ret)) {
1698 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1699 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1700 return;
1701 }
1702
b47f407b 1703 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1704 ATH5K_WARN(sc, "unsupported jumbo\n");
1705 goto next;
1706 }
1707
b47f407b
BR		 1708 if (unlikely(rs.rs_status)) {
1709 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1710 goto next;
b47f407b 1711 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1712 /*
1713 * Decrypt error. If the error occurred
1714 * because there was no hardware key, then
1715 * let the frame through so the upper layers
1716 * can process it. This is necessary for 5210
1717 * parts which have no way to setup a ``clear''
1718 * key cache entry.
1719 *
1720 * XXX do key cache faulting
1721 */
b47f407b
BR		 1722 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1723 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1724 goto accept;
1725 }
b47f407b 1726 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1727 rxs.flag |= RX_FLAG_MMIC_ERROR;
1728 goto accept;
1729 }
1730
1731 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1732 if ((rs.rs_status &
1733 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1734 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1735 goto next;
1736 }
1737accept:
fa1c114f
JS		 1738 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1739 PCI_DMA_FROMDEVICE);
1740 bf->skb = NULL;
1741
b47f407b 1742 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1743
1744 /*
1745 * the hardware adds a padding to 4 byte boundaries between
1746 * the header and the payload data if the header length is
1747 * not multiples of 4 - remove it
1748 */
1749 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1750 if (hdrlen & 3) {
1751 pad = hdrlen % 4;
1752 memmove(skb->data + pad, skb->data, hdrlen);
1753 skb_pull(skb, pad);
1754 }
1755
c0e1899b
BR		 1756 /*
1757 * always extend the mac timestamp, since this information is
1758 * also needed for proper IBSS merging.
1759 *
1760 * XXX: it might be too late to do it here, since rs_tstamp is
1761 * 15bit only. that means TSF extension has to be done within
1762 * 32768usec (about 32ms). it might be necessary to move this to
1763 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1764 *
1765 * Unfortunately we don't know when the hardware takes the rx
1766 * timestamp (beginning of phy frame, data frame, end of rx?).
1767 * The only thing we know is that it is hardware specific...
1768 * On AR5213 it seems the rx timestamp is at the end of the
1769 * frame, but i'm not sure.
1770 *
1771 * NOTE: mac80211 defines mactime at the beginning of the first
1772 * data symbol. Since we don't have any time references it's
1773 * impossible to comply to that. This affects IBSS merge only
1774 * right now, so it's not too bad...
c0e1899b 1775 */
b47f407b 1776 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1777 rxs.flag |= RX_FLAG_TSFT;
1778
d8ee398d
LR		 1779 rxs.freq = sc->curchan->center_freq;
1780 rxs.band = sc->curband->band;
fa1c114f 1781
fa1c114f 1782 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1783 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1784
1785 /* An rssi of 35 indicates you should be able use
1786 * 54 Mbps reliably. A more elaborate scheme can be used
1787 * here but it requires a map of SNR/throughput for each
1788 * possible mode used */
1789 rxs.qual = rs.rs_rssi * 100 / 35;
1790
1791 /* rssi can be more than 35 though, anything above that
1792 * should be considered at 100% */
1793 if (rxs.qual > 100)
1794 rxs.qual = 100;
fa1c114f 1795
b47f407b
BR		 1796 rxs.antenna = rs.rs_antenna;
1797 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1798 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1799
06303352
BR		 1800 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1801 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1802 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1803
fa1c114f
JS		 1804 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1805
036cd1ec 1806 /* check beacons in IBSS mode */
05c914fe 1807 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1808 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1809
fa1c114f 1810 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1811next:
1812 list_move_tail(&bf->list, &sc->rxbuf);
1813 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1814unlock:
fa1c114f
JS		 1815 spin_unlock(&sc->rxbuflock);
1816}
1817
1818
1819
1820
1821/*************\
1822* TX Handling *
1823\*************/
1824
1825static void
1826ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1827{
b47f407b 1828 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1829 struct ath5k_buf *bf, *bf0;
1830 struct ath5k_desc *ds;
1831 struct sk_buff *skb;
e039fa4a 1832 struct ieee80211_tx_info *info;
2f7fe870 1833 int i, ret;
fa1c114f
JS		 1834
1835 spin_lock(&txq->lock);
1836 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1837 ds = bf->desc;
1838
b47f407b 1839 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1840 if (unlikely(ret == -EINPROGRESS))
1841 break;
1842 else if (unlikely(ret)) {
1843 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1844 ret, txq->qnum);
1845 break;
1846 }
1847
1848 skb = bf->skb;
a888d52d 1849 info = IEEE80211_SKB_CB(skb);
fa1c114f 1850 bf->skb = NULL;
e039fa4a 1851
fa1c114f
JS		 1852 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1853 PCI_DMA_TODEVICE);
1854
e6a9854b 1855 ieee80211_tx_info_clear_status(info);
2f7fe870 1856 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1857 struct ieee80211_tx_rate *r =
1858 &info->status.rates[i];
2f7fe870
FF		 1859
1860 if (ts.ts_rate[i]) {
e6a9854b
JB		 1861 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1862 r->count = ts.ts_retry[i];
2f7fe870 1863 } else {
e6a9854b
JB		 1864 r->idx = -1;
1865 r->count = 0;
2f7fe870
FF		 1866 }
1867 }
1868
e6a9854b
JB		 1869 /* count the successful attempt as well */
1870 info->status.rates[ts.ts_final_idx].count++;
1871
b47f407b 1872 if (unlikely(ts.ts_status)) {
fa1c114f 1873 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1874 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1875 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1876 } else {
e039fa4a
JB		 1877 info->flags |= IEEE80211_TX_STAT_ACK;
1878 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1879 }
1880
e039fa4a 1881 ieee80211_tx_status(sc->hw, skb);
57ffc589 1882 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1883
1884 spin_lock(&sc->txbuflock);
57ffc589 1885 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1886 list_move_tail(&bf->list, &sc->txbuf);
1887 sc->txbuf_len++;
1888 spin_unlock(&sc->txbuflock);
1889 }
1890 if (likely(list_empty(&txq->q)))
1891 txq->link = NULL;
1892 spin_unlock(&txq->lock);
1893 if (sc->txbuf_len > ATH_TXBUF / 5)
1894 ieee80211_wake_queues(sc->hw);
1895}
1896
1897static void
1898ath5k_tasklet_tx(unsigned long data)
1899{
1900 struct ath5k_softc *sc = (void *)data;
1901
1902 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1903}
1904
1905
fa1c114f
JS		 1906/*****************\
1907* Beacon handling *
1908\*****************/
1909
1910/*
1911 * Setup the beacon frame for transmit.
1912 */
1913static int
e039fa4a 1914ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1915{
1916 struct sk_buff *skb = bf->skb;
a888d52d 1917 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1918 struct ath5k_hw *ah = sc->ah;
1919 struct ath5k_desc *ds;
1920 int ret, antenna = 0;
1921 u32 flags;
1922
1923 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1924 PCI_DMA_TODEVICE);
1925 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1926 "skbaddr %llx\n", skb, skb->data, skb->len,
1927 (unsigned long long)bf->skbaddr);
8d8bb39b 1928 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1929 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1930 return -EIO;
1931 }
1932
1933 ds = bf->desc;
1934
1935 flags = AR5K_TXDESC_NOACK;
05c914fe 1936 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1937 ds->ds_link = bf->daddr; /* self-linked */
1938 flags |= AR5K_TXDESC_VEOL;
1939 /*
1940 * Let hardware handle antenna switching if txantenna is not set
1941 */
1942 } else {
1943 ds->ds_link = 0;
1944 /*
1945 * Switch antenna every 4 beacons if txantenna is not set
1946 * XXX assumes two antennas
1947 */
1948 if (antenna == 0)
1949 antenna = sc->bsent & 4 ? 2 : 1;
1950 }
1951
1952 ds->ds_data = bf->skbaddr;
281c56dd 1953 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1954 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1955 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1956 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1957 1, AR5K_TXKEYIX_INVALID,
400ec45a 1958 antenna, flags, 0, 0);
fa1c114f
JS		 1959 if (ret)
1960 goto err_unmap;
1961
1962 return 0;
1963err_unmap:
1964 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1965 return ret;
1966}
1967
1968/*
1969 * Transmit a beacon frame at SWBA. Dynamic updates to the
1970 * frame contents are done as needed and the slot time is
1971 * also adjusted based on current state.
1972 *
1973 * this is usually called from interrupt context (ath5k_intr())
1974 * but also from ath5k_beacon_config() in IBSS mode which in turn
1975 * can be called from a tasklet and user context
1976 */
1977static void
1978ath5k_beacon_send(struct ath5k_softc *sc)
1979{
1980 struct ath5k_buf *bf = sc->bbuf;
1981 struct ath5k_hw *ah = sc->ah;
1982
be9b7259 1983 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1984
05c914fe
JB		 1985 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1986 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 1987 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1988 return;
1989 }
1990 /*
1991 * Check if the previous beacon has gone out. If
1992 * not don't don't try to post another, skip this
1993 * period and wait for the next. Missed beacons
1994 * indicate a problem and should not occur. If we
1995 * miss too many consecutive beacons reset the device.
1996 */
1997 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1998 sc->bmisscount++;
be9b7259 1999 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2000 "missed %u consecutive beacons\n", sc->bmisscount);
2001 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2002 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2003 "stuck beacon time (%u missed)\n",
2004 sc->bmisscount);
2005 tasklet_schedule(&sc->restq);
2006 }
2007 return;
2008 }
2009 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2010 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2011 "resume beacon xmit after %u misses\n",
2012 sc->bmisscount);
2013 sc->bmisscount = 0;
2014 }
2015
2016 /*
2017 * Stop any current dma and put the new frame on the queue.
2018 * This should never fail since we check above that no frames
2019 * are still pending on the queue.
2020 */
2021 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2022 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2023 /* NB: hw still stops DMA, so proceed */
2024 }
fa1c114f 2025
c6e387a2
NK		 2026 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2027 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2028 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2029 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2030
2031 sc->bsent++;
2032}
2033
2034
9804b98d
BR		 2035/**
2036 * ath5k_beacon_update_timers - update beacon timers
2037 *
2038 * @sc: struct ath5k_softc pointer we are operating on
2039 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2040 * beacon timer update based on the current HW TSF.
2041 *
2042 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2043 * of a received beacon or the current local hardware TSF and write it to the
2044 * beacon timer registers.
2045 *
2046 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2047 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2048 * when we otherwise know we have to update the timers, but we keep it in this
2049 * function to have it all together in one place.
2050 */
fa1c114f 2051static void
9804b98d 2052ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2053{
2054 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2055 u32 nexttbtt, intval, hw_tu, bc_tu;
2056 u64 hw_tsf;
fa1c114f
JS		 2057
2058 intval = sc->bintval & AR5K_BEACON_PERIOD;
2059 if (WARN_ON(!intval))
2060 return;
2061
9804b98d
BR		 2062 /* beacon TSF converted to TU */
2063 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2064
9804b98d
BR		 2065 /* current TSF converted to TU */
2066 hw_tsf = ath5k_hw_get_tsf64(ah);
2067 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2068
9804b98d
BR		 2069#define FUDGE 3
2070 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2071 if (bc_tsf == -1) {
2072 /*
2073 * no beacons received, called internally.
2074 * just need to refresh timers based on HW TSF.
2075 */
2076 nexttbtt = roundup(hw_tu + FUDGE, intval);
2077 } else if (bc_tsf == 0) {
2078 /*
2079 * no beacon received, probably called by ath5k_reset_tsf().
2080 * reset TSF to start with 0.
2081 */
2082 nexttbtt = intval;
2083 intval |= AR5K_BEACON_RESET_TSF;
2084 } else if (bc_tsf > hw_tsf) {
2085 /*
2086 * beacon received, SW merge happend but HW TSF not yet updated.
2087 * not possible to reconfigure timers yet, but next time we
2088 * receive a beacon with the same BSSID, the hardware will
2089 * automatically update the TSF and then we need to reconfigure
2090 * the timers.
2091 */
2092 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2093 "need to wait for HW TSF sync\n");
2094 return;
2095 } else {
2096 /*
2097 * most important case for beacon synchronization between STA.
2098 *
2099 * beacon received and HW TSF has been already updated by HW.
2100 * update next TBTT based on the TSF of the beacon, but make
2101 * sure it is ahead of our local TSF timer.
2102 */
2103 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2104 }
2105#undef FUDGE
fa1c114f 2106
036cd1ec
BR		 2107 sc->nexttbtt = nexttbtt;
2108
fa1c114f 2109 intval |= AR5K_BEACON_ENA;
fa1c114f 2110 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2111
2112 /*
2113 * debugging output last in order to preserve the time critical aspect
2114 * of this function
2115 */
2116 if (bc_tsf == -1)
2117 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2118 "reconfigured timers based on HW TSF\n");
2119 else if (bc_tsf == 0)
2120 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2121 "reset HW TSF and timers\n");
2122 else
2123 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2124 "updated timers based on beacon TSF\n");
2125
2126 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2127 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2128 (unsigned long long) bc_tsf,
2129 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2130 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2131 intval & AR5K_BEACON_PERIOD,
2132 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2133 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2134}
2135
2136
036cd1ec
BR		 2137/**
2138 * ath5k_beacon_config - Configure the beacon queues and interrupts
2139 *
2140 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2141 *
2142 * When operating in station mode we want to receive a BMISS interrupt when we
2143 * stop seeing beacons from the AP we've associated with so we can look for
2144 * another AP to associate with.
2145 *
036cd1ec 2146 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2147 * interrupts to detect TSF updates only.
fa1c114f
JS		 2148 */
2149static void
2150ath5k_beacon_config(struct ath5k_softc *sc)
2151{
2152 struct ath5k_hw *ah = sc->ah;
2153
c6e387a2 2154 ath5k_hw_set_imr(ah, 0);
fa1c114f 2155 sc->bmisscount = 0;
dc1968e7 2156 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2157
05c914fe 2158 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2159 sc->imask |= AR5K_INT_BMISS;
da966bca 2160 } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2161 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2162 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2163 /*
036cd1ec
BR		 2164 * In IBSS mode we use a self-linked tx descriptor and let the
2165 * hardware send the beacons automatically. We have to load it
fa1c114f 2166 * only once here.
036cd1ec 2167 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2168 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2169 */
2170 ath5k_beaconq_config(sc);
fa1c114f 2171
036cd1ec
BR		 2172 sc->imask |= AR5K_INT_SWBA;
2173
da966bca
JS		 2174 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2175 if (ath5k_hw_hasveol(ah)) {
2176 spin_lock(&sc->block);
2177 ath5k_beacon_send(sc);
2178 spin_unlock(&sc->block);
2179 }
2180 } else
2181 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2182 }
fa1c114f 2183
c6e387a2 2184 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2185}
2186
2187
2188/********************\
2189* Interrupt handling *
2190\********************/
2191
2192static int
8bdd5b9c 2193ath5k_init(struct ath5k_softc *sc, bool is_resume)
fa1c114f 2194{
bc1b32d6
EO		 2195 struct ath5k_hw *ah = sc->ah;
2196 int ret, i;
fa1c114f
JS		 2197
2198 mutex_lock(&sc->lock);
2199
8bdd5b9c
BC		 2200 if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2201 goto out_ok;
2202
2203 __clear_bit(ATH_STAT_STARTED, sc->status);
2204
fa1c114f
JS		 2205 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2206
2207 /*
2208 * Stop anything previously setup. This is safe
2209 * no matter this is the first time through or not.
2210 */
2211 ath5k_stop_locked(sc);
2212
2213 /*
2214 * The basic interface to setting the hardware in a good
2215 * state is ``reset''. On return the hardware is known to
2216 * be powered up and with interrupts disabled. This must
2217 * be followed by initialization of the appropriate bits
2218 * and then setup of the interrupt mask.
2219 */
d8ee398d
LR		 2220 sc->curchan = sc->hw->conf.channel;
2221 sc->curband = &sc->sbands[sc->curchan->band];
4c674c60 2222 sc->imask = AR5K_INT_RXOK | AR5K_INT_TXOK | AR5K_INT_RXEOL |
194828a2
NK		 2223 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2224 AR5K_INT_MIB;
d7dc1003
JS		 2225 ret = ath5k_reset(sc, false, false);
2226 if (ret)
2227 goto done;
fa1c114f 2228
bc1b32d6
EO		 2229 /*
2230 * Reset the key cache since some parts do not reset the
2231 * contents on initial power up or resume from suspend.
2232 */
2233 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2234 ath5k_hw_reset_key(ah, i);
2235
8bdd5b9c
BC		 2236 __set_bit(ATH_STAT_STARTED, sc->status);
2237
fa1c114f 2238 /* Set ack to be sent at low bit-rates */
bc1b32d6 2239 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2240
2241 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2242 msecs_to_jiffies(ath5k_calinterval * 1000)));
2243
8bdd5b9c 2244out_ok:
fa1c114f
JS		 2245 ret = 0;
2246done:
274c7c36 2247 mmiowb();
fa1c114f
JS		 2248 mutex_unlock(&sc->lock);
2249 return ret;
2250}
2251
2252static int
2253ath5k_stop_locked(struct ath5k_softc *sc)
2254{
2255 struct ath5k_hw *ah = sc->ah;
2256
2257 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2258 test_bit(ATH_STAT_INVALID, sc->status));
2259
2260 /*
2261 * Shutdown the hardware and driver:
2262 * stop output from above
2263 * disable interrupts
2264 * turn off timers
2265 * turn off the radio
2266 * clear transmit machinery
2267 * clear receive machinery
2268 * drain and release tx queues
2269 * reclaim beacon resources
2270 * power down hardware
2271 *
2272 * Note that some of this work is not possible if the
2273 * hardware is gone (invalid).
2274 */
2275 ieee80211_stop_queues(sc->hw);
2276
2277 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2278 ath5k_led_off(sc);
c6e387a2 2279 ath5k_hw_set_imr(ah, 0);
274c7c36 2280 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2281 }
2282 ath5k_txq_cleanup(sc);
2283 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2284 ath5k_rx_stop(sc);
2285 ath5k_hw_phy_disable(ah);
2286 } else
2287 sc->rxlink = NULL;
2288
2289 return 0;
2290}
2291
2292/*
2293 * Stop the device, grabbing the top-level lock to protect
2294 * against concurrent entry through ath5k_init (which can happen
2295 * if another thread does a system call and the thread doing the
2296 * stop is preempted).
2297 */
2298static int
8bdd5b9c 2299ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
fa1c114f
JS		 2300{
2301 int ret;
2302
2303 mutex_lock(&sc->lock);
2304 ret = ath5k_stop_locked(sc);
2305 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2306 /*
2307 * Set the chip in full sleep mode. Note that we are
2308 * careful to do this only when bringing the interface
2309 * completely to a stop. When the chip is in this state
2310 * it must be carefully woken up or references to
2311 * registers in the PCI clock domain may freeze the bus
2312 * (and system). This varies by chip and is mostly an
2313 * issue with newer parts that go to sleep more quickly.
2314 */
2315 if (sc->ah->ah_mac_srev >= 0x78) {
2316 /*
2317 * XXX
2318 * don't put newer MAC revisions > 7.8 to sleep because
2319 * of the above mentioned problems
2320 */
2321 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2322 "not putting device to sleep\n");
2323 } else {
2324 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2325 "putting device to full sleep\n");
2326 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2327 }
2328 }
2329 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c
BC		 2330 if (!is_suspend)
2331 __clear_bit(ATH_STAT_STARTED, sc->status);
2332
274c7c36 2333 mmiowb();
fa1c114f
JS		 2334 mutex_unlock(&sc->lock);
2335
2336 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2337 tasklet_kill(&sc->rxtq);
2338 tasklet_kill(&sc->txtq);
2339 tasklet_kill(&sc->restq);
fa1c114f
JS		 2340
2341 return ret;
2342}
2343
2344static irqreturn_t
2345ath5k_intr(int irq, void *dev_id)
2346{
2347 struct ath5k_softc *sc = dev_id;
2348 struct ath5k_hw *ah = sc->ah;
2349 enum ath5k_int status;
2350 unsigned int counter = 1000;
2351
2352 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2353 !ath5k_hw_is_intr_pending(ah)))
2354 return IRQ_NONE;
2355
2356 do {
2357 /*
2358 * Figure out the reason(s) for the interrupt. Note
2359 * that get_isr returns a pseudo-ISR that may include
2360 * bits we haven't explicitly enabled so we mask the
2361 * value to insure we only process bits we requested.
2362 */
2363 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2364 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2365 status, sc->imask);
2366 status &= sc->imask; /* discard unasked for bits */
2367 if (unlikely(status & AR5K_INT_FATAL)) {
2368 /*
2369 * Fatal errors are unrecoverable.
2370 * Typically these are caused by DMA errors.
2371 */
2372 tasklet_schedule(&sc->restq);
2373 } else if (unlikely(status & AR5K_INT_RXORN)) {
2374 tasklet_schedule(&sc->restq);
2375 } else {
2376 if (status & AR5K_INT_SWBA) {
2377 /*
2378 * Software beacon alert--time to send a beacon.
2379 * Handle beacon transmission directly; deferring
2380 * this is too slow to meet timing constraints
2381 * under load.
036cd1ec
BR		 2382 *
2383 * In IBSS mode we use this interrupt just to
2384 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2385 * transmission time) in order to detect wether
2386 * automatic TSF updates happened.
fa1c114f 2387 */
05c914fe 2388 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2389 /* XXX: only if VEOL suppported */
2390 u64 tsf = ath5k_hw_get_tsf64(ah);
2391 sc->nexttbtt += sc->bintval;
2392 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2393 "SWBA nexttbtt: %x hw_tu: %x "
2394 "TSF: %llx\n",
2395 sc->nexttbtt,
2396 TSF_TO_TU(tsf),
2397 (unsigned long long) tsf);
036cd1ec 2398 } else {
00482973 2399 spin_lock(&sc->block);
036cd1ec 2400 ath5k_beacon_send(sc);
00482973 2401 spin_unlock(&sc->block);
036cd1ec 2402 }
fa1c114f
JS		 2403 }
2404 if (status & AR5K_INT_RXEOL) {
2405 /*
2406 * NB: the hardware should re-read the link when
2407 * RXE bit is written, but it doesn't work at
2408 * least on older hardware revs.
2409 */
2410 sc->rxlink = NULL;
2411 }
2412 if (status & AR5K_INT_TXURN) {
2413 /* bump tx trigger level */
2414 ath5k_hw_update_tx_triglevel(ah, true);
2415 }
4c674c60 2416 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2417 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2418 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2419 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2420 tasklet_schedule(&sc->txtq);
2421 if (status & AR5K_INT_BMISS) {
2422 }
2423 if (status & AR5K_INT_MIB) {
194828a2
NK		 2424 /*
2425 * These stats are also used for ANI i think
2426 * so how about updating them more often ?
2427 */
2428 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2429 }
2430 }
2431 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2432
2433 if (unlikely(!counter))
2434 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2435
2436 return IRQ_HANDLED;
2437}
2438
2439static void
2440ath5k_tasklet_reset(unsigned long data)
2441{
2442 struct ath5k_softc *sc = (void *)data;
2443
d7dc1003 2444 ath5k_reset_wake(sc);
fa1c114f
JS		 2445}
2446
2447/*
2448 * Periodically recalibrate the PHY to account
2449 * for temperature/environment changes.
2450 */
2451static void
2452ath5k_calibrate(unsigned long data)
2453{
2454 struct ath5k_softc *sc = (void *)data;
2455 struct ath5k_hw *ah = sc->ah;
2456
2457 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2458 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2459 sc->curchan->hw_value);
fa1c114f
JS		 2460
2461 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2462 /*
2463 * Rfgain is out of bounds, reset the chip
2464 * to load new gain values.
2465 */
2466 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2467 ath5k_reset_wake(sc);
fa1c114f
JS		 2468 }
2469 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2470 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2471 ieee80211_frequency_to_channel(
2472 sc->curchan->center_freq));
fa1c114f
JS		 2473
2474 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2475 msecs_to_jiffies(ath5k_calinterval * 1000)));
2476}
2477
2478
2479
2480/***************\
2481* LED functions *
2482\***************/
2483
2484static void
3a078876 2485ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2486{
3a078876
BC		 2487 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2488 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2489 ath5k_led_off(sc);
fa1c114f
JS		 2490 }
2491}
2492
fa1c114f 2493static void
3a078876 2494ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2495{
3a078876
BC		 2496 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2497 return;
fa1c114f 2498 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2499}
2500
2501static void
3a078876 2502ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2503{
3a078876 2504 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2505 return;
3a078876
BC		 2506 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2507}
2508
2509static void
2510ath5k_led_brightness_set(struct led_classdev *led_dev,
2511 enum led_brightness brightness)
2512{
2513 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2514 led_dev);
2515
2516 if (brightness == LED_OFF)
2517 ath5k_led_off(led->sc);
2518 else
2519 ath5k_led_on(led->sc);
2520}
2521
2522static int
2523ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2524 const char *name, char *trigger)
2525{
2526 int err;
2527
2528 led->sc = sc;
2529 strncpy(led->name, name, sizeof(led->name));
2530 led->led_dev.name = led->name;
2531 led->led_dev.default_trigger = trigger;
2532 led->led_dev.brightness_set = ath5k_led_brightness_set;
2533
2534 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
0bbac08f 2535 if (err) {
3a078876
BC		 2536 ATH5K_WARN(sc, "could not register LED %s\n", name);
2537 led->sc = NULL;
fa1c114f 2538 }
3a078876 2539 return err;
fa1c114f
JS		 2540}
2541
3a078876
BC		 2542static void
2543ath5k_unregister_led(struct ath5k_led *led)
2544{
2545 if (!led->sc)
2546 return;
2547 led_classdev_unregister(&led->led_dev);
2548 ath5k_led_off(led->sc);
2549 led->sc = NULL;
2550}
2551
2552static void
2553ath5k_unregister_leds(struct ath5k_softc *sc)
2554{
2555 ath5k_unregister_led(&sc->rx_led);
2556 ath5k_unregister_led(&sc->tx_led);
2557}
2558
2559
2560static int
2561ath5k_init_leds(struct ath5k_softc *sc)
2562{
2563 int ret = 0;
2564 struct ieee80211_hw *hw = sc->hw;
2565 struct pci_dev *pdev = sc->pdev;
2566 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2567
3a078876
BC		 2568 /*
2569 * Auto-enable soft led processing for IBM cards and for
2570 * 5211 minipci cards.
2571 */
2572 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2573 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2574 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2575 sc->led_pin = 0;
734b5aa9 2576 sc->led_on = 0; /* active low */
3a078876
BC		 2577 }
2578 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2579 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2580 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2581 sc->led_pin = 1;
734b5aa9 2582 sc->led_on = 1; /* active high */
3a078876
BC		 2583 }
2584 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2585 goto out;
2586
2587 ath5k_led_enable(sc);
2588
2589 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2590 ret = ath5k_register_led(sc, &sc->rx_led, name,
2591 ieee80211_get_rx_led_name(hw));
2592 if (ret)
2593 goto out;
2594
2595 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2596 ret = ath5k_register_led(sc, &sc->tx_led, name,
2597 ieee80211_get_tx_led_name(hw));
2598out:
2599 return ret;
2600}
fa1c114f
JS		 2601
2602
2603/********************\
2604* Mac80211 functions *
2605\********************/
2606
2607static int
e039fa4a 2608ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2609{
2610 struct ath5k_softc *sc = hw->priv;
2611 struct ath5k_buf *bf;
2612 unsigned long flags;
2613 int hdrlen;
2614 int pad;
2615
2616 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2617
05c914fe 2618 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2619 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2620
2621 /*
2622 * the hardware expects the header padded to 4 byte boundaries
2623 * if this is not the case we add the padding after the header
2624 */
2625 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2626 if (hdrlen & 3) {
2627 pad = hdrlen % 4;
2628 if (skb_headroom(skb) < pad) {
2629 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2630 " headroom to pad %d\n", hdrlen, pad);
2631 return -1;
2632 }
2633 skb_push(skb, pad);
2634 memmove(skb->data, skb->data+pad, hdrlen);
2635 }
2636
fa1c114f
JS		 2637 spin_lock_irqsave(&sc->txbuflock, flags);
2638 if (list_empty(&sc->txbuf)) {
2639 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2640 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2641 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2642 return -1;
2643 }
2644 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2645 list_del(&bf->list);
2646 sc->txbuf_len--;
2647 if (list_empty(&sc->txbuf))
2648 ieee80211_stop_queues(hw);
2649 spin_unlock_irqrestore(&sc->txbuflock, flags);
2650
2651 bf->skb = skb;
2652
e039fa4a 2653 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2654 bf->skb = NULL;
2655 spin_lock_irqsave(&sc->txbuflock, flags);
2656 list_add_tail(&bf->list, &sc->txbuf);
2657 sc->txbuf_len++;
2658 spin_unlock_irqrestore(&sc->txbuflock, flags);
2659 dev_kfree_skb_any(skb);
2660 return 0;
2661 }
2662
2663 return 0;
2664}
2665
2666static int
d7dc1003 2667ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2668{
fa1c114f
JS		 2669 struct ath5k_hw *ah = sc->ah;
2670 int ret;
2671
2672 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2673
d7dc1003 2674 if (stop) {
c6e387a2 2675 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2676 ath5k_txq_cleanup(sc);
2677 ath5k_rx_stop(sc);
2678 }
fa1c114f 2679 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2680 if (ret) {
fa1c114f
JS		 2681 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2682 goto err;
2683 }
d7dc1003
JS		 2684
2685 /*
2686 * This is needed only to setup initial state
2687 * but it's best done after a reset.
2688 */
fa1c114f
JS		 2689 ath5k_hw_set_txpower_limit(sc->ah, 0);
2690
2691 ret = ath5k_rx_start(sc);
d7dc1003 2692 if (ret) {
fa1c114f
JS		 2693 ATH5K_ERR(sc, "can't start recv logic\n");
2694 goto err;
2695 }
d7dc1003 2696
fa1c114f 2697 /*
d7dc1003
JS		 2698 * Change channels and update the h/w rate map if we're switching;
2699 * e.g. 11a to 11b/g.
2700 *
2701 * We may be doing a reset in response to an ioctl that changes the
2702 * channel so update any state that might change as a result.
fa1c114f
JS		 2703 *
2704 * XXX needed?
2705 */
2706/* ath5k_chan_change(sc, c); */
fa1c114f 2707
d7dc1003
JS		 2708 ath5k_beacon_config(sc);
2709 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2710
2711 return 0;
2712err:
2713 return ret;
2714}
2715
d7dc1003
JS		 2716static int
2717ath5k_reset_wake(struct ath5k_softc *sc)
2718{
2719 int ret;
2720
2721 ret = ath5k_reset(sc, true, true);
2722 if (!ret)
2723 ieee80211_wake_queues(sc->hw);
2724
2725 return ret;
2726}
2727
fa1c114f
JS		 2728static int ath5k_start(struct ieee80211_hw *hw)
2729{
8bdd5b9c 2730 return ath5k_init(hw->priv, false);
fa1c114f
JS		 2731}
2732
2733static void ath5k_stop(struct ieee80211_hw *hw)
2734{
8bdd5b9c 2735 ath5k_stop_hw(hw->priv, false);
fa1c114f
JS		 2736}
2737
2738static int ath5k_add_interface(struct ieee80211_hw *hw,
2739 struct ieee80211_if_init_conf *conf)
2740{
2741 struct ath5k_softc *sc = hw->priv;
2742 int ret;
2743
2744 mutex_lock(&sc->lock);
32bfd35d 2745 if (sc->vif) {
fa1c114f
JS		 2746 ret = 0;
2747 goto end;
2748 }
2749
32bfd35d 2750 sc->vif = conf->vif;
fa1c114f
JS		 2751
2752 switch (conf->type) {
da966bca 2753 case NL80211_IFTYPE_AP:
05c914fe
JB		 2754 case NL80211_IFTYPE_STATION:
2755 case NL80211_IFTYPE_ADHOC:
b706e65b 2756 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2757 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2758 sc->opmode = conf->type;
2759 break;
2760 default:
2761 ret = -EOPNOTSUPP;
2762 goto end;
2763 }
67d2e2df
JS		 2764
2765 /* Set to a reasonable value. Note that this will
2766 * be set to mac80211's value at ath5k_config(). */
2767 sc->bintval = 1000;
2768
fa1c114f
JS		 2769 ret = 0;
2770end:
2771 mutex_unlock(&sc->lock);
2772 return ret;
2773}
2774
2775static void
2776ath5k_remove_interface(struct ieee80211_hw *hw,
2777 struct ieee80211_if_init_conf *conf)
2778{
2779 struct ath5k_softc *sc = hw->priv;
2780
2781 mutex_lock(&sc->lock);
32bfd35d 2782 if (sc->vif != conf->vif)
fa1c114f
JS		 2783 goto end;
2784
32bfd35d 2785 sc->vif = NULL;
fa1c114f
JS		 2786end:
2787 mutex_unlock(&sc->lock);
2788}
2789
d8ee398d
LR		 2790/*
2791 * TODO: Phy disable/diversity etc
2792 */
fa1c114f 2793static int
e8975581 2794ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2795{
2796 struct ath5k_softc *sc = hw->priv;
e8975581 2797 struct ieee80211_conf *conf = &hw->conf;
fa1c114f 2798
e535c1ac 2799 sc->bintval = conf->beacon_int;
d8ee398d 2800 sc->power_level = conf->power_level;
fa1c114f 2801
d8ee398d 2802 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2803}
2804
2805static int
32bfd35d 2806ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2807 struct ieee80211_if_conf *conf)
2808{
2809 struct ath5k_softc *sc = hw->priv;
2810 struct ath5k_hw *ah = sc->ah;
2811 int ret;
2812
fa1c114f 2813 mutex_lock(&sc->lock);
32bfd35d 2814 if (sc->vif != vif) {
fa1c114f
JS		 2815 ret = -EIO;
2816 goto unlock;
2817 }
da966bca 2818 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2819 /* Cache for later use during resets */
2820 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2821 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2822 * a clean way of letting us retrieve this yet. */
2823 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2824 mmiowb();
fa1c114f 2825 }
9d139c81 2826 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2827 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2828 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2829 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2830 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2831 if (!beacon) {
2832 ret = -ENOMEM;
2833 goto unlock;
2834 }
da966bca 2835 ath5k_beacon_update(sc, beacon);
9d139c81 2836 }
fa1c114f
JS		 2837 mutex_unlock(&sc->lock);
2838
d7dc1003 2839 return ath5k_reset_wake(sc);
fa1c114f
JS		 2840unlock:
2841 mutex_unlock(&sc->lock);
2842 return ret;
2843}
2844
2845#define SUPPORTED_FIF_FLAGS \
2846 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2847 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2848 FIF_BCN_PRBRESP_PROMISC
2849/*
2850 * o always accept unicast, broadcast, and multicast traffic
2851 * o multicast traffic for all BSSIDs will be enabled if mac80211
2852 * says it should be
2853 * o maintain current state of phy ofdm or phy cck error reception.
2854 * If the hardware detects any of these type of errors then
2855 * ath5k_hw_get_rx_filter() will pass to us the respective
2856 * hardware filters to be able to receive these type of frames.
2857 * o probe request frames are accepted only when operating in
2858 * hostap, adhoc, or monitor modes
2859 * o enable promiscuous mode according to the interface state
2860 * o accept beacons:
2861 * - when operating in adhoc mode so the 802.11 layer creates
2862 * node table entries for peers,
2863 * - when operating in station mode for collecting rssi data when
2864 * the station is otherwise quiet, or
2865 * - when scanning
2866 */
2867static void ath5k_configure_filter(struct ieee80211_hw *hw,
2868 unsigned int changed_flags,
2869 unsigned int *new_flags,
2870 int mc_count, struct dev_mc_list *mclist)
2871{
2872 struct ath5k_softc *sc = hw->priv;
2873 struct ath5k_hw *ah = sc->ah;
2874 u32 mfilt[2], val, rfilt;
2875 u8 pos;
2876 int i;
2877
2878 mfilt[0] = 0;
2879 mfilt[1] = 0;
2880
2881 /* Only deal with supported flags */
2882 changed_flags &= SUPPORTED_FIF_FLAGS;
2883 *new_flags &= SUPPORTED_FIF_FLAGS;
2884
2885 /* If HW detects any phy or radar errors, leave those filters on.
2886 * Also, always enable Unicast, Broadcasts and Multicast
2887 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2888 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2889 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2890 AR5K_RX_FILTER_MCAST);
2891
2892 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2893 if (*new_flags & FIF_PROMISC_IN_BSS) {
2894 rfilt |= AR5K_RX_FILTER_PROM;
2895 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2896 } else {
fa1c114f 2897 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2898 }
fa1c114f
JS		 2899 }
2900
2901 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2902 if (*new_flags & FIF_ALLMULTI) {
2903 mfilt[0] = ~0;
2904 mfilt[1] = ~0;
2905 } else {
2906 for (i = 0; i < mc_count; i++) {
2907 if (!mclist)
2908 break;
2909 /* calculate XOR of eight 6-bit values */
533dd1b0 2910 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2911 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2912 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2913 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2914 pos &= 0x3f;
2915 mfilt[pos / 32] |= (1 << (pos % 32));
2916 /* XXX: we might be able to just do this instead,
2917 * but not sure, needs testing, if we do use this we'd
2918 * neet to inform below to not reset the mcast */
2919 /* ath5k_hw_set_mcast_filterindex(ah,
2920 * mclist->dmi_addr[5]); */
2921 mclist = mclist->next;
2922 }
2923 }
2924
2925 /* This is the best we can do */
2926 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2927 rfilt |= AR5K_RX_FILTER_PHYERR;
2928
2929 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2930 * and probes for any BSSID, this needs testing */
2931 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2932 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2933
2934 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2935 * set we should only pass on control frames for this
2936 * station. This needs testing. I believe right now this
2937 * enables *all* control frames, which is OK.. but
2938 * but we should see if we can improve on granularity */
2939 if (*new_flags & FIF_CONTROL)
2940 rfilt |= AR5K_RX_FILTER_CONTROL;
2941
2942 /* Additional settings per mode -- this is per ath5k */
2943
2944 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2945
05c914fe 2946 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2947 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2948 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2949 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2950 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2951 if (sc->opmode != NL80211_IFTYPE_AP &&
2952 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2953 test_bit(ATH_STAT_PROMISC, sc->status))
2954 rfilt |= AR5K_RX_FILTER_PROM;
934f6c3f
JL		 2955 if (sc->opmode == NL80211_IFTYPE_STATION ||
2956 sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f 2957 rfilt |= AR5K_RX_FILTER_BEACON;
934f6c3f 2958 }
b706e65b
AY		 2959 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2960 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2961 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2962
2963 /* Set filters */
0bbac08f 2964 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2965
2966 /* Set multicast bits */
2967 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2968 /* Set the cached hw filter flags, this will alter actually
2969 * be set in HW */
2970 sc->filter_flags = rfilt;
2971}
2972
2973static int
2974ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2975 const u8 *local_addr, const u8 *addr,
2976 struct ieee80211_key_conf *key)
2977{
2978 struct ath5k_softc *sc = hw->priv;
2979 int ret = 0;
2980
9ad9a26e
BC		 2981 if (modparam_nohwcrypt)
2982 return -EOPNOTSUPP;
2983
0bbac08f 2984 switch (key->alg) {
fa1c114f 2985 case ALG_WEP:
9ad9a26e 2986 break;
fa1c114f
JS		 2987 case ALG_TKIP:
2988 case ALG_CCMP:
2989 return -EOPNOTSUPP;
2990 default:
2991 WARN_ON(1);
2992 return -EINVAL;
2993 }
2994
2995 mutex_lock(&sc->lock);
2996
2997 switch (cmd) {
2998 case SET_KEY:
2999 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
3000 if (ret) {
3001 ATH5K_ERR(sc, "can't set the key\n");
3002 goto unlock;
3003 }
3004 __set_bit(key->keyidx, sc->keymap);
3005 key->hw_key_idx = key->keyidx;
9ad9a26e 3006 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
fa1c114f
JS		 3007 break;
3008 case DISABLE_KEY:
3009 ath5k_hw_reset_key(sc->ah, key->keyidx);
3010 __clear_bit(key->keyidx, sc->keymap);
3011 break;
3012 default:
3013 ret = -EINVAL;
3014 goto unlock;
3015 }
3016
3017unlock:
274c7c36 3018 mmiowb();
fa1c114f
JS		 3019 mutex_unlock(&sc->lock);
3020 return ret;
3021}
3022
3023static int
3024ath5k_get_stats(struct ieee80211_hw *hw,
3025 struct ieee80211_low_level_stats *stats)
3026{
3027 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3028 struct ath5k_hw *ah = sc->ah;
3029
3030 /* Force update */
3031 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3032
3033 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3034
3035 return 0;
3036}
3037
3038static int
3039ath5k_get_tx_stats(struct ieee80211_hw *hw,
3040 struct ieee80211_tx_queue_stats *stats)
3041{
3042 struct ath5k_softc *sc = hw->priv;
3043
3044 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3045
3046 return 0;
3047}
3048
3049static u64
3050ath5k_get_tsf(struct ieee80211_hw *hw)
3051{
3052 struct ath5k_softc *sc = hw->priv;
3053
3054 return ath5k_hw_get_tsf64(sc->ah);
3055}
3056
3057static void
3058ath5k_reset_tsf(struct ieee80211_hw *hw)
3059{
3060 struct ath5k_softc *sc = hw->priv;
3061
9804b98d
BR		 3062 /*
3063 * in IBSS mode we need to update the beacon timers too.
3064 * this will also reset the TSF if we call it with 0
3065 */
05c914fe 3066 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3067 ath5k_beacon_update_timers(sc, 0);
3068 else
3069 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3070}
3071
3072static int
da966bca 3073ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3074{
00482973 3075 unsigned long flags;
fa1c114f
JS		 3076 int ret;
3077
3078 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3079
00482973 3080 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3081 ath5k_txbuf_free(sc, sc->bbuf);
3082 sc->bbuf->skb = skb;
e039fa4a 3083 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3084 if (ret)
3085 sc->bbuf->skb = NULL;
00482973
JS		 3086 spin_unlock_irqrestore(&sc->block, flags);
3087 if (!ret) {
fa1c114f 3088 ath5k_beacon_config(sc);
274c7c36
JS		 3089 mmiowb();
3090 }
fa1c114f 3091
fa1c114f
JS		 3092 return ret;
3093}
3094
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