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iwlwifi: correct device name for 1000 series
[net-next-2.6.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f
JS		 66
67
68/******************\
69* Internal defines *
70\******************/
71
72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 78MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 79
80
81/* Known PCI ids */
82static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 101 { 0 }
102};
103MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105/* Known SREVs */
106static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143};
144
63266a65
BR		 145static struct ieee80211_rate ath5k_rates[] = {
146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185};
186
fa1c114f
JS		 187/*
188 * Prototypes - PCI stack related functions
189 */
190static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193#ifdef CONFIG_PM
194static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196static int ath5k_pci_resume(struct pci_dev *pdev);
197#else
198#define ath5k_pci_suspend NULL
199#define ath5k_pci_resume NULL
200#endif /* CONFIG_PM */
201
04a9e451 202static struct pci_driver ath5k_pci_driver = {
9764f3f9 203 .name = KBUILD_MODNAME,
fa1c114f
JS		 204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209};
210
211
212
213/*
214 * Prototypes - MAC 802.11 stack related functions
215 */
e039fa4a 216static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 217static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 219static int ath5k_start(struct ieee80211_hw *hw);
220static void ath5k_stop(struct ieee80211_hw *hw);
221static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
e8975581 225static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 226static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
fa1c114f
JS		 228 struct ieee80211_if_conf *conf);
229static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
dc822b5d 235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 236 struct ieee80211_key_conf *key);
237static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 242static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 243static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 244static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 245 struct sk_buff *skb);
02969b38
MX		 246static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
249 u32 changes);
fa1c114f
JS		 250
251static struct ieee80211_ops ath5k_hw_ops = {
252 .tx = ath5k_tx,
253 .start = ath5k_start,
254 .stop = ath5k_stop,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
3b5d665b 265 .set_tsf = ath5k_set_tsf,
fa1c114f 266 .reset_tsf = ath5k_reset_tsf,
02969b38 267 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 268};
269
270/*
271 * Prototypes - Internal functions
272 */
273/* Attach detach */
274static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278/* Channel/mode setup */
279static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 280static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
63266a65 284static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 285static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 290
fa1c114f
JS		 291/* Descriptor setup */
292static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296/* Buffers setup */
297static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 300 struct ath5k_buf *bf);
fa1c114f
JS		 301static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303{
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
00482973 309 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 310 bf->skb = NULL;
311}
312
a6c8d375
FF		 313static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
315{
316 BUG_ON(!bf);
317 if (!bf->skb)
318 return;
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
320 PCI_DMA_FROMDEVICE);
321 dev_kfree_skb_any(bf->skb);
322 bf->skb = NULL;
323}
324
325
fa1c114f
JS		 326/* Queues setup */
327static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330static int ath5k_beaconq_config(struct ath5k_softc *sc);
331static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334static void ath5k_txq_release(struct ath5k_softc *sc);
335/* Rx handling */
336static int ath5k_rx_start(struct ath5k_softc *sc);
337static void ath5k_rx_stop(struct ath5k_softc *sc);
338static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
b47f407b
BR		 340 struct sk_buff *skb,
341 struct ath5k_rx_status *rs);
fa1c114f
JS		 342static void ath5k_tasklet_rx(unsigned long data);
343/* Tx handling */
344static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346static void ath5k_tasklet_tx(unsigned long data);
347/* Beacon handling */
348static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 349 struct ath5k_buf *bf);
fa1c114f
JS		 350static void ath5k_beacon_send(struct ath5k_softc *sc);
351static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 352static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 353static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 354
355static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
356{
357 u64 tsf = ath5k_hw_get_tsf64(ah);
358
359 if ((tsf & 0x7fff) < rstamp)
360 tsf -= 0x8000;
361
362 return (tsf & ~0x7fff) | rstamp;
363}
364
365/* Interrupt handling */
bb2becac 366static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 367static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 368static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 369static irqreturn_t ath5k_intr(int irq, void *dev_id);
370static void ath5k_tasklet_reset(unsigned long data);
371
372static void ath5k_calibrate(unsigned long data);
373/* LED functions */
3a078876
BC		 374static int ath5k_init_leds(struct ath5k_softc *sc);
375static void ath5k_led_enable(struct ath5k_softc *sc);
376static void ath5k_led_off(struct ath5k_softc *sc);
377static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 378
379/*
380 * Module init/exit functions
381 */
382static int __init
383init_ath5k_pci(void)
384{
385 int ret;
386
387 ath5k_debug_init();
388
04a9e451 389 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 390 if (ret) {
391 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
392 return ret;
393 }
394
395 return 0;
396}
397
398static void __exit
399exit_ath5k_pci(void)
400{
04a9e451 401 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 402
403 ath5k_debug_finish();
404}
405
406module_init(init_ath5k_pci);
407module_exit(exit_ath5k_pci);
408
409
410/********************\
411* PCI Initialization *
412\********************/
413
414static const char *
415ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
416{
417 const char *name = "xxxxx";
418 unsigned int i;
419
420 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
421 if (srev_names[i].sr_type != type)
422 continue;
75d0edb8
NK		 423
424 if ((val & 0xf0) == srev_names[i].sr_val)
425 name = srev_names[i].sr_name;
426
427 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 428 name = srev_names[i].sr_name;
429 break;
430 }
431 }
432
433 return name;
434}
435
436static int __devinit
437ath5k_pci_probe(struct pci_dev *pdev,
438 const struct pci_device_id *id)
439{
440 void __iomem *mem;
441 struct ath5k_softc *sc;
442 struct ieee80211_hw *hw;
443 int ret;
444 u8 csz;
445
446 ret = pci_enable_device(pdev);
447 if (ret) {
448 dev_err(&pdev->dev, "can't enable device\n");
449 goto err;
450 }
451
452 /* XXX 32-bit addressing only */
453 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
454 if (ret) {
455 dev_err(&pdev->dev, "32-bit DMA not available\n");
456 goto err_dis;
457 }
458
459 /*
460 * Cache line size is used to size and align various
461 * structures used to communicate with the hardware.
462 */
463 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
464 if (csz == 0) {
465 /*
466 * Linux 2.4.18 (at least) writes the cache line size
467 * register as a 16-bit wide register which is wrong.
468 * We must have this setup properly for rx buffer
469 * DMA to work so force a reasonable value here if it
470 * comes up zero.
471 */
472 csz = L1_CACHE_BYTES / sizeof(u32);
473 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
474 }
475 /*
476 * The default setting of latency timer yields poor results,
477 * set it to the value used by other systems. It may be worth
478 * tweaking this setting more.
479 */
480 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
481
482 /* Enable bus mastering */
483 pci_set_master(pdev);
484
485 /*
486 * Disable the RETRY_TIMEOUT register (0x41) to keep
487 * PCI Tx retries from interfering with C3 CPU state.
488 */
489 pci_write_config_byte(pdev, 0x41, 0);
490
491 ret = pci_request_region(pdev, 0, "ath5k");
492 if (ret) {
493 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
494 goto err_dis;
495 }
496
497 mem = pci_iomap(pdev, 0, 0);
498 if (!mem) {
499 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
500 ret = -EIO;
501 goto err_reg;
502 }
503
504 /*
505 * Allocate hw (mac80211 main struct)
506 * and hw->priv (driver private data)
507 */
508 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
509 if (hw == NULL) {
510 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
511 ret = -ENOMEM;
512 goto err_map;
513 }
514
515 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
516
517 /* Initialize driver private data */
518 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 519 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
520 IEEE80211_HW_SIGNAL_DBM |
521 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 522
523 hw->wiphy->interface_modes =
524 BIT(NL80211_IFTYPE_STATION) |
525 BIT(NL80211_IFTYPE_ADHOC) |
526 BIT(NL80211_IFTYPE_MESH_POINT);
527
fa1c114f
JS		 528 hw->extra_tx_headroom = 2;
529 hw->channel_change_time = 5000;
fa1c114f
JS		 530 sc = hw->priv;
531 sc->hw = hw;
532 sc->pdev = pdev;
533
534 ath5k_debug_init_device(sc);
535
536 /*
537 * Mark the device as detached to avoid processing
538 * interrupts until setup is complete.
539 */
540 __set_bit(ATH_STAT_INVALID, sc->status);
541
542 sc->iobase = mem; /* So we can unmap it on detach */
543 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 544 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 545 mutex_init(&sc->lock);
546 spin_lock_init(&sc->rxbuflock);
547 spin_lock_init(&sc->txbuflock);
00482973 548 spin_lock_init(&sc->block);
fa1c114f
JS		 549
550 /* Set private data */
551 pci_set_drvdata(pdev, hw);
552
fa1c114f
JS		 553 /* Setup interrupt handler */
554 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
555 if (ret) {
556 ATH5K_ERR(sc, "request_irq failed\n");
557 goto err_free;
558 }
559
560 /* Initialize device */
561 sc->ah = ath5k_hw_attach(sc, id->driver_data);
562 if (IS_ERR(sc->ah)) {
563 ret = PTR_ERR(sc->ah);
564 goto err_irq;
565 }
566
2f7fe870
FF		 567 /* set up multi-rate retry capabilities */
568 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 569 hw->max_rates = 4;
570 hw->max_rate_tries = 11;
2f7fe870
FF		 571 }
572
fa1c114f
JS		 573 /* Finish private driver data initialization */
574 ret = ath5k_attach(pdev, hw);
575 if (ret)
576 goto err_ah;
577
578 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 579 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 580 sc->ah->ah_mac_srev,
581 sc->ah->ah_phy_revision);
582
400ec45a 583 if (!sc->ah->ah_single_chip) {
fa1c114f 584 /* Single chip radio (!RF5111) */
400ec45a
LR		 585 if (sc->ah->ah_radio_5ghz_revision &&
586 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 587 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 588 if (!test_bit(AR5K_MODE_11A,
589 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 590 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 591 ath5k_chip_name(AR5K_VERSION_RAD,
592 sc->ah->ah_radio_5ghz_revision),
593 sc->ah->ah_radio_5ghz_revision);
594 /* No 2GHz support (5110 and some
595 * 5Ghz only cards) -> report 5Ghz radio */
596 } else if (!test_bit(AR5K_MODE_11B,
597 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 598 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 599 ath5k_chip_name(AR5K_VERSION_RAD,
600 sc->ah->ah_radio_5ghz_revision),
601 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 602 /* Multiband radio */
603 } else {
604 ATH5K_INFO(sc, "RF%s multiband radio found"
605 " (0x%x)\n",
400ec45a
LR		 606 ath5k_chip_name(AR5K_VERSION_RAD,
607 sc->ah->ah_radio_5ghz_revision),
608 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 609 }
610 }
400ec45a
LR		 611 /* Multi chip radio (RF5111 - RF2111) ->
612 * report both 2GHz/5GHz radios */
613 else if (sc->ah->ah_radio_5ghz_revision &&
614 sc->ah->ah_radio_2ghz_revision){
fa1c114f 615 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 616 ath5k_chip_name(AR5K_VERSION_RAD,
617 sc->ah->ah_radio_5ghz_revision),
618 sc->ah->ah_radio_5ghz_revision);
fa1c114f 619 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 620 ath5k_chip_name(AR5K_VERSION_RAD,
621 sc->ah->ah_radio_2ghz_revision),
622 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 623 }
624 }
625
626
627 /* ready to process interrupts */
628 __clear_bit(ATH_STAT_INVALID, sc->status);
629
630 return 0;
631err_ah:
632 ath5k_hw_detach(sc->ah);
633err_irq:
634 free_irq(pdev->irq, sc);
635err_free:
fa1c114f
JS		 636 ieee80211_free_hw(hw);
637err_map:
638 pci_iounmap(pdev, mem);
639err_reg:
640 pci_release_region(pdev, 0);
641err_dis:
642 pci_disable_device(pdev);
643err:
644 return ret;
645}
646
647static void __devexit
648ath5k_pci_remove(struct pci_dev *pdev)
649{
650 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
651 struct ath5k_softc *sc = hw->priv;
652
653 ath5k_debug_finish_device(sc);
654 ath5k_detach(pdev, hw);
655 ath5k_hw_detach(sc->ah);
656 free_irq(pdev->irq, sc);
fa1c114f
JS		 657 pci_iounmap(pdev, sc->iobase);
658 pci_release_region(pdev, 0);
659 pci_disable_device(pdev);
660 ieee80211_free_hw(hw);
661}
662
663#ifdef CONFIG_PM
664static int
665ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
666{
667 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
668 struct ath5k_softc *sc = hw->priv;
669
3a078876 670 ath5k_led_off(sc);
fa1c114f 671
3e4242b9 672 free_irq(pdev->irq, sc);
fa1c114f
JS		 673 pci_save_state(pdev);
674 pci_disable_device(pdev);
675 pci_set_power_state(pdev, PCI_D3hot);
676
677 return 0;
678}
679
680static int
681ath5k_pci_resume(struct pci_dev *pdev)
682{
683 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
684 struct ath5k_softc *sc = hw->priv;
bc1b32d6 685 int err;
fa1c114f 686
3e4242b9 687 pci_restore_state(pdev);
fa1c114f
JS		 688
689 err = pci_enable_device(pdev);
690 if (err)
691 return err;
692
fa1c114f
JS		 693 /*
694 * Suspend/Resume resets the PCI configuration space, so we have to
695 * re-disable the RETRY_TIMEOUT register (0x41) to keep
696 * PCI Tx retries from interfering with C3 CPU state
697 */
698 pci_write_config_byte(pdev, 0x41, 0);
699
3e4242b9
JS		 700 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
701 if (err) {
702 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 703 goto err_no_irq;
3e4242b9
JS		 704 }
705
3a078876 706 ath5k_led_enable(sc);
fa1c114f 707 return 0;
bb2becac 708
37465c8a 709err_no_irq:
3e4242b9
JS		 710 pci_disable_device(pdev);
711 return err;
fa1c114f
JS		 712}
713#endif /* CONFIG_PM */
714
715
fa1c114f
JS		 716/***********************\
717* Driver Initialization *
718\***********************/
719
720static int
721ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
722{
723 struct ath5k_softc *sc = hw->priv;
724 struct ath5k_hw *ah = sc->ah;
0e149cf5 725 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 726 int ret;
727
728 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
729
730 /*
731 * Check if the MAC has multi-rate retry support.
732 * We do this by trying to setup a fake extended
733 * descriptor. MAC's that don't have support will
734 * return false w/o doing anything. MAC's that do
735 * support it will return true w/o doing anything.
736 */
c6e387a2 737 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 738 if (ret < 0)
739 goto err;
740 if (ret > 0)
fa1c114f
JS		 741 __set_bit(ATH_STAT_MRRETRY, sc->status);
742
fa1c114f
JS		 743 /*
744 * Collect the channel list. The 802.11 layer
745 * is resposible for filtering this list based
746 * on settings like the phy mode and regulatory
747 * domain restrictions.
748 */
63266a65 749 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 750 if (ret) {
751 ATH5K_ERR(sc, "can't get channels\n");
752 goto err;
753 }
754
755 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 756 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
757 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 758 else
d8ee398d 759 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 760
761 /*
762 * Allocate tx+rx descriptors and populate the lists.
763 */
764 ret = ath5k_desc_alloc(sc, pdev);
765 if (ret) {
766 ATH5K_ERR(sc, "can't allocate descriptors\n");
767 goto err;
768 }
769
770 /*
771 * Allocate hardware transmit queues: one queue for
772 * beacon frames and one data queue for each QoS
773 * priority. Note that hw functions handle reseting
774 * these queues at the needed time.
775 */
776 ret = ath5k_beaconq_setup(ah);
777 if (ret < 0) {
778 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
779 goto err_desc;
780 }
781 sc->bhalq = ret;
782
783 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
784 if (IS_ERR(sc->txq)) {
785 ATH5K_ERR(sc, "can't setup xmit queue\n");
786 ret = PTR_ERR(sc->txq);
787 goto err_bhal;
788 }
789
790 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
791 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
792 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
acf3c1a5 793 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 794 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 795
0e149cf5
BC		 796 ret = ath5k_eeprom_read_mac(ah, mac);
797 if (ret) {
798 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
799 sc->pdev->device);
800 goto err_queues;
801 }
802
fa1c114f
JS		 803 SET_IEEE80211_PERM_ADDR(hw, mac);
804 /* All MAC address bits matter for ACKs */
805 memset(sc->bssidmask, 0xff, ETH_ALEN);
806 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
807
808 ret = ieee80211_register_hw(hw);
809 if (ret) {
810 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
811 goto err_queues;
812 }
813
3a078876
BC		 814 ath5k_init_leds(sc);
815
fa1c114f
JS		 816 return 0;
817err_queues:
818 ath5k_txq_release(sc);
819err_bhal:
820 ath5k_hw_release_tx_queue(ah, sc->bhalq);
821err_desc:
822 ath5k_desc_free(sc, pdev);
823err:
824 return ret;
825}
826
827static void
828ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
829{
830 struct ath5k_softc *sc = hw->priv;
831
832 /*
833 * NB: the order of these is important:
834 * o call the 802.11 layer before detaching ath5k_hw to
835 * insure callbacks into the driver to delete global
836 * key cache entries can be handled
837 * o reclaim the tx queue data structures after calling
838 * the 802.11 layer as we'll get called back to reclaim
839 * node state and potentially want to use them
840 * o to cleanup the tx queues the hal is called, so detach
841 * it last
842 * XXX: ??? detach ath5k_hw ???
843 * Other than that, it's straightforward...
844 */
845 ieee80211_unregister_hw(hw);
846 ath5k_desc_free(sc, pdev);
847 ath5k_txq_release(sc);
848 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 849 ath5k_unregister_leds(sc);
fa1c114f
JS		 850
851 /*
852 * NB: can't reclaim these until after ieee80211_ifdetach
853 * returns because we'll get called back to reclaim node
854 * state and potentially want to use them.
855 */
856}
857
858
859
860
861/********************\
862* Channel/mode setup *
863\********************/
864
865/*
866 * Convert IEEE channel number to MHz frequency.
867 */
868static inline short
869ath5k_ieee2mhz(short chan)
870{
871 if (chan <= 14 || chan >= 27)
872 return ieee80211chan2mhz(chan);
873 else
874 return 2212 + chan * 20;
875}
876
fa1c114f
JS		 877static unsigned int
878ath5k_copy_channels(struct ath5k_hw *ah,
879 struct ieee80211_channel *channels,
880 unsigned int mode,
881 unsigned int max)
882{
d8ee398d 883 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 884
885 if (!test_bit(mode, ah->ah_modes))
886 return 0;
887
fa1c114f 888 switch (mode) {
d8ee398d
LR		 889 case AR5K_MODE_11A:
890 case AR5K_MODE_11A_TURBO:
fa1c114f 891 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 892 size = 220 ;
fa1c114f
JS		 893 chfreq = CHANNEL_5GHZ;
894 break;
d8ee398d
LR		 895 case AR5K_MODE_11B:
896 case AR5K_MODE_11G:
897 case AR5K_MODE_11G_TURBO:
898 size = 26;
fa1c114f
JS		 899 chfreq = CHANNEL_2GHZ;
900 break;
901 default:
902 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
903 return 0;
904 }
905
906 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 907 ch = i + 1 ;
908 freq = ath5k_ieee2mhz(ch);
fa1c114f 909
d8ee398d
LR		 910 /* Check if channel is supported by the chipset */
911 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 912 continue;
913
d8ee398d
LR		 914 /* Write channel info and increment counter */
915 channels[count].center_freq = freq;
a3f4b914
LR		 916 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
917 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 918 switch (mode) {
919 case AR5K_MODE_11A:
920 case AR5K_MODE_11G:
921 channels[count].hw_value = chfreq | CHANNEL_OFDM;
922 break;
923 case AR5K_MODE_11A_TURBO:
924 case AR5K_MODE_11G_TURBO:
925 channels[count].hw_value = chfreq |
926 CHANNEL_OFDM | CHANNEL_TURBO;
927 break;
928 case AR5K_MODE_11B:
d8ee398d
LR		 929 channels[count].hw_value = CHANNEL_B;
930 }
fa1c114f 931
fa1c114f
JS		 932 count++;
933 max--;
934 }
935
936 return count;
937}
938
63266a65
BR		 939static void
940ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
941{
942 u8 i;
943
944 for (i = 0; i < AR5K_MAX_RATES; i++)
945 sc->rate_idx[b->band][i] = -1;
946
947 for (i = 0; i < b->n_bitrates; i++) {
948 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
949 if (b->bitrates[i].hw_value_short)
950 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
951 }
952}
953
d8ee398d 954static int
63266a65 955ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 956{
957 struct ath5k_softc *sc = hw->priv;
d8ee398d 958 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 959 struct ieee80211_supported_band *sband;
960 int max_c, count_c = 0;
961 int i;
fa1c114f 962
d8ee398d 963 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 964 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 965
966 /* 2GHz band */
63266a65
BR		 967 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
968 sband->band = IEEE80211_BAND_2GHZ;
969 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 970
63266a65
BR		 971 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
972 /* G mode */
973 memcpy(sband->bitrates, &ath5k_rates[0],
974 sizeof(struct ieee80211_rate) * 12);
975 sband->n_bitrates = 12;
fa1c114f 976
d8ee398d 977 sband->channels = sc->channels;
d8ee398d 978 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 979 AR5K_MODE_11G, max_c);
fa1c114f 980
63266a65 981 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 982 count_c = sband->n_channels;
63266a65
BR		 983 max_c -= count_c;
984 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
985 /* B mode */
986 memcpy(sband->bitrates, &ath5k_rates[0],
987 sizeof(struct ieee80211_rate) * 4);
988 sband->n_bitrates = 4;
989
990 /* 5211 only supports B rates and uses 4bit rate codes
991 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
992 * fix them up here:
993 */
994 if (ah->ah_version == AR5K_AR5211) {
995 for (i = 0; i < 4; i++) {
996 sband->bitrates[i].hw_value =
997 sband->bitrates[i].hw_value & 0xF;
998 sband->bitrates[i].hw_value_short =
999 sband->bitrates[i].hw_value_short & 0xF;
1000 }
1001 }
fa1c114f 1002
63266a65
BR		 1003 sband->channels = sc->channels;
1004 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1005 AR5K_MODE_11B, max_c);
d8ee398d 1006
63266a65
BR		 1007 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1008 count_c = sband->n_channels;
d8ee398d 1009 max_c -= count_c;
fa1c114f 1010 }
63266a65 1011 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1012
63266a65 1013 /* 5GHz band, A mode */
400ec45a 1014 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1015 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1016 sband->band = IEEE80211_BAND_5GHZ;
1017 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1018
63266a65
BR		 1019 memcpy(sband->bitrates, &ath5k_rates[4],
1020 sizeof(struct ieee80211_rate) * 8);
1021 sband->n_bitrates = 8;
fa1c114f 1022
63266a65 1023 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1024 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1025 AR5K_MODE_11A, max_c);
1026
d8ee398d
LR		 1027 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1028 }
63266a65 1029 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1030
b446197c 1031 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1032
1033 return 0;
fa1c114f
JS		 1034}
1035
1036/*
1037 * Set/change channels. If the channel is really being changed,
1038 * it's done by reseting the chip. To accomplish this we must
1039 * first cleanup any pending DMA, then restart stuff after a la
1040 * ath5k_init.
be009370
BC		 1041 *
1042 * Called with sc->lock.
fa1c114f
JS		 1043 */
1044static int
1045ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1046{
d8ee398d
LR		 1047 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1048 sc->curchan->center_freq, chan->center_freq);
1049
1050 if (chan->center_freq != sc->curchan->center_freq ||
1051 chan->hw_value != sc->curchan->hw_value) {
1052
1053 sc->curchan = chan;
1054 sc->curband = &sc->sbands[chan->band];
fa1c114f 1055
fa1c114f
JS		 1056 /*
1057 * To switch channels clear any pending DMA operations;
1058 * wait long enough for the RX fifo to drain, reset the
1059 * hardware at the new frequency, and then re-enable
1060 * the relevant bits of the h/w.
1061 */
d7dc1003 1062 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1063 }
1064
1065 return 0;
1066}
1067
1068static void
1069ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1070{
fa1c114f 1071 sc->curmode = mode;
d8ee398d 1072
400ec45a 1073 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1074 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1075 } else {
1076 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1077 }
fa1c114f
JS		 1078}
1079
1080static void
1081ath5k_mode_setup(struct ath5k_softc *sc)
1082{
1083 struct ath5k_hw *ah = sc->ah;
1084 u32 rfilt;
1085
1086 /* configure rx filter */
1087 rfilt = sc->filter_flags;
1088 ath5k_hw_set_rx_filter(ah, rfilt);
1089
1090 if (ath5k_hw_hasbssidmask(ah))
1091 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1092
1093 /* configure operational mode */
1094 ath5k_hw_set_opmode(ah);
1095
1096 ath5k_hw_set_mcast_filter(ah, 0, 0);
1097 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1098}
1099
d8ee398d 1100static inline int
63266a65
BR		 1101ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1102{
db5b4f7a
JS		 1103 WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1104 "hw_rix out of bounds: %x\n", hw_rix);
63266a65 1105 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1106}
1107
fa1c114f
JS		 1108/***************\
1109* Buffers setup *
1110\***************/
1111
b6ea0356
BC		 1112static
1113struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1114{
1115 struct sk_buff *skb;
1116 unsigned int off;
1117
1118 /*
1119 * Allocate buffer with headroom_needed space for the
1120 * fake physical layer header at the start.
1121 */
1122 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1123
1124 if (!skb) {
1125 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1126 sc->rxbufsize + sc->cachelsz - 1);
1127 return NULL;
1128 }
1129 /*
1130 * Cache-line-align. This is important (for the
1131 * 5210 at least) as not doing so causes bogus data
1132 * in rx'd frames.
1133 */
1134 off = ((unsigned long)skb->data) % sc->cachelsz;
1135 if (off != 0)
1136 skb_reserve(skb, sc->cachelsz - off);
1137
1138 *skb_addr = pci_map_single(sc->pdev,
1139 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1140 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1141 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1142 dev_kfree_skb(skb);
1143 return NULL;
1144 }
1145 return skb;
1146}
1147
fa1c114f
JS		 1148static int
1149ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1150{
1151 struct ath5k_hw *ah = sc->ah;
1152 struct sk_buff *skb = bf->skb;
1153 struct ath5k_desc *ds;
1154
b6ea0356
BC		 1155 if (!skb) {
1156 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1157 if (!skb)
fa1c114f 1158 return -ENOMEM;
fa1c114f 1159 bf->skb = skb;
fa1c114f
JS		 1160 }
1161
1162 /*
1163 * Setup descriptors. For receive we always terminate
1164 * the descriptor list with a self-linked entry so we'll
1165 * not get overrun under high load (as can happen with a
1166 * 5212 when ANI processing enables PHY error frames).
1167 *
1168 * To insure the last descriptor is self-linked we create
1169 * each descriptor as self-linked and add it to the end. As
1170 * each additional descriptor is added the previous self-linked
1171 * entry is ``fixed'' naturally. This should be safe even
1172 * if DMA is happening. When processing RX interrupts we
1173 * never remove/process the last, self-linked, entry on the
1174 * descriptor list. This insures the hardware always has
1175 * someplace to write a new frame.
1176 */
1177 ds = bf->desc;
1178 ds->ds_link = bf->daddr; /* link to self */
1179 ds->ds_data = bf->skbaddr;
c6e387a2 1180 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1181 skb_tailroom(skb), /* buffer size */
1182 0);
1183
1184 if (sc->rxlink != NULL)
1185 *sc->rxlink = bf->daddr;
1186 sc->rxlink = &ds->ds_link;
1187 return 0;
1188}
1189
1190static int
e039fa4a 1191ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1192{
1193 struct ath5k_hw *ah = sc->ah;
1194 struct ath5k_txq *txq = sc->txq;
1195 struct ath5k_desc *ds = bf->desc;
1196 struct sk_buff *skb = bf->skb;
a888d52d 1197 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1198 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1199 struct ieee80211_rate *rate;
1200 unsigned int mrr_rate[3], mrr_tries[3];
1201 int i, ret;
8902ff4e 1202 u16 hw_rate;
07c1e852
BC		 1203 u16 cts_rate = 0;
1204 u16 duration = 0;
8902ff4e 1205 u8 rc_flags;
fa1c114f
JS		 1206
1207 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1208
fa1c114f
JS		 1209 /* XXX endianness */
1210 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1211 PCI_DMA_TODEVICE);
1212
8902ff4e
BC		 1213 rate = ieee80211_get_tx_rate(sc->hw, info);
1214
e039fa4a 1215 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1216 flags |= AR5K_TXDESC_NOACK;
1217
8902ff4e
BC		 1218 rc_flags = info->control.rates[0].flags;
1219 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1220 rate->hw_value_short : rate->hw_value;
1221
281c56dd 1222 pktlen = skb->len;
fa1c114f 1223
362695e1
BC		 1224 if (info->control.hw_key) {
1225 keyidx = info->control.hw_key->hw_key_idx;
1226 pktlen += info->control.hw_key->icv_len;
1227 }
07c1e852
BC		 1228 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1229 flags |= AR5K_TXDESC_RTSENA;
1230 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1231 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1232 sc->vif, pktlen, info));
1233 }
1234 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1235 flags |= AR5K_TXDESC_CTSENA;
1236 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1237 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1238 sc->vif, pktlen, info));
1239 }
fa1c114f
JS		 1240 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1241 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1242 (sc->power_level * 2),
8902ff4e 1243 hw_rate,
07c1e852
BC		 1244 info->control.rates[0].count, keyidx, 0, flags,
1245 cts_rate, duration);
fa1c114f
JS		 1246 if (ret)
1247 goto err_unmap;
1248
2f7fe870
FF		 1249 memset(mrr_rate, 0, sizeof(mrr_rate));
1250 memset(mrr_tries, 0, sizeof(mrr_tries));
1251 for (i = 0; i < 3; i++) {
1252 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1253 if (!rate)
1254 break;
1255
1256 mrr_rate[i] = rate->hw_value;
e6a9854b 1257 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1258 }
1259
1260 ah->ah_setup_mrr_tx_desc(ah, ds,
1261 mrr_rate[0], mrr_tries[0],
1262 mrr_rate[1], mrr_tries[1],
1263 mrr_rate[2], mrr_tries[2]);
1264
fa1c114f
JS		 1265 ds->ds_link = 0;
1266 ds->ds_data = bf->skbaddr;
1267
1268 spin_lock_bh(&txq->lock);
1269 list_add_tail(&bf->list, &txq->q);
57ffc589 1270 sc->tx_stats[txq->qnum].len++;
fa1c114f 1271 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1272 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1273 else /* no, so only link it */
1274 *txq->link = bf->daddr;
1275
1276 txq->link = &ds->ds_link;
c6e387a2 1277 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1278 mmiowb();
fa1c114f
JS		 1279 spin_unlock_bh(&txq->lock);
1280
1281 return 0;
1282err_unmap:
1283 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1284 return ret;
1285}
1286
1287/*******************\
1288* Descriptors setup *
1289\*******************/
1290
1291static int
1292ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1293{
1294 struct ath5k_desc *ds;
1295 struct ath5k_buf *bf;
1296 dma_addr_t da;
1297 unsigned int i;
1298 int ret;
1299
1300 /* allocate descriptors */
1301 sc->desc_len = sizeof(struct ath5k_desc) *
1302 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1303 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1304 if (sc->desc == NULL) {
1305 ATH5K_ERR(sc, "can't allocate descriptors\n");
1306 ret = -ENOMEM;
1307 goto err;
1308 }
1309 ds = sc->desc;
1310 da = sc->desc_daddr;
1311 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1312 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1313
1314 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1315 sizeof(struct ath5k_buf), GFP_KERNEL);
1316 if (bf == NULL) {
1317 ATH5K_ERR(sc, "can't allocate bufptr\n");
1318 ret = -ENOMEM;
1319 goto err_free;
1320 }
1321 sc->bufptr = bf;
1322
1323 INIT_LIST_HEAD(&sc->rxbuf);
1324 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1325 bf->desc = ds;
1326 bf->daddr = da;
1327 list_add_tail(&bf->list, &sc->rxbuf);
1328 }
1329
1330 INIT_LIST_HEAD(&sc->txbuf);
1331 sc->txbuf_len = ATH_TXBUF;
1332 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1333 da += sizeof(*ds)) {
1334 bf->desc = ds;
1335 bf->daddr = da;
1336 list_add_tail(&bf->list, &sc->txbuf);
1337 }
1338
1339 /* beacon buffer */
1340 bf->desc = ds;
1341 bf->daddr = da;
1342 sc->bbuf = bf;
1343
1344 return 0;
1345err_free:
1346 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1347err:
1348 sc->desc = NULL;
1349 return ret;
1350}
1351
1352static void
1353ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1354{
1355 struct ath5k_buf *bf;
1356
1357 ath5k_txbuf_free(sc, sc->bbuf);
1358 list_for_each_entry(bf, &sc->txbuf, list)
1359 ath5k_txbuf_free(sc, bf);
1360 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1361 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1362
1363 /* Free memory associated with all descriptors */
1364 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1365
1366 kfree(sc->bufptr);
1367 sc->bufptr = NULL;
1368}
1369
1370
1371
1372
1373
1374/**************\
1375* Queues setup *
1376\**************/
1377
1378static struct ath5k_txq *
1379ath5k_txq_setup(struct ath5k_softc *sc,
1380 int qtype, int subtype)
1381{
1382 struct ath5k_hw *ah = sc->ah;
1383 struct ath5k_txq *txq;
1384 struct ath5k_txq_info qi = {
1385 .tqi_subtype = subtype,
1386 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1387 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1388 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1389 };
1390 int qnum;
1391
1392 /*
1393 * Enable interrupts only for EOL and DESC conditions.
1394 * We mark tx descriptors to receive a DESC interrupt
1395 * when a tx queue gets deep; otherwise waiting for the
1396 * EOL to reap descriptors. Note that this is done to
1397 * reduce interrupt load and this only defers reaping
1398 * descriptors, never transmitting frames. Aside from
1399 * reducing interrupts this also permits more concurrency.
1400 * The only potential downside is if the tx queue backs
1401 * up in which case the top half of the kernel may backup
1402 * due to a lack of tx descriptors.
1403 */
1404 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1405 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1406 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1407 if (qnum < 0) {
1408 /*
1409 * NB: don't print a message, this happens
1410 * normally on parts with too few tx queues
1411 */
1412 return ERR_PTR(qnum);
1413 }
1414 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1415 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1416 qnum, ARRAY_SIZE(sc->txqs));
1417 ath5k_hw_release_tx_queue(ah, qnum);
1418 return ERR_PTR(-EINVAL);
1419 }
1420 txq = &sc->txqs[qnum];
1421 if (!txq->setup) {
1422 txq->qnum = qnum;
1423 txq->link = NULL;
1424 INIT_LIST_HEAD(&txq->q);
1425 spin_lock_init(&txq->lock);
1426 txq->setup = true;
1427 }
1428 return &sc->txqs[qnum];
1429}
1430
1431static int
1432ath5k_beaconq_setup(struct ath5k_hw *ah)
1433{
1434 struct ath5k_txq_info qi = {
1435 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1436 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1437 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1438 /* NB: for dynamic turbo, don't enable any other interrupts */
1439 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1440 };
1441
1442 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1443}
1444
1445static int
1446ath5k_beaconq_config(struct ath5k_softc *sc)
1447{
1448 struct ath5k_hw *ah = sc->ah;
1449 struct ath5k_txq_info qi;
1450 int ret;
1451
1452 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1453 if (ret)
1454 return ret;
05c914fe
JB		 1455 if (sc->opmode == NL80211_IFTYPE_AP ||
1456 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1457 /*
1458 * Always burst out beacon and CAB traffic
1459 * (aifs = cwmin = cwmax = 0)
1460 */
1461 qi.tqi_aifs = 0;
1462 qi.tqi_cw_min = 0;
1463 qi.tqi_cw_max = 0;
05c914fe 1464 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1465 /*
1466 * Adhoc mode; backoff between 0 and (2 * cw_min).
1467 */
1468 qi.tqi_aifs = 0;
1469 qi.tqi_cw_min = 0;
1470 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1471 }
1472
6d91e1d8
BR		 1473 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1474 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1475 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1476
c6e387a2 1477 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1478 if (ret) {
1479 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1480 "hardware queue!\n", __func__);
1481 return ret;
1482 }
1483
1484 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1485}
1486
1487static void
1488ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1489{
1490 struct ath5k_buf *bf, *bf0;
1491
1492 /*
1493 * NB: this assumes output has been stopped and
1494 * we do not need to block ath5k_tx_tasklet
1495 */
1496 spin_lock_bh(&txq->lock);
1497 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1498 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1499
1500 ath5k_txbuf_free(sc, bf);
1501
1502 spin_lock_bh(&sc->txbuflock);
57ffc589 1503 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1504 list_move_tail(&bf->list, &sc->txbuf);
1505 sc->txbuf_len++;
1506 spin_unlock_bh(&sc->txbuflock);
1507 }
1508 txq->link = NULL;
1509 spin_unlock_bh(&txq->lock);
1510}
1511
1512/*
1513 * Drain the transmit queues and reclaim resources.
1514 */
1515static void
1516ath5k_txq_cleanup(struct ath5k_softc *sc)
1517{
1518 struct ath5k_hw *ah = sc->ah;
1519 unsigned int i;
1520
1521 /* XXX return value */
1522 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1523 /* don't touch the hardware if marked invalid */
1524 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1525 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1526 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1527 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1528 if (sc->txqs[i].setup) {
1529 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1530 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1531 "link %p\n",
1532 sc->txqs[i].qnum,
c6e387a2 1533 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1534 sc->txqs[i].qnum),
1535 sc->txqs[i].link);
1536 }
1537 }
36d6825b 1538 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1539
1540 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1541 if (sc->txqs[i].setup)
1542 ath5k_txq_drainq(sc, &sc->txqs[i]);
1543}
1544
1545static void
1546ath5k_txq_release(struct ath5k_softc *sc)
1547{
1548 struct ath5k_txq *txq = sc->txqs;
1549 unsigned int i;
1550
1551 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1552 if (txq->setup) {
1553 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1554 txq->setup = false;
1555 }
1556}
1557
1558
1559
1560
1561/*************\
1562* RX Handling *
1563\*************/
1564
1565/*
1566 * Enable the receive h/w following a reset.
1567 */
1568static int
1569ath5k_rx_start(struct ath5k_softc *sc)
1570{
1571 struct ath5k_hw *ah = sc->ah;
1572 struct ath5k_buf *bf;
1573 int ret;
1574
1575 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1576
1577 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1578 sc->cachelsz, sc->rxbufsize);
1579
1580 sc->rxlink = NULL;
1581
1582 spin_lock_bh(&sc->rxbuflock);
1583 list_for_each_entry(bf, &sc->rxbuf, list) {
1584 ret = ath5k_rxbuf_setup(sc, bf);
1585 if (ret != 0) {
1586 spin_unlock_bh(&sc->rxbuflock);
1587 goto err;
1588 }
1589 }
1590 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1591 spin_unlock_bh(&sc->rxbuflock);
1592
c6e387a2
NK		 1593 ath5k_hw_set_rxdp(ah, bf->daddr);
1594 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1595 ath5k_mode_setup(sc); /* set filters, etc. */
1596 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1597
1598 return 0;
1599err:
1600 return ret;
1601}
1602
1603/*
1604 * Disable the receive h/w in preparation for a reset.
1605 */
1606static void
1607ath5k_rx_stop(struct ath5k_softc *sc)
1608{
1609 struct ath5k_hw *ah = sc->ah;
1610
c6e387a2 1611 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1612 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1613 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1614
1615 ath5k_debug_printrxbuffs(sc, ah);
1616
1617 sc->rxlink = NULL; /* just in case */
1618}
1619
1620static unsigned int
1621ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1622 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1623{
1624 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1625 unsigned int keyix, hlen;
fa1c114f 1626
b47f407b
BR		 1627 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1628 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1629 return RX_FLAG_DECRYPTED;
1630
1631 /* Apparently when a default key is used to decrypt the packet
1632 the hw does not set the index used to decrypt. In such cases
1633 get the index from the packet. */
798ee985 1634 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1635 if (ieee80211_has_protected(hdr->frame_control) &&
1636 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1637 skb->len >= hlen + 4) {
fa1c114f
JS		 1638 keyix = skb->data[hlen + 3] >> 6;
1639
1640 if (test_bit(keyix, sc->keymap))
1641 return RX_FLAG_DECRYPTED;
1642 }
1643
1644 return 0;
1645}
1646
036cd1ec
BR		 1647
1648static void
6ba81c2c
BR		 1649ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1650 struct ieee80211_rx_status *rxs)
036cd1ec 1651{
6ba81c2c 1652 u64 tsf, bc_tstamp;
036cd1ec
BR		 1653 u32 hw_tu;
1654 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1655
24b56e70 1656 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1657 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1658 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1659 /*
6ba81c2c
BR		 1660 * Received an IBSS beacon with the same BSSID. Hardware *must*
1661 * have updated the local TSF. We have to work around various
1662 * hardware bugs, though...
036cd1ec 1663 */
6ba81c2c
BR		 1664 tsf = ath5k_hw_get_tsf64(sc->ah);
1665 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1666 hw_tu = TSF_TO_TU(tsf);
1667
1668 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1669 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1670 (unsigned long long)bc_tstamp,
1671 (unsigned long long)rxs->mactime,
1672 (unsigned long long)(rxs->mactime - bc_tstamp),
1673 (unsigned long long)tsf);
6ba81c2c
BR		 1674
1675 /*
1676 * Sometimes the HW will give us a wrong tstamp in the rx
1677 * status, causing the timestamp extension to go wrong.
1678 * (This seems to happen especially with beacon frames bigger
1679 * than 78 byte (incl. FCS))
1680 * But we know that the receive timestamp must be later than the
1681 * timestamp of the beacon since HW must have synced to that.
1682 *
1683 * NOTE: here we assume mactime to be after the frame was
1684 * received, not like mac80211 which defines it at the start.
1685 */
1686 if (bc_tstamp > rxs->mactime) {
036cd1ec 1687 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1688 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1689 (unsigned long long)rxs->mactime,
1690 (unsigned long long)tsf);
6ba81c2c 1691 rxs->mactime = tsf;
036cd1ec 1692 }
6ba81c2c
BR		 1693
1694 /*
1695 * Local TSF might have moved higher than our beacon timers,
1696 * in that case we have to update them to continue sending
1697 * beacons. This also takes care of synchronizing beacon sending
1698 * times with other stations.
1699 */
1700 if (hw_tu >= sc->nexttbtt)
1701 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1702 }
1703}
1704
acf3c1a5
BC		 1705static void ath5k_tasklet_beacon(unsigned long data)
1706{
1707 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1708
1709 /*
1710 * Software beacon alert--time to send a beacon.
1711 *
1712 * In IBSS mode we use this interrupt just to
1713 * keep track of the next TBTT (target beacon
1714 * transmission time) in order to detect wether
1715 * automatic TSF updates happened.
1716 */
1717 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1718 /* XXX: only if VEOL suppported */
1719 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1720 sc->nexttbtt += sc->bintval;
1721 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1722 "SWBA nexttbtt: %x hw_tu: %x "
1723 "TSF: %llx\n",
1724 sc->nexttbtt,
1725 TSF_TO_TU(tsf),
1726 (unsigned long long) tsf);
1727 } else {
1728 spin_lock(&sc->block);
1729 ath5k_beacon_send(sc);
1730 spin_unlock(&sc->block);
1731 }
1732}
1733
fa1c114f
JS		 1734static void
1735ath5k_tasklet_rx(unsigned long data)
1736{
1737 struct ieee80211_rx_status rxs = {};
b47f407b 1738 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1739 struct sk_buff *skb, *next_skb;
1740 dma_addr_t next_skb_addr;
fa1c114f 1741 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1742 struct ath5k_buf *bf, *bf_last;
fa1c114f 1743 struct ath5k_desc *ds;
fa1c114f
JS		 1744 int ret;
1745 int hdrlen;
0fe45b1d 1746 int padsize;
fa1c114f
JS		 1747
1748 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1749 if (list_empty(&sc->rxbuf)) {
1750 ATH5K_WARN(sc, "empty rx buf pool\n");
1751 goto unlock;
1752 }
1753 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1754 do {
d6894b5b
BC		 1755 rxs.flag = 0;
1756
fa1c114f
JS		 1757 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1758 BUG_ON(bf->skb == NULL);
1759 skb = bf->skb;
1760 ds = bf->desc;
1761
3a0f2c87
JS		 1762 /*
1763 * last buffer must not be freed to ensure proper hardware
1764 * function. When the hardware finishes also a packet next to
1765 * it, we are sure, it doesn't use it anymore and we can go on.
1766 */
1767 if (bf_last == bf)
1768 bf->flags |= 1;
1769 if (bf->flags) {
1770 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1771 struct ath5k_buf, list);
1772 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1773 &rs);
1774 if (ret)
1775 break;
1776 bf->flags &= ~1;
1777 /* skip the overwritten one (even status is martian) */
1778 goto next;
1779 }
fa1c114f 1780
b47f407b 1781 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1782 if (unlikely(ret == -EINPROGRESS))
1783 break;
1784 else if (unlikely(ret)) {
1785 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1786 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1787 return;
1788 }
1789
b47f407b 1790 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1791 ATH5K_WARN(sc, "unsupported jumbo\n");
1792 goto next;
1793 }
1794
b47f407b
BR		 1795 if (unlikely(rs.rs_status)) {
1796 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1797 goto next;
b47f407b 1798 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1799 /*
1800 * Decrypt error. If the error occurred
1801 * because there was no hardware key, then
1802 * let the frame through so the upper layers
1803 * can process it. This is necessary for 5210
1804 * parts which have no way to setup a ``clear''
1805 * key cache entry.
1806 *
1807 * XXX do key cache faulting
1808 */
b47f407b
BR		 1809 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1810 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1811 goto accept;
1812 }
b47f407b 1813 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1814 rxs.flag |= RX_FLAG_MMIC_ERROR;
1815 goto accept;
1816 }
1817
1818 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1819 if ((rs.rs_status &
1820 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1821 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1822 goto next;
1823 }
1824accept:
b6ea0356
BC		 1825 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1826
1827 /*
1828 * If we can't replace bf->skb with a new skb under memory
1829 * pressure, just skip this packet
1830 */
1831 if (!next_skb)
1832 goto next;
1833
fa1c114f
JS		 1834 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1835 PCI_DMA_FROMDEVICE);
b47f407b 1836 skb_put(skb, rs.rs_datalen);
fa1c114f 1837
0fe45b1d
BP		 1838 /* The MAC header is padded to have 32-bit boundary if the
1839 * packet payload is non-zero. The general calculation for
1840 * padsize would take into account odd header lengths:
1841 * padsize = (4 - hdrlen % 4) % 4; However, since only
1842 * even-length headers are used, padding can only be 0 or 2
1843 * bytes and we can optimize this a bit. In addition, we must
1844 * not try to remove padding from short control frames that do
1845 * not have payload. */
fa1c114f 1846 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1847 padsize = ath5k_pad_size(hdrlen);
1848 if (padsize) {
0fe45b1d
BP		 1849 memmove(skb->data + padsize, skb->data, hdrlen);
1850 skb_pull(skb, padsize);
fa1c114f
JS		 1851 }
1852
c0e1899b
BR		 1853 /*
1854 * always extend the mac timestamp, since this information is
1855 * also needed for proper IBSS merging.
1856 *
1857 * XXX: it might be too late to do it here, since rs_tstamp is
1858 * 15bit only. that means TSF extension has to be done within
1859 * 32768usec (about 32ms). it might be necessary to move this to
1860 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1861 *
1862 * Unfortunately we don't know when the hardware takes the rx
1863 * timestamp (beginning of phy frame, data frame, end of rx?).
1864 * The only thing we know is that it is hardware specific...
1865 * On AR5213 it seems the rx timestamp is at the end of the
1866 * frame, but i'm not sure.
1867 *
1868 * NOTE: mac80211 defines mactime at the beginning of the first
1869 * data symbol. Since we don't have any time references it's
1870 * impossible to comply to that. This affects IBSS merge only
1871 * right now, so it's not too bad...
c0e1899b 1872 */
b47f407b 1873 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1874 rxs.flag |= RX_FLAG_TSFT;
1875
d8ee398d
LR		 1876 rxs.freq = sc->curchan->center_freq;
1877 rxs.band = sc->curband->band;
fa1c114f 1878
fa1c114f 1879 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1880 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1881
1882 /* An rssi of 35 indicates you should be able use
1883 * 54 Mbps reliably. A more elaborate scheme can be used
1884 * here but it requires a map of SNR/throughput for each
1885 * possible mode used */
1886 rxs.qual = rs.rs_rssi * 100 / 35;
1887
1888 /* rssi can be more than 35 though, anything above that
1889 * should be considered at 100% */
1890 if (rxs.qual > 100)
1891 rxs.qual = 100;
fa1c114f 1892
b47f407b
BR		 1893 rxs.antenna = rs.rs_antenna;
1894 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1895 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1896
06303352
BR		 1897 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1898 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1899 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1900
fa1c114f
JS		 1901 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1902
036cd1ec 1903 /* check beacons in IBSS mode */
05c914fe 1904 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1905 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1906
fa1c114f 1907 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1908
1909 bf->skb = next_skb;
1910 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1911next:
1912 list_move_tail(&bf->list, &sc->rxbuf);
1913 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1914unlock:
fa1c114f
JS		 1915 spin_unlock(&sc->rxbuflock);
1916}
1917
1918
1919
1920
1921/*************\
1922* TX Handling *
1923\*************/
1924
1925static void
1926ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1927{
b47f407b 1928 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1929 struct ath5k_buf *bf, *bf0;
1930 struct ath5k_desc *ds;
1931 struct sk_buff *skb;
e039fa4a 1932 struct ieee80211_tx_info *info;
2f7fe870 1933 int i, ret;
fa1c114f
JS		 1934
1935 spin_lock(&txq->lock);
1936 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1937 ds = bf->desc;
1938
b47f407b 1939 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1940 if (unlikely(ret == -EINPROGRESS))
1941 break;
1942 else if (unlikely(ret)) {
1943 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1944 ret, txq->qnum);
1945 break;
1946 }
1947
1948 skb = bf->skb;
a888d52d 1949 info = IEEE80211_SKB_CB(skb);
fa1c114f 1950 bf->skb = NULL;
e039fa4a 1951
fa1c114f
JS		 1952 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1953 PCI_DMA_TODEVICE);
1954
e6a9854b 1955 ieee80211_tx_info_clear_status(info);
2f7fe870 1956 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1957 struct ieee80211_tx_rate *r =
1958 &info->status.rates[i];
2f7fe870
FF		 1959
1960 if (ts.ts_rate[i]) {
e6a9854b
JB		 1961 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1962 r->count = ts.ts_retry[i];
2f7fe870 1963 } else {
e6a9854b
JB		 1964 r->idx = -1;
1965 r->count = 0;
2f7fe870
FF		 1966 }
1967 }
1968
e6a9854b
JB		 1969 /* count the successful attempt as well */
1970 info->status.rates[ts.ts_final_idx].count++;
1971
b47f407b 1972 if (unlikely(ts.ts_status)) {
fa1c114f 1973 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1974 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1975 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1976 } else {
e039fa4a
JB		 1977 info->flags |= IEEE80211_TX_STAT_ACK;
1978 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1979 }
1980
e039fa4a 1981 ieee80211_tx_status(sc->hw, skb);
57ffc589 1982 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1983
1984 spin_lock(&sc->txbuflock);
57ffc589 1985 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1986 list_move_tail(&bf->list, &sc->txbuf);
1987 sc->txbuf_len++;
1988 spin_unlock(&sc->txbuflock);
1989 }
1990 if (likely(list_empty(&txq->q)))
1991 txq->link = NULL;
1992 spin_unlock(&txq->lock);
1993 if (sc->txbuf_len > ATH_TXBUF / 5)
1994 ieee80211_wake_queues(sc->hw);
1995}
1996
1997static void
1998ath5k_tasklet_tx(unsigned long data)
1999{
2000 struct ath5k_softc *sc = (void *)data;
2001
2002 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 2003}
2004
2005
fa1c114f
JS		 2006/*****************\
2007* Beacon handling *
2008\*****************/
2009
2010/*
2011 * Setup the beacon frame for transmit.
2012 */
2013static int
e039fa4a 2014ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2015{
2016 struct sk_buff *skb = bf->skb;
a888d52d 2017 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2018 struct ath5k_hw *ah = sc->ah;
2019 struct ath5k_desc *ds;
2020 int ret, antenna = 0;
2021 u32 flags;
2022
2023 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2024 PCI_DMA_TODEVICE);
2025 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2026 "skbaddr %llx\n", skb, skb->data, skb->len,
2027 (unsigned long long)bf->skbaddr);
8d8bb39b 2028 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2029 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2030 return -EIO;
2031 }
2032
2033 ds = bf->desc;
2034
2035 flags = AR5K_TXDESC_NOACK;
05c914fe 2036 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2037 ds->ds_link = bf->daddr; /* self-linked */
2038 flags |= AR5K_TXDESC_VEOL;
2039 /*
2040 * Let hardware handle antenna switching if txantenna is not set
2041 */
2042 } else {
2043 ds->ds_link = 0;
2044 /*
2045 * Switch antenna every 4 beacons if txantenna is not set
2046 * XXX assumes two antennas
2047 */
2048 if (antenna == 0)
2049 antenna = sc->bsent & 4 ? 2 : 1;
2050 }
2051
2052 ds->ds_data = bf->skbaddr;
281c56dd 2053 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2054 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2055 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2056 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2057 1, AR5K_TXKEYIX_INVALID,
400ec45a 2058 antenna, flags, 0, 0);
fa1c114f
JS		 2059 if (ret)
2060 goto err_unmap;
2061
2062 return 0;
2063err_unmap:
2064 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2065 return ret;
2066}
2067
2068/*
2069 * Transmit a beacon frame at SWBA. Dynamic updates to the
2070 * frame contents are done as needed and the slot time is
2071 * also adjusted based on current state.
2072 *
acf3c1a5
BC		 2073 * This is called from software irq context (beacontq or restq
2074 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2075 */
2076static void
2077ath5k_beacon_send(struct ath5k_softc *sc)
2078{
2079 struct ath5k_buf *bf = sc->bbuf;
2080 struct ath5k_hw *ah = sc->ah;
2081
be9b7259 2082 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2083
05c914fe
JB		 2084 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2085 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2086 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2087 return;
2088 }
2089 /*
2090 * Check if the previous beacon has gone out. If
2091 * not don't don't try to post another, skip this
2092 * period and wait for the next. Missed beacons
2093 * indicate a problem and should not occur. If we
2094 * miss too many consecutive beacons reset the device.
2095 */
2096 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2097 sc->bmisscount++;
be9b7259 2098 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2099 "missed %u consecutive beacons\n", sc->bmisscount);
2100 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2101 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2102 "stuck beacon time (%u missed)\n",
2103 sc->bmisscount);
2104 tasklet_schedule(&sc->restq);
2105 }
2106 return;
2107 }
2108 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2109 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2110 "resume beacon xmit after %u misses\n",
2111 sc->bmisscount);
2112 sc->bmisscount = 0;
2113 }
2114
2115 /*
2116 * Stop any current dma and put the new frame on the queue.
2117 * This should never fail since we check above that no frames
2118 * are still pending on the queue.
2119 */
2120 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2121 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2122 /* NB: hw still stops DMA, so proceed */
2123 }
fa1c114f 2124
c6e387a2
NK		 2125 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2126 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2127 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2128 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2129
2130 sc->bsent++;
2131}
2132
2133
9804b98d
BR		 2134/**
2135 * ath5k_beacon_update_timers - update beacon timers
2136 *
2137 * @sc: struct ath5k_softc pointer we are operating on
2138 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2139 * beacon timer update based on the current HW TSF.
2140 *
2141 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2142 * of a received beacon or the current local hardware TSF and write it to the
2143 * beacon timer registers.
2144 *
2145 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2146 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2147 * when we otherwise know we have to update the timers, but we keep it in this
2148 * function to have it all together in one place.
2149 */
fa1c114f 2150static void
9804b98d 2151ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2152{
2153 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2154 u32 nexttbtt, intval, hw_tu, bc_tu;
2155 u64 hw_tsf;
fa1c114f
JS		 2156
2157 intval = sc->bintval & AR5K_BEACON_PERIOD;
2158 if (WARN_ON(!intval))
2159 return;
2160
9804b98d
BR		 2161 /* beacon TSF converted to TU */
2162 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2163
9804b98d
BR		 2164 /* current TSF converted to TU */
2165 hw_tsf = ath5k_hw_get_tsf64(ah);
2166 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2167
9804b98d
BR		 2168#define FUDGE 3
2169 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2170 if (bc_tsf == -1) {
2171 /*
2172 * no beacons received, called internally.
2173 * just need to refresh timers based on HW TSF.
2174 */
2175 nexttbtt = roundup(hw_tu + FUDGE, intval);
2176 } else if (bc_tsf == 0) {
2177 /*
2178 * no beacon received, probably called by ath5k_reset_tsf().
2179 * reset TSF to start with 0.
2180 */
2181 nexttbtt = intval;
2182 intval |= AR5K_BEACON_RESET_TSF;
2183 } else if (bc_tsf > hw_tsf) {
2184 /*
2185 * beacon received, SW merge happend but HW TSF not yet updated.
2186 * not possible to reconfigure timers yet, but next time we
2187 * receive a beacon with the same BSSID, the hardware will
2188 * automatically update the TSF and then we need to reconfigure
2189 * the timers.
2190 */
2191 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2192 "need to wait for HW TSF sync\n");
2193 return;
2194 } else {
2195 /*
2196 * most important case for beacon synchronization between STA.
2197 *
2198 * beacon received and HW TSF has been already updated by HW.
2199 * update next TBTT based on the TSF of the beacon, but make
2200 * sure it is ahead of our local TSF timer.
2201 */
2202 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2203 }
2204#undef FUDGE
fa1c114f 2205
036cd1ec
BR		 2206 sc->nexttbtt = nexttbtt;
2207
fa1c114f 2208 intval |= AR5K_BEACON_ENA;
fa1c114f 2209 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2210
2211 /*
2212 * debugging output last in order to preserve the time critical aspect
2213 * of this function
2214 */
2215 if (bc_tsf == -1)
2216 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2217 "reconfigured timers based on HW TSF\n");
2218 else if (bc_tsf == 0)
2219 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2220 "reset HW TSF and timers\n");
2221 else
2222 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2223 "updated timers based on beacon TSF\n");
2224
2225 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2226 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2227 (unsigned long long) bc_tsf,
2228 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2229 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2230 intval & AR5K_BEACON_PERIOD,
2231 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2232 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2233}
2234
2235
036cd1ec
BR		 2236/**
2237 * ath5k_beacon_config - Configure the beacon queues and interrupts
2238 *
2239 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2240 *
036cd1ec 2241 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2242 * interrupts to detect TSF updates only.
fa1c114f
JS		 2243 */
2244static void
2245ath5k_beacon_config(struct ath5k_softc *sc)
2246{
2247 struct ath5k_hw *ah = sc->ah;
b5f03956 2248 unsigned long flags;
fa1c114f 2249
c6e387a2 2250 ath5k_hw_set_imr(ah, 0);
fa1c114f 2251 sc->bmisscount = 0;
dc1968e7 2252 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2253
1e3e6e8f 2254 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2255 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2256 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2257 /*
036cd1ec
BR		 2258 * In IBSS mode we use a self-linked tx descriptor and let the
2259 * hardware send the beacons automatically. We have to load it
fa1c114f 2260 * only once here.
036cd1ec 2261 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2262 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2263 */
2264 ath5k_beaconq_config(sc);
fa1c114f 2265
036cd1ec
BR		 2266 sc->imask |= AR5K_INT_SWBA;
2267
da966bca
JS		 2268 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2269 if (ath5k_hw_hasveol(ah)) {
b5f03956 2270 spin_lock_irqsave(&sc->block, flags);
da966bca 2271 ath5k_beacon_send(sc);
b5f03956 2272 spin_unlock_irqrestore(&sc->block, flags);
da966bca
JS		 2273 }
2274 } else
2275 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2276 }
fa1c114f 2277
c6e387a2 2278 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2279}
2280
2281
2282/********************\
2283* Interrupt handling *
2284\********************/
2285
2286static int
bb2becac 2287ath5k_init(struct ath5k_softc *sc)
fa1c114f 2288{
bc1b32d6
EO		 2289 struct ath5k_hw *ah = sc->ah;
2290 int ret, i;
fa1c114f
JS		 2291
2292 mutex_lock(&sc->lock);
2293
2294 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2295
2296 /*
2297 * Stop anything previously setup. This is safe
2298 * no matter this is the first time through or not.
2299 */
2300 ath5k_stop_locked(sc);
2301
2302 /*
2303 * The basic interface to setting the hardware in a good
2304 * state is ``reset''. On return the hardware is known to
2305 * be powered up and with interrupts disabled. This must
2306 * be followed by initialization of the appropriate bits
2307 * and then setup of the interrupt mask.
2308 */
d8ee398d
LR		 2309 sc->curchan = sc->hw->conf.channel;
2310 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2311 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2312 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2313 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
d7dc1003
JS		 2314 ret = ath5k_reset(sc, false, false);
2315 if (ret)
2316 goto done;
fa1c114f 2317
bc1b32d6
EO		 2318 /*
2319 * Reset the key cache since some parts do not reset the
2320 * contents on initial power up or resume from suspend.
2321 */
2322 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2323 ath5k_hw_reset_key(ah, i);
2324
fa1c114f 2325 /* Set ack to be sent at low bit-rates */
bc1b32d6 2326 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2327
2328 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2329 msecs_to_jiffies(ath5k_calinterval * 1000)));
2330
2331 ret = 0;
2332done:
274c7c36 2333 mmiowb();
fa1c114f
JS		 2334 mutex_unlock(&sc->lock);
2335 return ret;
2336}
2337
2338static int
2339ath5k_stop_locked(struct ath5k_softc *sc)
2340{
2341 struct ath5k_hw *ah = sc->ah;
2342
2343 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2344 test_bit(ATH_STAT_INVALID, sc->status));
2345
2346 /*
2347 * Shutdown the hardware and driver:
2348 * stop output from above
2349 * disable interrupts
2350 * turn off timers
2351 * turn off the radio
2352 * clear transmit machinery
2353 * clear receive machinery
2354 * drain and release tx queues
2355 * reclaim beacon resources
2356 * power down hardware
2357 *
2358 * Note that some of this work is not possible if the
2359 * hardware is gone (invalid).
2360 */
2361 ieee80211_stop_queues(sc->hw);
2362
2363 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2364 ath5k_led_off(sc);
c6e387a2 2365 ath5k_hw_set_imr(ah, 0);
274c7c36 2366 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2367 }
2368 ath5k_txq_cleanup(sc);
2369 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2370 ath5k_rx_stop(sc);
2371 ath5k_hw_phy_disable(ah);
2372 } else
2373 sc->rxlink = NULL;
2374
2375 return 0;
2376}
2377
2378/*
2379 * Stop the device, grabbing the top-level lock to protect
2380 * against concurrent entry through ath5k_init (which can happen
2381 * if another thread does a system call and the thread doing the
2382 * stop is preempted).
2383 */
2384static int
bb2becac 2385ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2386{
2387 int ret;
2388
2389 mutex_lock(&sc->lock);
2390 ret = ath5k_stop_locked(sc);
2391 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2392 /*
2393 * Set the chip in full sleep mode. Note that we are
2394 * careful to do this only when bringing the interface
2395 * completely to a stop. When the chip is in this state
2396 * it must be carefully woken up or references to
2397 * registers in the PCI clock domain may freeze the bus
2398 * (and system). This varies by chip and is mostly an
2399 * issue with newer parts that go to sleep more quickly.
2400 */
2401 if (sc->ah->ah_mac_srev >= 0x78) {
2402 /*
2403 * XXX
2404 * don't put newer MAC revisions > 7.8 to sleep because
2405 * of the above mentioned problems
2406 */
2407 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2408 "not putting device to sleep\n");
2409 } else {
2410 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2411 "putting device to full sleep\n");
2412 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2413 }
2414 }
2415 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2416
274c7c36 2417 mmiowb();
fa1c114f
JS		 2418 mutex_unlock(&sc->lock);
2419
2420 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2421 tasklet_kill(&sc->rxtq);
2422 tasklet_kill(&sc->txtq);
2423 tasklet_kill(&sc->restq);
acf3c1a5 2424 tasklet_kill(&sc->beacontq);
fa1c114f
JS		 2425
2426 return ret;
2427}
2428
2429static irqreturn_t
2430ath5k_intr(int irq, void *dev_id)
2431{
2432 struct ath5k_softc *sc = dev_id;
2433 struct ath5k_hw *ah = sc->ah;
2434 enum ath5k_int status;
2435 unsigned int counter = 1000;
2436
2437 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2438 !ath5k_hw_is_intr_pending(ah)))
2439 return IRQ_NONE;
2440
2441 do {
fa1c114f
JS		 2442 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2443 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2444 status, sc->imask);
fa1c114f
JS		 2445 if (unlikely(status & AR5K_INT_FATAL)) {
2446 /*
2447 * Fatal errors are unrecoverable.
2448 * Typically these are caused by DMA errors.
2449 */
2450 tasklet_schedule(&sc->restq);
2451 } else if (unlikely(status & AR5K_INT_RXORN)) {
2452 tasklet_schedule(&sc->restq);
2453 } else {
2454 if (status & AR5K_INT_SWBA) {
acf3c1a5 2455 tasklet_schedule(&sc->beacontq);
fa1c114f
JS		 2456 }
2457 if (status & AR5K_INT_RXEOL) {
2458 /*
2459 * NB: the hardware should re-read the link when
2460 * RXE bit is written, but it doesn't work at
2461 * least on older hardware revs.
2462 */
2463 sc->rxlink = NULL;
2464 }
2465 if (status & AR5K_INT_TXURN) {
2466 /* bump tx trigger level */
2467 ath5k_hw_update_tx_triglevel(ah, true);
2468 }
4c674c60 2469 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2470 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2471 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2472 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2473 tasklet_schedule(&sc->txtq);
2474 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2475 /* TODO */
fa1c114f
JS		 2476 }
2477 if (status & AR5K_INT_MIB) {
194828a2
NK		 2478 /*
2479 * These stats are also used for ANI i think
2480 * so how about updating them more often ?
2481 */
2482 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2483 }
2484 }
2485 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2486
2487 if (unlikely(!counter))
2488 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2489
2490 return IRQ_HANDLED;
2491}
2492
2493static void
2494ath5k_tasklet_reset(unsigned long data)
2495{
2496 struct ath5k_softc *sc = (void *)data;
2497
d7dc1003 2498 ath5k_reset_wake(sc);
fa1c114f
JS		 2499}
2500
2501/*
2502 * Periodically recalibrate the PHY to account
2503 * for temperature/environment changes.
2504 */
2505static void
2506ath5k_calibrate(unsigned long data)
2507{
2508 struct ath5k_softc *sc = (void *)data;
2509 struct ath5k_hw *ah = sc->ah;
2510
2511 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2512 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2513 sc->curchan->hw_value);
fa1c114f 2514
6f3b414a 2515 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2516 /*
2517 * Rfgain is out of bounds, reset the chip
2518 * to load new gain values.
2519 */
2520 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2521 ath5k_reset_wake(sc);
fa1c114f
JS		 2522 }
2523 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2524 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2525 ieee80211_frequency_to_channel(
2526 sc->curchan->center_freq));
fa1c114f
JS		 2527
2528 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2529 msecs_to_jiffies(ath5k_calinterval * 1000)));
2530}
2531
2532
2533
2534/***************\
2535* LED functions *
2536\***************/
2537
2538static void
3a078876 2539ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2540{
3a078876
BC		 2541 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2542 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2543 ath5k_led_off(sc);
fa1c114f
JS		 2544 }
2545}
2546
fa1c114f 2547static void
3a078876 2548ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2549{
3a078876
BC		 2550 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2551 return;
fa1c114f 2552 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2553}
2554
2555static void
3a078876 2556ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2557{
3a078876 2558 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2559 return;
3a078876
BC		 2560 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2561}
2562
2563static void
2564ath5k_led_brightness_set(struct led_classdev *led_dev,
2565 enum led_brightness brightness)
2566{
2567 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2568 led_dev);
2569
2570 if (brightness == LED_OFF)
2571 ath5k_led_off(led->sc);
2572 else
2573 ath5k_led_on(led->sc);
2574}
2575
2576static int
2577ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2578 const char *name, char *trigger)
2579{
2580 int err;
2581
2582 led->sc = sc;
2583 strncpy(led->name, name, sizeof(led->name));
2584 led->led_dev.name = led->name;
2585 led->led_dev.default_trigger = trigger;
2586 led->led_dev.brightness_set = ath5k_led_brightness_set;
2587
2588 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
0bbac08f 2589 if (err) {
3a078876
BC		 2590 ATH5K_WARN(sc, "could not register LED %s\n", name);
2591 led->sc = NULL;
fa1c114f 2592 }
3a078876 2593 return err;
fa1c114f
JS		 2594}
2595
3a078876
BC		 2596static void
2597ath5k_unregister_led(struct ath5k_led *led)
2598{
2599 if (!led->sc)
2600 return;
2601 led_classdev_unregister(&led->led_dev);
2602 ath5k_led_off(led->sc);
2603 led->sc = NULL;
2604}
2605
2606static void
2607ath5k_unregister_leds(struct ath5k_softc *sc)
2608{
2609 ath5k_unregister_led(&sc->rx_led);
2610 ath5k_unregister_led(&sc->tx_led);
2611}
2612
2613
2614static int
2615ath5k_init_leds(struct ath5k_softc *sc)
2616{
2617 int ret = 0;
2618 struct ieee80211_hw *hw = sc->hw;
2619 struct pci_dev *pdev = sc->pdev;
2620 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2621
3a078876
BC		 2622 /*
2623 * Auto-enable soft led processing for IBM cards and for
2624 * 5211 minipci cards.
2625 */
2626 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2627 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2628 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2629 sc->led_pin = 0;
734b5aa9 2630 sc->led_on = 0; /* active low */
3a078876
BC		 2631 }
2632 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2633 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2634 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2635 sc->led_pin = 1;
734b5aa9 2636 sc->led_on = 1; /* active high */
3a078876 2637 }
f677d770
TMQMF		 2638 /*
2639 * Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) and
2640 * in emachines notebooks with AMBIT subsystem.
2641 */
2642 if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN ||
2643 pdev->subsystem_vendor == PCI_VENDOR_ID_AMBIT) {
63649b6c
BC		 2644 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2645 sc->led_pin = 3;
2646 sc->led_on = 0; /* active low */
2647 }
2648
3a078876
BC		 2649 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2650 goto out;
2651
2652 ath5k_led_enable(sc);
2653
2654 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2655 ret = ath5k_register_led(sc, &sc->rx_led, name,
2656 ieee80211_get_rx_led_name(hw));
2657 if (ret)
2658 goto out;
2659
2660 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2661 ret = ath5k_register_led(sc, &sc->tx_led, name,
2662 ieee80211_get_tx_led_name(hw));
2663out:
2664 return ret;
2665}
fa1c114f
JS		 2666
2667
2668/********************\
2669* Mac80211 functions *
2670\********************/
2671
2672static int
e039fa4a 2673ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2674{
2675 struct ath5k_softc *sc = hw->priv;
2676 struct ath5k_buf *bf;
2677 unsigned long flags;
2678 int hdrlen;
0fe45b1d 2679 int padsize;
fa1c114f
JS		 2680
2681 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2682
05c914fe 2683 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2684 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2685
2686 /*
2687 * the hardware expects the header padded to 4 byte boundaries
2688 * if this is not the case we add the padding after the header
2689 */
2690 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2691 padsize = ath5k_pad_size(hdrlen);
2692 if (padsize) {
0fe45b1d
BP		 2693
2694 if (skb_headroom(skb) < padsize) {
fa1c114f 2695 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2696 " headroom to pad %d\n", hdrlen, padsize);
71ef99c8 2697 return NETDEV_TX_BUSY;
fa1c114f 2698 }
0fe45b1d
BP		 2699 skb_push(skb, padsize);
2700 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2701 }
2702
fa1c114f
JS		 2703 spin_lock_irqsave(&sc->txbuflock, flags);
2704 if (list_empty(&sc->txbuf)) {
2705 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2706 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2707 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
71ef99c8 2708 return NETDEV_TX_BUSY;
fa1c114f
JS		 2709 }
2710 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2711 list_del(&bf->list);
2712 sc->txbuf_len--;
2713 if (list_empty(&sc->txbuf))
2714 ieee80211_stop_queues(hw);
2715 spin_unlock_irqrestore(&sc->txbuflock, flags);
2716
2717 bf->skb = skb;
2718
e039fa4a 2719 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2720 bf->skb = NULL;
2721 spin_lock_irqsave(&sc->txbuflock, flags);
2722 list_add_tail(&bf->list, &sc->txbuf);
2723 sc->txbuf_len++;
2724 spin_unlock_irqrestore(&sc->txbuflock, flags);
2725 dev_kfree_skb_any(skb);
71ef99c8 2726 return NETDEV_TX_OK;
fa1c114f
JS		 2727 }
2728
71ef99c8 2729 return NETDEV_TX_OK;
fa1c114f
JS		 2730}
2731
2732static int
d7dc1003 2733ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2734{
fa1c114f
JS		 2735 struct ath5k_hw *ah = sc->ah;
2736 int ret;
2737
2738 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2739
d7dc1003 2740 if (stop) {
c6e387a2 2741 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2742 ath5k_txq_cleanup(sc);
2743 ath5k_rx_stop(sc);
2744 }
fa1c114f 2745 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2746 if (ret) {
fa1c114f
JS		 2747 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2748 goto err;
2749 }
d7dc1003
JS		 2750
2751 /*
2752 * This is needed only to setup initial state
2753 * but it's best done after a reset.
2754 */
fa1c114f
JS		 2755 ath5k_hw_set_txpower_limit(sc->ah, 0);
2756
2757 ret = ath5k_rx_start(sc);
d7dc1003 2758 if (ret) {
fa1c114f
JS		 2759 ATH5K_ERR(sc, "can't start recv logic\n");
2760 goto err;
2761 }
d7dc1003 2762
fa1c114f 2763 /*
d7dc1003
JS		 2764 * Change channels and update the h/w rate map if we're switching;
2765 * e.g. 11a to 11b/g.
2766 *
2767 * We may be doing a reset in response to an ioctl that changes the
2768 * channel so update any state that might change as a result.
fa1c114f
JS		 2769 *
2770 * XXX needed?
2771 */
2772/* ath5k_chan_change(sc, c); */
fa1c114f 2773
d7dc1003
JS		 2774 ath5k_beacon_config(sc);
2775 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2776
2777 return 0;
2778err:
2779 return ret;
2780}
2781
d7dc1003
JS		 2782static int
2783ath5k_reset_wake(struct ath5k_softc *sc)
2784{
2785 int ret;
2786
2787 ret = ath5k_reset(sc, true, true);
2788 if (!ret)
2789 ieee80211_wake_queues(sc->hw);
2790
2791 return ret;
2792}
2793
fa1c114f
JS		 2794static int ath5k_start(struct ieee80211_hw *hw)
2795{
bb2becac 2796 return ath5k_init(hw->priv);
fa1c114f
JS		 2797}
2798
2799static void ath5k_stop(struct ieee80211_hw *hw)
2800{
bb2becac 2801 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2802}
2803
2804static int ath5k_add_interface(struct ieee80211_hw *hw,
2805 struct ieee80211_if_init_conf *conf)
2806{
2807 struct ath5k_softc *sc = hw->priv;
2808 int ret;
2809
2810 mutex_lock(&sc->lock);
32bfd35d 2811 if (sc->vif) {
fa1c114f
JS		 2812 ret = 0;
2813 goto end;
2814 }
2815
32bfd35d 2816 sc->vif = conf->vif;
fa1c114f
JS		 2817
2818 switch (conf->type) {
da966bca 2819 case NL80211_IFTYPE_AP:
05c914fe
JB		 2820 case NL80211_IFTYPE_STATION:
2821 case NL80211_IFTYPE_ADHOC:
b706e65b 2822 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2823 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2824 sc->opmode = conf->type;
2825 break;
2826 default:
2827 ret = -EOPNOTSUPP;
2828 goto end;
2829 }
67d2e2df
JS		 2830
2831 /* Set to a reasonable value. Note that this will
2832 * be set to mac80211's value at ath5k_config(). */
2833 sc->bintval = 1000;
0e149cf5 2834 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2835
fa1c114f
JS		 2836 ret = 0;
2837end:
2838 mutex_unlock(&sc->lock);
2839 return ret;
2840}
2841
2842static void
2843ath5k_remove_interface(struct ieee80211_hw *hw,
2844 struct ieee80211_if_init_conf *conf)
2845{
2846 struct ath5k_softc *sc = hw->priv;
0e149cf5 2847 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2848
2849 mutex_lock(&sc->lock);
32bfd35d 2850 if (sc->vif != conf->vif)
fa1c114f
JS		 2851 goto end;
2852
0e149cf5 2853 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2854 sc->vif = NULL;
fa1c114f
JS		 2855end:
2856 mutex_unlock(&sc->lock);
2857}
2858
d8ee398d
LR		 2859/*
2860 * TODO: Phy disable/diversity etc
2861 */
fa1c114f 2862static int
e8975581 2863ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2864{
2865 struct ath5k_softc *sc = hw->priv;
e8975581 2866 struct ieee80211_conf *conf = &hw->conf;
be009370
BC		 2867 int ret;
2868
2869 mutex_lock(&sc->lock);
fa1c114f 2870
e535c1ac 2871 sc->bintval = conf->beacon_int;
d8ee398d 2872 sc->power_level = conf->power_level;
fa1c114f 2873
be009370
BC		 2874 ret = ath5k_chan_set(sc, conf->channel);
2875
2876 mutex_unlock(&sc->lock);
2877 return ret;
fa1c114f
JS		 2878}
2879
2880static int
32bfd35d 2881ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2882 struct ieee80211_if_conf *conf)
2883{
2884 struct ath5k_softc *sc = hw->priv;
2885 struct ath5k_hw *ah = sc->ah;
fa8419d0 2886 int ret = 0;
fa1c114f 2887
fa1c114f 2888 mutex_lock(&sc->lock);
32bfd35d 2889 if (sc->vif != vif) {
fa1c114f
JS		 2890 ret = -EIO;
2891 goto unlock;
2892 }
da966bca 2893 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2894 /* Cache for later use during resets */
2895 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2896 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2897 * a clean way of letting us retrieve this yet. */
2898 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2899 mmiowb();
fa1c114f 2900 }
9d139c81 2901 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2902 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2903 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2904 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2905 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2906 if (!beacon) {
2907 ret = -ENOMEM;
2908 goto unlock;
2909 }
da966bca 2910 ath5k_beacon_update(sc, beacon);
9d139c81 2911 }
fa1c114f 2912
fa1c114f
JS		 2913unlock:
2914 mutex_unlock(&sc->lock);
2915 return ret;
2916}
2917
2918#define SUPPORTED_FIF_FLAGS \
2919 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2920 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2921 FIF_BCN_PRBRESP_PROMISC
2922/*
2923 * o always accept unicast, broadcast, and multicast traffic
2924 * o multicast traffic for all BSSIDs will be enabled if mac80211
2925 * says it should be
2926 * o maintain current state of phy ofdm or phy cck error reception.
2927 * If the hardware detects any of these type of errors then
2928 * ath5k_hw_get_rx_filter() will pass to us the respective
2929 * hardware filters to be able to receive these type of frames.
2930 * o probe request frames are accepted only when operating in
2931 * hostap, adhoc, or monitor modes
2932 * o enable promiscuous mode according to the interface state
2933 * o accept beacons:
2934 * - when operating in adhoc mode so the 802.11 layer creates
2935 * node table entries for peers,
2936 * - when operating in station mode for collecting rssi data when
2937 * the station is otherwise quiet, or
2938 * - when scanning
2939 */
2940static void ath5k_configure_filter(struct ieee80211_hw *hw,
2941 unsigned int changed_flags,
2942 unsigned int *new_flags,
2943 int mc_count, struct dev_mc_list *mclist)
2944{
2945 struct ath5k_softc *sc = hw->priv;
2946 struct ath5k_hw *ah = sc->ah;
2947 u32 mfilt[2], val, rfilt;
2948 u8 pos;
2949 int i;
2950
2951 mfilt[0] = 0;
2952 mfilt[1] = 0;
2953
2954 /* Only deal with supported flags */
2955 changed_flags &= SUPPORTED_FIF_FLAGS;
2956 *new_flags &= SUPPORTED_FIF_FLAGS;
2957
2958 /* If HW detects any phy or radar errors, leave those filters on.
2959 * Also, always enable Unicast, Broadcasts and Multicast
2960 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2961 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2962 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2963 AR5K_RX_FILTER_MCAST);
2964
2965 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2966 if (*new_flags & FIF_PROMISC_IN_BSS) {
2967 rfilt |= AR5K_RX_FILTER_PROM;
2968 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2969 } else {
fa1c114f 2970 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2971 }
fa1c114f
JS		 2972 }
2973
2974 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2975 if (*new_flags & FIF_ALLMULTI) {
2976 mfilt[0] = ~0;
2977 mfilt[1] = ~0;
2978 } else {
2979 for (i = 0; i < mc_count; i++) {
2980 if (!mclist)
2981 break;
2982 /* calculate XOR of eight 6-bit values */
533dd1b0 2983 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2984 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2985 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2986 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2987 pos &= 0x3f;
2988 mfilt[pos / 32] |= (1 << (pos % 32));
2989 /* XXX: we might be able to just do this instead,
2990 * but not sure, needs testing, if we do use this we'd
2991 * neet to inform below to not reset the mcast */
2992 /* ath5k_hw_set_mcast_filterindex(ah,
2993 * mclist->dmi_addr[5]); */
2994 mclist = mclist->next;
2995 }
2996 }
2997
2998 /* This is the best we can do */
2999 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3000 rfilt |= AR5K_RX_FILTER_PHYERR;
3001
3002 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3003 * and probes for any BSSID, this needs testing */
3004 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3005 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3006
3007 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3008 * set we should only pass on control frames for this
3009 * station. This needs testing. I believe right now this
3010 * enables *all* control frames, which is OK.. but
3011 * but we should see if we can improve on granularity */
3012 if (*new_flags & FIF_CONTROL)
3013 rfilt |= AR5K_RX_FILTER_CONTROL;
3014
3015 /* Additional settings per mode -- this is per ath5k */
3016
3017 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3018
05c914fe 3019 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 3020 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3021 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 3022 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 3023 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 3024 if (sc->opmode != NL80211_IFTYPE_AP &&
3025 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 3026 test_bit(ATH_STAT_PROMISC, sc->status))
3027 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 3028 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 3029 sc->opmode == NL80211_IFTYPE_ADHOC ||
3030 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 3031 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 3032 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
3033 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3034 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 3035
3036 /* Set filters */
0bbac08f 3037 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3038
3039 /* Set multicast bits */
3040 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3041 /* Set the cached hw filter flags, this will alter actually
3042 * be set in HW */
3043 sc->filter_flags = rfilt;
3044}
3045
3046static int
3047ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3048 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3049 struct ieee80211_key_conf *key)
fa1c114f
JS		 3050{
3051 struct ath5k_softc *sc = hw->priv;
3052 int ret = 0;
3053
9ad9a26e
BC		 3054 if (modparam_nohwcrypt)
3055 return -EOPNOTSUPP;
3056
0bbac08f 3057 switch (key->alg) {
fa1c114f 3058 case ALG_WEP:
fa1c114f 3059 case ALG_TKIP:
3f64b435 3060 break;
fa1c114f
JS		 3061 case ALG_CCMP:
3062 return -EOPNOTSUPP;
3063 default:
3064 WARN_ON(1);
3065 return -EINVAL;
3066 }
3067
3068 mutex_lock(&sc->lock);
3069
3070 switch (cmd) {
3071 case SET_KEY:
dc822b5d
JB		 3072 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3073 sta ? sta->addr : NULL);
fa1c114f
JS		 3074 if (ret) {
3075 ATH5K_ERR(sc, "can't set the key\n");
3076 goto unlock;
3077 }
3078 __set_bit(key->keyidx, sc->keymap);
3079 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3080 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3081 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3082 break;
3083 case DISABLE_KEY:
3084 ath5k_hw_reset_key(sc->ah, key->keyidx);
3085 __clear_bit(key->keyidx, sc->keymap);
3086 break;
3087 default:
3088 ret = -EINVAL;
3089 goto unlock;
3090 }
3091
3092unlock:
274c7c36 3093 mmiowb();
fa1c114f
JS		 3094 mutex_unlock(&sc->lock);
3095 return ret;
3096}
3097
3098static int
3099ath5k_get_stats(struct ieee80211_hw *hw,
3100 struct ieee80211_low_level_stats *stats)
3101{
3102 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3103 struct ath5k_hw *ah = sc->ah;
3104
3105 /* Force update */
3106 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3107
3108 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3109
3110 return 0;
3111}
3112
3113static int
3114ath5k_get_tx_stats(struct ieee80211_hw *hw,
3115 struct ieee80211_tx_queue_stats *stats)
3116{
3117 struct ath5k_softc *sc = hw->priv;
3118
3119 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3120
3121 return 0;
3122}
3123
3124static u64
3125ath5k_get_tsf(struct ieee80211_hw *hw)
3126{
3127 struct ath5k_softc *sc = hw->priv;
3128
3129 return ath5k_hw_get_tsf64(sc->ah);
3130}
3131
3b5d665b
AF		 3132static void
3133ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3134{
3135 struct ath5k_softc *sc = hw->priv;
3136
3137 ath5k_hw_set_tsf64(sc->ah, tsf);
3138}
3139
fa1c114f
JS		 3140static void
3141ath5k_reset_tsf(struct ieee80211_hw *hw)
3142{
3143 struct ath5k_softc *sc = hw->priv;
3144
9804b98d
BR		 3145 /*
3146 * in IBSS mode we need to update the beacon timers too.
3147 * this will also reset the TSF if we call it with 0
3148 */
05c914fe 3149 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3150 ath5k_beacon_update_timers(sc, 0);
3151 else
3152 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3153}
3154
3155static int
da966bca 3156ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3157{
00482973 3158 unsigned long flags;
fa1c114f
JS		 3159 int ret;
3160
3161 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3162
00482973 3163 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3164 ath5k_txbuf_free(sc, sc->bbuf);
3165 sc->bbuf->skb = skb;
e039fa4a 3166 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3167 if (ret)
3168 sc->bbuf->skb = NULL;
00482973
JS		 3169 spin_unlock_irqrestore(&sc->block, flags);
3170 if (!ret) {
fa1c114f 3171 ath5k_beacon_config(sc);
274c7c36
JS		 3172 mmiowb();
3173 }
fa1c114f 3174
fa1c114f
JS		 3175 return ret;
3176}
02969b38
MX		 3177static void
3178set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3179{
3180 struct ath5k_softc *sc = hw->priv;
3181 struct ath5k_hw *ah = sc->ah;
3182 u32 rfilt;
3183 rfilt = ath5k_hw_get_rx_filter(ah);
3184 if (enable)
3185 rfilt |= AR5K_RX_FILTER_BEACON;
3186 else
3187 rfilt &= ~AR5K_RX_FILTER_BEACON;
3188 ath5k_hw_set_rx_filter(ah, rfilt);
3189 sc->filter_flags = rfilt;
3190}
fa1c114f 3191
02969b38
MX		 3192static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3193 struct ieee80211_vif *vif,
3194 struct ieee80211_bss_conf *bss_conf,
3195 u32 changes)
3196{
3197 struct ath5k_softc *sc = hw->priv;
3198 if (changes & BSS_CHANGED_ASSOC) {
3199 mutex_lock(&sc->lock);
3200 sc->assoc = bss_conf->assoc;
3201 if (sc->opmode == NL80211_IFTYPE_STATION)
3202 set_beacon_filter(hw, sc->assoc);
3203 mutex_unlock(&sc->lock);
3204 }
3205}
Clone of davem's net-next-2.6 tree