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[net-next-2.6.git] / drivers / net / wireless / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f
JS		 66
67
68/******************\
69* Internal defines *
70\******************/
71
72/* Module info */
73MODULE_AUTHOR("Jiri Slaby");
74MODULE_AUTHOR("Nick Kossifidis");
75MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 78MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 79
80
81/* Known PCI ids */
2c91108c 82static const struct pci_device_id ath5k_pci_id_table[] = {
fa1c114f
JS		 83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 101 { 0 }
102};
103MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105/* Known SREVs */
2c91108c 106static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143};
144
2c91108c 145static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185};
186
fa1c114f
JS		 187/*
188 * Prototypes - PCI stack related functions
189 */
190static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193#ifdef CONFIG_PM
194static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196static int ath5k_pci_resume(struct pci_dev *pdev);
197#else
198#define ath5k_pci_suspend NULL
199#define ath5k_pci_resume NULL
200#endif /* CONFIG_PM */
201
04a9e451 202static struct pci_driver ath5k_pci_driver = {
9764f3f9 203 .name = KBUILD_MODNAME,
fa1c114f
JS		 204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209};
210
211
212
213/*
214 * Prototypes - MAC 802.11 stack related functions
215 */
e039fa4a 216static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 217static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 219static int ath5k_start(struct ieee80211_hw *hw);
220static void ath5k_stop(struct ieee80211_hw *hw);
221static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
e8975581 225static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 226static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
fa1c114f
JS		 228 struct ieee80211_if_conf *conf);
229static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
dc822b5d 235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 236 struct ieee80211_key_conf *key);
237static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 242static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 243static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 244static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 245 struct sk_buff *skb);
02969b38
MX		 246static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
249 u32 changes);
fa1c114f 250
2c91108c 251static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 252 .tx = ath5k_tx,
253 .start = ath5k_start,
254 .stop = ath5k_stop,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
3b5d665b 265 .set_tsf = ath5k_set_tsf,
fa1c114f 266 .reset_tsf = ath5k_reset_tsf,
02969b38 267 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 268};
269
270/*
271 * Prototypes - Internal functions
272 */
273/* Attach detach */
274static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278/* Channel/mode setup */
279static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 280static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
63266a65 284static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 285static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 290
fa1c114f
JS		 291/* Descriptor setup */
292static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296/* Buffers setup */
297static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 300 struct ath5k_buf *bf);
fa1c114f
JS		 301static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303{
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
00482973 309 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 310 bf->skb = NULL;
311}
312
a6c8d375
FF		 313static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
315{
316 BUG_ON(!bf);
317 if (!bf->skb)
318 return;
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
320 PCI_DMA_FROMDEVICE);
321 dev_kfree_skb_any(bf->skb);
322 bf->skb = NULL;
323}
324
325
fa1c114f
JS		 326/* Queues setup */
327static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330static int ath5k_beaconq_config(struct ath5k_softc *sc);
331static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334static void ath5k_txq_release(struct ath5k_softc *sc);
335/* Rx handling */
336static int ath5k_rx_start(struct ath5k_softc *sc);
337static void ath5k_rx_stop(struct ath5k_softc *sc);
338static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
b47f407b
BR		 340 struct sk_buff *skb,
341 struct ath5k_rx_status *rs);
fa1c114f
JS		 342static void ath5k_tasklet_rx(unsigned long data);
343/* Tx handling */
344static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346static void ath5k_tasklet_tx(unsigned long data);
347/* Beacon handling */
348static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 349 struct ath5k_buf *bf);
fa1c114f
JS		 350static void ath5k_beacon_send(struct ath5k_softc *sc);
351static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 352static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 353static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 354
355static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
356{
357 u64 tsf = ath5k_hw_get_tsf64(ah);
358
359 if ((tsf & 0x7fff) < rstamp)
360 tsf -= 0x8000;
361
362 return (tsf & ~0x7fff) | rstamp;
363}
364
365/* Interrupt handling */
bb2becac 366static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 367static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 368static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 369static irqreturn_t ath5k_intr(int irq, void *dev_id);
370static void ath5k_tasklet_reset(unsigned long data);
371
372static void ath5k_calibrate(unsigned long data);
fa1c114f
JS		 373
374/*
375 * Module init/exit functions
376 */
377static int __init
378init_ath5k_pci(void)
379{
380 int ret;
381
382 ath5k_debug_init();
383
04a9e451 384 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 385 if (ret) {
386 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
387 return ret;
388 }
389
390 return 0;
391}
392
393static void __exit
394exit_ath5k_pci(void)
395{
04a9e451 396 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 397
398 ath5k_debug_finish();
399}
400
401module_init(init_ath5k_pci);
402module_exit(exit_ath5k_pci);
403
404
405/********************\
406* PCI Initialization *
407\********************/
408
409static const char *
410ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
411{
412 const char *name = "xxxxx";
413 unsigned int i;
414
415 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
416 if (srev_names[i].sr_type != type)
417 continue;
75d0edb8
NK		 418
419 if ((val & 0xf0) == srev_names[i].sr_val)
420 name = srev_names[i].sr_name;
421
422 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 423 name = srev_names[i].sr_name;
424 break;
425 }
426 }
427
428 return name;
429}
430
431static int __devinit
432ath5k_pci_probe(struct pci_dev *pdev,
433 const struct pci_device_id *id)
434{
435 void __iomem *mem;
436 struct ath5k_softc *sc;
437 struct ieee80211_hw *hw;
438 int ret;
439 u8 csz;
440
441 ret = pci_enable_device(pdev);
442 if (ret) {
443 dev_err(&pdev->dev, "can't enable device\n");
444 goto err;
445 }
446
447 /* XXX 32-bit addressing only */
448 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
449 if (ret) {
450 dev_err(&pdev->dev, "32-bit DMA not available\n");
451 goto err_dis;
452 }
453
454 /*
455 * Cache line size is used to size and align various
456 * structures used to communicate with the hardware.
457 */
458 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
459 if (csz == 0) {
460 /*
461 * Linux 2.4.18 (at least) writes the cache line size
462 * register as a 16-bit wide register which is wrong.
463 * We must have this setup properly for rx buffer
464 * DMA to work so force a reasonable value here if it
465 * comes up zero.
466 */
467 csz = L1_CACHE_BYTES / sizeof(u32);
468 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
469 }
470 /*
471 * The default setting of latency timer yields poor results,
472 * set it to the value used by other systems. It may be worth
473 * tweaking this setting more.
474 */
475 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
476
477 /* Enable bus mastering */
478 pci_set_master(pdev);
479
480 /*
481 * Disable the RETRY_TIMEOUT register (0x41) to keep
482 * PCI Tx retries from interfering with C3 CPU state.
483 */
484 pci_write_config_byte(pdev, 0x41, 0);
485
486 ret = pci_request_region(pdev, 0, "ath5k");
487 if (ret) {
488 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
489 goto err_dis;
490 }
491
492 mem = pci_iomap(pdev, 0, 0);
493 if (!mem) {
494 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
495 ret = -EIO;
496 goto err_reg;
497 }
498
499 /*
500 * Allocate hw (mac80211 main struct)
501 * and hw->priv (driver private data)
502 */
503 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
504 if (hw == NULL) {
505 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
506 ret = -ENOMEM;
507 goto err_map;
508 }
509
510 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
511
512 /* Initialize driver private data */
513 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 514 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
515 IEEE80211_HW_SIGNAL_DBM |
516 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 517
518 hw->wiphy->interface_modes =
519 BIT(NL80211_IFTYPE_STATION) |
520 BIT(NL80211_IFTYPE_ADHOC) |
521 BIT(NL80211_IFTYPE_MESH_POINT);
522
fa1c114f
JS		 523 hw->extra_tx_headroom = 2;
524 hw->channel_change_time = 5000;
fa1c114f
JS		 525 sc = hw->priv;
526 sc->hw = hw;
527 sc->pdev = pdev;
528
529 ath5k_debug_init_device(sc);
530
531 /*
532 * Mark the device as detached to avoid processing
533 * interrupts until setup is complete.
534 */
535 __set_bit(ATH_STAT_INVALID, sc->status);
536
537 sc->iobase = mem; /* So we can unmap it on detach */
538 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 539 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 540 mutex_init(&sc->lock);
541 spin_lock_init(&sc->rxbuflock);
542 spin_lock_init(&sc->txbuflock);
00482973 543 spin_lock_init(&sc->block);
fa1c114f
JS		 544
545 /* Set private data */
546 pci_set_drvdata(pdev, hw);
547
fa1c114f
JS		 548 /* Setup interrupt handler */
549 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
550 if (ret) {
551 ATH5K_ERR(sc, "request_irq failed\n");
552 goto err_free;
553 }
554
555 /* Initialize device */
556 sc->ah = ath5k_hw_attach(sc, id->driver_data);
557 if (IS_ERR(sc->ah)) {
558 ret = PTR_ERR(sc->ah);
559 goto err_irq;
560 }
561
2f7fe870
FF		 562 /* set up multi-rate retry capabilities */
563 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 564 hw->max_rates = 4;
565 hw->max_rate_tries = 11;
2f7fe870
FF		 566 }
567
fa1c114f
JS		 568 /* Finish private driver data initialization */
569 ret = ath5k_attach(pdev, hw);
570 if (ret)
571 goto err_ah;
572
573 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 574 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 575 sc->ah->ah_mac_srev,
576 sc->ah->ah_phy_revision);
577
400ec45a 578 if (!sc->ah->ah_single_chip) {
fa1c114f 579 /* Single chip radio (!RF5111) */
400ec45a
LR		 580 if (sc->ah->ah_radio_5ghz_revision &&
581 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 582 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 583 if (!test_bit(AR5K_MODE_11A,
584 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 585 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 586 ath5k_chip_name(AR5K_VERSION_RAD,
587 sc->ah->ah_radio_5ghz_revision),
588 sc->ah->ah_radio_5ghz_revision);
589 /* No 2GHz support (5110 and some
590 * 5Ghz only cards) -> report 5Ghz radio */
591 } else if (!test_bit(AR5K_MODE_11B,
592 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 593 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 594 ath5k_chip_name(AR5K_VERSION_RAD,
595 sc->ah->ah_radio_5ghz_revision),
596 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 597 /* Multiband radio */
598 } else {
599 ATH5K_INFO(sc, "RF%s multiband radio found"
600 " (0x%x)\n",
400ec45a
LR		 601 ath5k_chip_name(AR5K_VERSION_RAD,
602 sc->ah->ah_radio_5ghz_revision),
603 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 604 }
605 }
400ec45a
LR		 606 /* Multi chip radio (RF5111 - RF2111) ->
607 * report both 2GHz/5GHz radios */
608 else if (sc->ah->ah_radio_5ghz_revision &&
609 sc->ah->ah_radio_2ghz_revision){
fa1c114f 610 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
fa1c114f 614 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 615 ath5k_chip_name(AR5K_VERSION_RAD,
616 sc->ah->ah_radio_2ghz_revision),
617 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 618 }
619 }
620
621
622 /* ready to process interrupts */
623 __clear_bit(ATH_STAT_INVALID, sc->status);
624
625 return 0;
626err_ah:
627 ath5k_hw_detach(sc->ah);
628err_irq:
629 free_irq(pdev->irq, sc);
630err_free:
fa1c114f
JS		 631 ieee80211_free_hw(hw);
632err_map:
633 pci_iounmap(pdev, mem);
634err_reg:
635 pci_release_region(pdev, 0);
636err_dis:
637 pci_disable_device(pdev);
638err:
639 return ret;
640}
641
642static void __devexit
643ath5k_pci_remove(struct pci_dev *pdev)
644{
645 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
646 struct ath5k_softc *sc = hw->priv;
647
648 ath5k_debug_finish_device(sc);
649 ath5k_detach(pdev, hw);
650 ath5k_hw_detach(sc->ah);
651 free_irq(pdev->irq, sc);
fa1c114f
JS		 652 pci_iounmap(pdev, sc->iobase);
653 pci_release_region(pdev, 0);
654 pci_disable_device(pdev);
655 ieee80211_free_hw(hw);
656}
657
658#ifdef CONFIG_PM
659static int
660ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
661{
662 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
663 struct ath5k_softc *sc = hw->priv;
664
3a078876 665 ath5k_led_off(sc);
fa1c114f 666
3e4242b9 667 free_irq(pdev->irq, sc);
fa1c114f
JS		 668 pci_save_state(pdev);
669 pci_disable_device(pdev);
670 pci_set_power_state(pdev, PCI_D3hot);
671
672 return 0;
673}
674
675static int
676ath5k_pci_resume(struct pci_dev *pdev)
677{
678 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
679 struct ath5k_softc *sc = hw->priv;
bc1b32d6 680 int err;
fa1c114f 681
3e4242b9 682 pci_restore_state(pdev);
fa1c114f
JS		 683
684 err = pci_enable_device(pdev);
685 if (err)
686 return err;
687
3e4242b9
JS		 688 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
689 if (err) {
690 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 691 goto err_no_irq;
3e4242b9
JS		 692 }
693
3a078876 694 ath5k_led_enable(sc);
fa1c114f 695 return 0;
bb2becac 696
37465c8a 697err_no_irq:
3e4242b9
JS		 698 pci_disable_device(pdev);
699 return err;
fa1c114f
JS		 700}
701#endif /* CONFIG_PM */
702
703
fa1c114f
JS		 704/***********************\
705* Driver Initialization *
706\***********************/
707
708static int
709ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
710{
711 struct ath5k_softc *sc = hw->priv;
712 struct ath5k_hw *ah = sc->ah;
0e149cf5 713 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 714 int ret;
715
716 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
717
718 /*
719 * Check if the MAC has multi-rate retry support.
720 * We do this by trying to setup a fake extended
721 * descriptor. MAC's that don't have support will
722 * return false w/o doing anything. MAC's that do
723 * support it will return true w/o doing anything.
724 */
c6e387a2 725 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 726 if (ret < 0)
727 goto err;
728 if (ret > 0)
fa1c114f
JS		 729 __set_bit(ATH_STAT_MRRETRY, sc->status);
730
fa1c114f
JS		 731 /*
732 * Collect the channel list. The 802.11 layer
733 * is resposible for filtering this list based
734 * on settings like the phy mode and regulatory
735 * domain restrictions.
736 */
63266a65 737 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 738 if (ret) {
739 ATH5K_ERR(sc, "can't get channels\n");
740 goto err;
741 }
742
743 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 744 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
745 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 746 else
d8ee398d 747 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 748
749 /*
750 * Allocate tx+rx descriptors and populate the lists.
751 */
752 ret = ath5k_desc_alloc(sc, pdev);
753 if (ret) {
754 ATH5K_ERR(sc, "can't allocate descriptors\n");
755 goto err;
756 }
757
758 /*
759 * Allocate hardware transmit queues: one queue for
760 * beacon frames and one data queue for each QoS
761 * priority. Note that hw functions handle reseting
762 * these queues at the needed time.
763 */
764 ret = ath5k_beaconq_setup(ah);
765 if (ret < 0) {
766 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
767 goto err_desc;
768 }
769 sc->bhalq = ret;
770
771 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
772 if (IS_ERR(sc->txq)) {
773 ATH5K_ERR(sc, "can't setup xmit queue\n");
774 ret = PTR_ERR(sc->txq);
775 goto err_bhal;
776 }
777
778 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
779 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
780 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
acf3c1a5 781 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 782 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 783
0e149cf5
BC		 784 ret = ath5k_eeprom_read_mac(ah, mac);
785 if (ret) {
786 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
787 sc->pdev->device);
788 goto err_queues;
789 }
790
fa1c114f
JS		 791 SET_IEEE80211_PERM_ADDR(hw, mac);
792 /* All MAC address bits matter for ACKs */
793 memset(sc->bssidmask, 0xff, ETH_ALEN);
794 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
795
796 ret = ieee80211_register_hw(hw);
797 if (ret) {
798 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
799 goto err_queues;
800 }
801
3a078876
BC		 802 ath5k_init_leds(sc);
803
fa1c114f
JS		 804 return 0;
805err_queues:
806 ath5k_txq_release(sc);
807err_bhal:
808 ath5k_hw_release_tx_queue(ah, sc->bhalq);
809err_desc:
810 ath5k_desc_free(sc, pdev);
811err:
812 return ret;
813}
814
815static void
816ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
817{
818 struct ath5k_softc *sc = hw->priv;
819
820 /*
821 * NB: the order of these is important:
822 * o call the 802.11 layer before detaching ath5k_hw to
823 * insure callbacks into the driver to delete global
824 * key cache entries can be handled
825 * o reclaim the tx queue data structures after calling
826 * the 802.11 layer as we'll get called back to reclaim
827 * node state and potentially want to use them
828 * o to cleanup the tx queues the hal is called, so detach
829 * it last
830 * XXX: ??? detach ath5k_hw ???
831 * Other than that, it's straightforward...
832 */
833 ieee80211_unregister_hw(hw);
834 ath5k_desc_free(sc, pdev);
835 ath5k_txq_release(sc);
836 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 837 ath5k_unregister_leds(sc);
fa1c114f
JS		 838
839 /*
840 * NB: can't reclaim these until after ieee80211_ifdetach
841 * returns because we'll get called back to reclaim node
842 * state and potentially want to use them.
843 */
844}
845
846
847
848
849/********************\
850* Channel/mode setup *
851\********************/
852
853/*
854 * Convert IEEE channel number to MHz frequency.
855 */
856static inline short
857ath5k_ieee2mhz(short chan)
858{
859 if (chan <= 14 || chan >= 27)
860 return ieee80211chan2mhz(chan);
861 else
862 return 2212 + chan * 20;
863}
864
fa1c114f
JS		 865static unsigned int
866ath5k_copy_channels(struct ath5k_hw *ah,
867 struct ieee80211_channel *channels,
868 unsigned int mode,
869 unsigned int max)
870{
d8ee398d 871 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 872
873 if (!test_bit(mode, ah->ah_modes))
874 return 0;
875
fa1c114f 876 switch (mode) {
d8ee398d
LR		 877 case AR5K_MODE_11A:
878 case AR5K_MODE_11A_TURBO:
fa1c114f 879 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 880 size = 220 ;
fa1c114f
JS		 881 chfreq = CHANNEL_5GHZ;
882 break;
d8ee398d
LR		 883 case AR5K_MODE_11B:
884 case AR5K_MODE_11G:
885 case AR5K_MODE_11G_TURBO:
886 size = 26;
fa1c114f
JS		 887 chfreq = CHANNEL_2GHZ;
888 break;
889 default:
890 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
891 return 0;
892 }
893
894 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 895 ch = i + 1 ;
896 freq = ath5k_ieee2mhz(ch);
fa1c114f 897
d8ee398d
LR		 898 /* Check if channel is supported by the chipset */
899 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 900 continue;
901
d8ee398d
LR		 902 /* Write channel info and increment counter */
903 channels[count].center_freq = freq;
a3f4b914
LR		 904 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
905 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 906 switch (mode) {
907 case AR5K_MODE_11A:
908 case AR5K_MODE_11G:
909 channels[count].hw_value = chfreq | CHANNEL_OFDM;
910 break;
911 case AR5K_MODE_11A_TURBO:
912 case AR5K_MODE_11G_TURBO:
913 channels[count].hw_value = chfreq |
914 CHANNEL_OFDM | CHANNEL_TURBO;
915 break;
916 case AR5K_MODE_11B:
d8ee398d
LR		 917 channels[count].hw_value = CHANNEL_B;
918 }
fa1c114f 919
fa1c114f
JS		 920 count++;
921 max--;
922 }
923
924 return count;
925}
926
63266a65
BR		 927static void
928ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
929{
930 u8 i;
931
932 for (i = 0; i < AR5K_MAX_RATES; i++)
933 sc->rate_idx[b->band][i] = -1;
934
935 for (i = 0; i < b->n_bitrates; i++) {
936 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
937 if (b->bitrates[i].hw_value_short)
938 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
939 }
940}
941
d8ee398d 942static int
63266a65 943ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 944{
945 struct ath5k_softc *sc = hw->priv;
d8ee398d 946 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 947 struct ieee80211_supported_band *sband;
948 int max_c, count_c = 0;
949 int i;
fa1c114f 950
d8ee398d 951 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 952 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 953
954 /* 2GHz band */
63266a65
BR		 955 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
956 sband->band = IEEE80211_BAND_2GHZ;
957 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 958
63266a65
BR		 959 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
960 /* G mode */
961 memcpy(sband->bitrates, &ath5k_rates[0],
962 sizeof(struct ieee80211_rate) * 12);
963 sband->n_bitrates = 12;
fa1c114f 964
d8ee398d 965 sband->channels = sc->channels;
d8ee398d 966 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 967 AR5K_MODE_11G, max_c);
fa1c114f 968
63266a65 969 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 970 count_c = sband->n_channels;
63266a65
BR		 971 max_c -= count_c;
972 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
973 /* B mode */
974 memcpy(sband->bitrates, &ath5k_rates[0],
975 sizeof(struct ieee80211_rate) * 4);
976 sband->n_bitrates = 4;
977
978 /* 5211 only supports B rates and uses 4bit rate codes
979 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
980 * fix them up here:
981 */
982 if (ah->ah_version == AR5K_AR5211) {
983 for (i = 0; i < 4; i++) {
984 sband->bitrates[i].hw_value =
985 sband->bitrates[i].hw_value & 0xF;
986 sband->bitrates[i].hw_value_short =
987 sband->bitrates[i].hw_value_short & 0xF;
988 }
989 }
fa1c114f 990
63266a65
BR		 991 sband->channels = sc->channels;
992 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
993 AR5K_MODE_11B, max_c);
d8ee398d 994
63266a65
BR		 995 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
996 count_c = sband->n_channels;
d8ee398d 997 max_c -= count_c;
fa1c114f 998 }
63266a65 999 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1000
63266a65 1001 /* 5GHz band, A mode */
400ec45a 1002 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1003 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1004 sband->band = IEEE80211_BAND_5GHZ;
1005 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1006
63266a65
BR		 1007 memcpy(sband->bitrates, &ath5k_rates[4],
1008 sizeof(struct ieee80211_rate) * 8);
1009 sband->n_bitrates = 8;
fa1c114f 1010
63266a65 1011 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1012 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1013 AR5K_MODE_11A, max_c);
1014
d8ee398d
LR		 1015 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1016 }
63266a65 1017 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1018
b446197c 1019 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1020
1021 return 0;
fa1c114f
JS		 1022}
1023
1024/*
1025 * Set/change channels. If the channel is really being changed,
1026 * it's done by reseting the chip. To accomplish this we must
1027 * first cleanup any pending DMA, then restart stuff after a la
1028 * ath5k_init.
be009370
BC		 1029 *
1030 * Called with sc->lock.
fa1c114f
JS		 1031 */
1032static int
1033ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1034{
d8ee398d
LR		 1035 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1036 sc->curchan->center_freq, chan->center_freq);
1037
1038 if (chan->center_freq != sc->curchan->center_freq ||
1039 chan->hw_value != sc->curchan->hw_value) {
1040
1041 sc->curchan = chan;
1042 sc->curband = &sc->sbands[chan->band];
fa1c114f 1043
fa1c114f
JS		 1044 /*
1045 * To switch channels clear any pending DMA operations;
1046 * wait long enough for the RX fifo to drain, reset the
1047 * hardware at the new frequency, and then re-enable
1048 * the relevant bits of the h/w.
1049 */
d7dc1003 1050 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1051 }
1052
1053 return 0;
1054}
1055
1056static void
1057ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1058{
fa1c114f 1059 sc->curmode = mode;
d8ee398d 1060
400ec45a 1061 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1062 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1063 } else {
1064 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1065 }
fa1c114f
JS		 1066}
1067
1068static void
1069ath5k_mode_setup(struct ath5k_softc *sc)
1070{
1071 struct ath5k_hw *ah = sc->ah;
1072 u32 rfilt;
1073
1074 /* configure rx filter */
1075 rfilt = sc->filter_flags;
1076 ath5k_hw_set_rx_filter(ah, rfilt);
1077
1078 if (ath5k_hw_hasbssidmask(ah))
1079 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1080
1081 /* configure operational mode */
1082 ath5k_hw_set_opmode(ah);
1083
1084 ath5k_hw_set_mcast_filter(ah, 0, 0);
1085 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1086}
1087
d8ee398d 1088static inline int
63266a65
BR		 1089ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1090{
db5b4f7a
JS		 1091 WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1092 "hw_rix out of bounds: %x\n", hw_rix);
63266a65 1093 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1094}
1095
fa1c114f
JS		 1096/***************\
1097* Buffers setup *
1098\***************/
1099
b6ea0356
BC		 1100static
1101struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1102{
1103 struct sk_buff *skb;
1104 unsigned int off;
1105
1106 /*
1107 * Allocate buffer with headroom_needed space for the
1108 * fake physical layer header at the start.
1109 */
1110 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1111
1112 if (!skb) {
1113 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1114 sc->rxbufsize + sc->cachelsz - 1);
1115 return NULL;
1116 }
1117 /*
1118 * Cache-line-align. This is important (for the
1119 * 5210 at least) as not doing so causes bogus data
1120 * in rx'd frames.
1121 */
1122 off = ((unsigned long)skb->data) % sc->cachelsz;
1123 if (off != 0)
1124 skb_reserve(skb, sc->cachelsz - off);
1125
1126 *skb_addr = pci_map_single(sc->pdev,
1127 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1128 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1129 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1130 dev_kfree_skb(skb);
1131 return NULL;
1132 }
1133 return skb;
1134}
1135
fa1c114f
JS		 1136static int
1137ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1138{
1139 struct ath5k_hw *ah = sc->ah;
1140 struct sk_buff *skb = bf->skb;
1141 struct ath5k_desc *ds;
1142
b6ea0356
BC		 1143 if (!skb) {
1144 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1145 if (!skb)
fa1c114f 1146 return -ENOMEM;
fa1c114f 1147 bf->skb = skb;
fa1c114f
JS		 1148 }
1149
1150 /*
1151 * Setup descriptors. For receive we always terminate
1152 * the descriptor list with a self-linked entry so we'll
1153 * not get overrun under high load (as can happen with a
1154 * 5212 when ANI processing enables PHY error frames).
1155 *
1156 * To insure the last descriptor is self-linked we create
1157 * each descriptor as self-linked and add it to the end. As
1158 * each additional descriptor is added the previous self-linked
1159 * entry is ``fixed'' naturally. This should be safe even
1160 * if DMA is happening. When processing RX interrupts we
1161 * never remove/process the last, self-linked, entry on the
1162 * descriptor list. This insures the hardware always has
1163 * someplace to write a new frame.
1164 */
1165 ds = bf->desc;
1166 ds->ds_link = bf->daddr; /* link to self */
1167 ds->ds_data = bf->skbaddr;
c6e387a2 1168 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1169 skb_tailroom(skb), /* buffer size */
1170 0);
1171
1172 if (sc->rxlink != NULL)
1173 *sc->rxlink = bf->daddr;
1174 sc->rxlink = &ds->ds_link;
1175 return 0;
1176}
1177
1178static int
e039fa4a 1179ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1180{
1181 struct ath5k_hw *ah = sc->ah;
1182 struct ath5k_txq *txq = sc->txq;
1183 struct ath5k_desc *ds = bf->desc;
1184 struct sk_buff *skb = bf->skb;
a888d52d 1185 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1186 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1187 struct ieee80211_rate *rate;
1188 unsigned int mrr_rate[3], mrr_tries[3];
1189 int i, ret;
8902ff4e 1190 u16 hw_rate;
07c1e852
BC		 1191 u16 cts_rate = 0;
1192 u16 duration = 0;
8902ff4e 1193 u8 rc_flags;
fa1c114f
JS		 1194
1195 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1196
fa1c114f
JS		 1197 /* XXX endianness */
1198 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1199 PCI_DMA_TODEVICE);
1200
8902ff4e
BC		 1201 rate = ieee80211_get_tx_rate(sc->hw, info);
1202
e039fa4a 1203 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1204 flags |= AR5K_TXDESC_NOACK;
1205
8902ff4e
BC		 1206 rc_flags = info->control.rates[0].flags;
1207 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1208 rate->hw_value_short : rate->hw_value;
1209
281c56dd 1210 pktlen = skb->len;
fa1c114f 1211
362695e1
BC		 1212 if (info->control.hw_key) {
1213 keyidx = info->control.hw_key->hw_key_idx;
1214 pktlen += info->control.hw_key->icv_len;
1215 }
07c1e852
BC		 1216 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1217 flags |= AR5K_TXDESC_RTSENA;
1218 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1219 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1220 sc->vif, pktlen, info));
1221 }
1222 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1223 flags |= AR5K_TXDESC_CTSENA;
1224 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1225 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1226 sc->vif, pktlen, info));
1227 }
fa1c114f
JS		 1228 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1229 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1230 (sc->power_level * 2),
8902ff4e 1231 hw_rate,
07c1e852
BC		 1232 info->control.rates[0].count, keyidx, 0, flags,
1233 cts_rate, duration);
fa1c114f
JS		 1234 if (ret)
1235 goto err_unmap;
1236
2f7fe870
FF		 1237 memset(mrr_rate, 0, sizeof(mrr_rate));
1238 memset(mrr_tries, 0, sizeof(mrr_tries));
1239 for (i = 0; i < 3; i++) {
1240 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1241 if (!rate)
1242 break;
1243
1244 mrr_rate[i] = rate->hw_value;
e6a9854b 1245 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1246 }
1247
1248 ah->ah_setup_mrr_tx_desc(ah, ds,
1249 mrr_rate[0], mrr_tries[0],
1250 mrr_rate[1], mrr_tries[1],
1251 mrr_rate[2], mrr_tries[2]);
1252
fa1c114f
JS		 1253 ds->ds_link = 0;
1254 ds->ds_data = bf->skbaddr;
1255
1256 spin_lock_bh(&txq->lock);
1257 list_add_tail(&bf->list, &txq->q);
57ffc589 1258 sc->tx_stats[txq->qnum].len++;
fa1c114f 1259 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1260 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1261 else /* no, so only link it */
1262 *txq->link = bf->daddr;
1263
1264 txq->link = &ds->ds_link;
c6e387a2 1265 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1266 mmiowb();
fa1c114f
JS		 1267 spin_unlock_bh(&txq->lock);
1268
1269 return 0;
1270err_unmap:
1271 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1272 return ret;
1273}
1274
1275/*******************\
1276* Descriptors setup *
1277\*******************/
1278
1279static int
1280ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1281{
1282 struct ath5k_desc *ds;
1283 struct ath5k_buf *bf;
1284 dma_addr_t da;
1285 unsigned int i;
1286 int ret;
1287
1288 /* allocate descriptors */
1289 sc->desc_len = sizeof(struct ath5k_desc) *
1290 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1291 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1292 if (sc->desc == NULL) {
1293 ATH5K_ERR(sc, "can't allocate descriptors\n");
1294 ret = -ENOMEM;
1295 goto err;
1296 }
1297 ds = sc->desc;
1298 da = sc->desc_daddr;
1299 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1300 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1301
1302 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1303 sizeof(struct ath5k_buf), GFP_KERNEL);
1304 if (bf == NULL) {
1305 ATH5K_ERR(sc, "can't allocate bufptr\n");
1306 ret = -ENOMEM;
1307 goto err_free;
1308 }
1309 sc->bufptr = bf;
1310
1311 INIT_LIST_HEAD(&sc->rxbuf);
1312 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1313 bf->desc = ds;
1314 bf->daddr = da;
1315 list_add_tail(&bf->list, &sc->rxbuf);
1316 }
1317
1318 INIT_LIST_HEAD(&sc->txbuf);
1319 sc->txbuf_len = ATH_TXBUF;
1320 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1321 da += sizeof(*ds)) {
1322 bf->desc = ds;
1323 bf->daddr = da;
1324 list_add_tail(&bf->list, &sc->txbuf);
1325 }
1326
1327 /* beacon buffer */
1328 bf->desc = ds;
1329 bf->daddr = da;
1330 sc->bbuf = bf;
1331
1332 return 0;
1333err_free:
1334 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1335err:
1336 sc->desc = NULL;
1337 return ret;
1338}
1339
1340static void
1341ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1342{
1343 struct ath5k_buf *bf;
1344
1345 ath5k_txbuf_free(sc, sc->bbuf);
1346 list_for_each_entry(bf, &sc->txbuf, list)
1347 ath5k_txbuf_free(sc, bf);
1348 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1349 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1350
1351 /* Free memory associated with all descriptors */
1352 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1353
1354 kfree(sc->bufptr);
1355 sc->bufptr = NULL;
1356}
1357
1358
1359
1360
1361
1362/**************\
1363* Queues setup *
1364\**************/
1365
1366static struct ath5k_txq *
1367ath5k_txq_setup(struct ath5k_softc *sc,
1368 int qtype, int subtype)
1369{
1370 struct ath5k_hw *ah = sc->ah;
1371 struct ath5k_txq *txq;
1372 struct ath5k_txq_info qi = {
1373 .tqi_subtype = subtype,
1374 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1375 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1376 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1377 };
1378 int qnum;
1379
1380 /*
1381 * Enable interrupts only for EOL and DESC conditions.
1382 * We mark tx descriptors to receive a DESC interrupt
1383 * when a tx queue gets deep; otherwise waiting for the
1384 * EOL to reap descriptors. Note that this is done to
1385 * reduce interrupt load and this only defers reaping
1386 * descriptors, never transmitting frames. Aside from
1387 * reducing interrupts this also permits more concurrency.
1388 * The only potential downside is if the tx queue backs
1389 * up in which case the top half of the kernel may backup
1390 * due to a lack of tx descriptors.
1391 */
1392 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1393 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1394 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1395 if (qnum < 0) {
1396 /*
1397 * NB: don't print a message, this happens
1398 * normally on parts with too few tx queues
1399 */
1400 return ERR_PTR(qnum);
1401 }
1402 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1403 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1404 qnum, ARRAY_SIZE(sc->txqs));
1405 ath5k_hw_release_tx_queue(ah, qnum);
1406 return ERR_PTR(-EINVAL);
1407 }
1408 txq = &sc->txqs[qnum];
1409 if (!txq->setup) {
1410 txq->qnum = qnum;
1411 txq->link = NULL;
1412 INIT_LIST_HEAD(&txq->q);
1413 spin_lock_init(&txq->lock);
1414 txq->setup = true;
1415 }
1416 return &sc->txqs[qnum];
1417}
1418
1419static int
1420ath5k_beaconq_setup(struct ath5k_hw *ah)
1421{
1422 struct ath5k_txq_info qi = {
1423 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1424 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1425 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1426 /* NB: for dynamic turbo, don't enable any other interrupts */
1427 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1428 };
1429
1430 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1431}
1432
1433static int
1434ath5k_beaconq_config(struct ath5k_softc *sc)
1435{
1436 struct ath5k_hw *ah = sc->ah;
1437 struct ath5k_txq_info qi;
1438 int ret;
1439
1440 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1441 if (ret)
1442 return ret;
05c914fe
JB		 1443 if (sc->opmode == NL80211_IFTYPE_AP ||
1444 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1445 /*
1446 * Always burst out beacon and CAB traffic
1447 * (aifs = cwmin = cwmax = 0)
1448 */
1449 qi.tqi_aifs = 0;
1450 qi.tqi_cw_min = 0;
1451 qi.tqi_cw_max = 0;
05c914fe 1452 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1453 /*
1454 * Adhoc mode; backoff between 0 and (2 * cw_min).
1455 */
1456 qi.tqi_aifs = 0;
1457 qi.tqi_cw_min = 0;
1458 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1459 }
1460
6d91e1d8
BR		 1461 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1462 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1463 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1464
c6e387a2 1465 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1466 if (ret) {
1467 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1468 "hardware queue!\n", __func__);
1469 return ret;
1470 }
1471
1472 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1473}
1474
1475static void
1476ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1477{
1478 struct ath5k_buf *bf, *bf0;
1479
1480 /*
1481 * NB: this assumes output has been stopped and
1482 * we do not need to block ath5k_tx_tasklet
1483 */
1484 spin_lock_bh(&txq->lock);
1485 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1486 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1487
1488 ath5k_txbuf_free(sc, bf);
1489
1490 spin_lock_bh(&sc->txbuflock);
57ffc589 1491 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1492 list_move_tail(&bf->list, &sc->txbuf);
1493 sc->txbuf_len++;
1494 spin_unlock_bh(&sc->txbuflock);
1495 }
1496 txq->link = NULL;
1497 spin_unlock_bh(&txq->lock);
1498}
1499
1500/*
1501 * Drain the transmit queues and reclaim resources.
1502 */
1503static void
1504ath5k_txq_cleanup(struct ath5k_softc *sc)
1505{
1506 struct ath5k_hw *ah = sc->ah;
1507 unsigned int i;
1508
1509 /* XXX return value */
1510 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1511 /* don't touch the hardware if marked invalid */
1512 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1513 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1514 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1515 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1516 if (sc->txqs[i].setup) {
1517 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1518 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1519 "link %p\n",
1520 sc->txqs[i].qnum,
c6e387a2 1521 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1522 sc->txqs[i].qnum),
1523 sc->txqs[i].link);
1524 }
1525 }
36d6825b 1526 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1527
1528 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1529 if (sc->txqs[i].setup)
1530 ath5k_txq_drainq(sc, &sc->txqs[i]);
1531}
1532
1533static void
1534ath5k_txq_release(struct ath5k_softc *sc)
1535{
1536 struct ath5k_txq *txq = sc->txqs;
1537 unsigned int i;
1538
1539 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1540 if (txq->setup) {
1541 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1542 txq->setup = false;
1543 }
1544}
1545
1546
1547
1548
1549/*************\
1550* RX Handling *
1551\*************/
1552
1553/*
1554 * Enable the receive h/w following a reset.
1555 */
1556static int
1557ath5k_rx_start(struct ath5k_softc *sc)
1558{
1559 struct ath5k_hw *ah = sc->ah;
1560 struct ath5k_buf *bf;
1561 int ret;
1562
1563 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1564
1565 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1566 sc->cachelsz, sc->rxbufsize);
1567
1568 sc->rxlink = NULL;
1569
1570 spin_lock_bh(&sc->rxbuflock);
1571 list_for_each_entry(bf, &sc->rxbuf, list) {
1572 ret = ath5k_rxbuf_setup(sc, bf);
1573 if (ret != 0) {
1574 spin_unlock_bh(&sc->rxbuflock);
1575 goto err;
1576 }
1577 }
1578 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1579 spin_unlock_bh(&sc->rxbuflock);
1580
c6e387a2
NK		 1581 ath5k_hw_set_rxdp(ah, bf->daddr);
1582 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1583 ath5k_mode_setup(sc); /* set filters, etc. */
1584 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1585
1586 return 0;
1587err:
1588 return ret;
1589}
1590
1591/*
1592 * Disable the receive h/w in preparation for a reset.
1593 */
1594static void
1595ath5k_rx_stop(struct ath5k_softc *sc)
1596{
1597 struct ath5k_hw *ah = sc->ah;
1598
c6e387a2 1599 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1600 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1601 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1602
1603 ath5k_debug_printrxbuffs(sc, ah);
1604
1605 sc->rxlink = NULL; /* just in case */
1606}
1607
1608static unsigned int
1609ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1610 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1611{
1612 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1613 unsigned int keyix, hlen;
fa1c114f 1614
b47f407b
BR		 1615 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1616 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1617 return RX_FLAG_DECRYPTED;
1618
1619 /* Apparently when a default key is used to decrypt the packet
1620 the hw does not set the index used to decrypt. In such cases
1621 get the index from the packet. */
798ee985 1622 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1623 if (ieee80211_has_protected(hdr->frame_control) &&
1624 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1625 skb->len >= hlen + 4) {
fa1c114f
JS		 1626 keyix = skb->data[hlen + 3] >> 6;
1627
1628 if (test_bit(keyix, sc->keymap))
1629 return RX_FLAG_DECRYPTED;
1630 }
1631
1632 return 0;
1633}
1634
036cd1ec
BR		 1635
1636static void
6ba81c2c
BR		 1637ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1638 struct ieee80211_rx_status *rxs)
036cd1ec 1639{
6ba81c2c 1640 u64 tsf, bc_tstamp;
036cd1ec
BR		 1641 u32 hw_tu;
1642 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1643
24b56e70 1644 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1645 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1646 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1647 /*
6ba81c2c
BR		 1648 * Received an IBSS beacon with the same BSSID. Hardware *must*
1649 * have updated the local TSF. We have to work around various
1650 * hardware bugs, though...
036cd1ec 1651 */
6ba81c2c
BR		 1652 tsf = ath5k_hw_get_tsf64(sc->ah);
1653 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1654 hw_tu = TSF_TO_TU(tsf);
1655
1656 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1657 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1658 (unsigned long long)bc_tstamp,
1659 (unsigned long long)rxs->mactime,
1660 (unsigned long long)(rxs->mactime - bc_tstamp),
1661 (unsigned long long)tsf);
6ba81c2c
BR		 1662
1663 /*
1664 * Sometimes the HW will give us a wrong tstamp in the rx
1665 * status, causing the timestamp extension to go wrong.
1666 * (This seems to happen especially with beacon frames bigger
1667 * than 78 byte (incl. FCS))
1668 * But we know that the receive timestamp must be later than the
1669 * timestamp of the beacon since HW must have synced to that.
1670 *
1671 * NOTE: here we assume mactime to be after the frame was
1672 * received, not like mac80211 which defines it at the start.
1673 */
1674 if (bc_tstamp > rxs->mactime) {
036cd1ec 1675 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1676 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1677 (unsigned long long)rxs->mactime,
1678 (unsigned long long)tsf);
6ba81c2c 1679 rxs->mactime = tsf;
036cd1ec 1680 }
6ba81c2c
BR		 1681
1682 /*
1683 * Local TSF might have moved higher than our beacon timers,
1684 * in that case we have to update them to continue sending
1685 * beacons. This also takes care of synchronizing beacon sending
1686 * times with other stations.
1687 */
1688 if (hw_tu >= sc->nexttbtt)
1689 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1690 }
1691}
1692
acf3c1a5
BC		 1693static void ath5k_tasklet_beacon(unsigned long data)
1694{
1695 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1696
1697 /*
1698 * Software beacon alert--time to send a beacon.
1699 *
1700 * In IBSS mode we use this interrupt just to
1701 * keep track of the next TBTT (target beacon
1702 * transmission time) in order to detect wether
1703 * automatic TSF updates happened.
1704 */
1705 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1706 /* XXX: only if VEOL suppported */
1707 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1708 sc->nexttbtt += sc->bintval;
1709 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1710 "SWBA nexttbtt: %x hw_tu: %x "
1711 "TSF: %llx\n",
1712 sc->nexttbtt,
1713 TSF_TO_TU(tsf),
1714 (unsigned long long) tsf);
1715 } else {
1716 spin_lock(&sc->block);
1717 ath5k_beacon_send(sc);
1718 spin_unlock(&sc->block);
1719 }
1720}
1721
fa1c114f
JS		 1722static void
1723ath5k_tasklet_rx(unsigned long data)
1724{
1725 struct ieee80211_rx_status rxs = {};
b47f407b 1726 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1727 struct sk_buff *skb, *next_skb;
1728 dma_addr_t next_skb_addr;
fa1c114f 1729 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1730 struct ath5k_buf *bf, *bf_last;
fa1c114f 1731 struct ath5k_desc *ds;
fa1c114f
JS		 1732 int ret;
1733 int hdrlen;
0fe45b1d 1734 int padsize;
fa1c114f
JS		 1735
1736 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1737 if (list_empty(&sc->rxbuf)) {
1738 ATH5K_WARN(sc, "empty rx buf pool\n");
1739 goto unlock;
1740 }
1741 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1742 do {
d6894b5b
BC		 1743 rxs.flag = 0;
1744
fa1c114f
JS		 1745 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1746 BUG_ON(bf->skb == NULL);
1747 skb = bf->skb;
1748 ds = bf->desc;
1749
3a0f2c87
JS		 1750 /*
1751 * last buffer must not be freed to ensure proper hardware
1752 * function. When the hardware finishes also a packet next to
1753 * it, we are sure, it doesn't use it anymore and we can go on.
1754 */
1755 if (bf_last == bf)
1756 bf->flags |= 1;
1757 if (bf->flags) {
1758 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1759 struct ath5k_buf, list);
1760 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1761 &rs);
1762 if (ret)
1763 break;
1764 bf->flags &= ~1;
1765 /* skip the overwritten one (even status is martian) */
1766 goto next;
1767 }
fa1c114f 1768
b47f407b 1769 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1770 if (unlikely(ret == -EINPROGRESS))
1771 break;
1772 else if (unlikely(ret)) {
1773 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1774 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1775 return;
1776 }
1777
b47f407b 1778 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1779 ATH5K_WARN(sc, "unsupported jumbo\n");
1780 goto next;
1781 }
1782
b47f407b
BR		 1783 if (unlikely(rs.rs_status)) {
1784 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1785 goto next;
b47f407b 1786 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1787 /*
1788 * Decrypt error. If the error occurred
1789 * because there was no hardware key, then
1790 * let the frame through so the upper layers
1791 * can process it. This is necessary for 5210
1792 * parts which have no way to setup a ``clear''
1793 * key cache entry.
1794 *
1795 * XXX do key cache faulting
1796 */
b47f407b
BR		 1797 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1798 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1799 goto accept;
1800 }
b47f407b 1801 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1802 rxs.flag |= RX_FLAG_MMIC_ERROR;
1803 goto accept;
1804 }
1805
1806 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1807 if ((rs.rs_status &
1808 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1809 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1810 goto next;
1811 }
1812accept:
b6ea0356
BC		 1813 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1814
1815 /*
1816 * If we can't replace bf->skb with a new skb under memory
1817 * pressure, just skip this packet
1818 */
1819 if (!next_skb)
1820 goto next;
1821
fa1c114f
JS		 1822 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1823 PCI_DMA_FROMDEVICE);
b47f407b 1824 skb_put(skb, rs.rs_datalen);
fa1c114f 1825
0fe45b1d
BP		 1826 /* The MAC header is padded to have 32-bit boundary if the
1827 * packet payload is non-zero. The general calculation for
1828 * padsize would take into account odd header lengths:
1829 * padsize = (4 - hdrlen % 4) % 4; However, since only
1830 * even-length headers are used, padding can only be 0 or 2
1831 * bytes and we can optimize this a bit. In addition, we must
1832 * not try to remove padding from short control frames that do
1833 * not have payload. */
fa1c114f 1834 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1835 padsize = ath5k_pad_size(hdrlen);
1836 if (padsize) {
0fe45b1d
BP		 1837 memmove(skb->data + padsize, skb->data, hdrlen);
1838 skb_pull(skb, padsize);
fa1c114f
JS		 1839 }
1840
c0e1899b
BR		 1841 /*
1842 * always extend the mac timestamp, since this information is
1843 * also needed for proper IBSS merging.
1844 *
1845 * XXX: it might be too late to do it here, since rs_tstamp is
1846 * 15bit only. that means TSF extension has to be done within
1847 * 32768usec (about 32ms). it might be necessary to move this to
1848 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1849 *
1850 * Unfortunately we don't know when the hardware takes the rx
1851 * timestamp (beginning of phy frame, data frame, end of rx?).
1852 * The only thing we know is that it is hardware specific...
1853 * On AR5213 it seems the rx timestamp is at the end of the
1854 * frame, but i'm not sure.
1855 *
1856 * NOTE: mac80211 defines mactime at the beginning of the first
1857 * data symbol. Since we don't have any time references it's
1858 * impossible to comply to that. This affects IBSS merge only
1859 * right now, so it's not too bad...
c0e1899b 1860 */
b47f407b 1861 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1862 rxs.flag |= RX_FLAG_TSFT;
1863
d8ee398d
LR		 1864 rxs.freq = sc->curchan->center_freq;
1865 rxs.band = sc->curband->band;
fa1c114f 1866
fa1c114f 1867 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1868 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1869
1870 /* An rssi of 35 indicates you should be able use
1871 * 54 Mbps reliably. A more elaborate scheme can be used
1872 * here but it requires a map of SNR/throughput for each
1873 * possible mode used */
1874 rxs.qual = rs.rs_rssi * 100 / 35;
1875
1876 /* rssi can be more than 35 though, anything above that
1877 * should be considered at 100% */
1878 if (rxs.qual > 100)
1879 rxs.qual = 100;
fa1c114f 1880
b47f407b
BR		 1881 rxs.antenna = rs.rs_antenna;
1882 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1883 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1884
06303352
BR		 1885 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1886 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1887 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1888
fa1c114f
JS		 1889 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1890
036cd1ec 1891 /* check beacons in IBSS mode */
05c914fe 1892 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1893 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1894
fa1c114f 1895 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1896
1897 bf->skb = next_skb;
1898 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1899next:
1900 list_move_tail(&bf->list, &sc->rxbuf);
1901 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1902unlock:
fa1c114f
JS		 1903 spin_unlock(&sc->rxbuflock);
1904}
1905
1906
1907
1908
1909/*************\
1910* TX Handling *
1911\*************/
1912
1913static void
1914ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1915{
b47f407b 1916 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1917 struct ath5k_buf *bf, *bf0;
1918 struct ath5k_desc *ds;
1919 struct sk_buff *skb;
e039fa4a 1920 struct ieee80211_tx_info *info;
2f7fe870 1921 int i, ret;
fa1c114f
JS		 1922
1923 spin_lock(&txq->lock);
1924 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1925 ds = bf->desc;
1926
b47f407b 1927 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1928 if (unlikely(ret == -EINPROGRESS))
1929 break;
1930 else if (unlikely(ret)) {
1931 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1932 ret, txq->qnum);
1933 break;
1934 }
1935
1936 skb = bf->skb;
a888d52d 1937 info = IEEE80211_SKB_CB(skb);
fa1c114f 1938 bf->skb = NULL;
e039fa4a 1939
fa1c114f
JS		 1940 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1941 PCI_DMA_TODEVICE);
1942
e6a9854b 1943 ieee80211_tx_info_clear_status(info);
2f7fe870 1944 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1945 struct ieee80211_tx_rate *r =
1946 &info->status.rates[i];
2f7fe870
FF		 1947
1948 if (ts.ts_rate[i]) {
e6a9854b
JB		 1949 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1950 r->count = ts.ts_retry[i];
2f7fe870 1951 } else {
e6a9854b
JB		 1952 r->idx = -1;
1953 r->count = 0;
2f7fe870
FF		 1954 }
1955 }
1956
e6a9854b
JB		 1957 /* count the successful attempt as well */
1958 info->status.rates[ts.ts_final_idx].count++;
1959
b47f407b 1960 if (unlikely(ts.ts_status)) {
fa1c114f 1961 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1962 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1963 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1964 } else {
e039fa4a
JB		 1965 info->flags |= IEEE80211_TX_STAT_ACK;
1966 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1967 }
1968
e039fa4a 1969 ieee80211_tx_status(sc->hw, skb);
57ffc589 1970 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1971
1972 spin_lock(&sc->txbuflock);
57ffc589 1973 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1974 list_move_tail(&bf->list, &sc->txbuf);
1975 sc->txbuf_len++;
1976 spin_unlock(&sc->txbuflock);
1977 }
1978 if (likely(list_empty(&txq->q)))
1979 txq->link = NULL;
1980 spin_unlock(&txq->lock);
1981 if (sc->txbuf_len > ATH_TXBUF / 5)
1982 ieee80211_wake_queues(sc->hw);
1983}
1984
1985static void
1986ath5k_tasklet_tx(unsigned long data)
1987{
1988 struct ath5k_softc *sc = (void *)data;
1989
1990 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1991}
1992
1993
fa1c114f
JS		 1994/*****************\
1995* Beacon handling *
1996\*****************/
1997
1998/*
1999 * Setup the beacon frame for transmit.
2000 */
2001static int
e039fa4a 2002ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2003{
2004 struct sk_buff *skb = bf->skb;
a888d52d 2005 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2006 struct ath5k_hw *ah = sc->ah;
2007 struct ath5k_desc *ds;
2008 int ret, antenna = 0;
2009 u32 flags;
2010
2011 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2012 PCI_DMA_TODEVICE);
2013 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2014 "skbaddr %llx\n", skb, skb->data, skb->len,
2015 (unsigned long long)bf->skbaddr);
8d8bb39b 2016 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2017 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2018 return -EIO;
2019 }
2020
2021 ds = bf->desc;
2022
2023 flags = AR5K_TXDESC_NOACK;
05c914fe 2024 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2025 ds->ds_link = bf->daddr; /* self-linked */
2026 flags |= AR5K_TXDESC_VEOL;
2027 /*
2028 * Let hardware handle antenna switching if txantenna is not set
2029 */
2030 } else {
2031 ds->ds_link = 0;
2032 /*
2033 * Switch antenna every 4 beacons if txantenna is not set
2034 * XXX assumes two antennas
2035 */
2036 if (antenna == 0)
2037 antenna = sc->bsent & 4 ? 2 : 1;
2038 }
2039
2040 ds->ds_data = bf->skbaddr;
281c56dd 2041 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2042 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2043 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2044 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2045 1, AR5K_TXKEYIX_INVALID,
400ec45a 2046 antenna, flags, 0, 0);
fa1c114f
JS		 2047 if (ret)
2048 goto err_unmap;
2049
2050 return 0;
2051err_unmap:
2052 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2053 return ret;
2054}
2055
2056/*
2057 * Transmit a beacon frame at SWBA. Dynamic updates to the
2058 * frame contents are done as needed and the slot time is
2059 * also adjusted based on current state.
2060 *
acf3c1a5
BC		 2061 * This is called from software irq context (beacontq or restq
2062 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2063 */
2064static void
2065ath5k_beacon_send(struct ath5k_softc *sc)
2066{
2067 struct ath5k_buf *bf = sc->bbuf;
2068 struct ath5k_hw *ah = sc->ah;
2069
be9b7259 2070 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2071
05c914fe
JB		 2072 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2073 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2074 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2075 return;
2076 }
2077 /*
2078 * Check if the previous beacon has gone out. If
2079 * not don't don't try to post another, skip this
2080 * period and wait for the next. Missed beacons
2081 * indicate a problem and should not occur. If we
2082 * miss too many consecutive beacons reset the device.
2083 */
2084 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2085 sc->bmisscount++;
be9b7259 2086 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2087 "missed %u consecutive beacons\n", sc->bmisscount);
2088 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2089 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2090 "stuck beacon time (%u missed)\n",
2091 sc->bmisscount);
2092 tasklet_schedule(&sc->restq);
2093 }
2094 return;
2095 }
2096 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2097 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2098 "resume beacon xmit after %u misses\n",
2099 sc->bmisscount);
2100 sc->bmisscount = 0;
2101 }
2102
2103 /*
2104 * Stop any current dma and put the new frame on the queue.
2105 * This should never fail since we check above that no frames
2106 * are still pending on the queue.
2107 */
2108 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2109 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2110 /* NB: hw still stops DMA, so proceed */
2111 }
fa1c114f 2112
c6e387a2
NK		 2113 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2114 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2115 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2116 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2117
2118 sc->bsent++;
2119}
2120
2121
9804b98d
BR		 2122/**
2123 * ath5k_beacon_update_timers - update beacon timers
2124 *
2125 * @sc: struct ath5k_softc pointer we are operating on
2126 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2127 * beacon timer update based on the current HW TSF.
2128 *
2129 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2130 * of a received beacon or the current local hardware TSF and write it to the
2131 * beacon timer registers.
2132 *
2133 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2134 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2135 * when we otherwise know we have to update the timers, but we keep it in this
2136 * function to have it all together in one place.
2137 */
fa1c114f 2138static void
9804b98d 2139ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2140{
2141 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2142 u32 nexttbtt, intval, hw_tu, bc_tu;
2143 u64 hw_tsf;
fa1c114f
JS		 2144
2145 intval = sc->bintval & AR5K_BEACON_PERIOD;
2146 if (WARN_ON(!intval))
2147 return;
2148
9804b98d
BR		 2149 /* beacon TSF converted to TU */
2150 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2151
9804b98d
BR		 2152 /* current TSF converted to TU */
2153 hw_tsf = ath5k_hw_get_tsf64(ah);
2154 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2155
9804b98d
BR		 2156#define FUDGE 3
2157 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2158 if (bc_tsf == -1) {
2159 /*
2160 * no beacons received, called internally.
2161 * just need to refresh timers based on HW TSF.
2162 */
2163 nexttbtt = roundup(hw_tu + FUDGE, intval);
2164 } else if (bc_tsf == 0) {
2165 /*
2166 * no beacon received, probably called by ath5k_reset_tsf().
2167 * reset TSF to start with 0.
2168 */
2169 nexttbtt = intval;
2170 intval |= AR5K_BEACON_RESET_TSF;
2171 } else if (bc_tsf > hw_tsf) {
2172 /*
2173 * beacon received, SW merge happend but HW TSF not yet updated.
2174 * not possible to reconfigure timers yet, but next time we
2175 * receive a beacon with the same BSSID, the hardware will
2176 * automatically update the TSF and then we need to reconfigure
2177 * the timers.
2178 */
2179 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2180 "need to wait for HW TSF sync\n");
2181 return;
2182 } else {
2183 /*
2184 * most important case for beacon synchronization between STA.
2185 *
2186 * beacon received and HW TSF has been already updated by HW.
2187 * update next TBTT based on the TSF of the beacon, but make
2188 * sure it is ahead of our local TSF timer.
2189 */
2190 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2191 }
2192#undef FUDGE
fa1c114f 2193
036cd1ec
BR		 2194 sc->nexttbtt = nexttbtt;
2195
fa1c114f 2196 intval |= AR5K_BEACON_ENA;
fa1c114f 2197 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2198
2199 /*
2200 * debugging output last in order to preserve the time critical aspect
2201 * of this function
2202 */
2203 if (bc_tsf == -1)
2204 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2205 "reconfigured timers based on HW TSF\n");
2206 else if (bc_tsf == 0)
2207 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2208 "reset HW TSF and timers\n");
2209 else
2210 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2211 "updated timers based on beacon TSF\n");
2212
2213 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2214 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2215 (unsigned long long) bc_tsf,
2216 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2217 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2218 intval & AR5K_BEACON_PERIOD,
2219 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2220 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2221}
2222
2223
036cd1ec
BR		 2224/**
2225 * ath5k_beacon_config - Configure the beacon queues and interrupts
2226 *
2227 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2228 *
036cd1ec 2229 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2230 * interrupts to detect TSF updates only.
fa1c114f
JS		 2231 */
2232static void
2233ath5k_beacon_config(struct ath5k_softc *sc)
2234{
2235 struct ath5k_hw *ah = sc->ah;
b5f03956 2236 unsigned long flags;
fa1c114f 2237
c6e387a2 2238 ath5k_hw_set_imr(ah, 0);
fa1c114f 2239 sc->bmisscount = 0;
dc1968e7 2240 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2241
1e3e6e8f 2242 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2243 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2244 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2245 /*
036cd1ec
BR		 2246 * In IBSS mode we use a self-linked tx descriptor and let the
2247 * hardware send the beacons automatically. We have to load it
fa1c114f 2248 * only once here.
036cd1ec 2249 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2250 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2251 */
2252 ath5k_beaconq_config(sc);
fa1c114f 2253
036cd1ec
BR		 2254 sc->imask |= AR5K_INT_SWBA;
2255
da966bca
JS		 2256 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2257 if (ath5k_hw_hasveol(ah)) {
b5f03956 2258 spin_lock_irqsave(&sc->block, flags);
da966bca 2259 ath5k_beacon_send(sc);
b5f03956 2260 spin_unlock_irqrestore(&sc->block, flags);
da966bca
JS		 2261 }
2262 } else
2263 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2264 }
fa1c114f 2265
c6e387a2 2266 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2267}
2268
2269
2270/********************\
2271* Interrupt handling *
2272\********************/
2273
2274static int
bb2becac 2275ath5k_init(struct ath5k_softc *sc)
fa1c114f 2276{
bc1b32d6
EO		 2277 struct ath5k_hw *ah = sc->ah;
2278 int ret, i;
fa1c114f
JS		 2279
2280 mutex_lock(&sc->lock);
2281
2282 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2283
2284 /*
2285 * Stop anything previously setup. This is safe
2286 * no matter this is the first time through or not.
2287 */
2288 ath5k_stop_locked(sc);
2289
2290 /*
2291 * The basic interface to setting the hardware in a good
2292 * state is ``reset''. On return the hardware is known to
2293 * be powered up and with interrupts disabled. This must
2294 * be followed by initialization of the appropriate bits
2295 * and then setup of the interrupt mask.
2296 */
d8ee398d
LR		 2297 sc->curchan = sc->hw->conf.channel;
2298 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2299 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2300 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
9ca9fb8a 2301 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
d7dc1003
JS		 2302 ret = ath5k_reset(sc, false, false);
2303 if (ret)
2304 goto done;
fa1c114f 2305
bc1b32d6
EO		 2306 /*
2307 * Reset the key cache since some parts do not reset the
2308 * contents on initial power up or resume from suspend.
2309 */
2310 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2311 ath5k_hw_reset_key(ah, i);
2312
fa1c114f 2313 /* Set ack to be sent at low bit-rates */
bc1b32d6 2314 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2315
2316 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2317 msecs_to_jiffies(ath5k_calinterval * 1000)));
2318
2319 ret = 0;
2320done:
274c7c36 2321 mmiowb();
fa1c114f
JS		 2322 mutex_unlock(&sc->lock);
2323 return ret;
2324}
2325
2326static int
2327ath5k_stop_locked(struct ath5k_softc *sc)
2328{
2329 struct ath5k_hw *ah = sc->ah;
2330
2331 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2332 test_bit(ATH_STAT_INVALID, sc->status));
2333
2334 /*
2335 * Shutdown the hardware and driver:
2336 * stop output from above
2337 * disable interrupts
2338 * turn off timers
2339 * turn off the radio
2340 * clear transmit machinery
2341 * clear receive machinery
2342 * drain and release tx queues
2343 * reclaim beacon resources
2344 * power down hardware
2345 *
2346 * Note that some of this work is not possible if the
2347 * hardware is gone (invalid).
2348 */
2349 ieee80211_stop_queues(sc->hw);
2350
2351 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2352 ath5k_led_off(sc);
c6e387a2 2353 ath5k_hw_set_imr(ah, 0);
274c7c36 2354 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2355 }
2356 ath5k_txq_cleanup(sc);
2357 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2358 ath5k_rx_stop(sc);
2359 ath5k_hw_phy_disable(ah);
2360 } else
2361 sc->rxlink = NULL;
2362
2363 return 0;
2364}
2365
2366/*
2367 * Stop the device, grabbing the top-level lock to protect
2368 * against concurrent entry through ath5k_init (which can happen
2369 * if another thread does a system call and the thread doing the
2370 * stop is preempted).
2371 */
2372static int
bb2becac 2373ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2374{
2375 int ret;
2376
2377 mutex_lock(&sc->lock);
2378 ret = ath5k_stop_locked(sc);
2379 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2380 /*
2381 * Set the chip in full sleep mode. Note that we are
2382 * careful to do this only when bringing the interface
2383 * completely to a stop. When the chip is in this state
2384 * it must be carefully woken up or references to
2385 * registers in the PCI clock domain may freeze the bus
2386 * (and system). This varies by chip and is mostly an
2387 * issue with newer parts that go to sleep more quickly.
2388 */
2389 if (sc->ah->ah_mac_srev >= 0x78) {
2390 /*
2391 * XXX
2392 * don't put newer MAC revisions > 7.8 to sleep because
2393 * of the above mentioned problems
2394 */
2395 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2396 "not putting device to sleep\n");
2397 } else {
2398 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2399 "putting device to full sleep\n");
2400 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2401 }
2402 }
2403 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2404
274c7c36 2405 mmiowb();
fa1c114f
JS		 2406 mutex_unlock(&sc->lock);
2407
2408 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2409 tasklet_kill(&sc->rxtq);
2410 tasklet_kill(&sc->txtq);
2411 tasklet_kill(&sc->restq);
acf3c1a5 2412 tasklet_kill(&sc->beacontq);
fa1c114f
JS		 2413
2414 return ret;
2415}
2416
2417static irqreturn_t
2418ath5k_intr(int irq, void *dev_id)
2419{
2420 struct ath5k_softc *sc = dev_id;
2421 struct ath5k_hw *ah = sc->ah;
2422 enum ath5k_int status;
2423 unsigned int counter = 1000;
2424
2425 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2426 !ath5k_hw_is_intr_pending(ah)))
2427 return IRQ_NONE;
2428
2429 do {
fa1c114f
JS		 2430 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2431 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2432 status, sc->imask);
fa1c114f
JS		 2433 if (unlikely(status & AR5K_INT_FATAL)) {
2434 /*
2435 * Fatal errors are unrecoverable.
2436 * Typically these are caused by DMA errors.
2437 */
2438 tasklet_schedule(&sc->restq);
2439 } else if (unlikely(status & AR5K_INT_RXORN)) {
2440 tasklet_schedule(&sc->restq);
2441 } else {
2442 if (status & AR5K_INT_SWBA) {
acf3c1a5 2443 tasklet_schedule(&sc->beacontq);
fa1c114f
JS		 2444 }
2445 if (status & AR5K_INT_RXEOL) {
2446 /*
2447 * NB: the hardware should re-read the link when
2448 * RXE bit is written, but it doesn't work at
2449 * least on older hardware revs.
2450 */
2451 sc->rxlink = NULL;
2452 }
2453 if (status & AR5K_INT_TXURN) {
2454 /* bump tx trigger level */
2455 ath5k_hw_update_tx_triglevel(ah, true);
2456 }
4c674c60 2457 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2458 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2459 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2460 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2461 tasklet_schedule(&sc->txtq);
2462 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2463 /* TODO */
fa1c114f
JS		 2464 }
2465 if (status & AR5K_INT_MIB) {
194828a2
NK		 2466 /*
2467 * These stats are also used for ANI i think
2468 * so how about updating them more often ?
2469 */
2470 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2471 }
2472 }
2473 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2474
2475 if (unlikely(!counter))
2476 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2477
2478 return IRQ_HANDLED;
2479}
2480
2481static void
2482ath5k_tasklet_reset(unsigned long data)
2483{
2484 struct ath5k_softc *sc = (void *)data;
2485
d7dc1003 2486 ath5k_reset_wake(sc);
fa1c114f
JS		 2487}
2488
2489/*
2490 * Periodically recalibrate the PHY to account
2491 * for temperature/environment changes.
2492 */
2493static void
2494ath5k_calibrate(unsigned long data)
2495{
2496 struct ath5k_softc *sc = (void *)data;
2497 struct ath5k_hw *ah = sc->ah;
2498
2499 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2500 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2501 sc->curchan->hw_value);
fa1c114f 2502
6f3b414a 2503 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2504 /*
2505 * Rfgain is out of bounds, reset the chip
2506 * to load new gain values.
2507 */
2508 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2509 ath5k_reset_wake(sc);
fa1c114f
JS		 2510 }
2511 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2512 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2513 ieee80211_frequency_to_channel(
2514 sc->curchan->center_freq));
fa1c114f
JS		 2515
2516 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2517 msecs_to_jiffies(ath5k_calinterval * 1000)));
2518}
2519
2520
fa1c114f
JS		 2521/********************\
2522* Mac80211 functions *
2523\********************/
2524
2525static int
e039fa4a 2526ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2527{
2528 struct ath5k_softc *sc = hw->priv;
2529 struct ath5k_buf *bf;
2530 unsigned long flags;
2531 int hdrlen;
0fe45b1d 2532 int padsize;
fa1c114f
JS		 2533
2534 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2535
05c914fe 2536 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2537 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2538
2539 /*
2540 * the hardware expects the header padded to 4 byte boundaries
2541 * if this is not the case we add the padding after the header
2542 */
2543 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2544 padsize = ath5k_pad_size(hdrlen);
2545 if (padsize) {
0fe45b1d
BP		 2546
2547 if (skb_headroom(skb) < padsize) {
fa1c114f 2548 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2549 " headroom to pad %d\n", hdrlen, padsize);
71ef99c8 2550 return NETDEV_TX_BUSY;
fa1c114f 2551 }
0fe45b1d
BP		 2552 skb_push(skb, padsize);
2553 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2554 }
2555
fa1c114f
JS		 2556 spin_lock_irqsave(&sc->txbuflock, flags);
2557 if (list_empty(&sc->txbuf)) {
2558 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2559 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2560 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
71ef99c8 2561 return NETDEV_TX_BUSY;
fa1c114f
JS		 2562 }
2563 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2564 list_del(&bf->list);
2565 sc->txbuf_len--;
2566 if (list_empty(&sc->txbuf))
2567 ieee80211_stop_queues(hw);
2568 spin_unlock_irqrestore(&sc->txbuflock, flags);
2569
2570 bf->skb = skb;
2571
e039fa4a 2572 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2573 bf->skb = NULL;
2574 spin_lock_irqsave(&sc->txbuflock, flags);
2575 list_add_tail(&bf->list, &sc->txbuf);
2576 sc->txbuf_len++;
2577 spin_unlock_irqrestore(&sc->txbuflock, flags);
2578 dev_kfree_skb_any(skb);
71ef99c8 2579 return NETDEV_TX_OK;
fa1c114f
JS		 2580 }
2581
71ef99c8 2582 return NETDEV_TX_OK;
fa1c114f
JS		 2583}
2584
2585static int
d7dc1003 2586ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2587{
fa1c114f
JS		 2588 struct ath5k_hw *ah = sc->ah;
2589 int ret;
2590
2591 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2592
d7dc1003 2593 if (stop) {
c6e387a2 2594 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2595 ath5k_txq_cleanup(sc);
2596 ath5k_rx_stop(sc);
2597 }
fa1c114f 2598 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2599 if (ret) {
fa1c114f
JS		 2600 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2601 goto err;
2602 }
d7dc1003
JS		 2603
2604 /*
2605 * This is needed only to setup initial state
2606 * but it's best done after a reset.
2607 */
fa1c114f
JS		 2608 ath5k_hw_set_txpower_limit(sc->ah, 0);
2609
2610 ret = ath5k_rx_start(sc);
d7dc1003 2611 if (ret) {
fa1c114f
JS		 2612 ATH5K_ERR(sc, "can't start recv logic\n");
2613 goto err;
2614 }
d7dc1003 2615
fa1c114f 2616 /*
d7dc1003
JS		 2617 * Change channels and update the h/w rate map if we're switching;
2618 * e.g. 11a to 11b/g.
2619 *
2620 * We may be doing a reset in response to an ioctl that changes the
2621 * channel so update any state that might change as a result.
fa1c114f
JS		 2622 *
2623 * XXX needed?
2624 */
2625/* ath5k_chan_change(sc, c); */
fa1c114f 2626
d7dc1003
JS		 2627 ath5k_beacon_config(sc);
2628 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2629
2630 return 0;
2631err:
2632 return ret;
2633}
2634
d7dc1003
JS		 2635static int
2636ath5k_reset_wake(struct ath5k_softc *sc)
2637{
2638 int ret;
2639
2640 ret = ath5k_reset(sc, true, true);
2641 if (!ret)
2642 ieee80211_wake_queues(sc->hw);
2643
2644 return ret;
2645}
2646
fa1c114f
JS		 2647static int ath5k_start(struct ieee80211_hw *hw)
2648{
bb2becac 2649 return ath5k_init(hw->priv);
fa1c114f
JS		 2650}
2651
2652static void ath5k_stop(struct ieee80211_hw *hw)
2653{
bb2becac 2654 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2655}
2656
2657static int ath5k_add_interface(struct ieee80211_hw *hw,
2658 struct ieee80211_if_init_conf *conf)
2659{
2660 struct ath5k_softc *sc = hw->priv;
2661 int ret;
2662
2663 mutex_lock(&sc->lock);
32bfd35d 2664 if (sc->vif) {
fa1c114f
JS		 2665 ret = 0;
2666 goto end;
2667 }
2668
32bfd35d 2669 sc->vif = conf->vif;
fa1c114f
JS		 2670
2671 switch (conf->type) {
da966bca 2672 case NL80211_IFTYPE_AP:
05c914fe
JB		 2673 case NL80211_IFTYPE_STATION:
2674 case NL80211_IFTYPE_ADHOC:
b706e65b 2675 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2676 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2677 sc->opmode = conf->type;
2678 break;
2679 default:
2680 ret = -EOPNOTSUPP;
2681 goto end;
2682 }
67d2e2df
JS		 2683
2684 /* Set to a reasonable value. Note that this will
2685 * be set to mac80211's value at ath5k_config(). */
2686 sc->bintval = 1000;
0e149cf5 2687 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2688
fa1c114f
JS		 2689 ret = 0;
2690end:
2691 mutex_unlock(&sc->lock);
2692 return ret;
2693}
2694
2695static void
2696ath5k_remove_interface(struct ieee80211_hw *hw,
2697 struct ieee80211_if_init_conf *conf)
2698{
2699 struct ath5k_softc *sc = hw->priv;
0e149cf5 2700 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2701
2702 mutex_lock(&sc->lock);
32bfd35d 2703 if (sc->vif != conf->vif)
fa1c114f
JS		 2704 goto end;
2705
0e149cf5 2706 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2707 sc->vif = NULL;
fa1c114f
JS		 2708end:
2709 mutex_unlock(&sc->lock);
2710}
2711
d8ee398d
LR		 2712/*
2713 * TODO: Phy disable/diversity etc
2714 */
fa1c114f 2715static int
e8975581 2716ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2717{
2718 struct ath5k_softc *sc = hw->priv;
e8975581 2719 struct ieee80211_conf *conf = &hw->conf;
be009370
BC		 2720 int ret;
2721
2722 mutex_lock(&sc->lock);
fa1c114f 2723
e535c1ac 2724 sc->bintval = conf->beacon_int;
d8ee398d 2725 sc->power_level = conf->power_level;
fa1c114f 2726
be009370
BC		 2727 ret = ath5k_chan_set(sc, conf->channel);
2728
2729 mutex_unlock(&sc->lock);
2730 return ret;
fa1c114f
JS		 2731}
2732
2733static int
32bfd35d 2734ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2735 struct ieee80211_if_conf *conf)
2736{
2737 struct ath5k_softc *sc = hw->priv;
2738 struct ath5k_hw *ah = sc->ah;
fa8419d0 2739 int ret = 0;
fa1c114f 2740
fa1c114f 2741 mutex_lock(&sc->lock);
32bfd35d 2742 if (sc->vif != vif) {
fa1c114f
JS		 2743 ret = -EIO;
2744 goto unlock;
2745 }
da966bca 2746 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2747 /* Cache for later use during resets */
2748 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2749 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2750 * a clean way of letting us retrieve this yet. */
2751 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2752 mmiowb();
fa1c114f 2753 }
9d139c81 2754 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2755 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2756 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2757 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2758 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2759 if (!beacon) {
2760 ret = -ENOMEM;
2761 goto unlock;
2762 }
da966bca 2763 ath5k_beacon_update(sc, beacon);
9d139c81 2764 }
fa1c114f 2765
fa1c114f
JS		 2766unlock:
2767 mutex_unlock(&sc->lock);
2768 return ret;
2769}
2770
2771#define SUPPORTED_FIF_FLAGS \
2772 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2773 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2774 FIF_BCN_PRBRESP_PROMISC
2775/*
2776 * o always accept unicast, broadcast, and multicast traffic
2777 * o multicast traffic for all BSSIDs will be enabled if mac80211
2778 * says it should be
2779 * o maintain current state of phy ofdm or phy cck error reception.
2780 * If the hardware detects any of these type of errors then
2781 * ath5k_hw_get_rx_filter() will pass to us the respective
2782 * hardware filters to be able to receive these type of frames.
2783 * o probe request frames are accepted only when operating in
2784 * hostap, adhoc, or monitor modes
2785 * o enable promiscuous mode according to the interface state
2786 * o accept beacons:
2787 * - when operating in adhoc mode so the 802.11 layer creates
2788 * node table entries for peers,
2789 * - when operating in station mode for collecting rssi data when
2790 * the station is otherwise quiet, or
2791 * - when scanning
2792 */
2793static void ath5k_configure_filter(struct ieee80211_hw *hw,
2794 unsigned int changed_flags,
2795 unsigned int *new_flags,
2796 int mc_count, struct dev_mc_list *mclist)
2797{
2798 struct ath5k_softc *sc = hw->priv;
2799 struct ath5k_hw *ah = sc->ah;
2800 u32 mfilt[2], val, rfilt;
2801 u8 pos;
2802 int i;
2803
2804 mfilt[0] = 0;
2805 mfilt[1] = 0;
2806
2807 /* Only deal with supported flags */
2808 changed_flags &= SUPPORTED_FIF_FLAGS;
2809 *new_flags &= SUPPORTED_FIF_FLAGS;
2810
2811 /* If HW detects any phy or radar errors, leave those filters on.
2812 * Also, always enable Unicast, Broadcasts and Multicast
2813 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2814 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2815 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2816 AR5K_RX_FILTER_MCAST);
2817
2818 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2819 if (*new_flags & FIF_PROMISC_IN_BSS) {
2820 rfilt |= AR5K_RX_FILTER_PROM;
2821 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2822 } else {
fa1c114f 2823 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2824 }
fa1c114f
JS		 2825 }
2826
2827 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2828 if (*new_flags & FIF_ALLMULTI) {
2829 mfilt[0] = ~0;
2830 mfilt[1] = ~0;
2831 } else {
2832 for (i = 0; i < mc_count; i++) {
2833 if (!mclist)
2834 break;
2835 /* calculate XOR of eight 6-bit values */
533dd1b0 2836 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2837 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2838 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2839 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2840 pos &= 0x3f;
2841 mfilt[pos / 32] |= (1 << (pos % 32));
2842 /* XXX: we might be able to just do this instead,
2843 * but not sure, needs testing, if we do use this we'd
2844 * neet to inform below to not reset the mcast */
2845 /* ath5k_hw_set_mcast_filterindex(ah,
2846 * mclist->dmi_addr[5]); */
2847 mclist = mclist->next;
2848 }
2849 }
2850
2851 /* This is the best we can do */
2852 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2853 rfilt |= AR5K_RX_FILTER_PHYERR;
2854
2855 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2856 * and probes for any BSSID, this needs testing */
2857 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2858 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2859
2860 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2861 * set we should only pass on control frames for this
2862 * station. This needs testing. I believe right now this
2863 * enables *all* control frames, which is OK.. but
2864 * but we should see if we can improve on granularity */
2865 if (*new_flags & FIF_CONTROL)
2866 rfilt |= AR5K_RX_FILTER_CONTROL;
2867
2868 /* Additional settings per mode -- this is per ath5k */
2869
2870 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2871
05c914fe 2872 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2873 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2874 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2875 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2876 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2877 if (sc->opmode != NL80211_IFTYPE_AP &&
2878 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2879 test_bit(ATH_STAT_PROMISC, sc->status))
2880 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2881 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2882 sc->opmode == NL80211_IFTYPE_ADHOC ||
2883 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2884 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2885 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2886 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2887 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2888
2889 /* Set filters */
0bbac08f 2890 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2891
2892 /* Set multicast bits */
2893 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2894 /* Set the cached hw filter flags, this will alter actually
2895 * be set in HW */
2896 sc->filter_flags = rfilt;
2897}
2898
2899static int
2900ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2901 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2902 struct ieee80211_key_conf *key)
fa1c114f
JS		 2903{
2904 struct ath5k_softc *sc = hw->priv;
2905 int ret = 0;
2906
9ad9a26e
BC		 2907 if (modparam_nohwcrypt)
2908 return -EOPNOTSUPP;
2909
0bbac08f 2910 switch (key->alg) {
fa1c114f 2911 case ALG_WEP:
fa1c114f 2912 case ALG_TKIP:
3f64b435 2913 break;
fa1c114f
JS		 2914 case ALG_CCMP:
2915 return -EOPNOTSUPP;
2916 default:
2917 WARN_ON(1);
2918 return -EINVAL;
2919 }
2920
2921 mutex_lock(&sc->lock);
2922
2923 switch (cmd) {
2924 case SET_KEY:
dc822b5d
JB		 2925 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2926 sta ? sta->addr : NULL);
fa1c114f
JS		 2927 if (ret) {
2928 ATH5K_ERR(sc, "can't set the key\n");
2929 goto unlock;
2930 }
2931 __set_bit(key->keyidx, sc->keymap);
2932 key->hw_key_idx = key->keyidx;
3f64b435
BC		 2933 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2934 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 2935 break;
2936 case DISABLE_KEY:
2937 ath5k_hw_reset_key(sc->ah, key->keyidx);
2938 __clear_bit(key->keyidx, sc->keymap);
2939 break;
2940 default:
2941 ret = -EINVAL;
2942 goto unlock;
2943 }
2944
2945unlock:
274c7c36 2946 mmiowb();
fa1c114f
JS		 2947 mutex_unlock(&sc->lock);
2948 return ret;
2949}
2950
2951static int
2952ath5k_get_stats(struct ieee80211_hw *hw,
2953 struct ieee80211_low_level_stats *stats)
2954{
2955 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2956 struct ath5k_hw *ah = sc->ah;
2957
2958 /* Force update */
2959 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2960
2961 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2962
2963 return 0;
2964}
2965
2966static int
2967ath5k_get_tx_stats(struct ieee80211_hw *hw,
2968 struct ieee80211_tx_queue_stats *stats)
2969{
2970 struct ath5k_softc *sc = hw->priv;
2971
2972 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2973
2974 return 0;
2975}
2976
2977static u64
2978ath5k_get_tsf(struct ieee80211_hw *hw)
2979{
2980 struct ath5k_softc *sc = hw->priv;
2981
2982 return ath5k_hw_get_tsf64(sc->ah);
2983}
2984
3b5d665b
AF		 2985static void
2986ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2987{
2988 struct ath5k_softc *sc = hw->priv;
2989
2990 ath5k_hw_set_tsf64(sc->ah, tsf);
2991}
2992
fa1c114f
JS		 2993static void
2994ath5k_reset_tsf(struct ieee80211_hw *hw)
2995{
2996 struct ath5k_softc *sc = hw->priv;
2997
9804b98d
BR		 2998 /*
2999 * in IBSS mode we need to update the beacon timers too.
3000 * this will also reset the TSF if we call it with 0
3001 */
05c914fe 3002 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3003 ath5k_beacon_update_timers(sc, 0);
3004 else
3005 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3006}
3007
3008static int
da966bca 3009ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3010{
00482973 3011 unsigned long flags;
fa1c114f
JS		 3012 int ret;
3013
3014 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3015
00482973 3016 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3017 ath5k_txbuf_free(sc, sc->bbuf);
3018 sc->bbuf->skb = skb;
e039fa4a 3019 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3020 if (ret)
3021 sc->bbuf->skb = NULL;
00482973
JS		 3022 spin_unlock_irqrestore(&sc->block, flags);
3023 if (!ret) {
fa1c114f 3024 ath5k_beacon_config(sc);
274c7c36
JS		 3025 mmiowb();
3026 }
fa1c114f 3027
fa1c114f
JS		 3028 return ret;
3029}
02969b38
MX		 3030static void
3031set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3032{
3033 struct ath5k_softc *sc = hw->priv;
3034 struct ath5k_hw *ah = sc->ah;
3035 u32 rfilt;
3036 rfilt = ath5k_hw_get_rx_filter(ah);
3037 if (enable)
3038 rfilt |= AR5K_RX_FILTER_BEACON;
3039 else
3040 rfilt &= ~AR5K_RX_FILTER_BEACON;
3041 ath5k_hw_set_rx_filter(ah, rfilt);
3042 sc->filter_flags = rfilt;
3043}
fa1c114f 3044
02969b38
MX		 3045static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3046 struct ieee80211_vif *vif,
3047 struct ieee80211_bss_conf *bss_conf,
3048 u32 changes)
3049{
3050 struct ath5k_softc *sc = hw->priv;
3051 if (changes & BSS_CHANGED_ASSOC) {
3052 mutex_lock(&sc->lock);
3053 sc->assoc = bss_conf->assoc;
3054 if (sc->opmode == NL80211_IFTYPE_STATION)
3055 set_beacon_filter(hw, sc->assoc);
3056 mutex_unlock(&sc->lock);
3057 }
3058}
Clone of davem's net-next-2.6 tree