]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/ath5k/base.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ath5k: Use QUIET mechanism on tx dma stop
[net-next-2.6.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f
JS		 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63
64
65/******************\
66* Internal defines *
67\******************/
68
69/* Module info */
70MODULE_AUTHOR("Jiri Slaby");
71MODULE_AUTHOR("Nick Kossifidis");
72MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74MODULE_LICENSE("Dual BSD/GPL");
400ec45a 75MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
fa1c114f
JS		 76
77
78/* Known PCI ids */
79static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
80 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
82 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
84 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
85 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
86 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
fa1c114f
JS		 97 { 0 }
98};
99MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
100
101/* Known SREVs */
102static struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
121 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 124 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 125 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
126 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
127 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 128 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 129 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
130 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 131 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
132 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
133 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
136 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 137 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
138 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
139};
140
63266a65
BR		 141static struct ieee80211_rate ath5k_rates[] = {
142 { .bitrate = 10,
143 .hw_value = ATH5K_RATE_CODE_1M, },
144 { .bitrate = 20,
145 .hw_value = ATH5K_RATE_CODE_2M,
146 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
147 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
148 { .bitrate = 55,
149 .hw_value = ATH5K_RATE_CODE_5_5M,
150 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 110,
153 .hw_value = ATH5K_RATE_CODE_11M,
154 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 60,
157 .hw_value = ATH5K_RATE_CODE_6M,
158 .flags = 0 },
159 { .bitrate = 90,
160 .hw_value = ATH5K_RATE_CODE_9M,
161 .flags = 0 },
162 { .bitrate = 120,
163 .hw_value = ATH5K_RATE_CODE_12M,
164 .flags = 0 },
165 { .bitrate = 180,
166 .hw_value = ATH5K_RATE_CODE_18M,
167 .flags = 0 },
168 { .bitrate = 240,
169 .hw_value = ATH5K_RATE_CODE_24M,
170 .flags = 0 },
171 { .bitrate = 360,
172 .hw_value = ATH5K_RATE_CODE_36M,
173 .flags = 0 },
174 { .bitrate = 480,
175 .hw_value = ATH5K_RATE_CODE_48M,
176 .flags = 0 },
177 { .bitrate = 540,
178 .hw_value = ATH5K_RATE_CODE_54M,
179 .flags = 0 },
180 /* XR missing */
181};
182
fa1c114f
JS		 183/*
184 * Prototypes - PCI stack related functions
185 */
186static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
187 const struct pci_device_id *id);
188static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
189#ifdef CONFIG_PM
190static int ath5k_pci_suspend(struct pci_dev *pdev,
191 pm_message_t state);
192static int ath5k_pci_resume(struct pci_dev *pdev);
193#else
194#define ath5k_pci_suspend NULL
195#define ath5k_pci_resume NULL
196#endif /* CONFIG_PM */
197
04a9e451 198static struct pci_driver ath5k_pci_driver = {
fa1c114f
JS		 199 .name = "ath5k_pci",
200 .id_table = ath5k_pci_id_table,
201 .probe = ath5k_pci_probe,
202 .remove = __devexit_p(ath5k_pci_remove),
203 .suspend = ath5k_pci_suspend,
204 .resume = ath5k_pci_resume,
205};
206
207
208
209/*
210 * Prototypes - MAC 802.11 stack related functions
211 */
e039fa4a 212static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 213static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
214static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 215static int ath5k_start(struct ieee80211_hw *hw);
216static void ath5k_stop(struct ieee80211_hw *hw);
217static int ath5k_add_interface(struct ieee80211_hw *hw,
218 struct ieee80211_if_init_conf *conf);
219static void ath5k_remove_interface(struct ieee80211_hw *hw,
220 struct ieee80211_if_init_conf *conf);
221static int ath5k_config(struct ieee80211_hw *hw,
222 struct ieee80211_conf *conf);
32bfd35d
JB		 223static int ath5k_config_interface(struct ieee80211_hw *hw,
224 struct ieee80211_vif *vif,
fa1c114f
JS		 225 struct ieee80211_if_conf *conf);
226static void ath5k_configure_filter(struct ieee80211_hw *hw,
227 unsigned int changed_flags,
228 unsigned int *new_flags,
229 int mc_count, struct dev_mc_list *mclist);
230static int ath5k_set_key(struct ieee80211_hw *hw,
231 enum set_key_cmd cmd,
232 const u8 *local_addr, const u8 *addr,
233 struct ieee80211_key_conf *key);
234static int ath5k_get_stats(struct ieee80211_hw *hw,
235 struct ieee80211_low_level_stats *stats);
236static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
237 struct ieee80211_tx_queue_stats *stats);
238static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
239static void ath5k_reset_tsf(struct ieee80211_hw *hw);
240static int ath5k_beacon_update(struct ieee80211_hw *hw,
e039fa4a 241 struct sk_buff *skb);
fa1c114f
JS		 242
243static struct ieee80211_ops ath5k_hw_ops = {
244 .tx = ath5k_tx,
245 .start = ath5k_start,
246 .stop = ath5k_stop,
247 .add_interface = ath5k_add_interface,
248 .remove_interface = ath5k_remove_interface,
249 .config = ath5k_config,
250 .config_interface = ath5k_config_interface,
251 .configure_filter = ath5k_configure_filter,
252 .set_key = ath5k_set_key,
253 .get_stats = ath5k_get_stats,
254 .conf_tx = NULL,
255 .get_tx_stats = ath5k_get_tx_stats,
256 .get_tsf = ath5k_get_tsf,
257 .reset_tsf = ath5k_reset_tsf,
fa1c114f
JS		 258};
259
260/*
261 * Prototypes - Internal functions
262 */
263/* Attach detach */
264static int ath5k_attach(struct pci_dev *pdev,
265 struct ieee80211_hw *hw);
266static void ath5k_detach(struct pci_dev *pdev,
267 struct ieee80211_hw *hw);
268/* Channel/mode setup */
269static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 270static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
271 struct ieee80211_channel *channels,
272 unsigned int mode,
273 unsigned int max);
63266a65 274static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 275static int ath5k_chan_set(struct ath5k_softc *sc,
276 struct ieee80211_channel *chan);
277static void ath5k_setcurmode(struct ath5k_softc *sc,
278 unsigned int mode);
279static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 280
fa1c114f
JS		 281/* Descriptor setup */
282static int ath5k_desc_alloc(struct ath5k_softc *sc,
283 struct pci_dev *pdev);
284static void ath5k_desc_free(struct ath5k_softc *sc,
285 struct pci_dev *pdev);
286/* Buffers setup */
287static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
288 struct ath5k_buf *bf);
289static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 290 struct ath5k_buf *bf);
fa1c114f
JS		 291static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
292 struct ath5k_buf *bf)
293{
294 BUG_ON(!bf);
295 if (!bf->skb)
296 return;
297 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
298 PCI_DMA_TODEVICE);
00482973 299 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 300 bf->skb = NULL;
301}
302
303/* Queues setup */
304static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
305 int qtype, int subtype);
306static int ath5k_beaconq_setup(struct ath5k_hw *ah);
307static int ath5k_beaconq_config(struct ath5k_softc *sc);
308static void ath5k_txq_drainq(struct ath5k_softc *sc,
309 struct ath5k_txq *txq);
310static void ath5k_txq_cleanup(struct ath5k_softc *sc);
311static void ath5k_txq_release(struct ath5k_softc *sc);
312/* Rx handling */
313static int ath5k_rx_start(struct ath5k_softc *sc);
314static void ath5k_rx_stop(struct ath5k_softc *sc);
315static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
316 struct ath5k_desc *ds,
b47f407b
BR		 317 struct sk_buff *skb,
318 struct ath5k_rx_status *rs);
fa1c114f
JS		 319static void ath5k_tasklet_rx(unsigned long data);
320/* Tx handling */
321static void ath5k_tx_processq(struct ath5k_softc *sc,
322 struct ath5k_txq *txq);
323static void ath5k_tasklet_tx(unsigned long data);
324/* Beacon handling */
325static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 326 struct ath5k_buf *bf);
fa1c114f
JS		 327static void ath5k_beacon_send(struct ath5k_softc *sc);
328static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 329static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 330
331static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
332{
333 u64 tsf = ath5k_hw_get_tsf64(ah);
334
335 if ((tsf & 0x7fff) < rstamp)
336 tsf -= 0x8000;
337
338 return (tsf & ~0x7fff) | rstamp;
339}
340
341/* Interrupt handling */
342static int ath5k_init(struct ath5k_softc *sc);
343static int ath5k_stop_locked(struct ath5k_softc *sc);
344static int ath5k_stop_hw(struct ath5k_softc *sc);
345static irqreturn_t ath5k_intr(int irq, void *dev_id);
346static void ath5k_tasklet_reset(unsigned long data);
347
348static void ath5k_calibrate(unsigned long data);
349/* LED functions */
3a078876
BC		 350static int ath5k_init_leds(struct ath5k_softc *sc);
351static void ath5k_led_enable(struct ath5k_softc *sc);
352static void ath5k_led_off(struct ath5k_softc *sc);
353static void ath5k_unregister_leds(struct ath5k_softc *sc);
fa1c114f
JS		 354
355/*
356 * Module init/exit functions
357 */
358static int __init
359init_ath5k_pci(void)
360{
361 int ret;
362
363 ath5k_debug_init();
364
04a9e451 365 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 366 if (ret) {
367 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
368 return ret;
369 }
370
371 return 0;
372}
373
374static void __exit
375exit_ath5k_pci(void)
376{
04a9e451 377 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 378
379 ath5k_debug_finish();
380}
381
382module_init(init_ath5k_pci);
383module_exit(exit_ath5k_pci);
384
385
386/********************\
387* PCI Initialization *
388\********************/
389
390static const char *
391ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
392{
393 const char *name = "xxxxx";
394 unsigned int i;
395
396 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
397 if (srev_names[i].sr_type != type)
398 continue;
399 if ((val & 0xff) < srev_names[i + 1].sr_val) {
400 name = srev_names[i].sr_name;
401 break;
402 }
403 }
404
405 return name;
406}
407
408static int __devinit
409ath5k_pci_probe(struct pci_dev *pdev,
410 const struct pci_device_id *id)
411{
412 void __iomem *mem;
413 struct ath5k_softc *sc;
414 struct ieee80211_hw *hw;
415 int ret;
416 u8 csz;
417
418 ret = pci_enable_device(pdev);
419 if (ret) {
420 dev_err(&pdev->dev, "can't enable device\n");
421 goto err;
422 }
423
424 /* XXX 32-bit addressing only */
425 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
426 if (ret) {
427 dev_err(&pdev->dev, "32-bit DMA not available\n");
428 goto err_dis;
429 }
430
431 /*
432 * Cache line size is used to size and align various
433 * structures used to communicate with the hardware.
434 */
435 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
436 if (csz == 0) {
437 /*
438 * Linux 2.4.18 (at least) writes the cache line size
439 * register as a 16-bit wide register which is wrong.
440 * We must have this setup properly for rx buffer
441 * DMA to work so force a reasonable value here if it
442 * comes up zero.
443 */
444 csz = L1_CACHE_BYTES / sizeof(u32);
445 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
446 }
447 /*
448 * The default setting of latency timer yields poor results,
449 * set it to the value used by other systems. It may be worth
450 * tweaking this setting more.
451 */
452 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
453
454 /* Enable bus mastering */
455 pci_set_master(pdev);
456
457 /*
458 * Disable the RETRY_TIMEOUT register (0x41) to keep
459 * PCI Tx retries from interfering with C3 CPU state.
460 */
461 pci_write_config_byte(pdev, 0x41, 0);
462
463 ret = pci_request_region(pdev, 0, "ath5k");
464 if (ret) {
465 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
466 goto err_dis;
467 }
468
469 mem = pci_iomap(pdev, 0, 0);
470 if (!mem) {
471 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
472 ret = -EIO;
473 goto err_reg;
474 }
475
476 /*
477 * Allocate hw (mac80211 main struct)
478 * and hw->priv (driver private data)
479 */
480 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
481 if (hw == NULL) {
482 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
483 ret = -ENOMEM;
484 goto err_map;
485 }
486
487 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
488
489 /* Initialize driver private data */
490 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 491 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
492 IEEE80211_HW_SIGNAL_DBM |
493 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 494
495 hw->wiphy->interface_modes =
496 BIT(NL80211_IFTYPE_STATION) |
497 BIT(NL80211_IFTYPE_ADHOC) |
498 BIT(NL80211_IFTYPE_MESH_POINT);
499
fa1c114f
JS		 500 hw->extra_tx_headroom = 2;
501 hw->channel_change_time = 5000;
fa1c114f
JS		 502 sc = hw->priv;
503 sc->hw = hw;
504 sc->pdev = pdev;
505
506 ath5k_debug_init_device(sc);
507
508 /*
509 * Mark the device as detached to avoid processing
510 * interrupts until setup is complete.
511 */
512 __set_bit(ATH_STAT_INVALID, sc->status);
513
514 sc->iobase = mem; /* So we can unmap it on detach */
515 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 516 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 517 mutex_init(&sc->lock);
518 spin_lock_init(&sc->rxbuflock);
519 spin_lock_init(&sc->txbuflock);
00482973 520 spin_lock_init(&sc->block);
fa1c114f
JS		 521
522 /* Set private data */
523 pci_set_drvdata(pdev, hw);
524
fa1c114f
JS		 525 /* Setup interrupt handler */
526 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
527 if (ret) {
528 ATH5K_ERR(sc, "request_irq failed\n");
529 goto err_free;
530 }
531
532 /* Initialize device */
533 sc->ah = ath5k_hw_attach(sc, id->driver_data);
534 if (IS_ERR(sc->ah)) {
535 ret = PTR_ERR(sc->ah);
536 goto err_irq;
537 }
538
539 /* Finish private driver data initialization */
540 ret = ath5k_attach(pdev, hw);
541 if (ret)
542 goto err_ah;
543
544 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 545 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 546 sc->ah->ah_mac_srev,
547 sc->ah->ah_phy_revision);
548
400ec45a 549 if (!sc->ah->ah_single_chip) {
fa1c114f 550 /* Single chip radio (!RF5111) */
400ec45a
LR		 551 if (sc->ah->ah_radio_5ghz_revision &&
552 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 553 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 554 if (!test_bit(AR5K_MODE_11A,
555 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 556 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 557 ath5k_chip_name(AR5K_VERSION_RAD,
558 sc->ah->ah_radio_5ghz_revision),
559 sc->ah->ah_radio_5ghz_revision);
560 /* No 2GHz support (5110 and some
561 * 5Ghz only cards) -> report 5Ghz radio */
562 } else if (!test_bit(AR5K_MODE_11B,
563 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 564 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 565 ath5k_chip_name(AR5K_VERSION_RAD,
566 sc->ah->ah_radio_5ghz_revision),
567 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 568 /* Multiband radio */
569 } else {
570 ATH5K_INFO(sc, "RF%s multiband radio found"
571 " (0x%x)\n",
400ec45a
LR		 572 ath5k_chip_name(AR5K_VERSION_RAD,
573 sc->ah->ah_radio_5ghz_revision),
574 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 575 }
576 }
400ec45a
LR		 577 /* Multi chip radio (RF5111 - RF2111) ->
578 * report both 2GHz/5GHz radios */
579 else if (sc->ah->ah_radio_5ghz_revision &&
580 sc->ah->ah_radio_2ghz_revision){
fa1c114f 581 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 582 ath5k_chip_name(AR5K_VERSION_RAD,
583 sc->ah->ah_radio_5ghz_revision),
584 sc->ah->ah_radio_5ghz_revision);
fa1c114f 585 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 586 ath5k_chip_name(AR5K_VERSION_RAD,
587 sc->ah->ah_radio_2ghz_revision),
588 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 589 }
590 }
591
592
593 /* ready to process interrupts */
594 __clear_bit(ATH_STAT_INVALID, sc->status);
595
596 return 0;
597err_ah:
598 ath5k_hw_detach(sc->ah);
599err_irq:
600 free_irq(pdev->irq, sc);
601err_free:
fa1c114f
JS		 602 ieee80211_free_hw(hw);
603err_map:
604 pci_iounmap(pdev, mem);
605err_reg:
606 pci_release_region(pdev, 0);
607err_dis:
608 pci_disable_device(pdev);
609err:
610 return ret;
611}
612
613static void __devexit
614ath5k_pci_remove(struct pci_dev *pdev)
615{
616 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
617 struct ath5k_softc *sc = hw->priv;
618
619 ath5k_debug_finish_device(sc);
620 ath5k_detach(pdev, hw);
621 ath5k_hw_detach(sc->ah);
622 free_irq(pdev->irq, sc);
fa1c114f
JS		 623 pci_iounmap(pdev, sc->iobase);
624 pci_release_region(pdev, 0);
625 pci_disable_device(pdev);
626 ieee80211_free_hw(hw);
627}
628
629#ifdef CONFIG_PM
630static int
631ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
632{
633 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
634 struct ath5k_softc *sc = hw->priv;
635
3a078876 636 ath5k_led_off(sc);
fa1c114f
JS		 637
638 ath5k_stop_hw(sc);
3e4242b9
JS		 639
640 free_irq(pdev->irq, sc);
fa1c114f
JS		 641 pci_save_state(pdev);
642 pci_disable_device(pdev);
643 pci_set_power_state(pdev, PCI_D3hot);
644
645 return 0;
646}
647
648static int
649ath5k_pci_resume(struct pci_dev *pdev)
650{
651 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
652 struct ath5k_softc *sc = hw->priv;
247ae449
JL		 653 struct ath5k_hw *ah = sc->ah;
654 int i, err;
fa1c114f 655
3e4242b9 656 pci_restore_state(pdev);
fa1c114f
JS		 657
658 err = pci_enable_device(pdev);
659 if (err)
660 return err;
661
fa1c114f
JS		 662 /*
663 * Suspend/Resume resets the PCI configuration space, so we have to
664 * re-disable the RETRY_TIMEOUT register (0x41) to keep
665 * PCI Tx retries from interfering with C3 CPU state
666 */
667 pci_write_config_byte(pdev, 0x41, 0);
668
3e4242b9
JS		 669 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
670 if (err) {
671 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 672 goto err_no_irq;
3e4242b9
JS		 673 }
674
675 err = ath5k_init(sc);
676 if (err)
677 goto err_irq;
3a078876 678 ath5k_led_enable(sc);
fa1c114f 679
247ae449
JL		 680 /*
681 * Reset the key cache since some parts do not
682 * reset the contents on initial power up or resume.
683 *
684 * FIXME: This may need to be revisited when mac80211 becomes
685 * aware of suspend/resume.
686 */
687 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
688 ath5k_hw_reset_key(ah, i);
689
fa1c114f 690 return 0;
3e4242b9
JS		 691err_irq:
692 free_irq(pdev->irq, sc);
37465c8a 693err_no_irq:
3e4242b9
JS		 694 pci_disable_device(pdev);
695 return err;
fa1c114f
JS		 696}
697#endif /* CONFIG_PM */
698
699
fa1c114f
JS		 700/***********************\
701* Driver Initialization *
702\***********************/
703
704static int
705ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
706{
707 struct ath5k_softc *sc = hw->priv;
708 struct ath5k_hw *ah = sc->ah;
709 u8 mac[ETH_ALEN];
710 unsigned int i;
711 int ret;
712
713 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
714
715 /*
716 * Check if the MAC has multi-rate retry support.
717 * We do this by trying to setup a fake extended
718 * descriptor. MAC's that don't have support will
719 * return false w/o doing anything. MAC's that do
720 * support it will return true w/o doing anything.
721 */
c6e387a2 722 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 723 if (ret < 0)
724 goto err;
725 if (ret > 0)
fa1c114f
JS		 726 __set_bit(ATH_STAT_MRRETRY, sc->status);
727
728 /*
729 * Reset the key cache since some parts do not
730 * reset the contents on initial power up.
731 */
c65638a7 732 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
fa1c114f
JS		 733 ath5k_hw_reset_key(ah, i);
734
735 /*
736 * Collect the channel list. The 802.11 layer
737 * is resposible for filtering this list based
738 * on settings like the phy mode and regulatory
739 * domain restrictions.
740 */
63266a65 741 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 742 if (ret) {
743 ATH5K_ERR(sc, "can't get channels\n");
744 goto err;
745 }
746
747 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 748 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
749 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 750 else
d8ee398d 751 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 752
753 /*
754 * Allocate tx+rx descriptors and populate the lists.
755 */
756 ret = ath5k_desc_alloc(sc, pdev);
757 if (ret) {
758 ATH5K_ERR(sc, "can't allocate descriptors\n");
759 goto err;
760 }
761
762 /*
763 * Allocate hardware transmit queues: one queue for
764 * beacon frames and one data queue for each QoS
765 * priority. Note that hw functions handle reseting
766 * these queues at the needed time.
767 */
768 ret = ath5k_beaconq_setup(ah);
769 if (ret < 0) {
770 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
771 goto err_desc;
772 }
773 sc->bhalq = ret;
774
775 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
776 if (IS_ERR(sc->txq)) {
777 ATH5K_ERR(sc, "can't setup xmit queue\n");
778 ret = PTR_ERR(sc->txq);
779 goto err_bhal;
780 }
781
782 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
783 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
784 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
785 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f
JS		 786
787 ath5k_hw_get_lladdr(ah, mac);
788 SET_IEEE80211_PERM_ADDR(hw, mac);
789 /* All MAC address bits matter for ACKs */
790 memset(sc->bssidmask, 0xff, ETH_ALEN);
791 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
792
793 ret = ieee80211_register_hw(hw);
794 if (ret) {
795 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
796 goto err_queues;
797 }
798
3a078876
BC		 799 ath5k_init_leds(sc);
800
fa1c114f
JS		 801 return 0;
802err_queues:
803 ath5k_txq_release(sc);
804err_bhal:
805 ath5k_hw_release_tx_queue(ah, sc->bhalq);
806err_desc:
807 ath5k_desc_free(sc, pdev);
808err:
809 return ret;
810}
811
812static void
813ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
814{
815 struct ath5k_softc *sc = hw->priv;
816
817 /*
818 * NB: the order of these is important:
819 * o call the 802.11 layer before detaching ath5k_hw to
820 * insure callbacks into the driver to delete global
821 * key cache entries can be handled
822 * o reclaim the tx queue data structures after calling
823 * the 802.11 layer as we'll get called back to reclaim
824 * node state and potentially want to use them
825 * o to cleanup the tx queues the hal is called, so detach
826 * it last
827 * XXX: ??? detach ath5k_hw ???
828 * Other than that, it's straightforward...
829 */
830 ieee80211_unregister_hw(hw);
831 ath5k_desc_free(sc, pdev);
832 ath5k_txq_release(sc);
833 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 834 ath5k_unregister_leds(sc);
fa1c114f
JS		 835
836 /*
837 * NB: can't reclaim these until after ieee80211_ifdetach
838 * returns because we'll get called back to reclaim node
839 * state and potentially want to use them.
840 */
841}
842
843
844
845
846/********************\
847* Channel/mode setup *
848\********************/
849
850/*
851 * Convert IEEE channel number to MHz frequency.
852 */
853static inline short
854ath5k_ieee2mhz(short chan)
855{
856 if (chan <= 14 || chan >= 27)
857 return ieee80211chan2mhz(chan);
858 else
859 return 2212 + chan * 20;
860}
861
fa1c114f
JS		 862static unsigned int
863ath5k_copy_channels(struct ath5k_hw *ah,
864 struct ieee80211_channel *channels,
865 unsigned int mode,
866 unsigned int max)
867{
d8ee398d 868 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 869
870 if (!test_bit(mode, ah->ah_modes))
871 return 0;
872
fa1c114f 873 switch (mode) {
d8ee398d
LR		 874 case AR5K_MODE_11A:
875 case AR5K_MODE_11A_TURBO:
fa1c114f 876 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 877 size = 220 ;
fa1c114f
JS		 878 chfreq = CHANNEL_5GHZ;
879 break;
d8ee398d
LR		 880 case AR5K_MODE_11B:
881 case AR5K_MODE_11G:
882 case AR5K_MODE_11G_TURBO:
883 size = 26;
fa1c114f
JS		 884 chfreq = CHANNEL_2GHZ;
885 break;
886 default:
887 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
888 return 0;
889 }
890
891 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 892 ch = i + 1 ;
893 freq = ath5k_ieee2mhz(ch);
fa1c114f 894
d8ee398d
LR		 895 /* Check if channel is supported by the chipset */
896 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 897 continue;
898
d8ee398d
LR		 899 /* Write channel info and increment counter */
900 channels[count].center_freq = freq;
a3f4b914
LR		 901 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
902 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 903 switch (mode) {
904 case AR5K_MODE_11A:
905 case AR5K_MODE_11G:
906 channels[count].hw_value = chfreq | CHANNEL_OFDM;
907 break;
908 case AR5K_MODE_11A_TURBO:
909 case AR5K_MODE_11G_TURBO:
910 channels[count].hw_value = chfreq |
911 CHANNEL_OFDM | CHANNEL_TURBO;
912 break;
913 case AR5K_MODE_11B:
d8ee398d
LR		 914 channels[count].hw_value = CHANNEL_B;
915 }
fa1c114f 916
fa1c114f
JS		 917 count++;
918 max--;
919 }
920
921 return count;
922}
923
63266a65
BR		 924static void
925ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
926{
927 u8 i;
928
929 for (i = 0; i < AR5K_MAX_RATES; i++)
930 sc->rate_idx[b->band][i] = -1;
931
932 for (i = 0; i < b->n_bitrates; i++) {
933 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
934 if (b->bitrates[i].hw_value_short)
935 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
936 }
937}
938
d8ee398d 939static int
63266a65 940ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 941{
942 struct ath5k_softc *sc = hw->priv;
d8ee398d 943 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 944 struct ieee80211_supported_band *sband;
945 int max_c, count_c = 0;
946 int i;
fa1c114f 947
d8ee398d 948 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 949 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 950
951 /* 2GHz band */
63266a65
BR		 952 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
953 sband->band = IEEE80211_BAND_2GHZ;
954 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 955
63266a65
BR		 956 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
957 /* G mode */
958 memcpy(sband->bitrates, &ath5k_rates[0],
959 sizeof(struct ieee80211_rate) * 12);
960 sband->n_bitrates = 12;
fa1c114f 961
d8ee398d 962 sband->channels = sc->channels;
d8ee398d 963 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 964 AR5K_MODE_11G, max_c);
fa1c114f 965
63266a65 966 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 967 count_c = sband->n_channels;
63266a65
BR		 968 max_c -= count_c;
969 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
970 /* B mode */
971 memcpy(sband->bitrates, &ath5k_rates[0],
972 sizeof(struct ieee80211_rate) * 4);
973 sband->n_bitrates = 4;
974
975 /* 5211 only supports B rates and uses 4bit rate codes
976 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
977 * fix them up here:
978 */
979 if (ah->ah_version == AR5K_AR5211) {
980 for (i = 0; i < 4; i++) {
981 sband->bitrates[i].hw_value =
982 sband->bitrates[i].hw_value & 0xF;
983 sband->bitrates[i].hw_value_short =
984 sband->bitrates[i].hw_value_short & 0xF;
985 }
986 }
fa1c114f 987
63266a65
BR		 988 sband->channels = sc->channels;
989 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
990 AR5K_MODE_11B, max_c);
d8ee398d 991
63266a65
BR		 992 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
993 count_c = sband->n_channels;
d8ee398d 994 max_c -= count_c;
fa1c114f 995 }
63266a65 996 ath5k_setup_rate_idx(sc, sband);
fa1c114f 997
63266a65 998 /* 5GHz band, A mode */
400ec45a 999 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1000 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1001 sband->band = IEEE80211_BAND_5GHZ;
1002 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1003
63266a65
BR		 1004 memcpy(sband->bitrates, &ath5k_rates[4],
1005 sizeof(struct ieee80211_rate) * 8);
1006 sband->n_bitrates = 8;
fa1c114f 1007
63266a65 1008 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1009 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1010 AR5K_MODE_11A, max_c);
1011
d8ee398d
LR		 1012 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1013 }
63266a65 1014 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1015
b446197c 1016 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1017
1018 return 0;
fa1c114f
JS		 1019}
1020
1021/*
1022 * Set/change channels. If the channel is really being changed,
1023 * it's done by reseting the chip. To accomplish this we must
1024 * first cleanup any pending DMA, then restart stuff after a la
1025 * ath5k_init.
1026 */
1027static int
1028ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1029{
d8ee398d
LR		 1030 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1031 sc->curchan->center_freq, chan->center_freq);
1032
1033 if (chan->center_freq != sc->curchan->center_freq ||
1034 chan->hw_value != sc->curchan->hw_value) {
1035
1036 sc->curchan = chan;
1037 sc->curband = &sc->sbands[chan->band];
fa1c114f 1038
fa1c114f
JS		 1039 /*
1040 * To switch channels clear any pending DMA operations;
1041 * wait long enough for the RX fifo to drain, reset the
1042 * hardware at the new frequency, and then re-enable
1043 * the relevant bits of the h/w.
1044 */
d7dc1003 1045 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1046 }
1047
1048 return 0;
1049}
1050
1051static void
1052ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1053{
fa1c114f 1054 sc->curmode = mode;
d8ee398d 1055
400ec45a 1056 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1057 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1058 } else {
1059 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1060 }
fa1c114f
JS		 1061}
1062
1063static void
1064ath5k_mode_setup(struct ath5k_softc *sc)
1065{
1066 struct ath5k_hw *ah = sc->ah;
1067 u32 rfilt;
1068
1069 /* configure rx filter */
1070 rfilt = sc->filter_flags;
1071 ath5k_hw_set_rx_filter(ah, rfilt);
1072
1073 if (ath5k_hw_hasbssidmask(ah))
1074 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1075
1076 /* configure operational mode */
1077 ath5k_hw_set_opmode(ah);
1078
1079 ath5k_hw_set_mcast_filter(ah, 0, 0);
1080 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1081}
1082
d8ee398d 1083static inline int
63266a65
BR		 1084ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1085{
1086 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1087 return sc->rate_idx[sc->curband->band][hw_rix];
d8ee398d
LR		 1088}
1089
fa1c114f
JS		 1090/***************\
1091* Buffers setup *
1092\***************/
1093
1094static int
1095ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1096{
1097 struct ath5k_hw *ah = sc->ah;
1098 struct sk_buff *skb = bf->skb;
1099 struct ath5k_desc *ds;
1100
1101 if (likely(skb == NULL)) {
1102 unsigned int off;
1103
1104 /*
1105 * Allocate buffer with headroom_needed space for the
1106 * fake physical layer header at the start.
1107 */
1108 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1109 if (unlikely(skb == NULL)) {
1110 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1111 sc->rxbufsize + sc->cachelsz - 1);
1112 return -ENOMEM;
1113 }
1114 /*
1115 * Cache-line-align. This is important (for the
1116 * 5210 at least) as not doing so causes bogus data
1117 * in rx'd frames.
1118 */
1119 off = ((unsigned long)skb->data) % sc->cachelsz;
1120 if (off != 0)
1121 skb_reserve(skb, sc->cachelsz - off);
1122
1123 bf->skb = skb;
1124 bf->skbaddr = pci_map_single(sc->pdev,
1125 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
8d8bb39b 1126 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
fa1c114f
JS		 1127 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1128 dev_kfree_skb(skb);
1129 bf->skb = NULL;
1130 return -ENOMEM;
1131 }
1132 }
1133
1134 /*
1135 * Setup descriptors. For receive we always terminate
1136 * the descriptor list with a self-linked entry so we'll
1137 * not get overrun under high load (as can happen with a
1138 * 5212 when ANI processing enables PHY error frames).
1139 *
1140 * To insure the last descriptor is self-linked we create
1141 * each descriptor as self-linked and add it to the end. As
1142 * each additional descriptor is added the previous self-linked
1143 * entry is ``fixed'' naturally. This should be safe even
1144 * if DMA is happening. When processing RX interrupts we
1145 * never remove/process the last, self-linked, entry on the
1146 * descriptor list. This insures the hardware always has
1147 * someplace to write a new frame.
1148 */
1149 ds = bf->desc;
1150 ds->ds_link = bf->daddr; /* link to self */
1151 ds->ds_data = bf->skbaddr;
c6e387a2 1152 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1153 skb_tailroom(skb), /* buffer size */
1154 0);
1155
1156 if (sc->rxlink != NULL)
1157 *sc->rxlink = bf->daddr;
1158 sc->rxlink = &ds->ds_link;
1159 return 0;
1160}
1161
1162static int
e039fa4a 1163ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1164{
1165 struct ath5k_hw *ah = sc->ah;
1166 struct ath5k_txq *txq = sc->txq;
1167 struct ath5k_desc *ds = bf->desc;
1168 struct sk_buff *skb = bf->skb;
a888d52d 1169 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1170 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1171 int ret;
1172
1173 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1174
fa1c114f
JS		 1175 /* XXX endianness */
1176 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1177 PCI_DMA_TODEVICE);
1178
e039fa4a 1179 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1180 flags |= AR5K_TXDESC_NOACK;
1181
281c56dd 1182 pktlen = skb->len;
fa1c114f 1183
d0f09804 1184 if (info->control.hw_key) {
e039fa4a
JB		 1185 keyidx = info->control.hw_key->hw_key_idx;
1186 pktlen += info->control.icv_len;
fa1c114f 1187 }
fa1c114f
JS		 1188 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1189 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1190 (sc->power_level * 2),
e039fa4a
JB		 1191 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1192 info->control.retry_limit, keyidx, 0, flags, 0, 0);
fa1c114f
JS		 1193 if (ret)
1194 goto err_unmap;
1195
1196 ds->ds_link = 0;
1197 ds->ds_data = bf->skbaddr;
1198
1199 spin_lock_bh(&txq->lock);
1200 list_add_tail(&bf->list, &txq->q);
57ffc589 1201 sc->tx_stats[txq->qnum].len++;
fa1c114f 1202 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1203 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1204 else /* no, so only link it */
1205 *txq->link = bf->daddr;
1206
1207 txq->link = &ds->ds_link;
c6e387a2 1208 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1209 mmiowb();
fa1c114f
JS		 1210 spin_unlock_bh(&txq->lock);
1211
1212 return 0;
1213err_unmap:
1214 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1215 return ret;
1216}
1217
1218/*******************\
1219* Descriptors setup *
1220\*******************/
1221
1222static int
1223ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1224{
1225 struct ath5k_desc *ds;
1226 struct ath5k_buf *bf;
1227 dma_addr_t da;
1228 unsigned int i;
1229 int ret;
1230
1231 /* allocate descriptors */
1232 sc->desc_len = sizeof(struct ath5k_desc) *
1233 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1234 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1235 if (sc->desc == NULL) {
1236 ATH5K_ERR(sc, "can't allocate descriptors\n");
1237 ret = -ENOMEM;
1238 goto err;
1239 }
1240 ds = sc->desc;
1241 da = sc->desc_daddr;
1242 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1243 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1244
1245 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1246 sizeof(struct ath5k_buf), GFP_KERNEL);
1247 if (bf == NULL) {
1248 ATH5K_ERR(sc, "can't allocate bufptr\n");
1249 ret = -ENOMEM;
1250 goto err_free;
1251 }
1252 sc->bufptr = bf;
1253
1254 INIT_LIST_HEAD(&sc->rxbuf);
1255 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1256 bf->desc = ds;
1257 bf->daddr = da;
1258 list_add_tail(&bf->list, &sc->rxbuf);
1259 }
1260
1261 INIT_LIST_HEAD(&sc->txbuf);
1262 sc->txbuf_len = ATH_TXBUF;
1263 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1264 da += sizeof(*ds)) {
1265 bf->desc = ds;
1266 bf->daddr = da;
1267 list_add_tail(&bf->list, &sc->txbuf);
1268 }
1269
1270 /* beacon buffer */
1271 bf->desc = ds;
1272 bf->daddr = da;
1273 sc->bbuf = bf;
1274
1275 return 0;
1276err_free:
1277 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1278err:
1279 sc->desc = NULL;
1280 return ret;
1281}
1282
1283static void
1284ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1285{
1286 struct ath5k_buf *bf;
1287
1288 ath5k_txbuf_free(sc, sc->bbuf);
1289 list_for_each_entry(bf, &sc->txbuf, list)
1290 ath5k_txbuf_free(sc, bf);
1291 list_for_each_entry(bf, &sc->rxbuf, list)
1292 ath5k_txbuf_free(sc, bf);
1293
1294 /* Free memory associated with all descriptors */
1295 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1296
1297 kfree(sc->bufptr);
1298 sc->bufptr = NULL;
1299}
1300
1301
1302
1303
1304
1305/**************\
1306* Queues setup *
1307\**************/
1308
1309static struct ath5k_txq *
1310ath5k_txq_setup(struct ath5k_softc *sc,
1311 int qtype, int subtype)
1312{
1313 struct ath5k_hw *ah = sc->ah;
1314 struct ath5k_txq *txq;
1315 struct ath5k_txq_info qi = {
1316 .tqi_subtype = subtype,
1317 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1318 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1319 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1320 };
1321 int qnum;
1322
1323 /*
1324 * Enable interrupts only for EOL and DESC conditions.
1325 * We mark tx descriptors to receive a DESC interrupt
1326 * when a tx queue gets deep; otherwise waiting for the
1327 * EOL to reap descriptors. Note that this is done to
1328 * reduce interrupt load and this only defers reaping
1329 * descriptors, never transmitting frames. Aside from
1330 * reducing interrupts this also permits more concurrency.
1331 * The only potential downside is if the tx queue backs
1332 * up in which case the top half of the kernel may backup
1333 * due to a lack of tx descriptors.
1334 */
1335 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1336 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1337 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1338 if (qnum < 0) {
1339 /*
1340 * NB: don't print a message, this happens
1341 * normally on parts with too few tx queues
1342 */
1343 return ERR_PTR(qnum);
1344 }
1345 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1346 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1347 qnum, ARRAY_SIZE(sc->txqs));
1348 ath5k_hw_release_tx_queue(ah, qnum);
1349 return ERR_PTR(-EINVAL);
1350 }
1351 txq = &sc->txqs[qnum];
1352 if (!txq->setup) {
1353 txq->qnum = qnum;
1354 txq->link = NULL;
1355 INIT_LIST_HEAD(&txq->q);
1356 spin_lock_init(&txq->lock);
1357 txq->setup = true;
1358 }
1359 return &sc->txqs[qnum];
1360}
1361
1362static int
1363ath5k_beaconq_setup(struct ath5k_hw *ah)
1364{
1365 struct ath5k_txq_info qi = {
1366 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1367 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1368 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1369 /* NB: for dynamic turbo, don't enable any other interrupts */
1370 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1371 };
1372
1373 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1374}
1375
1376static int
1377ath5k_beaconq_config(struct ath5k_softc *sc)
1378{
1379 struct ath5k_hw *ah = sc->ah;
1380 struct ath5k_txq_info qi;
1381 int ret;
1382
1383 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1384 if (ret)
1385 return ret;
05c914fe
JB		 1386 if (sc->opmode == NL80211_IFTYPE_AP ||
1387 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1388 /*
1389 * Always burst out beacon and CAB traffic
1390 * (aifs = cwmin = cwmax = 0)
1391 */
1392 qi.tqi_aifs = 0;
1393 qi.tqi_cw_min = 0;
1394 qi.tqi_cw_max = 0;
05c914fe 1395 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1396 /*
1397 * Adhoc mode; backoff between 0 and (2 * cw_min).
1398 */
1399 qi.tqi_aifs = 0;
1400 qi.tqi_cw_min = 0;
1401 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1402 }
1403
6d91e1d8
BR		 1404 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1405 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1406 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1407
c6e387a2 1408 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1409 if (ret) {
1410 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1411 "hardware queue!\n", __func__);
1412 return ret;
1413 }
1414
1415 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1416}
1417
1418static void
1419ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1420{
1421 struct ath5k_buf *bf, *bf0;
1422
1423 /*
1424 * NB: this assumes output has been stopped and
1425 * we do not need to block ath5k_tx_tasklet
1426 */
1427 spin_lock_bh(&txq->lock);
1428 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1429 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1430
1431 ath5k_txbuf_free(sc, bf);
1432
1433 spin_lock_bh(&sc->txbuflock);
57ffc589 1434 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1435 list_move_tail(&bf->list, &sc->txbuf);
1436 sc->txbuf_len++;
1437 spin_unlock_bh(&sc->txbuflock);
1438 }
1439 txq->link = NULL;
1440 spin_unlock_bh(&txq->lock);
1441}
1442
1443/*
1444 * Drain the transmit queues and reclaim resources.
1445 */
1446static void
1447ath5k_txq_cleanup(struct ath5k_softc *sc)
1448{
1449 struct ath5k_hw *ah = sc->ah;
1450 unsigned int i;
1451
1452 /* XXX return value */
1453 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1454 /* don't touch the hardware if marked invalid */
1455 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1456 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1457 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1458 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1459 if (sc->txqs[i].setup) {
1460 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1461 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1462 "link %p\n",
1463 sc->txqs[i].qnum,
c6e387a2 1464 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1465 sc->txqs[i].qnum),
1466 sc->txqs[i].link);
1467 }
1468 }
36d6825b 1469 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1470
1471 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1472 if (sc->txqs[i].setup)
1473 ath5k_txq_drainq(sc, &sc->txqs[i]);
1474}
1475
1476static void
1477ath5k_txq_release(struct ath5k_softc *sc)
1478{
1479 struct ath5k_txq *txq = sc->txqs;
1480 unsigned int i;
1481
1482 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1483 if (txq->setup) {
1484 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1485 txq->setup = false;
1486 }
1487}
1488
1489
1490
1491
1492/*************\
1493* RX Handling *
1494\*************/
1495
1496/*
1497 * Enable the receive h/w following a reset.
1498 */
1499static int
1500ath5k_rx_start(struct ath5k_softc *sc)
1501{
1502 struct ath5k_hw *ah = sc->ah;
1503 struct ath5k_buf *bf;
1504 int ret;
1505
1506 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1507
1508 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1509 sc->cachelsz, sc->rxbufsize);
1510
1511 sc->rxlink = NULL;
1512
1513 spin_lock_bh(&sc->rxbuflock);
1514 list_for_each_entry(bf, &sc->rxbuf, list) {
1515 ret = ath5k_rxbuf_setup(sc, bf);
1516 if (ret != 0) {
1517 spin_unlock_bh(&sc->rxbuflock);
1518 goto err;
1519 }
1520 }
1521 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1522 spin_unlock_bh(&sc->rxbuflock);
1523
c6e387a2
NK		 1524 ath5k_hw_set_rxdp(ah, bf->daddr);
1525 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1526 ath5k_mode_setup(sc); /* set filters, etc. */
1527 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1528
1529 return 0;
1530err:
1531 return ret;
1532}
1533
1534/*
1535 * Disable the receive h/w in preparation for a reset.
1536 */
1537static void
1538ath5k_rx_stop(struct ath5k_softc *sc)
1539{
1540 struct ath5k_hw *ah = sc->ah;
1541
c6e387a2 1542 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1543 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1544 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1545
1546 ath5k_debug_printrxbuffs(sc, ah);
1547
1548 sc->rxlink = NULL; /* just in case */
1549}
1550
1551static unsigned int
1552ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1553 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1554{
1555 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1556 unsigned int keyix, hlen;
fa1c114f 1557
b47f407b
BR		 1558 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1559 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1560 return RX_FLAG_DECRYPTED;
1561
1562 /* Apparently when a default key is used to decrypt the packet
1563 the hw does not set the index used to decrypt. In such cases
1564 get the index from the packet. */
798ee985 1565 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1566 if (ieee80211_has_protected(hdr->frame_control) &&
1567 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1568 skb->len >= hlen + 4) {
fa1c114f
JS		 1569 keyix = skb->data[hlen + 3] >> 6;
1570
1571 if (test_bit(keyix, sc->keymap))
1572 return RX_FLAG_DECRYPTED;
1573 }
1574
1575 return 0;
1576}
1577
036cd1ec
BR		 1578
1579static void
6ba81c2c
BR		 1580ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1581 struct ieee80211_rx_status *rxs)
036cd1ec 1582{
6ba81c2c 1583 u64 tsf, bc_tstamp;
036cd1ec
BR		 1584 u32 hw_tu;
1585 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1586
24b56e70 1587 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1588 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1589 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1590 /*
6ba81c2c
BR		 1591 * Received an IBSS beacon with the same BSSID. Hardware *must*
1592 * have updated the local TSF. We have to work around various
1593 * hardware bugs, though...
036cd1ec 1594 */
6ba81c2c
BR		 1595 tsf = ath5k_hw_get_tsf64(sc->ah);
1596 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1597 hw_tu = TSF_TO_TU(tsf);
1598
1599 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1600 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1601 (unsigned long long)bc_tstamp,
1602 (unsigned long long)rxs->mactime,
1603 (unsigned long long)(rxs->mactime - bc_tstamp),
1604 (unsigned long long)tsf);
6ba81c2c
BR		 1605
1606 /*
1607 * Sometimes the HW will give us a wrong tstamp in the rx
1608 * status, causing the timestamp extension to go wrong.
1609 * (This seems to happen especially with beacon frames bigger
1610 * than 78 byte (incl. FCS))
1611 * But we know that the receive timestamp must be later than the
1612 * timestamp of the beacon since HW must have synced to that.
1613 *
1614 * NOTE: here we assume mactime to be after the frame was
1615 * received, not like mac80211 which defines it at the start.
1616 */
1617 if (bc_tstamp > rxs->mactime) {
036cd1ec 1618 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1619 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1620 (unsigned long long)rxs->mactime,
1621 (unsigned long long)tsf);
6ba81c2c 1622 rxs->mactime = tsf;
036cd1ec 1623 }
6ba81c2c
BR		 1624
1625 /*
1626 * Local TSF might have moved higher than our beacon timers,
1627 * in that case we have to update them to continue sending
1628 * beacons. This also takes care of synchronizing beacon sending
1629 * times with other stations.
1630 */
1631 if (hw_tu >= sc->nexttbtt)
1632 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1633 }
1634}
1635
1636
fa1c114f
JS		 1637static void
1638ath5k_tasklet_rx(unsigned long data)
1639{
1640 struct ieee80211_rx_status rxs = {};
b47f407b 1641 struct ath5k_rx_status rs = {};
fa1c114f
JS		 1642 struct sk_buff *skb;
1643 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1644 struct ath5k_buf *bf, *bf_last;
fa1c114f 1645 struct ath5k_desc *ds;
fa1c114f
JS		 1646 int ret;
1647 int hdrlen;
1648 int pad;
1649
1650 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1651 if (list_empty(&sc->rxbuf)) {
1652 ATH5K_WARN(sc, "empty rx buf pool\n");
1653 goto unlock;
1654 }
1655 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1656 do {
d6894b5b
BC		 1657 rxs.flag = 0;
1658
fa1c114f
JS		 1659 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1660 BUG_ON(bf->skb == NULL);
1661 skb = bf->skb;
1662 ds = bf->desc;
1663
3a0f2c87
JS		 1664 /*
1665 * last buffer must not be freed to ensure proper hardware
1666 * function. When the hardware finishes also a packet next to
1667 * it, we are sure, it doesn't use it anymore and we can go on.
1668 */
1669 if (bf_last == bf)
1670 bf->flags |= 1;
1671 if (bf->flags) {
1672 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1673 struct ath5k_buf, list);
1674 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1675 &rs);
1676 if (ret)
1677 break;
1678 bf->flags &= ~1;
1679 /* skip the overwritten one (even status is martian) */
1680 goto next;
1681 }
fa1c114f 1682
b47f407b 1683 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1684 if (unlikely(ret == -EINPROGRESS))
1685 break;
1686 else if (unlikely(ret)) {
1687 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1688 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1689 return;
1690 }
1691
b47f407b 1692 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1693 ATH5K_WARN(sc, "unsupported jumbo\n");
1694 goto next;
1695 }
1696
b47f407b
BR		 1697 if (unlikely(rs.rs_status)) {
1698 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1699 goto next;
b47f407b 1700 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1701 /*
1702 * Decrypt error. If the error occurred
1703 * because there was no hardware key, then
1704 * let the frame through so the upper layers
1705 * can process it. This is necessary for 5210
1706 * parts which have no way to setup a ``clear''
1707 * key cache entry.
1708 *
1709 * XXX do key cache faulting
1710 */
b47f407b
BR		 1711 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1712 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1713 goto accept;
1714 }
b47f407b 1715 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1716 rxs.flag |= RX_FLAG_MMIC_ERROR;
1717 goto accept;
1718 }
1719
1720 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1721 if ((rs.rs_status &
1722 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1723 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1724 goto next;
1725 }
1726accept:
fa1c114f
JS		 1727 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1728 PCI_DMA_FROMDEVICE);
1729 bf->skb = NULL;
1730
b47f407b 1731 skb_put(skb, rs.rs_datalen);
fa1c114f
JS		 1732
1733 /*
1734 * the hardware adds a padding to 4 byte boundaries between
1735 * the header and the payload data if the header length is
1736 * not multiples of 4 - remove it
1737 */
1738 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1739 if (hdrlen & 3) {
1740 pad = hdrlen % 4;
1741 memmove(skb->data + pad, skb->data, hdrlen);
1742 skb_pull(skb, pad);
1743 }
1744
c0e1899b
BR		 1745 /*
1746 * always extend the mac timestamp, since this information is
1747 * also needed for proper IBSS merging.
1748 *
1749 * XXX: it might be too late to do it here, since rs_tstamp is
1750 * 15bit only. that means TSF extension has to be done within
1751 * 32768usec (about 32ms). it might be necessary to move this to
1752 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1753 *
1754 * Unfortunately we don't know when the hardware takes the rx
1755 * timestamp (beginning of phy frame, data frame, end of rx?).
1756 * The only thing we know is that it is hardware specific...
1757 * On AR5213 it seems the rx timestamp is at the end of the
1758 * frame, but i'm not sure.
1759 *
1760 * NOTE: mac80211 defines mactime at the beginning of the first
1761 * data symbol. Since we don't have any time references it's
1762 * impossible to comply to that. This affects IBSS merge only
1763 * right now, so it's not too bad...
c0e1899b 1764 */
b47f407b 1765 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1766 rxs.flag |= RX_FLAG_TSFT;
1767
d8ee398d
LR		 1768 rxs.freq = sc->curchan->center_freq;
1769 rxs.band = sc->curband->band;
fa1c114f 1770
fa1c114f 1771 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a
BR		 1772 rxs.signal = rxs.noise + rs.rs_rssi;
1773 rxs.qual = rs.rs_rssi * 100 / 64;
fa1c114f 1774
b47f407b
BR		 1775 rxs.antenna = rs.rs_antenna;
1776 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1777 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1778
06303352
BR		 1779 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1780 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1781 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1782
fa1c114f
JS		 1783 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1784
036cd1ec 1785 /* check beacons in IBSS mode */
05c914fe 1786 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1787 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1788
fa1c114f 1789 __ieee80211_rx(sc->hw, skb, &rxs);
fa1c114f
JS		 1790next:
1791 list_move_tail(&bf->list, &sc->rxbuf);
1792 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1793unlock:
fa1c114f
JS		 1794 spin_unlock(&sc->rxbuflock);
1795}
1796
1797
1798
1799
1800/*************\
1801* TX Handling *
1802\*************/
1803
1804static void
1805ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1806{
b47f407b 1807 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1808 struct ath5k_buf *bf, *bf0;
1809 struct ath5k_desc *ds;
1810 struct sk_buff *skb;
e039fa4a 1811 struct ieee80211_tx_info *info;
fa1c114f
JS		 1812 int ret;
1813
1814 spin_lock(&txq->lock);
1815 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1816 ds = bf->desc;
1817
b47f407b 1818 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1819 if (unlikely(ret == -EINPROGRESS))
1820 break;
1821 else if (unlikely(ret)) {
1822 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1823 ret, txq->qnum);
1824 break;
1825 }
1826
1827 skb = bf->skb;
a888d52d 1828 info = IEEE80211_SKB_CB(skb);
fa1c114f 1829 bf->skb = NULL;
e039fa4a 1830
fa1c114f
JS		 1831 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1832 PCI_DMA_TODEVICE);
1833
e039fa4a 1834 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
b47f407b 1835 if (unlikely(ts.ts_status)) {
fa1c114f 1836 sc->ll_stats.dot11ACKFailureCount++;
b47f407b 1837 if (ts.ts_status & AR5K_TXERR_XRETRY)
e039fa4a 1838 info->status.excessive_retries = 1;
b47f407b 1839 else if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1840 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1841 } else {
e039fa4a
JB		 1842 info->flags |= IEEE80211_TX_STAT_ACK;
1843 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1844 }
1845
e039fa4a 1846 ieee80211_tx_status(sc->hw, skb);
57ffc589 1847 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1848
1849 spin_lock(&sc->txbuflock);
57ffc589 1850 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1851 list_move_tail(&bf->list, &sc->txbuf);
1852 sc->txbuf_len++;
1853 spin_unlock(&sc->txbuflock);
1854 }
1855 if (likely(list_empty(&txq->q)))
1856 txq->link = NULL;
1857 spin_unlock(&txq->lock);
1858 if (sc->txbuf_len > ATH_TXBUF / 5)
1859 ieee80211_wake_queues(sc->hw);
1860}
1861
1862static void
1863ath5k_tasklet_tx(unsigned long data)
1864{
1865 struct ath5k_softc *sc = (void *)data;
1866
1867 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1868}
1869
1870
fa1c114f
JS		 1871/*****************\
1872* Beacon handling *
1873\*****************/
1874
1875/*
1876 * Setup the beacon frame for transmit.
1877 */
1878static int
e039fa4a 1879ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1880{
1881 struct sk_buff *skb = bf->skb;
a888d52d 1882 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1883 struct ath5k_hw *ah = sc->ah;
1884 struct ath5k_desc *ds;
1885 int ret, antenna = 0;
1886 u32 flags;
1887
1888 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1889 PCI_DMA_TODEVICE);
1890 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1891 "skbaddr %llx\n", skb, skb->data, skb->len,
1892 (unsigned long long)bf->skbaddr);
8d8bb39b 1893 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1894 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1895 return -EIO;
1896 }
1897
1898 ds = bf->desc;
1899
1900 flags = AR5K_TXDESC_NOACK;
05c914fe 1901 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1902 ds->ds_link = bf->daddr; /* self-linked */
1903 flags |= AR5K_TXDESC_VEOL;
1904 /*
1905 * Let hardware handle antenna switching if txantenna is not set
1906 */
1907 } else {
1908 ds->ds_link = 0;
1909 /*
1910 * Switch antenna every 4 beacons if txantenna is not set
1911 * XXX assumes two antennas
1912 */
1913 if (antenna == 0)
1914 antenna = sc->bsent & 4 ? 2 : 1;
1915 }
1916
1917 ds->ds_data = bf->skbaddr;
281c56dd 1918 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 1919 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 1920 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1921 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1922 1, AR5K_TXKEYIX_INVALID,
400ec45a 1923 antenna, flags, 0, 0);
fa1c114f
JS		 1924 if (ret)
1925 goto err_unmap;
1926
1927 return 0;
1928err_unmap:
1929 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1930 return ret;
1931}
1932
1933/*
1934 * Transmit a beacon frame at SWBA. Dynamic updates to the
1935 * frame contents are done as needed and the slot time is
1936 * also adjusted based on current state.
1937 *
1938 * this is usually called from interrupt context (ath5k_intr())
1939 * but also from ath5k_beacon_config() in IBSS mode which in turn
1940 * can be called from a tasklet and user context
1941 */
1942static void
1943ath5k_beacon_send(struct ath5k_softc *sc)
1944{
1945 struct ath5k_buf *bf = sc->bbuf;
1946 struct ath5k_hw *ah = sc->ah;
1947
be9b7259 1948 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1949
05c914fe
JB		 1950 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1951 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 1952 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1953 return;
1954 }
1955 /*
1956 * Check if the previous beacon has gone out. If
1957 * not don't don't try to post another, skip this
1958 * period and wait for the next. Missed beacons
1959 * indicate a problem and should not occur. If we
1960 * miss too many consecutive beacons reset the device.
1961 */
1962 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1963 sc->bmisscount++;
be9b7259 1964 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1965 "missed %u consecutive beacons\n", sc->bmisscount);
1966 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 1967 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1968 "stuck beacon time (%u missed)\n",
1969 sc->bmisscount);
1970 tasklet_schedule(&sc->restq);
1971 }
1972 return;
1973 }
1974 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1975 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1976 "resume beacon xmit after %u misses\n",
1977 sc->bmisscount);
1978 sc->bmisscount = 0;
1979 }
1980
1981 /*
1982 * Stop any current dma and put the new frame on the queue.
1983 * This should never fail since we check above that no frames
1984 * are still pending on the queue.
1985 */
1986 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
1987 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
1988 /* NB: hw still stops DMA, so proceed */
1989 }
fa1c114f 1990
c6e387a2
NK		 1991 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1992 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1993 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1994 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1995
1996 sc->bsent++;
1997}
1998
1999
9804b98d
BR		 2000/**
2001 * ath5k_beacon_update_timers - update beacon timers
2002 *
2003 * @sc: struct ath5k_softc pointer we are operating on
2004 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2005 * beacon timer update based on the current HW TSF.
2006 *
2007 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2008 * of a received beacon or the current local hardware TSF and write it to the
2009 * beacon timer registers.
2010 *
2011 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2012 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2013 * when we otherwise know we have to update the timers, but we keep it in this
2014 * function to have it all together in one place.
2015 */
fa1c114f 2016static void
9804b98d 2017ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2018{
2019 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2020 u32 nexttbtt, intval, hw_tu, bc_tu;
2021 u64 hw_tsf;
fa1c114f
JS		 2022
2023 intval = sc->bintval & AR5K_BEACON_PERIOD;
2024 if (WARN_ON(!intval))
2025 return;
2026
9804b98d
BR		 2027 /* beacon TSF converted to TU */
2028 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2029
9804b98d
BR		 2030 /* current TSF converted to TU */
2031 hw_tsf = ath5k_hw_get_tsf64(ah);
2032 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2033
9804b98d
BR		 2034#define FUDGE 3
2035 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2036 if (bc_tsf == -1) {
2037 /*
2038 * no beacons received, called internally.
2039 * just need to refresh timers based on HW TSF.
2040 */
2041 nexttbtt = roundup(hw_tu + FUDGE, intval);
2042 } else if (bc_tsf == 0) {
2043 /*
2044 * no beacon received, probably called by ath5k_reset_tsf().
2045 * reset TSF to start with 0.
2046 */
2047 nexttbtt = intval;
2048 intval |= AR5K_BEACON_RESET_TSF;
2049 } else if (bc_tsf > hw_tsf) {
2050 /*
2051 * beacon received, SW merge happend but HW TSF not yet updated.
2052 * not possible to reconfigure timers yet, but next time we
2053 * receive a beacon with the same BSSID, the hardware will
2054 * automatically update the TSF and then we need to reconfigure
2055 * the timers.
2056 */
2057 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2058 "need to wait for HW TSF sync\n");
2059 return;
2060 } else {
2061 /*
2062 * most important case for beacon synchronization between STA.
2063 *
2064 * beacon received and HW TSF has been already updated by HW.
2065 * update next TBTT based on the TSF of the beacon, but make
2066 * sure it is ahead of our local TSF timer.
2067 */
2068 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2069 }
2070#undef FUDGE
fa1c114f 2071
036cd1ec
BR		 2072 sc->nexttbtt = nexttbtt;
2073
fa1c114f 2074 intval |= AR5K_BEACON_ENA;
fa1c114f 2075 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2076
2077 /*
2078 * debugging output last in order to preserve the time critical aspect
2079 * of this function
2080 */
2081 if (bc_tsf == -1)
2082 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2083 "reconfigured timers based on HW TSF\n");
2084 else if (bc_tsf == 0)
2085 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2086 "reset HW TSF and timers\n");
2087 else
2088 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2089 "updated timers based on beacon TSF\n");
2090
2091 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2092 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2093 (unsigned long long) bc_tsf,
2094 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2095 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2096 intval & AR5K_BEACON_PERIOD,
2097 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2098 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2099}
2100
2101
036cd1ec
BR		 2102/**
2103 * ath5k_beacon_config - Configure the beacon queues and interrupts
2104 *
2105 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f
JS		 2106 *
2107 * When operating in station mode we want to receive a BMISS interrupt when we
2108 * stop seeing beacons from the AP we've associated with so we can look for
2109 * another AP to associate with.
2110 *
036cd1ec 2111 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2112 * interrupts to detect TSF updates only.
036cd1ec
BR		 2113 *
2114 * AP mode is missing.
fa1c114f
JS		 2115 */
2116static void
2117ath5k_beacon_config(struct ath5k_softc *sc)
2118{
2119 struct ath5k_hw *ah = sc->ah;
2120
c6e387a2 2121 ath5k_hw_set_imr(ah, 0);
fa1c114f 2122 sc->bmisscount = 0;
dc1968e7 2123 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2124
05c914fe 2125 if (sc->opmode == NL80211_IFTYPE_STATION) {
fa1c114f 2126 sc->imask |= AR5K_INT_BMISS;
05c914fe 2127 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f 2128 /*
036cd1ec
BR		 2129 * In IBSS mode we use a self-linked tx descriptor and let the
2130 * hardware send the beacons automatically. We have to load it
fa1c114f 2131 * only once here.
036cd1ec 2132 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2133 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2134 */
2135 ath5k_beaconq_config(sc);
fa1c114f 2136
036cd1ec
BR		 2137 sc->imask |= AR5K_INT_SWBA;
2138
00482973
JS		 2139 if (ath5k_hw_hasveol(ah)) {
2140 spin_lock(&sc->block);
fa1c114f 2141 ath5k_beacon_send(sc);
00482973
JS		 2142 spin_unlock(&sc->block);
2143 }
fa1c114f
JS		 2144 }
2145 /* TODO else AP */
2146
c6e387a2 2147 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2148}
2149
2150
2151/********************\
2152* Interrupt handling *
2153\********************/
2154
2155static int
2156ath5k_init(struct ath5k_softc *sc)
2157{
2158 int ret;
2159
2160 mutex_lock(&sc->lock);
2161
2162 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2163
2164 /*
2165 * Stop anything previously setup. This is safe
2166 * no matter this is the first time through or not.
2167 */
2168 ath5k_stop_locked(sc);
2169
2170 /*
2171 * The basic interface to setting the hardware in a good
2172 * state is ``reset''. On return the hardware is known to
2173 * be powered up and with interrupts disabled. This must
2174 * be followed by initialization of the appropriate bits
2175 * and then setup of the interrupt mask.
2176 */
d8ee398d
LR		 2177 sc->curchan = sc->hw->conf.channel;
2178 sc->curband = &sc->sbands[sc->curchan->band];
fa1c114f 2179 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
194828a2
NK		 2180 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2181 AR5K_INT_MIB;
d7dc1003
JS		 2182 ret = ath5k_reset(sc, false, false);
2183 if (ret)
2184 goto done;
fa1c114f 2185
fa1c114f
JS		 2186 /* Set ack to be sent at low bit-rates */
2187 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2188
2189 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2190 msecs_to_jiffies(ath5k_calinterval * 1000)));
2191
2192 ret = 0;
2193done:
274c7c36 2194 mmiowb();
fa1c114f
JS		 2195 mutex_unlock(&sc->lock);
2196 return ret;
2197}
2198
2199static int
2200ath5k_stop_locked(struct ath5k_softc *sc)
2201{
2202 struct ath5k_hw *ah = sc->ah;
2203
2204 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2205 test_bit(ATH_STAT_INVALID, sc->status));
2206
2207 /*
2208 * Shutdown the hardware and driver:
2209 * stop output from above
2210 * disable interrupts
2211 * turn off timers
2212 * turn off the radio
2213 * clear transmit machinery
2214 * clear receive machinery
2215 * drain and release tx queues
2216 * reclaim beacon resources
2217 * power down hardware
2218 *
2219 * Note that some of this work is not possible if the
2220 * hardware is gone (invalid).
2221 */
2222 ieee80211_stop_queues(sc->hw);
2223
2224 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2225 ath5k_led_off(sc);
c6e387a2 2226 ath5k_hw_set_imr(ah, 0);
274c7c36 2227 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2228 }
2229 ath5k_txq_cleanup(sc);
2230 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2231 ath5k_rx_stop(sc);
2232 ath5k_hw_phy_disable(ah);
2233 } else
2234 sc->rxlink = NULL;
2235
2236 return 0;
2237}
2238
2239/*
2240 * Stop the device, grabbing the top-level lock to protect
2241 * against concurrent entry through ath5k_init (which can happen
2242 * if another thread does a system call and the thread doing the
2243 * stop is preempted).
2244 */
2245static int
2246ath5k_stop_hw(struct ath5k_softc *sc)
2247{
2248 int ret;
2249
2250 mutex_lock(&sc->lock);
2251 ret = ath5k_stop_locked(sc);
2252 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2253 /*
2254 * Set the chip in full sleep mode. Note that we are
2255 * careful to do this only when bringing the interface
2256 * completely to a stop. When the chip is in this state
2257 * it must be carefully woken up or references to
2258 * registers in the PCI clock domain may freeze the bus
2259 * (and system). This varies by chip and is mostly an
2260 * issue with newer parts that go to sleep more quickly.
2261 */
2262 if (sc->ah->ah_mac_srev >= 0x78) {
2263 /*
2264 * XXX
2265 * don't put newer MAC revisions > 7.8 to sleep because
2266 * of the above mentioned problems
2267 */
2268 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2269 "not putting device to sleep\n");
2270 } else {
2271 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2272 "putting device to full sleep\n");
2273 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2274 }
2275 }
2276 ath5k_txbuf_free(sc, sc->bbuf);
274c7c36 2277 mmiowb();
fa1c114f
JS		 2278 mutex_unlock(&sc->lock);
2279
2280 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2281 tasklet_kill(&sc->rxtq);
2282 tasklet_kill(&sc->txtq);
2283 tasklet_kill(&sc->restq);
fa1c114f
JS		 2284
2285 return ret;
2286}
2287
2288static irqreturn_t
2289ath5k_intr(int irq, void *dev_id)
2290{
2291 struct ath5k_softc *sc = dev_id;
2292 struct ath5k_hw *ah = sc->ah;
2293 enum ath5k_int status;
2294 unsigned int counter = 1000;
2295
2296 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2297 !ath5k_hw_is_intr_pending(ah)))
2298 return IRQ_NONE;
2299
2300 do {
2301 /*
2302 * Figure out the reason(s) for the interrupt. Note
2303 * that get_isr returns a pseudo-ISR that may include
2304 * bits we haven't explicitly enabled so we mask the
2305 * value to insure we only process bits we requested.
2306 */
2307 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2308 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2309 status, sc->imask);
2310 status &= sc->imask; /* discard unasked for bits */
2311 if (unlikely(status & AR5K_INT_FATAL)) {
2312 /*
2313 * Fatal errors are unrecoverable.
2314 * Typically these are caused by DMA errors.
2315 */
2316 tasklet_schedule(&sc->restq);
2317 } else if (unlikely(status & AR5K_INT_RXORN)) {
2318 tasklet_schedule(&sc->restq);
2319 } else {
2320 if (status & AR5K_INT_SWBA) {
2321 /*
2322 * Software beacon alert--time to send a beacon.
2323 * Handle beacon transmission directly; deferring
2324 * this is too slow to meet timing constraints
2325 * under load.
036cd1ec
BR		 2326 *
2327 * In IBSS mode we use this interrupt just to
2328 * keep track of the next TBTT (target beacon
6ba81c2c
BR		 2329 * transmission time) in order to detect wether
2330 * automatic TSF updates happened.
fa1c114f 2331 */
05c914fe 2332 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
036cd1ec
BR		 2333 /* XXX: only if VEOL suppported */
2334 u64 tsf = ath5k_hw_get_tsf64(ah);
2335 sc->nexttbtt += sc->bintval;
2336 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2337 "SWBA nexttbtt: %x hw_tu: %x "
2338 "TSF: %llx\n",
2339 sc->nexttbtt,
2340 TSF_TO_TU(tsf),
2341 (unsigned long long) tsf);
036cd1ec 2342 } else {
00482973 2343 spin_lock(&sc->block);
036cd1ec 2344 ath5k_beacon_send(sc);
00482973 2345 spin_unlock(&sc->block);
036cd1ec 2346 }
fa1c114f
JS		 2347 }
2348 if (status & AR5K_INT_RXEOL) {
2349 /*
2350 * NB: the hardware should re-read the link when
2351 * RXE bit is written, but it doesn't work at
2352 * least on older hardware revs.
2353 */
2354 sc->rxlink = NULL;
2355 }
2356 if (status & AR5K_INT_TXURN) {
2357 /* bump tx trigger level */
2358 ath5k_hw_update_tx_triglevel(ah, true);
2359 }
2360 if (status & AR5K_INT_RX)
2361 tasklet_schedule(&sc->rxtq);
2362 if (status & AR5K_INT_TX)
2363 tasklet_schedule(&sc->txtq);
2364 if (status & AR5K_INT_BMISS) {
2365 }
2366 if (status & AR5K_INT_MIB) {
194828a2
NK		 2367 /*
2368 * These stats are also used for ANI i think
2369 * so how about updating them more often ?
2370 */
2371 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2372 }
2373 }
2374 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2375
2376 if (unlikely(!counter))
2377 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2378
2379 return IRQ_HANDLED;
2380}
2381
2382static void
2383ath5k_tasklet_reset(unsigned long data)
2384{
2385 struct ath5k_softc *sc = (void *)data;
2386
d7dc1003 2387 ath5k_reset_wake(sc);
fa1c114f
JS		 2388}
2389
2390/*
2391 * Periodically recalibrate the PHY to account
2392 * for temperature/environment changes.
2393 */
2394static void
2395ath5k_calibrate(unsigned long data)
2396{
2397 struct ath5k_softc *sc = (void *)data;
2398 struct ath5k_hw *ah = sc->ah;
2399
2400 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2401 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2402 sc->curchan->hw_value);
fa1c114f
JS		 2403
2404 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2405 /*
2406 * Rfgain is out of bounds, reset the chip
2407 * to load new gain values.
2408 */
2409 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2410 ath5k_reset_wake(sc);
fa1c114f
JS		 2411 }
2412 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2413 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2414 ieee80211_frequency_to_channel(
2415 sc->curchan->center_freq));
fa1c114f
JS		 2416
2417 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2418 msecs_to_jiffies(ath5k_calinterval * 1000)));
2419}
2420
2421
2422
2423/***************\
2424* LED functions *
2425\***************/
2426
2427static void
3a078876 2428ath5k_led_enable(struct ath5k_softc *sc)
fa1c114f 2429{
3a078876
BC		 2430 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2431 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2432 ath5k_led_off(sc);
fa1c114f
JS		 2433 }
2434}
2435
fa1c114f 2436static void
3a078876 2437ath5k_led_on(struct ath5k_softc *sc)
fa1c114f 2438{
3a078876
BC		 2439 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2440 return;
fa1c114f 2441 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
fa1c114f
JS		 2442}
2443
2444static void
3a078876 2445ath5k_led_off(struct ath5k_softc *sc)
fa1c114f 2446{
3a078876 2447 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
fa1c114f 2448 return;
3a078876
BC		 2449 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2450}
2451
2452static void
2453ath5k_led_brightness_set(struct led_classdev *led_dev,
2454 enum led_brightness brightness)
2455{
2456 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2457 led_dev);
2458
2459 if (brightness == LED_OFF)
2460 ath5k_led_off(led->sc);
2461 else
2462 ath5k_led_on(led->sc);
2463}
2464
2465static int
2466ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2467 const char *name, char *trigger)
2468{
2469 int err;
2470
2471 led->sc = sc;
2472 strncpy(led->name, name, sizeof(led->name));
2473 led->led_dev.name = led->name;
2474 led->led_dev.default_trigger = trigger;
2475 led->led_dev.brightness_set = ath5k_led_brightness_set;
2476
2477 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2478 if (err)
2479 {
2480 ATH5K_WARN(sc, "could not register LED %s\n", name);
2481 led->sc = NULL;
fa1c114f 2482 }
3a078876 2483 return err;
fa1c114f
JS		 2484}
2485
3a078876
BC		 2486static void
2487ath5k_unregister_led(struct ath5k_led *led)
2488{
2489 if (!led->sc)
2490 return;
2491 led_classdev_unregister(&led->led_dev);
2492 ath5k_led_off(led->sc);
2493 led->sc = NULL;
2494}
2495
2496static void
2497ath5k_unregister_leds(struct ath5k_softc *sc)
2498{
2499 ath5k_unregister_led(&sc->rx_led);
2500 ath5k_unregister_led(&sc->tx_led);
2501}
2502
2503
2504static int
2505ath5k_init_leds(struct ath5k_softc *sc)
2506{
2507 int ret = 0;
2508 struct ieee80211_hw *hw = sc->hw;
2509 struct pci_dev *pdev = sc->pdev;
2510 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2511
3a078876
BC		 2512 /*
2513 * Auto-enable soft led processing for IBM cards and for
2514 * 5211 minipci cards.
2515 */
2516 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2517 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2518 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2519 sc->led_pin = 0;
734b5aa9 2520 sc->led_on = 0; /* active low */
3a078876
BC		 2521 }
2522 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2523 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2524 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2525 sc->led_pin = 1;
734b5aa9 2526 sc->led_on = 1; /* active high */
3a078876
BC		 2527 }
2528 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2529 goto out;
2530
2531 ath5k_led_enable(sc);
2532
2533 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2534 ret = ath5k_register_led(sc, &sc->rx_led, name,
2535 ieee80211_get_rx_led_name(hw));
2536 if (ret)
2537 goto out;
2538
2539 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2540 ret = ath5k_register_led(sc, &sc->tx_led, name,
2541 ieee80211_get_tx_led_name(hw));
2542out:
2543 return ret;
2544}
fa1c114f
JS		 2545
2546
2547/********************\
2548* Mac80211 functions *
2549\********************/
2550
2551static int
e039fa4a 2552ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2553{
2554 struct ath5k_softc *sc = hw->priv;
2555 struct ath5k_buf *bf;
2556 unsigned long flags;
2557 int hdrlen;
2558 int pad;
2559
2560 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2561
05c914fe 2562 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2563 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2564
2565 /*
2566 * the hardware expects the header padded to 4 byte boundaries
2567 * if this is not the case we add the padding after the header
2568 */
2569 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2570 if (hdrlen & 3) {
2571 pad = hdrlen % 4;
2572 if (skb_headroom(skb) < pad) {
2573 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2574 " headroom to pad %d\n", hdrlen, pad);
2575 return -1;
2576 }
2577 skb_push(skb, pad);
2578 memmove(skb->data, skb->data+pad, hdrlen);
2579 }
2580
fa1c114f
JS		 2581 spin_lock_irqsave(&sc->txbuflock, flags);
2582 if (list_empty(&sc->txbuf)) {
2583 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2584 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2585 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
fa1c114f
JS		 2586 return -1;
2587 }
2588 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2589 list_del(&bf->list);
2590 sc->txbuf_len--;
2591 if (list_empty(&sc->txbuf))
2592 ieee80211_stop_queues(hw);
2593 spin_unlock_irqrestore(&sc->txbuflock, flags);
2594
2595 bf->skb = skb;
2596
e039fa4a 2597 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2598 bf->skb = NULL;
2599 spin_lock_irqsave(&sc->txbuflock, flags);
2600 list_add_tail(&bf->list, &sc->txbuf);
2601 sc->txbuf_len++;
2602 spin_unlock_irqrestore(&sc->txbuflock, flags);
2603 dev_kfree_skb_any(skb);
2604 return 0;
2605 }
2606
2607 return 0;
2608}
2609
2610static int
d7dc1003 2611ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2612{
fa1c114f
JS		 2613 struct ath5k_hw *ah = sc->ah;
2614 int ret;
2615
2616 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2617
d7dc1003 2618 if (stop) {
c6e387a2 2619 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2620 ath5k_txq_cleanup(sc);
2621 ath5k_rx_stop(sc);
2622 }
fa1c114f 2623 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2624 if (ret) {
fa1c114f
JS		 2625 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2626 goto err;
2627 }
d7dc1003
JS		 2628
2629 /*
2630 * This is needed only to setup initial state
2631 * but it's best done after a reset.
2632 */
fa1c114f
JS		 2633 ath5k_hw_set_txpower_limit(sc->ah, 0);
2634
2635 ret = ath5k_rx_start(sc);
d7dc1003 2636 if (ret) {
fa1c114f
JS		 2637 ATH5K_ERR(sc, "can't start recv logic\n");
2638 goto err;
2639 }
d7dc1003 2640
fa1c114f 2641 /*
d7dc1003
JS		 2642 * Change channels and update the h/w rate map if we're switching;
2643 * e.g. 11a to 11b/g.
2644 *
2645 * We may be doing a reset in response to an ioctl that changes the
2646 * channel so update any state that might change as a result.
fa1c114f
JS		 2647 *
2648 * XXX needed?
2649 */
2650/* ath5k_chan_change(sc, c); */
fa1c114f 2651
d7dc1003
JS		 2652 ath5k_beacon_config(sc);
2653 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2654
2655 return 0;
2656err:
2657 return ret;
2658}
2659
d7dc1003
JS		 2660static int
2661ath5k_reset_wake(struct ath5k_softc *sc)
2662{
2663 int ret;
2664
2665 ret = ath5k_reset(sc, true, true);
2666 if (!ret)
2667 ieee80211_wake_queues(sc->hw);
2668
2669 return ret;
2670}
2671
fa1c114f
JS		 2672static int ath5k_start(struct ieee80211_hw *hw)
2673{
2674 return ath5k_init(hw->priv);
2675}
2676
2677static void ath5k_stop(struct ieee80211_hw *hw)
2678{
2679 ath5k_stop_hw(hw->priv);
2680}
2681
2682static int ath5k_add_interface(struct ieee80211_hw *hw,
2683 struct ieee80211_if_init_conf *conf)
2684{
2685 struct ath5k_softc *sc = hw->priv;
2686 int ret;
2687
2688 mutex_lock(&sc->lock);
32bfd35d 2689 if (sc->vif) {
fa1c114f
JS		 2690 ret = 0;
2691 goto end;
2692 }
2693
32bfd35d 2694 sc->vif = conf->vif;
fa1c114f
JS		 2695
2696 switch (conf->type) {
05c914fe
JB		 2697 case NL80211_IFTYPE_STATION:
2698 case NL80211_IFTYPE_ADHOC:
2699 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2700 sc->opmode = conf->type;
2701 break;
2702 default:
2703 ret = -EOPNOTSUPP;
2704 goto end;
2705 }
67d2e2df
JS		 2706
2707 /* Set to a reasonable value. Note that this will
2708 * be set to mac80211's value at ath5k_config(). */
2709 sc->bintval = 1000;
2710
fa1c114f
JS		 2711 ret = 0;
2712end:
2713 mutex_unlock(&sc->lock);
2714 return ret;
2715}
2716
2717static void
2718ath5k_remove_interface(struct ieee80211_hw *hw,
2719 struct ieee80211_if_init_conf *conf)
2720{
2721 struct ath5k_softc *sc = hw->priv;
2722
2723 mutex_lock(&sc->lock);
32bfd35d 2724 if (sc->vif != conf->vif)
fa1c114f
JS		 2725 goto end;
2726
32bfd35d 2727 sc->vif = NULL;
fa1c114f
JS		 2728end:
2729 mutex_unlock(&sc->lock);
2730}
2731
d8ee398d
LR		 2732/*
2733 * TODO: Phy disable/diversity etc
2734 */
fa1c114f
JS		 2735static int
2736ath5k_config(struct ieee80211_hw *hw,
2737 struct ieee80211_conf *conf)
2738{
2739 struct ath5k_softc *sc = hw->priv;
2740
e535c1ac 2741 sc->bintval = conf->beacon_int;
d8ee398d 2742 sc->power_level = conf->power_level;
fa1c114f 2743
d8ee398d 2744 return ath5k_chan_set(sc, conf->channel);
fa1c114f
JS		 2745}
2746
2747static int
32bfd35d 2748ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2749 struct ieee80211_if_conf *conf)
2750{
2751 struct ath5k_softc *sc = hw->priv;
2752 struct ath5k_hw *ah = sc->ah;
2753 int ret;
2754
fa1c114f 2755 mutex_lock(&sc->lock);
32bfd35d 2756 if (sc->vif != vif) {
fa1c114f
JS		 2757 ret = -EIO;
2758 goto unlock;
2759 }
2760 if (conf->bssid) {
2761 /* Cache for later use during resets */
2762 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2763 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2764 * a clean way of letting us retrieve this yet. */
2765 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2766 mmiowb();
fa1c114f 2767 }
9d139c81
JB		 2768
2769 if (conf->changed & IEEE80211_IFCC_BEACON &&
05c914fe 2770 vif->type == NL80211_IFTYPE_ADHOC) {
9d139c81
JB		 2771 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2772 if (!beacon) {
2773 ret = -ENOMEM;
2774 goto unlock;
2775 }
2776 /* call old handler for now */
2777 ath5k_beacon_update(hw, beacon);
2778 }
2779
fa1c114f
JS		 2780 mutex_unlock(&sc->lock);
2781
d7dc1003 2782 return ath5k_reset_wake(sc);
fa1c114f
JS		 2783unlock:
2784 mutex_unlock(&sc->lock);
2785 return ret;
2786}
2787
2788#define SUPPORTED_FIF_FLAGS \
2789 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2790 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2791 FIF_BCN_PRBRESP_PROMISC
2792/*
2793 * o always accept unicast, broadcast, and multicast traffic
2794 * o multicast traffic for all BSSIDs will be enabled if mac80211
2795 * says it should be
2796 * o maintain current state of phy ofdm or phy cck error reception.
2797 * If the hardware detects any of these type of errors then
2798 * ath5k_hw_get_rx_filter() will pass to us the respective
2799 * hardware filters to be able to receive these type of frames.
2800 * o probe request frames are accepted only when operating in
2801 * hostap, adhoc, or monitor modes
2802 * o enable promiscuous mode according to the interface state
2803 * o accept beacons:
2804 * - when operating in adhoc mode so the 802.11 layer creates
2805 * node table entries for peers,
2806 * - when operating in station mode for collecting rssi data when
2807 * the station is otherwise quiet, or
2808 * - when scanning
2809 */
2810static void ath5k_configure_filter(struct ieee80211_hw *hw,
2811 unsigned int changed_flags,
2812 unsigned int *new_flags,
2813 int mc_count, struct dev_mc_list *mclist)
2814{
2815 struct ath5k_softc *sc = hw->priv;
2816 struct ath5k_hw *ah = sc->ah;
2817 u32 mfilt[2], val, rfilt;
2818 u8 pos;
2819 int i;
2820
2821 mfilt[0] = 0;
2822 mfilt[1] = 0;
2823
2824 /* Only deal with supported flags */
2825 changed_flags &= SUPPORTED_FIF_FLAGS;
2826 *new_flags &= SUPPORTED_FIF_FLAGS;
2827
2828 /* If HW detects any phy or radar errors, leave those filters on.
2829 * Also, always enable Unicast, Broadcasts and Multicast
2830 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2831 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2832 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2833 AR5K_RX_FILTER_MCAST);
2834
2835 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2836 if (*new_flags & FIF_PROMISC_IN_BSS) {
2837 rfilt |= AR5K_RX_FILTER_PROM;
2838 __set_bit(ATH_STAT_PROMISC, sc->status);
2839 }
2840 else
2841 __clear_bit(ATH_STAT_PROMISC, sc->status);
2842 }
2843
2844 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2845 if (*new_flags & FIF_ALLMULTI) {
2846 mfilt[0] = ~0;
2847 mfilt[1] = ~0;
2848 } else {
2849 for (i = 0; i < mc_count; i++) {
2850 if (!mclist)
2851 break;
2852 /* calculate XOR of eight 6-bit values */
533dd1b0 2853 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2854 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2855 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2856 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2857 pos &= 0x3f;
2858 mfilt[pos / 32] |= (1 << (pos % 32));
2859 /* XXX: we might be able to just do this instead,
2860 * but not sure, needs testing, if we do use this we'd
2861 * neet to inform below to not reset the mcast */
2862 /* ath5k_hw_set_mcast_filterindex(ah,
2863 * mclist->dmi_addr[5]); */
2864 mclist = mclist->next;
2865 }
2866 }
2867
2868 /* This is the best we can do */
2869 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2870 rfilt |= AR5K_RX_FILTER_PHYERR;
2871
2872 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2873 * and probes for any BSSID, this needs testing */
2874 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2875 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2876
2877 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2878 * set we should only pass on control frames for this
2879 * station. This needs testing. I believe right now this
2880 * enables *all* control frames, which is OK.. but
2881 * but we should see if we can improve on granularity */
2882 if (*new_flags & FIF_CONTROL)
2883 rfilt |= AR5K_RX_FILTER_CONTROL;
2884
2885 /* Additional settings per mode -- this is per ath5k */
2886
2887 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2888
05c914fe 2889 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2890 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2891 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2892 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2893 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2894 if (sc->opmode != NL80211_IFTYPE_AP &&
2895 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2896 test_bit(ATH_STAT_PROMISC, sc->status))
2897 rfilt |= AR5K_RX_FILTER_PROM;
05c914fe
JB		 2898 if (sc->opmode == NL80211_IFTYPE_STATION ||
2899 sc->opmode == NL80211_IFTYPE_ADHOC) {
fa1c114f
JS		 2900 rfilt |= AR5K_RX_FILTER_BEACON;
2901 }
2902
2903 /* Set filters */
2904 ath5k_hw_set_rx_filter(ah,rfilt);
2905
2906 /* Set multicast bits */
2907 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2908 /* Set the cached hw filter flags, this will alter actually
2909 * be set in HW */
2910 sc->filter_flags = rfilt;
2911}
2912
2913static int
2914ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2915 const u8 *local_addr, const u8 *addr,
2916 struct ieee80211_key_conf *key)
2917{
2918 struct ath5k_softc *sc = hw->priv;
2919 int ret = 0;
2920
2921 switch(key->alg) {
2922 case ALG_WEP:
6844e63a
LR		 2923 /* XXX: fix hardware encryption, its not working. For now
2924 * allow software encryption */
2925 /* break; */
fa1c114f
JS		 2926 case ALG_TKIP:
2927 case ALG_CCMP:
2928 return -EOPNOTSUPP;
2929 default:
2930 WARN_ON(1);
2931 return -EINVAL;
2932 }
2933
2934 mutex_lock(&sc->lock);
2935
2936 switch (cmd) {
2937 case SET_KEY:
2938 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2939 if (ret) {
2940 ATH5K_ERR(sc, "can't set the key\n");
2941 goto unlock;
2942 }
2943 __set_bit(key->keyidx, sc->keymap);
2944 key->hw_key_idx = key->keyidx;
2945 break;
2946 case DISABLE_KEY:
2947 ath5k_hw_reset_key(sc->ah, key->keyidx);
2948 __clear_bit(key->keyidx, sc->keymap);
2949 break;
2950 default:
2951 ret = -EINVAL;
2952 goto unlock;
2953 }
2954
2955unlock:
274c7c36 2956 mmiowb();
fa1c114f
JS		 2957 mutex_unlock(&sc->lock);
2958 return ret;
2959}
2960
2961static int
2962ath5k_get_stats(struct ieee80211_hw *hw,
2963 struct ieee80211_low_level_stats *stats)
2964{
2965 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2966 struct ath5k_hw *ah = sc->ah;
2967
2968 /* Force update */
2969 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2970
2971 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2972
2973 return 0;
2974}
2975
2976static int
2977ath5k_get_tx_stats(struct ieee80211_hw *hw,
2978 struct ieee80211_tx_queue_stats *stats)
2979{
2980 struct ath5k_softc *sc = hw->priv;
2981
2982 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2983
2984 return 0;
2985}
2986
2987static u64
2988ath5k_get_tsf(struct ieee80211_hw *hw)
2989{
2990 struct ath5k_softc *sc = hw->priv;
2991
2992 return ath5k_hw_get_tsf64(sc->ah);
2993}
2994
2995static void
2996ath5k_reset_tsf(struct ieee80211_hw *hw)
2997{
2998 struct ath5k_softc *sc = hw->priv;
2999
9804b98d
BR		 3000 /*
3001 * in IBSS mode we need to update the beacon timers too.
3002 * this will also reset the TSF if we call it with 0
3003 */
05c914fe 3004 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3005 ath5k_beacon_update_timers(sc, 0);
3006 else
3007 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3008}
3009
3010static int
e039fa4a 3011ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 3012{
3013 struct ath5k_softc *sc = hw->priv;
00482973 3014 unsigned long flags;
fa1c114f
JS		 3015 int ret;
3016
3017 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3018
05c914fe 3019 if (sc->opmode != NL80211_IFTYPE_ADHOC) {
fa1c114f
JS		 3020 ret = -EIO;
3021 goto end;
3022 }
3023
00482973 3024 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3025 ath5k_txbuf_free(sc, sc->bbuf);
3026 sc->bbuf->skb = skb;
e039fa4a 3027 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3028 if (ret)
3029 sc->bbuf->skb = NULL;
00482973
JS		 3030 spin_unlock_irqrestore(&sc->block, flags);
3031 if (!ret) {
fa1c114f 3032 ath5k_beacon_config(sc);
274c7c36
JS		 3033 mmiowb();
3034 }
fa1c114f
JS		 3035
3036end:
fa1c114f
JS		 3037 return ret;
3038}
3039
Clone of davem's net-next-2.6 tree