git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| f078f209 | 1 | /* |
| cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
| f078f209 LR |
3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any | |
| 5 | * purpose with or without fee is hereby granted, provided that the above | |
| 6 | * copyright notice and this permission notice appear in all copies. | |
| 7 | * | |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| 15 | */ | |
| 16 | ||
| 17 | #ifndef PHY_H | |
| 18 | #define PHY_H | |
| 19 | ||
| 7152451a LR |
20 | #define CHANSEL_DIV 15 |
| 21 | #define CHANSEL_2G(_freq) (((_freq) * 0x10000) / CHANSEL_DIV) | |
| 22 | #define CHANSEL_5G(_freq) (((_freq) * 0x8000) / CHANSEL_DIV) | |
| 23 | ||
| f078f209 LR |
24 | #define AR_PHY_BASE 0x9800 |
| 25 | #define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) | |
| 26 | ||
| 53bc7aa0 VN |
27 | #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 |
| 28 | #define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 | |
| 53bc7aa0 VN |
29 | #define AR_PHY_TX_GAIN_CLC 0x0000001E |
| 30 | #define AR_PHY_TX_GAIN_CLC_S 1 | |
| 31 | #define AR_PHY_TX_GAIN 0x0007F000 | |
| 32 | #define AR_PHY_TX_GAIN_S 12 | |
| 33 | ||
| 34 | #define AR_PHY_CLC_TBL1 0xa35c | |
| 35 | #define AR_PHY_CLC_I0 0x07ff0000 | |
| 36 | #define AR_PHY_CLC_I0_S 16 | |
| 37 | #define AR_PHY_CLC_Q0 0x0000ffd0 | |
| 38 | #define AR_PHY_CLC_Q0_S 5 | |
| 8bd1d07f | 39 | |
| f078f209 LR |
40 | #define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \ |
| 41 | int r; \ | |
| 42 | for (r = 0; r < ((iniarray)->ia_rows); r++) { \ | |
| 43 | REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \ | |
| f078f209 LR |
44 | DO_DELAY(regWr); \ |
| 45 | } \ | |
| 46 | } while (0) | |
| 47 | ||
| f078f209 LR |
48 | #define ANTSWAP_AB 0x0001 |
| 49 | #define REDUCE_CHAIN_0 0x00000050 | |
| 50 | #define REDUCE_CHAIN_1 0x00000051 | |
| 8fe65368 | 51 | #define AR_PHY_CHIP_ID 0x9818 |
| f078f209 LR |
52 | |
| 53 | #define RF_BANK_SETUP(_bank, _iniarray, _col) do { \ | |
| 54 | int i; \ | |
| 55 | for (i = 0; i < (_iniarray)->ia_rows; i++) \ | |
| 56 | (_bank)[i] = INI_RA((_iniarray), i, _col);; \ | |
| 57 | } while (0) | |
| 58 | ||
| 1547da37 LR |
59 | #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000 |
| 60 | #define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20 | |
| 61 | ||
| f078f209 | 62 | #endif |