[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / pci.c

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/nl80211.h>
#include <linux/pci.h>
#include "ath9k.h"

static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI   */
	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
	{ 0 }
};

/* return bus cachesize in 4B word units */
static void ath_pci_read_cachesize(struct ath_common *common, int *csz)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	u8 u8tmp;

	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
	*csz = (int)u8tmp;

	/*
	 * This check was put in to avoid "unplesant" consequences if
	 * the bootrom has not fully initialized all PCI devices.
	 * Sometimes the cache line size register is not set
	 */

	if (*csz == 0)
		*csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
}

static void ath_pci_cleanup(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct pci_dev *pdev = to_pci_dev(sc->dev);

	pci_iounmap(pdev, sc->mem);
	pci_disable_device(pdev);
	pci_release_region(pdev, 0);
}

static bool ath_pci_eeprom_read(struct ath_common *common, u32 off, u16 *data)
{
	struct ath_hw *ah = (struct ath_hw *) common->ah;

	common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));

	if (!ath9k_hw_wait(ah,
			   AR_EEPROM_STATUS_DATA,
			   AR_EEPROM_STATUS_DATA_BUSY |
			   AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
			   AH_WAIT_TIMEOUT)) {
		return false;
	}

	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
		   AR_EEPROM_STATUS_DATA_VAL);

	return true;
}

/*
 * Bluetooth coexistance requires disabling ASPM.
 */
static void ath_pci_bt_coex_prep(struct ath_common *common)
{
	struct ath_softc *sc = (struct ath_softc *) common->priv;
	struct pci_dev *pdev = to_pci_dev(sc->dev);
	u8 aspm;

	if (!pdev->is_pcie)
		return;

	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
	aspm &= ~(ATH_PCIE_CAP_LINK_L0S | ATH_PCIE_CAP_LINK_L1);
	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
}

static const struct ath_bus_ops ath_pci_bus_ops = {
	.read_cachesize = ath_pci_read_cachesize,
	.cleanup = ath_pci_cleanup,
	.eeprom_read = ath_pci_eeprom_read,
	.bt_coex_prep = ath_pci_bt_coex_prep,
};

static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
	void __iomem *mem;
	struct ath_wiphy *aphy;
	struct ath_softc *sc;
	struct ieee80211_hw *hw;
	u8 csz;
	u16 subsysid;
	u32 val;
	int ret = 0;
	struct ath_hw *ah;
	char hw_name[64];

	if (pci_enable_device(pdev))
		return -EIO;

	ret =  pci_set_dma_mask(pdev, DMA_BIT_MASK(32));

	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
		goto bad;
	}

	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));

	if (ret) {
		printk(KERN_ERR "ath9k: 32-bit DMA consistent "
			"DMA enable failed\n");
		goto bad;
	}

	/*
	 * Cache line size is used to size and align various
	 * structures used to communicate with the hardware.
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	if (csz == 0) {
		/*
		 * Linux 2.4.18 (at least) writes the cache line size
		 * register as a 16-bit wide register which is wrong.
		 * We must have this setup properly for rx buffer
		 * DMA to work so force a reasonable value here if it
		 * comes up zero.
		 */
		csz = L1_CACHE_BYTES / sizeof(u32);
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	}
	/*
	 * The default setting of latency timer yields poor results,
	 * set it to the value used by other systems. It may be worth
	 * tweaking this setting more.
	 */
	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);

	pci_set_master(pdev);

	/*
	 * Disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state.
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	ret = pci_request_region(pdev, 0, "ath9k");
	if (ret) {
		dev_err(&pdev->dev, "PCI memory region reserve error\n");
		ret = -ENODEV;
		goto bad;
	}

	mem = pci_iomap(pdev, 0, 0);
	if (!mem) {
		printk(KERN_ERR "PCI memory map error\n") ;
		ret = -EIO;
		goto bad1;
	}

	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
				sizeof(struct ath_softc), &ath9k_ops);
	if (!hw) {
		dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
		ret = -ENOMEM;
		goto bad2;
	}

	SET_IEEE80211_DEV(hw, &pdev->dev);
	pci_set_drvdata(pdev, hw);

	aphy = hw->priv;
	sc = (struct ath_softc *) (aphy + 1);
	aphy->sc = sc;
	aphy->hw = hw;
	sc->pri_wiphy = aphy;
	sc->hw = hw;
	sc->dev = &pdev->dev;
	sc->mem = mem;

	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
	ret = ath_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize device\n");
		goto bad3;
	}

	/* setup interrupt service routine */

	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
	if (ret) {
		dev_err(&pdev->dev, "request_irq failed\n");
		goto bad4;
	}

	sc->irq = pdev->irq;

	ah = sc->sc_ah;
	ath9k_hw_name(ah, hw_name, sizeof(hw_name));
	printk(KERN_INFO
	       "%s: %s mem=0x%lx, irq=%d\n",
	       wiphy_name(hw->wiphy),
	       hw_name,
	       (unsigned long)mem, pdev->irq);

	return 0;
bad4:
	ath_detach(sc);
bad3:
	ieee80211_free_hw(hw);
bad2:
	pci_iounmap(pdev, mem);
bad1:
	pci_release_region(pdev, 0);
bad:
	pci_disable_device(pdev);
	return ret;
}

static void ath_pci_remove(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;

	ath_cleanup(sc);
}

#ifdef CONFIG_PM

static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;

	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	pci_save_state(pdev);
	pci_disable_device(pdev);
	pci_set_power_state(pdev, PCI_D3hot);

	return 0;
}

static int ath_pci_resume(struct pci_dev *pdev)
{
	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
	struct ath_wiphy *aphy = hw->priv;
	struct ath_softc *sc = aphy->sc;
	u32 val;
	int err;

	pci_restore_state(pdev);

	err = pci_enable_device(pdev);
	if (err)
		return err;

	/*
	 * Suspend/Resume resets the PCI configuration space, so we have to
	 * re-disable the RETRY_TIMEOUT register (0x41) to keep
	 * PCI Tx retries from interfering with C3 CPU state
	 */
	pci_read_config_dword(pdev, 0x40, &val);
	if ((val & 0x0000ff00) != 0)
		pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);

	/* Enable LED */
	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
			    AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);

	return 0;
}

#endif /* CONFIG_PM */

MODULE_DEVICE_TABLE(pci, ath_pci_id_table);

static struct pci_driver ath_pci_driver = {
	.name       = "ath9k",
	.id_table   = ath_pci_id_table,
	.probe      = ath_pci_probe,
	.remove     = ath_pci_remove,
#ifdef CONFIG_PM
	.suspend    = ath_pci_suspend,
	.resume     = ath_pci_resume,
#endif /* CONFIG_PM */
};

int ath_pci_init(void)
{
	return pci_register_driver(&ath_pci_driver);
}

void ath_pci_exit(void)
{
	pci_unregister_driver(&ath_pci_driver);
}
Commit	Line	Data
6baff7f9	1	/*
cee075a2	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
6baff7f9 GJ	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#include <linux/nl80211.h>
	18	#include <linux/pci.h>
394cf0a1	19	#include "ath9k.h"
6baff7f9	20
a3aa1884	21	static DEFINE_PCI_DEVICE_TABLE(ath_pci_id_table) = {
6baff7f9 GJ	22	{ PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
	23	{ PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
	24	{ PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
	25	{ PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
	26	{ PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
	27	{ PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
ac88b6ec VN	28	{ PCI_VDEVICE(ATHEROS, 0x002D) }, /* PCI */
ac88b6ec VN	29	{ PCI_VDEVICE(ATHEROS, 0x002E) }, /* PCI-E */
6baff7f9 GJ	30	{ 0 }
	31	};
	32
	33	/* return bus cachesize in 4B word units */
5bb12791	34	static void ath_pci_read_cachesize(struct ath_common common, int csz)
6baff7f9	35	{
bc974f4a	36	struct ath_softc sc = (struct ath_softc ) common->priv;
6baff7f9 GJ	37	u8 u8tmp;
6baff7f9 GJ	38
f020979d	39	pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE, &u8tmp);
6baff7f9 GJ	40	*csz = (int)u8tmp;
	41
	42	/*
	43	* This check was put in to avoid "unplesant" consequences if
	44	* the bootrom has not fully initialized all PCI devices.
	45	* Sometimes the cache line size register is not set
	46	*/
	47
	48	if (*csz == 0)
	49	csz = DEFAULT_CACHELINE >> 2; / Use the default size */
	50	}
	51
5bb12791	52	static void ath_pci_cleanup(struct ath_common *common)
6baff7f9	53	{
bc974f4a	54	struct ath_softc sc = (struct ath_softc ) common->priv;
6baff7f9 GJ	55	struct pci_dev *pdev = to_pci_dev(sc->dev);
	56
	57	pci_iounmap(pdev, sc->mem);
6baff7f9	58	pci_disable_device(pdev);
db0f41f5	59	pci_release_region(pdev, 0);
6baff7f9 GJ	60	}
6baff7f9 GJ	61
5bb12791	62	static bool ath_pci_eeprom_read(struct ath_common common, u32 off, u16 data)
9dbeb91a	63	{
5bb12791 LR	64	struct ath_hw ah = (struct ath_hw ) common->ah;
5bb12791 LR	65
475a6e4d	66	common->ops->read(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
9dbeb91a GJ	67
	68	if (!ath9k_hw_wait(ah,
	69	AR_EEPROM_STATUS_DATA,
	70	AR_EEPROM_STATUS_DATA_BUSY \|
0caa7b14 S	71	AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
0caa7b14 S	72	AH_WAIT_TIMEOUT)) {
9dbeb91a GJ	73	return false;
	74	}
	75
475a6e4d	76	*data = MS(common->ops->read(ah, AR_EEPROM_STATUS_DATA),
9dbeb91a GJ	77	AR_EEPROM_STATUS_DATA_VAL);
	78
	79	return true;
	80	}
	81
867633f0 LR	82	/*
	83	* Bluetooth coexistance requires disabling ASPM.
	84	*/
5bb12791	85	static void ath_pci_bt_coex_prep(struct ath_common *common)
867633f0	86	{
bc974f4a	87	struct ath_softc sc = (struct ath_softc ) common->priv;
867633f0 LR	88	struct pci_dev *pdev = to_pci_dev(sc->dev);
	89	u8 aspm;
	90
	91	if (!pdev->is_pcie)
	92	return;
	93
	94	pci_read_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, &aspm);
	95	aspm &= ~(ATH_PCIE_CAP_LINK_L0S \| ATH_PCIE_CAP_LINK_L1);
	96	pci_write_config_byte(pdev, ATH_PCIE_CAP_LINK_CTRL, aspm);
	97	}
	98
83bd11a0	99	static const struct ath_bus_ops ath_pci_bus_ops = {
6baff7f9 GJ	100	.read_cachesize = ath_pci_read_cachesize,
6baff7f9 GJ	101	.cleanup = ath_pci_cleanup,
9dbeb91a	102	.eeprom_read = ath_pci_eeprom_read,
867633f0	103	.bt_coex_prep = ath_pci_bt_coex_prep,
6baff7f9 GJ	104	};
	105
	106	static int ath_pci_probe(struct pci_dev pdev, const struct pci_device_id id)
	107	{
	108	void __iomem *mem;
bce048d7	109	struct ath_wiphy *aphy;
6baff7f9 GJ	110	struct ath_softc *sc;
	111	struct ieee80211_hw *hw;
	112	u8 csz;
aeac355d	113	u16 subsysid;
f0214843	114	u32 val;
6baff7f9	115	int ret = 0;
cbe61d8a	116	struct ath_hw *ah;
f934c4d9	117	char hw_name[64];
6baff7f9 GJ	118
	119	if (pci_enable_device(pdev))
	120	return -EIO;
	121
e930438c	122	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	123
	124	if (ret) {
	125	printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
	126	goto bad;
	127	}
	128
e930438c	129	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6baff7f9 GJ	130
	131	if (ret) {
	132	printk(KERN_ERR "ath9k: 32-bit DMA consistent "
	133	"DMA enable failed\n");
	134	goto bad;
	135	}
	136
	137	/*
	138	* Cache line size is used to size and align various
	139	* structures used to communicate with the hardware.
	140	*/
	141	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
	142	if (csz == 0) {
	143	/*
	144	* Linux 2.4.18 (at least) writes the cache line size
	145	* register as a 16-bit wide register which is wrong.
	146	* We must have this setup properly for rx buffer
	147	* DMA to work so force a reasonable value here if it
	148	* comes up zero.
	149	*/
	150	csz = L1_CACHE_BYTES / sizeof(u32);
	151	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
	152	}
	153	/*
	154	* The default setting of latency timer yields poor results,
	155	* set it to the value used by other systems. It may be worth
	156	* tweaking this setting more.
	157	*/
	158	pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
	159
	160	pci_set_master(pdev);
	161
f0214843 JM	162	/*
	163	* Disable the RETRY_TIMEOUT register (0x41) to keep
	164	* PCI Tx retries from interfering with C3 CPU state.
	165	*/
	166	pci_read_config_dword(pdev, 0x40, &val);
	167	if ((val & 0x0000ff00) != 0)
	168	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
	169
6baff7f9 GJ	170	ret = pci_request_region(pdev, 0, "ath9k");
	171	if (ret) {
	172	dev_err(&pdev->dev, "PCI memory region reserve error\n");
	173	ret = -ENODEV;
	174	goto bad;
	175	}
	176
	177	mem = pci_iomap(pdev, 0, 0);
	178	if (!mem) {
	179	printk(KERN_ERR "PCI memory map error\n") ;
	180	ret = -EIO;
	181	goto bad1;
	182	}
	183
bce048d7 JM	184	hw = ieee80211_alloc_hw(sizeof(struct ath_wiphy) +
bce048d7 JM	185	sizeof(struct ath_softc), &ath9k_ops);
db6be53c LR	186	if (!hw) {
	187	dev_err(&pdev->dev, "no memory for ieee80211_hw\n");
	188	ret = -ENOMEM;
6baff7f9 GJ	189	goto bad2;
	190	}
	191
	192	SET_IEEE80211_DEV(hw, &pdev->dev);
	193	pci_set_drvdata(pdev, hw);
	194
bce048d7 JM	195	aphy = hw->priv;
	196	sc = (struct ath_softc *) (aphy + 1);
	197	aphy->sc = sc;
	198	aphy->hw = hw;
	199	sc->pri_wiphy = aphy;
6baff7f9 GJ	200	sc->hw = hw;
	201	sc->dev = &pdev->dev;
	202	sc->mem = mem;
6baff7f9	203
aeac355d	204	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &subsysid);
5bb12791	205	ret = ath_init_device(id->device, sc, subsysid, &ath_pci_bus_ops);
580171f7 LR	206	if (ret) {
580171f7 LR	207	dev_err(&pdev->dev, "failed to initialize device\n");
6baff7f9 GJ	208	goto bad3;
	209	}
	210
	211	/* setup interrupt service routine */
	212
fc548af8	213	ret = request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath9k", sc);
580171f7 LR	214	if (ret) {
580171f7 LR	215	dev_err(&pdev->dev, "request_irq failed\n");
6baff7f9 GJ	216	goto bad4;
	217	}
	218
	219	sc->irq = pdev->irq;
	220
	221	ah = sc->sc_ah;
f934c4d9	222	ath9k_hw_name(ah, hw_name, sizeof(hw_name));
6baff7f9	223	printk(KERN_INFO
f934c4d9	224	"%s: %s mem=0x%lx, irq=%d\n",
6baff7f9	225	wiphy_name(hw->wiphy),
f934c4d9	226	hw_name,
6baff7f9 GJ	227	(unsigned long)mem, pdev->irq);
	228
	229	return 0;
	230	bad4:
	231	ath_detach(sc);
	232	bad3:
	233	ieee80211_free_hw(hw);
	234	bad2:
	235	pci_iounmap(pdev, mem);
	236	bad1:
	237	pci_release_region(pdev, 0);
	238	bad:
	239	pci_disable_device(pdev);
	240	return ret;
	241	}
	242
	243	static void ath_pci_remove(struct pci_dev *pdev)
	244	{
	245	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	246	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	247	struct ath_softc *sc = aphy->sc;
6baff7f9 GJ	248
	249	ath_cleanup(sc);
	250	}
	251
	252	#ifdef CONFIG_PM
	253
	254	static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
	255	{
	256	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	257	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	258	struct ath_softc *sc = aphy->sc;
6baff7f9	259
08fc5c1b	260	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	261
6baff7f9 GJ	262	pci_save_state(pdev);
	263	pci_disable_device(pdev);
	264	pci_set_power_state(pdev, PCI_D3hot);
	265
	266	return 0;
	267	}
	268
	269	static int ath_pci_resume(struct pci_dev *pdev)
	270	{
	271	struct ieee80211_hw *hw = pci_get_drvdata(pdev);
bce048d7 JM	272	struct ath_wiphy *aphy = hw->priv;
bce048d7 JM	273	struct ath_softc *sc = aphy->sc;
f0214843	274	u32 val;
6baff7f9 GJ	275	int err;
6baff7f9 GJ	276
523c36fc S	277	pci_restore_state(pdev);
523c36fc S	278
6baff7f9 GJ	279	err = pci_enable_device(pdev);
	280	if (err)
	281	return err;
523c36fc	282
f0214843 JM	283	/*
	284	* Suspend/Resume resets the PCI configuration space, so we have to
	285	* re-disable the RETRY_TIMEOUT register (0x41) to keep
	286	* PCI Tx retries from interfering with C3 CPU state
	287	*/
	288	pci_read_config_dword(pdev, 0x40, &val);
	289	if ((val & 0x0000ff00) != 0)
	290	pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
6baff7f9 GJ	291
6baff7f9 GJ	292	/* Enable LED */
08fc5c1b	293	ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
6baff7f9	294	AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b	295	ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
6baff7f9	296
6baff7f9 GJ	297	return 0;
	298	}
	299
	300	#endif /* CONFIG_PM */
	301
	302	MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
	303
	304	static struct pci_driver ath_pci_driver = {
	305	.name = "ath9k",
	306	.id_table = ath_pci_id_table,
	307	.probe = ath_pci_probe,
	308	.remove = ath_pci_remove,
	309	#ifdef CONFIG_PM
	310	.suspend = ath_pci_suspend,
	311	.resume = ath_pci_resume,
	312	#endif /* CONFIG_PM */
	313	};
	314
db0f41f5	315	int ath_pci_init(void)
6baff7f9 GJ	316	{
	317	return pci_register_driver(&ath_pci_driver);
	318	}
	319
	320	void ath_pci_exit(void)
	321	{
	322	pci_unregister_driver(&ath_pci_driver);
	323	}