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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
f078f209 | 17 | #include <linux/nl80211.h> |
394cf0a1 | 18 | #include "ath9k.h" |
af03abec | 19 | #include "btcoex.h" |
f078f209 | 20 | |
ce111bad LR |
21 | static void ath_cache_conf_rate(struct ath_softc *sc, |
22 | struct ieee80211_conf *conf) | |
ff37e337 | 23 | { |
030bb495 LR |
24 | switch (conf->channel->band) { |
25 | case IEEE80211_BAND_2GHZ: | |
26 | if (conf_is_ht20(conf)) | |
545750d3 | 27 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT20; |
030bb495 | 28 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 29 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS; |
030bb495 | 30 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 31 | sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS; |
96742256 | 32 | else |
545750d3 | 33 | sc->cur_rate_mode = ATH9K_MODE_11G; |
030bb495 LR |
34 | break; |
35 | case IEEE80211_BAND_5GHZ: | |
36 | if (conf_is_ht20(conf)) | |
545750d3 | 37 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT20; |
030bb495 | 38 | else if (conf_is_ht40_minus(conf)) |
545750d3 | 39 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS; |
030bb495 | 40 | else if (conf_is_ht40_plus(conf)) |
545750d3 | 41 | sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS; |
030bb495 | 42 | else |
545750d3 | 43 | sc->cur_rate_mode = ATH9K_MODE_11A; |
030bb495 LR |
44 | break; |
45 | default: | |
ce111bad | 46 | BUG_ON(1); |
030bb495 LR |
47 | break; |
48 | } | |
ff37e337 S |
49 | } |
50 | ||
51 | static void ath_update_txpow(struct ath_softc *sc) | |
52 | { | |
cbe61d8a | 53 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
54 | u32 txpow; |
55 | ||
17d7904d S |
56 | if (sc->curtxpow != sc->config.txpowlimit) { |
57 | ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit); | |
ff37e337 S |
58 | /* read back in case value is clamped */ |
59 | ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow); | |
17d7904d | 60 | sc->curtxpow = txpow; |
ff37e337 S |
61 | } |
62 | } | |
63 | ||
64 | static u8 parse_mpdudensity(u8 mpdudensity) | |
65 | { | |
66 | /* | |
67 | * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing": | |
68 | * 0 for no restriction | |
69 | * 1 for 1/4 us | |
70 | * 2 for 1/2 us | |
71 | * 3 for 1 us | |
72 | * 4 for 2 us | |
73 | * 5 for 4 us | |
74 | * 6 for 8 us | |
75 | * 7 for 16 us | |
76 | */ | |
77 | switch (mpdudensity) { | |
78 | case 0: | |
79 | return 0; | |
80 | case 1: | |
81 | case 2: | |
82 | case 3: | |
83 | /* Our lower layer calculations limit our precision to | |
84 | 1 microsecond */ | |
85 | return 1; | |
86 | case 4: | |
87 | return 2; | |
88 | case 5: | |
89 | return 4; | |
90 | case 6: | |
91 | return 8; | |
92 | case 7: | |
93 | return 16; | |
94 | default: | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | ||
82880a7c VT |
99 | static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc, |
100 | struct ieee80211_hw *hw) | |
101 | { | |
102 | struct ieee80211_channel *curchan = hw->conf.channel; | |
103 | struct ath9k_channel *channel; | |
104 | u8 chan_idx; | |
105 | ||
106 | chan_idx = curchan->hw_value; | |
107 | channel = &sc->sc_ah->channels[chan_idx]; | |
108 | ath9k_update_ichannel(sc, hw, channel); | |
109 | return channel; | |
110 | } | |
111 | ||
55624204 | 112 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode) |
8c77a569 LR |
113 | { |
114 | unsigned long flags; | |
115 | bool ret; | |
116 | ||
9ecdef4b LR |
117 | spin_lock_irqsave(&sc->sc_pm_lock, flags); |
118 | ret = ath9k_hw_setpower(sc->sc_ah, mode); | |
119 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
8c77a569 LR |
120 | |
121 | return ret; | |
122 | } | |
123 | ||
a91d75ae LR |
124 | void ath9k_ps_wakeup(struct ath_softc *sc) |
125 | { | |
126 | unsigned long flags; | |
127 | ||
128 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
129 | if (++sc->ps_usecount != 1) | |
130 | goto unlock; | |
131 | ||
9ecdef4b | 132 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); |
a91d75ae LR |
133 | |
134 | unlock: | |
135 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
136 | } | |
137 | ||
138 | void ath9k_ps_restore(struct ath_softc *sc) | |
139 | { | |
140 | unsigned long flags; | |
141 | ||
142 | spin_lock_irqsave(&sc->sc_pm_lock, flags); | |
143 | if (--sc->ps_usecount != 0) | |
144 | goto unlock; | |
145 | ||
1dbfd9d4 VN |
146 | if (sc->ps_idle) |
147 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP); | |
148 | else if (sc->ps_enabled && | |
149 | !(sc->ps_flags & (PS_WAIT_FOR_BEACON | | |
1b04b930 S |
150 | PS_WAIT_FOR_CAB | |
151 | PS_WAIT_FOR_PSPOLL_DATA | | |
152 | PS_WAIT_FOR_TX_ACK))) | |
9ecdef4b | 153 | ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP); |
a91d75ae LR |
154 | |
155 | unlock: | |
156 | spin_unlock_irqrestore(&sc->sc_pm_lock, flags); | |
157 | } | |
158 | ||
ff37e337 S |
159 | /* |
160 | * Set/change channels. If the channel is really being changed, it's done | |
161 | * by reseting the chip. To accomplish this we must first cleanup any pending | |
162 | * DMA, then restart stuff. | |
163 | */ | |
0e2dedf9 JM |
164 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, |
165 | struct ath9k_channel *hchan) | |
ff37e337 | 166 | { |
cbe61d8a | 167 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 168 | struct ath_common *common = ath9k_hw_common(ah); |
25c56eec | 169 | struct ieee80211_conf *conf = &common->hw->conf; |
ff37e337 | 170 | bool fastcc = true, stopped; |
ae8d2858 LR |
171 | struct ieee80211_channel *channel = hw->conf.channel; |
172 | int r; | |
ff37e337 S |
173 | |
174 | if (sc->sc_flags & SC_OP_INVALID) | |
175 | return -EIO; | |
176 | ||
3cbb5dd7 VN |
177 | ath9k_ps_wakeup(sc); |
178 | ||
c0d7c7af LR |
179 | /* |
180 | * This is only performed if the channel settings have | |
181 | * actually changed. | |
182 | * | |
183 | * To switch channels clear any pending DMA operations; | |
184 | * wait long enough for the RX fifo to drain, reset the | |
185 | * hardware at the new frequency, and then re-enable | |
186 | * the relevant bits of the h/w. | |
187 | */ | |
188 | ath9k_hw_set_interrupts(ah, 0); | |
043a0405 | 189 | ath_drain_all_txq(sc, false); |
c0d7c7af | 190 | stopped = ath_stoprecv(sc); |
ff37e337 | 191 | |
c0d7c7af LR |
192 | /* XXX: do not flush receive queue here. We don't want |
193 | * to flush data frames already in queue because of | |
194 | * changing channel. */ | |
ff37e337 | 195 | |
c0d7c7af LR |
196 | if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) |
197 | fastcc = false; | |
198 | ||
c46917bb | 199 | ath_print(common, ATH_DBG_CONFIG, |
25c56eec | 200 | "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n", |
c46917bb | 201 | sc->sc_ah->curchan->channel, |
25c56eec | 202 | channel->center_freq, conf_is_ht40(conf)); |
ff37e337 | 203 | |
c0d7c7af LR |
204 | spin_lock_bh(&sc->sc_resetlock); |
205 | ||
206 | r = ath9k_hw_reset(ah, hchan, fastcc); | |
207 | if (r) { | |
c46917bb | 208 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 209 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
210 | "reset status %d\n", |
211 | channel->center_freq, r); | |
c0d7c7af | 212 | spin_unlock_bh(&sc->sc_resetlock); |
3989279c | 213 | goto ps_restore; |
ff37e337 | 214 | } |
c0d7c7af LR |
215 | spin_unlock_bh(&sc->sc_resetlock); |
216 | ||
c0d7c7af LR |
217 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
218 | ||
219 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
220 | ath_print(common, ATH_DBG_FATAL, |
221 | "Unable to restart recv logic\n"); | |
3989279c GJ |
222 | r = -EIO; |
223 | goto ps_restore; | |
c0d7c7af LR |
224 | } |
225 | ||
226 | ath_cache_conf_rate(sc, &hw->conf); | |
227 | ath_update_txpow(sc); | |
3069168c | 228 | ath9k_hw_set_interrupts(ah, ah->imask); |
3989279c GJ |
229 | |
230 | ps_restore: | |
3cbb5dd7 | 231 | ath9k_ps_restore(sc); |
3989279c | 232 | return r; |
ff37e337 S |
233 | } |
234 | ||
235 | /* | |
236 | * This routine performs the periodic noise floor calibration function | |
237 | * that is used to adjust and optimize the chip performance. This | |
238 | * takes environmental changes (location, temperature) into account. | |
239 | * When the task is complete, it reschedules itself depending on the | |
240 | * appropriate interval that was calculated. | |
241 | */ | |
55624204 | 242 | void ath_ani_calibrate(unsigned long data) |
ff37e337 | 243 | { |
20977d3e S |
244 | struct ath_softc *sc = (struct ath_softc *)data; |
245 | struct ath_hw *ah = sc->sc_ah; | |
c46917bb | 246 | struct ath_common *common = ath9k_hw_common(ah); |
ff37e337 S |
247 | bool longcal = false; |
248 | bool shortcal = false; | |
249 | bool aniflag = false; | |
250 | unsigned int timestamp = jiffies_to_msecs(jiffies); | |
20977d3e | 251 | u32 cal_interval, short_cal_interval; |
ff37e337 | 252 | |
20977d3e S |
253 | short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ? |
254 | ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL; | |
ff37e337 | 255 | |
1ffc1c61 JM |
256 | /* Only calibrate if awake */ |
257 | if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE) | |
258 | goto set_timer; | |
259 | ||
260 | ath9k_ps_wakeup(sc); | |
261 | ||
ff37e337 | 262 | /* Long calibration runs independently of short calibration. */ |
3d536acf | 263 | if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { |
ff37e337 | 264 | longcal = true; |
c46917bb | 265 | ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies); |
3d536acf | 266 | common->ani.longcal_timer = timestamp; |
ff37e337 S |
267 | } |
268 | ||
17d7904d | 269 | /* Short calibration applies only while caldone is false */ |
3d536acf LR |
270 | if (!common->ani.caldone) { |
271 | if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) { | |
ff37e337 | 272 | shortcal = true; |
c46917bb LR |
273 | ath_print(common, ATH_DBG_ANI, |
274 | "shortcal @%lu\n", jiffies); | |
3d536acf LR |
275 | common->ani.shortcal_timer = timestamp; |
276 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
277 | } |
278 | } else { | |
3d536acf | 279 | if ((timestamp - common->ani.resetcal_timer) >= |
ff37e337 | 280 | ATH_RESTART_CALINTERVAL) { |
3d536acf LR |
281 | common->ani.caldone = ath9k_hw_reset_calvalid(ah); |
282 | if (common->ani.caldone) | |
283 | common->ani.resetcal_timer = timestamp; | |
ff37e337 S |
284 | } |
285 | } | |
286 | ||
287 | /* Verify whether we must check ANI */ | |
3d536acf | 288 | if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) { |
ff37e337 | 289 | aniflag = true; |
3d536acf | 290 | common->ani.checkani_timer = timestamp; |
ff37e337 S |
291 | } |
292 | ||
293 | /* Skip all processing if there's nothing to do. */ | |
294 | if (longcal || shortcal || aniflag) { | |
295 | /* Call ANI routine if necessary */ | |
296 | if (aniflag) | |
22e66a4c | 297 | ath9k_hw_ani_monitor(ah, ah->curchan); |
ff37e337 S |
298 | |
299 | /* Perform calibration if necessary */ | |
300 | if (longcal || shortcal) { | |
3d536acf | 301 | common->ani.caldone = |
43c27613 LR |
302 | ath9k_hw_calibrate(ah, |
303 | ah->curchan, | |
304 | common->rx_chainmask, | |
305 | longcal); | |
379f0440 S |
306 | |
307 | if (longcal) | |
3d536acf | 308 | common->ani.noise_floor = ath9k_hw_getchan_noise(ah, |
379f0440 S |
309 | ah->curchan); |
310 | ||
c46917bb LR |
311 | ath_print(common, ATH_DBG_ANI, |
312 | " calibrate chan %u/%x nf: %d\n", | |
313 | ah->curchan->channel, | |
314 | ah->curchan->channelFlags, | |
3d536acf | 315 | common->ani.noise_floor); |
ff37e337 S |
316 | } |
317 | } | |
318 | ||
1ffc1c61 JM |
319 | ath9k_ps_restore(sc); |
320 | ||
20977d3e | 321 | set_timer: |
ff37e337 S |
322 | /* |
323 | * Set timer interval based on previous results. | |
324 | * The interval must be the shortest necessary to satisfy ANI, | |
325 | * short calibration and long calibration. | |
326 | */ | |
aac9207e | 327 | cal_interval = ATH_LONG_CALINTERVAL; |
2660b81a | 328 | if (sc->sc_ah->config.enable_ani) |
aac9207e | 329 | cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL); |
3d536acf | 330 | if (!common->ani.caldone) |
20977d3e | 331 | cal_interval = min(cal_interval, (u32)short_cal_interval); |
ff37e337 | 332 | |
3d536acf | 333 | mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval)); |
ff37e337 S |
334 | } |
335 | ||
3d536acf | 336 | static void ath_start_ani(struct ath_common *common) |
415f738e S |
337 | { |
338 | unsigned long timestamp = jiffies_to_msecs(jiffies); | |
6c3118e2 VT |
339 | struct ath_softc *sc = (struct ath_softc *) common->priv; |
340 | ||
341 | if (!(sc->sc_flags & SC_OP_ANI_RUN)) | |
342 | return; | |
415f738e | 343 | |
3d536acf LR |
344 | common->ani.longcal_timer = timestamp; |
345 | common->ani.shortcal_timer = timestamp; | |
346 | common->ani.checkani_timer = timestamp; | |
415f738e | 347 | |
3d536acf | 348 | mod_timer(&common->ani.timer, |
415f738e S |
349 | jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL)); |
350 | } | |
351 | ||
ff37e337 S |
352 | /* |
353 | * Update tx/rx chainmask. For legacy association, | |
354 | * hard code chainmask to 1x1, for 11n association, use | |
c97c92d9 VT |
355 | * the chainmask configuration, for bt coexistence, use |
356 | * the chainmask configuration even in legacy mode. | |
ff37e337 | 357 | */ |
0e2dedf9 | 358 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
ff37e337 | 359 | { |
af03abec | 360 | struct ath_hw *ah = sc->sc_ah; |
43c27613 | 361 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 362 | |
3d832611 | 363 | if ((sc->sc_flags & SC_OP_SCANNING) || is_ht || |
766ec4a9 | 364 | (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) { |
43c27613 LR |
365 | common->tx_chainmask = ah->caps.tx_chainmask; |
366 | common->rx_chainmask = ah->caps.rx_chainmask; | |
ff37e337 | 367 | } else { |
43c27613 LR |
368 | common->tx_chainmask = 1; |
369 | common->rx_chainmask = 1; | |
ff37e337 S |
370 | } |
371 | ||
43c27613 | 372 | ath_print(common, ATH_DBG_CONFIG, |
c46917bb | 373 | "tx chmask: %d, rx chmask: %d\n", |
43c27613 LR |
374 | common->tx_chainmask, |
375 | common->rx_chainmask); | |
ff37e337 S |
376 | } |
377 | ||
378 | static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
379 | { | |
380 | struct ath_node *an; | |
381 | ||
382 | an = (struct ath_node *)sta->drv_priv; | |
383 | ||
87792efc | 384 | if (sc->sc_flags & SC_OP_TXAGGR) { |
ff37e337 | 385 | ath_tx_node_init(sc, an); |
9e98ac65 | 386 | an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR + |
87792efc S |
387 | sta->ht_cap.ampdu_factor); |
388 | an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density); | |
a59b5a5e | 389 | an->last_rssi = ATH_RSSI_DUMMY_MARKER; |
87792efc | 390 | } |
ff37e337 S |
391 | } |
392 | ||
393 | static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta) | |
394 | { | |
395 | struct ath_node *an = (struct ath_node *)sta->drv_priv; | |
396 | ||
397 | if (sc->sc_flags & SC_OP_TXAGGR) | |
398 | ath_tx_node_cleanup(sc, an); | |
399 | } | |
400 | ||
55624204 | 401 | void ath9k_tasklet(unsigned long data) |
ff37e337 S |
402 | { |
403 | struct ath_softc *sc = (struct ath_softc *)data; | |
af03abec | 404 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 405 | struct ath_common *common = ath9k_hw_common(ah); |
af03abec | 406 | |
17d7904d | 407 | u32 status = sc->intrstatus; |
b5c80475 | 408 | u32 rxmask; |
ff37e337 | 409 | |
153e080d VT |
410 | ath9k_ps_wakeup(sc); |
411 | ||
c9c99e5e FF |
412 | if ((status & ATH9K_INT_FATAL) || |
413 | !ath9k_hw_check_alive(ah)) { | |
ff37e337 | 414 | ath_reset(sc, false); |
153e080d | 415 | ath9k_ps_restore(sc); |
ff37e337 | 416 | return; |
063d8be3 | 417 | } |
ff37e337 | 418 | |
b5c80475 FF |
419 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) |
420 | rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL | | |
421 | ATH9K_INT_RXORN); | |
422 | else | |
423 | rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
424 | ||
425 | if (status & rxmask) { | |
063d8be3 | 426 | spin_lock_bh(&sc->rx.rxflushlock); |
b5c80475 FF |
427 | |
428 | /* Check for high priority Rx first */ | |
429 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) && | |
430 | (status & ATH9K_INT_RXHP)) | |
431 | ath_rx_tasklet(sc, 0, true); | |
432 | ||
433 | ath_rx_tasklet(sc, 0, false); | |
063d8be3 | 434 | spin_unlock_bh(&sc->rx.rxflushlock); |
ff37e337 S |
435 | } |
436 | ||
e5003249 VT |
437 | if (status & ATH9K_INT_TX) { |
438 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
439 | ath_tx_edma_tasklet(sc); | |
440 | else | |
441 | ath_tx_tasklet(sc); | |
442 | } | |
063d8be3 | 443 | |
96148326 | 444 | if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) { |
54ce846e JM |
445 | /* |
446 | * TSF sync does not look correct; remain awake to sync with | |
447 | * the next Beacon. | |
448 | */ | |
c46917bb LR |
449 | ath_print(common, ATH_DBG_PS, |
450 | "TSFOOR - Sync with next Beacon\n"); | |
1b04b930 | 451 | sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC; |
54ce846e JM |
452 | } |
453 | ||
766ec4a9 | 454 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
ebb8e1d7 VT |
455 | if (status & ATH9K_INT_GENTIMER) |
456 | ath_gen_timer_isr(sc->sc_ah); | |
457 | ||
ff37e337 | 458 | /* re-enable hardware interrupt */ |
3069168c | 459 | ath9k_hw_set_interrupts(ah, ah->imask); |
153e080d | 460 | ath9k_ps_restore(sc); |
ff37e337 S |
461 | } |
462 | ||
6baff7f9 | 463 | irqreturn_t ath_isr(int irq, void *dev) |
ff37e337 | 464 | { |
063d8be3 S |
465 | #define SCHED_INTR ( \ |
466 | ATH9K_INT_FATAL | \ | |
467 | ATH9K_INT_RXORN | \ | |
468 | ATH9K_INT_RXEOL | \ | |
469 | ATH9K_INT_RX | \ | |
b5c80475 FF |
470 | ATH9K_INT_RXLP | \ |
471 | ATH9K_INT_RXHP | \ | |
063d8be3 S |
472 | ATH9K_INT_TX | \ |
473 | ATH9K_INT_BMISS | \ | |
474 | ATH9K_INT_CST | \ | |
ebb8e1d7 VT |
475 | ATH9K_INT_TSFOOR | \ |
476 | ATH9K_INT_GENTIMER) | |
063d8be3 | 477 | |
ff37e337 | 478 | struct ath_softc *sc = dev; |
cbe61d8a | 479 | struct ath_hw *ah = sc->sc_ah; |
ff37e337 S |
480 | enum ath9k_int status; |
481 | bool sched = false; | |
482 | ||
063d8be3 S |
483 | /* |
484 | * The hardware is not ready/present, don't | |
485 | * touch anything. Note this can happen early | |
486 | * on if the IRQ is shared. | |
487 | */ | |
488 | if (sc->sc_flags & SC_OP_INVALID) | |
489 | return IRQ_NONE; | |
ff37e337 | 490 | |
063d8be3 S |
491 | |
492 | /* shared irq, not for us */ | |
493 | ||
153e080d | 494 | if (!ath9k_hw_intrpend(ah)) |
063d8be3 | 495 | return IRQ_NONE; |
063d8be3 S |
496 | |
497 | /* | |
498 | * Figure out the reason(s) for the interrupt. Note | |
499 | * that the hal returns a pseudo-ISR that may include | |
500 | * bits we haven't explicitly enabled so we mask the | |
501 | * value to insure we only process bits we requested. | |
502 | */ | |
503 | ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */ | |
3069168c | 504 | status &= ah->imask; /* discard unasked-for bits */ |
ff37e337 | 505 | |
063d8be3 S |
506 | /* |
507 | * If there are no status bits set, then this interrupt was not | |
508 | * for me (should have been caught above). | |
509 | */ | |
153e080d | 510 | if (!status) |
063d8be3 | 511 | return IRQ_NONE; |
ff37e337 | 512 | |
063d8be3 S |
513 | /* Cache the status */ |
514 | sc->intrstatus = status; | |
515 | ||
516 | if (status & SCHED_INTR) | |
517 | sched = true; | |
518 | ||
519 | /* | |
520 | * If a FATAL or RXORN interrupt is received, we have to reset the | |
521 | * chip immediately. | |
522 | */ | |
b5c80475 FF |
523 | if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) && |
524 | !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))) | |
063d8be3 S |
525 | goto chip_reset; |
526 | ||
527 | if (status & ATH9K_INT_SWBA) | |
528 | tasklet_schedule(&sc->bcon_tasklet); | |
529 | ||
530 | if (status & ATH9K_INT_TXURN) | |
531 | ath9k_hw_updatetxtriglevel(ah, true); | |
532 | ||
b5c80475 FF |
533 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { |
534 | if (status & ATH9K_INT_RXEOL) { | |
535 | ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN); | |
536 | ath9k_hw_set_interrupts(ah, ah->imask); | |
537 | } | |
538 | } | |
539 | ||
063d8be3 | 540 | if (status & ATH9K_INT_MIB) { |
ff37e337 | 541 | /* |
063d8be3 S |
542 | * Disable interrupts until we service the MIB |
543 | * interrupt; otherwise it will continue to | |
544 | * fire. | |
ff37e337 | 545 | */ |
063d8be3 S |
546 | ath9k_hw_set_interrupts(ah, 0); |
547 | /* | |
548 | * Let the hal handle the event. We assume | |
549 | * it will clear whatever condition caused | |
550 | * the interrupt. | |
551 | */ | |
22e66a4c | 552 | ath9k_hw_procmibevent(ah); |
3069168c | 553 | ath9k_hw_set_interrupts(ah, ah->imask); |
063d8be3 | 554 | } |
ff37e337 | 555 | |
153e080d VT |
556 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) |
557 | if (status & ATH9K_INT_TIM_TIMER) { | |
063d8be3 S |
558 | /* Clear RxAbort bit so that we can |
559 | * receive frames */ | |
9ecdef4b | 560 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
153e080d | 561 | ath9k_hw_setrxabort(sc->sc_ah, 0); |
1b04b930 | 562 | sc->ps_flags |= PS_WAIT_FOR_BEACON; |
ff37e337 | 563 | } |
063d8be3 S |
564 | |
565 | chip_reset: | |
ff37e337 | 566 | |
817e11de S |
567 | ath_debug_stat_interrupt(sc, status); |
568 | ||
ff37e337 S |
569 | if (sched) { |
570 | /* turn off every interrupt except SWBA */ | |
3069168c | 571 | ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA)); |
ff37e337 S |
572 | tasklet_schedule(&sc->intr_tq); |
573 | } | |
574 | ||
575 | return IRQ_HANDLED; | |
063d8be3 S |
576 | |
577 | #undef SCHED_INTR | |
ff37e337 S |
578 | } |
579 | ||
f078f209 | 580 | static u32 ath_get_extchanmode(struct ath_softc *sc, |
99405f93 | 581 | struct ieee80211_channel *chan, |
094d05dc | 582 | enum nl80211_channel_type channel_type) |
f078f209 LR |
583 | { |
584 | u32 chanmode = 0; | |
f078f209 LR |
585 | |
586 | switch (chan->band) { | |
587 | case IEEE80211_BAND_2GHZ: | |
094d05dc S |
588 | switch(channel_type) { |
589 | case NL80211_CHAN_NO_HT: | |
590 | case NL80211_CHAN_HT20: | |
f078f209 | 591 | chanmode = CHANNEL_G_HT20; |
094d05dc S |
592 | break; |
593 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 594 | chanmode = CHANNEL_G_HT40PLUS; |
094d05dc S |
595 | break; |
596 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 597 | chanmode = CHANNEL_G_HT40MINUS; |
094d05dc S |
598 | break; |
599 | } | |
f078f209 LR |
600 | break; |
601 | case IEEE80211_BAND_5GHZ: | |
094d05dc S |
602 | switch(channel_type) { |
603 | case NL80211_CHAN_NO_HT: | |
604 | case NL80211_CHAN_HT20: | |
f078f209 | 605 | chanmode = CHANNEL_A_HT20; |
094d05dc S |
606 | break; |
607 | case NL80211_CHAN_HT40PLUS: | |
f078f209 | 608 | chanmode = CHANNEL_A_HT40PLUS; |
094d05dc S |
609 | break; |
610 | case NL80211_CHAN_HT40MINUS: | |
f078f209 | 611 | chanmode = CHANNEL_A_HT40MINUS; |
094d05dc S |
612 | break; |
613 | } | |
f078f209 LR |
614 | break; |
615 | default: | |
616 | break; | |
617 | } | |
618 | ||
619 | return chanmode; | |
620 | } | |
621 | ||
7e86c104 | 622 | static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key, |
3f53dd64 JM |
623 | struct ath9k_keyval *hk, const u8 *addr, |
624 | bool authenticator) | |
f078f209 | 625 | { |
7e86c104 | 626 | struct ath_hw *ah = common->ah; |
6ace2891 JM |
627 | const u8 *key_rxmic; |
628 | const u8 *key_txmic; | |
f078f209 | 629 | |
6ace2891 JM |
630 | key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY; |
631 | key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY; | |
f078f209 LR |
632 | |
633 | if (addr == NULL) { | |
d216aaa6 JM |
634 | /* |
635 | * Group key installation - only two key cache entries are used | |
636 | * regardless of splitmic capability since group key is only | |
637 | * used either for TX or RX. | |
638 | */ | |
3f53dd64 JM |
639 | if (authenticator) { |
640 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); | |
641 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic)); | |
642 | } else { | |
643 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
644 | memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic)); | |
645 | } | |
7e86c104 | 646 | return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr); |
f078f209 | 647 | } |
7e86c104 | 648 | if (!common->splitmic) { |
d216aaa6 | 649 | /* TX and RX keys share the same key cache entry. */ |
f078f209 LR |
650 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); |
651 | memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic)); | |
7e86c104 | 652 | return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr); |
f078f209 | 653 | } |
d216aaa6 JM |
654 | |
655 | /* Separate key cache entries for TX and RX */ | |
656 | ||
657 | /* TX key goes at first index, RX key at +32. */ | |
f078f209 | 658 | memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); |
7e86c104 | 659 | if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) { |
d216aaa6 | 660 | /* TX MIC entry failed. No need to proceed further */ |
7e86c104 | 661 | ath_print(common, ATH_DBG_FATAL, |
c46917bb | 662 | "Setting TX MIC Key Failed\n"); |
f078f209 LR |
663 | return 0; |
664 | } | |
665 | ||
666 | memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic)); | |
667 | /* XXX delete tx key on failure? */ | |
7e86c104 | 668 | return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr); |
6ace2891 JM |
669 | } |
670 | ||
7e86c104 | 671 | static int ath_reserve_key_cache_slot_tkip(struct ath_common *common) |
6ace2891 JM |
672 | { |
673 | int i; | |
674 | ||
7e86c104 LR |
675 | for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) { |
676 | if (test_bit(i, common->keymap) || | |
677 | test_bit(i + 64, common->keymap)) | |
6ace2891 | 678 | continue; /* At least one part of TKIP key allocated */ |
7e86c104 LR |
679 | if (common->splitmic && |
680 | (test_bit(i + 32, common->keymap) || | |
681 | test_bit(i + 64 + 32, common->keymap))) | |
6ace2891 JM |
682 | continue; /* At least one part of TKIP key allocated */ |
683 | ||
684 | /* Found a free slot for a TKIP key */ | |
685 | return i; | |
686 | } | |
687 | return -1; | |
688 | } | |
689 | ||
7e86c104 | 690 | static int ath_reserve_key_cache_slot(struct ath_common *common) |
6ace2891 JM |
691 | { |
692 | int i; | |
693 | ||
694 | /* First, try to find slots that would not be available for TKIP. */ | |
7e86c104 LR |
695 | if (common->splitmic) { |
696 | for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) { | |
697 | if (!test_bit(i, common->keymap) && | |
698 | (test_bit(i + 32, common->keymap) || | |
699 | test_bit(i + 64, common->keymap) || | |
700 | test_bit(i + 64 + 32, common->keymap))) | |
6ace2891 | 701 | return i; |
7e86c104 LR |
702 | if (!test_bit(i + 32, common->keymap) && |
703 | (test_bit(i, common->keymap) || | |
704 | test_bit(i + 64, common->keymap) || | |
705 | test_bit(i + 64 + 32, common->keymap))) | |
6ace2891 | 706 | return i + 32; |
7e86c104 LR |
707 | if (!test_bit(i + 64, common->keymap) && |
708 | (test_bit(i , common->keymap) || | |
709 | test_bit(i + 32, common->keymap) || | |
710 | test_bit(i + 64 + 32, common->keymap))) | |
ea612132 | 711 | return i + 64; |
7e86c104 LR |
712 | if (!test_bit(i + 64 + 32, common->keymap) && |
713 | (test_bit(i, common->keymap) || | |
714 | test_bit(i + 32, common->keymap) || | |
715 | test_bit(i + 64, common->keymap))) | |
ea612132 | 716 | return i + 64 + 32; |
6ace2891 JM |
717 | } |
718 | } else { | |
7e86c104 LR |
719 | for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) { |
720 | if (!test_bit(i, common->keymap) && | |
721 | test_bit(i + 64, common->keymap)) | |
6ace2891 | 722 | return i; |
7e86c104 LR |
723 | if (test_bit(i, common->keymap) && |
724 | !test_bit(i + 64, common->keymap)) | |
6ace2891 JM |
725 | return i + 64; |
726 | } | |
727 | } | |
728 | ||
729 | /* No partially used TKIP slots, pick any available slot */ | |
7e86c104 | 730 | for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) { |
be2864cf JM |
731 | /* Do not allow slots that could be needed for TKIP group keys |
732 | * to be used. This limitation could be removed if we know that | |
733 | * TKIP will not be used. */ | |
734 | if (i >= 64 && i < 64 + IEEE80211_WEP_NKID) | |
735 | continue; | |
7e86c104 | 736 | if (common->splitmic) { |
be2864cf JM |
737 | if (i >= 32 && i < 32 + IEEE80211_WEP_NKID) |
738 | continue; | |
739 | if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID) | |
740 | continue; | |
741 | } | |
742 | ||
7e86c104 | 743 | if (!test_bit(i, common->keymap)) |
6ace2891 JM |
744 | return i; /* Found a free slot for a key */ |
745 | } | |
746 | ||
747 | /* No free slot found */ | |
748 | return -1; | |
f078f209 LR |
749 | } |
750 | ||
7e86c104 | 751 | static int ath_key_config(struct ath_common *common, |
3f53dd64 | 752 | struct ieee80211_vif *vif, |
dc822b5d | 753 | struct ieee80211_sta *sta, |
f078f209 LR |
754 | struct ieee80211_key_conf *key) |
755 | { | |
7e86c104 | 756 | struct ath_hw *ah = common->ah; |
f078f209 LR |
757 | struct ath9k_keyval hk; |
758 | const u8 *mac = NULL; | |
759 | int ret = 0; | |
6ace2891 | 760 | int idx; |
f078f209 LR |
761 | |
762 | memset(&hk, 0, sizeof(hk)); | |
763 | ||
764 | switch (key->alg) { | |
765 | case ALG_WEP: | |
766 | hk.kv_type = ATH9K_CIPHER_WEP; | |
767 | break; | |
768 | case ALG_TKIP: | |
769 | hk.kv_type = ATH9K_CIPHER_TKIP; | |
770 | break; | |
771 | case ALG_CCMP: | |
772 | hk.kv_type = ATH9K_CIPHER_AES_CCM; | |
773 | break; | |
774 | default: | |
ca470b29 | 775 | return -EOPNOTSUPP; |
f078f209 LR |
776 | } |
777 | ||
6ace2891 | 778 | hk.kv_len = key->keylen; |
f078f209 LR |
779 | memcpy(hk.kv_val, key->key, key->keylen); |
780 | ||
6ace2891 | 781 | if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { |
3dc3fc52 JL |
782 | /* For now, use the default keys for broadcast keys. This may |
783 | * need to change with virtual interfaces. */ | |
784 | idx = key->keyidx; | |
6ace2891 | 785 | } else if (key->keyidx) { |
dc822b5d JB |
786 | if (WARN_ON(!sta)) |
787 | return -EOPNOTSUPP; | |
788 | mac = sta->addr; | |
789 | ||
6ace2891 JM |
790 | if (vif->type != NL80211_IFTYPE_AP) { |
791 | /* Only keyidx 0 should be used with unicast key, but | |
792 | * allow this for client mode for now. */ | |
793 | idx = key->keyidx; | |
794 | } else | |
795 | return -EIO; | |
f078f209 | 796 | } else { |
dc822b5d JB |
797 | if (WARN_ON(!sta)) |
798 | return -EOPNOTSUPP; | |
799 | mac = sta->addr; | |
800 | ||
6ace2891 | 801 | if (key->alg == ALG_TKIP) |
7e86c104 | 802 | idx = ath_reserve_key_cache_slot_tkip(common); |
6ace2891 | 803 | else |
7e86c104 | 804 | idx = ath_reserve_key_cache_slot(common); |
6ace2891 | 805 | if (idx < 0) |
ca470b29 | 806 | return -ENOSPC; /* no free key cache entries */ |
f078f209 LR |
807 | } |
808 | ||
809 | if (key->alg == ALG_TKIP) | |
7e86c104 | 810 | ret = ath_setkey_tkip(common, idx, key->key, &hk, mac, |
3f53dd64 | 811 | vif->type == NL80211_IFTYPE_AP); |
f078f209 | 812 | else |
7e86c104 | 813 | ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac); |
f078f209 LR |
814 | |
815 | if (!ret) | |
816 | return -EIO; | |
817 | ||
7e86c104 | 818 | set_bit(idx, common->keymap); |
6ace2891 | 819 | if (key->alg == ALG_TKIP) { |
7e86c104 LR |
820 | set_bit(idx + 64, common->keymap); |
821 | if (common->splitmic) { | |
822 | set_bit(idx + 32, common->keymap); | |
823 | set_bit(idx + 64 + 32, common->keymap); | |
6ace2891 JM |
824 | } |
825 | } | |
826 | ||
827 | return idx; | |
f078f209 LR |
828 | } |
829 | ||
7e86c104 | 830 | static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key) |
f078f209 | 831 | { |
7e86c104 LR |
832 | struct ath_hw *ah = common->ah; |
833 | ||
834 | ath9k_hw_keyreset(ah, key->hw_key_idx); | |
6ace2891 JM |
835 | if (key->hw_key_idx < IEEE80211_WEP_NKID) |
836 | return; | |
837 | ||
7e86c104 | 838 | clear_bit(key->hw_key_idx, common->keymap); |
6ace2891 JM |
839 | if (key->alg != ALG_TKIP) |
840 | return; | |
f078f209 | 841 | |
7e86c104 LR |
842 | clear_bit(key->hw_key_idx + 64, common->keymap); |
843 | if (common->splitmic) { | |
733da37d | 844 | ath9k_hw_keyreset(ah, key->hw_key_idx + 32); |
7e86c104 LR |
845 | clear_bit(key->hw_key_idx + 32, common->keymap); |
846 | clear_bit(key->hw_key_idx + 64 + 32, common->keymap); | |
6ace2891 | 847 | } |
f078f209 LR |
848 | } |
849 | ||
8feceb67 | 850 | static void ath9k_bss_assoc_info(struct ath_softc *sc, |
5640b08e | 851 | struct ieee80211_vif *vif, |
8feceb67 | 852 | struct ieee80211_bss_conf *bss_conf) |
f078f209 | 853 | { |
f2b2143e | 854 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 855 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 856 | |
8feceb67 | 857 | if (bss_conf->assoc) { |
c46917bb LR |
858 | ath_print(common, ATH_DBG_CONFIG, |
859 | "Bss Info ASSOC %d, bssid: %pM\n", | |
860 | bss_conf->aid, common->curbssid); | |
f078f209 | 861 | |
8feceb67 | 862 | /* New association, store aid */ |
1510718d | 863 | common->curaid = bss_conf->aid; |
f2b2143e | 864 | ath9k_hw_write_associd(ah); |
2664f201 SB |
865 | |
866 | /* | |
867 | * Request a re-configuration of Beacon related timers | |
868 | * on the receipt of the first Beacon frame (i.e., | |
869 | * after time sync with the AP). | |
870 | */ | |
1b04b930 | 871 | sc->ps_flags |= PS_BEACON_SYNC; |
f078f209 | 872 | |
8feceb67 | 873 | /* Configure the beacon */ |
2c3db3d5 | 874 | ath_beacon_config(sc, vif); |
f078f209 | 875 | |
8feceb67 | 876 | /* Reset rssi stats */ |
22e66a4c | 877 | sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER; |
f078f209 | 878 | |
6c3118e2 | 879 | sc->sc_flags |= SC_OP_ANI_RUN; |
3d536acf | 880 | ath_start_ani(common); |
8feceb67 | 881 | } else { |
c46917bb | 882 | ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); |
1510718d | 883 | common->curaid = 0; |
f38faa31 | 884 | /* Stop ANI */ |
6c3118e2 | 885 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 886 | del_timer_sync(&common->ani.timer); |
f078f209 | 887 | } |
8feceb67 | 888 | } |
f078f209 | 889 | |
68a89116 | 890 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 891 | { |
cbe61d8a | 892 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 893 | struct ath_common *common = ath9k_hw_common(ah); |
68a89116 | 894 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 895 | int r; |
500c064d | 896 | |
3cbb5dd7 | 897 | ath9k_ps_wakeup(sc); |
93b1b37f | 898 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ae8d2858 | 899 | |
159cd468 VT |
900 | if (!ah->curchan) |
901 | ah->curchan = ath_get_curchannel(sc, sc->hw); | |
902 | ||
d2f5b3a6 | 903 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 904 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 905 | if (r) { |
c46917bb | 906 | ath_print(common, ATH_DBG_FATAL, |
f643e51d | 907 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
908 | "reset status %d\n", |
909 | channel->center_freq, r); | |
500c064d VT |
910 | } |
911 | spin_unlock_bh(&sc->sc_resetlock); | |
912 | ||
913 | ath_update_txpow(sc); | |
914 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
915 | ath_print(common, ATH_DBG_FATAL, |
916 | "Unable to restart recv logic\n"); | |
500c064d VT |
917 | return; |
918 | } | |
919 | ||
920 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 921 | ath_beacon_config(sc, NULL); /* restart beacons */ |
500c064d VT |
922 | |
923 | /* Re-Enable interrupts */ | |
3069168c | 924 | ath9k_hw_set_interrupts(ah, ah->imask); |
500c064d VT |
925 | |
926 | /* Enable LED */ | |
08fc5c1b | 927 | ath9k_hw_cfg_output(ah, ah->led_pin, |
500c064d | 928 | AR_GPIO_OUTPUT_MUX_AS_OUTPUT); |
08fc5c1b | 929 | ath9k_hw_set_gpio(ah, ah->led_pin, 0); |
500c064d | 930 | |
68a89116 | 931 | ieee80211_wake_queues(hw); |
3cbb5dd7 | 932 | ath9k_ps_restore(sc); |
500c064d VT |
933 | } |
934 | ||
68a89116 | 935 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw) |
500c064d | 936 | { |
cbe61d8a | 937 | struct ath_hw *ah = sc->sc_ah; |
68a89116 | 938 | struct ieee80211_channel *channel = hw->conf.channel; |
ae8d2858 | 939 | int r; |
500c064d | 940 | |
3cbb5dd7 | 941 | ath9k_ps_wakeup(sc); |
68a89116 | 942 | ieee80211_stop_queues(hw); |
500c064d VT |
943 | |
944 | /* Disable LED */ | |
08fc5c1b VN |
945 | ath9k_hw_set_gpio(ah, ah->led_pin, 1); |
946 | ath9k_hw_cfg_gpio_input(ah, ah->led_pin); | |
500c064d VT |
947 | |
948 | /* Disable interrupts */ | |
949 | ath9k_hw_set_interrupts(ah, 0); | |
950 | ||
043a0405 | 951 | ath_drain_all_txq(sc, false); /* clear pending tx frames */ |
500c064d VT |
952 | ath_stoprecv(sc); /* turn off frame recv */ |
953 | ath_flushrecv(sc); /* flush recv queue */ | |
954 | ||
159cd468 | 955 | if (!ah->curchan) |
68a89116 | 956 | ah->curchan = ath_get_curchannel(sc, hw); |
159cd468 | 957 | |
500c064d | 958 | spin_lock_bh(&sc->sc_resetlock); |
2660b81a | 959 | r = ath9k_hw_reset(ah, ah->curchan, false); |
ae8d2858 | 960 | if (r) { |
c46917bb | 961 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
f643e51d | 962 | "Unable to reset channel (%u MHz), " |
c46917bb LR |
963 | "reset status %d\n", |
964 | channel->center_freq, r); | |
500c064d VT |
965 | } |
966 | spin_unlock_bh(&sc->sc_resetlock); | |
967 | ||
968 | ath9k_hw_phy_disable(ah); | |
93b1b37f | 969 | ath9k_hw_configpcipowersave(ah, 1, 1); |
3cbb5dd7 | 970 | ath9k_ps_restore(sc); |
9ecdef4b | 971 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
500c064d VT |
972 | } |
973 | ||
ff37e337 S |
974 | int ath_reset(struct ath_softc *sc, bool retry_tx) |
975 | { | |
cbe61d8a | 976 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 977 | struct ath_common *common = ath9k_hw_common(ah); |
030bb495 | 978 | struct ieee80211_hw *hw = sc->hw; |
ae8d2858 | 979 | int r; |
ff37e337 | 980 | |
2ab81d4a S |
981 | /* Stop ANI */ |
982 | del_timer_sync(&common->ani.timer); | |
983 | ||
cc9c378a S |
984 | ieee80211_stop_queues(hw); |
985 | ||
ff37e337 | 986 | ath9k_hw_set_interrupts(ah, 0); |
043a0405 | 987 | ath_drain_all_txq(sc, retry_tx); |
ff37e337 S |
988 | ath_stoprecv(sc); |
989 | ath_flushrecv(sc); | |
990 | ||
991 | spin_lock_bh(&sc->sc_resetlock); | |
2660b81a | 992 | r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); |
ae8d2858 | 993 | if (r) |
c46917bb LR |
994 | ath_print(common, ATH_DBG_FATAL, |
995 | "Unable to reset hardware; reset status %d\n", r); | |
ff37e337 S |
996 | spin_unlock_bh(&sc->sc_resetlock); |
997 | ||
998 | if (ath_startrecv(sc) != 0) | |
c46917bb LR |
999 | ath_print(common, ATH_DBG_FATAL, |
1000 | "Unable to start recv logic\n"); | |
ff37e337 S |
1001 | |
1002 | /* | |
1003 | * We may be doing a reset in response to a request | |
1004 | * that changes the channel so update any state that | |
1005 | * might change as a result. | |
1006 | */ | |
ce111bad | 1007 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1008 | |
1009 | ath_update_txpow(sc); | |
1010 | ||
1011 | if (sc->sc_flags & SC_OP_BEACONS) | |
2c3db3d5 | 1012 | ath_beacon_config(sc, NULL); /* restart beacons */ |
ff37e337 | 1013 | |
3069168c | 1014 | ath9k_hw_set_interrupts(ah, ah->imask); |
ff37e337 S |
1015 | |
1016 | if (retry_tx) { | |
1017 | int i; | |
1018 | for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { | |
1019 | if (ATH_TXQ_SETUP(sc, i)) { | |
b77f483f S |
1020 | spin_lock_bh(&sc->tx.txq[i].axq_lock); |
1021 | ath_txq_schedule(sc, &sc->tx.txq[i]); | |
1022 | spin_unlock_bh(&sc->tx.txq[i].axq_lock); | |
ff37e337 S |
1023 | } |
1024 | } | |
1025 | } | |
1026 | ||
cc9c378a S |
1027 | ieee80211_wake_queues(hw); |
1028 | ||
2ab81d4a S |
1029 | /* Start ANI */ |
1030 | ath_start_ani(common); | |
1031 | ||
ae8d2858 | 1032 | return r; |
ff37e337 S |
1033 | } |
1034 | ||
ff37e337 S |
1035 | int ath_get_hal_qnum(u16 queue, struct ath_softc *sc) |
1036 | { | |
1037 | int qnum; | |
1038 | ||
1039 | switch (queue) { | |
1040 | case 0: | |
b77f483f | 1041 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO]; |
ff37e337 S |
1042 | break; |
1043 | case 1: | |
b77f483f | 1044 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI]; |
ff37e337 S |
1045 | break; |
1046 | case 2: | |
b77f483f | 1047 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
1048 | break; |
1049 | case 3: | |
b77f483f | 1050 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK]; |
ff37e337 S |
1051 | break; |
1052 | default: | |
b77f483f | 1053 | qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE]; |
ff37e337 S |
1054 | break; |
1055 | } | |
1056 | ||
1057 | return qnum; | |
1058 | } | |
1059 | ||
1060 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc) | |
1061 | { | |
1062 | int qnum; | |
1063 | ||
1064 | switch (queue) { | |
1065 | case ATH9K_WME_AC_VO: | |
1066 | qnum = 0; | |
1067 | break; | |
1068 | case ATH9K_WME_AC_VI: | |
1069 | qnum = 1; | |
1070 | break; | |
1071 | case ATH9K_WME_AC_BE: | |
1072 | qnum = 2; | |
1073 | break; | |
1074 | case ATH9K_WME_AC_BK: | |
1075 | qnum = 3; | |
1076 | break; | |
1077 | default: | |
1078 | qnum = -1; | |
1079 | break; | |
1080 | } | |
1081 | ||
1082 | return qnum; | |
1083 | } | |
1084 | ||
5f8e077c LR |
1085 | /* XXX: Remove me once we don't depend on ath9k_channel for all |
1086 | * this redundant data */ | |
0e2dedf9 JM |
1087 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
1088 | struct ath9k_channel *ichan) | |
5f8e077c | 1089 | { |
5f8e077c LR |
1090 | struct ieee80211_channel *chan = hw->conf.channel; |
1091 | struct ieee80211_conf *conf = &hw->conf; | |
1092 | ||
1093 | ichan->channel = chan->center_freq; | |
1094 | ichan->chan = chan; | |
1095 | ||
1096 | if (chan->band == IEEE80211_BAND_2GHZ) { | |
1097 | ichan->chanmode = CHANNEL_G; | |
8813262e | 1098 | ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G; |
5f8e077c LR |
1099 | } else { |
1100 | ichan->chanmode = CHANNEL_A; | |
1101 | ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM; | |
1102 | } | |
1103 | ||
25c56eec | 1104 | if (conf_is_ht(conf)) |
5f8e077c LR |
1105 | ichan->chanmode = ath_get_extchanmode(sc, chan, |
1106 | conf->channel_type); | |
5f8e077c LR |
1107 | } |
1108 | ||
ff37e337 S |
1109 | /**********************/ |
1110 | /* mac80211 callbacks */ | |
1111 | /**********************/ | |
1112 | ||
8feceb67 | 1113 | static int ath9k_start(struct ieee80211_hw *hw) |
f078f209 | 1114 | { |
bce048d7 JM |
1115 | struct ath_wiphy *aphy = hw->priv; |
1116 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1117 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1118 | struct ath_common *common = ath9k_hw_common(ah); |
8feceb67 | 1119 | struct ieee80211_channel *curchan = hw->conf.channel; |
ff37e337 | 1120 | struct ath9k_channel *init_channel; |
82880a7c | 1121 | int r; |
f078f209 | 1122 | |
c46917bb LR |
1123 | ath_print(common, ATH_DBG_CONFIG, |
1124 | "Starting driver with initial channel: %d MHz\n", | |
1125 | curchan->center_freq); | |
f078f209 | 1126 | |
141b38b6 S |
1127 | mutex_lock(&sc->mutex); |
1128 | ||
9580a222 JM |
1129 | if (ath9k_wiphy_started(sc)) { |
1130 | if (sc->chan_idx == curchan->hw_value) { | |
1131 | /* | |
1132 | * Already on the operational channel, the new wiphy | |
1133 | * can be marked active. | |
1134 | */ | |
1135 | aphy->state = ATH_WIPHY_ACTIVE; | |
1136 | ieee80211_wake_queues(hw); | |
1137 | } else { | |
1138 | /* | |
1139 | * Another wiphy is on another channel, start the new | |
1140 | * wiphy in paused state. | |
1141 | */ | |
1142 | aphy->state = ATH_WIPHY_PAUSED; | |
1143 | ieee80211_stop_queues(hw); | |
1144 | } | |
1145 | mutex_unlock(&sc->mutex); | |
1146 | return 0; | |
1147 | } | |
1148 | aphy->state = ATH_WIPHY_ACTIVE; | |
1149 | ||
8feceb67 | 1150 | /* setup initial channel */ |
f078f209 | 1151 | |
82880a7c | 1152 | sc->chan_idx = curchan->hw_value; |
f078f209 | 1153 | |
82880a7c | 1154 | init_channel = ath_get_curchannel(sc, hw); |
ff37e337 S |
1155 | |
1156 | /* Reset SERDES registers */ | |
af03abec | 1157 | ath9k_hw_configpcipowersave(ah, 0, 0); |
ff37e337 S |
1158 | |
1159 | /* | |
1160 | * The basic interface to setting the hardware in a good | |
1161 | * state is ``reset''. On return the hardware is known to | |
1162 | * be powered up and with interrupts disabled. This must | |
1163 | * be followed by initialization of the appropriate bits | |
1164 | * and then setup of the interrupt mask. | |
1165 | */ | |
1166 | spin_lock_bh(&sc->sc_resetlock); | |
af03abec | 1167 | r = ath9k_hw_reset(ah, init_channel, false); |
ae8d2858 | 1168 | if (r) { |
c46917bb LR |
1169 | ath_print(common, ATH_DBG_FATAL, |
1170 | "Unable to reset hardware; reset status %d " | |
1171 | "(freq %u MHz)\n", r, | |
1172 | curchan->center_freq); | |
ff37e337 | 1173 | spin_unlock_bh(&sc->sc_resetlock); |
141b38b6 | 1174 | goto mutex_unlock; |
ff37e337 S |
1175 | } |
1176 | spin_unlock_bh(&sc->sc_resetlock); | |
1177 | ||
1178 | /* | |
1179 | * This is needed only to setup initial state | |
1180 | * but it's best done after a reset. | |
1181 | */ | |
1182 | ath_update_txpow(sc); | |
8feceb67 | 1183 | |
ff37e337 S |
1184 | /* |
1185 | * Setup the hardware after reset: | |
1186 | * The receive engine is set going. | |
1187 | * Frame transmit is handled entirely | |
1188 | * in the frame output path; there's nothing to do | |
1189 | * here except setup the interrupt mask. | |
1190 | */ | |
1191 | if (ath_startrecv(sc) != 0) { | |
c46917bb LR |
1192 | ath_print(common, ATH_DBG_FATAL, |
1193 | "Unable to start recv logic\n"); | |
141b38b6 S |
1194 | r = -EIO; |
1195 | goto mutex_unlock; | |
f078f209 | 1196 | } |
8feceb67 | 1197 | |
ff37e337 | 1198 | /* Setup our intr mask. */ |
b5c80475 FF |
1199 | ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL | |
1200 | ATH9K_INT_RXORN | ATH9K_INT_FATAL | | |
1201 | ATH9K_INT_GLOBAL; | |
1202 | ||
1203 | if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) | |
1204 | ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP; | |
1205 | else | |
1206 | ah->imask |= ATH9K_INT_RX; | |
ff37e337 | 1207 | |
af03abec | 1208 | if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT) |
3069168c | 1209 | ah->imask |= ATH9K_INT_GTT; |
ff37e337 | 1210 | |
af03abec | 1211 | if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) |
3069168c | 1212 | ah->imask |= ATH9K_INT_CST; |
ff37e337 | 1213 | |
ce111bad | 1214 | ath_cache_conf_rate(sc, &hw->conf); |
ff37e337 S |
1215 | |
1216 | sc->sc_flags &= ~SC_OP_INVALID; | |
1217 | ||
1218 | /* Disable BMISS interrupt when we're not associated */ | |
3069168c PR |
1219 | ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS); |
1220 | ath9k_hw_set_interrupts(ah, ah->imask); | |
ff37e337 | 1221 | |
bce048d7 | 1222 | ieee80211_wake_queues(hw); |
ff37e337 | 1223 | |
42935eca | 1224 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
164ace38 | 1225 | |
766ec4a9 LR |
1226 | if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) && |
1227 | !ah->btcoex_hw.enabled) { | |
5e197292 LR |
1228 | ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT, |
1229 | AR_STOMP_LOW_WLAN_WGHT); | |
af03abec | 1230 | ath9k_hw_btcoex_enable(ah); |
f985ad12 | 1231 | |
5bb12791 LR |
1232 | if (common->bus_ops->bt_coex_prep) |
1233 | common->bus_ops->bt_coex_prep(common); | |
766ec4a9 | 1234 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1235 | ath9k_btcoex_timer_resume(sc); |
1773912b VT |
1236 | } |
1237 | ||
141b38b6 S |
1238 | mutex_unlock: |
1239 | mutex_unlock(&sc->mutex); | |
1240 | ||
ae8d2858 | 1241 | return r; |
f078f209 LR |
1242 | } |
1243 | ||
8feceb67 VT |
1244 | static int ath9k_tx(struct ieee80211_hw *hw, |
1245 | struct sk_buff *skb) | |
f078f209 | 1246 | { |
528f0c6b | 1247 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
bce048d7 JM |
1248 | struct ath_wiphy *aphy = hw->priv; |
1249 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1250 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
528f0c6b | 1251 | struct ath_tx_control txctl; |
1bc14880 BP |
1252 | int padpos, padsize; |
1253 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data; | |
528f0c6b | 1254 | |
8089cc47 | 1255 | if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) { |
c46917bb LR |
1256 | ath_print(common, ATH_DBG_XMIT, |
1257 | "ath9k: %s: TX in unexpected wiphy state " | |
1258 | "%d\n", wiphy_name(hw->wiphy), aphy->state); | |
ee166a0e JM |
1259 | goto exit; |
1260 | } | |
1261 | ||
96148326 | 1262 | if (sc->ps_enabled) { |
dc8c4585 JM |
1263 | /* |
1264 | * mac80211 does not set PM field for normal data frames, so we | |
1265 | * need to update that based on the current PS mode. | |
1266 | */ | |
1267 | if (ieee80211_is_data(hdr->frame_control) && | |
1268 | !ieee80211_is_nullfunc(hdr->frame_control) && | |
1269 | !ieee80211_has_pm(hdr->frame_control)) { | |
c46917bb LR |
1270 | ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame " |
1271 | "while in PS mode\n"); | |
dc8c4585 JM |
1272 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); |
1273 | } | |
1274 | } | |
1275 | ||
9a23f9ca JM |
1276 | if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) { |
1277 | /* | |
1278 | * We are using PS-Poll and mac80211 can request TX while in | |
1279 | * power save mode. Need to wake up hardware for the TX to be | |
1280 | * completed and if needed, also for RX of buffered frames. | |
1281 | */ | |
9a23f9ca JM |
1282 | ath9k_ps_wakeup(sc); |
1283 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1284 | if (ieee80211_is_pspoll(hdr->frame_control)) { | |
c46917bb LR |
1285 | ath_print(common, ATH_DBG_PS, |
1286 | "Sending PS-Poll to pick a buffered frame\n"); | |
1b04b930 | 1287 | sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA; |
9a23f9ca | 1288 | } else { |
c46917bb LR |
1289 | ath_print(common, ATH_DBG_PS, |
1290 | "Wake up to complete TX\n"); | |
1b04b930 | 1291 | sc->ps_flags |= PS_WAIT_FOR_TX_ACK; |
9a23f9ca JM |
1292 | } |
1293 | /* | |
1294 | * The actual restore operation will happen only after | |
1295 | * the sc_flags bit is cleared. We are just dropping | |
1296 | * the ps_usecount here. | |
1297 | */ | |
1298 | ath9k_ps_restore(sc); | |
1299 | } | |
1300 | ||
528f0c6b | 1301 | memset(&txctl, 0, sizeof(struct ath_tx_control)); |
f078f209 | 1302 | |
8feceb67 VT |
1303 | /* |
1304 | * As a temporary workaround, assign seq# here; this will likely need | |
1305 | * to be cleaned up to work better with Beacon transmission and virtual | |
1306 | * BSSes. | |
1307 | */ | |
1308 | if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) { | |
8feceb67 | 1309 | if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT) |
b77f483f | 1310 | sc->tx.seq_no += 0x10; |
8feceb67 | 1311 | hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG); |
b77f483f | 1312 | hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no); |
8feceb67 | 1313 | } |
f078f209 | 1314 | |
8feceb67 | 1315 | /* Add the padding after the header if this is not already done */ |
1bc14880 BP |
1316 | padpos = ath9k_cmn_padpos(hdr->frame_control); |
1317 | padsize = padpos & 3; | |
1318 | if (padsize && skb->len>padpos) { | |
8feceb67 VT |
1319 | if (skb_headroom(skb) < padsize) |
1320 | return -1; | |
1321 | skb_push(skb, padsize); | |
1bc14880 | 1322 | memmove(skb->data, skb->data + padsize, padpos); |
8feceb67 VT |
1323 | } |
1324 | ||
528f0c6b S |
1325 | /* Check if a tx queue is available */ |
1326 | ||
1327 | txctl.txq = ath_test_get_txq(sc, skb); | |
1328 | if (!txctl.txq) | |
1329 | goto exit; | |
1330 | ||
c46917bb | 1331 | ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); |
8feceb67 | 1332 | |
c52f33d0 | 1333 | if (ath_tx_start(hw, skb, &txctl) != 0) { |
c46917bb | 1334 | ath_print(common, ATH_DBG_XMIT, "TX failed\n"); |
528f0c6b | 1335 | goto exit; |
8feceb67 VT |
1336 | } |
1337 | ||
528f0c6b S |
1338 | return 0; |
1339 | exit: | |
1340 | dev_kfree_skb_any(skb); | |
8feceb67 | 1341 | return 0; |
f078f209 LR |
1342 | } |
1343 | ||
8feceb67 | 1344 | static void ath9k_stop(struct ieee80211_hw *hw) |
f078f209 | 1345 | { |
bce048d7 JM |
1346 | struct ath_wiphy *aphy = hw->priv; |
1347 | struct ath_softc *sc = aphy->sc; | |
af03abec | 1348 | struct ath_hw *ah = sc->sc_ah; |
c46917bb | 1349 | struct ath_common *common = ath9k_hw_common(ah); |
f078f209 | 1350 | |
4c483817 S |
1351 | mutex_lock(&sc->mutex); |
1352 | ||
9580a222 JM |
1353 | aphy->state = ATH_WIPHY_INACTIVE; |
1354 | ||
c94dbff7 LR |
1355 | cancel_delayed_work_sync(&sc->ath_led_blink_work); |
1356 | cancel_delayed_work_sync(&sc->tx_complete_work); | |
1357 | ||
1358 | if (!sc->num_sec_wiphy) { | |
1359 | cancel_delayed_work_sync(&sc->wiphy_work); | |
1360 | cancel_work_sync(&sc->chan_work); | |
1361 | } | |
1362 | ||
9c84b797 | 1363 | if (sc->sc_flags & SC_OP_INVALID) { |
c46917bb | 1364 | ath_print(common, ATH_DBG_ANY, "Device not present\n"); |
4c483817 | 1365 | mutex_unlock(&sc->mutex); |
9c84b797 S |
1366 | return; |
1367 | } | |
8feceb67 | 1368 | |
9580a222 JM |
1369 | if (ath9k_wiphy_started(sc)) { |
1370 | mutex_unlock(&sc->mutex); | |
1371 | return; /* another wiphy still in use */ | |
1372 | } | |
1373 | ||
3867cf6a S |
1374 | /* Ensure HW is awake when we try to shut it down. */ |
1375 | ath9k_ps_wakeup(sc); | |
1376 | ||
766ec4a9 | 1377 | if (ah->btcoex_hw.enabled) { |
af03abec | 1378 | ath9k_hw_btcoex_disable(ah); |
766ec4a9 | 1379 | if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE) |
75d7839f | 1380 | ath9k_btcoex_timer_pause(sc); |
1773912b VT |
1381 | } |
1382 | ||
ff37e337 S |
1383 | /* make sure h/w will not generate any interrupt |
1384 | * before setting the invalid flag. */ | |
af03abec | 1385 | ath9k_hw_set_interrupts(ah, 0); |
ff37e337 S |
1386 | |
1387 | if (!(sc->sc_flags & SC_OP_INVALID)) { | |
043a0405 | 1388 | ath_drain_all_txq(sc, false); |
ff37e337 | 1389 | ath_stoprecv(sc); |
af03abec | 1390 | ath9k_hw_phy_disable(ah); |
ff37e337 | 1391 | } else |
b77f483f | 1392 | sc->rx.rxlink = NULL; |
ff37e337 | 1393 | |
ff37e337 | 1394 | /* disable HAL and put h/w to sleep */ |
af03abec LR |
1395 | ath9k_hw_disable(ah); |
1396 | ath9k_hw_configpcipowersave(ah, 1, 1); | |
3867cf6a S |
1397 | ath9k_ps_restore(sc); |
1398 | ||
1399 | /* Finally, put the chip in FULL SLEEP mode */ | |
9ecdef4b | 1400 | ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP); |
ff37e337 S |
1401 | |
1402 | sc->sc_flags |= SC_OP_INVALID; | |
500c064d | 1403 | |
141b38b6 S |
1404 | mutex_unlock(&sc->mutex); |
1405 | ||
c46917bb | 1406 | ath_print(common, ATH_DBG_CONFIG, "Driver halt\n"); |
f078f209 LR |
1407 | } |
1408 | ||
8feceb67 | 1409 | static int ath9k_add_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1410 | struct ieee80211_vif *vif) |
f078f209 | 1411 | { |
bce048d7 JM |
1412 | struct ath_wiphy *aphy = hw->priv; |
1413 | struct ath_softc *sc = aphy->sc; | |
3069168c PR |
1414 | struct ath_hw *ah = sc->sc_ah; |
1415 | struct ath_common *common = ath9k_hw_common(ah); | |
1ed32e4f | 1416 | struct ath_vif *avp = (void *)vif->drv_priv; |
d97809db | 1417 | enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED; |
2c3db3d5 | 1418 | int ret = 0; |
8feceb67 | 1419 | |
141b38b6 S |
1420 | mutex_lock(&sc->mutex); |
1421 | ||
3069168c | 1422 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) && |
8ca21f01 JM |
1423 | sc->nvifs > 0) { |
1424 | ret = -ENOBUFS; | |
1425 | goto out; | |
1426 | } | |
1427 | ||
1ed32e4f | 1428 | switch (vif->type) { |
05c914fe | 1429 | case NL80211_IFTYPE_STATION: |
d97809db | 1430 | ic_opmode = NL80211_IFTYPE_STATION; |
f078f209 | 1431 | break; |
05c914fe | 1432 | case NL80211_IFTYPE_ADHOC: |
05c914fe | 1433 | case NL80211_IFTYPE_AP: |
9cb5412b | 1434 | case NL80211_IFTYPE_MESH_POINT: |
2c3db3d5 JM |
1435 | if (sc->nbcnvifs >= ATH_BCBUF) { |
1436 | ret = -ENOBUFS; | |
1437 | goto out; | |
1438 | } | |
1ed32e4f | 1439 | ic_opmode = vif->type; |
f078f209 LR |
1440 | break; |
1441 | default: | |
c46917bb | 1442 | ath_print(common, ATH_DBG_FATAL, |
1ed32e4f | 1443 | "Interface type %d not yet supported\n", vif->type); |
2c3db3d5 JM |
1444 | ret = -EOPNOTSUPP; |
1445 | goto out; | |
f078f209 LR |
1446 | } |
1447 | ||
c46917bb LR |
1448 | ath_print(common, ATH_DBG_CONFIG, |
1449 | "Attach a VIF of type: %d\n", ic_opmode); | |
8feceb67 | 1450 | |
17d7904d | 1451 | /* Set the VIF opmode */ |
5640b08e S |
1452 | avp->av_opmode = ic_opmode; |
1453 | avp->av_bslot = -1; | |
1454 | ||
2c3db3d5 | 1455 | sc->nvifs++; |
8ca21f01 | 1456 | |
3069168c | 1457 | if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) |
8ca21f01 JM |
1458 | ath9k_set_bssid_mask(hw); |
1459 | ||
2c3db3d5 JM |
1460 | if (sc->nvifs > 1) |
1461 | goto out; /* skip global settings for secondary vif */ | |
1462 | ||
b238e90e | 1463 | if (ic_opmode == NL80211_IFTYPE_AP) { |
3069168c | 1464 | ath9k_hw_set_tsfadjust(ah, 1); |
b238e90e S |
1465 | sc->sc_flags |= SC_OP_TSF_RESET; |
1466 | } | |
5640b08e | 1467 | |
5640b08e | 1468 | /* Set the device opmode */ |
3069168c | 1469 | ah->opmode = ic_opmode; |
5640b08e | 1470 | |
4e30ffa2 VN |
1471 | /* |
1472 | * Enable MIB interrupts when there are hardware phy counters. | |
1473 | * Note we only do this (at the moment) for station mode. | |
1474 | */ | |
1ed32e4f JB |
1475 | if ((vif->type == NL80211_IFTYPE_STATION) || |
1476 | (vif->type == NL80211_IFTYPE_ADHOC) || | |
1477 | (vif->type == NL80211_IFTYPE_MESH_POINT)) { | |
3448f912 LR |
1478 | if (ah->config.enable_ani) |
1479 | ah->imask |= ATH9K_INT_MIB; | |
3069168c | 1480 | ah->imask |= ATH9K_INT_TSFOOR; |
4af9cf4f S |
1481 | } |
1482 | ||
3069168c | 1483 | ath9k_hw_set_interrupts(ah, ah->imask); |
4e30ffa2 | 1484 | |
1ed32e4f JB |
1485 | if (vif->type == NL80211_IFTYPE_AP || |
1486 | vif->type == NL80211_IFTYPE_ADHOC || | |
6c3118e2 VT |
1487 | vif->type == NL80211_IFTYPE_MONITOR) { |
1488 | sc->sc_flags |= SC_OP_ANI_RUN; | |
3d536acf | 1489 | ath_start_ani(common); |
6c3118e2 | 1490 | } |
6f255425 | 1491 | |
2c3db3d5 | 1492 | out: |
141b38b6 | 1493 | mutex_unlock(&sc->mutex); |
2c3db3d5 | 1494 | return ret; |
f078f209 LR |
1495 | } |
1496 | ||
8feceb67 | 1497 | static void ath9k_remove_interface(struct ieee80211_hw *hw, |
1ed32e4f | 1498 | struct ieee80211_vif *vif) |
f078f209 | 1499 | { |
bce048d7 JM |
1500 | struct ath_wiphy *aphy = hw->priv; |
1501 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1502 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
1ed32e4f | 1503 | struct ath_vif *avp = (void *)vif->drv_priv; |
2c3db3d5 | 1504 | int i; |
f078f209 | 1505 | |
c46917bb | 1506 | ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n"); |
f078f209 | 1507 | |
141b38b6 S |
1508 | mutex_lock(&sc->mutex); |
1509 | ||
6f255425 | 1510 | /* Stop ANI */ |
6c3118e2 | 1511 | sc->sc_flags &= ~SC_OP_ANI_RUN; |
3d536acf | 1512 | del_timer_sync(&common->ani.timer); |
580f0b8a | 1513 | |
8feceb67 | 1514 | /* Reclaim beacon resources */ |
9cb5412b PE |
1515 | if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) || |
1516 | (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) || | |
1517 | (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) { | |
5f70a88f | 1518 | ath9k_ps_wakeup(sc); |
b77f483f | 1519 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); |
5f70a88f | 1520 | ath9k_ps_restore(sc); |
580f0b8a | 1521 | } |
f078f209 | 1522 | |
74401773 | 1523 | ath_beacon_return(sc, avp); |
8feceb67 | 1524 | sc->sc_flags &= ~SC_OP_BEACONS; |
f078f209 | 1525 | |
2c3db3d5 | 1526 | for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) { |
1ed32e4f | 1527 | if (sc->beacon.bslot[i] == vif) { |
2c3db3d5 JM |
1528 | printk(KERN_DEBUG "%s: vif had allocated beacon " |
1529 | "slot\n", __func__); | |
1530 | sc->beacon.bslot[i] = NULL; | |
c52f33d0 | 1531 | sc->beacon.bslot_aphy[i] = NULL; |
2c3db3d5 JM |
1532 | } |
1533 | } | |
1534 | ||
17d7904d | 1535 | sc->nvifs--; |
141b38b6 S |
1536 | |
1537 | mutex_unlock(&sc->mutex); | |
f078f209 LR |
1538 | } |
1539 | ||
3f7c5c10 SB |
1540 | void ath9k_enable_ps(struct ath_softc *sc) |
1541 | { | |
3069168c PR |
1542 | struct ath_hw *ah = sc->sc_ah; |
1543 | ||
3f7c5c10 | 1544 | sc->ps_enabled = true; |
3069168c PR |
1545 | if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
1546 | if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) { | |
1547 | ah->imask |= ATH9K_INT_TIM_TIMER; | |
1548 | ath9k_hw_set_interrupts(ah, ah->imask); | |
3f7c5c10 SB |
1549 | } |
1550 | } | |
3069168c | 1551 | ath9k_hw_setrxabort(ah, 1); |
3f7c5c10 SB |
1552 | } |
1553 | ||
e8975581 | 1554 | static int ath9k_config(struct ieee80211_hw *hw, u32 changed) |
f078f209 | 1555 | { |
bce048d7 JM |
1556 | struct ath_wiphy *aphy = hw->priv; |
1557 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1558 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
e8975581 | 1559 | struct ieee80211_conf *conf = &hw->conf; |
8782b41d | 1560 | struct ath_hw *ah = sc->sc_ah; |
194b7c13 | 1561 | bool disable_radio; |
f078f209 | 1562 | |
aa33de09 | 1563 | mutex_lock(&sc->mutex); |
141b38b6 | 1564 | |
194b7c13 LR |
1565 | /* |
1566 | * Leave this as the first check because we need to turn on the | |
1567 | * radio if it was disabled before prior to processing the rest | |
1568 | * of the changes. Likewise we must only disable the radio towards | |
1569 | * the end. | |
1570 | */ | |
64839170 | 1571 | if (changed & IEEE80211_CONF_CHANGE_IDLE) { |
194b7c13 LR |
1572 | bool enable_radio; |
1573 | bool all_wiphys_idle; | |
1574 | bool idle = !!(conf->flags & IEEE80211_CONF_IDLE); | |
64839170 LR |
1575 | |
1576 | spin_lock_bh(&sc->wiphy_lock); | |
1577 | all_wiphys_idle = ath9k_all_wiphys_idle(sc); | |
194b7c13 LR |
1578 | ath9k_set_wiphy_idle(aphy, idle); |
1579 | ||
11446011 | 1580 | enable_radio = (!idle && all_wiphys_idle); |
194b7c13 LR |
1581 | |
1582 | /* | |
1583 | * After we unlock here its possible another wiphy | |
1584 | * can be re-renabled so to account for that we will | |
1585 | * only disable the radio toward the end of this routine | |
1586 | * if by then all wiphys are still idle. | |
1587 | */ | |
64839170 LR |
1588 | spin_unlock_bh(&sc->wiphy_lock); |
1589 | ||
194b7c13 | 1590 | if (enable_radio) { |
1dbfd9d4 | 1591 | sc->ps_idle = false; |
68a89116 | 1592 | ath_radio_enable(sc, hw); |
c46917bb LR |
1593 | ath_print(common, ATH_DBG_CONFIG, |
1594 | "not-idle: enabling radio\n"); | |
64839170 LR |
1595 | } |
1596 | } | |
1597 | ||
e7824a50 LR |
1598 | /* |
1599 | * We just prepare to enable PS. We have to wait until our AP has | |
1600 | * ACK'd our null data frame to disable RX otherwise we'll ignore | |
1601 | * those ACKs and end up retransmitting the same null data frames. | |
1602 | * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode. | |
1603 | */ | |
3cbb5dd7 VN |
1604 | if (changed & IEEE80211_CONF_CHANGE_PS) { |
1605 | if (conf->flags & IEEE80211_CONF_PS) { | |
1b04b930 | 1606 | sc->ps_flags |= PS_ENABLED; |
e7824a50 LR |
1607 | /* |
1608 | * At this point we know hardware has received an ACK | |
1609 | * of a previously sent null data frame. | |
1610 | */ | |
1b04b930 S |
1611 | if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) { |
1612 | sc->ps_flags &= ~PS_NULLFUNC_COMPLETED; | |
3f7c5c10 | 1613 | ath9k_enable_ps(sc); |
e7824a50 | 1614 | } |
3cbb5dd7 | 1615 | } else { |
96148326 | 1616 | sc->ps_enabled = false; |
1b04b930 S |
1617 | sc->ps_flags &= ~(PS_ENABLED | |
1618 | PS_NULLFUNC_COMPLETED); | |
9ecdef4b | 1619 | ath9k_setpower(sc, ATH9K_PM_AWAKE); |
8782b41d VN |
1620 | if (!(ah->caps.hw_caps & |
1621 | ATH9K_HW_CAP_AUTOSLEEP)) { | |
1622 | ath9k_hw_setrxabort(sc->sc_ah, 0); | |
1b04b930 S |
1623 | sc->ps_flags &= ~(PS_WAIT_FOR_BEACON | |
1624 | PS_WAIT_FOR_CAB | | |
1625 | PS_WAIT_FOR_PSPOLL_DATA | | |
1626 | PS_WAIT_FOR_TX_ACK); | |
3069168c PR |
1627 | if (ah->imask & ATH9K_INT_TIM_TIMER) { |
1628 | ah->imask &= ~ATH9K_INT_TIM_TIMER; | |
8782b41d | 1629 | ath9k_hw_set_interrupts(sc->sc_ah, |
3069168c | 1630 | ah->imask); |
8782b41d | 1631 | } |
3cbb5dd7 VN |
1632 | } |
1633 | } | |
1634 | } | |
1635 | ||
199afd9d S |
1636 | if (changed & IEEE80211_CONF_CHANGE_MONITOR) { |
1637 | if (conf->flags & IEEE80211_CONF_MONITOR) { | |
1638 | ath_print(common, ATH_DBG_CONFIG, | |
1639 | "HW opmode set to Monitor mode\n"); | |
1640 | sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR; | |
1641 | } | |
1642 | } | |
1643 | ||
4797938c | 1644 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
99405f93 | 1645 | struct ieee80211_channel *curchan = hw->conf.channel; |
5f8e077c | 1646 | int pos = curchan->hw_value; |
ae5eb026 | 1647 | |
0e2dedf9 JM |
1648 | aphy->chan_idx = pos; |
1649 | aphy->chan_is_ht = conf_is_ht(conf); | |
1650 | ||
8089cc47 JM |
1651 | if (aphy->state == ATH_WIPHY_SCAN || |
1652 | aphy->state == ATH_WIPHY_ACTIVE) | |
1653 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
1654 | else { | |
1655 | /* | |
1656 | * Do not change operational channel based on a paused | |
1657 | * wiphy changes. | |
1658 | */ | |
1659 | goto skip_chan_change; | |
1660 | } | |
0e2dedf9 | 1661 | |
c46917bb LR |
1662 | ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n", |
1663 | curchan->center_freq); | |
f078f209 | 1664 | |
5f8e077c | 1665 | /* XXX: remove me eventualy */ |
0e2dedf9 | 1666 | ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]); |
e11602b7 | 1667 | |
ecf70441 | 1668 | ath_update_chainmask(sc, conf_is_ht(conf)); |
86060f0d | 1669 | |
0e2dedf9 | 1670 | if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { |
c46917bb LR |
1671 | ath_print(common, ATH_DBG_FATAL, |
1672 | "Unable to set channel\n"); | |
aa33de09 | 1673 | mutex_unlock(&sc->mutex); |
e11602b7 S |
1674 | return -EINVAL; |
1675 | } | |
094d05dc | 1676 | } |
f078f209 | 1677 | |
8089cc47 | 1678 | skip_chan_change: |
c9f6a656 | 1679 | if (changed & IEEE80211_CONF_CHANGE_POWER) { |
17d7904d | 1680 | sc->config.txpowlimit = 2 * conf->power_level; |
c9f6a656 LR |
1681 | ath_update_txpow(sc); |
1682 | } | |
f078f209 | 1683 | |
194b7c13 LR |
1684 | spin_lock_bh(&sc->wiphy_lock); |
1685 | disable_radio = ath9k_all_wiphys_idle(sc); | |
1686 | spin_unlock_bh(&sc->wiphy_lock); | |
1687 | ||
64839170 | 1688 | if (disable_radio) { |
c46917bb | 1689 | ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n"); |
1dbfd9d4 | 1690 | sc->ps_idle = true; |
68a89116 | 1691 | ath_radio_disable(sc, hw); |
64839170 LR |
1692 | } |
1693 | ||
aa33de09 | 1694 | mutex_unlock(&sc->mutex); |
141b38b6 | 1695 | |
f078f209 LR |
1696 | return 0; |
1697 | } | |
1698 | ||
8feceb67 VT |
1699 | #define SUPPORTED_FILTERS \ |
1700 | (FIF_PROMISC_IN_BSS | \ | |
1701 | FIF_ALLMULTI | \ | |
1702 | FIF_CONTROL | \ | |
af6a3fc7 | 1703 | FIF_PSPOLL | \ |
8feceb67 VT |
1704 | FIF_OTHER_BSS | \ |
1705 | FIF_BCN_PRBRESP_PROMISC | \ | |
1706 | FIF_FCSFAIL) | |
c83be688 | 1707 | |
8feceb67 VT |
1708 | /* FIXME: sc->sc_full_reset ? */ |
1709 | static void ath9k_configure_filter(struct ieee80211_hw *hw, | |
1710 | unsigned int changed_flags, | |
1711 | unsigned int *total_flags, | |
3ac64bee | 1712 | u64 multicast) |
8feceb67 | 1713 | { |
bce048d7 JM |
1714 | struct ath_wiphy *aphy = hw->priv; |
1715 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 1716 | u32 rfilt; |
f078f209 | 1717 | |
8feceb67 VT |
1718 | changed_flags &= SUPPORTED_FILTERS; |
1719 | *total_flags &= SUPPORTED_FILTERS; | |
f078f209 | 1720 | |
b77f483f | 1721 | sc->rx.rxfilter = *total_flags; |
aa68aeaa | 1722 | ath9k_ps_wakeup(sc); |
8feceb67 VT |
1723 | rfilt = ath_calcrxfilter(sc); |
1724 | ath9k_hw_setrxfilter(sc->sc_ah, rfilt); | |
aa68aeaa | 1725 | ath9k_ps_restore(sc); |
f078f209 | 1726 | |
c46917bb LR |
1727 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG, |
1728 | "Set HW RX filter: 0x%x\n", rfilt); | |
8feceb67 | 1729 | } |
f078f209 | 1730 | |
4ca77860 JB |
1731 | static int ath9k_sta_add(struct ieee80211_hw *hw, |
1732 | struct ieee80211_vif *vif, | |
1733 | struct ieee80211_sta *sta) | |
8feceb67 | 1734 | { |
bce048d7 JM |
1735 | struct ath_wiphy *aphy = hw->priv; |
1736 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1737 | |
4ca77860 JB |
1738 | ath_node_attach(sc, sta); |
1739 | ||
1740 | return 0; | |
1741 | } | |
1742 | ||
1743 | static int ath9k_sta_remove(struct ieee80211_hw *hw, | |
1744 | struct ieee80211_vif *vif, | |
1745 | struct ieee80211_sta *sta) | |
1746 | { | |
1747 | struct ath_wiphy *aphy = hw->priv; | |
1748 | struct ath_softc *sc = aphy->sc; | |
1749 | ||
1750 | ath_node_detach(sc, sta); | |
1751 | ||
1752 | return 0; | |
f078f209 LR |
1753 | } |
1754 | ||
141b38b6 | 1755 | static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue, |
8feceb67 | 1756 | const struct ieee80211_tx_queue_params *params) |
f078f209 | 1757 | { |
bce048d7 JM |
1758 | struct ath_wiphy *aphy = hw->priv; |
1759 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1760 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 VT |
1761 | struct ath9k_tx_queue_info qi; |
1762 | int ret = 0, qnum; | |
f078f209 | 1763 | |
8feceb67 VT |
1764 | if (queue >= WME_NUM_AC) |
1765 | return 0; | |
f078f209 | 1766 | |
141b38b6 S |
1767 | mutex_lock(&sc->mutex); |
1768 | ||
1ffb0610 S |
1769 | memset(&qi, 0, sizeof(struct ath9k_tx_queue_info)); |
1770 | ||
8feceb67 VT |
1771 | qi.tqi_aifs = params->aifs; |
1772 | qi.tqi_cwmin = params->cw_min; | |
1773 | qi.tqi_cwmax = params->cw_max; | |
1774 | qi.tqi_burstTime = params->txop; | |
1775 | qnum = ath_get_hal_qnum(queue, sc); | |
f078f209 | 1776 | |
c46917bb LR |
1777 | ath_print(common, ATH_DBG_CONFIG, |
1778 | "Configure tx [queue/halq] [%d/%d], " | |
1779 | "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", | |
1780 | queue, qnum, params->aifs, params->cw_min, | |
1781 | params->cw_max, params->txop); | |
f078f209 | 1782 | |
8feceb67 VT |
1783 | ret = ath_txq_update(sc, qnum, &qi); |
1784 | if (ret) | |
c46917bb | 1785 | ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n"); |
f078f209 | 1786 | |
94db2936 VN |
1787 | if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) |
1788 | if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret) | |
1789 | ath_beaconq_config(sc); | |
1790 | ||
141b38b6 S |
1791 | mutex_unlock(&sc->mutex); |
1792 | ||
8feceb67 VT |
1793 | return ret; |
1794 | } | |
f078f209 | 1795 | |
8feceb67 VT |
1796 | static int ath9k_set_key(struct ieee80211_hw *hw, |
1797 | enum set_key_cmd cmd, | |
dc822b5d JB |
1798 | struct ieee80211_vif *vif, |
1799 | struct ieee80211_sta *sta, | |
8feceb67 VT |
1800 | struct ieee80211_key_conf *key) |
1801 | { | |
bce048d7 JM |
1802 | struct ath_wiphy *aphy = hw->priv; |
1803 | struct ath_softc *sc = aphy->sc; | |
c46917bb | 1804 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
8feceb67 | 1805 | int ret = 0; |
f078f209 | 1806 | |
b3bd89ce JM |
1807 | if (modparam_nohwcrypt) |
1808 | return -ENOSPC; | |
1809 | ||
141b38b6 | 1810 | mutex_lock(&sc->mutex); |
3cbb5dd7 | 1811 | ath9k_ps_wakeup(sc); |
c46917bb | 1812 | ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n"); |
f078f209 | 1813 | |
8feceb67 VT |
1814 | switch (cmd) { |
1815 | case SET_KEY: | |
7e86c104 | 1816 | ret = ath_key_config(common, vif, sta, key); |
6ace2891 JM |
1817 | if (ret >= 0) { |
1818 | key->hw_key_idx = ret; | |
8feceb67 VT |
1819 | /* push IV and Michael MIC generation to stack */ |
1820 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; | |
1821 | if (key->alg == ALG_TKIP) | |
1822 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; | |
0ced0e17 JM |
1823 | if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP) |
1824 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT; | |
6ace2891 | 1825 | ret = 0; |
8feceb67 VT |
1826 | } |
1827 | break; | |
1828 | case DISABLE_KEY: | |
7e86c104 | 1829 | ath_key_delete(common, key); |
8feceb67 VT |
1830 | break; |
1831 | default: | |
1832 | ret = -EINVAL; | |
1833 | } | |
f078f209 | 1834 | |
3cbb5dd7 | 1835 | ath9k_ps_restore(sc); |
141b38b6 S |
1836 | mutex_unlock(&sc->mutex); |
1837 | ||
8feceb67 VT |
1838 | return ret; |
1839 | } | |
f078f209 | 1840 | |
8feceb67 VT |
1841 | static void ath9k_bss_info_changed(struct ieee80211_hw *hw, |
1842 | struct ieee80211_vif *vif, | |
1843 | struct ieee80211_bss_conf *bss_conf, | |
1844 | u32 changed) | |
1845 | { | |
bce048d7 JM |
1846 | struct ath_wiphy *aphy = hw->priv; |
1847 | struct ath_softc *sc = aphy->sc; | |
2d0ddec5 | 1848 | struct ath_hw *ah = sc->sc_ah; |
1510718d | 1849 | struct ath_common *common = ath9k_hw_common(ah); |
2d0ddec5 | 1850 | struct ath_vif *avp = (void *)vif->drv_priv; |
0005baf4 | 1851 | int slottime; |
c6089ccc | 1852 | int error; |
f078f209 | 1853 | |
141b38b6 S |
1854 | mutex_lock(&sc->mutex); |
1855 | ||
c6089ccc S |
1856 | if (changed & BSS_CHANGED_BSSID) { |
1857 | /* Set BSSID */ | |
1858 | memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN); | |
1859 | memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN); | |
1510718d | 1860 | common->curaid = 0; |
f2b2143e | 1861 | ath9k_hw_write_associd(ah); |
2d0ddec5 | 1862 | |
c6089ccc S |
1863 | /* Set aggregation protection mode parameters */ |
1864 | sc->config.ath_aggr_prot = 0; | |
2d0ddec5 | 1865 | |
c6089ccc S |
1866 | /* Only legacy IBSS for now */ |
1867 | if (vif->type == NL80211_IFTYPE_ADHOC) | |
1868 | ath_update_chainmask(sc, 0); | |
2d0ddec5 | 1869 | |
c6089ccc S |
1870 | ath_print(common, ATH_DBG_CONFIG, |
1871 | "BSSID: %pM aid: 0x%x\n", | |
1872 | common->curbssid, common->curaid); | |
2d0ddec5 | 1873 | |
c6089ccc S |
1874 | /* need to reconfigure the beacon */ |
1875 | sc->sc_flags &= ~SC_OP_BEACONS ; | |
1876 | } | |
2d0ddec5 | 1877 | |
c6089ccc S |
1878 | /* Enable transmission of beacons (AP, IBSS, MESH) */ |
1879 | if ((changed & BSS_CHANGED_BEACON) || | |
1880 | ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) { | |
1881 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
1882 | error = ath_beacon_alloc(aphy, vif); | |
1883 | if (!error) | |
1884 | ath_beacon_config(sc, vif); | |
0005baf4 FF |
1885 | } |
1886 | ||
1887 | if (changed & BSS_CHANGED_ERP_SLOT) { | |
1888 | if (bss_conf->use_short_slot) | |
1889 | slottime = 9; | |
1890 | else | |
1891 | slottime = 20; | |
1892 | if (vif->type == NL80211_IFTYPE_AP) { | |
1893 | /* | |
1894 | * Defer update, so that connected stations can adjust | |
1895 | * their settings at the same time. | |
1896 | * See beacon.c for more details | |
1897 | */ | |
1898 | sc->beacon.slottime = slottime; | |
1899 | sc->beacon.updateslot = UPDATE; | |
1900 | } else { | |
1901 | ah->slottime = slottime; | |
1902 | ath9k_hw_init_global_settings(ah); | |
1903 | } | |
2d0ddec5 JB |
1904 | } |
1905 | ||
c6089ccc S |
1906 | /* Disable transmission of beacons */ |
1907 | if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon) | |
1908 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 | 1909 | |
c6089ccc S |
1910 | if (changed & BSS_CHANGED_BEACON_INT) { |
1911 | sc->beacon_interval = bss_conf->beacon_int; | |
1912 | /* | |
1913 | * In case of AP mode, the HW TSF has to be reset | |
1914 | * when the beacon interval changes. | |
1915 | */ | |
1916 | if (vif->type == NL80211_IFTYPE_AP) { | |
1917 | sc->sc_flags |= SC_OP_TSF_RESET; | |
1918 | ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq); | |
2d0ddec5 JB |
1919 | error = ath_beacon_alloc(aphy, vif); |
1920 | if (!error) | |
1921 | ath_beacon_config(sc, vif); | |
c6089ccc S |
1922 | } else { |
1923 | ath_beacon_config(sc, vif); | |
2d0ddec5 JB |
1924 | } |
1925 | } | |
1926 | ||
8feceb67 | 1927 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
c46917bb LR |
1928 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", |
1929 | bss_conf->use_short_preamble); | |
8feceb67 VT |
1930 | if (bss_conf->use_short_preamble) |
1931 | sc->sc_flags |= SC_OP_PREAMBLE_SHORT; | |
1932 | else | |
1933 | sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT; | |
1934 | } | |
f078f209 | 1935 | |
8feceb67 | 1936 | if (changed & BSS_CHANGED_ERP_CTS_PROT) { |
c46917bb LR |
1937 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", |
1938 | bss_conf->use_cts_prot); | |
8feceb67 VT |
1939 | if (bss_conf->use_cts_prot && |
1940 | hw->conf.channel->band != IEEE80211_BAND_5GHZ) | |
1941 | sc->sc_flags |= SC_OP_PROTECT_ENABLE; | |
1942 | else | |
1943 | sc->sc_flags &= ~SC_OP_PROTECT_ENABLE; | |
1944 | } | |
f078f209 | 1945 | |
8feceb67 | 1946 | if (changed & BSS_CHANGED_ASSOC) { |
c46917bb | 1947 | ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", |
8feceb67 | 1948 | bss_conf->assoc); |
5640b08e | 1949 | ath9k_bss_assoc_info(sc, vif, bss_conf); |
8feceb67 | 1950 | } |
141b38b6 S |
1951 | |
1952 | mutex_unlock(&sc->mutex); | |
8feceb67 | 1953 | } |
f078f209 | 1954 | |
8feceb67 VT |
1955 | static u64 ath9k_get_tsf(struct ieee80211_hw *hw) |
1956 | { | |
1957 | u64 tsf; | |
bce048d7 JM |
1958 | struct ath_wiphy *aphy = hw->priv; |
1959 | struct ath_softc *sc = aphy->sc; | |
f078f209 | 1960 | |
141b38b6 S |
1961 | mutex_lock(&sc->mutex); |
1962 | tsf = ath9k_hw_gettsf64(sc->sc_ah); | |
1963 | mutex_unlock(&sc->mutex); | |
f078f209 | 1964 | |
8feceb67 VT |
1965 | return tsf; |
1966 | } | |
f078f209 | 1967 | |
3b5d665b AF |
1968 | static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf) |
1969 | { | |
bce048d7 JM |
1970 | struct ath_wiphy *aphy = hw->priv; |
1971 | struct ath_softc *sc = aphy->sc; | |
3b5d665b | 1972 | |
141b38b6 S |
1973 | mutex_lock(&sc->mutex); |
1974 | ath9k_hw_settsf64(sc->sc_ah, tsf); | |
1975 | mutex_unlock(&sc->mutex); | |
3b5d665b AF |
1976 | } |
1977 | ||
8feceb67 VT |
1978 | static void ath9k_reset_tsf(struct ieee80211_hw *hw) |
1979 | { | |
bce048d7 JM |
1980 | struct ath_wiphy *aphy = hw->priv; |
1981 | struct ath_softc *sc = aphy->sc; | |
c83be688 | 1982 | |
141b38b6 | 1983 | mutex_lock(&sc->mutex); |
21526d57 LR |
1984 | |
1985 | ath9k_ps_wakeup(sc); | |
141b38b6 | 1986 | ath9k_hw_reset_tsf(sc->sc_ah); |
21526d57 LR |
1987 | ath9k_ps_restore(sc); |
1988 | ||
141b38b6 | 1989 | mutex_unlock(&sc->mutex); |
8feceb67 | 1990 | } |
f078f209 | 1991 | |
8feceb67 | 1992 | static int ath9k_ampdu_action(struct ieee80211_hw *hw, |
c951ad35 | 1993 | struct ieee80211_vif *vif, |
141b38b6 S |
1994 | enum ieee80211_ampdu_mlme_action action, |
1995 | struct ieee80211_sta *sta, | |
1996 | u16 tid, u16 *ssn) | |
8feceb67 | 1997 | { |
bce048d7 JM |
1998 | struct ath_wiphy *aphy = hw->priv; |
1999 | struct ath_softc *sc = aphy->sc; | |
8feceb67 | 2000 | int ret = 0; |
f078f209 | 2001 | |
8feceb67 VT |
2002 | switch (action) { |
2003 | case IEEE80211_AMPDU_RX_START: | |
dca3edb8 S |
2004 | if (!(sc->sc_flags & SC_OP_RXAGGR)) |
2005 | ret = -ENOTSUPP; | |
8feceb67 VT |
2006 | break; |
2007 | case IEEE80211_AMPDU_RX_STOP: | |
8feceb67 VT |
2008 | break; |
2009 | case IEEE80211_AMPDU_TX_START: | |
8b685ba9 | 2010 | ath9k_ps_wakeup(sc); |
f83da965 | 2011 | ath_tx_aggr_start(sc, sta, tid, ssn); |
c951ad35 | 2012 | ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2013 | ath9k_ps_restore(sc); |
8feceb67 VT |
2014 | break; |
2015 | case IEEE80211_AMPDU_TX_STOP: | |
8b685ba9 | 2016 | ath9k_ps_wakeup(sc); |
f83da965 | 2017 | ath_tx_aggr_stop(sc, sta, tid); |
c951ad35 | 2018 | ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); |
8b685ba9 | 2019 | ath9k_ps_restore(sc); |
8feceb67 | 2020 | break; |
b1720231 | 2021 | case IEEE80211_AMPDU_TX_OPERATIONAL: |
8b685ba9 | 2022 | ath9k_ps_wakeup(sc); |
8469cdef | 2023 | ath_tx_aggr_resume(sc, sta, tid); |
8b685ba9 | 2024 | ath9k_ps_restore(sc); |
8469cdef | 2025 | break; |
8feceb67 | 2026 | default: |
c46917bb LR |
2027 | ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL, |
2028 | "Unknown AMPDU action\n"); | |
8feceb67 VT |
2029 | } |
2030 | ||
2031 | return ret; | |
f078f209 LR |
2032 | } |
2033 | ||
62dad5b0 BP |
2034 | static int ath9k_get_survey(struct ieee80211_hw *hw, int idx, |
2035 | struct survey_info *survey) | |
2036 | { | |
2037 | struct ath_wiphy *aphy = hw->priv; | |
2038 | struct ath_softc *sc = aphy->sc; | |
2039 | struct ath_hw *ah = sc->sc_ah; | |
2040 | struct ath_common *common = ath9k_hw_common(ah); | |
2041 | struct ieee80211_conf *conf = &hw->conf; | |
2042 | ||
2043 | if (idx != 0) | |
2044 | return -ENOENT; | |
2045 | ||
2046 | survey->channel = conf->channel; | |
2047 | survey->filled = SURVEY_INFO_NOISE_DBM; | |
2048 | survey->noise = common->ani.noise_floor; | |
2049 | ||
2050 | return 0; | |
2051 | } | |
2052 | ||
0c98de65 S |
2053 | static void ath9k_sw_scan_start(struct ieee80211_hw *hw) |
2054 | { | |
bce048d7 JM |
2055 | struct ath_wiphy *aphy = hw->priv; |
2056 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 2057 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 2058 | |
3d832611 | 2059 | mutex_lock(&sc->mutex); |
8089cc47 JM |
2060 | if (ath9k_wiphy_scanning(sc)) { |
2061 | printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the " | |
2062 | "same time\n"); | |
2063 | /* | |
2064 | * Do not allow the concurrent scanning state for now. This | |
2065 | * could be improved with scanning control moved into ath9k. | |
2066 | */ | |
3d832611 | 2067 | mutex_unlock(&sc->mutex); |
8089cc47 JM |
2068 | return; |
2069 | } | |
2070 | ||
2071 | aphy->state = ATH_WIPHY_SCAN; | |
2072 | ath9k_wiphy_pause_all_forced(sc, aphy); | |
0c98de65 | 2073 | sc->sc_flags |= SC_OP_SCANNING; |
05c78d6d | 2074 | del_timer_sync(&common->ani.timer); |
b6ce5c33 | 2075 | cancel_delayed_work_sync(&sc->tx_complete_work); |
3d832611 | 2076 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2077 | } |
2078 | ||
2079 | static void ath9k_sw_scan_complete(struct ieee80211_hw *hw) | |
2080 | { | |
bce048d7 JM |
2081 | struct ath_wiphy *aphy = hw->priv; |
2082 | struct ath_softc *sc = aphy->sc; | |
05c78d6d | 2083 | struct ath_common *common = ath9k_hw_common(sc->sc_ah); |
0c98de65 | 2084 | |
3d832611 | 2085 | mutex_lock(&sc->mutex); |
8089cc47 | 2086 | aphy->state = ATH_WIPHY_ACTIVE; |
0c98de65 | 2087 | sc->sc_flags &= ~SC_OP_SCANNING; |
9c07a777 | 2088 | sc->sc_flags |= SC_OP_FULL_RESET; |
05c78d6d | 2089 | ath_start_ani(common); |
b6ce5c33 | 2090 | ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0); |
d0bec342 | 2091 | ath_beacon_config(sc, NULL); |
3d832611 | 2092 | mutex_unlock(&sc->mutex); |
0c98de65 S |
2093 | } |
2094 | ||
e239d859 FF |
2095 | static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class) |
2096 | { | |
2097 | struct ath_wiphy *aphy = hw->priv; | |
2098 | struct ath_softc *sc = aphy->sc; | |
2099 | struct ath_hw *ah = sc->sc_ah; | |
2100 | ||
2101 | mutex_lock(&sc->mutex); | |
2102 | ah->coverage_class = coverage_class; | |
2103 | ath9k_hw_init_global_settings(ah); | |
2104 | mutex_unlock(&sc->mutex); | |
2105 | } | |
2106 | ||
6baff7f9 | 2107 | struct ieee80211_ops ath9k_ops = { |
8feceb67 VT |
2108 | .tx = ath9k_tx, |
2109 | .start = ath9k_start, | |
2110 | .stop = ath9k_stop, | |
2111 | .add_interface = ath9k_add_interface, | |
2112 | .remove_interface = ath9k_remove_interface, | |
2113 | .config = ath9k_config, | |
8feceb67 | 2114 | .configure_filter = ath9k_configure_filter, |
4ca77860 JB |
2115 | .sta_add = ath9k_sta_add, |
2116 | .sta_remove = ath9k_sta_remove, | |
8feceb67 | 2117 | .conf_tx = ath9k_conf_tx, |
8feceb67 | 2118 | .bss_info_changed = ath9k_bss_info_changed, |
8feceb67 | 2119 | .set_key = ath9k_set_key, |
8feceb67 | 2120 | .get_tsf = ath9k_get_tsf, |
3b5d665b | 2121 | .set_tsf = ath9k_set_tsf, |
8feceb67 | 2122 | .reset_tsf = ath9k_reset_tsf, |
4233df6b | 2123 | .ampdu_action = ath9k_ampdu_action, |
62dad5b0 | 2124 | .get_survey = ath9k_get_survey, |
0c98de65 S |
2125 | .sw_scan_start = ath9k_sw_scan_start, |
2126 | .sw_scan_complete = ath9k_sw_scan_complete, | |
3b319aae | 2127 | .rfkill_poll = ath9k_rfkill_poll_state, |
e239d859 | 2128 | .set_coverage_class = ath9k_set_coverage_class, |
8feceb67 | 2129 | }; |