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Merge branch 'master' of git://dev.medozas.de/linux
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ce111bad
LR
21static void ath_cache_conf_rate(struct ath_softc *sc,
22 struct ieee80211_conf *conf)
ff37e337 23{
030bb495
LR
24 switch (conf->channel->band) {
25 case IEEE80211_BAND_2GHZ:
26 if (conf_is_ht20(conf))
545750d3 27 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
030bb495 28 else if (conf_is_ht40_minus(conf))
545750d3 29 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
030bb495 30 else if (conf_is_ht40_plus(conf))
545750d3 31 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
96742256 32 else
545750d3 33 sc->cur_rate_mode = ATH9K_MODE_11G;
030bb495
LR
34 break;
35 case IEEE80211_BAND_5GHZ:
36 if (conf_is_ht20(conf))
545750d3 37 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
030bb495 38 else if (conf_is_ht40_minus(conf))
545750d3 39 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
030bb495 40 else if (conf_is_ht40_plus(conf))
545750d3 41 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
030bb495 42 else
545750d3 43 sc->cur_rate_mode = ATH9K_MODE_11A;
030bb495
LR
44 break;
45 default:
ce111bad 46 BUG_ON(1);
030bb495
LR
47 break;
48 }
ff37e337
S
49}
50
51static void ath_update_txpow(struct ath_softc *sc)
52{
cbe61d8a 53 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
54 u32 txpow;
55
17d7904d
S
56 if (sc->curtxpow != sc->config.txpowlimit) {
57 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S
58 /* read back in case value is clamped */
59 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 60 sc->curtxpow = txpow;
ff37e337
S
61 }
62}
63
64static u8 parse_mpdudensity(u8 mpdudensity)
65{
66 /*
67 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
68 * 0 for no restriction
69 * 1 for 1/4 us
70 * 2 for 1/2 us
71 * 3 for 1 us
72 * 4 for 2 us
73 * 5 for 4 us
74 * 6 for 8 us
75 * 7 for 16 us
76 */
77 switch (mpdudensity) {
78 case 0:
79 return 0;
80 case 1:
81 case 2:
82 case 3:
83 /* Our lower layer calculations limit our precision to
84 1 microsecond */
85 return 1;
86 case 4:
87 return 2;
88 case 5:
89 return 4;
90 case 6:
91 return 8;
92 case 7:
93 return 16;
94 default:
95 return 0;
96 }
97}
98
82880a7c
VT
99static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
100 struct ieee80211_hw *hw)
101{
102 struct ieee80211_channel *curchan = hw->conf.channel;
103 struct ath9k_channel *channel;
104 u8 chan_idx;
105
106 chan_idx = curchan->hw_value;
107 channel = &sc->sc_ah->channels[chan_idx];
108 ath9k_update_ichannel(sc, hw, channel);
109 return channel;
110}
111
55624204 112bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
113{
114 unsigned long flags;
115 bool ret;
116
9ecdef4b
LR
117 spin_lock_irqsave(&sc->sc_pm_lock, flags);
118 ret = ath9k_hw_setpower(sc->sc_ah, mode);
119 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
120
121 return ret;
122}
123
a91d75ae
LR
124void ath9k_ps_wakeup(struct ath_softc *sc)
125{
126 unsigned long flags;
127
128 spin_lock_irqsave(&sc->sc_pm_lock, flags);
129 if (++sc->ps_usecount != 1)
130 goto unlock;
131
9ecdef4b 132 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR
133
134 unlock:
135 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
136}
137
138void ath9k_ps_restore(struct ath_softc *sc)
139{
140 unsigned long flags;
141
142 spin_lock_irqsave(&sc->sc_pm_lock, flags);
143 if (--sc->ps_usecount != 0)
144 goto unlock;
145
1dbfd9d4
VN
146 if (sc->ps_idle)
147 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
148 else if (sc->ps_enabled &&
149 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
150 PS_WAIT_FOR_CAB |
151 PS_WAIT_FOR_PSPOLL_DATA |
152 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 153 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
154
155 unlock:
156 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
157}
158
ff37e337
S
159/*
160 * Set/change channels. If the channel is really being changed, it's done
161 * by reseting the chip. To accomplish this we must first cleanup any pending
162 * DMA, then restart stuff.
163*/
0e2dedf9
JM
164int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
165 struct ath9k_channel *hchan)
ff37e337 166{
cbe61d8a 167 struct ath_hw *ah = sc->sc_ah;
c46917bb 168 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 169 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 170 bool fastcc = true, stopped;
ae8d2858
LR
171 struct ieee80211_channel *channel = hw->conf.channel;
172 int r;
ff37e337
S
173
174 if (sc->sc_flags & SC_OP_INVALID)
175 return -EIO;
176
3cbb5dd7
VN
177 ath9k_ps_wakeup(sc);
178
c0d7c7af
LR
179 /*
180 * This is only performed if the channel settings have
181 * actually changed.
182 *
183 * To switch channels clear any pending DMA operations;
184 * wait long enough for the RX fifo to drain, reset the
185 * hardware at the new frequency, and then re-enable
186 * the relevant bits of the h/w.
187 */
188 ath9k_hw_set_interrupts(ah, 0);
043a0405 189 ath_drain_all_txq(sc, false);
c0d7c7af 190 stopped = ath_stoprecv(sc);
ff37e337 191
c0d7c7af
LR
192 /* XXX: do not flush receive queue here. We don't want
193 * to flush data frames already in queue because of
194 * changing channel. */
ff37e337 195
c0d7c7af
LR
196 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
197 fastcc = false;
198
c46917bb 199 ath_print(common, ATH_DBG_CONFIG,
25c56eec 200 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
c46917bb 201 sc->sc_ah->curchan->channel,
25c56eec 202 channel->center_freq, conf_is_ht40(conf));
ff37e337 203
c0d7c7af
LR
204 spin_lock_bh(&sc->sc_resetlock);
205
206 r = ath9k_hw_reset(ah, hchan, fastcc);
207 if (r) {
c46917bb 208 ath_print(common, ATH_DBG_FATAL,
f643e51d 209 "Unable to reset channel (%u MHz), "
c46917bb
LR
210 "reset status %d\n",
211 channel->center_freq, r);
c0d7c7af 212 spin_unlock_bh(&sc->sc_resetlock);
3989279c 213 goto ps_restore;
ff37e337 214 }
c0d7c7af
LR
215 spin_unlock_bh(&sc->sc_resetlock);
216
c0d7c7af
LR
217 sc->sc_flags &= ~SC_OP_FULL_RESET;
218
219 if (ath_startrecv(sc) != 0) {
c46917bb
LR
220 ath_print(common, ATH_DBG_FATAL,
221 "Unable to restart recv logic\n");
3989279c
GJ
222 r = -EIO;
223 goto ps_restore;
c0d7c7af
LR
224 }
225
226 ath_cache_conf_rate(sc, &hw->conf);
227 ath_update_txpow(sc);
3069168c 228 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c
GJ
229
230 ps_restore:
3cbb5dd7 231 ath9k_ps_restore(sc);
3989279c 232 return r;
ff37e337
S
233}
234
235/*
236 * This routine performs the periodic noise floor calibration function
237 * that is used to adjust and optimize the chip performance. This
238 * takes environmental changes (location, temperature) into account.
239 * When the task is complete, it reschedules itself depending on the
240 * appropriate interval that was calculated.
241 */
55624204 242void ath_ani_calibrate(unsigned long data)
ff37e337 243{
20977d3e
S
244 struct ath_softc *sc = (struct ath_softc *)data;
245 struct ath_hw *ah = sc->sc_ah;
c46917bb 246 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
247 bool longcal = false;
248 bool shortcal = false;
249 bool aniflag = false;
250 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 251 u32 cal_interval, short_cal_interval;
ff37e337 252
20977d3e
S
253 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
254 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 255
1ffc1c61
JM
256 /* Only calibrate if awake */
257 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
258 goto set_timer;
259
260 ath9k_ps_wakeup(sc);
261
ff37e337 262 /* Long calibration runs independently of short calibration. */
3d536acf 263 if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 264 longcal = true;
c46917bb 265 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 266 common->ani.longcal_timer = timestamp;
ff37e337
S
267 }
268
17d7904d 269 /* Short calibration applies only while caldone is false */
3d536acf
LR
270 if (!common->ani.caldone) {
271 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 272 shortcal = true;
c46917bb
LR
273 ath_print(common, ATH_DBG_ANI,
274 "shortcal @%lu\n", jiffies);
3d536acf
LR
275 common->ani.shortcal_timer = timestamp;
276 common->ani.resetcal_timer = timestamp;
ff37e337
S
277 }
278 } else {
3d536acf 279 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 280 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
281 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
282 if (common->ani.caldone)
283 common->ani.resetcal_timer = timestamp;
ff37e337
S
284 }
285 }
286
287 /* Verify whether we must check ANI */
3d536acf 288 if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 289 aniflag = true;
3d536acf 290 common->ani.checkani_timer = timestamp;
ff37e337
S
291 }
292
293 /* Skip all processing if there's nothing to do. */
294 if (longcal || shortcal || aniflag) {
295 /* Call ANI routine if necessary */
296 if (aniflag)
22e66a4c 297 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S
298
299 /* Perform calibration if necessary */
300 if (longcal || shortcal) {
3d536acf 301 common->ani.caldone =
43c27613
LR
302 ath9k_hw_calibrate(ah,
303 ah->curchan,
304 common->rx_chainmask,
305 longcal);
379f0440
S
306
307 if (longcal)
3d536acf 308 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
379f0440
S
309 ah->curchan);
310
c46917bb
LR
311 ath_print(common, ATH_DBG_ANI,
312 " calibrate chan %u/%x nf: %d\n",
313 ah->curchan->channel,
314 ah->curchan->channelFlags,
3d536acf 315 common->ani.noise_floor);
ff37e337
S
316 }
317 }
318
1ffc1c61
JM
319 ath9k_ps_restore(sc);
320
20977d3e 321set_timer:
ff37e337
S
322 /*
323 * Set timer interval based on previous results.
324 * The interval must be the shortest necessary to satisfy ANI,
325 * short calibration and long calibration.
326 */
aac9207e 327 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 328 if (sc->sc_ah->config.enable_ani)
aac9207e 329 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
3d536acf 330 if (!common->ani.caldone)
20977d3e 331 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 332
3d536acf 333 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S
334}
335
3d536acf 336static void ath_start_ani(struct ath_common *common)
415f738e
S
337{
338 unsigned long timestamp = jiffies_to_msecs(jiffies);
339
3d536acf
LR
340 common->ani.longcal_timer = timestamp;
341 common->ani.shortcal_timer = timestamp;
342 common->ani.checkani_timer = timestamp;
415f738e 343
3d536acf 344 mod_timer(&common->ani.timer,
415f738e
S
345 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
346}
347
ff37e337
S
348/*
349 * Update tx/rx chainmask. For legacy association,
350 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT
351 * the chainmask configuration, for bt coexistence, use
352 * the chainmask configuration even in legacy mode.
ff37e337 353 */
0e2dedf9 354void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 355{
af03abec 356 struct ath_hw *ah = sc->sc_ah;
43c27613 357 struct ath_common *common = ath9k_hw_common(ah);
af03abec 358
3d832611 359 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
766ec4a9 360 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR
361 common->tx_chainmask = ah->caps.tx_chainmask;
362 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 363 } else {
43c27613
LR
364 common->tx_chainmask = 1;
365 common->rx_chainmask = 1;
ff37e337
S
366 }
367
43c27613 368 ath_print(common, ATH_DBG_CONFIG,
c46917bb 369 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR
370 common->tx_chainmask,
371 common->rx_chainmask);
ff37e337
S
372}
373
374static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
375{
376 struct ath_node *an;
377
378 an = (struct ath_node *)sta->drv_priv;
379
87792efc 380 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 381 ath_tx_node_init(sc, an);
9e98ac65 382 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
383 sta->ht_cap.ampdu_factor);
384 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 385 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 386 }
ff37e337
S
387}
388
389static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
390{
391 struct ath_node *an = (struct ath_node *)sta->drv_priv;
392
393 if (sc->sc_flags & SC_OP_TXAGGR)
394 ath_tx_node_cleanup(sc, an);
395}
396
55624204 397void ath9k_tasklet(unsigned long data)
ff37e337
S
398{
399 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 400 struct ath_hw *ah = sc->sc_ah;
c46917bb 401 struct ath_common *common = ath9k_hw_common(ah);
af03abec 402
17d7904d 403 u32 status = sc->intrstatus;
b5c80475 404 u32 rxmask;
ff37e337 405
153e080d
VT
406 ath9k_ps_wakeup(sc);
407
c9c99e5e
FF
408 if ((status & ATH9K_INT_FATAL) ||
409 !ath9k_hw_check_alive(ah)) {
ff37e337 410 ath_reset(sc, false);
153e080d 411 ath9k_ps_restore(sc);
ff37e337 412 return;
063d8be3 413 }
ff37e337 414
b5c80475
FF
415 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
416 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
417 ATH9K_INT_RXORN);
418 else
419 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
420
421 if (status & rxmask) {
063d8be3 422 spin_lock_bh(&sc->rx.rxflushlock);
b5c80475
FF
423
424 /* Check for high priority Rx first */
425 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
426 (status & ATH9K_INT_RXHP))
427 ath_rx_tasklet(sc, 0, true);
428
429 ath_rx_tasklet(sc, 0, false);
063d8be3 430 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S
431 }
432
e5003249
VT
433 if (status & ATH9K_INT_TX) {
434 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
435 ath_tx_edma_tasklet(sc);
436 else
437 ath_tx_tasklet(sc);
438 }
063d8be3 439
96148326 440 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
441 /*
442 * TSF sync does not look correct; remain awake to sync with
443 * the next Beacon.
444 */
c46917bb
LR
445 ath_print(common, ATH_DBG_PS,
446 "TSFOOR - Sync with next Beacon\n");
1b04b930 447 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
448 }
449
766ec4a9 450 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
451 if (status & ATH9K_INT_GENTIMER)
452 ath_gen_timer_isr(sc->sc_ah);
453
ff37e337 454 /* re-enable hardware interrupt */
3069168c 455 ath9k_hw_set_interrupts(ah, ah->imask);
153e080d 456 ath9k_ps_restore(sc);
ff37e337
S
457}
458
6baff7f9 459irqreturn_t ath_isr(int irq, void *dev)
ff37e337 460{
063d8be3
S
461#define SCHED_INTR ( \
462 ATH9K_INT_FATAL | \
463 ATH9K_INT_RXORN | \
464 ATH9K_INT_RXEOL | \
465 ATH9K_INT_RX | \
b5c80475
FF
466 ATH9K_INT_RXLP | \
467 ATH9K_INT_RXHP | \
063d8be3
S
468 ATH9K_INT_TX | \
469 ATH9K_INT_BMISS | \
470 ATH9K_INT_CST | \
ebb8e1d7
VT
471 ATH9K_INT_TSFOOR | \
472 ATH9K_INT_GENTIMER)
063d8be3 473
ff37e337 474 struct ath_softc *sc = dev;
cbe61d8a 475 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
476 enum ath9k_int status;
477 bool sched = false;
478
063d8be3
S
479 /*
480 * The hardware is not ready/present, don't
481 * touch anything. Note this can happen early
482 * on if the IRQ is shared.
483 */
484 if (sc->sc_flags & SC_OP_INVALID)
485 return IRQ_NONE;
ff37e337 486
063d8be3
S
487
488 /* shared irq, not for us */
489
153e080d 490 if (!ath9k_hw_intrpend(ah))
063d8be3 491 return IRQ_NONE;
063d8be3
S
492
493 /*
494 * Figure out the reason(s) for the interrupt. Note
495 * that the hal returns a pseudo-ISR that may include
496 * bits we haven't explicitly enabled so we mask the
497 * value to insure we only process bits we requested.
498 */
499 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 500 status &= ah->imask; /* discard unasked-for bits */
ff37e337 501
063d8be3
S
502 /*
503 * If there are no status bits set, then this interrupt was not
504 * for me (should have been caught above).
505 */
153e080d 506 if (!status)
063d8be3 507 return IRQ_NONE;
ff37e337 508
063d8be3
S
509 /* Cache the status */
510 sc->intrstatus = status;
511
512 if (status & SCHED_INTR)
513 sched = true;
514
515 /*
516 * If a FATAL or RXORN interrupt is received, we have to reset the
517 * chip immediately.
518 */
b5c80475
FF
519 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
520 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
521 goto chip_reset;
522
523 if (status & ATH9K_INT_SWBA)
524 tasklet_schedule(&sc->bcon_tasklet);
525
526 if (status & ATH9K_INT_TXURN)
527 ath9k_hw_updatetxtriglevel(ah, true);
528
b5c80475
FF
529 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
530 if (status & ATH9K_INT_RXEOL) {
531 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
532 ath9k_hw_set_interrupts(ah, ah->imask);
533 }
534 }
535
063d8be3 536 if (status & ATH9K_INT_MIB) {
ff37e337 537 /*
063d8be3
S
538 * Disable interrupts until we service the MIB
539 * interrupt; otherwise it will continue to
540 * fire.
ff37e337 541 */
063d8be3
S
542 ath9k_hw_set_interrupts(ah, 0);
543 /*
544 * Let the hal handle the event. We assume
545 * it will clear whatever condition caused
546 * the interrupt.
547 */
22e66a4c 548 ath9k_hw_procmibevent(ah);
3069168c 549 ath9k_hw_set_interrupts(ah, ah->imask);
063d8be3 550 }
ff37e337 551
153e080d
VT
552 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
553 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S
554 /* Clear RxAbort bit so that we can
555 * receive frames */
9ecdef4b 556 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 557 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 558 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 559 }
063d8be3
S
560
561chip_reset:
ff37e337 562
817e11de
S
563 ath_debug_stat_interrupt(sc, status);
564
ff37e337
S
565 if (sched) {
566 /* turn off every interrupt except SWBA */
3069168c 567 ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
ff37e337
S
568 tasklet_schedule(&sc->intr_tq);
569 }
570
571 return IRQ_HANDLED;
063d8be3
S
572
573#undef SCHED_INTR
ff37e337
S
574}
575
f078f209 576static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 577 struct ieee80211_channel *chan,
094d05dc 578 enum nl80211_channel_type channel_type)
f078f209
LR
579{
580 u32 chanmode = 0;
f078f209
LR
581
582 switch (chan->band) {
583 case IEEE80211_BAND_2GHZ:
094d05dc
S
584 switch(channel_type) {
585 case NL80211_CHAN_NO_HT:
586 case NL80211_CHAN_HT20:
f078f209 587 chanmode = CHANNEL_G_HT20;
094d05dc
S
588 break;
589 case NL80211_CHAN_HT40PLUS:
f078f209 590 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
591 break;
592 case NL80211_CHAN_HT40MINUS:
f078f209 593 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
594 break;
595 }
f078f209
LR
596 break;
597 case IEEE80211_BAND_5GHZ:
094d05dc
S
598 switch(channel_type) {
599 case NL80211_CHAN_NO_HT:
600 case NL80211_CHAN_HT20:
f078f209 601 chanmode = CHANNEL_A_HT20;
094d05dc
S
602 break;
603 case NL80211_CHAN_HT40PLUS:
f078f209 604 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
605 break;
606 case NL80211_CHAN_HT40MINUS:
f078f209 607 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
608 break;
609 }
f078f209
LR
610 break;
611 default:
612 break;
613 }
614
615 return chanmode;
616}
617
7e86c104 618static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
3f53dd64
JM
619 struct ath9k_keyval *hk, const u8 *addr,
620 bool authenticator)
f078f209 621{
7e86c104 622 struct ath_hw *ah = common->ah;
6ace2891
JM
623 const u8 *key_rxmic;
624 const u8 *key_txmic;
f078f209 625
6ace2891
JM
626 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
627 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR
628
629 if (addr == NULL) {
d216aaa6
JM
630 /*
631 * Group key installation - only two key cache entries are used
632 * regardless of splitmic capability since group key is only
633 * used either for TX or RX.
634 */
3f53dd64
JM
635 if (authenticator) {
636 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
637 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
638 } else {
639 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
640 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
641 }
7e86c104 642 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 643 }
7e86c104 644 if (!common->splitmic) {
d216aaa6 645 /* TX and RX keys share the same key cache entry. */
f078f209
LR
646 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
647 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
7e86c104 648 return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
f078f209 649 }
d216aaa6
JM
650
651 /* Separate key cache entries for TX and RX */
652
653 /* TX key goes at first index, RX key at +32. */
f078f209 654 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
7e86c104 655 if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
d216aaa6 656 /* TX MIC entry failed. No need to proceed further */
7e86c104 657 ath_print(common, ATH_DBG_FATAL,
c46917bb 658 "Setting TX MIC Key Failed\n");
f078f209
LR
659 return 0;
660 }
661
662 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
663 /* XXX delete tx key on failure? */
7e86c104 664 return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
6ace2891
JM
665}
666
7e86c104 667static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
6ace2891
JM
668{
669 int i;
670
7e86c104
LR
671 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
672 if (test_bit(i, common->keymap) ||
673 test_bit(i + 64, common->keymap))
6ace2891 674 continue; /* At least one part of TKIP key allocated */
7e86c104
LR
675 if (common->splitmic &&
676 (test_bit(i + 32, common->keymap) ||
677 test_bit(i + 64 + 32, common->keymap)))
6ace2891
JM
678 continue; /* At least one part of TKIP key allocated */
679
680 /* Found a free slot for a TKIP key */
681 return i;
682 }
683 return -1;
684}
685
7e86c104 686static int ath_reserve_key_cache_slot(struct ath_common *common)
6ace2891
JM
687{
688 int i;
689
690 /* First, try to find slots that would not be available for TKIP. */
7e86c104
LR
691 if (common->splitmic) {
692 for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
693 if (!test_bit(i, common->keymap) &&
694 (test_bit(i + 32, common->keymap) ||
695 test_bit(i + 64, common->keymap) ||
696 test_bit(i + 64 + 32, common->keymap)))
6ace2891 697 return i;
7e86c104
LR
698 if (!test_bit(i + 32, common->keymap) &&
699 (test_bit(i, common->keymap) ||
700 test_bit(i + 64, common->keymap) ||
701 test_bit(i + 64 + 32, common->keymap)))
6ace2891 702 return i + 32;
7e86c104
LR
703 if (!test_bit(i + 64, common->keymap) &&
704 (test_bit(i , common->keymap) ||
705 test_bit(i + 32, common->keymap) ||
706 test_bit(i + 64 + 32, common->keymap)))
ea612132 707 return i + 64;
7e86c104
LR
708 if (!test_bit(i + 64 + 32, common->keymap) &&
709 (test_bit(i, common->keymap) ||
710 test_bit(i + 32, common->keymap) ||
711 test_bit(i + 64, common->keymap)))
ea612132 712 return i + 64 + 32;
6ace2891
JM
713 }
714 } else {
7e86c104
LR
715 for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
716 if (!test_bit(i, common->keymap) &&
717 test_bit(i + 64, common->keymap))
6ace2891 718 return i;
7e86c104
LR
719 if (test_bit(i, common->keymap) &&
720 !test_bit(i + 64, common->keymap))
6ace2891
JM
721 return i + 64;
722 }
723 }
724
725 /* No partially used TKIP slots, pick any available slot */
7e86c104 726 for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
be2864cf
JM
727 /* Do not allow slots that could be needed for TKIP group keys
728 * to be used. This limitation could be removed if we know that
729 * TKIP will not be used. */
730 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
731 continue;
7e86c104 732 if (common->splitmic) {
be2864cf
JM
733 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
734 continue;
735 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
736 continue;
737 }
738
7e86c104 739 if (!test_bit(i, common->keymap))
6ace2891
JM
740 return i; /* Found a free slot for a key */
741 }
742
743 /* No free slot found */
744 return -1;
f078f209
LR
745}
746
7e86c104 747static int ath_key_config(struct ath_common *common,
3f53dd64 748 struct ieee80211_vif *vif,
dc822b5d 749 struct ieee80211_sta *sta,
f078f209
LR
750 struct ieee80211_key_conf *key)
751{
7e86c104 752 struct ath_hw *ah = common->ah;
f078f209
LR
753 struct ath9k_keyval hk;
754 const u8 *mac = NULL;
03ceedea 755 u8 gmac[ETH_ALEN];
f078f209 756 int ret = 0;
6ace2891 757 int idx;
f078f209
LR
758
759 memset(&hk, 0, sizeof(hk));
760
761 switch (key->alg) {
762 case ALG_WEP:
763 hk.kv_type = ATH9K_CIPHER_WEP;
764 break;
765 case ALG_TKIP:
766 hk.kv_type = ATH9K_CIPHER_TKIP;
767 break;
768 case ALG_CCMP:
769 hk.kv_type = ATH9K_CIPHER_AES_CCM;
770 break;
771 default:
ca470b29 772 return -EOPNOTSUPP;
f078f209
LR
773 }
774
6ace2891 775 hk.kv_len = key->keylen;
f078f209
LR
776 memcpy(hk.kv_val, key->key, key->keylen);
777
6ace2891 778 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
03ceedea
DYM
779
780 if (key->ap_addr) {
781 /*
782 * Group keys on hardware that supports multicast frame
783 * key search use a mac that is the sender's address with
784 * the high bit set instead of the app-specified address.
785 */
786 memcpy(gmac, key->ap_addr, ETH_ALEN);
787 gmac[0] |= 0x80;
788 mac = gmac;
789
790 if (key->alg == ALG_TKIP)
791 idx = ath_reserve_key_cache_slot_tkip(common);
792 else
793 idx = ath_reserve_key_cache_slot(common);
794 if (idx < 0)
795 mac = NULL; /* no free key cache entries */
796 }
797
798 if (!mac) {
799 /* For now, use the default keys for broadcast keys. This may
800 * need to change with virtual interfaces. */
801 idx = key->keyidx;
802 }
6ace2891 803 } else if (key->keyidx) {
dc822b5d
JB
804 if (WARN_ON(!sta))
805 return -EOPNOTSUPP;
806 mac = sta->addr;
807
6ace2891
JM
808 if (vif->type != NL80211_IFTYPE_AP) {
809 /* Only keyidx 0 should be used with unicast key, but
810 * allow this for client mode for now. */
811 idx = key->keyidx;
812 } else
813 return -EIO;
f078f209 814 } else {
dc822b5d
JB
815 if (WARN_ON(!sta))
816 return -EOPNOTSUPP;
817 mac = sta->addr;
818
6ace2891 819 if (key->alg == ALG_TKIP)
7e86c104 820 idx = ath_reserve_key_cache_slot_tkip(common);
6ace2891 821 else
7e86c104 822 idx = ath_reserve_key_cache_slot(common);
6ace2891 823 if (idx < 0)
ca470b29 824 return -ENOSPC; /* no free key cache entries */
f078f209
LR
825 }
826
827 if (key->alg == ALG_TKIP)
7e86c104 828 ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
3f53dd64 829 vif->type == NL80211_IFTYPE_AP);
f078f209 830 else
7e86c104 831 ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
f078f209
LR
832
833 if (!ret)
834 return -EIO;
835
7e86c104 836 set_bit(idx, common->keymap);
6ace2891 837 if (key->alg == ALG_TKIP) {
7e86c104
LR
838 set_bit(idx + 64, common->keymap);
839 if (common->splitmic) {
840 set_bit(idx + 32, common->keymap);
841 set_bit(idx + 64 + 32, common->keymap);
6ace2891
JM
842 }
843 }
844
845 return idx;
f078f209
LR
846}
847
7e86c104 848static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
f078f209 849{
7e86c104
LR
850 struct ath_hw *ah = common->ah;
851
852 ath9k_hw_keyreset(ah, key->hw_key_idx);
6ace2891
JM
853 if (key->hw_key_idx < IEEE80211_WEP_NKID)
854 return;
855
7e86c104 856 clear_bit(key->hw_key_idx, common->keymap);
6ace2891
JM
857 if (key->alg != ALG_TKIP)
858 return;
f078f209 859
7e86c104
LR
860 clear_bit(key->hw_key_idx + 64, common->keymap);
861 if (common->splitmic) {
733da37d 862 ath9k_hw_keyreset(ah, key->hw_key_idx + 32);
7e86c104
LR
863 clear_bit(key->hw_key_idx + 32, common->keymap);
864 clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
6ace2891 865 }
f078f209
LR
866}
867
8feceb67 868static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 869 struct ieee80211_vif *vif,
8feceb67 870 struct ieee80211_bss_conf *bss_conf)
f078f209 871{
f2b2143e 872 struct ath_hw *ah = sc->sc_ah;
1510718d 873 struct ath_common *common = ath9k_hw_common(ah);
f078f209 874
8feceb67 875 if (bss_conf->assoc) {
c46917bb
LR
876 ath_print(common, ATH_DBG_CONFIG,
877 "Bss Info ASSOC %d, bssid: %pM\n",
878 bss_conf->aid, common->curbssid);
f078f209 879
8feceb67 880 /* New association, store aid */
1510718d 881 common->curaid = bss_conf->aid;
f2b2143e 882 ath9k_hw_write_associd(ah);
2664f201
SB
883
884 /*
885 * Request a re-configuration of Beacon related timers
886 * on the receipt of the first Beacon frame (i.e.,
887 * after time sync with the AP).
888 */
1b04b930 889 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 890
8feceb67 891 /* Configure the beacon */
2c3db3d5 892 ath_beacon_config(sc, vif);
f078f209 893
8feceb67 894 /* Reset rssi stats */
22e66a4c 895 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 896
3d536acf 897 ath_start_ani(common);
8feceb67 898 } else {
c46917bb 899 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 900 common->curaid = 0;
f38faa31 901 /* Stop ANI */
3d536acf 902 del_timer_sync(&common->ani.timer);
f078f209 903 }
8feceb67 904}
f078f209 905
68a89116 906void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 907{
cbe61d8a 908 struct ath_hw *ah = sc->sc_ah;
c46917bb 909 struct ath_common *common = ath9k_hw_common(ah);
68a89116 910 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 911 int r;
500c064d 912
3cbb5dd7 913 ath9k_ps_wakeup(sc);
93b1b37f 914 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 915
159cd468
VT
916 if (!ah->curchan)
917 ah->curchan = ath_get_curchannel(sc, sc->hw);
918
d2f5b3a6 919 spin_lock_bh(&sc->sc_resetlock);
2660b81a 920 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 921 if (r) {
c46917bb 922 ath_print(common, ATH_DBG_FATAL,
f643e51d 923 "Unable to reset channel (%u MHz), "
c46917bb
LR
924 "reset status %d\n",
925 channel->center_freq, r);
500c064d
VT
926 }
927 spin_unlock_bh(&sc->sc_resetlock);
928
929 ath_update_txpow(sc);
930 if (ath_startrecv(sc) != 0) {
c46917bb
LR
931 ath_print(common, ATH_DBG_FATAL,
932 "Unable to restart recv logic\n");
500c064d
VT
933 return;
934 }
935
936 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 937 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
938
939 /* Re-Enable interrupts */
3069168c 940 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT
941
942 /* Enable LED */
08fc5c1b 943 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 944 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 945 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 946
68a89116 947 ieee80211_wake_queues(hw);
3cbb5dd7 948 ath9k_ps_restore(sc);
500c064d
VT
949}
950
68a89116 951void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 952{
cbe61d8a 953 struct ath_hw *ah = sc->sc_ah;
68a89116 954 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 955 int r;
500c064d 956
3cbb5dd7 957 ath9k_ps_wakeup(sc);
68a89116 958 ieee80211_stop_queues(hw);
500c064d
VT
959
960 /* Disable LED */
08fc5c1b
VN
961 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
962 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
500c064d
VT
963
964 /* Disable interrupts */
965 ath9k_hw_set_interrupts(ah, 0);
966
043a0405 967 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT
968 ath_stoprecv(sc); /* turn off frame recv */
969 ath_flushrecv(sc); /* flush recv queue */
970
159cd468 971 if (!ah->curchan)
68a89116 972 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 973
500c064d 974 spin_lock_bh(&sc->sc_resetlock);
2660b81a 975 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 976 if (r) {
c46917bb 977 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
f643e51d 978 "Unable to reset channel (%u MHz), "
c46917bb
LR
979 "reset status %d\n",
980 channel->center_freq, r);
500c064d
VT
981 }
982 spin_unlock_bh(&sc->sc_resetlock);
983
984 ath9k_hw_phy_disable(ah);
93b1b37f 985 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 986 ath9k_ps_restore(sc);
9ecdef4b 987 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT
988}
989
ff37e337
S
990int ath_reset(struct ath_softc *sc, bool retry_tx)
991{
cbe61d8a 992 struct ath_hw *ah = sc->sc_ah;
c46917bb 993 struct ath_common *common = ath9k_hw_common(ah);
030bb495 994 struct ieee80211_hw *hw = sc->hw;
ae8d2858 995 int r;
ff37e337 996
2ab81d4a
S
997 /* Stop ANI */
998 del_timer_sync(&common->ani.timer);
999
cc9c378a
S
1000 ieee80211_stop_queues(hw);
1001
ff37e337 1002 ath9k_hw_set_interrupts(ah, 0);
043a0405 1003 ath_drain_all_txq(sc, retry_tx);
ff37e337
S
1004 ath_stoprecv(sc);
1005 ath_flushrecv(sc);
1006
1007 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1008 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1009 if (r)
c46917bb
LR
1010 ath_print(common, ATH_DBG_FATAL,
1011 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
1012 spin_unlock_bh(&sc->sc_resetlock);
1013
1014 if (ath_startrecv(sc) != 0)
c46917bb
LR
1015 ath_print(common, ATH_DBG_FATAL,
1016 "Unable to start recv logic\n");
ff37e337
S
1017
1018 /*
1019 * We may be doing a reset in response to a request
1020 * that changes the channel so update any state that
1021 * might change as a result.
1022 */
ce111bad 1023 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
1024
1025 ath_update_txpow(sc);
1026
1027 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1028 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1029
3069168c 1030 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S
1031
1032 if (retry_tx) {
1033 int i;
1034 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1035 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
1036 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1037 ath_txq_schedule(sc, &sc->tx.txq[i]);
1038 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
1039 }
1040 }
1041 }
1042
cc9c378a
S
1043 ieee80211_wake_queues(hw);
1044
2ab81d4a
S
1045 /* Start ANI */
1046 ath_start_ani(common);
1047
ae8d2858 1048 return r;
ff37e337
S
1049}
1050
ff37e337
S
1051int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1052{
1053 int qnum;
1054
1055 switch (queue) {
1056 case 0:
b77f483f 1057 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S
1058 break;
1059 case 1:
b77f483f 1060 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S
1061 break;
1062 case 2:
b77f483f 1063 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S
1064 break;
1065 case 3:
b77f483f 1066 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S
1067 break;
1068 default:
b77f483f 1069 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S
1070 break;
1071 }
1072
1073 return qnum;
1074}
1075
1076int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1077{
1078 int qnum;
1079
1080 switch (queue) {
1081 case ATH9K_WME_AC_VO:
1082 qnum = 0;
1083 break;
1084 case ATH9K_WME_AC_VI:
1085 qnum = 1;
1086 break;
1087 case ATH9K_WME_AC_BE:
1088 qnum = 2;
1089 break;
1090 case ATH9K_WME_AC_BK:
1091 qnum = 3;
1092 break;
1093 default:
1094 qnum = -1;
1095 break;
1096 }
1097
1098 return qnum;
1099}
1100
5f8e077c
LR
1101/* XXX: Remove me once we don't depend on ath9k_channel for all
1102 * this redundant data */
0e2dedf9
JM
1103void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1104 struct ath9k_channel *ichan)
5f8e077c 1105{
5f8e077c
LR
1106 struct ieee80211_channel *chan = hw->conf.channel;
1107 struct ieee80211_conf *conf = &hw->conf;
1108
1109 ichan->channel = chan->center_freq;
1110 ichan->chan = chan;
1111
1112 if (chan->band == IEEE80211_BAND_2GHZ) {
1113 ichan->chanmode = CHANNEL_G;
8813262e 1114 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR
1115 } else {
1116 ichan->chanmode = CHANNEL_A;
1117 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1118 }
1119
25c56eec 1120 if (conf_is_ht(conf))
5f8e077c
LR
1121 ichan->chanmode = ath_get_extchanmode(sc, chan,
1122 conf->channel_type);
5f8e077c
LR
1123}
1124
ff37e337
S
1125/**********************/
1126/* mac80211 callbacks */
1127/**********************/
1128
8feceb67 1129static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1130{
bce048d7
JM
1131 struct ath_wiphy *aphy = hw->priv;
1132 struct ath_softc *sc = aphy->sc;
af03abec 1133 struct ath_hw *ah = sc->sc_ah;
c46917bb 1134 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1135 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1136 struct ath9k_channel *init_channel;
82880a7c 1137 int r;
f078f209 1138
c46917bb
LR
1139 ath_print(common, ATH_DBG_CONFIG,
1140 "Starting driver with initial channel: %d MHz\n",
1141 curchan->center_freq);
f078f209 1142
141b38b6
S
1143 mutex_lock(&sc->mutex);
1144
9580a222
JM
1145 if (ath9k_wiphy_started(sc)) {
1146 if (sc->chan_idx == curchan->hw_value) {
1147 /*
1148 * Already on the operational channel, the new wiphy
1149 * can be marked active.
1150 */
1151 aphy->state = ATH_WIPHY_ACTIVE;
1152 ieee80211_wake_queues(hw);
1153 } else {
1154 /*
1155 * Another wiphy is on another channel, start the new
1156 * wiphy in paused state.
1157 */
1158 aphy->state = ATH_WIPHY_PAUSED;
1159 ieee80211_stop_queues(hw);
1160 }
1161 mutex_unlock(&sc->mutex);
1162 return 0;
1163 }
1164 aphy->state = ATH_WIPHY_ACTIVE;
1165
8feceb67 1166 /* setup initial channel */
f078f209 1167
82880a7c 1168 sc->chan_idx = curchan->hw_value;
f078f209 1169
82880a7c 1170 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S
1171
1172 /* Reset SERDES registers */
af03abec 1173 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1174
1175 /*
1176 * The basic interface to setting the hardware in a good
1177 * state is ``reset''. On return the hardware is known to
1178 * be powered up and with interrupts disabled. This must
1179 * be followed by initialization of the appropriate bits
1180 * and then setup of the interrupt mask.
1181 */
1182 spin_lock_bh(&sc->sc_resetlock);
af03abec 1183 r = ath9k_hw_reset(ah, init_channel, false);
ae8d2858 1184 if (r) {
c46917bb
LR
1185 ath_print(common, ATH_DBG_FATAL,
1186 "Unable to reset hardware; reset status %d "
1187 "(freq %u MHz)\n", r,
1188 curchan->center_freq);
ff37e337 1189 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1190 goto mutex_unlock;
ff37e337
S
1191 }
1192 spin_unlock_bh(&sc->sc_resetlock);
1193
1194 /*
1195 * This is needed only to setup initial state
1196 * but it's best done after a reset.
1197 */
1198 ath_update_txpow(sc);
8feceb67 1199
ff37e337
S
1200 /*
1201 * Setup the hardware after reset:
1202 * The receive engine is set going.
1203 * Frame transmit is handled entirely
1204 * in the frame output path; there's nothing to do
1205 * here except setup the interrupt mask.
1206 */
1207 if (ath_startrecv(sc) != 0) {
c46917bb
LR
1208 ath_print(common, ATH_DBG_FATAL,
1209 "Unable to start recv logic\n");
141b38b6
S
1210 r = -EIO;
1211 goto mutex_unlock;
f078f209 1212 }
8feceb67 1213
ff37e337 1214 /* Setup our intr mask. */
b5c80475
FF
1215 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1216 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1217 ATH9K_INT_GLOBAL;
1218
1219 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
1220 ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
1221 else
1222 ah->imask |= ATH9K_INT_RX;
ff37e337 1223
af03abec 1224 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
3069168c 1225 ah->imask |= ATH9K_INT_GTT;
ff37e337 1226
af03abec 1227 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1228 ah->imask |= ATH9K_INT_CST;
ff37e337 1229
ce111bad 1230 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
1231
1232 sc->sc_flags &= ~SC_OP_INVALID;
1233
1234 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1235 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1236 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1237
bce048d7 1238 ieee80211_wake_queues(hw);
ff37e337 1239
42935eca 1240 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1241
766ec4a9
LR
1242 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1243 !ah->btcoex_hw.enabled) {
5e197292
LR
1244 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1245 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1246 ath9k_hw_btcoex_enable(ah);
f985ad12 1247
5bb12791
LR
1248 if (common->bus_ops->bt_coex_prep)
1249 common->bus_ops->bt_coex_prep(common);
766ec4a9 1250 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1251 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1252 }
1253
141b38b6
S
1254mutex_unlock:
1255 mutex_unlock(&sc->mutex);
1256
ae8d2858 1257 return r;
f078f209
LR
1258}
1259
8feceb67
VT
1260static int ath9k_tx(struct ieee80211_hw *hw,
1261 struct sk_buff *skb)
f078f209 1262{
528f0c6b 1263 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM
1264 struct ath_wiphy *aphy = hw->priv;
1265 struct ath_softc *sc = aphy->sc;
c46917bb 1266 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1267 struct ath_tx_control txctl;
1bc14880
BP
1268 int padpos, padsize;
1269 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
528f0c6b 1270
8089cc47 1271 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR
1272 ath_print(common, ATH_DBG_XMIT,
1273 "ath9k: %s: TX in unexpected wiphy state "
1274 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM
1275 goto exit;
1276 }
1277
96148326 1278 if (sc->ps_enabled) {
dc8c4585
JM
1279 /*
1280 * mac80211 does not set PM field for normal data frames, so we
1281 * need to update that based on the current PS mode.
1282 */
1283 if (ieee80211_is_data(hdr->frame_control) &&
1284 !ieee80211_is_nullfunc(hdr->frame_control) &&
1285 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR
1286 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
1287 "while in PS mode\n");
dc8c4585
JM
1288 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1289 }
1290 }
1291
9a23f9ca
JM
1292 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1293 /*
1294 * We are using PS-Poll and mac80211 can request TX while in
1295 * power save mode. Need to wake up hardware for the TX to be
1296 * completed and if needed, also for RX of buffered frames.
1297 */
9a23f9ca
JM
1298 ath9k_ps_wakeup(sc);
1299 ath9k_hw_setrxabort(sc->sc_ah, 0);
1300 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR
1301 ath_print(common, ATH_DBG_PS,
1302 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1303 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1304 } else {
c46917bb
LR
1305 ath_print(common, ATH_DBG_PS,
1306 "Wake up to complete TX\n");
1b04b930 1307 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1308 }
1309 /*
1310 * The actual restore operation will happen only after
1311 * the sc_flags bit is cleared. We are just dropping
1312 * the ps_usecount here.
1313 */
1314 ath9k_ps_restore(sc);
1315 }
1316
528f0c6b 1317 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1318
8feceb67
VT
1319 /*
1320 * As a temporary workaround, assign seq# here; this will likely need
1321 * to be cleaned up to work better with Beacon transmission and virtual
1322 * BSSes.
1323 */
1324 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
8feceb67 1325 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1326 sc->tx.seq_no += 0x10;
8feceb67 1327 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1328 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1329 }
f078f209 1330
8feceb67 1331 /* Add the padding after the header if this is not already done */
1bc14880
BP
1332 padpos = ath9k_cmn_padpos(hdr->frame_control);
1333 padsize = padpos & 3;
1334 if (padsize && skb->len>padpos) {
8feceb67
VT
1335 if (skb_headroom(skb) < padsize)
1336 return -1;
1337 skb_push(skb, padsize);
1bc14880 1338 memmove(skb->data, skb->data + padsize, padpos);
8feceb67
VT
1339 }
1340
528f0c6b
S
1341 /* Check if a tx queue is available */
1342
1343 txctl.txq = ath_test_get_txq(sc, skb);
1344 if (!txctl.txq)
1345 goto exit;
1346
c46917bb 1347 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1348
c52f33d0 1349 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 1350 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1351 goto exit;
8feceb67
VT
1352 }
1353
528f0c6b
S
1354 return 0;
1355exit:
1356 dev_kfree_skb_any(skb);
8feceb67 1357 return 0;
f078f209
LR
1358}
1359
8feceb67 1360static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1361{
bce048d7
JM
1362 struct ath_wiphy *aphy = hw->priv;
1363 struct ath_softc *sc = aphy->sc;
af03abec 1364 struct ath_hw *ah = sc->sc_ah;
c46917bb 1365 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1366
4c483817
S
1367 mutex_lock(&sc->mutex);
1368
9580a222
JM
1369 aphy->state = ATH_WIPHY_INACTIVE;
1370
c94dbff7
LR
1371 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1372 cancel_delayed_work_sync(&sc->tx_complete_work);
1373
1374 if (!sc->num_sec_wiphy) {
1375 cancel_delayed_work_sync(&sc->wiphy_work);
1376 cancel_work_sync(&sc->chan_work);
1377 }
1378
9c84b797 1379 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 1380 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1381 mutex_unlock(&sc->mutex);
9c84b797
S
1382 return;
1383 }
8feceb67 1384
9580a222
JM
1385 if (ath9k_wiphy_started(sc)) {
1386 mutex_unlock(&sc->mutex);
1387 return; /* another wiphy still in use */
1388 }
1389
3867cf6a
S
1390 /* Ensure HW is awake when we try to shut it down. */
1391 ath9k_ps_wakeup(sc);
1392
766ec4a9 1393 if (ah->btcoex_hw.enabled) {
af03abec 1394 ath9k_hw_btcoex_disable(ah);
766ec4a9 1395 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1396 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1397 }
1398
ff37e337
S
1399 /* make sure h/w will not generate any interrupt
1400 * before setting the invalid flag. */
af03abec 1401 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S
1402
1403 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1404 ath_drain_all_txq(sc, false);
ff37e337 1405 ath_stoprecv(sc);
af03abec 1406 ath9k_hw_phy_disable(ah);
ff37e337 1407 } else
b77f483f 1408 sc->rx.rxlink = NULL;
ff37e337 1409
ff37e337 1410 /* disable HAL and put h/w to sleep */
af03abec
LR
1411 ath9k_hw_disable(ah);
1412 ath9k_hw_configpcipowersave(ah, 1, 1);
3867cf6a
S
1413 ath9k_ps_restore(sc);
1414
1415 /* Finally, put the chip in FULL SLEEP mode */
9ecdef4b 1416 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S
1417
1418 sc->sc_flags |= SC_OP_INVALID;
500c064d 1419
141b38b6
S
1420 mutex_unlock(&sc->mutex);
1421
c46917bb 1422 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1423}
1424
8feceb67 1425static int ath9k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 1426 struct ieee80211_vif *vif)
f078f209 1427{
bce048d7
JM
1428 struct ath_wiphy *aphy = hw->priv;
1429 struct ath_softc *sc = aphy->sc;
3069168c
PR
1430 struct ath_hw *ah = sc->sc_ah;
1431 struct ath_common *common = ath9k_hw_common(ah);
1ed32e4f 1432 struct ath_vif *avp = (void *)vif->drv_priv;
d97809db 1433 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 1434 int ret = 0;
8feceb67 1435
141b38b6
S
1436 mutex_lock(&sc->mutex);
1437
3069168c 1438 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
8ca21f01
JM
1439 sc->nvifs > 0) {
1440 ret = -ENOBUFS;
1441 goto out;
1442 }
1443
1ed32e4f 1444 switch (vif->type) {
05c914fe 1445 case NL80211_IFTYPE_STATION:
d97809db 1446 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 1447 break;
05c914fe 1448 case NL80211_IFTYPE_ADHOC:
05c914fe 1449 case NL80211_IFTYPE_AP:
9cb5412b 1450 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM
1451 if (sc->nbcnvifs >= ATH_BCBUF) {
1452 ret = -ENOBUFS;
1453 goto out;
1454 }
1ed32e4f 1455 ic_opmode = vif->type;
f078f209
LR
1456 break;
1457 default:
c46917bb 1458 ath_print(common, ATH_DBG_FATAL,
1ed32e4f 1459 "Interface type %d not yet supported\n", vif->type);
2c3db3d5
JM
1460 ret = -EOPNOTSUPP;
1461 goto out;
f078f209
LR
1462 }
1463
c46917bb
LR
1464 ath_print(common, ATH_DBG_CONFIG,
1465 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 1466
17d7904d 1467 /* Set the VIF opmode */
5640b08e
S
1468 avp->av_opmode = ic_opmode;
1469 avp->av_bslot = -1;
1470
2c3db3d5 1471 sc->nvifs++;
8ca21f01 1472
3069168c 1473 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
8ca21f01
JM
1474 ath9k_set_bssid_mask(hw);
1475
2c3db3d5
JM
1476 if (sc->nvifs > 1)
1477 goto out; /* skip global settings for secondary vif */
1478
b238e90e 1479 if (ic_opmode == NL80211_IFTYPE_AP) {
3069168c 1480 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e
S
1481 sc->sc_flags |= SC_OP_TSF_RESET;
1482 }
5640b08e 1483
5640b08e 1484 /* Set the device opmode */
3069168c 1485 ah->opmode = ic_opmode;
5640b08e 1486
4e30ffa2
VN
1487 /*
1488 * Enable MIB interrupts when there are hardware phy counters.
1489 * Note we only do this (at the moment) for station mode.
1490 */
1ed32e4f
JB
1491 if ((vif->type == NL80211_IFTYPE_STATION) ||
1492 (vif->type == NL80211_IFTYPE_ADHOC) ||
1493 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
3448f912
LR
1494 if (ah->config.enable_ani)
1495 ah->imask |= ATH9K_INT_MIB;
3069168c 1496 ah->imask |= ATH9K_INT_TSFOOR;
4af9cf4f
S
1497 }
1498
3069168c 1499 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1500
1ed32e4f
JB
1501 if (vif->type == NL80211_IFTYPE_AP ||
1502 vif->type == NL80211_IFTYPE_ADHOC ||
1503 vif->type == NL80211_IFTYPE_MONITOR)
3d536acf 1504 ath_start_ani(common);
6f255425 1505
2c3db3d5 1506out:
141b38b6 1507 mutex_unlock(&sc->mutex);
2c3db3d5 1508 return ret;
f078f209
LR
1509}
1510
8feceb67 1511static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1512 struct ieee80211_vif *vif)
f078f209 1513{
bce048d7
JM
1514 struct ath_wiphy *aphy = hw->priv;
1515 struct ath_softc *sc = aphy->sc;
c46917bb 1516 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1517 struct ath_vif *avp = (void *)vif->drv_priv;
2c3db3d5 1518 int i;
f078f209 1519
c46917bb 1520 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1521
141b38b6
S
1522 mutex_lock(&sc->mutex);
1523
6f255425 1524 /* Stop ANI */
3d536acf 1525 del_timer_sync(&common->ani.timer);
580f0b8a 1526
8feceb67 1527 /* Reclaim beacon resources */
9cb5412b
PE
1528 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1529 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1530 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
5f70a88f 1531 ath9k_ps_wakeup(sc);
b77f483f 1532 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
5f70a88f 1533 ath9k_ps_restore(sc);
580f0b8a 1534 }
f078f209 1535
74401773 1536 ath_beacon_return(sc, avp);
8feceb67 1537 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1538
2c3db3d5 1539 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1ed32e4f 1540 if (sc->beacon.bslot[i] == vif) {
2c3db3d5
JM
1541 printk(KERN_DEBUG "%s: vif had allocated beacon "
1542 "slot\n", __func__);
1543 sc->beacon.bslot[i] = NULL;
c52f33d0 1544 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM
1545 }
1546 }
1547
17d7904d 1548 sc->nvifs--;
141b38b6
S
1549
1550 mutex_unlock(&sc->mutex);
f078f209
LR
1551}
1552
3f7c5c10
SB
1553void ath9k_enable_ps(struct ath_softc *sc)
1554{
3069168c
PR
1555 struct ath_hw *ah = sc->sc_ah;
1556
3f7c5c10 1557 sc->ps_enabled = true;
3069168c
PR
1558 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1559 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1560 ah->imask |= ATH9K_INT_TIM_TIMER;
1561 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10
SB
1562 }
1563 }
3069168c 1564 ath9k_hw_setrxabort(ah, 1);
3f7c5c10
SB
1565}
1566
e8975581 1567static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1568{
bce048d7
JM
1569 struct ath_wiphy *aphy = hw->priv;
1570 struct ath_softc *sc = aphy->sc;
c46917bb 1571 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 1572 struct ieee80211_conf *conf = &hw->conf;
8782b41d 1573 struct ath_hw *ah = sc->sc_ah;
194b7c13 1574 bool disable_radio;
f078f209 1575
aa33de09 1576 mutex_lock(&sc->mutex);
141b38b6 1577
194b7c13
LR
1578 /*
1579 * Leave this as the first check because we need to turn on the
1580 * radio if it was disabled before prior to processing the rest
1581 * of the changes. Likewise we must only disable the radio towards
1582 * the end.
1583 */
64839170 1584 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR
1585 bool enable_radio;
1586 bool all_wiphys_idle;
1587 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR
1588
1589 spin_lock_bh(&sc->wiphy_lock);
1590 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR
1591 ath9k_set_wiphy_idle(aphy, idle);
1592
11446011 1593 enable_radio = (!idle && all_wiphys_idle);
194b7c13
LR
1594
1595 /*
1596 * After we unlock here its possible another wiphy
1597 * can be re-renabled so to account for that we will
1598 * only disable the radio toward the end of this routine
1599 * if by then all wiphys are still idle.
1600 */
64839170
LR
1601 spin_unlock_bh(&sc->wiphy_lock);
1602
194b7c13 1603 if (enable_radio) {
1dbfd9d4 1604 sc->ps_idle = false;
68a89116 1605 ath_radio_enable(sc, hw);
c46917bb
LR
1606 ath_print(common, ATH_DBG_CONFIG,
1607 "not-idle: enabling radio\n");
64839170
LR
1608 }
1609 }
1610
e7824a50
LR
1611 /*
1612 * We just prepare to enable PS. We have to wait until our AP has
1613 * ACK'd our null data frame to disable RX otherwise we'll ignore
1614 * those ACKs and end up retransmitting the same null data frames.
1615 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1616 */
3cbb5dd7
VN
1617 if (changed & IEEE80211_CONF_CHANGE_PS) {
1618 if (conf->flags & IEEE80211_CONF_PS) {
1b04b930 1619 sc->ps_flags |= PS_ENABLED;
e7824a50
LR
1620 /*
1621 * At this point we know hardware has received an ACK
1622 * of a previously sent null data frame.
1623 */
1b04b930
S
1624 if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
1625 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
3f7c5c10 1626 ath9k_enable_ps(sc);
e7824a50 1627 }
3cbb5dd7 1628 } else {
96148326 1629 sc->ps_enabled = false;
1b04b930
S
1630 sc->ps_flags &= ~(PS_ENABLED |
1631 PS_NULLFUNC_COMPLETED);
9ecdef4b 1632 ath9k_setpower(sc, ATH9K_PM_AWAKE);
8782b41d
VN
1633 if (!(ah->caps.hw_caps &
1634 ATH9K_HW_CAP_AUTOSLEEP)) {
1635 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930
S
1636 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1637 PS_WAIT_FOR_CAB |
1638 PS_WAIT_FOR_PSPOLL_DATA |
1639 PS_WAIT_FOR_TX_ACK);
3069168c
PR
1640 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1641 ah->imask &= ~ATH9K_INT_TIM_TIMER;
8782b41d 1642 ath9k_hw_set_interrupts(sc->sc_ah,
3069168c 1643 ah->imask);
8782b41d 1644 }
3cbb5dd7
VN
1645 }
1646 }
1647 }
1648
199afd9d
S
1649 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1650 if (conf->flags & IEEE80211_CONF_MONITOR) {
1651 ath_print(common, ATH_DBG_CONFIG,
1652 "HW opmode set to Monitor mode\n");
1653 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1654 }
1655 }
1656
4797938c 1657 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1658 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1659 int pos = curchan->hw_value;
ae5eb026 1660
0e2dedf9
JM
1661 aphy->chan_idx = pos;
1662 aphy->chan_is_ht = conf_is_ht(conf);
1663
8089cc47
JM
1664 if (aphy->state == ATH_WIPHY_SCAN ||
1665 aphy->state == ATH_WIPHY_ACTIVE)
1666 ath9k_wiphy_pause_all_forced(sc, aphy);
1667 else {
1668 /*
1669 * Do not change operational channel based on a paused
1670 * wiphy changes.
1671 */
1672 goto skip_chan_change;
1673 }
0e2dedf9 1674
c46917bb
LR
1675 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1676 curchan->center_freq);
f078f209 1677
5f8e077c 1678 /* XXX: remove me eventualy */
0e2dedf9 1679 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1680
ecf70441 1681 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 1682
0e2dedf9 1683 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR
1684 ath_print(common, ATH_DBG_FATAL,
1685 "Unable to set channel\n");
aa33de09 1686 mutex_unlock(&sc->mutex);
e11602b7
S
1687 return -EINVAL;
1688 }
094d05dc 1689 }
f078f209 1690
8089cc47 1691skip_chan_change:
c9f6a656 1692 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1693 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR
1694 ath_update_txpow(sc);
1695 }
f078f209 1696
194b7c13
LR
1697 spin_lock_bh(&sc->wiphy_lock);
1698 disable_radio = ath9k_all_wiphys_idle(sc);
1699 spin_unlock_bh(&sc->wiphy_lock);
1700
64839170 1701 if (disable_radio) {
c46917bb 1702 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1703 sc->ps_idle = true;
68a89116 1704 ath_radio_disable(sc, hw);
64839170
LR
1705 }
1706
aa33de09 1707 mutex_unlock(&sc->mutex);
141b38b6 1708
f078f209
LR
1709 return 0;
1710}
1711
8feceb67
VT
1712#define SUPPORTED_FILTERS \
1713 (FIF_PROMISC_IN_BSS | \
1714 FIF_ALLMULTI | \
1715 FIF_CONTROL | \
af6a3fc7 1716 FIF_PSPOLL | \
8feceb67
VT
1717 FIF_OTHER_BSS | \
1718 FIF_BCN_PRBRESP_PROMISC | \
1719 FIF_FCSFAIL)
c83be688 1720
8feceb67
VT
1721/* FIXME: sc->sc_full_reset ? */
1722static void ath9k_configure_filter(struct ieee80211_hw *hw,
1723 unsigned int changed_flags,
1724 unsigned int *total_flags,
3ac64bee 1725 u64 multicast)
8feceb67 1726{
bce048d7
JM
1727 struct ath_wiphy *aphy = hw->priv;
1728 struct ath_softc *sc = aphy->sc;
8feceb67 1729 u32 rfilt;
f078f209 1730
8feceb67
VT
1731 changed_flags &= SUPPORTED_FILTERS;
1732 *total_flags &= SUPPORTED_FILTERS;
f078f209 1733
b77f483f 1734 sc->rx.rxfilter = *total_flags;
aa68aeaa 1735 ath9k_ps_wakeup(sc);
8feceb67
VT
1736 rfilt = ath_calcrxfilter(sc);
1737 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1738 ath9k_ps_restore(sc);
f078f209 1739
c46917bb
LR
1740 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1741 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1742}
f078f209 1743
4ca77860
JB
1744static int ath9k_sta_add(struct ieee80211_hw *hw,
1745 struct ieee80211_vif *vif,
1746 struct ieee80211_sta *sta)
8feceb67 1747{
bce048d7
JM
1748 struct ath_wiphy *aphy = hw->priv;
1749 struct ath_softc *sc = aphy->sc;
f078f209 1750
4ca77860
JB
1751 ath_node_attach(sc, sta);
1752
1753 return 0;
1754}
1755
1756static int ath9k_sta_remove(struct ieee80211_hw *hw,
1757 struct ieee80211_vif *vif,
1758 struct ieee80211_sta *sta)
1759{
1760 struct ath_wiphy *aphy = hw->priv;
1761 struct ath_softc *sc = aphy->sc;
1762
1763 ath_node_detach(sc, sta);
1764
1765 return 0;
f078f209
LR
1766}
1767
141b38b6 1768static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1769 const struct ieee80211_tx_queue_params *params)
f078f209 1770{
bce048d7
JM
1771 struct ath_wiphy *aphy = hw->priv;
1772 struct ath_softc *sc = aphy->sc;
c46917bb 1773 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT
1774 struct ath9k_tx_queue_info qi;
1775 int ret = 0, qnum;
f078f209 1776
8feceb67
VT
1777 if (queue >= WME_NUM_AC)
1778 return 0;
f078f209 1779
141b38b6
S
1780 mutex_lock(&sc->mutex);
1781
1ffb0610
S
1782 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1783
8feceb67
VT
1784 qi.tqi_aifs = params->aifs;
1785 qi.tqi_cwmin = params->cw_min;
1786 qi.tqi_cwmax = params->cw_max;
1787 qi.tqi_burstTime = params->txop;
1788 qnum = ath_get_hal_qnum(queue, sc);
f078f209 1789
c46917bb
LR
1790 ath_print(common, ATH_DBG_CONFIG,
1791 "Configure tx [queue/halq] [%d/%d], "
1792 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1793 queue, qnum, params->aifs, params->cw_min,
1794 params->cw_max, params->txop);
f078f209 1795
8feceb67
VT
1796 ret = ath_txq_update(sc, qnum, &qi);
1797 if (ret)
c46917bb 1798 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 1799
94db2936
VN
1800 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1801 if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
1802 ath_beaconq_config(sc);
1803
141b38b6
S
1804 mutex_unlock(&sc->mutex);
1805
8feceb67
VT
1806 return ret;
1807}
f078f209 1808
8feceb67
VT
1809static int ath9k_set_key(struct ieee80211_hw *hw,
1810 enum set_key_cmd cmd,
dc822b5d
JB
1811 struct ieee80211_vif *vif,
1812 struct ieee80211_sta *sta,
8feceb67
VT
1813 struct ieee80211_key_conf *key)
1814{
bce048d7
JM
1815 struct ath_wiphy *aphy = hw->priv;
1816 struct ath_softc *sc = aphy->sc;
c46917bb 1817 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1818 int ret = 0;
f078f209 1819
b3bd89ce
JM
1820 if (modparam_nohwcrypt)
1821 return -ENOSPC;
1822
141b38b6 1823 mutex_lock(&sc->mutex);
3cbb5dd7 1824 ath9k_ps_wakeup(sc);
c46917bb 1825 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1826
8feceb67
VT
1827 switch (cmd) {
1828 case SET_KEY:
7e86c104 1829 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1830 if (ret >= 0) {
1831 key->hw_key_idx = ret;
8feceb67
VT
1832 /* push IV and Michael MIC generation to stack */
1833 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1834 if (key->alg == ALG_TKIP)
1835 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM
1836 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
1837 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1838 ret = 0;
8feceb67
VT
1839 }
1840 break;
1841 case DISABLE_KEY:
7e86c104 1842 ath_key_delete(common, key);
8feceb67
VT
1843 break;
1844 default:
1845 ret = -EINVAL;
1846 }
f078f209 1847
3cbb5dd7 1848 ath9k_ps_restore(sc);
141b38b6
S
1849 mutex_unlock(&sc->mutex);
1850
8feceb67
VT
1851 return ret;
1852}
f078f209 1853
8feceb67
VT
1854static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1855 struct ieee80211_vif *vif,
1856 struct ieee80211_bss_conf *bss_conf,
1857 u32 changed)
1858{
bce048d7
JM
1859 struct ath_wiphy *aphy = hw->priv;
1860 struct ath_softc *sc = aphy->sc;
2d0ddec5 1861 struct ath_hw *ah = sc->sc_ah;
1510718d 1862 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1863 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1864 int slottime;
c6089ccc 1865 int error;
f078f209 1866
141b38b6
S
1867 mutex_lock(&sc->mutex);
1868
c6089ccc
S
1869 if (changed & BSS_CHANGED_BSSID) {
1870 /* Set BSSID */
1871 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1872 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 1873 common->curaid = 0;
f2b2143e 1874 ath9k_hw_write_associd(ah);
2d0ddec5 1875
c6089ccc
S
1876 /* Set aggregation protection mode parameters */
1877 sc->config.ath_aggr_prot = 0;
2d0ddec5 1878
c6089ccc
S
1879 /* Only legacy IBSS for now */
1880 if (vif->type == NL80211_IFTYPE_ADHOC)
1881 ath_update_chainmask(sc, 0);
2d0ddec5 1882
c6089ccc
S
1883 ath_print(common, ATH_DBG_CONFIG,
1884 "BSSID: %pM aid: 0x%x\n",
1885 common->curbssid, common->curaid);
2d0ddec5 1886
c6089ccc
S
1887 /* need to reconfigure the beacon */
1888 sc->sc_flags &= ~SC_OP_BEACONS ;
1889 }
2d0ddec5 1890
c6089ccc
S
1891 /* Enable transmission of beacons (AP, IBSS, MESH) */
1892 if ((changed & BSS_CHANGED_BEACON) ||
1893 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1894 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1895 error = ath_beacon_alloc(aphy, vif);
1896 if (!error)
1897 ath_beacon_config(sc, vif);
0005baf4
FF
1898 }
1899
1900 if (changed & BSS_CHANGED_ERP_SLOT) {
1901 if (bss_conf->use_short_slot)
1902 slottime = 9;
1903 else
1904 slottime = 20;
1905 if (vif->type == NL80211_IFTYPE_AP) {
1906 /*
1907 * Defer update, so that connected stations can adjust
1908 * their settings at the same time.
1909 * See beacon.c for more details
1910 */
1911 sc->beacon.slottime = slottime;
1912 sc->beacon.updateslot = UPDATE;
1913 } else {
1914 ah->slottime = slottime;
1915 ath9k_hw_init_global_settings(ah);
1916 }
2d0ddec5
JB
1917 }
1918
c6089ccc
S
1919 /* Disable transmission of beacons */
1920 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1921 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 1922
c6089ccc
S
1923 if (changed & BSS_CHANGED_BEACON_INT) {
1924 sc->beacon_interval = bss_conf->beacon_int;
1925 /*
1926 * In case of AP mode, the HW TSF has to be reset
1927 * when the beacon interval changes.
1928 */
1929 if (vif->type == NL80211_IFTYPE_AP) {
1930 sc->sc_flags |= SC_OP_TSF_RESET;
1931 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB
1932 error = ath_beacon_alloc(aphy, vif);
1933 if (!error)
1934 ath_beacon_config(sc, vif);
c6089ccc
S
1935 } else {
1936 ath_beacon_config(sc, vif);
2d0ddec5
JB
1937 }
1938 }
1939
8feceb67 1940 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR
1941 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1942 bss_conf->use_short_preamble);
8feceb67
VT
1943 if (bss_conf->use_short_preamble)
1944 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1945 else
1946 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1947 }
f078f209 1948
8feceb67 1949 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR
1950 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1951 bss_conf->use_cts_prot);
8feceb67
VT
1952 if (bss_conf->use_cts_prot &&
1953 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1954 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1955 else
1956 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1957 }
f078f209 1958
8feceb67 1959 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 1960 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 1961 bss_conf->assoc);
5640b08e 1962 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 1963 }
141b38b6
S
1964
1965 mutex_unlock(&sc->mutex);
8feceb67 1966}
f078f209 1967
8feceb67
VT
1968static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1969{
1970 u64 tsf;
bce048d7
JM
1971 struct ath_wiphy *aphy = hw->priv;
1972 struct ath_softc *sc = aphy->sc;
f078f209 1973
141b38b6
S
1974 mutex_lock(&sc->mutex);
1975 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1976 mutex_unlock(&sc->mutex);
f078f209 1977
8feceb67
VT
1978 return tsf;
1979}
f078f209 1980
3b5d665b
AF
1981static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
1982{
bce048d7
JM
1983 struct ath_wiphy *aphy = hw->priv;
1984 struct ath_softc *sc = aphy->sc;
3b5d665b 1985
141b38b6
S
1986 mutex_lock(&sc->mutex);
1987 ath9k_hw_settsf64(sc->sc_ah, tsf);
1988 mutex_unlock(&sc->mutex);
3b5d665b
AF
1989}
1990
8feceb67
VT
1991static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1992{
bce048d7
JM
1993 struct ath_wiphy *aphy = hw->priv;
1994 struct ath_softc *sc = aphy->sc;
c83be688 1995
141b38b6 1996 mutex_lock(&sc->mutex);
21526d57
LR
1997
1998 ath9k_ps_wakeup(sc);
141b38b6 1999 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
2000 ath9k_ps_restore(sc);
2001
141b38b6 2002 mutex_unlock(&sc->mutex);
8feceb67 2003}
f078f209 2004
8feceb67 2005static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 2006 struct ieee80211_vif *vif,
141b38b6
S
2007 enum ieee80211_ampdu_mlme_action action,
2008 struct ieee80211_sta *sta,
2009 u16 tid, u16 *ssn)
8feceb67 2010{
bce048d7
JM
2011 struct ath_wiphy *aphy = hw->priv;
2012 struct ath_softc *sc = aphy->sc;
8feceb67 2013 int ret = 0;
f078f209 2014
8feceb67
VT
2015 switch (action) {
2016 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
2017 if (!(sc->sc_flags & SC_OP_RXAGGR))
2018 ret = -ENOTSUPP;
8feceb67
VT
2019 break;
2020 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
2021 break;
2022 case IEEE80211_AMPDU_TX_START:
8b685ba9 2023 ath9k_ps_wakeup(sc);
f83da965 2024 ath_tx_aggr_start(sc, sta, tid, ssn);
c951ad35 2025 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2026 ath9k_ps_restore(sc);
8feceb67
VT
2027 break;
2028 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 2029 ath9k_ps_wakeup(sc);
f83da965 2030 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 2031 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 2032 ath9k_ps_restore(sc);
8feceb67 2033 break;
b1720231 2034 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 2035 ath9k_ps_wakeup(sc);
8469cdef 2036 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 2037 ath9k_ps_restore(sc);
8469cdef 2038 break;
8feceb67 2039 default:
c46917bb
LR
2040 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
2041 "Unknown AMPDU action\n");
8feceb67
VT
2042 }
2043
2044 return ret;
f078f209
LR
2045}
2046
62dad5b0
BP
2047static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2048 struct survey_info *survey)
2049{
2050 struct ath_wiphy *aphy = hw->priv;
2051 struct ath_softc *sc = aphy->sc;
2052 struct ath_hw *ah = sc->sc_ah;
2053 struct ath_common *common = ath9k_hw_common(ah);
2054 struct ieee80211_conf *conf = &hw->conf;
2055
2056 if (idx != 0)
2057 return -ENOENT;
2058
2059 survey->channel = conf->channel;
2060 survey->filled = SURVEY_INFO_NOISE_DBM;
2061 survey->noise = common->ani.noise_floor;
2062
2063 return 0;
2064}
2065
0c98de65
S
2066static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2067{
bce048d7
JM
2068 struct ath_wiphy *aphy = hw->priv;
2069 struct ath_softc *sc = aphy->sc;
05c78d6d 2070 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0c98de65 2071
3d832611 2072 mutex_lock(&sc->mutex);
8089cc47
JM
2073 if (ath9k_wiphy_scanning(sc)) {
2074 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2075 "same time\n");
2076 /*
2077 * Do not allow the concurrent scanning state for now. This
2078 * could be improved with scanning control moved into ath9k.
2079 */
3d832611 2080 mutex_unlock(&sc->mutex);
8089cc47
JM
2081 return;
2082 }
2083
2084 aphy->state = ATH_WIPHY_SCAN;
2085 ath9k_wiphy_pause_all_forced(sc, aphy);
0c98de65 2086 sc->sc_flags |= SC_OP_SCANNING;
05c78d6d 2087 del_timer_sync(&common->ani.timer);
b6ce5c33 2088 cancel_delayed_work_sync(&sc->tx_complete_work);
3d832611 2089 mutex_unlock(&sc->mutex);
0c98de65
S
2090}
2091
2092static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2093{
bce048d7
JM
2094 struct ath_wiphy *aphy = hw->priv;
2095 struct ath_softc *sc = aphy->sc;
05c78d6d 2096 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
0c98de65 2097
3d832611 2098 mutex_lock(&sc->mutex);
8089cc47 2099 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2100 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2101 sc->sc_flags |= SC_OP_FULL_RESET;
05c78d6d 2102 ath_start_ani(common);
b6ce5c33 2103 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
d0bec342 2104 ath_beacon_config(sc, NULL);
3d832611 2105 mutex_unlock(&sc->mutex);
0c98de65
S
2106}
2107
e239d859
FF
2108static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2109{
2110 struct ath_wiphy *aphy = hw->priv;
2111 struct ath_softc *sc = aphy->sc;
2112 struct ath_hw *ah = sc->sc_ah;
2113
2114 mutex_lock(&sc->mutex);
2115 ah->coverage_class = coverage_class;
2116 ath9k_hw_init_global_settings(ah);
2117 mutex_unlock(&sc->mutex);
2118}
2119
6baff7f9 2120struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2121 .tx = ath9k_tx,
2122 .start = ath9k_start,
2123 .stop = ath9k_stop,
2124 .add_interface = ath9k_add_interface,
2125 .remove_interface = ath9k_remove_interface,
2126 .config = ath9k_config,
8feceb67 2127 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2128 .sta_add = ath9k_sta_add,
2129 .sta_remove = ath9k_sta_remove,
8feceb67 2130 .conf_tx = ath9k_conf_tx,
8feceb67 2131 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2132 .set_key = ath9k_set_key,
8feceb67 2133 .get_tsf = ath9k_get_tsf,
3b5d665b 2134 .set_tsf = ath9k_set_tsf,
8feceb67 2135 .reset_tsf = ath9k_reset_tsf,
4233df6b 2136 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2137 .get_survey = ath9k_get_survey,
0c98de65
S
2138 .sw_scan_start = ath9k_sw_scan_start,
2139 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2140 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2141 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2142};