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ath9k: Remove redundant HT macros
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
f078f209
LR		 19
20#define ATH_PCI_VERSION "0.1"
21
f078f209
LR		 22static char *dev_info = "ath9k";
23
24MODULE_AUTHOR("Atheros Communications");
25MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27MODULE_LICENSE("Dual BSD/GPL");
28
b3bd89ce
JM		 29static int modparam_nohwcrypt;
30module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
31MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32
5f8e077c
LR		 33/* We use the hw_value as an index into our private channel structure */
34
35#define CHAN2G(_freq, _idx) { \
36 .center_freq = (_freq), \
37 .hw_value = (_idx), \
eeddfd9d 38 .max_power = 20, \
5f8e077c
LR		 39}
40
41#define CHAN5G(_freq, _idx) { \
42 .band = IEEE80211_BAND_5GHZ, \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
eeddfd9d 45 .max_power = 20, \
5f8e077c
LR		 46}
47
48/* Some 2 GHz radios are actually tunable on 2312-2732
49 * on 5 MHz steps, we support the channels which we know
50 * we have calibration data for all cards though to make
51 * this static */
52static struct ieee80211_channel ath9k_2ghz_chantable[] = {
53 CHAN2G(2412, 0), /* Channel 1 */
54 CHAN2G(2417, 1), /* Channel 2 */
55 CHAN2G(2422, 2), /* Channel 3 */
56 CHAN2G(2427, 3), /* Channel 4 */
57 CHAN2G(2432, 4), /* Channel 5 */
58 CHAN2G(2437, 5), /* Channel 6 */
59 CHAN2G(2442, 6), /* Channel 7 */
60 CHAN2G(2447, 7), /* Channel 8 */
61 CHAN2G(2452, 8), /* Channel 9 */
62 CHAN2G(2457, 9), /* Channel 10 */
63 CHAN2G(2462, 10), /* Channel 11 */
64 CHAN2G(2467, 11), /* Channel 12 */
65 CHAN2G(2472, 12), /* Channel 13 */
66 CHAN2G(2484, 13), /* Channel 14 */
67};
68
69/* Some 5 GHz radios are actually tunable on XXXX-YYYY
70 * on 5 MHz steps, we support the channels which we know
71 * we have calibration data for all cards though to make
72 * this static */
73static struct ieee80211_channel ath9k_5ghz_chantable[] = {
74 /* _We_ call this UNII 1 */
75 CHAN5G(5180, 14), /* Channel 36 */
76 CHAN5G(5200, 15), /* Channel 40 */
77 CHAN5G(5220, 16), /* Channel 44 */
78 CHAN5G(5240, 17), /* Channel 48 */
79 /* _We_ call this UNII 2 */
80 CHAN5G(5260, 18), /* Channel 52 */
81 CHAN5G(5280, 19), /* Channel 56 */
82 CHAN5G(5300, 20), /* Channel 60 */
83 CHAN5G(5320, 21), /* Channel 64 */
84 /* _We_ call this "Middle band" */
85 CHAN5G(5500, 22), /* Channel 100 */
86 CHAN5G(5520, 23), /* Channel 104 */
87 CHAN5G(5540, 24), /* Channel 108 */
88 CHAN5G(5560, 25), /* Channel 112 */
89 CHAN5G(5580, 26), /* Channel 116 */
90 CHAN5G(5600, 27), /* Channel 120 */
91 CHAN5G(5620, 28), /* Channel 124 */
92 CHAN5G(5640, 29), /* Channel 128 */
93 CHAN5G(5660, 30), /* Channel 132 */
94 CHAN5G(5680, 31), /* Channel 136 */
95 CHAN5G(5700, 32), /* Channel 140 */
96 /* _We_ call this UNII 3 */
97 CHAN5G(5745, 33), /* Channel 149 */
98 CHAN5G(5765, 34), /* Channel 153 */
99 CHAN5G(5785, 35), /* Channel 157 */
100 CHAN5G(5805, 36), /* Channel 161 */
101 CHAN5G(5825, 37), /* Channel 165 */
102};
103
ce111bad
LR		 104static void ath_cache_conf_rate(struct ath_softc *sc,
105 struct ieee80211_conf *conf)
ff37e337 106{
030bb495
LR		 107 switch (conf->channel->band) {
108 case IEEE80211_BAND_2GHZ:
109 if (conf_is_ht20(conf))
110 sc->cur_rate_table =
111 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
112 else if (conf_is_ht40_minus(conf))
113 sc->cur_rate_table =
114 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
115 else if (conf_is_ht40_plus(conf))
116 sc->cur_rate_table =
117 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
96742256 118 else
030bb495
LR		 119 sc->cur_rate_table =
120 sc->hw_rate_table[ATH9K_MODE_11G];
030bb495
LR		 121 break;
122 case IEEE80211_BAND_5GHZ:
123 if (conf_is_ht20(conf))
124 sc->cur_rate_table =
125 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
126 else if (conf_is_ht40_minus(conf))
127 sc->cur_rate_table =
128 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
129 else if (conf_is_ht40_plus(conf))
130 sc->cur_rate_table =
131 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
132 else
96742256
LR		 133 sc->cur_rate_table =
134 sc->hw_rate_table[ATH9K_MODE_11A];
030bb495
LR		 135 break;
136 default:
ce111bad 137 BUG_ON(1);
030bb495
LR		 138 break;
139 }
ff37e337
S		 140}
141
142static void ath_update_txpow(struct ath_softc *sc)
143{
cbe61d8a 144 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 145 u32 txpow;
146
17d7904d
S		 147 if (sc->curtxpow != sc->config.txpowlimit) {
148 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337
S		 149 /* read back in case value is clamped */
150 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
17d7904d 151 sc->curtxpow = txpow;
ff37e337
S		 152 }
153}
154
155static u8 parse_mpdudensity(u8 mpdudensity)
156{
157 /*
158 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
159 * 0 for no restriction
160 * 1 for 1/4 us
161 * 2 for 1/2 us
162 * 3 for 1 us
163 * 4 for 2 us
164 * 5 for 4 us
165 * 6 for 8 us
166 * 7 for 16 us
167 */
168 switch (mpdudensity) {
169 case 0:
170 return 0;
171 case 1:
172 case 2:
173 case 3:
174 /* Our lower layer calculations limit our precision to
175 1 microsecond */
176 return 1;
177 case 4:
178 return 2;
179 case 5:
180 return 4;
181 case 6:
182 return 8;
183 case 7:
184 return 16;
185 default:
186 return 0;
187 }
188}
189
190static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191{
4f0fc7c3 192 const struct ath_rate_table *rate_table = NULL;
ff37e337
S		 193 struct ieee80211_supported_band *sband;
194 struct ieee80211_rate *rate;
195 int i, maxrates;
196
197 switch (band) {
198 case IEEE80211_BAND_2GHZ:
199 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 break;
201 case IEEE80211_BAND_5GHZ:
202 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
203 break;
204 default:
205 break;
206 }
207
208 if (rate_table == NULL)
209 return;
210
211 sband = &sc->sbands[band];
212 rate = sc->rates[band];
213
214 if (rate_table->rate_cnt > ATH_RATE_MAX)
215 maxrates = ATH_RATE_MAX;
216 else
217 maxrates = rate_table->rate_cnt;
218
219 for (i = 0; i < maxrates; i++) {
220 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
221 rate[i].hw_value = rate_table->info[i].ratecode;
f46730d1
S		 222 if (rate_table->info[i].short_preamble) {
223 rate[i].hw_value_short = rate_table->info[i].ratecode |
224 rate_table->info[i].short_preamble;
225 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
226 }
ff37e337 227 sband->n_bitrates++;
f46730d1 228
04bd4638
S		 229 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
ff37e337
S		 231 }
232}
233
82880a7c
VT		 234static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
236{
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
239 u8 chan_idx;
240
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
244 return channel;
245}
246
ff37e337
S		 247/*
248 * Set/change channels. If the channel is really being changed, it's done
249 * by reseting the chip. To accomplish this we must first cleanup any pending
250 * DMA, then restart stuff.
251*/
0e2dedf9
JM		 252int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
253 struct ath9k_channel *hchan)
ff37e337 254{
cbe61d8a 255 struct ath_hw *ah = sc->sc_ah;
ff37e337 256 bool fastcc = true, stopped;
ae8d2858
LR		 257 struct ieee80211_channel *channel = hw->conf.channel;
258 int r;
ff37e337
S		 259
260 if (sc->sc_flags & SC_OP_INVALID)
261 return -EIO;
262
3cbb5dd7
VN		 263 ath9k_ps_wakeup(sc);
264
c0d7c7af
LR		 265 /*
266 * This is only performed if the channel settings have
267 * actually changed.
268 *
269 * To switch channels clear any pending DMA operations;
270 * wait long enough for the RX fifo to drain, reset the
271 * hardware at the new frequency, and then re-enable
272 * the relevant bits of the h/w.
273 */
274 ath9k_hw_set_interrupts(ah, 0);
043a0405 275 ath_drain_all_txq(sc, false);
c0d7c7af 276 stopped = ath_stoprecv(sc);
ff37e337 277
c0d7c7af
LR		 278 /* XXX: do not flush receive queue here. We don't want
279 * to flush data frames already in queue because of
280 * changing channel. */
ff37e337 281
c0d7c7af
LR		 282 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
283 fastcc = false;
284
285 DPRINTF(sc, ATH_DBG_CONFIG,
286 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
2660b81a 287 sc->sc_ah->curchan->channel,
c0d7c7af 288 channel->center_freq, sc->tx_chan_width);
ff37e337 289
c0d7c7af
LR		 290 spin_lock_bh(&sc->sc_resetlock);
291
292 r = ath9k_hw_reset(ah, hchan, fastcc);
293 if (r) {
294 DPRINTF(sc, ATH_DBG_FATAL,
295 "Unable to reset channel (%u Mhz) "
6b45784f 296 "reset status %d\n",
c0d7c7af
LR		 297 channel->center_freq, r);
298 spin_unlock_bh(&sc->sc_resetlock);
3989279c 299 goto ps_restore;
ff37e337 300 }
c0d7c7af
LR		 301 spin_unlock_bh(&sc->sc_resetlock);
302
c0d7c7af
LR		 303 sc->sc_flags &= ~SC_OP_FULL_RESET;
304
305 if (ath_startrecv(sc) != 0) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to restart recv logic\n");
3989279c
GJ		 308 r = -EIO;
309 goto ps_restore;
c0d7c7af
LR		 310 }
311
312 ath_cache_conf_rate(sc, &hw->conf);
313 ath_update_txpow(sc);
17d7904d 314 ath9k_hw_set_interrupts(ah, sc->imask);
3989279c
GJ		 315
316 ps_restore:
3cbb5dd7 317 ath9k_ps_restore(sc);
3989279c 318 return r;
ff37e337
S		 319}
320
321/*
322 * This routine performs the periodic noise floor calibration function
323 * that is used to adjust and optimize the chip performance. This
324 * takes environmental changes (location, temperature) into account.
325 * When the task is complete, it reschedules itself depending on the
326 * appropriate interval that was calculated.
327 */
328static void ath_ani_calibrate(unsigned long data)
329{
20977d3e
S		 330 struct ath_softc *sc = (struct ath_softc *)data;
331 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 332 bool longcal = false;
333 bool shortcal = false;
334 bool aniflag = false;
335 unsigned int timestamp = jiffies_to_msecs(jiffies);
20977d3e 336 u32 cal_interval, short_cal_interval;
ff37e337 337
20977d3e
S		 338 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
339 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337
S		 340
341 /*
342 * don't calibrate when we're scanning.
343 * we are most likely not on our home channel.
344 */
e5f0921a 345 spin_lock(&sc->ani_lock);
0c98de65 346 if (sc->sc_flags & SC_OP_SCANNING)
20977d3e 347 goto set_timer;
ff37e337 348
1ffc1c61
JM		 349 /* Only calibrate if awake */
350 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
351 goto set_timer;
352
353 ath9k_ps_wakeup(sc);
354
ff37e337 355 /* Long calibration runs independently of short calibration. */
17d7904d 356 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
ff37e337 357 longcal = true;
04bd4638 358 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
17d7904d 359 sc->ani.longcal_timer = timestamp;
ff37e337
S		 360 }
361
17d7904d
S		 362 /* Short calibration applies only while caldone is false */
363 if (!sc->ani.caldone) {
20977d3e 364 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 365 shortcal = true;
04bd4638 366 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
17d7904d
S		 367 sc->ani.shortcal_timer = timestamp;
368 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 369 }
370 } else {
17d7904d 371 if ((timestamp - sc->ani.resetcal_timer) >=
ff37e337 372 ATH_RESTART_CALINTERVAL) {
17d7904d
S		 373 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
374 if (sc->ani.caldone)
375 sc->ani.resetcal_timer = timestamp;
ff37e337
S		 376 }
377 }
378
379 /* Verify whether we must check ANI */
20977d3e 380 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
ff37e337 381 aniflag = true;
17d7904d 382 sc->ani.checkani_timer = timestamp;
ff37e337
S		 383 }
384
385 /* Skip all processing if there's nothing to do. */
386 if (longcal || shortcal || aniflag) {
387 /* Call ANI routine if necessary */
388 if (aniflag)
20977d3e 389 ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
ff37e337
S		 390
391 /* Perform calibration if necessary */
392 if (longcal || shortcal) {
379f0440
S		 393 sc->ani.caldone = ath9k_hw_calibrate(ah, ah->curchan,
394 sc->rx_chainmask, longcal);
395
396 if (longcal)
397 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
398 ah->curchan);
399
400 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
401 ah->curchan->channel, ah->curchan->channelFlags,
402 sc->ani.noise_floor);
ff37e337
S		 403 }
404 }
405
1ffc1c61
JM		 406 ath9k_ps_restore(sc);
407
20977d3e 408set_timer:
e5f0921a 409 spin_unlock(&sc->ani_lock);
ff37e337
S		 410 /*
411 * Set timer interval based on previous results.
412 * The interval must be the shortest necessary to satisfy ANI,
413 * short calibration and long calibration.
414 */
aac9207e 415 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 416 if (sc->sc_ah->config.enable_ani)
aac9207e 417 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
17d7904d 418 if (!sc->ani.caldone)
20977d3e 419 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 420
17d7904d 421 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
ff37e337
S		 422}
423
415f738e
S		 424static void ath_start_ani(struct ath_softc *sc)
425{
426 unsigned long timestamp = jiffies_to_msecs(jiffies);
427
428 sc->ani.longcal_timer = timestamp;
429 sc->ani.shortcal_timer = timestamp;
430 sc->ani.checkani_timer = timestamp;
431
432 mod_timer(&sc->ani.timer,
433 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
434}
435
ff37e337
S		 436/*
437 * Update tx/rx chainmask. For legacy association,
438 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT		 439 * the chainmask configuration, for bt coexistence, use
440 * the chainmask configuration even in legacy mode.
ff37e337 441 */
0e2dedf9 442void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 443{
c97c92d9 444 if (is_ht ||
2660b81a
S		 445 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
446 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
447 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
ff37e337 448 } else {
17d7904d
S		 449 sc->tx_chainmask = 1;
450 sc->rx_chainmask = 1;
ff37e337
S		 451 }
452
04bd4638 453 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
17d7904d 454 sc->tx_chainmask, sc->rx_chainmask);
ff37e337
S		 455}
456
457static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
458{
459 struct ath_node *an;
460
461 an = (struct ath_node *)sta->drv_priv;
462
87792efc 463 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 464 ath_tx_node_init(sc, an);
9e98ac65 465 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S		 466 sta->ht_cap.ampdu_factor);
467 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 468 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 469 }
ff37e337
S		 470}
471
472static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
473{
474 struct ath_node *an = (struct ath_node *)sta->drv_priv;
475
476 if (sc->sc_flags & SC_OP_TXAGGR)
477 ath_tx_node_cleanup(sc, an);
478}
479
480static void ath9k_tasklet(unsigned long data)
481{
482 struct ath_softc *sc = (struct ath_softc *)data;
17d7904d 483 u32 status = sc->intrstatus;
ff37e337 484
153e080d
VT		 485 ath9k_ps_wakeup(sc);
486
ff37e337 487 if (status & ATH9K_INT_FATAL) {
ff37e337 488 ath_reset(sc, false);
153e080d 489 ath9k_ps_restore(sc);
ff37e337 490 return;
063d8be3 491 }
ff37e337 492
063d8be3
S		 493 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
494 spin_lock_bh(&sc->rx.rxflushlock);
495 ath_rx_tasklet(sc, 0);
496 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S		 497 }
498
063d8be3
S		 499 if (status & ATH9K_INT_TX)
500 ath_tx_tasklet(sc);
501
54ce846e
JM		 502 if ((status & ATH9K_INT_TSFOOR) &&
503 (sc->hw->conf.flags & IEEE80211_CONF_PS)) {
504 /*
505 * TSF sync does not look correct; remain awake to sync with
506 * the next Beacon.
507 */
508 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
ccdfeab6 509 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
54ce846e
JM		 510 }
511
ff37e337 512 /* re-enable hardware interrupt */
17d7904d 513 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
153e080d 514 ath9k_ps_restore(sc);
ff37e337
S		 515}
516
6baff7f9 517irqreturn_t ath_isr(int irq, void *dev)
ff37e337 518{
063d8be3
S		 519#define SCHED_INTR ( \
520 ATH9K_INT_FATAL | \
521 ATH9K_INT_RXORN | \
522 ATH9K_INT_RXEOL | \
523 ATH9K_INT_RX | \
524 ATH9K_INT_TX | \
525 ATH9K_INT_BMISS | \
526 ATH9K_INT_CST | \
527 ATH9K_INT_TSFOOR)
528
ff37e337 529 struct ath_softc *sc = dev;
cbe61d8a 530 struct ath_hw *ah = sc->sc_ah;
ff37e337
S		 531 enum ath9k_int status;
532 bool sched = false;
533
063d8be3
S		 534 /*
535 * The hardware is not ready/present, don't
536 * touch anything. Note this can happen early
537 * on if the IRQ is shared.
538 */
539 if (sc->sc_flags & SC_OP_INVALID)
540 return IRQ_NONE;
ff37e337 541
063d8be3
S		 542
543 /* shared irq, not for us */
544
153e080d 545 if (!ath9k_hw_intrpend(ah))
063d8be3 546 return IRQ_NONE;
063d8be3
S		 547
548 /*
549 * Figure out the reason(s) for the interrupt. Note
550 * that the hal returns a pseudo-ISR that may include
551 * bits we haven't explicitly enabled so we mask the
552 * value to insure we only process bits we requested.
553 */
554 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
555 status &= sc->imask; /* discard unasked-for bits */
ff37e337 556
063d8be3
S		 557 /*
558 * If there are no status bits set, then this interrupt was not
559 * for me (should have been caught above).
560 */
153e080d 561 if (!status)
063d8be3 562 return IRQ_NONE;
ff37e337 563
063d8be3
S		 564 /* Cache the status */
565 sc->intrstatus = status;
566
567 if (status & SCHED_INTR)
568 sched = true;
569
570 /*
571 * If a FATAL or RXORN interrupt is received, we have to reset the
572 * chip immediately.
573 */
574 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
575 goto chip_reset;
576
577 if (status & ATH9K_INT_SWBA)
578 tasklet_schedule(&sc->bcon_tasklet);
579
580 if (status & ATH9K_INT_TXURN)
581 ath9k_hw_updatetxtriglevel(ah, true);
582
583 if (status & ATH9K_INT_MIB) {
ff37e337 584 /*
063d8be3
S		 585 * Disable interrupts until we service the MIB
586 * interrupt; otherwise it will continue to
587 * fire.
ff37e337 588 */
063d8be3
S		 589 ath9k_hw_set_interrupts(ah, 0);
590 /*
591 * Let the hal handle the event. We assume
592 * it will clear whatever condition caused
593 * the interrupt.
594 */
595 ath9k_hw_procmibevent(ah, &sc->nodestats);
596 ath9k_hw_set_interrupts(ah, sc->imask);
597 }
ff37e337 598
153e080d
VT		 599 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
600 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S		 601 /* Clear RxAbort bit so that we can
602 * receive frames */
603 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
153e080d 604 ath9k_hw_setrxabort(sc->sc_ah, 0);
063d8be3 605 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
ff37e337 606 }
063d8be3
S		 607
608chip_reset:
ff37e337 609
817e11de
S		 610 ath_debug_stat_interrupt(sc, status);
611
ff37e337
S		 612 if (sched) {
613 /* turn off every interrupt except SWBA */
17d7904d 614 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
ff37e337
S		 615 tasklet_schedule(&sc->intr_tq);
616 }
617
618 return IRQ_HANDLED;
063d8be3
S		 619
620#undef SCHED_INTR
ff37e337
S		 621}
622
f078f209 623static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 624 struct ieee80211_channel *chan,
094d05dc 625 enum nl80211_channel_type channel_type)
f078f209
LR		 626{
627 u32 chanmode = 0;
f078f209
LR		 628
629 switch (chan->band) {
630 case IEEE80211_BAND_2GHZ:
094d05dc
S		 631 switch(channel_type) {
632 case NL80211_CHAN_NO_HT:
633 case NL80211_CHAN_HT20:
f078f209 634 chanmode = CHANNEL_G_HT20;
094d05dc
S		 635 break;
636 case NL80211_CHAN_HT40PLUS:
f078f209 637 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S		 638 break;
639 case NL80211_CHAN_HT40MINUS:
f078f209 640 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S		 641 break;
642 }
f078f209
LR		 643 break;
644 case IEEE80211_BAND_5GHZ:
094d05dc
S		 645 switch(channel_type) {
646 case NL80211_CHAN_NO_HT:
647 case NL80211_CHAN_HT20:
f078f209 648 chanmode = CHANNEL_A_HT20;
094d05dc
S		 649 break;
650 case NL80211_CHAN_HT40PLUS:
f078f209 651 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S		 652 break;
653 case NL80211_CHAN_HT40MINUS:
f078f209 654 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S		 655 break;
656 }
f078f209
LR		 657 break;
658 default:
659 break;
660 }
661
662 return chanmode;
663}
664
6ace2891 665static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
3f53dd64
JM		 666 struct ath9k_keyval *hk, const u8 *addr,
667 bool authenticator)
f078f209 668{
6ace2891
JM		 669 const u8 *key_rxmic;
670 const u8 *key_txmic;
f078f209 671
6ace2891
JM		 672 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
673 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
f078f209
LR		 674
675 if (addr == NULL) {
d216aaa6
JM		 676 /*
677 * Group key installation - only two key cache entries are used
678 * regardless of splitmic capability since group key is only
679 * used either for TX or RX.
680 */
3f53dd64
JM		 681 if (authenticator) {
682 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
683 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
684 } else {
685 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
686 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
687 }
d216aaa6 688 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 689 }
17d7904d 690 if (!sc->splitmic) {
d216aaa6 691 /* TX and RX keys share the same key cache entry. */
f078f209
LR		 692 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
693 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
d216aaa6 694 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
f078f209 695 }
d216aaa6
JM		 696
697 /* Separate key cache entries for TX and RX */
698
699 /* TX key goes at first index, RX key at +32. */
f078f209 700 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
d216aaa6
JM		 701 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
702 /* TX MIC entry failed. No need to proceed further */
d8baa939 703 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 704 "Setting TX MIC Key Failed\n");
f078f209
LR		 705 return 0;
706 }
707
708 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
709 /* XXX delete tx key on failure? */
d216aaa6 710 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
6ace2891
JM		 711}
712
713static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
714{
715 int i;
716
17d7904d
S		 717 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
718 if (test_bit(i, sc->keymap) ||
719 test_bit(i + 64, sc->keymap))
6ace2891 720 continue; /* At least one part of TKIP key allocated */
17d7904d
S		 721 if (sc->splitmic &&
722 (test_bit(i + 32, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
6ace2891
JM		 724 continue; /* At least one part of TKIP key allocated */
725
726 /* Found a free slot for a TKIP key */
727 return i;
728 }
729 return -1;
730}
731
732static int ath_reserve_key_cache_slot(struct ath_softc *sc)
733{
734 int i;
735
736 /* First, try to find slots that would not be available for TKIP. */
17d7904d
S		 737 if (sc->splitmic) {
738 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
739 if (!test_bit(i, sc->keymap) &&
740 (test_bit(i + 32, sc->keymap) ||
741 test_bit(i + 64, sc->keymap) ||
742 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 743 return i;
17d7904d
S		 744 if (!test_bit(i + 32, sc->keymap) &&
745 (test_bit(i, sc->keymap) ||
746 test_bit(i + 64, sc->keymap) ||
747 test_bit(i + 64 + 32, sc->keymap)))
6ace2891 748 return i + 32;
17d7904d
S		 749 if (!test_bit(i + 64, sc->keymap) &&
750 (test_bit(i , sc->keymap) ||
751 test_bit(i + 32, sc->keymap) ||
752 test_bit(i + 64 + 32, sc->keymap)))
ea612132 753 return i + 64;
17d7904d
S		 754 if (!test_bit(i + 64 + 32, sc->keymap) &&
755 (test_bit(i, sc->keymap) ||
756 test_bit(i + 32, sc->keymap) ||
757 test_bit(i + 64, sc->keymap)))
ea612132 758 return i + 64 + 32;
6ace2891
JM		 759 }
760 } else {
17d7904d
S		 761 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
762 if (!test_bit(i, sc->keymap) &&
763 test_bit(i + 64, sc->keymap))
6ace2891 764 return i;
17d7904d
S		 765 if (test_bit(i, sc->keymap) &&
766 !test_bit(i + 64, sc->keymap))
6ace2891
JM		 767 return i + 64;
768 }
769 }
770
771 /* No partially used TKIP slots, pick any available slot */
17d7904d 772 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
be2864cf
JM		 773 /* Do not allow slots that could be needed for TKIP group keys
774 * to be used. This limitation could be removed if we know that
775 * TKIP will not be used. */
776 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
777 continue;
17d7904d 778 if (sc->splitmic) {
be2864cf
JM		 779 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
780 continue;
781 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
782 continue;
783 }
784
17d7904d 785 if (!test_bit(i, sc->keymap))
6ace2891
JM		 786 return i; /* Found a free slot for a key */
787 }
788
789 /* No free slot found */
790 return -1;
f078f209
LR		 791}
792
793static int ath_key_config(struct ath_softc *sc,
3f53dd64 794 struct ieee80211_vif *vif,
dc822b5d 795 struct ieee80211_sta *sta,
f078f209
LR		 796 struct ieee80211_key_conf *key)
797{
f078f209
LR		 798 struct ath9k_keyval hk;
799 const u8 *mac = NULL;
800 int ret = 0;
6ace2891 801 int idx;
f078f209
LR		 802
803 memset(&hk, 0, sizeof(hk));
804
805 switch (key->alg) {
806 case ALG_WEP:
807 hk.kv_type = ATH9K_CIPHER_WEP;
808 break;
809 case ALG_TKIP:
810 hk.kv_type = ATH9K_CIPHER_TKIP;
811 break;
812 case ALG_CCMP:
813 hk.kv_type = ATH9K_CIPHER_AES_CCM;
814 break;
815 default:
ca470b29 816 return -EOPNOTSUPP;
f078f209
LR		 817 }
818
6ace2891 819 hk.kv_len = key->keylen;
f078f209
LR		 820 memcpy(hk.kv_val, key->key, key->keylen);
821
6ace2891
JM		 822 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
823 /* For now, use the default keys for broadcast keys. This may
824 * need to change with virtual interfaces. */
825 idx = key->keyidx;
826 } else if (key->keyidx) {
dc822b5d
JB		 827 if (WARN_ON(!sta))
828 return -EOPNOTSUPP;
829 mac = sta->addr;
830
6ace2891
JM		 831 if (vif->type != NL80211_IFTYPE_AP) {
832 /* Only keyidx 0 should be used with unicast key, but
833 * allow this for client mode for now. */
834 idx = key->keyidx;
835 } else
836 return -EIO;
f078f209 837 } else {
dc822b5d
JB		 838 if (WARN_ON(!sta))
839 return -EOPNOTSUPP;
840 mac = sta->addr;
841
6ace2891
JM		 842 if (key->alg == ALG_TKIP)
843 idx = ath_reserve_key_cache_slot_tkip(sc);
844 else
845 idx = ath_reserve_key_cache_slot(sc);
846 if (idx < 0)
ca470b29 847 return -ENOSPC; /* no free key cache entries */
f078f209
LR		 848 }
849
850 if (key->alg == ALG_TKIP)
3f53dd64
JM		 851 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
852 vif->type == NL80211_IFTYPE_AP);
f078f209 853 else
d216aaa6 854 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
f078f209
LR		 855
856 if (!ret)
857 return -EIO;
858
17d7904d 859 set_bit(idx, sc->keymap);
6ace2891 860 if (key->alg == ALG_TKIP) {
17d7904d
S		 861 set_bit(idx + 64, sc->keymap);
862 if (sc->splitmic) {
863 set_bit(idx + 32, sc->keymap);
864 set_bit(idx + 64 + 32, sc->keymap);
6ace2891
JM		 865 }
866 }
867
868 return idx;
f078f209
LR		 869}
870
871static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
872{
6ace2891
JM		 873 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
874 if (key->hw_key_idx < IEEE80211_WEP_NKID)
875 return;
876
17d7904d 877 clear_bit(key->hw_key_idx, sc->keymap);
6ace2891
JM		 878 if (key->alg != ALG_TKIP)
879 return;
f078f209 880
17d7904d
S		 881 clear_bit(key->hw_key_idx + 64, sc->keymap);
882 if (sc->splitmic) {
883 clear_bit(key->hw_key_idx + 32, sc->keymap);
884 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
6ace2891 885 }
f078f209
LR		 886}
887
eb2599ca
S		 888static void setup_ht_cap(struct ath_softc *sc,
889 struct ieee80211_sta_ht_cap *ht_info)
f078f209 890{
140add21 891 u8 tx_streams, rx_streams;
f078f209 892
d9fe60de
JB		 893 ht_info->ht_supported = true;
894 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
895 IEEE80211_HT_CAP_SM_PS |
896 IEEE80211_HT_CAP_SGI_40 |
897 IEEE80211_HT_CAP_DSSSCCK40;
f078f209 898
9e98ac65
S		 899 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
900 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
eb2599ca 901
d9fe60de
JB		 902 /* set up supported mcs set */
903 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
140add21
SB		 904 tx_streams = !(sc->tx_chainmask & (sc->tx_chainmask - 1)) ? 1 : 2;
905 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
906
907 if (tx_streams != rx_streams) {
908 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
909 tx_streams, rx_streams);
910 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
911 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
912 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
913 }
eb2599ca 914
140add21
SB		 915 ht_info->mcs.rx_mask[0] = 0xff;
916 if (rx_streams >= 2)
eb2599ca 917 ht_info->mcs.rx_mask[1] = 0xff;
eb2599ca 918
140add21 919 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
f078f209
LR		 920}
921
8feceb67 922static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 923 struct ieee80211_vif *vif,
8feceb67 924 struct ieee80211_bss_conf *bss_conf)
f078f209 925{
f078f209 926
8feceb67 927 if (bss_conf->assoc) {
094d05dc 928 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
17d7904d 929 bss_conf->aid, sc->curbssid);
f078f209 930
8feceb67 931 /* New association, store aid */
2664f201
SB		 932 sc->curaid = bss_conf->aid;
933 ath9k_hw_write_associd(sc);
934
935 /*
936 * Request a re-configuration of Beacon related timers
937 * on the receipt of the first Beacon frame (i.e.,
938 * after time sync with the AP).
939 */
940 sc->sc_flags |= SC_OP_BEACON_SYNC;
f078f209 941
8feceb67 942 /* Configure the beacon */
2c3db3d5 943 ath_beacon_config(sc, vif);
f078f209 944
8feceb67 945 /* Reset rssi stats */
17d7904d
S		 946 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
947 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
948 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
949 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
f078f209 950
415f738e 951 ath_start_ani(sc);
8feceb67 952 } else {
1ffb0610 953 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
17d7904d 954 sc->curaid = 0;
f38faa31
SB		 955 /* Stop ANI */
956 del_timer_sync(&sc->ani.timer);
f078f209 957 }
8feceb67 958}
f078f209 959
8feceb67
VT		 960/********************************/
961/* LED functions */
962/********************************/
f078f209 963
f2bffa7e
VT		 964static void ath_led_blink_work(struct work_struct *work)
965{
966 struct ath_softc *sc = container_of(work, struct ath_softc,
967 ath_led_blink_work.work);
968
969 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
970 return;
85067c06
VT		 971
972 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
973 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
974 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
975 else
976 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
977 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
f2bffa7e
VT		 978
979 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
980 (sc->sc_flags & SC_OP_LED_ON) ?
981 msecs_to_jiffies(sc->led_off_duration) :
982 msecs_to_jiffies(sc->led_on_duration));
983
85067c06
VT		 984 sc->led_on_duration = sc->led_on_cnt ?
985 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
986 ATH_LED_ON_DURATION_IDLE;
987 sc->led_off_duration = sc->led_off_cnt ?
988 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
989 ATH_LED_OFF_DURATION_IDLE;
f2bffa7e
VT		 990 sc->led_on_cnt = sc->led_off_cnt = 0;
991 if (sc->sc_flags & SC_OP_LED_ON)
992 sc->sc_flags &= ~SC_OP_LED_ON;
993 else
994 sc->sc_flags |= SC_OP_LED_ON;
995}
996
8feceb67
VT		 997static void ath_led_brightness(struct led_classdev *led_cdev,
998 enum led_brightness brightness)
999{
1000 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1001 struct ath_softc *sc = led->sc;
f078f209 1002
8feceb67
VT		 1003 switch (brightness) {
1004 case LED_OFF:
1005 if (led->led_type == ATH_LED_ASSOC ||
f2bffa7e
VT		 1006 led->led_type == ATH_LED_RADIO) {
1007 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
1008 (led->led_type == ATH_LED_RADIO));
8feceb67 1009 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1010 if (led->led_type == ATH_LED_RADIO)
1011 sc->sc_flags &= ~SC_OP_LED_ON;
1012 } else {
1013 sc->led_off_cnt++;
1014 }
8feceb67
VT		 1015 break;
1016 case LED_FULL:
f2bffa7e 1017 if (led->led_type == ATH_LED_ASSOC) {
8feceb67 1018 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
f2bffa7e
VT		 1019 queue_delayed_work(sc->hw->workqueue,
1020 &sc->ath_led_blink_work, 0);
1021 } else if (led->led_type == ATH_LED_RADIO) {
1022 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
1023 sc->sc_flags |= SC_OP_LED_ON;
1024 } else {
1025 sc->led_on_cnt++;
1026 }
8feceb67
VT		 1027 break;
1028 default:
1029 break;
f078f209 1030 }
8feceb67 1031}
f078f209 1032
8feceb67
VT		 1033static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1034 char *trigger)
1035{
1036 int ret;
f078f209 1037
8feceb67
VT		 1038 led->sc = sc;
1039 led->led_cdev.name = led->name;
1040 led->led_cdev.default_trigger = trigger;
1041 led->led_cdev.brightness_set = ath_led_brightness;
f078f209 1042
8feceb67
VT		 1043 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1044 if (ret)
1045 DPRINTF(sc, ATH_DBG_FATAL,
1046 "Failed to register led:%s", led->name);
1047 else
1048 led->registered = 1;
1049 return ret;
1050}
f078f209 1051
8feceb67
VT		 1052static void ath_unregister_led(struct ath_led *led)
1053{
1054 if (led->registered) {
1055 led_classdev_unregister(&led->led_cdev);
1056 led->registered = 0;
f078f209 1057 }
f078f209
LR		 1058}
1059
8feceb67 1060static void ath_deinit_leds(struct ath_softc *sc)
f078f209 1061{
f2bffa7e 1062 cancel_delayed_work_sync(&sc->ath_led_blink_work);
8feceb67
VT		 1063 ath_unregister_led(&sc->assoc_led);
1064 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1065 ath_unregister_led(&sc->tx_led);
1066 ath_unregister_led(&sc->rx_led);
1067 ath_unregister_led(&sc->radio_led);
1068 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1069}
f078f209 1070
8feceb67
VT		 1071static void ath_init_leds(struct ath_softc *sc)
1072{
1073 char *trigger;
1074 int ret;
f078f209 1075
8feceb67
VT		 1076 /* Configure gpio 1 for output */
1077 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1078 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1079 /* LED off, active low */
1080 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
7dcfdcd9 1081
f2bffa7e
VT		 1082 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1083
8feceb67
VT		 1084 trigger = ieee80211_get_radio_led_name(sc->hw);
1085 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
0818cb8a 1086 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1087 ret = ath_register_led(sc, &sc->radio_led, trigger);
1088 sc->radio_led.led_type = ATH_LED_RADIO;
1089 if (ret)
1090 goto fail;
7dcfdcd9 1091
8feceb67
VT		 1092 trigger = ieee80211_get_assoc_led_name(sc->hw);
1093 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
0818cb8a 1094 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1095 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1096 sc->assoc_led.led_type = ATH_LED_ASSOC;
1097 if (ret)
1098 goto fail;
f078f209 1099
8feceb67
VT		 1100 trigger = ieee80211_get_tx_led_name(sc->hw);
1101 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
0818cb8a 1102 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1103 ret = ath_register_led(sc, &sc->tx_led, trigger);
1104 sc->tx_led.led_type = ATH_LED_TX;
1105 if (ret)
1106 goto fail;
f078f209 1107
8feceb67
VT		 1108 trigger = ieee80211_get_rx_led_name(sc->hw);
1109 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
0818cb8a 1110 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
8feceb67
VT		 1111 ret = ath_register_led(sc, &sc->rx_led, trigger);
1112 sc->rx_led.led_type = ATH_LED_RX;
1113 if (ret)
1114 goto fail;
f078f209 1115
8feceb67
VT		 1116 return;
1117
1118fail:
1119 ath_deinit_leds(sc);
f078f209
LR		 1120}
1121
7ec3e514 1122void ath_radio_enable(struct ath_softc *sc)
500c064d 1123{
cbe61d8a 1124 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1125 struct ieee80211_channel *channel = sc->hw->conf.channel;
1126 int r;
500c064d 1127
3cbb5dd7 1128 ath9k_ps_wakeup(sc);
d2f5b3a6 1129 ath9k_hw_configpcipowersave(ah, 0);
ae8d2858 1130
159cd468
VT		 1131 if (!ah->curchan)
1132 ah->curchan = ath_get_curchannel(sc, sc->hw);
1133
d2f5b3a6 1134 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1135 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1136 if (r) {
500c064d 1137 DPRINTF(sc, ATH_DBG_FATAL,
ae8d2858 1138 "Unable to reset channel %u (%uMhz) ",
6b45784f 1139 "reset status %d\n",
ae8d2858 1140 channel->center_freq, r);
500c064d
VT		 1141 }
1142 spin_unlock_bh(&sc->sc_resetlock);
1143
1144 ath_update_txpow(sc);
1145 if (ath_startrecv(sc) != 0) {
1146 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1147 "Unable to restart recv logic\n");
500c064d
VT		 1148 return;
1149 }
1150
1151 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1152 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT		 1153
1154 /* Re-Enable interrupts */
17d7904d 1155 ath9k_hw_set_interrupts(ah, sc->imask);
500c064d
VT		 1156
1157 /* Enable LED */
1158 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1159 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1160 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1161
1162 ieee80211_wake_queues(sc->hw);
3cbb5dd7 1163 ath9k_ps_restore(sc);
500c064d
VT		 1164}
1165
7ec3e514 1166void ath_radio_disable(struct ath_softc *sc)
500c064d 1167{
cbe61d8a 1168 struct ath_hw *ah = sc->sc_ah;
ae8d2858
LR		 1169 struct ieee80211_channel *channel = sc->hw->conf.channel;
1170 int r;
500c064d 1171
3cbb5dd7 1172 ath9k_ps_wakeup(sc);
500c064d
VT		 1173 ieee80211_stop_queues(sc->hw);
1174
1175 /* Disable LED */
1176 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1177 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1178
1179 /* Disable interrupts */
1180 ath9k_hw_set_interrupts(ah, 0);
1181
043a0405 1182 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT		 1183 ath_stoprecv(sc); /* turn off frame recv */
1184 ath_flushrecv(sc); /* flush recv queue */
1185
159cd468
VT		 1186 if (!ah->curchan)
1187 ah->curchan = ath_get_curchannel(sc, sc->hw);
1188
500c064d 1189 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1190 r = ath9k_hw_reset(ah, ah->curchan, false);
ae8d2858 1191 if (r) {
500c064d 1192 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1193 "Unable to reset channel %u (%uMhz) "
6b45784f 1194 "reset status %d\n",
ae8d2858 1195 channel->center_freq, r);
500c064d
VT		 1196 }
1197 spin_unlock_bh(&sc->sc_resetlock);
1198
1199 ath9k_hw_phy_disable(ah);
d2f5b3a6 1200 ath9k_hw_configpcipowersave(ah, 1);
3cbb5dd7 1201 ath9k_ps_restore(sc);
38ab422e 1202 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
500c064d
VT		 1203}
1204
5077fd35
GJ		 1205/*******************/
1206/* Rfkill */
1207/*******************/
1208
500c064d
VT		 1209static bool ath_is_rfkill_set(struct ath_softc *sc)
1210{
cbe61d8a 1211 struct ath_hw *ah = sc->sc_ah;
500c064d 1212
2660b81a
S		 1213 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1214 ah->rfkill_polarity;
500c064d
VT		 1215}
1216
3b319aae 1217static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
500c064d 1218{
3b319aae
JB		 1219 struct ath_wiphy *aphy = hw->priv;
1220 struct ath_softc *sc = aphy->sc;
19d337df 1221 bool blocked = !!ath_is_rfkill_set(sc);
500c064d 1222
3b319aae
JB		 1223 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1224
1225 if (blocked)
19d337df
JB		 1226 ath_radio_disable(sc);
1227 else
1228 ath_radio_enable(sc);
500c064d
VT		 1229}
1230
3b319aae 1231static void ath_start_rfkill_poll(struct ath_softc *sc)
500c064d 1232{
3b319aae 1233 struct ath_hw *ah = sc->sc_ah;
9c84b797 1234
3b319aae
JB		 1235 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1236 wiphy_rfkill_start_polling(sc->hw->wiphy);
9c84b797 1237}
500c064d 1238
6baff7f9 1239void ath_cleanup(struct ath_softc *sc)
39c3c2f2
GJ		 1240{
1241 ath_detach(sc);
1242 free_irq(sc->irq, sc);
1243 ath_bus_cleanup(sc);
c52f33d0 1244 kfree(sc->sec_wiphy);
39c3c2f2
GJ		 1245 ieee80211_free_hw(sc->hw);
1246}
1247
6baff7f9 1248void ath_detach(struct ath_softc *sc)
f078f209 1249{
8feceb67 1250 struct ieee80211_hw *hw = sc->hw;
9c84b797 1251 int i = 0;
f078f209 1252
3cbb5dd7
VN		 1253 ath9k_ps_wakeup(sc);
1254
04bd4638 1255 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
f078f209 1256
3fcdfb4b 1257 ath_deinit_leds(sc);
0e2dedf9 1258 cancel_work_sync(&sc->chan_work);
f98c3bd2 1259 cancel_delayed_work_sync(&sc->wiphy_work);
164ace38 1260 cancel_delayed_work_sync(&sc->tx_complete_work);
3fcdfb4b 1261
c52f33d0
JM		 1262 for (i = 0; i < sc->num_sec_wiphy; i++) {
1263 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1264 if (aphy == NULL)
1265 continue;
1266 sc->sec_wiphy[i] = NULL;
1267 ieee80211_unregister_hw(aphy->hw);
1268 ieee80211_free_hw(aphy->hw);
1269 }
3fcdfb4b 1270 ieee80211_unregister_hw(hw);
8feceb67
VT		 1271 ath_rx_cleanup(sc);
1272 ath_tx_cleanup(sc);
f078f209 1273
9c84b797
S		 1274 tasklet_kill(&sc->intr_tq);
1275 tasklet_kill(&sc->bcon_tasklet);
f078f209 1276
9c84b797
S		 1277 if (!(sc->sc_flags & SC_OP_INVALID))
1278 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8feceb67 1279
9c84b797
S		 1280 /* cleanup tx queues */
1281 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1282 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1283 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
9c84b797
S		 1284
1285 ath9k_hw_detach(sc->sc_ah);
826d2680 1286 ath9k_exit_debug(sc);
f078f209
LR		 1287}
1288
e3bb249b
BC		 1289static int ath9k_reg_notifier(struct wiphy *wiphy,
1290 struct regulatory_request *request)
1291{
1292 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1293 struct ath_wiphy *aphy = hw->priv;
1294 struct ath_softc *sc = aphy->sc;
1295 struct ath_regulatory *reg = &sc->sc_ah->regulatory;
1296
1297 return ath_reg_notifier_apply(wiphy, request, reg);
1298}
1299
ff37e337
S		 1300static int ath_init(u16 devid, struct ath_softc *sc)
1301{
cbe61d8a 1302 struct ath_hw *ah = NULL;
ff37e337
S		 1303 int status;
1304 int error = 0, i;
1305 int csz = 0;
1306
1307 /* XXX: hardware will not be ready until ath_open() being called */
1308 sc->sc_flags |= SC_OP_INVALID;
88b126af 1309
826d2680
S		 1310 if (ath9k_init_debug(sc) < 0)
1311 printk(KERN_ERR "Unable to create debugfs files\n");
ff37e337 1312
c52f33d0 1313 spin_lock_init(&sc->wiphy_lock);
ff37e337 1314 spin_lock_init(&sc->sc_resetlock);
6158425b 1315 spin_lock_init(&sc->sc_serial_rw);
e5f0921a 1316 spin_lock_init(&sc->ani_lock);
04717ccd 1317 spin_lock_init(&sc->sc_pm_lock);
aa33de09 1318 mutex_init(&sc->mutex);
ff37e337 1319 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
9fc9ab0a 1320 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
ff37e337
S		 1321 (unsigned long)sc);
1322
1323 /*
1324 * Cache line size is used to size and align various
1325 * structures used to communicate with the hardware.
1326 */
88d15707 1327 ath_read_cachesize(sc, &csz);
ff37e337 1328 /* XXX assert csz is non-zero */
17d7904d 1329 sc->cachelsz = csz << 2; /* convert to bytes */
ff37e337 1330
cbe61d8a 1331 ah = ath9k_hw_attach(devid, sc, &status);
ff37e337
S		 1332 if (ah == NULL) {
1333 DPRINTF(sc, ATH_DBG_FATAL,
295834fe 1334 "Unable to attach hardware; HAL status %d\n", status);
ff37e337
S		 1335 error = -ENXIO;
1336 goto bad;
1337 }
1338 sc->sc_ah = ah;
1339
1340 /* Get the hardware key cache size. */
2660b81a 1341 sc->keymax = ah->caps.keycache_size;
17d7904d 1342 if (sc->keymax > ATH_KEYMAX) {
d8baa939 1343 DPRINTF(sc, ATH_DBG_ANY,
04bd4638 1344 "Warning, using only %u entries in %u key cache\n",
17d7904d
S		 1345 ATH_KEYMAX, sc->keymax);
1346 sc->keymax = ATH_KEYMAX;
ff37e337
S		 1347 }
1348
1349 /*
1350 * Reset the key cache since some parts do not
1351 * reset the contents on initial power up.
1352 */
17d7904d 1353 for (i = 0; i < sc->keymax; i++)
ff37e337 1354 ath9k_hw_keyreset(ah, (u16) i);
ff37e337 1355
85efc86e 1356 if (error)
ff37e337
S		 1357 goto bad;
1358
1359 /* default to MONITOR mode */
2660b81a 1360 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
d97809db 1361
ff37e337
S		 1362 /* Setup rate tables */
1363
1364 ath_rate_attach(sc);
1365 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1366 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1367
1368 /*
1369 * Allocate hardware transmit queues: one queue for
1370 * beacon frames and one data queue for each QoS
1371 * priority. Note that the hal handles reseting
1372 * these queues at the needed time.
1373 */
b77f483f
S		 1374 sc->beacon.beaconq = ath_beaconq_setup(ah);
1375 if (sc->beacon.beaconq == -1) {
ff37e337 1376 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1377 "Unable to setup a beacon xmit queue\n");
ff37e337
S		 1378 error = -EIO;
1379 goto bad2;
1380 }
b77f483f
S		 1381 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1382 if (sc->beacon.cabq == NULL) {
ff37e337 1383 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1384 "Unable to setup CAB xmit queue\n");
ff37e337
S		 1385 error = -EIO;
1386 goto bad2;
1387 }
1388
17d7904d 1389 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
ff37e337
S		 1390 ath_cabq_update(sc);
1391
b77f483f
S		 1392 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1393 sc->tx.hwq_map[i] = -1;
ff37e337
S		 1394
1395 /* Setup data queues */
1396 /* NB: ensure BK queue is the lowest priority h/w queue */
1397 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1398 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1399 "Unable to setup xmit queue for BK traffic\n");
ff37e337
S		 1400 error = -EIO;
1401 goto bad2;
1402 }
1403
1404 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1405 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1406 "Unable to setup xmit queue for BE traffic\n");
ff37e337
S		 1407 error = -EIO;
1408 goto bad2;
1409 }
1410 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1411 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1412 "Unable to setup xmit queue for VI traffic\n");
ff37e337
S		 1413 error = -EIO;
1414 goto bad2;
1415 }
1416 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1417 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 1418 "Unable to setup xmit queue for VO traffic\n");
ff37e337
S		 1419 error = -EIO;
1420 goto bad2;
1421 }
1422
1423 /* Initializes the noise floor to a reasonable default value.
1424 * Later on this will be updated during ANI processing. */
1425
17d7904d
S		 1426 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1427 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
ff37e337
S		 1428
1429 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1430 ATH9K_CIPHER_TKIP, NULL)) {
1431 /*
1432 * Whether we should enable h/w TKIP MIC.
1433 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1434 * report WMM capable, so it's always safe to turn on
1435 * TKIP MIC in this case.
1436 */
1437 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1438 0, 1, NULL);
1439 }
1440
1441 /*
1442 * Check whether the separate key cache entries
1443 * are required to handle both tx+rx MIC keys.
1444 * With split mic keys the number of stations is limited
1445 * to 27 otherwise 59.
1446 */
1447 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1448 ATH9K_CIPHER_TKIP, NULL)
1449 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1450 ATH9K_CIPHER_MIC, NULL)
1451 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1452 0, NULL))
17d7904d 1453 sc->splitmic = 1;
ff37e337
S		 1454
1455 /* turn on mcast key search if possible */
1456 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1457 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1458 1, NULL);
1459
17d7904d 1460 sc->config.txpowlimit = ATH_TXPOWER_MAX;
ff37e337
S		 1461
1462 /* 11n Capabilities */
2660b81a 1463 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
ff37e337
S		 1464 sc->sc_flags |= SC_OP_TXAGGR;
1465 sc->sc_flags |= SC_OP_RXAGGR;
1466 }
1467
2660b81a
S		 1468 sc->tx_chainmask = ah->caps.tx_chainmask;
1469 sc->rx_chainmask = ah->caps.rx_chainmask;
ff37e337
S		 1470
1471 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
b77f483f 1472 sc->rx.defant = ath9k_hw_getdefantenna(ah);
ff37e337 1473
8ca21f01 1474 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
ba52da58 1475 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
ff37e337 1476
b77f483f 1477 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
ff37e337
S		 1478
1479 /* initialize beacon slots */
c52f33d0 1480 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2c3db3d5 1481 sc->beacon.bslot[i] = NULL;
c52f33d0
JM		 1482 sc->beacon.bslot_aphy[i] = NULL;
1483 }
ff37e337 1484
ff37e337
S		 1485 /* setup channels and rates */
1486
5f8e077c 1487 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
ff37e337
S		 1488 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1489 sc->rates[IEEE80211_BAND_2GHZ];
1490 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
5f8e077c
LR		 1491 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1492 ARRAY_SIZE(ath9k_2ghz_chantable);
ff37e337 1493
2660b81a 1494 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
5f8e077c 1495 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
ff37e337
S		 1496 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1497 sc->rates[IEEE80211_BAND_5GHZ];
1498 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
5f8e077c
LR		 1499 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1500 ARRAY_SIZE(ath9k_5ghz_chantable);
ff37e337
S		 1501 }
1502
2660b81a 1503 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
c97c92d9
VT		 1504 ath9k_hw_btcoex_enable(sc->sc_ah);
1505
ff37e337
S		 1506 return 0;
1507bad2:
1508 /* cleanup tx queues */
1509 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1510 if (ATH_TXQ_SETUP(sc, i))
b77f483f 1511 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
ff37e337
S		 1512bad:
1513 if (ah)
1514 ath9k_hw_detach(ah);
40b130a9 1515 ath9k_exit_debug(sc);
ff37e337
S		 1516
1517 return error;
1518}
1519
c52f33d0 1520void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
f078f209 1521{
9c84b797
S		 1522 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1523 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1524 IEEE80211_HW_SIGNAL_DBM |
3cbb5dd7
VN		 1525 IEEE80211_HW_AMPDU_AGGREGATION |
1526 IEEE80211_HW_SUPPORTS_PS |
eeee1320
S		 1527 IEEE80211_HW_PS_NULLFUNC_STACK |
1528 IEEE80211_HW_SPECTRUM_MGMT;
f078f209 1529
b3bd89ce 1530 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
0ced0e17
JM		 1531 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1532
9c84b797
S		 1533 hw->wiphy->interface_modes =
1534 BIT(NL80211_IFTYPE_AP) |
1535 BIT(NL80211_IFTYPE_STATION) |
9cb5412b
PE		 1536 BIT(NL80211_IFTYPE_ADHOC) |
1537 BIT(NL80211_IFTYPE_MESH_POINT);
f078f209 1538
8feceb67 1539 hw->queues = 4;
e63835b0 1540 hw->max_rates = 4;
171387ef 1541 hw->channel_change_time = 5000;
465ca84d 1542 hw->max_listen_interval = 10;
dd190183
LR		 1543 /* Hardware supports 10 but we use 4 */
1544 hw->max_rate_tries = 4;
528f0c6b 1545 hw->sta_data_size = sizeof(struct ath_node);
17d7904d 1546 hw->vif_data_size = sizeof(struct ath_vif);
f078f209 1547
8feceb67 1548 hw->rate_control_algorithm = "ath9k_rate_control";
f078f209 1549
c52f33d0
JM		 1550 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1551 &sc->sbands[IEEE80211_BAND_2GHZ];
1552 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1553 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1554 &sc->sbands[IEEE80211_BAND_5GHZ];
1555}
1556
1557int ath_attach(u16 devid, struct ath_softc *sc)
1558{
1559 struct ieee80211_hw *hw = sc->hw;
c52f33d0 1560 int error = 0, i;
3a702e49 1561 struct ath_regulatory *reg;
c52f33d0
JM		 1562
1563 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1564
1565 error = ath_init(devid, sc);
1566 if (error != 0)
1567 return error;
1568
1569 /* get mac address from hardware and set in mac80211 */
1570
1571 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1572
1573 ath_set_hw_capab(sc, hw);
1574
c26c2e57
LR		 1575 error = ath_regd_init(&sc->sc_ah->regulatory, sc->hw->wiphy,
1576 ath9k_reg_notifier);
1577 if (error)
1578 return error;
1579
1580 reg = &sc->sc_ah->regulatory;
1581
2660b81a 1582 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
eb2599ca 1583 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
2660b81a 1584 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
eb2599ca 1585 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
9c84b797
S		 1586 }
1587
db93e7b5
SB		 1588 /* initialize tx/rx engine */
1589 error = ath_tx_init(sc, ATH_TXBUF);
1590 if (error != 0)
40b130a9 1591 goto error_attach;
8feceb67 1592
db93e7b5
SB		 1593 error = ath_rx_init(sc, ATH_RXBUF);
1594 if (error != 0)
40b130a9 1595 goto error_attach;
8feceb67 1596
0e2dedf9 1597 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
f98c3bd2
JM		 1598 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1599 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
0e2dedf9 1600
db93e7b5 1601 error = ieee80211_register_hw(hw);
8feceb67 1602
3a702e49 1603 if (!ath_is_world_regd(reg)) {
c02cf373 1604 error = regulatory_hint(hw->wiphy, reg->alpha2);
fe33eb39
LR		 1605 if (error)
1606 goto error_attach;
1607 }
5f8e077c 1608
db93e7b5
SB		 1609 /* Initialize LED control */
1610 ath_init_leds(sc);
8feceb67 1611
3b319aae 1612 ath_start_rfkill_poll(sc);
5f8e077c 1613
8feceb67 1614 return 0;
40b130a9
VT		 1615
1616error_attach:
1617 /* cleanup tx queues */
1618 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1619 if (ATH_TXQ_SETUP(sc, i))
1620 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1621
1622 ath9k_hw_detach(sc->sc_ah);
1623 ath9k_exit_debug(sc);
1624
8feceb67 1625 return error;
f078f209
LR		 1626}
1627
ff37e337
S		 1628int ath_reset(struct ath_softc *sc, bool retry_tx)
1629{
cbe61d8a 1630 struct ath_hw *ah = sc->sc_ah;
030bb495 1631 struct ieee80211_hw *hw = sc->hw;
ae8d2858 1632 int r;
ff37e337
S		 1633
1634 ath9k_hw_set_interrupts(ah, 0);
043a0405 1635 ath_drain_all_txq(sc, retry_tx);
ff37e337
S		 1636 ath_stoprecv(sc);
1637 ath_flushrecv(sc);
1638
1639 spin_lock_bh(&sc->sc_resetlock);
2660b81a 1640 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
ae8d2858 1641 if (r)
ff37e337 1642 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1643 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S		 1644 spin_unlock_bh(&sc->sc_resetlock);
1645
1646 if (ath_startrecv(sc) != 0)
04bd4638 1647 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
ff37e337
S		 1648
1649 /*
1650 * We may be doing a reset in response to a request
1651 * that changes the channel so update any state that
1652 * might change as a result.
1653 */
ce111bad 1654 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1655
1656 ath_update_txpow(sc);
1657
1658 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 1659 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 1660
17d7904d 1661 ath9k_hw_set_interrupts(ah, sc->imask);
ff37e337
S		 1662
1663 if (retry_tx) {
1664 int i;
1665 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1666 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S		 1667 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1668 ath_txq_schedule(sc, &sc->tx.txq[i]);
1669 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S		 1670 }
1671 }
1672 }
1673
ae8d2858 1674 return r;
ff37e337
S		 1675}
1676
1677/*
1678 * This function will allocate both the DMA descriptor structure, and the
1679 * buffers it contains. These are used to contain the descriptors used
1680 * by the system.
1681*/
1682int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1683 struct list_head *head, const char *name,
1684 int nbuf, int ndesc)
1685{
1686#define DS2PHYS(_dd, _ds) \
1687 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1688#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1689#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1690
1691 struct ath_desc *ds;
1692 struct ath_buf *bf;
1693 int i, bsize, error;
1694
04bd4638
S		 1695 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1696 name, nbuf, ndesc);
ff37e337 1697
b03a9db9 1698 INIT_LIST_HEAD(head);
ff37e337
S		 1699 /* ath_desc must be a multiple of DWORDs */
1700 if ((sizeof(struct ath_desc) % 4) != 0) {
04bd4638 1701 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
ff37e337
S		 1702 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1703 error = -ENOMEM;
1704 goto fail;
1705 }
1706
ff37e337
S		 1707 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1708
1709 /*
1710 * Need additional DMA memory because we can't use
1711 * descriptors that cross the 4K page boundary. Assume
1712 * one skipped descriptor per 4K page.
1713 */
2660b81a 1714 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
ff37e337
S		 1715 u32 ndesc_skipped =
1716 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1717 u32 dma_len;
1718
1719 while (ndesc_skipped) {
1720 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1721 dd->dd_desc_len += dma_len;
1722
1723 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1724 };
1725 }
1726
1727 /* allocate descriptors */
7da3c55c 1728 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
f0e6ce13 1729 &dd->dd_desc_paddr, GFP_KERNEL);
ff37e337
S		 1730 if (dd->dd_desc == NULL) {
1731 error = -ENOMEM;
1732 goto fail;
1733 }
1734 ds = dd->dd_desc;
04bd4638 1735 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
ae459af1 1736 name, ds, (u32) dd->dd_desc_len,
ff37e337
S		 1737 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1738
1739 /* allocate buffers */
1740 bsize = sizeof(struct ath_buf) * nbuf;
f0e6ce13 1741 bf = kzalloc(bsize, GFP_KERNEL);
ff37e337
S		 1742 if (bf == NULL) {
1743 error = -ENOMEM;
1744 goto fail2;
1745 }
ff37e337
S		 1746 dd->dd_bufptr = bf;
1747
ff37e337
S		 1748 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1749 bf->bf_desc = ds;
1750 bf->bf_daddr = DS2PHYS(dd, ds);
1751
2660b81a 1752 if (!(sc->sc_ah->caps.hw_caps &
ff37e337
S		 1753 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1754 /*
1755 * Skip descriptor addresses which can cause 4KB
1756 * boundary crossing (addr + length) with a 32 dword
1757 * descriptor fetch.
1758 */
1759 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1760 ASSERT((caddr_t) bf->bf_desc <
1761 ((caddr_t) dd->dd_desc +
1762 dd->dd_desc_len));
1763
1764 ds += ndesc;
1765 bf->bf_desc = ds;
1766 bf->bf_daddr = DS2PHYS(dd, ds);
1767 }
1768 }
1769 list_add_tail(&bf->list, head);
1770 }
1771 return 0;
1772fail2:
7da3c55c
GJ		 1773 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1774 dd->dd_desc_paddr);
ff37e337
S		 1775fail:
1776 memset(dd, 0, sizeof(*dd));
1777 return error;
1778#undef ATH_DESC_4KB_BOUND_CHECK
1779#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1780#undef DS2PHYS
1781}
1782
1783void ath_descdma_cleanup(struct ath_softc *sc,
1784 struct ath_descdma *dd,
1785 struct list_head *head)
1786{
7da3c55c
GJ		 1787 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1788 dd->dd_desc_paddr);
ff37e337
S		 1789
1790 INIT_LIST_HEAD(head);
1791 kfree(dd->dd_bufptr);
1792 memset(dd, 0, sizeof(*dd));
1793}
1794
1795int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1796{
1797 int qnum;
1798
1799 switch (queue) {
1800 case 0:
b77f483f 1801 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
ff37e337
S		 1802 break;
1803 case 1:
b77f483f 1804 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
ff37e337
S		 1805 break;
1806 case 2:
b77f483f 1807 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1808 break;
1809 case 3:
b77f483f 1810 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
ff37e337
S		 1811 break;
1812 default:
b77f483f 1813 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
ff37e337
S		 1814 break;
1815 }
1816
1817 return qnum;
1818}
1819
1820int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1821{
1822 int qnum;
1823
1824 switch (queue) {
1825 case ATH9K_WME_AC_VO:
1826 qnum = 0;
1827 break;
1828 case ATH9K_WME_AC_VI:
1829 qnum = 1;
1830 break;
1831 case ATH9K_WME_AC_BE:
1832 qnum = 2;
1833 break;
1834 case ATH9K_WME_AC_BK:
1835 qnum = 3;
1836 break;
1837 default:
1838 qnum = -1;
1839 break;
1840 }
1841
1842 return qnum;
1843}
1844
5f8e077c
LR		 1845/* XXX: Remove me once we don't depend on ath9k_channel for all
1846 * this redundant data */
0e2dedf9
JM		 1847void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1848 struct ath9k_channel *ichan)
5f8e077c 1849{
5f8e077c
LR		 1850 struct ieee80211_channel *chan = hw->conf.channel;
1851 struct ieee80211_conf *conf = &hw->conf;
1852
1853 ichan->channel = chan->center_freq;
1854 ichan->chan = chan;
1855
1856 if (chan->band == IEEE80211_BAND_2GHZ) {
1857 ichan->chanmode = CHANNEL_G;
1858 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1859 } else {
1860 ichan->chanmode = CHANNEL_A;
1861 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1862 }
1863
1864 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1865
1866 if (conf_is_ht(conf)) {
1867 if (conf_is_ht40(conf))
1868 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1869
1870 ichan->chanmode = ath_get_extchanmode(sc, chan,
1871 conf->channel_type);
1872 }
1873}
1874
ff37e337
S		 1875/**********************/
1876/* mac80211 callbacks */
1877/**********************/
1878
8feceb67 1879static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1880{
bce048d7
JM		 1881 struct ath_wiphy *aphy = hw->priv;
1882 struct ath_softc *sc = aphy->sc;
8feceb67 1883 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1884 struct ath9k_channel *init_channel;
82880a7c 1885 int r;
f078f209 1886
04bd4638
S		 1887 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1888 "initial channel: %d MHz\n", curchan->center_freq);
f078f209 1889
141b38b6
S		 1890 mutex_lock(&sc->mutex);
1891
9580a222
JM		 1892 if (ath9k_wiphy_started(sc)) {
1893 if (sc->chan_idx == curchan->hw_value) {
1894 /*
1895 * Already on the operational channel, the new wiphy
1896 * can be marked active.
1897 */
1898 aphy->state = ATH_WIPHY_ACTIVE;
1899 ieee80211_wake_queues(hw);
1900 } else {
1901 /*
1902 * Another wiphy is on another channel, start the new
1903 * wiphy in paused state.
1904 */
1905 aphy->state = ATH_WIPHY_PAUSED;
1906 ieee80211_stop_queues(hw);
1907 }
1908 mutex_unlock(&sc->mutex);
1909 return 0;
1910 }
1911 aphy->state = ATH_WIPHY_ACTIVE;
1912
8feceb67 1913 /* setup initial channel */
f078f209 1914
82880a7c 1915 sc->chan_idx = curchan->hw_value;
f078f209 1916
82880a7c 1917 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S		 1918
1919 /* Reset SERDES registers */
1920 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1921
1922 /*
1923 * The basic interface to setting the hardware in a good
1924 * state is ``reset''. On return the hardware is known to
1925 * be powered up and with interrupts disabled. This must
1926 * be followed by initialization of the appropriate bits
1927 * and then setup of the interrupt mask.
1928 */
1929 spin_lock_bh(&sc->sc_resetlock);
ae8d2858
LR		 1930 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1931 if (r) {
ff37e337 1932 DPRINTF(sc, ATH_DBG_FATAL,
6b45784f 1933 "Unable to reset hardware; reset status %d "
ae8d2858
LR		 1934 "(freq %u MHz)\n", r,
1935 curchan->center_freq);
ff37e337 1936 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1937 goto mutex_unlock;
ff37e337
S		 1938 }
1939 spin_unlock_bh(&sc->sc_resetlock);
1940
1941 /*
1942 * This is needed only to setup initial state
1943 * but it's best done after a reset.
1944 */
1945 ath_update_txpow(sc);
8feceb67 1946
ff37e337
S		 1947 /*
1948 * Setup the hardware after reset:
1949 * The receive engine is set going.
1950 * Frame transmit is handled entirely
1951 * in the frame output path; there's nothing to do
1952 * here except setup the interrupt mask.
1953 */
1954 if (ath_startrecv(sc) != 0) {
1ffb0610 1955 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
141b38b6
S		 1956 r = -EIO;
1957 goto mutex_unlock;
f078f209 1958 }
8feceb67 1959
ff37e337 1960 /* Setup our intr mask. */
17d7904d 1961 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
ff37e337
S		 1962 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1963 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1964
2660b81a 1965 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
17d7904d 1966 sc->imask |= ATH9K_INT_GTT;
ff37e337 1967
2660b81a 1968 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
17d7904d 1969 sc->imask |= ATH9K_INT_CST;
ff37e337 1970
ce111bad 1971 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S		 1972
1973 sc->sc_flags &= ~SC_OP_INVALID;
1974
1975 /* Disable BMISS interrupt when we're not associated */
17d7904d
S		 1976 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1977 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
ff37e337 1978
bce048d7 1979 ieee80211_wake_queues(hw);
ff37e337 1980
164ace38
SB		 1981 queue_delayed_work(sc->hw->workqueue, &sc->tx_complete_work, 0);
1982
141b38b6
S		 1983mutex_unlock:
1984 mutex_unlock(&sc->mutex);
1985
ae8d2858 1986 return r;
f078f209
LR		 1987}
1988
8feceb67
VT		 1989static int ath9k_tx(struct ieee80211_hw *hw,
1990 struct sk_buff *skb)
f078f209 1991{
528f0c6b 1992 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM		 1993 struct ath_wiphy *aphy = hw->priv;
1994 struct ath_softc *sc = aphy->sc;
528f0c6b 1995 struct ath_tx_control txctl;
8feceb67 1996 int hdrlen, padsize;
528f0c6b 1997
8089cc47 1998 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
ee166a0e
JM		 1999 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2000 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2001 goto exit;
2002 }
2003
dc8c4585
JM		 2004 if (sc->hw->conf.flags & IEEE80211_CONF_PS) {
2005 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2006 /*
2007 * mac80211 does not set PM field for normal data frames, so we
2008 * need to update that based on the current PS mode.
2009 */
2010 if (ieee80211_is_data(hdr->frame_control) &&
2011 !ieee80211_is_nullfunc(hdr->frame_control) &&
2012 !ieee80211_has_pm(hdr->frame_control)) {
2013 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame "
2014 "while in PS mode\n");
2015 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2016 }
2017 }
2018
9a23f9ca
JM		 2019 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2020 /*
2021 * We are using PS-Poll and mac80211 can request TX while in
2022 * power save mode. Need to wake up hardware for the TX to be
2023 * completed and if needed, also for RX of buffered frames.
2024 */
2025 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2026 ath9k_ps_wakeup(sc);
2027 ath9k_hw_setrxabort(sc->sc_ah, 0);
2028 if (ieee80211_is_pspoll(hdr->frame_control)) {
2029 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a "
2030 "buffered frame\n");
2031 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2032 } else {
2033 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n");
2034 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2035 }
2036 /*
2037 * The actual restore operation will happen only after
2038 * the sc_flags bit is cleared. We are just dropping
2039 * the ps_usecount here.
2040 */
2041 ath9k_ps_restore(sc);
2042 }
2043
528f0c6b 2044 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 2045
8feceb67
VT		 2046 /*
2047 * As a temporary workaround, assign seq# here; this will likely need
2048 * to be cleaned up to work better with Beacon transmission and virtual
2049 * BSSes.
2050 */
2051 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2052 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2053 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 2054 sc->tx.seq_no += 0x10;
8feceb67 2055 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 2056 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 2057 }
f078f209 2058
8feceb67
VT		 2059 /* Add the padding after the header if this is not already done */
2060 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2061 if (hdrlen & 3) {
2062 padsize = hdrlen % 4;
2063 if (skb_headroom(skb) < padsize)
2064 return -1;
2065 skb_push(skb, padsize);
2066 memmove(skb->data, skb->data + padsize, hdrlen);
2067 }
2068
528f0c6b
S		 2069 /* Check if a tx queue is available */
2070
2071 txctl.txq = ath_test_get_txq(sc, skb);
2072 if (!txctl.txq)
2073 goto exit;
2074
04bd4638 2075 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 2076
c52f33d0 2077 if (ath_tx_start(hw, skb, &txctl) != 0) {
04bd4638 2078 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 2079 goto exit;
8feceb67
VT		 2080 }
2081
528f0c6b
S		 2082 return 0;
2083exit:
2084 dev_kfree_skb_any(skb);
8feceb67 2085 return 0;
f078f209
LR		 2086}
2087
8feceb67 2088static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 2089{
bce048d7
JM		 2090 struct ath_wiphy *aphy = hw->priv;
2091 struct ath_softc *sc = aphy->sc;
f078f209 2092
9580a222
JM		 2093 aphy->state = ATH_WIPHY_INACTIVE;
2094
9c84b797 2095 if (sc->sc_flags & SC_OP_INVALID) {
04bd4638 2096 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
9c84b797
S		 2097 return;
2098 }
8feceb67 2099
141b38b6 2100 mutex_lock(&sc->mutex);
ff37e337 2101
9580a222
JM		 2102 if (ath9k_wiphy_started(sc)) {
2103 mutex_unlock(&sc->mutex);
2104 return; /* another wiphy still in use */
2105 }
2106
ff37e337
S		 2107 /* make sure h/w will not generate any interrupt
2108 * before setting the invalid flag. */
2109 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2110
2111 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 2112 ath_drain_all_txq(sc, false);
ff37e337
S		 2113 ath_stoprecv(sc);
2114 ath9k_hw_phy_disable(sc->sc_ah);
2115 } else
b77f483f 2116 sc->rx.rxlink = NULL;
ff37e337 2117
3b319aae 2118 wiphy_rfkill_stop_polling(sc->hw->wiphy);
19d337df 2119
ff37e337
S		 2120 /* disable HAL and put h/w to sleep */
2121 ath9k_hw_disable(sc->sc_ah);
2122 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2123
2124 sc->sc_flags |= SC_OP_INVALID;
500c064d 2125
141b38b6
S		 2126 mutex_unlock(&sc->mutex);
2127
04bd4638 2128 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR		 2129}
2130
8feceb67
VT		 2131static int ath9k_add_interface(struct ieee80211_hw *hw,
2132 struct ieee80211_if_init_conf *conf)
f078f209 2133{
bce048d7
JM		 2134 struct ath_wiphy *aphy = hw->priv;
2135 struct ath_softc *sc = aphy->sc;
17d7904d 2136 struct ath_vif *avp = (void *)conf->vif->drv_priv;
d97809db 2137 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 2138 int ret = 0;
8feceb67 2139
141b38b6
S		 2140 mutex_lock(&sc->mutex);
2141
8ca21f01
JM		 2142 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2143 sc->nvifs > 0) {
2144 ret = -ENOBUFS;
2145 goto out;
2146 }
2147
8feceb67 2148 switch (conf->type) {
05c914fe 2149 case NL80211_IFTYPE_STATION:
d97809db 2150 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 2151 break;
05c914fe 2152 case NL80211_IFTYPE_ADHOC:
05c914fe 2153 case NL80211_IFTYPE_AP:
9cb5412b 2154 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM		 2155 if (sc->nbcnvifs >= ATH_BCBUF) {
2156 ret = -ENOBUFS;
2157 goto out;
2158 }
9cb5412b 2159 ic_opmode = conf->type;
f078f209
LR		 2160 break;
2161 default:
2162 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2163 "Interface type %d not yet supported\n", conf->type);
2c3db3d5
JM		 2164 ret = -EOPNOTSUPP;
2165 goto out;
f078f209
LR		 2166 }
2167
17d7904d 2168 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 2169
17d7904d 2170 /* Set the VIF opmode */
5640b08e
S		 2171 avp->av_opmode = ic_opmode;
2172 avp->av_bslot = -1;
2173
2c3db3d5 2174 sc->nvifs++;
8ca21f01
JM		 2175
2176 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2177 ath9k_set_bssid_mask(hw);
2178
2c3db3d5
JM		 2179 if (sc->nvifs > 1)
2180 goto out; /* skip global settings for secondary vif */
2181
b238e90e 2182 if (ic_opmode == NL80211_IFTYPE_AP) {
5640b08e 2183 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
b238e90e
S		 2184 sc->sc_flags |= SC_OP_TSF_RESET;
2185 }
5640b08e 2186
5640b08e 2187 /* Set the device opmode */
2660b81a 2188 sc->sc_ah->opmode = ic_opmode;
5640b08e 2189
4e30ffa2
VN		 2190 /*
2191 * Enable MIB interrupts when there are hardware phy counters.
2192 * Note we only do this (at the moment) for station mode.
2193 */
4af9cf4f 2194 if ((conf->type == NL80211_IFTYPE_STATION) ||
9cb5412b
PE		 2195 (conf->type == NL80211_IFTYPE_ADHOC) ||
2196 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
4af9cf4f
S		 2197 if (ath9k_hw_phycounters(sc->sc_ah))
2198 sc->imask |= ATH9K_INT_MIB;
2199 sc->imask |= ATH9K_INT_TSFOOR;
2200 }
2201
17d7904d 2202 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
4e30ffa2 2203
f38faa31
SB		 2204 if (conf->type == NL80211_IFTYPE_AP ||
2205 conf->type == NL80211_IFTYPE_ADHOC ||
2206 conf->type == NL80211_IFTYPE_MONITOR)
415f738e 2207 ath_start_ani(sc);
6f255425 2208
2c3db3d5 2209out:
141b38b6 2210 mutex_unlock(&sc->mutex);
2c3db3d5 2211 return ret;
f078f209
LR		 2212}
2213
8feceb67
VT		 2214static void ath9k_remove_interface(struct ieee80211_hw *hw,
2215 struct ieee80211_if_init_conf *conf)
f078f209 2216{
bce048d7
JM		 2217 struct ath_wiphy *aphy = hw->priv;
2218 struct ath_softc *sc = aphy->sc;
17d7904d 2219 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2c3db3d5 2220 int i;
f078f209 2221
04bd4638 2222 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 2223
141b38b6
S		 2224 mutex_lock(&sc->mutex);
2225
6f255425 2226 /* Stop ANI */
17d7904d 2227 del_timer_sync(&sc->ani.timer);
580f0b8a 2228
8feceb67 2229 /* Reclaim beacon resources */
9cb5412b
PE		 2230 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2231 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2232 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
b77f483f 2233 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
8feceb67 2234 ath_beacon_return(sc, avp);
580f0b8a 2235 }
f078f209 2236
8feceb67 2237 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 2238
2c3db3d5
JM		 2239 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2240 if (sc->beacon.bslot[i] == conf->vif) {
2241 printk(KERN_DEBUG "%s: vif had allocated beacon "
2242 "slot\n", __func__);
2243 sc->beacon.bslot[i] = NULL;
c52f33d0 2244 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM		 2245 }
2246 }
2247
17d7904d 2248 sc->nvifs--;
141b38b6
S		 2249
2250 mutex_unlock(&sc->mutex);
f078f209
LR		 2251}
2252
e8975581 2253static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 2254{
bce048d7
JM		 2255 struct ath_wiphy *aphy = hw->priv;
2256 struct ath_softc *sc = aphy->sc;
e8975581 2257 struct ieee80211_conf *conf = &hw->conf;
8782b41d 2258 struct ath_hw *ah = sc->sc_ah;
64839170 2259 bool all_wiphys_idle = false, disable_radio = false;
f078f209 2260
aa33de09 2261 mutex_lock(&sc->mutex);
141b38b6 2262
64839170
LR		 2263 /* Leave this as the first check */
2264 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2265
2266 spin_lock_bh(&sc->wiphy_lock);
2267 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2268 spin_unlock_bh(&sc->wiphy_lock);
2269
2270 if (conf->flags & IEEE80211_CONF_IDLE){
2271 if (all_wiphys_idle)
2272 disable_radio = true;
2273 }
2274 else if (all_wiphys_idle) {
2275 ath_radio_enable(sc);
2276 DPRINTF(sc, ATH_DBG_CONFIG,
2277 "not-idle: enabling radio\n");
2278 }
2279 }
2280
3cbb5dd7
VN		 2281 if (changed & IEEE80211_CONF_CHANGE_PS) {
2282 if (conf->flags & IEEE80211_CONF_PS) {
8782b41d
VN		 2283 if (!(ah->caps.hw_caps &
2284 ATH9K_HW_CAP_AUTOSLEEP)) {
2285 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2286 sc->imask |= ATH9K_INT_TIM_TIMER;
2287 ath9k_hw_set_interrupts(sc->sc_ah,
2288 sc->imask);
2289 }
2290 ath9k_hw_setrxabort(sc->sc_ah, 1);
3cbb5dd7 2291 }
3cbb5dd7
VN		 2292 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2293 } else {
2294 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN		 2295 if (!(ah->caps.hw_caps &
2296 ATH9K_HW_CAP_AUTOSLEEP)) {
2297 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca
JM		 2298 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2299 SC_OP_WAIT_FOR_CAB |
2300 SC_OP_WAIT_FOR_PSPOLL_DATA |
2301 SC_OP_WAIT_FOR_TX_ACK);
8782b41d
VN		 2302 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2303 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2304 ath9k_hw_set_interrupts(sc->sc_ah,
2305 sc->imask);
2306 }
3cbb5dd7
VN		 2307 }
2308 }
2309 }
2310
4797938c 2311 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 2312 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 2313 int pos = curchan->hw_value;
ae5eb026 2314
0e2dedf9
JM		 2315 aphy->chan_idx = pos;
2316 aphy->chan_is_ht = conf_is_ht(conf);
2317
8089cc47
JM		 2318 if (aphy->state == ATH_WIPHY_SCAN ||
2319 aphy->state == ATH_WIPHY_ACTIVE)
2320 ath9k_wiphy_pause_all_forced(sc, aphy);
2321 else {
2322 /*
2323 * Do not change operational channel based on a paused
2324 * wiphy changes.
2325 */
2326 goto skip_chan_change;
2327 }
0e2dedf9 2328
04bd4638
S		 2329 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2330 curchan->center_freq);
f078f209 2331
5f8e077c 2332 /* XXX: remove me eventualy */
0e2dedf9 2333 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 2334
ecf70441 2335 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 2336
0e2dedf9 2337 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
04bd4638 2338 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
aa33de09 2339 mutex_unlock(&sc->mutex);
e11602b7
S		 2340 return -EINVAL;
2341 }
094d05dc 2342 }
f078f209 2343
8089cc47 2344skip_chan_change:
5c020dc6 2345 if (changed & IEEE80211_CONF_CHANGE_POWER)
17d7904d 2346 sc->config.txpowlimit = 2 * conf->power_level;
f078f209 2347
64839170
LR		 2348 if (disable_radio) {
2349 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n");
2350 ath_radio_disable(sc);
2351 }
2352
aa33de09 2353 mutex_unlock(&sc->mutex);
141b38b6 2354
f078f209
LR		 2355 return 0;
2356}
2357
8feceb67
VT		 2358#define SUPPORTED_FILTERS \
2359 (FIF_PROMISC_IN_BSS | \
2360 FIF_ALLMULTI | \
2361 FIF_CONTROL | \
2362 FIF_OTHER_BSS | \
2363 FIF_BCN_PRBRESP_PROMISC | \
2364 FIF_FCSFAIL)
c83be688 2365
8feceb67
VT		 2366/* FIXME: sc->sc_full_reset ? */
2367static void ath9k_configure_filter(struct ieee80211_hw *hw,
2368 unsigned int changed_flags,
2369 unsigned int *total_flags,
2370 int mc_count,
2371 struct dev_mc_list *mclist)
2372{
bce048d7
JM		 2373 struct ath_wiphy *aphy = hw->priv;
2374 struct ath_softc *sc = aphy->sc;
8feceb67 2375 u32 rfilt;
f078f209 2376
8feceb67
VT		 2377 changed_flags &= SUPPORTED_FILTERS;
2378 *total_flags &= SUPPORTED_FILTERS;
f078f209 2379
b77f483f 2380 sc->rx.rxfilter = *total_flags;
aa68aeaa 2381 ath9k_ps_wakeup(sc);
8feceb67
VT		 2382 rfilt = ath_calcrxfilter(sc);
2383 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 2384 ath9k_ps_restore(sc);
f078f209 2385
b77f483f 2386 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
8feceb67 2387}
f078f209 2388
8feceb67
VT		 2389static void ath9k_sta_notify(struct ieee80211_hw *hw,
2390 struct ieee80211_vif *vif,
2391 enum sta_notify_cmd cmd,
17741cdc 2392 struct ieee80211_sta *sta)
8feceb67 2393{
bce048d7
JM		 2394 struct ath_wiphy *aphy = hw->priv;
2395 struct ath_softc *sc = aphy->sc;
f078f209 2396
8feceb67
VT		 2397 switch (cmd) {
2398 case STA_NOTIFY_ADD:
5640b08e 2399 ath_node_attach(sc, sta);
8feceb67
VT		 2400 break;
2401 case STA_NOTIFY_REMOVE:
b5aa9bf9 2402 ath_node_detach(sc, sta);
8feceb67
VT		 2403 break;
2404 default:
2405 break;
2406 }
f078f209
LR		 2407}
2408
141b38b6 2409static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 2410 const struct ieee80211_tx_queue_params *params)
f078f209 2411{
bce048d7
JM		 2412 struct ath_wiphy *aphy = hw->priv;
2413 struct ath_softc *sc = aphy->sc;
8feceb67
VT		 2414 struct ath9k_tx_queue_info qi;
2415 int ret = 0, qnum;
f078f209 2416
8feceb67
VT		 2417 if (queue >= WME_NUM_AC)
2418 return 0;
f078f209 2419
141b38b6
S		 2420 mutex_lock(&sc->mutex);
2421
1ffb0610
S		 2422 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2423
8feceb67
VT		 2424 qi.tqi_aifs = params->aifs;
2425 qi.tqi_cwmin = params->cw_min;
2426 qi.tqi_cwmax = params->cw_max;
2427 qi.tqi_burstTime = params->txop;
2428 qnum = ath_get_hal_qnum(queue, sc);
f078f209 2429
8feceb67 2430 DPRINTF(sc, ATH_DBG_CONFIG,
04bd4638 2431 "Configure tx [queue/halq] [%d/%d], "
8feceb67 2432 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
04bd4638
S		 2433 queue, qnum, params->aifs, params->cw_min,
2434 params->cw_max, params->txop);
f078f209 2435
8feceb67
VT		 2436 ret = ath_txq_update(sc, qnum, &qi);
2437 if (ret)
04bd4638 2438 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 2439
141b38b6
S		 2440 mutex_unlock(&sc->mutex);
2441
8feceb67
VT		 2442 return ret;
2443}
f078f209 2444
8feceb67
VT		 2445static int ath9k_set_key(struct ieee80211_hw *hw,
2446 enum set_key_cmd cmd,
dc822b5d
JB		 2447 struct ieee80211_vif *vif,
2448 struct ieee80211_sta *sta,
8feceb67
VT		 2449 struct ieee80211_key_conf *key)
2450{
bce048d7
JM		 2451 struct ath_wiphy *aphy = hw->priv;
2452 struct ath_softc *sc = aphy->sc;
8feceb67 2453 int ret = 0;
f078f209 2454
b3bd89ce
JM		 2455 if (modparam_nohwcrypt)
2456 return -ENOSPC;
2457
141b38b6 2458 mutex_lock(&sc->mutex);
3cbb5dd7 2459 ath9k_ps_wakeup(sc);
d8baa939 2460 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 2461
8feceb67
VT		 2462 switch (cmd) {
2463 case SET_KEY:
3f53dd64 2464 ret = ath_key_config(sc, vif, sta, key);
6ace2891
JM		 2465 if (ret >= 0) {
2466 key->hw_key_idx = ret;
8feceb67
VT		 2467 /* push IV and Michael MIC generation to stack */
2468 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2469 if (key->alg == ALG_TKIP)
2470 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
0ced0e17
JM		 2471 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2472 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 2473 ret = 0;
8feceb67
VT		 2474 }
2475 break;
2476 case DISABLE_KEY:
2477 ath_key_delete(sc, key);
8feceb67
VT		 2478 break;
2479 default:
2480 ret = -EINVAL;
2481 }
f078f209 2482
3cbb5dd7 2483 ath9k_ps_restore(sc);
141b38b6
S		 2484 mutex_unlock(&sc->mutex);
2485
8feceb67
VT		 2486 return ret;
2487}
f078f209 2488
8feceb67
VT		 2489static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2490 struct ieee80211_vif *vif,
2491 struct ieee80211_bss_conf *bss_conf,
2492 u32 changed)
2493{
bce048d7
JM		 2494 struct ath_wiphy *aphy = hw->priv;
2495 struct ath_softc *sc = aphy->sc;
2d0ddec5
JB		 2496 struct ath_hw *ah = sc->sc_ah;
2497 struct ath_vif *avp = (void *)vif->drv_priv;
2498 u32 rfilt = 0;
2499 int error, i;
f078f209 2500
141b38b6
S		 2501 mutex_lock(&sc->mutex);
2502
2d0ddec5
JB		 2503 /*
2504 * TODO: Need to decide which hw opmode to use for
2505 * multi-interface cases
2506 * XXX: This belongs into add_interface!
2507 */
2508 if (vif->type == NL80211_IFTYPE_AP &&
2509 ah->opmode != NL80211_IFTYPE_AP) {
2510 ah->opmode = NL80211_IFTYPE_STATION;
2511 ath9k_hw_setopmode(ah);
2512 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2513 sc->curaid = 0;
2514 ath9k_hw_write_associd(sc);
2515 /* Request full reset to get hw opmode changed properly */
2516 sc->sc_flags |= SC_OP_FULL_RESET;
2517 }
2518
2519 if ((changed & BSS_CHANGED_BSSID) &&
2520 !is_zero_ether_addr(bss_conf->bssid)) {
2521 switch (vif->type) {
2522 case NL80211_IFTYPE_STATION:
2523 case NL80211_IFTYPE_ADHOC:
2524 case NL80211_IFTYPE_MESH_POINT:
2525 /* Set BSSID */
2526 memcpy(sc->curbssid, bss_conf->bssid, ETH_ALEN);
2527 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2528 sc->curaid = 0;
2529 ath9k_hw_write_associd(sc);
2530
2531 /* Set aggregation protection mode parameters */
2532 sc->config.ath_aggr_prot = 0;
2533
2534 DPRINTF(sc, ATH_DBG_CONFIG,
2535 "RX filter 0x%x bssid %pM aid 0x%x\n",
2536 rfilt, sc->curbssid, sc->curaid);
2537
2538 /* need to reconfigure the beacon */
2539 sc->sc_flags &= ~SC_OP_BEACONS ;
2540
2541 break;
2542 default:
2543 break;
2544 }
2545 }
2546
2547 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2548 (vif->type == NL80211_IFTYPE_AP) ||
2549 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2550 if ((changed & BSS_CHANGED_BEACON) ||
2551 (changed & BSS_CHANGED_BEACON_ENABLED &&
2552 bss_conf->enable_beacon)) {
2553 /*
2554 * Allocate and setup the beacon frame.
2555 *
2556 * Stop any previous beacon DMA. This may be
2557 * necessary, for example, when an ibss merge
2558 * causes reconfiguration; we may be called
2559 * with beacon transmission active.
2560 */
2561 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2562
2563 error = ath_beacon_alloc(aphy, vif);
2564 if (!error)
2565 ath_beacon_config(sc, vif);
2566 }
2567 }
2568
2569 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2570 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2571 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2572 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2573 ath9k_hw_keysetmac(sc->sc_ah,
2574 (u16)i,
2575 sc->curbssid);
2576 }
2577
2578 /* Only legacy IBSS for now */
2579 if (vif->type == NL80211_IFTYPE_ADHOC)
2580 ath_update_chainmask(sc, 0);
2581
8feceb67 2582 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
04bd4638 2583 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
8feceb67
VT		 2584 bss_conf->use_short_preamble);
2585 if (bss_conf->use_short_preamble)
2586 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2587 else
2588 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2589 }
f078f209 2590
8feceb67 2591 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
04bd4638 2592 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
8feceb67
VT		 2593 bss_conf->use_cts_prot);
2594 if (bss_conf->use_cts_prot &&
2595 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2596 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2597 else
2598 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2599 }
f078f209 2600
8feceb67 2601 if (changed & BSS_CHANGED_ASSOC) {
04bd4638 2602 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 2603 bss_conf->assoc);
5640b08e 2604 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 2605 }
141b38b6 2606
57c4d7b4
JB		 2607 /*
2608 * The HW TSF has to be reset when the beacon interval changes.
2609 * We set the flag here, and ath_beacon_config_ap() would take this
2610 * into account when it gets called through the subsequent
2611 * config_interface() call - with IFCC_BEACON in the changed field.
2612 */
2613
2614 if (changed & BSS_CHANGED_BEACON_INT) {
2615 sc->sc_flags |= SC_OP_TSF_RESET;
2616 sc->beacon_interval = bss_conf->beacon_int;
2617 }
2618
141b38b6 2619 mutex_unlock(&sc->mutex);
8feceb67 2620}
f078f209 2621
8feceb67
VT		 2622static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2623{
2624 u64 tsf;
bce048d7
JM		 2625 struct ath_wiphy *aphy = hw->priv;
2626 struct ath_softc *sc = aphy->sc;
f078f209 2627
141b38b6
S		 2628 mutex_lock(&sc->mutex);
2629 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2630 mutex_unlock(&sc->mutex);
f078f209 2631
8feceb67
VT		 2632 return tsf;
2633}
f078f209 2634
3b5d665b
AF		 2635static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2636{
bce048d7
JM		 2637 struct ath_wiphy *aphy = hw->priv;
2638 struct ath_softc *sc = aphy->sc;
3b5d665b 2639
141b38b6
S		 2640 mutex_lock(&sc->mutex);
2641 ath9k_hw_settsf64(sc->sc_ah, tsf);
2642 mutex_unlock(&sc->mutex);
3b5d665b
AF		 2643}
2644
8feceb67
VT		 2645static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2646{
bce048d7
JM		 2647 struct ath_wiphy *aphy = hw->priv;
2648 struct ath_softc *sc = aphy->sc;
c83be688 2649
141b38b6
S		 2650 mutex_lock(&sc->mutex);
2651 ath9k_hw_reset_tsf(sc->sc_ah);
2652 mutex_unlock(&sc->mutex);
8feceb67 2653}
f078f209 2654
8feceb67 2655static int ath9k_ampdu_action(struct ieee80211_hw *hw,
141b38b6
S		 2656 enum ieee80211_ampdu_mlme_action action,
2657 struct ieee80211_sta *sta,
2658 u16 tid, u16 *ssn)
8feceb67 2659{
bce048d7
JM		 2660 struct ath_wiphy *aphy = hw->priv;
2661 struct ath_softc *sc = aphy->sc;
8feceb67 2662 int ret = 0;
f078f209 2663
8feceb67
VT		 2664 switch (action) {
2665 case IEEE80211_AMPDU_RX_START:
dca3edb8
S		 2666 if (!(sc->sc_flags & SC_OP_RXAGGR))
2667 ret = -ENOTSUPP;
8feceb67
VT		 2668 break;
2669 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT		 2670 break;
2671 case IEEE80211_AMPDU_TX_START:
b5aa9bf9 2672 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
8feceb67
VT		 2673 if (ret < 0)
2674 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2675 "Unable to start TX aggregation\n");
8feceb67 2676 else
17741cdc 2677 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67
VT		 2678 break;
2679 case IEEE80211_AMPDU_TX_STOP:
b5aa9bf9 2680 ret = ath_tx_aggr_stop(sc, sta, tid);
8feceb67
VT		 2681 if (ret < 0)
2682 DPRINTF(sc, ATH_DBG_FATAL,
04bd4638 2683 "Unable to stop TX aggregation\n");
f078f209 2684
17741cdc 2685 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
8feceb67 2686 break;
b1720231 2687 case IEEE80211_AMPDU_TX_OPERATIONAL:
8469cdef
S		 2688 ath_tx_aggr_resume(sc, sta, tid);
2689 break;
8feceb67 2690 default:
04bd4638 2691 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
8feceb67
VT		 2692 }
2693
2694 return ret;
f078f209
LR		 2695}
2696
0c98de65
S		 2697static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2698{
bce048d7
JM		 2699 struct ath_wiphy *aphy = hw->priv;
2700 struct ath_softc *sc = aphy->sc;
0c98de65 2701
8089cc47
JM		 2702 if (ath9k_wiphy_scanning(sc)) {
2703 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2704 "same time\n");
2705 /*
2706 * Do not allow the concurrent scanning state for now. This
2707 * could be improved with scanning control moved into ath9k.
2708 */
2709 return;
2710 }
2711
2712 aphy->state = ATH_WIPHY_SCAN;
2713 ath9k_wiphy_pause_all_forced(sc, aphy);
2714
e5f0921a 2715 spin_lock_bh(&sc->ani_lock);
0c98de65 2716 sc->sc_flags |= SC_OP_SCANNING;
e5f0921a 2717 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2718}
2719
2720static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2721{
bce048d7
JM		 2722 struct ath_wiphy *aphy = hw->priv;
2723 struct ath_softc *sc = aphy->sc;
0c98de65 2724
e5f0921a 2725 spin_lock_bh(&sc->ani_lock);
8089cc47 2726 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2727 sc->sc_flags &= ~SC_OP_SCANNING;
9c07a777 2728 sc->sc_flags |= SC_OP_FULL_RESET;
e5f0921a 2729 spin_unlock_bh(&sc->ani_lock);
0c98de65
S		 2730}
2731
6baff7f9 2732struct ieee80211_ops ath9k_ops = {
8feceb67
VT		 2733 .tx = ath9k_tx,
2734 .start = ath9k_start,
2735 .stop = ath9k_stop,
2736 .add_interface = ath9k_add_interface,
2737 .remove_interface = ath9k_remove_interface,
2738 .config = ath9k_config,
8feceb67 2739 .configure_filter = ath9k_configure_filter,
8feceb67
VT		 2740 .sta_notify = ath9k_sta_notify,
2741 .conf_tx = ath9k_conf_tx,
8feceb67 2742 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2743 .set_key = ath9k_set_key,
8feceb67 2744 .get_tsf = ath9k_get_tsf,
3b5d665b 2745 .set_tsf = ath9k_set_tsf,
8feceb67 2746 .reset_tsf = ath9k_reset_tsf,
4233df6b 2747 .ampdu_action = ath9k_ampdu_action,
0c98de65
S		 2748 .sw_scan_start = ath9k_sw_scan_start,
2749 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2750 .rfkill_poll = ath9k_rfkill_poll_state,
8feceb67
VT		 2751};
2752
392dff83
BP		 2753static struct {
2754 u32 version;
2755 const char * name;
2756} ath_mac_bb_names[] = {
2757 { AR_SREV_VERSION_5416_PCI, "5416" },
2758 { AR_SREV_VERSION_5416_PCIE, "5418" },
2759 { AR_SREV_VERSION_9100, "9100" },
2760 { AR_SREV_VERSION_9160, "9160" },
2761 { AR_SREV_VERSION_9280, "9280" },
2762 { AR_SREV_VERSION_9285, "9285" }
2763};
2764
2765static struct {
2766 u16 version;
2767 const char * name;
2768} ath_rf_names[] = {
2769 { 0, "5133" },
2770 { AR_RAD5133_SREV_MAJOR, "5133" },
2771 { AR_RAD5122_SREV_MAJOR, "5122" },
2772 { AR_RAD2133_SREV_MAJOR, "2133" },
2773 { AR_RAD2122_SREV_MAJOR, "2122" }
2774};
2775
2776/*
2777 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2778 */
6baff7f9 2779const char *
392dff83
BP		 2780ath_mac_bb_name(u32 mac_bb_version)
2781{
2782 int i;
2783
2784 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2785 if (ath_mac_bb_names[i].version == mac_bb_version) {
2786 return ath_mac_bb_names[i].name;
2787 }
2788 }
2789
2790 return "????";
2791}
2792
2793/*
2794 * Return the RF name. "????" is returned if the RF is unknown.
2795 */
6baff7f9 2796const char *
392dff83
BP		 2797ath_rf_name(u16 rf_version)
2798{
2799 int i;
2800
2801 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2802 if (ath_rf_names[i].version == rf_version) {
2803 return ath_rf_names[i].name;
2804 }
2805 }
2806
2807 return "????";
2808}
2809
6baff7f9 2810static int __init ath9k_init(void)
f078f209 2811{
ca8a8560
VT		 2812 int error;
2813
ca8a8560
VT		 2814 /* Register rate control algorithm */
2815 error = ath_rate_control_register();
2816 if (error != 0) {
2817 printk(KERN_ERR
b51bb3cd
LR		 2818 "ath9k: Unable to register rate control "
2819 "algorithm: %d\n",
ca8a8560 2820 error);
6baff7f9 2821 goto err_out;
ca8a8560
VT		 2822 }
2823
19d8bc22
GJ		 2824 error = ath9k_debug_create_root();
2825 if (error) {
2826 printk(KERN_ERR
2827 "ath9k: Unable to create debugfs root: %d\n",
2828 error);
2829 goto err_rate_unregister;
2830 }
2831
6baff7f9
GJ		 2832 error = ath_pci_init();
2833 if (error < 0) {
f078f209 2834 printk(KERN_ERR
b51bb3cd 2835 "ath9k: No PCI devices found, driver not installed.\n");
6baff7f9 2836 error = -ENODEV;
19d8bc22 2837 goto err_remove_root;
f078f209
LR		 2838 }
2839
09329d37
GJ		 2840 error = ath_ahb_init();
2841 if (error < 0) {
2842 error = -ENODEV;
2843 goto err_pci_exit;
2844 }
2845
f078f209 2846 return 0;
6baff7f9 2847
09329d37
GJ		 2848 err_pci_exit:
2849 ath_pci_exit();
2850
19d8bc22
GJ		 2851 err_remove_root:
2852 ath9k_debug_remove_root();
6baff7f9
GJ		 2853 err_rate_unregister:
2854 ath_rate_control_unregister();
2855 err_out:
2856 return error;
f078f209 2857}
6baff7f9 2858module_init(ath9k_init);
f078f209 2859
6baff7f9 2860static void __exit ath9k_exit(void)
f078f209 2861{
09329d37 2862 ath_ahb_exit();
6baff7f9 2863 ath_pci_exit();
19d8bc22 2864 ath9k_debug_remove_root();
ca8a8560 2865 ath_rate_control_unregister();
04bd4638 2866 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
f078f209 2867}
6baff7f9 2868module_exit(ath9k_exit);
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