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ath9k: fix regression on beacon loss after bgscan
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / main.c
CommitLineData
f078f209 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
f078f209
LR
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
f078f209 17#include <linux/nl80211.h>
394cf0a1 18#include "ath9k.h"
af03abec 19#include "btcoex.h"
f078f209 20
ce111bad
LR
21static void ath_cache_conf_rate(struct ath_softc *sc,
22 struct ieee80211_conf *conf)
ff37e337 23{
030bb495
LR
24 switch (conf->channel->band) {
25 case IEEE80211_BAND_2GHZ:
26 if (conf_is_ht20(conf))
545750d3 27 sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
030bb495 28 else if (conf_is_ht40_minus(conf))
545750d3 29 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
030bb495 30 else if (conf_is_ht40_plus(conf))
545750d3 31 sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
96742256 32 else
545750d3 33 sc->cur_rate_mode = ATH9K_MODE_11G;
030bb495
LR
34 break;
35 case IEEE80211_BAND_5GHZ:
36 if (conf_is_ht20(conf))
545750d3 37 sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
030bb495 38 else if (conf_is_ht40_minus(conf))
545750d3 39 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
030bb495 40 else if (conf_is_ht40_plus(conf))
545750d3 41 sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
030bb495 42 else
545750d3 43 sc->cur_rate_mode = ATH9K_MODE_11A;
030bb495
LR
44 break;
45 default:
ce111bad 46 BUG_ON(1);
030bb495
LR
47 break;
48 }
ff37e337
S
49}
50
51static void ath_update_txpow(struct ath_softc *sc)
52{
cbe61d8a 53 struct ath_hw *ah = sc->sc_ah;
ff37e337 54
17d7904d
S
55 if (sc->curtxpow != sc->config.txpowlimit) {
56 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
ff37e337 57 /* read back in case value is clamped */
9cc3271f 58 sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
ff37e337
S
59 }
60}
61
62static u8 parse_mpdudensity(u8 mpdudensity)
63{
64 /*
65 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
66 * 0 for no restriction
67 * 1 for 1/4 us
68 * 2 for 1/2 us
69 * 3 for 1 us
70 * 4 for 2 us
71 * 5 for 4 us
72 * 6 for 8 us
73 * 7 for 16 us
74 */
75 switch (mpdudensity) {
76 case 0:
77 return 0;
78 case 1:
79 case 2:
80 case 3:
81 /* Our lower layer calculations limit our precision to
82 1 microsecond */
83 return 1;
84 case 4:
85 return 2;
86 case 5:
87 return 4;
88 case 6:
89 return 8;
90 case 7:
91 return 16;
92 default:
93 return 0;
94 }
95}
96
82880a7c
VT
97static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
98 struct ieee80211_hw *hw)
99{
100 struct ieee80211_channel *curchan = hw->conf.channel;
101 struct ath9k_channel *channel;
102 u8 chan_idx;
103
104 chan_idx = curchan->hw_value;
105 channel = &sc->sc_ah->channels[chan_idx];
106 ath9k_update_ichannel(sc, hw, channel);
107 return channel;
108}
109
55624204 110bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
8c77a569
LR
111{
112 unsigned long flags;
113 bool ret;
114
9ecdef4b
LR
115 spin_lock_irqsave(&sc->sc_pm_lock, flags);
116 ret = ath9k_hw_setpower(sc->sc_ah, mode);
117 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
8c77a569
LR
118
119 return ret;
120}
121
a91d75ae
LR
122void ath9k_ps_wakeup(struct ath_softc *sc)
123{
124 unsigned long flags;
125
126 spin_lock_irqsave(&sc->sc_pm_lock, flags);
127 if (++sc->ps_usecount != 1)
128 goto unlock;
129
9ecdef4b 130 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
a91d75ae
LR
131
132 unlock:
133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
134}
135
136void ath9k_ps_restore(struct ath_softc *sc)
137{
138 unsigned long flags;
139
140 spin_lock_irqsave(&sc->sc_pm_lock, flags);
141 if (--sc->ps_usecount != 0)
142 goto unlock;
143
1dbfd9d4
VN
144 if (sc->ps_idle)
145 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
146 else if (sc->ps_enabled &&
147 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
1b04b930
S
148 PS_WAIT_FOR_CAB |
149 PS_WAIT_FOR_PSPOLL_DATA |
150 PS_WAIT_FOR_TX_ACK)))
9ecdef4b 151 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
a91d75ae
LR
152
153 unlock:
154 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
155}
156
5ee08656
FF
157static void ath_start_ani(struct ath_common *common)
158{
159 struct ath_hw *ah = common->ah;
160 unsigned long timestamp = jiffies_to_msecs(jiffies);
161 struct ath_softc *sc = (struct ath_softc *) common->priv;
162
163 if (!(sc->sc_flags & SC_OP_ANI_RUN))
164 return;
165
166 if (sc->sc_flags & SC_OP_OFFCHANNEL)
167 return;
168
169 common->ani.longcal_timer = timestamp;
170 common->ani.shortcal_timer = timestamp;
171 common->ani.checkani_timer = timestamp;
172
173 mod_timer(&common->ani.timer,
174 jiffies +
175 msecs_to_jiffies((u32)ah->config.ani_poll_interval));
176}
177
ff37e337
S
178/*
179 * Set/change channels. If the channel is really being changed, it's done
180 * by reseting the chip. To accomplish this we must first cleanup any pending
181 * DMA, then restart stuff.
182*/
0e2dedf9
JM
183int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
184 struct ath9k_channel *hchan)
ff37e337 185{
20bd2a09 186 struct ath_wiphy *aphy = hw->priv;
cbe61d8a 187 struct ath_hw *ah = sc->sc_ah;
c46917bb 188 struct ath_common *common = ath9k_hw_common(ah);
25c56eec 189 struct ieee80211_conf *conf = &common->hw->conf;
ff37e337 190 bool fastcc = true, stopped;
ae8d2858 191 struct ieee80211_channel *channel = hw->conf.channel;
20bd2a09 192 struct ath9k_hw_cal_data *caldata = NULL;
ae8d2858 193 int r;
ff37e337
S
194
195 if (sc->sc_flags & SC_OP_INVALID)
196 return -EIO;
197
5ee08656
FF
198 del_timer_sync(&common->ani.timer);
199 cancel_work_sync(&sc->paprd_work);
200 cancel_work_sync(&sc->hw_check_work);
201 cancel_delayed_work_sync(&sc->tx_complete_work);
202
3cbb5dd7
VN
203 ath9k_ps_wakeup(sc);
204
c0d7c7af
LR
205 /*
206 * This is only performed if the channel settings have
207 * actually changed.
208 *
209 * To switch channels clear any pending DMA operations;
210 * wait long enough for the RX fifo to drain, reset the
211 * hardware at the new frequency, and then re-enable
212 * the relevant bits of the h/w.
213 */
214 ath9k_hw_set_interrupts(ah, 0);
043a0405 215 ath_drain_all_txq(sc, false);
c0d7c7af 216 stopped = ath_stoprecv(sc);
ff37e337 217
c0d7c7af
LR
218 /* XXX: do not flush receive queue here. We don't want
219 * to flush data frames already in queue because of
220 * changing channel. */
ff37e337 221
5ee08656 222 if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
c0d7c7af
LR
223 fastcc = false;
224
20bd2a09
FF
225 if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
226 caldata = &aphy->caldata;
227
c46917bb 228 ath_print(common, ATH_DBG_CONFIG,
1e51b2ff 229 "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
c46917bb 230 sc->sc_ah->curchan->channel,
1e51b2ff
LR
231 channel->center_freq, conf_is_ht40(conf),
232 fastcc);
ff37e337 233
c0d7c7af
LR
234 spin_lock_bh(&sc->sc_resetlock);
235
20bd2a09 236 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
c0d7c7af 237 if (r) {
c46917bb 238 ath_print(common, ATH_DBG_FATAL,
f643e51d 239 "Unable to reset channel (%u MHz), "
c46917bb
LR
240 "reset status %d\n",
241 channel->center_freq, r);
c0d7c7af 242 spin_unlock_bh(&sc->sc_resetlock);
3989279c 243 goto ps_restore;
ff37e337 244 }
c0d7c7af
LR
245 spin_unlock_bh(&sc->sc_resetlock);
246
c0d7c7af 247 if (ath_startrecv(sc) != 0) {
c46917bb
LR
248 ath_print(common, ATH_DBG_FATAL,
249 "Unable to restart recv logic\n");
3989279c
GJ
250 r = -EIO;
251 goto ps_restore;
c0d7c7af
LR
252 }
253
254 ath_cache_conf_rate(sc, &hw->conf);
255 ath_update_txpow(sc);
3069168c 256 ath9k_hw_set_interrupts(ah, ah->imask);
3989279c 257
5ee08656
FF
258 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL | SC_OP_SCANNING))) {
259 ath_start_ani(common);
260 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
5ee08656
FF
261 }
262
52b8ac92
LR
263 if (!(sc->sc_flags & (SC_OP_OFFCHANNEL)))
264 ath_beacon_config(sc, NULL);
265
3989279c 266 ps_restore:
3cbb5dd7 267 ath9k_ps_restore(sc);
3989279c 268 return r;
ff37e337
S
269}
270
9f42c2b6
FF
271static void ath_paprd_activate(struct ath_softc *sc)
272{
273 struct ath_hw *ah = sc->sc_ah;
20bd2a09 274 struct ath9k_hw_cal_data *caldata = ah->caldata;
9f42c2b6
FF
275 int chain;
276
20bd2a09 277 if (!caldata || !caldata->paprd_done)
9f42c2b6
FF
278 return;
279
280 ath9k_ps_wakeup(sc);
ddfef792 281 ar9003_paprd_enable(ah, false);
9f42c2b6
FF
282 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
283 if (!(ah->caps.tx_chainmask & BIT(chain)))
284 continue;
285
20bd2a09 286 ar9003_paprd_populate_single_table(ah, caldata, chain);
9f42c2b6
FF
287 }
288
289 ar9003_paprd_enable(ah, true);
290 ath9k_ps_restore(sc);
291}
292
293void ath_paprd_calibrate(struct work_struct *work)
294{
295 struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
296 struct ieee80211_hw *hw = sc->hw;
297 struct ath_hw *ah = sc->sc_ah;
298 struct ieee80211_hdr *hdr;
299 struct sk_buff *skb = NULL;
300 struct ieee80211_tx_info *tx_info;
301 int band = hw->conf.channel->band;
302 struct ieee80211_supported_band *sband = &sc->sbands[band];
303 struct ath_tx_control txctl;
20bd2a09 304 struct ath9k_hw_cal_data *caldata = ah->caldata;
9f42c2b6
FF
305 int qnum, ftype;
306 int chain_ok = 0;
307 int chain;
308 int len = 1800;
309 int time_left;
310 int i;
311
20bd2a09
FF
312 if (!caldata)
313 return;
314
9f42c2b6
FF
315 skb = alloc_skb(len, GFP_KERNEL);
316 if (!skb)
317 return;
318
319 tx_info = IEEE80211_SKB_CB(skb);
320
321 skb_put(skb, len);
322 memset(skb->data, 0, len);
323 hdr = (struct ieee80211_hdr *)skb->data;
324 ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
325 hdr->frame_control = cpu_to_le16(ftype);
a3d3da14 326 hdr->duration_id = cpu_to_le16(10);
9f42c2b6
FF
327 memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
328 memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
329 memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
330
331 memset(&txctl, 0, sizeof(txctl));
332 qnum = sc->tx.hwq_map[WME_AC_BE];
333 txctl.txq = &sc->tx.txq[qnum];
334
47399f1a 335 ath9k_ps_wakeup(sc);
9f42c2b6
FF
336 ar9003_paprd_init_table(ah);
337 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
338 if (!(ah->caps.tx_chainmask & BIT(chain)))
339 continue;
340
341 chain_ok = 0;
342 memset(tx_info, 0, sizeof(*tx_info));
343 tx_info->band = band;
344
345 for (i = 0; i < 4; i++) {
346 tx_info->control.rates[i].idx = sband->n_bitrates - 1;
347 tx_info->control.rates[i].count = 6;
348 }
349
350 init_completion(&sc->paprd_complete);
351 ar9003_paprd_setup_gain_table(ah, chain);
352 txctl.paprd = BIT(chain);
353 if (ath_tx_start(hw, skb, &txctl) != 0)
354 break;
355
356 time_left = wait_for_completion_timeout(&sc->paprd_complete,
ca369eb4 357 msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
9f42c2b6
FF
358 if (!time_left) {
359 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
360 "Timeout waiting for paprd training on "
361 "TX chain %d\n",
362 chain);
ca369eb4 363 goto fail_paprd;
9f42c2b6
FF
364 }
365
366 if (!ar9003_paprd_is_done(ah))
367 break;
368
20bd2a09 369 if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
9f42c2b6
FF
370 break;
371
372 chain_ok = 1;
373 }
374 kfree_skb(skb);
375
376 if (chain_ok) {
20bd2a09 377 caldata->paprd_done = true;
9f42c2b6
FF
378 ath_paprd_activate(sc);
379 }
380
ca369eb4 381fail_paprd:
9f42c2b6
FF
382 ath9k_ps_restore(sc);
383}
384
ff37e337
S
385/*
386 * This routine performs the periodic noise floor calibration function
387 * that is used to adjust and optimize the chip performance. This
388 * takes environmental changes (location, temperature) into account.
389 * When the task is complete, it reschedules itself depending on the
390 * appropriate interval that was calculated.
391 */
55624204 392void ath_ani_calibrate(unsigned long data)
ff37e337 393{
20977d3e
S
394 struct ath_softc *sc = (struct ath_softc *)data;
395 struct ath_hw *ah = sc->sc_ah;
c46917bb 396 struct ath_common *common = ath9k_hw_common(ah);
ff37e337
S
397 bool longcal = false;
398 bool shortcal = false;
399 bool aniflag = false;
400 unsigned int timestamp = jiffies_to_msecs(jiffies);
6044474e
FF
401 u32 cal_interval, short_cal_interval, long_cal_interval;
402
403 if (ah->caldata && ah->caldata->nfcal_interference)
404 long_cal_interval = ATH_LONG_CALINTERVAL_INT;
405 else
406 long_cal_interval = ATH_LONG_CALINTERVAL;
ff37e337 407
20977d3e
S
408 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
409 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
ff37e337 410
1ffc1c61
JM
411 /* Only calibrate if awake */
412 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
413 goto set_timer;
414
415 ath9k_ps_wakeup(sc);
416
ff37e337 417 /* Long calibration runs independently of short calibration. */
6044474e 418 if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
ff37e337 419 longcal = true;
c46917bb 420 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
3d536acf 421 common->ani.longcal_timer = timestamp;
ff37e337
S
422 }
423
17d7904d 424 /* Short calibration applies only while caldone is false */
3d536acf
LR
425 if (!common->ani.caldone) {
426 if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
ff37e337 427 shortcal = true;
c46917bb
LR
428 ath_print(common, ATH_DBG_ANI,
429 "shortcal @%lu\n", jiffies);
3d536acf
LR
430 common->ani.shortcal_timer = timestamp;
431 common->ani.resetcal_timer = timestamp;
ff37e337
S
432 }
433 } else {
3d536acf 434 if ((timestamp - common->ani.resetcal_timer) >=
ff37e337 435 ATH_RESTART_CALINTERVAL) {
3d536acf
LR
436 common->ani.caldone = ath9k_hw_reset_calvalid(ah);
437 if (common->ani.caldone)
438 common->ani.resetcal_timer = timestamp;
ff37e337
S
439 }
440 }
441
442 /* Verify whether we must check ANI */
e36b27af
LR
443 if ((timestamp - common->ani.checkani_timer) >=
444 ah->config.ani_poll_interval) {
ff37e337 445 aniflag = true;
3d536acf 446 common->ani.checkani_timer = timestamp;
ff37e337
S
447 }
448
449 /* Skip all processing if there's nothing to do. */
450 if (longcal || shortcal || aniflag) {
451 /* Call ANI routine if necessary */
452 if (aniflag)
22e66a4c 453 ath9k_hw_ani_monitor(ah, ah->curchan);
ff37e337
S
454
455 /* Perform calibration if necessary */
456 if (longcal || shortcal) {
3d536acf 457 common->ani.caldone =
43c27613
LR
458 ath9k_hw_calibrate(ah,
459 ah->curchan,
460 common->rx_chainmask,
461 longcal);
379f0440
S
462
463 if (longcal)
3d536acf 464 common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
379f0440
S
465 ah->curchan);
466
c46917bb
LR
467 ath_print(common, ATH_DBG_ANI,
468 " calibrate chan %u/%x nf: %d\n",
469 ah->curchan->channel,
470 ah->curchan->channelFlags,
3d536acf 471 common->ani.noise_floor);
ff37e337
S
472 }
473 }
474
1ffc1c61
JM
475 ath9k_ps_restore(sc);
476
20977d3e 477set_timer:
ff37e337
S
478 /*
479 * Set timer interval based on previous results.
480 * The interval must be the shortest necessary to satisfy ANI,
481 * short calibration and long calibration.
482 */
aac9207e 483 cal_interval = ATH_LONG_CALINTERVAL;
2660b81a 484 if (sc->sc_ah->config.enable_ani)
e36b27af
LR
485 cal_interval = min(cal_interval,
486 (u32)ah->config.ani_poll_interval);
3d536acf 487 if (!common->ani.caldone)
20977d3e 488 cal_interval = min(cal_interval, (u32)short_cal_interval);
ff37e337 489
3d536acf 490 mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
20bd2a09
FF
491 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
492 if (!ah->caldata->paprd_done)
9f42c2b6
FF
493 ieee80211_queue_work(sc->hw, &sc->paprd_work);
494 else
495 ath_paprd_activate(sc);
496 }
ff37e337
S
497}
498
499/*
500 * Update tx/rx chainmask. For legacy association,
501 * hard code chainmask to 1x1, for 11n association, use
c97c92d9
VT
502 * the chainmask configuration, for bt coexistence, use
503 * the chainmask configuration even in legacy mode.
ff37e337 504 */
0e2dedf9 505void ath_update_chainmask(struct ath_softc *sc, int is_ht)
ff37e337 506{
af03abec 507 struct ath_hw *ah = sc->sc_ah;
43c27613 508 struct ath_common *common = ath9k_hw_common(ah);
af03abec 509
5ee08656 510 if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
766ec4a9 511 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
43c27613
LR
512 common->tx_chainmask = ah->caps.tx_chainmask;
513 common->rx_chainmask = ah->caps.rx_chainmask;
ff37e337 514 } else {
43c27613
LR
515 common->tx_chainmask = 1;
516 common->rx_chainmask = 1;
ff37e337
S
517 }
518
43c27613 519 ath_print(common, ATH_DBG_CONFIG,
c46917bb 520 "tx chmask: %d, rx chmask: %d\n",
43c27613
LR
521 common->tx_chainmask,
522 common->rx_chainmask);
ff37e337
S
523}
524
525static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
526{
527 struct ath_node *an;
528
529 an = (struct ath_node *)sta->drv_priv;
530
87792efc 531 if (sc->sc_flags & SC_OP_TXAGGR) {
ff37e337 532 ath_tx_node_init(sc, an);
9e98ac65 533 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
87792efc
S
534 sta->ht_cap.ampdu_factor);
535 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
a59b5a5e 536 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
87792efc 537 }
ff37e337
S
538}
539
540static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
541{
542 struct ath_node *an = (struct ath_node *)sta->drv_priv;
543
544 if (sc->sc_flags & SC_OP_TXAGGR)
545 ath_tx_node_cleanup(sc, an);
546}
547
347809fc
FF
548void ath_hw_check(struct work_struct *work)
549{
550 struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
551 int i;
552
553 ath9k_ps_wakeup(sc);
554
555 for (i = 0; i < 3; i++) {
556 if (ath9k_hw_check_alive(sc->sc_ah))
557 goto out;
558
559 msleep(1);
560 }
561 ath_reset(sc, false);
562
563out:
564 ath9k_ps_restore(sc);
565}
566
55624204 567void ath9k_tasklet(unsigned long data)
ff37e337
S
568{
569 struct ath_softc *sc = (struct ath_softc *)data;
af03abec 570 struct ath_hw *ah = sc->sc_ah;
c46917bb 571 struct ath_common *common = ath9k_hw_common(ah);
af03abec 572
17d7904d 573 u32 status = sc->intrstatus;
b5c80475 574 u32 rxmask;
ff37e337 575
153e080d
VT
576 ath9k_ps_wakeup(sc);
577
347809fc 578 if (status & ATH9K_INT_FATAL) {
ff37e337 579 ath_reset(sc, false);
153e080d 580 ath9k_ps_restore(sc);
ff37e337 581 return;
063d8be3 582 }
ff37e337 583
347809fc
FF
584 if (!ath9k_hw_check_alive(ah))
585 ieee80211_queue_work(sc->hw, &sc->hw_check_work);
586
b5c80475
FF
587 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
588 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
589 ATH9K_INT_RXORN);
590 else
591 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
592
593 if (status & rxmask) {
063d8be3 594 spin_lock_bh(&sc->rx.rxflushlock);
b5c80475
FF
595
596 /* Check for high priority Rx first */
597 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
598 (status & ATH9K_INT_RXHP))
599 ath_rx_tasklet(sc, 0, true);
600
601 ath_rx_tasklet(sc, 0, false);
063d8be3 602 spin_unlock_bh(&sc->rx.rxflushlock);
ff37e337
S
603 }
604
e5003249
VT
605 if (status & ATH9K_INT_TX) {
606 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
607 ath_tx_edma_tasklet(sc);
608 else
609 ath_tx_tasklet(sc);
610 }
063d8be3 611
96148326 612 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
54ce846e
JM
613 /*
614 * TSF sync does not look correct; remain awake to sync with
615 * the next Beacon.
616 */
c46917bb
LR
617 ath_print(common, ATH_DBG_PS,
618 "TSFOOR - Sync with next Beacon\n");
1b04b930 619 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
54ce846e
JM
620 }
621
766ec4a9 622 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
ebb8e1d7
VT
623 if (status & ATH9K_INT_GENTIMER)
624 ath_gen_timer_isr(sc->sc_ah);
625
ff37e337 626 /* re-enable hardware interrupt */
3069168c 627 ath9k_hw_set_interrupts(ah, ah->imask);
153e080d 628 ath9k_ps_restore(sc);
ff37e337
S
629}
630
6baff7f9 631irqreturn_t ath_isr(int irq, void *dev)
ff37e337 632{
063d8be3
S
633#define SCHED_INTR ( \
634 ATH9K_INT_FATAL | \
635 ATH9K_INT_RXORN | \
636 ATH9K_INT_RXEOL | \
637 ATH9K_INT_RX | \
b5c80475
FF
638 ATH9K_INT_RXLP | \
639 ATH9K_INT_RXHP | \
063d8be3
S
640 ATH9K_INT_TX | \
641 ATH9K_INT_BMISS | \
642 ATH9K_INT_CST | \
ebb8e1d7
VT
643 ATH9K_INT_TSFOOR | \
644 ATH9K_INT_GENTIMER)
063d8be3 645
ff37e337 646 struct ath_softc *sc = dev;
cbe61d8a 647 struct ath_hw *ah = sc->sc_ah;
ff37e337
S
648 enum ath9k_int status;
649 bool sched = false;
650
063d8be3
S
651 /*
652 * The hardware is not ready/present, don't
653 * touch anything. Note this can happen early
654 * on if the IRQ is shared.
655 */
656 if (sc->sc_flags & SC_OP_INVALID)
657 return IRQ_NONE;
ff37e337 658
063d8be3
S
659
660 /* shared irq, not for us */
661
153e080d 662 if (!ath9k_hw_intrpend(ah))
063d8be3 663 return IRQ_NONE;
063d8be3
S
664
665 /*
666 * Figure out the reason(s) for the interrupt. Note
667 * that the hal returns a pseudo-ISR that may include
668 * bits we haven't explicitly enabled so we mask the
669 * value to insure we only process bits we requested.
670 */
671 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
3069168c 672 status &= ah->imask; /* discard unasked-for bits */
ff37e337 673
063d8be3
S
674 /*
675 * If there are no status bits set, then this interrupt was not
676 * for me (should have been caught above).
677 */
153e080d 678 if (!status)
063d8be3 679 return IRQ_NONE;
ff37e337 680
063d8be3
S
681 /* Cache the status */
682 sc->intrstatus = status;
683
684 if (status & SCHED_INTR)
685 sched = true;
686
687 /*
688 * If a FATAL or RXORN interrupt is received, we have to reset the
689 * chip immediately.
690 */
b5c80475
FF
691 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
692 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
063d8be3
S
693 goto chip_reset;
694
08578b8f
LR
695 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
696 (status & ATH9K_INT_BB_WATCHDOG)) {
697 ar9003_hw_bb_watchdog_dbg_info(ah);
698 goto chip_reset;
699 }
700
063d8be3
S
701 if (status & ATH9K_INT_SWBA)
702 tasklet_schedule(&sc->bcon_tasklet);
703
704 if (status & ATH9K_INT_TXURN)
705 ath9k_hw_updatetxtriglevel(ah, true);
706
b5c80475
FF
707 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
708 if (status & ATH9K_INT_RXEOL) {
709 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
710 ath9k_hw_set_interrupts(ah, ah->imask);
711 }
712 }
713
063d8be3 714 if (status & ATH9K_INT_MIB) {
ff37e337 715 /*
063d8be3
S
716 * Disable interrupts until we service the MIB
717 * interrupt; otherwise it will continue to
718 * fire.
ff37e337 719 */
063d8be3
S
720 ath9k_hw_set_interrupts(ah, 0);
721 /*
722 * Let the hal handle the event. We assume
723 * it will clear whatever condition caused
724 * the interrupt.
725 */
22e66a4c 726 ath9k_hw_procmibevent(ah);
3069168c 727 ath9k_hw_set_interrupts(ah, ah->imask);
063d8be3 728 }
ff37e337 729
153e080d
VT
730 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
731 if (status & ATH9K_INT_TIM_TIMER) {
063d8be3
S
732 /* Clear RxAbort bit so that we can
733 * receive frames */
9ecdef4b 734 ath9k_setpower(sc, ATH9K_PM_AWAKE);
153e080d 735 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930 736 sc->ps_flags |= PS_WAIT_FOR_BEACON;
ff37e337 737 }
063d8be3
S
738
739chip_reset:
ff37e337 740
817e11de
S
741 ath_debug_stat_interrupt(sc, status);
742
ff37e337
S
743 if (sched) {
744 /* turn off every interrupt except SWBA */
3069168c 745 ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
ff37e337
S
746 tasklet_schedule(&sc->intr_tq);
747 }
748
749 return IRQ_HANDLED;
063d8be3
S
750
751#undef SCHED_INTR
ff37e337
S
752}
753
f078f209 754static u32 ath_get_extchanmode(struct ath_softc *sc,
99405f93 755 struct ieee80211_channel *chan,
094d05dc 756 enum nl80211_channel_type channel_type)
f078f209
LR
757{
758 u32 chanmode = 0;
f078f209
LR
759
760 switch (chan->band) {
761 case IEEE80211_BAND_2GHZ:
094d05dc
S
762 switch(channel_type) {
763 case NL80211_CHAN_NO_HT:
764 case NL80211_CHAN_HT20:
f078f209 765 chanmode = CHANNEL_G_HT20;
094d05dc
S
766 break;
767 case NL80211_CHAN_HT40PLUS:
f078f209 768 chanmode = CHANNEL_G_HT40PLUS;
094d05dc
S
769 break;
770 case NL80211_CHAN_HT40MINUS:
f078f209 771 chanmode = CHANNEL_G_HT40MINUS;
094d05dc
S
772 break;
773 }
f078f209
LR
774 break;
775 case IEEE80211_BAND_5GHZ:
094d05dc
S
776 switch(channel_type) {
777 case NL80211_CHAN_NO_HT:
778 case NL80211_CHAN_HT20:
f078f209 779 chanmode = CHANNEL_A_HT20;
094d05dc
S
780 break;
781 case NL80211_CHAN_HT40PLUS:
f078f209 782 chanmode = CHANNEL_A_HT40PLUS;
094d05dc
S
783 break;
784 case NL80211_CHAN_HT40MINUS:
f078f209 785 chanmode = CHANNEL_A_HT40MINUS;
094d05dc
S
786 break;
787 }
f078f209
LR
788 break;
789 default:
790 break;
791 }
792
793 return chanmode;
794}
795
8feceb67 796static void ath9k_bss_assoc_info(struct ath_softc *sc,
5640b08e 797 struct ieee80211_vif *vif,
8feceb67 798 struct ieee80211_bss_conf *bss_conf)
f078f209 799{
f2b2143e 800 struct ath_hw *ah = sc->sc_ah;
1510718d 801 struct ath_common *common = ath9k_hw_common(ah);
f078f209 802
8feceb67 803 if (bss_conf->assoc) {
c46917bb
LR
804 ath_print(common, ATH_DBG_CONFIG,
805 "Bss Info ASSOC %d, bssid: %pM\n",
806 bss_conf->aid, common->curbssid);
f078f209 807
8feceb67 808 /* New association, store aid */
1510718d 809 common->curaid = bss_conf->aid;
f2b2143e 810 ath9k_hw_write_associd(ah);
2664f201
SB
811
812 /*
813 * Request a re-configuration of Beacon related timers
814 * on the receipt of the first Beacon frame (i.e.,
815 * after time sync with the AP).
816 */
1b04b930 817 sc->ps_flags |= PS_BEACON_SYNC;
f078f209 818
8feceb67 819 /* Configure the beacon */
2c3db3d5 820 ath_beacon_config(sc, vif);
f078f209 821
8feceb67 822 /* Reset rssi stats */
22e66a4c 823 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
f078f209 824
6c3118e2 825 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 826 ath_start_ani(common);
8feceb67 827 } else {
c46917bb 828 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1510718d 829 common->curaid = 0;
f38faa31 830 /* Stop ANI */
6c3118e2 831 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 832 del_timer_sync(&common->ani.timer);
f078f209 833 }
8feceb67 834}
f078f209 835
68a89116 836void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 837{
cbe61d8a 838 struct ath_hw *ah = sc->sc_ah;
c46917bb 839 struct ath_common *common = ath9k_hw_common(ah);
68a89116 840 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 841 int r;
500c064d 842
3cbb5dd7 843 ath9k_ps_wakeup(sc);
93b1b37f 844 ath9k_hw_configpcipowersave(ah, 0, 0);
ae8d2858 845
159cd468
VT
846 if (!ah->curchan)
847 ah->curchan = ath_get_curchannel(sc, sc->hw);
848
d2f5b3a6 849 spin_lock_bh(&sc->sc_resetlock);
20bd2a09 850 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 851 if (r) {
c46917bb 852 ath_print(common, ATH_DBG_FATAL,
f643e51d 853 "Unable to reset channel (%u MHz), "
c46917bb
LR
854 "reset status %d\n",
855 channel->center_freq, r);
500c064d
VT
856 }
857 spin_unlock_bh(&sc->sc_resetlock);
858
859 ath_update_txpow(sc);
860 if (ath_startrecv(sc) != 0) {
c46917bb
LR
861 ath_print(common, ATH_DBG_FATAL,
862 "Unable to restart recv logic\n");
500c064d
VT
863 return;
864 }
865
866 if (sc->sc_flags & SC_OP_BEACONS)
2c3db3d5 867 ath_beacon_config(sc, NULL); /* restart beacons */
500c064d
VT
868
869 /* Re-Enable interrupts */
3069168c 870 ath9k_hw_set_interrupts(ah, ah->imask);
500c064d
VT
871
872 /* Enable LED */
08fc5c1b 873 ath9k_hw_cfg_output(ah, ah->led_pin,
500c064d 874 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
08fc5c1b 875 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
500c064d 876
68a89116 877 ieee80211_wake_queues(hw);
3cbb5dd7 878 ath9k_ps_restore(sc);
500c064d
VT
879}
880
68a89116 881void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
500c064d 882{
cbe61d8a 883 struct ath_hw *ah = sc->sc_ah;
68a89116 884 struct ieee80211_channel *channel = hw->conf.channel;
ae8d2858 885 int r;
500c064d 886
3cbb5dd7 887 ath9k_ps_wakeup(sc);
68a89116 888 ieee80211_stop_queues(hw);
500c064d 889
982723df
VN
890 /*
891 * Keep the LED on when the radio is disabled
892 * during idle unassociated state.
893 */
894 if (!sc->ps_idle) {
895 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
896 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
897 }
500c064d
VT
898
899 /* Disable interrupts */
900 ath9k_hw_set_interrupts(ah, 0);
901
043a0405 902 ath_drain_all_txq(sc, false); /* clear pending tx frames */
500c064d
VT
903 ath_stoprecv(sc); /* turn off frame recv */
904 ath_flushrecv(sc); /* flush recv queue */
905
159cd468 906 if (!ah->curchan)
68a89116 907 ah->curchan = ath_get_curchannel(sc, hw);
159cd468 908
500c064d 909 spin_lock_bh(&sc->sc_resetlock);
20bd2a09 910 r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
ae8d2858 911 if (r) {
c46917bb 912 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
f643e51d 913 "Unable to reset channel (%u MHz), "
c46917bb
LR
914 "reset status %d\n",
915 channel->center_freq, r);
500c064d
VT
916 }
917 spin_unlock_bh(&sc->sc_resetlock);
918
919 ath9k_hw_phy_disable(ah);
93b1b37f 920 ath9k_hw_configpcipowersave(ah, 1, 1);
3cbb5dd7 921 ath9k_ps_restore(sc);
9ecdef4b 922 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
500c064d
VT
923}
924
ff37e337
S
925int ath_reset(struct ath_softc *sc, bool retry_tx)
926{
cbe61d8a 927 struct ath_hw *ah = sc->sc_ah;
c46917bb 928 struct ath_common *common = ath9k_hw_common(ah);
030bb495 929 struct ieee80211_hw *hw = sc->hw;
ae8d2858 930 int r;
ff37e337 931
2ab81d4a
S
932 /* Stop ANI */
933 del_timer_sync(&common->ani.timer);
934
cc9c378a
S
935 ieee80211_stop_queues(hw);
936
ff37e337 937 ath9k_hw_set_interrupts(ah, 0);
043a0405 938 ath_drain_all_txq(sc, retry_tx);
ff37e337
S
939 ath_stoprecv(sc);
940 ath_flushrecv(sc);
941
942 spin_lock_bh(&sc->sc_resetlock);
20bd2a09 943 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
ae8d2858 944 if (r)
c46917bb
LR
945 ath_print(common, ATH_DBG_FATAL,
946 "Unable to reset hardware; reset status %d\n", r);
ff37e337
S
947 spin_unlock_bh(&sc->sc_resetlock);
948
949 if (ath_startrecv(sc) != 0)
c46917bb
LR
950 ath_print(common, ATH_DBG_FATAL,
951 "Unable to start recv logic\n");
ff37e337
S
952
953 /*
954 * We may be doing a reset in response to a request
955 * that changes the channel so update any state that
956 * might change as a result.
957 */
ce111bad 958 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
959
960 ath_update_txpow(sc);
961
52b8ac92 962 if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
2c3db3d5 963 ath_beacon_config(sc, NULL); /* restart beacons */
ff37e337 964
3069168c 965 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337
S
966
967 if (retry_tx) {
968 int i;
969 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
970 if (ATH_TXQ_SETUP(sc, i)) {
b77f483f
S
971 spin_lock_bh(&sc->tx.txq[i].axq_lock);
972 ath_txq_schedule(sc, &sc->tx.txq[i]);
973 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
ff37e337
S
974 }
975 }
976 }
977
cc9c378a
S
978 ieee80211_wake_queues(hw);
979
2ab81d4a
S
980 /* Start ANI */
981 ath_start_ani(common);
982
ae8d2858 983 return r;
ff37e337
S
984}
985
ebe297c3 986static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
ff37e337
S
987{
988 int qnum;
989
990 switch (queue) {
991 case 0:
1d2231e2 992 qnum = sc->tx.hwq_map[WME_AC_VO];
ff37e337
S
993 break;
994 case 1:
1d2231e2 995 qnum = sc->tx.hwq_map[WME_AC_VI];
ff37e337
S
996 break;
997 case 2:
1d2231e2 998 qnum = sc->tx.hwq_map[WME_AC_BE];
ff37e337
S
999 break;
1000 case 3:
1d2231e2 1001 qnum = sc->tx.hwq_map[WME_AC_BK];
ff37e337
S
1002 break;
1003 default:
1d2231e2 1004 qnum = sc->tx.hwq_map[WME_AC_BE];
ff37e337
S
1005 break;
1006 }
1007
1008 return qnum;
1009}
1010
1011int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1012{
1013 int qnum;
1014
1015 switch (queue) {
1d2231e2 1016 case WME_AC_VO:
ff37e337
S
1017 qnum = 0;
1018 break;
1d2231e2 1019 case WME_AC_VI:
ff37e337
S
1020 qnum = 1;
1021 break;
1d2231e2 1022 case WME_AC_BE:
ff37e337
S
1023 qnum = 2;
1024 break;
1d2231e2 1025 case WME_AC_BK:
ff37e337
S
1026 qnum = 3;
1027 break;
1028 default:
1029 qnum = -1;
1030 break;
1031 }
1032
1033 return qnum;
1034}
1035
5f8e077c
LR
1036/* XXX: Remove me once we don't depend on ath9k_channel for all
1037 * this redundant data */
0e2dedf9
JM
1038void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1039 struct ath9k_channel *ichan)
5f8e077c 1040{
5f8e077c
LR
1041 struct ieee80211_channel *chan = hw->conf.channel;
1042 struct ieee80211_conf *conf = &hw->conf;
1043
1044 ichan->channel = chan->center_freq;
1045 ichan->chan = chan;
1046
1047 if (chan->band == IEEE80211_BAND_2GHZ) {
1048 ichan->chanmode = CHANNEL_G;
8813262e 1049 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
5f8e077c
LR
1050 } else {
1051 ichan->chanmode = CHANNEL_A;
1052 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1053 }
1054
25c56eec 1055 if (conf_is_ht(conf))
5f8e077c
LR
1056 ichan->chanmode = ath_get_extchanmode(sc, chan,
1057 conf->channel_type);
5f8e077c
LR
1058}
1059
ff37e337
S
1060/**********************/
1061/* mac80211 callbacks */
1062/**********************/
1063
8feceb67 1064static int ath9k_start(struct ieee80211_hw *hw)
f078f209 1065{
bce048d7
JM
1066 struct ath_wiphy *aphy = hw->priv;
1067 struct ath_softc *sc = aphy->sc;
af03abec 1068 struct ath_hw *ah = sc->sc_ah;
c46917bb 1069 struct ath_common *common = ath9k_hw_common(ah);
8feceb67 1070 struct ieee80211_channel *curchan = hw->conf.channel;
ff37e337 1071 struct ath9k_channel *init_channel;
82880a7c 1072 int r;
f078f209 1073
c46917bb
LR
1074 ath_print(common, ATH_DBG_CONFIG,
1075 "Starting driver with initial channel: %d MHz\n",
1076 curchan->center_freq);
f078f209 1077
141b38b6
S
1078 mutex_lock(&sc->mutex);
1079
9580a222
JM
1080 if (ath9k_wiphy_started(sc)) {
1081 if (sc->chan_idx == curchan->hw_value) {
1082 /*
1083 * Already on the operational channel, the new wiphy
1084 * can be marked active.
1085 */
1086 aphy->state = ATH_WIPHY_ACTIVE;
1087 ieee80211_wake_queues(hw);
1088 } else {
1089 /*
1090 * Another wiphy is on another channel, start the new
1091 * wiphy in paused state.
1092 */
1093 aphy->state = ATH_WIPHY_PAUSED;
1094 ieee80211_stop_queues(hw);
1095 }
1096 mutex_unlock(&sc->mutex);
1097 return 0;
1098 }
1099 aphy->state = ATH_WIPHY_ACTIVE;
1100
8feceb67 1101 /* setup initial channel */
f078f209 1102
82880a7c 1103 sc->chan_idx = curchan->hw_value;
f078f209 1104
82880a7c 1105 init_channel = ath_get_curchannel(sc, hw);
ff37e337
S
1106
1107 /* Reset SERDES registers */
af03abec 1108 ath9k_hw_configpcipowersave(ah, 0, 0);
ff37e337
S
1109
1110 /*
1111 * The basic interface to setting the hardware in a good
1112 * state is ``reset''. On return the hardware is known to
1113 * be powered up and with interrupts disabled. This must
1114 * be followed by initialization of the appropriate bits
1115 * and then setup of the interrupt mask.
1116 */
1117 spin_lock_bh(&sc->sc_resetlock);
20bd2a09 1118 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
ae8d2858 1119 if (r) {
c46917bb
LR
1120 ath_print(common, ATH_DBG_FATAL,
1121 "Unable to reset hardware; reset status %d "
1122 "(freq %u MHz)\n", r,
1123 curchan->center_freq);
ff37e337 1124 spin_unlock_bh(&sc->sc_resetlock);
141b38b6 1125 goto mutex_unlock;
ff37e337
S
1126 }
1127 spin_unlock_bh(&sc->sc_resetlock);
1128
1129 /*
1130 * This is needed only to setup initial state
1131 * but it's best done after a reset.
1132 */
1133 ath_update_txpow(sc);
8feceb67 1134
ff37e337
S
1135 /*
1136 * Setup the hardware after reset:
1137 * The receive engine is set going.
1138 * Frame transmit is handled entirely
1139 * in the frame output path; there's nothing to do
1140 * here except setup the interrupt mask.
1141 */
1142 if (ath_startrecv(sc) != 0) {
c46917bb
LR
1143 ath_print(common, ATH_DBG_FATAL,
1144 "Unable to start recv logic\n");
141b38b6
S
1145 r = -EIO;
1146 goto mutex_unlock;
f078f209 1147 }
8feceb67 1148
ff37e337 1149 /* Setup our intr mask. */
b5c80475
FF
1150 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
1151 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
1152 ATH9K_INT_GLOBAL;
1153
1154 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
08578b8f
LR
1155 ah->imask |= ATH9K_INT_RXHP |
1156 ATH9K_INT_RXLP |
1157 ATH9K_INT_BB_WATCHDOG;
b5c80475
FF
1158 else
1159 ah->imask |= ATH9K_INT_RX;
ff37e337 1160
364734fa 1161 ah->imask |= ATH9K_INT_GTT;
ff37e337 1162
af03abec 1163 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
3069168c 1164 ah->imask |= ATH9K_INT_CST;
ff37e337 1165
ce111bad 1166 ath_cache_conf_rate(sc, &hw->conf);
ff37e337
S
1167
1168 sc->sc_flags &= ~SC_OP_INVALID;
1169
1170 /* Disable BMISS interrupt when we're not associated */
3069168c
PR
1171 ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1172 ath9k_hw_set_interrupts(ah, ah->imask);
ff37e337 1173
bce048d7 1174 ieee80211_wake_queues(hw);
ff37e337 1175
42935eca 1176 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
164ace38 1177
766ec4a9
LR
1178 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
1179 !ah->btcoex_hw.enabled) {
5e197292
LR
1180 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1181 AR_STOMP_LOW_WLAN_WGHT);
af03abec 1182 ath9k_hw_btcoex_enable(ah);
f985ad12 1183
5bb12791
LR
1184 if (common->bus_ops->bt_coex_prep)
1185 common->bus_ops->bt_coex_prep(common);
766ec4a9 1186 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1187 ath9k_btcoex_timer_resume(sc);
1773912b
VT
1188 }
1189
141b38b6
S
1190mutex_unlock:
1191 mutex_unlock(&sc->mutex);
1192
ae8d2858 1193 return r;
f078f209
LR
1194}
1195
8feceb67
VT
1196static int ath9k_tx(struct ieee80211_hw *hw,
1197 struct sk_buff *skb)
f078f209 1198{
528f0c6b 1199 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
bce048d7
JM
1200 struct ath_wiphy *aphy = hw->priv;
1201 struct ath_softc *sc = aphy->sc;
c46917bb 1202 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
528f0c6b 1203 struct ath_tx_control txctl;
1bc14880
BP
1204 int padpos, padsize;
1205 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
84642d6b 1206 int qnum;
528f0c6b 1207
8089cc47 1208 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
c46917bb
LR
1209 ath_print(common, ATH_DBG_XMIT,
1210 "ath9k: %s: TX in unexpected wiphy state "
1211 "%d\n", wiphy_name(hw->wiphy), aphy->state);
ee166a0e
JM
1212 goto exit;
1213 }
1214
96148326 1215 if (sc->ps_enabled) {
dc8c4585
JM
1216 /*
1217 * mac80211 does not set PM field for normal data frames, so we
1218 * need to update that based on the current PS mode.
1219 */
1220 if (ieee80211_is_data(hdr->frame_control) &&
1221 !ieee80211_is_nullfunc(hdr->frame_control) &&
1222 !ieee80211_has_pm(hdr->frame_control)) {
c46917bb
LR
1223 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
1224 "while in PS mode\n");
dc8c4585
JM
1225 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1226 }
1227 }
1228
9a23f9ca
JM
1229 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
1230 /*
1231 * We are using PS-Poll and mac80211 can request TX while in
1232 * power save mode. Need to wake up hardware for the TX to be
1233 * completed and if needed, also for RX of buffered frames.
1234 */
9a23f9ca 1235 ath9k_ps_wakeup(sc);
fdf76622
VT
1236 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
1237 ath9k_hw_setrxabort(sc->sc_ah, 0);
9a23f9ca 1238 if (ieee80211_is_pspoll(hdr->frame_control)) {
c46917bb
LR
1239 ath_print(common, ATH_DBG_PS,
1240 "Sending PS-Poll to pick a buffered frame\n");
1b04b930 1241 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
9a23f9ca 1242 } else {
c46917bb
LR
1243 ath_print(common, ATH_DBG_PS,
1244 "Wake up to complete TX\n");
1b04b930 1245 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
9a23f9ca
JM
1246 }
1247 /*
1248 * The actual restore operation will happen only after
1249 * the sc_flags bit is cleared. We are just dropping
1250 * the ps_usecount here.
1251 */
1252 ath9k_ps_restore(sc);
1253 }
1254
528f0c6b 1255 memset(&txctl, 0, sizeof(struct ath_tx_control));
f078f209 1256
8feceb67
VT
1257 /*
1258 * As a temporary workaround, assign seq# here; this will likely need
1259 * to be cleaned up to work better with Beacon transmission and virtual
1260 * BSSes.
1261 */
1262 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
8feceb67 1263 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
b77f483f 1264 sc->tx.seq_no += 0x10;
8feceb67 1265 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
b77f483f 1266 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
8feceb67 1267 }
f078f209 1268
8feceb67 1269 /* Add the padding after the header if this is not already done */
1bc14880
BP
1270 padpos = ath9k_cmn_padpos(hdr->frame_control);
1271 padsize = padpos & 3;
1272 if (padsize && skb->len>padpos) {
8feceb67
VT
1273 if (skb_headroom(skb) < padsize)
1274 return -1;
1275 skb_push(skb, padsize);
1bc14880 1276 memmove(skb->data, skb->data + padsize, padpos);
8feceb67
VT
1277 }
1278
84642d6b
FF
1279 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
1280 txctl.txq = &sc->tx.txq[qnum];
528f0c6b 1281
c46917bb 1282 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
8feceb67 1283
c52f33d0 1284 if (ath_tx_start(hw, skb, &txctl) != 0) {
c46917bb 1285 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
528f0c6b 1286 goto exit;
8feceb67
VT
1287 }
1288
528f0c6b
S
1289 return 0;
1290exit:
1291 dev_kfree_skb_any(skb);
8feceb67 1292 return 0;
f078f209
LR
1293}
1294
8feceb67 1295static void ath9k_stop(struct ieee80211_hw *hw)
f078f209 1296{
bce048d7
JM
1297 struct ath_wiphy *aphy = hw->priv;
1298 struct ath_softc *sc = aphy->sc;
af03abec 1299 struct ath_hw *ah = sc->sc_ah;
c46917bb 1300 struct ath_common *common = ath9k_hw_common(ah);
447a42c2 1301 int i;
f078f209 1302
4c483817
S
1303 mutex_lock(&sc->mutex);
1304
9580a222
JM
1305 aphy->state = ATH_WIPHY_INACTIVE;
1306
9a75c2ff
VN
1307 if (led_blink)
1308 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1309
c94dbff7 1310 cancel_delayed_work_sync(&sc->tx_complete_work);
9f42c2b6 1311 cancel_work_sync(&sc->paprd_work);
347809fc 1312 cancel_work_sync(&sc->hw_check_work);
c94dbff7 1313
447a42c2
RM
1314 for (i = 0; i < sc->num_sec_wiphy; i++) {
1315 if (sc->sec_wiphy[i])
1316 break;
1317 }
1318
1319 if (i == sc->num_sec_wiphy) {
c94dbff7
LR
1320 cancel_delayed_work_sync(&sc->wiphy_work);
1321 cancel_work_sync(&sc->chan_work);
1322 }
1323
9c84b797 1324 if (sc->sc_flags & SC_OP_INVALID) {
c46917bb 1325 ath_print(common, ATH_DBG_ANY, "Device not present\n");
4c483817 1326 mutex_unlock(&sc->mutex);
9c84b797
S
1327 return;
1328 }
8feceb67 1329
9580a222
JM
1330 if (ath9k_wiphy_started(sc)) {
1331 mutex_unlock(&sc->mutex);
1332 return; /* another wiphy still in use */
1333 }
1334
3867cf6a
S
1335 /* Ensure HW is awake when we try to shut it down. */
1336 ath9k_ps_wakeup(sc);
1337
766ec4a9 1338 if (ah->btcoex_hw.enabled) {
af03abec 1339 ath9k_hw_btcoex_disable(ah);
766ec4a9 1340 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
75d7839f 1341 ath9k_btcoex_timer_pause(sc);
1773912b
VT
1342 }
1343
ff37e337
S
1344 /* make sure h/w will not generate any interrupt
1345 * before setting the invalid flag. */
af03abec 1346 ath9k_hw_set_interrupts(ah, 0);
ff37e337
S
1347
1348 if (!(sc->sc_flags & SC_OP_INVALID)) {
043a0405 1349 ath_drain_all_txq(sc, false);
ff37e337 1350 ath_stoprecv(sc);
af03abec 1351 ath9k_hw_phy_disable(ah);
ff37e337 1352 } else
b77f483f 1353 sc->rx.rxlink = NULL;
ff37e337 1354
ff37e337 1355 /* disable HAL and put h/w to sleep */
af03abec
LR
1356 ath9k_hw_disable(ah);
1357 ath9k_hw_configpcipowersave(ah, 1, 1);
3867cf6a
S
1358 ath9k_ps_restore(sc);
1359
1360 /* Finally, put the chip in FULL SLEEP mode */
9ecdef4b 1361 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
ff37e337
S
1362
1363 sc->sc_flags |= SC_OP_INVALID;
500c064d 1364
141b38b6
S
1365 mutex_unlock(&sc->mutex);
1366
c46917bb 1367 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
f078f209
LR
1368}
1369
8feceb67 1370static int ath9k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 1371 struct ieee80211_vif *vif)
f078f209 1372{
bce048d7
JM
1373 struct ath_wiphy *aphy = hw->priv;
1374 struct ath_softc *sc = aphy->sc;
3069168c
PR
1375 struct ath_hw *ah = sc->sc_ah;
1376 struct ath_common *common = ath9k_hw_common(ah);
1ed32e4f 1377 struct ath_vif *avp = (void *)vif->drv_priv;
d97809db 1378 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2c3db3d5 1379 int ret = 0;
8feceb67 1380
141b38b6
S
1381 mutex_lock(&sc->mutex);
1382
1ed32e4f 1383 switch (vif->type) {
05c914fe 1384 case NL80211_IFTYPE_STATION:
d97809db 1385 ic_opmode = NL80211_IFTYPE_STATION;
f078f209 1386 break;
05c914fe 1387 case NL80211_IFTYPE_ADHOC:
05c914fe 1388 case NL80211_IFTYPE_AP:
9cb5412b 1389 case NL80211_IFTYPE_MESH_POINT:
2c3db3d5
JM
1390 if (sc->nbcnvifs >= ATH_BCBUF) {
1391 ret = -ENOBUFS;
1392 goto out;
1393 }
1ed32e4f 1394 ic_opmode = vif->type;
f078f209
LR
1395 break;
1396 default:
c46917bb 1397 ath_print(common, ATH_DBG_FATAL,
1ed32e4f 1398 "Interface type %d not yet supported\n", vif->type);
2c3db3d5
JM
1399 ret = -EOPNOTSUPP;
1400 goto out;
f078f209
LR
1401 }
1402
c46917bb
LR
1403 ath_print(common, ATH_DBG_CONFIG,
1404 "Attach a VIF of type: %d\n", ic_opmode);
8feceb67 1405
17d7904d 1406 /* Set the VIF opmode */
5640b08e
S
1407 avp->av_opmode = ic_opmode;
1408 avp->av_bslot = -1;
1409
2c3db3d5 1410 sc->nvifs++;
8ca21f01 1411
364734fa 1412 ath9k_set_bssid_mask(hw, vif);
8ca21f01 1413
2c3db3d5
JM
1414 if (sc->nvifs > 1)
1415 goto out; /* skip global settings for secondary vif */
1416
b238e90e 1417 if (ic_opmode == NL80211_IFTYPE_AP) {
3069168c 1418 ath9k_hw_set_tsfadjust(ah, 1);
b238e90e
S
1419 sc->sc_flags |= SC_OP_TSF_RESET;
1420 }
5640b08e 1421
5640b08e 1422 /* Set the device opmode */
3069168c 1423 ah->opmode = ic_opmode;
5640b08e 1424
4e30ffa2
VN
1425 /*
1426 * Enable MIB interrupts when there are hardware phy counters.
1427 * Note we only do this (at the moment) for station mode.
1428 */
1ed32e4f
JB
1429 if ((vif->type == NL80211_IFTYPE_STATION) ||
1430 (vif->type == NL80211_IFTYPE_ADHOC) ||
1431 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
3448f912
LR
1432 if (ah->config.enable_ani)
1433 ah->imask |= ATH9K_INT_MIB;
3069168c 1434 ah->imask |= ATH9K_INT_TSFOOR;
4af9cf4f
S
1435 }
1436
3069168c 1437 ath9k_hw_set_interrupts(ah, ah->imask);
4e30ffa2 1438
1ed32e4f
JB
1439 if (vif->type == NL80211_IFTYPE_AP ||
1440 vif->type == NL80211_IFTYPE_ADHOC ||
6c3118e2
VT
1441 vif->type == NL80211_IFTYPE_MONITOR) {
1442 sc->sc_flags |= SC_OP_ANI_RUN;
3d536acf 1443 ath_start_ani(common);
6c3118e2 1444 }
6f255425 1445
2c3db3d5 1446out:
141b38b6 1447 mutex_unlock(&sc->mutex);
2c3db3d5 1448 return ret;
f078f209
LR
1449}
1450
8feceb67 1451static void ath9k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 1452 struct ieee80211_vif *vif)
f078f209 1453{
bce048d7
JM
1454 struct ath_wiphy *aphy = hw->priv;
1455 struct ath_softc *sc = aphy->sc;
c46917bb 1456 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1ed32e4f 1457 struct ath_vif *avp = (void *)vif->drv_priv;
2c3db3d5 1458 int i;
f078f209 1459
c46917bb 1460 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
f078f209 1461
141b38b6
S
1462 mutex_lock(&sc->mutex);
1463
6f255425 1464 /* Stop ANI */
6c3118e2 1465 sc->sc_flags &= ~SC_OP_ANI_RUN;
3d536acf 1466 del_timer_sync(&common->ani.timer);
580f0b8a 1467
8feceb67 1468 /* Reclaim beacon resources */
9cb5412b
PE
1469 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
1470 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
1471 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
5f70a88f 1472 ath9k_ps_wakeup(sc);
b77f483f 1473 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
5f70a88f 1474 ath9k_ps_restore(sc);
580f0b8a 1475 }
f078f209 1476
74401773 1477 ath_beacon_return(sc, avp);
8feceb67 1478 sc->sc_flags &= ~SC_OP_BEACONS;
f078f209 1479
2c3db3d5 1480 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1ed32e4f 1481 if (sc->beacon.bslot[i] == vif) {
2c3db3d5
JM
1482 printk(KERN_DEBUG "%s: vif had allocated beacon "
1483 "slot\n", __func__);
1484 sc->beacon.bslot[i] = NULL;
c52f33d0 1485 sc->beacon.bslot_aphy[i] = NULL;
2c3db3d5
JM
1486 }
1487 }
1488
17d7904d 1489 sc->nvifs--;
141b38b6
S
1490
1491 mutex_unlock(&sc->mutex);
f078f209
LR
1492}
1493
3f7c5c10
SB
1494void ath9k_enable_ps(struct ath_softc *sc)
1495{
3069168c
PR
1496 struct ath_hw *ah = sc->sc_ah;
1497
3f7c5c10 1498 sc->ps_enabled = true;
3069168c
PR
1499 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1500 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1501 ah->imask |= ATH9K_INT_TIM_TIMER;
1502 ath9k_hw_set_interrupts(ah, ah->imask);
3f7c5c10 1503 }
fdf76622 1504 ath9k_hw_setrxabort(ah, 1);
3f7c5c10 1505 }
3f7c5c10
SB
1506}
1507
e8975581 1508static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
f078f209 1509{
bce048d7
JM
1510 struct ath_wiphy *aphy = hw->priv;
1511 struct ath_softc *sc = aphy->sc;
c46917bb 1512 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
e8975581 1513 struct ieee80211_conf *conf = &hw->conf;
8782b41d 1514 struct ath_hw *ah = sc->sc_ah;
194b7c13 1515 bool disable_radio;
f078f209 1516
aa33de09 1517 mutex_lock(&sc->mutex);
141b38b6 1518
194b7c13
LR
1519 /*
1520 * Leave this as the first check because we need to turn on the
1521 * radio if it was disabled before prior to processing the rest
1522 * of the changes. Likewise we must only disable the radio towards
1523 * the end.
1524 */
64839170 1525 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
194b7c13
LR
1526 bool enable_radio;
1527 bool all_wiphys_idle;
1528 bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
64839170
LR
1529
1530 spin_lock_bh(&sc->wiphy_lock);
1531 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
194b7c13
LR
1532 ath9k_set_wiphy_idle(aphy, idle);
1533
11446011 1534 enable_radio = (!idle && all_wiphys_idle);
194b7c13
LR
1535
1536 /*
1537 * After we unlock here its possible another wiphy
1538 * can be re-renabled so to account for that we will
1539 * only disable the radio toward the end of this routine
1540 * if by then all wiphys are still idle.
1541 */
64839170
LR
1542 spin_unlock_bh(&sc->wiphy_lock);
1543
194b7c13 1544 if (enable_radio) {
1dbfd9d4 1545 sc->ps_idle = false;
68a89116 1546 ath_radio_enable(sc, hw);
c46917bb
LR
1547 ath_print(common, ATH_DBG_CONFIG,
1548 "not-idle: enabling radio\n");
64839170
LR
1549 }
1550 }
1551
e7824a50
LR
1552 /*
1553 * We just prepare to enable PS. We have to wait until our AP has
1554 * ACK'd our null data frame to disable RX otherwise we'll ignore
1555 * those ACKs and end up retransmitting the same null data frames.
1556 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1557 */
3cbb5dd7 1558 if (changed & IEEE80211_CONF_CHANGE_PS) {
8ab2cd09
LR
1559 unsigned long flags;
1560 spin_lock_irqsave(&sc->sc_pm_lock, flags);
3cbb5dd7 1561 if (conf->flags & IEEE80211_CONF_PS) {
1b04b930 1562 sc->ps_flags |= PS_ENABLED;
e7824a50
LR
1563 /*
1564 * At this point we know hardware has received an ACK
1565 * of a previously sent null data frame.
1566 */
1b04b930
S
1567 if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
1568 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
3f7c5c10 1569 ath9k_enable_ps(sc);
e7824a50 1570 }
3cbb5dd7 1571 } else {
96148326 1572 sc->ps_enabled = false;
1b04b930
S
1573 sc->ps_flags &= ~(PS_ENABLED |
1574 PS_NULLFUNC_COMPLETED);
8ab2cd09 1575 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
8782b41d
VN
1576 if (!(ah->caps.hw_caps &
1577 ATH9K_HW_CAP_AUTOSLEEP)) {
1578 ath9k_hw_setrxabort(sc->sc_ah, 0);
1b04b930
S
1579 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1580 PS_WAIT_FOR_CAB |
1581 PS_WAIT_FOR_PSPOLL_DATA |
1582 PS_WAIT_FOR_TX_ACK);
3069168c
PR
1583 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1584 ah->imask &= ~ATH9K_INT_TIM_TIMER;
8782b41d 1585 ath9k_hw_set_interrupts(sc->sc_ah,
3069168c 1586 ah->imask);
8782b41d 1587 }
3cbb5dd7
VN
1588 }
1589 }
8ab2cd09 1590 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
3cbb5dd7
VN
1591 }
1592
199afd9d
S
1593 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1594 if (conf->flags & IEEE80211_CONF_MONITOR) {
1595 ath_print(common, ATH_DBG_CONFIG,
1596 "HW opmode set to Monitor mode\n");
1597 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1598 }
1599 }
1600
4797938c 1601 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
99405f93 1602 struct ieee80211_channel *curchan = hw->conf.channel;
5f8e077c 1603 int pos = curchan->hw_value;
ae5eb026 1604
0e2dedf9
JM
1605 aphy->chan_idx = pos;
1606 aphy->chan_is_ht = conf_is_ht(conf);
5ee08656
FF
1607 if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
1608 sc->sc_flags |= SC_OP_OFFCHANNEL;
1609 else
1610 sc->sc_flags &= ~SC_OP_OFFCHANNEL;
0e2dedf9 1611
8089cc47
JM
1612 if (aphy->state == ATH_WIPHY_SCAN ||
1613 aphy->state == ATH_WIPHY_ACTIVE)
1614 ath9k_wiphy_pause_all_forced(sc, aphy);
1615 else {
1616 /*
1617 * Do not change operational channel based on a paused
1618 * wiphy changes.
1619 */
1620 goto skip_chan_change;
1621 }
0e2dedf9 1622
c46917bb
LR
1623 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
1624 curchan->center_freq);
f078f209 1625
5f8e077c 1626 /* XXX: remove me eventualy */
0e2dedf9 1627 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
e11602b7 1628
ecf70441 1629 ath_update_chainmask(sc, conf_is_ht(conf));
86060f0d 1630
0e2dedf9 1631 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
c46917bb
LR
1632 ath_print(common, ATH_DBG_FATAL,
1633 "Unable to set channel\n");
aa33de09 1634 mutex_unlock(&sc->mutex);
e11602b7
S
1635 return -EINVAL;
1636 }
094d05dc 1637 }
f078f209 1638
8089cc47 1639skip_chan_change:
c9f6a656 1640 if (changed & IEEE80211_CONF_CHANGE_POWER) {
17d7904d 1641 sc->config.txpowlimit = 2 * conf->power_level;
c9f6a656
LR
1642 ath_update_txpow(sc);
1643 }
f078f209 1644
194b7c13
LR
1645 spin_lock_bh(&sc->wiphy_lock);
1646 disable_radio = ath9k_all_wiphys_idle(sc);
1647 spin_unlock_bh(&sc->wiphy_lock);
1648
64839170 1649 if (disable_radio) {
c46917bb 1650 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
1dbfd9d4 1651 sc->ps_idle = true;
68a89116 1652 ath_radio_disable(sc, hw);
64839170
LR
1653 }
1654
aa33de09 1655 mutex_unlock(&sc->mutex);
141b38b6 1656
f078f209
LR
1657 return 0;
1658}
1659
8feceb67
VT
1660#define SUPPORTED_FILTERS \
1661 (FIF_PROMISC_IN_BSS | \
1662 FIF_ALLMULTI | \
1663 FIF_CONTROL | \
af6a3fc7 1664 FIF_PSPOLL | \
8feceb67
VT
1665 FIF_OTHER_BSS | \
1666 FIF_BCN_PRBRESP_PROMISC | \
1667 FIF_FCSFAIL)
c83be688 1668
8feceb67
VT
1669/* FIXME: sc->sc_full_reset ? */
1670static void ath9k_configure_filter(struct ieee80211_hw *hw,
1671 unsigned int changed_flags,
1672 unsigned int *total_flags,
3ac64bee 1673 u64 multicast)
8feceb67 1674{
bce048d7
JM
1675 struct ath_wiphy *aphy = hw->priv;
1676 struct ath_softc *sc = aphy->sc;
8feceb67 1677 u32 rfilt;
f078f209 1678
8feceb67
VT
1679 changed_flags &= SUPPORTED_FILTERS;
1680 *total_flags &= SUPPORTED_FILTERS;
f078f209 1681
b77f483f 1682 sc->rx.rxfilter = *total_flags;
aa68aeaa 1683 ath9k_ps_wakeup(sc);
8feceb67
VT
1684 rfilt = ath_calcrxfilter(sc);
1685 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
aa68aeaa 1686 ath9k_ps_restore(sc);
f078f209 1687
c46917bb
LR
1688 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
1689 "Set HW RX filter: 0x%x\n", rfilt);
8feceb67 1690}
f078f209 1691
4ca77860
JB
1692static int ath9k_sta_add(struct ieee80211_hw *hw,
1693 struct ieee80211_vif *vif,
1694 struct ieee80211_sta *sta)
8feceb67 1695{
bce048d7
JM
1696 struct ath_wiphy *aphy = hw->priv;
1697 struct ath_softc *sc = aphy->sc;
f078f209 1698
4ca77860
JB
1699 ath_node_attach(sc, sta);
1700
1701 return 0;
1702}
1703
1704static int ath9k_sta_remove(struct ieee80211_hw *hw,
1705 struct ieee80211_vif *vif,
1706 struct ieee80211_sta *sta)
1707{
1708 struct ath_wiphy *aphy = hw->priv;
1709 struct ath_softc *sc = aphy->sc;
1710
1711 ath_node_detach(sc, sta);
1712
1713 return 0;
f078f209
LR
1714}
1715
141b38b6 1716static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
8feceb67 1717 const struct ieee80211_tx_queue_params *params)
f078f209 1718{
bce048d7
JM
1719 struct ath_wiphy *aphy = hw->priv;
1720 struct ath_softc *sc = aphy->sc;
c46917bb 1721 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67
VT
1722 struct ath9k_tx_queue_info qi;
1723 int ret = 0, qnum;
f078f209 1724
8feceb67
VT
1725 if (queue >= WME_NUM_AC)
1726 return 0;
f078f209 1727
141b38b6
S
1728 mutex_lock(&sc->mutex);
1729
1ffb0610
S
1730 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1731
8feceb67
VT
1732 qi.tqi_aifs = params->aifs;
1733 qi.tqi_cwmin = params->cw_min;
1734 qi.tqi_cwmax = params->cw_max;
1735 qi.tqi_burstTime = params->txop;
1736 qnum = ath_get_hal_qnum(queue, sc);
f078f209 1737
c46917bb
LR
1738 ath_print(common, ATH_DBG_CONFIG,
1739 "Configure tx [queue/halq] [%d/%d], "
1740 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1741 queue, qnum, params->aifs, params->cw_min,
1742 params->cw_max, params->txop);
f078f209 1743
8feceb67
VT
1744 ret = ath_txq_update(sc, qnum, &qi);
1745 if (ret)
c46917bb 1746 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
f078f209 1747
94db2936 1748 if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
1d2231e2 1749 if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
94db2936
VN
1750 ath_beaconq_config(sc);
1751
141b38b6
S
1752 mutex_unlock(&sc->mutex);
1753
8feceb67
VT
1754 return ret;
1755}
f078f209 1756
8feceb67
VT
1757static int ath9k_set_key(struct ieee80211_hw *hw,
1758 enum set_key_cmd cmd,
dc822b5d
JB
1759 struct ieee80211_vif *vif,
1760 struct ieee80211_sta *sta,
8feceb67
VT
1761 struct ieee80211_key_conf *key)
1762{
bce048d7
JM
1763 struct ath_wiphy *aphy = hw->priv;
1764 struct ath_softc *sc = aphy->sc;
c46917bb 1765 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
8feceb67 1766 int ret = 0;
f078f209 1767
b3bd89ce
JM
1768 if (modparam_nohwcrypt)
1769 return -ENOSPC;
1770
141b38b6 1771 mutex_lock(&sc->mutex);
3cbb5dd7 1772 ath9k_ps_wakeup(sc);
c46917bb 1773 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
f078f209 1774
8feceb67
VT
1775 switch (cmd) {
1776 case SET_KEY:
040e539e 1777 ret = ath_key_config(common, vif, sta, key);
6ace2891
JM
1778 if (ret >= 0) {
1779 key->hw_key_idx = ret;
8feceb67
VT
1780 /* push IV and Michael MIC generation to stack */
1781 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
97359d12 1782 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
8feceb67 1783 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
97359d12
JB
1784 if (sc->sc_ah->sw_mgmt_crypto &&
1785 key->cipher == WLAN_CIPHER_SUITE_CCMP)
0ced0e17 1786 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
6ace2891 1787 ret = 0;
8feceb67
VT
1788 }
1789 break;
1790 case DISABLE_KEY:
040e539e 1791 ath_key_delete(common, key);
8feceb67
VT
1792 break;
1793 default:
1794 ret = -EINVAL;
1795 }
f078f209 1796
3cbb5dd7 1797 ath9k_ps_restore(sc);
141b38b6
S
1798 mutex_unlock(&sc->mutex);
1799
8feceb67
VT
1800 return ret;
1801}
f078f209 1802
8feceb67
VT
1803static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1804 struct ieee80211_vif *vif,
1805 struct ieee80211_bss_conf *bss_conf,
1806 u32 changed)
1807{
bce048d7
JM
1808 struct ath_wiphy *aphy = hw->priv;
1809 struct ath_softc *sc = aphy->sc;
2d0ddec5 1810 struct ath_hw *ah = sc->sc_ah;
1510718d 1811 struct ath_common *common = ath9k_hw_common(ah);
2d0ddec5 1812 struct ath_vif *avp = (void *)vif->drv_priv;
0005baf4 1813 int slottime;
c6089ccc 1814 int error;
f078f209 1815
141b38b6
S
1816 mutex_lock(&sc->mutex);
1817
c6089ccc
S
1818 if (changed & BSS_CHANGED_BSSID) {
1819 /* Set BSSID */
1820 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1821 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1510718d 1822 common->curaid = 0;
f2b2143e 1823 ath9k_hw_write_associd(ah);
2d0ddec5 1824
c6089ccc
S
1825 /* Set aggregation protection mode parameters */
1826 sc->config.ath_aggr_prot = 0;
2d0ddec5 1827
c6089ccc
S
1828 /* Only legacy IBSS for now */
1829 if (vif->type == NL80211_IFTYPE_ADHOC)
1830 ath_update_chainmask(sc, 0);
2d0ddec5 1831
c6089ccc
S
1832 ath_print(common, ATH_DBG_CONFIG,
1833 "BSSID: %pM aid: 0x%x\n",
1834 common->curbssid, common->curaid);
2d0ddec5 1835
c6089ccc
S
1836 /* need to reconfigure the beacon */
1837 sc->sc_flags &= ~SC_OP_BEACONS ;
1838 }
2d0ddec5 1839
c6089ccc
S
1840 /* Enable transmission of beacons (AP, IBSS, MESH) */
1841 if ((changed & BSS_CHANGED_BEACON) ||
1842 ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
1843 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1844 error = ath_beacon_alloc(aphy, vif);
1845 if (!error)
1846 ath_beacon_config(sc, vif);
0005baf4
FF
1847 }
1848
1849 if (changed & BSS_CHANGED_ERP_SLOT) {
1850 if (bss_conf->use_short_slot)
1851 slottime = 9;
1852 else
1853 slottime = 20;
1854 if (vif->type == NL80211_IFTYPE_AP) {
1855 /*
1856 * Defer update, so that connected stations can adjust
1857 * their settings at the same time.
1858 * See beacon.c for more details
1859 */
1860 sc->beacon.slottime = slottime;
1861 sc->beacon.updateslot = UPDATE;
1862 } else {
1863 ah->slottime = slottime;
1864 ath9k_hw_init_global_settings(ah);
1865 }
2d0ddec5
JB
1866 }
1867
c6089ccc
S
1868 /* Disable transmission of beacons */
1869 if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
1870 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5 1871
c6089ccc
S
1872 if (changed & BSS_CHANGED_BEACON_INT) {
1873 sc->beacon_interval = bss_conf->beacon_int;
1874 /*
1875 * In case of AP mode, the HW TSF has to be reset
1876 * when the beacon interval changes.
1877 */
1878 if (vif->type == NL80211_IFTYPE_AP) {
1879 sc->sc_flags |= SC_OP_TSF_RESET;
1880 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2d0ddec5
JB
1881 error = ath_beacon_alloc(aphy, vif);
1882 if (!error)
1883 ath_beacon_config(sc, vif);
c6089ccc
S
1884 } else {
1885 ath_beacon_config(sc, vif);
2d0ddec5
JB
1886 }
1887 }
1888
8feceb67 1889 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
c46917bb
LR
1890 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
1891 bss_conf->use_short_preamble);
8feceb67
VT
1892 if (bss_conf->use_short_preamble)
1893 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
1894 else
1895 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
1896 }
f078f209 1897
8feceb67 1898 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
c46917bb
LR
1899 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
1900 bss_conf->use_cts_prot);
8feceb67
VT
1901 if (bss_conf->use_cts_prot &&
1902 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
1903 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
1904 else
1905 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
1906 }
f078f209 1907
8feceb67 1908 if (changed & BSS_CHANGED_ASSOC) {
c46917bb 1909 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
8feceb67 1910 bss_conf->assoc);
5640b08e 1911 ath9k_bss_assoc_info(sc, vif, bss_conf);
8feceb67 1912 }
141b38b6
S
1913
1914 mutex_unlock(&sc->mutex);
8feceb67 1915}
f078f209 1916
8feceb67
VT
1917static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
1918{
1919 u64 tsf;
bce048d7
JM
1920 struct ath_wiphy *aphy = hw->priv;
1921 struct ath_softc *sc = aphy->sc;
f078f209 1922
141b38b6
S
1923 mutex_lock(&sc->mutex);
1924 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1925 mutex_unlock(&sc->mutex);
f078f209 1926
8feceb67
VT
1927 return tsf;
1928}
f078f209 1929
3b5d665b
AF
1930static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
1931{
bce048d7
JM
1932 struct ath_wiphy *aphy = hw->priv;
1933 struct ath_softc *sc = aphy->sc;
3b5d665b 1934
141b38b6
S
1935 mutex_lock(&sc->mutex);
1936 ath9k_hw_settsf64(sc->sc_ah, tsf);
1937 mutex_unlock(&sc->mutex);
3b5d665b
AF
1938}
1939
8feceb67
VT
1940static void ath9k_reset_tsf(struct ieee80211_hw *hw)
1941{
bce048d7
JM
1942 struct ath_wiphy *aphy = hw->priv;
1943 struct ath_softc *sc = aphy->sc;
c83be688 1944
141b38b6 1945 mutex_lock(&sc->mutex);
21526d57
LR
1946
1947 ath9k_ps_wakeup(sc);
141b38b6 1948 ath9k_hw_reset_tsf(sc->sc_ah);
21526d57
LR
1949 ath9k_ps_restore(sc);
1950
141b38b6 1951 mutex_unlock(&sc->mutex);
8feceb67 1952}
f078f209 1953
8feceb67 1954static int ath9k_ampdu_action(struct ieee80211_hw *hw,
c951ad35 1955 struct ieee80211_vif *vif,
141b38b6
S
1956 enum ieee80211_ampdu_mlme_action action,
1957 struct ieee80211_sta *sta,
1958 u16 tid, u16 *ssn)
8feceb67 1959{
bce048d7
JM
1960 struct ath_wiphy *aphy = hw->priv;
1961 struct ath_softc *sc = aphy->sc;
8feceb67 1962 int ret = 0;
f078f209 1963
85ad181e
JB
1964 local_bh_disable();
1965
8feceb67
VT
1966 switch (action) {
1967 case IEEE80211_AMPDU_RX_START:
dca3edb8
S
1968 if (!(sc->sc_flags & SC_OP_RXAGGR))
1969 ret = -ENOTSUPP;
8feceb67
VT
1970 break;
1971 case IEEE80211_AMPDU_RX_STOP:
8feceb67
VT
1972 break;
1973 case IEEE80211_AMPDU_TX_START:
8b685ba9 1974 ath9k_ps_wakeup(sc);
f83da965 1975 ath_tx_aggr_start(sc, sta, tid, ssn);
c951ad35 1976 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1977 ath9k_ps_restore(sc);
8feceb67
VT
1978 break;
1979 case IEEE80211_AMPDU_TX_STOP:
8b685ba9 1980 ath9k_ps_wakeup(sc);
f83da965 1981 ath_tx_aggr_stop(sc, sta, tid);
c951ad35 1982 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
8b685ba9 1983 ath9k_ps_restore(sc);
8feceb67 1984 break;
b1720231 1985 case IEEE80211_AMPDU_TX_OPERATIONAL:
8b685ba9 1986 ath9k_ps_wakeup(sc);
8469cdef 1987 ath_tx_aggr_resume(sc, sta, tid);
8b685ba9 1988 ath9k_ps_restore(sc);
8469cdef 1989 break;
8feceb67 1990 default:
c46917bb
LR
1991 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1992 "Unknown AMPDU action\n");
8feceb67
VT
1993 }
1994
85ad181e
JB
1995 local_bh_enable();
1996
8feceb67 1997 return ret;
f078f209
LR
1998}
1999
62dad5b0
BP
2000static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
2001 struct survey_info *survey)
2002{
2003 struct ath_wiphy *aphy = hw->priv;
2004 struct ath_softc *sc = aphy->sc;
2005 struct ath_hw *ah = sc->sc_ah;
2006 struct ath_common *common = ath9k_hw_common(ah);
2007 struct ieee80211_conf *conf = &hw->conf;
2008
2009 if (idx != 0)
2010 return -ENOENT;
2011
2012 survey->channel = conf->channel;
2013 survey->filled = SURVEY_INFO_NOISE_DBM;
2014 survey->noise = common->ani.noise_floor;
2015
2016 return 0;
2017}
2018
0c98de65
S
2019static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2020{
bce048d7
JM
2021 struct ath_wiphy *aphy = hw->priv;
2022 struct ath_softc *sc = aphy->sc;
0c98de65 2023
3d832611 2024 mutex_lock(&sc->mutex);
8089cc47 2025 if (ath9k_wiphy_scanning(sc)) {
8089cc47 2026 /*
30888338
LR
2027 * There is a race here in mac80211 but fixing it requires
2028 * we revisit how we handle the scan complete callback.
2029 * After mac80211 fixes we will not have configured hardware
2030 * to the home channel nor would we have configured the RX
2031 * filter yet.
8089cc47 2032 */
3d832611 2033 mutex_unlock(&sc->mutex);
8089cc47
JM
2034 return;
2035 }
2036
2037 aphy->state = ATH_WIPHY_SCAN;
2038 ath9k_wiphy_pause_all_forced(sc, aphy);
0c98de65 2039 sc->sc_flags |= SC_OP_SCANNING;
3d832611 2040 mutex_unlock(&sc->mutex);
0c98de65
S
2041}
2042
30888338
LR
2043/*
2044 * XXX: this requires a revisit after the driver
2045 * scan_complete gets moved to another place/removed in mac80211.
2046 */
0c98de65
S
2047static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2048{
bce048d7
JM
2049 struct ath_wiphy *aphy = hw->priv;
2050 struct ath_softc *sc = aphy->sc;
0c98de65 2051
3d832611 2052 mutex_lock(&sc->mutex);
8089cc47 2053 aphy->state = ATH_WIPHY_ACTIVE;
0c98de65 2054 sc->sc_flags &= ~SC_OP_SCANNING;
3d832611 2055 mutex_unlock(&sc->mutex);
0c98de65
S
2056}
2057
e239d859
FF
2058static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
2059{
2060 struct ath_wiphy *aphy = hw->priv;
2061 struct ath_softc *sc = aphy->sc;
2062 struct ath_hw *ah = sc->sc_ah;
2063
2064 mutex_lock(&sc->mutex);
2065 ah->coverage_class = coverage_class;
2066 ath9k_hw_init_global_settings(ah);
2067 mutex_unlock(&sc->mutex);
2068}
2069
6baff7f9 2070struct ieee80211_ops ath9k_ops = {
8feceb67
VT
2071 .tx = ath9k_tx,
2072 .start = ath9k_start,
2073 .stop = ath9k_stop,
2074 .add_interface = ath9k_add_interface,
2075 .remove_interface = ath9k_remove_interface,
2076 .config = ath9k_config,
8feceb67 2077 .configure_filter = ath9k_configure_filter,
4ca77860
JB
2078 .sta_add = ath9k_sta_add,
2079 .sta_remove = ath9k_sta_remove,
8feceb67 2080 .conf_tx = ath9k_conf_tx,
8feceb67 2081 .bss_info_changed = ath9k_bss_info_changed,
8feceb67 2082 .set_key = ath9k_set_key,
8feceb67 2083 .get_tsf = ath9k_get_tsf,
3b5d665b 2084 .set_tsf = ath9k_set_tsf,
8feceb67 2085 .reset_tsf = ath9k_reset_tsf,
4233df6b 2086 .ampdu_action = ath9k_ampdu_action,
62dad5b0 2087 .get_survey = ath9k_get_survey,
0c98de65
S
2088 .sw_scan_start = ath9k_sw_scan_start,
2089 .sw_scan_complete = ath9k_sw_scan_complete,
3b319aae 2090 .rfkill_poll = ath9k_rfkill_poll_state,
e239d859 2091 .set_coverage_class = ath9k_set_coverage_class,
8feceb67 2092};