]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/ath/ath9k/mac.h
ath9k_hw: Fill rx_enable() for the AR9003 hardware family
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / mac.h
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394cf0a1 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
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3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef MAC_H
18#define MAC_H
19
a8c96d3b 20#define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \
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21 MS(ads->ds_rxstatus0, AR_RxRate) : \
22 (ads->ds_rxstatus3 >> 2) & 0xFF)
23
24#define set11nTries(_series, _index) \
25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
26
27#define set11nRate(_series, _index) \
28 (SM((_series)[_index].Rate, AR_XmitRate##_index))
29
30#define set11nPktDurRTSCTS(_series, _index) \
31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
33 AR_RTSCTSQual##_index : 0))
34
35#define set11nRateFlags(_series, _index) \
36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
37 AR_2040_##_index : 0) \
38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
39 AR_GI##_index : 0) \
40 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
41
42#define CCK_SIFS_TIME 10
43#define CCK_PREAMBLE_BITS 144
44#define CCK_PLCP_BITS 48
45
46#define OFDM_SIFS_TIME 16
47#define OFDM_PREAMBLE_TIME 20
48#define OFDM_PLCP_BITS 22
49#define OFDM_SYMBOL_TIME 4
50
51#define OFDM_SIFS_TIME_HALF 32
52#define OFDM_PREAMBLE_TIME_HALF 40
53#define OFDM_PLCP_BITS_HALF 22
54#define OFDM_SYMBOL_TIME_HALF 8
55
56#define OFDM_SIFS_TIME_QUARTER 64
57#define OFDM_PREAMBLE_TIME_QUARTER 80
58#define OFDM_PLCP_BITS_QUARTER 22
59#define OFDM_SYMBOL_TIME_QUARTER 16
60
61#define INIT_AIFS 2
62#define INIT_CWMIN 15
63#define INIT_CWMIN_11B 31
64#define INIT_CWMAX 1023
65#define INIT_SH_RETRY 10
66#define INIT_LG_RETRY 10
67#define INIT_SSH_RETRY 32
68#define INIT_SLG_RETRY 32
69
70#define ATH9K_SLOT_TIME_6 6
71#define ATH9K_SLOT_TIME_9 9
72#define ATH9K_SLOT_TIME_20 20
73
74#define ATH9K_TXERR_XRETRY 0x01
75#define ATH9K_TXERR_FILT 0x02
76#define ATH9K_TXERR_FIFO 0x04
77#define ATH9K_TXERR_XTXOP 0x08
78#define ATH9K_TXERR_TIMER_EXPIRED 0x10
e7824a50 79#define ATH9K_TX_ACKED 0x20
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80#define ATH9K_TXERR_MASK \
81 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
82 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
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83
84#define ATH9K_TX_BA 0x01
85#define ATH9K_TX_PWRMGMT 0x02
86#define ATH9K_TX_DESC_CFG_ERR 0x04
87#define ATH9K_TX_DATA_UNDERRUN 0x08
88#define ATH9K_TX_DELIM_UNDERRUN 0x10
89#define ATH9K_TX_SW_ABORTED 0x40
90#define ATH9K_TX_SW_FILTERED 0x80
91
f4709fdf 92/* 64 bytes */
394cf0a1 93#define MIN_TX_FIFO_THRESHOLD 0x1
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94
95/*
96 * Single stream device AR9285 and AR9271 require 2 KB
97 * to work around a hardware issue, all other devices
98 * have can use the max 4 KB limit.
99 */
394cf0a1 100#define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
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101
102struct ath_tx_status {
103 u32 ts_tstamp;
104 u16 ts_seqnum;
105 u8 ts_status;
106 u8 ts_ratecode;
107 u8 ts_rateindex;
108 int8_t ts_rssi;
109 u8 ts_shortretry;
110 u8 ts_longretry;
111 u8 ts_virtcol;
112 u8 ts_antenna;
113 u8 ts_flags;
114 int8_t ts_rssi_ctl0;
115 int8_t ts_rssi_ctl1;
116 int8_t ts_rssi_ctl2;
117 int8_t ts_rssi_ext0;
118 int8_t ts_rssi_ext1;
119 int8_t ts_rssi_ext2;
120 u8 pad[3];
121 u32 ba_low;
122 u32 ba_high;
123 u32 evm0;
124 u32 evm1;
125 u32 evm2;
126};
127
128struct ath_rx_status {
129 u32 rs_tstamp;
130 u16 rs_datalen;
131 u8 rs_status;
132 u8 rs_phyerr;
133 int8_t rs_rssi;
134 u8 rs_keyix;
135 u8 rs_rate;
136 u8 rs_antenna;
137 u8 rs_more;
138 int8_t rs_rssi_ctl0;
139 int8_t rs_rssi_ctl1;
140 int8_t rs_rssi_ctl2;
141 int8_t rs_rssi_ext0;
142 int8_t rs_rssi_ext1;
143 int8_t rs_rssi_ext2;
144 u8 rs_isaggr;
145 u8 rs_moreaggr;
146 u8 rs_num_delims;
147 u8 rs_flags;
148 u32 evm0;
149 u32 evm1;
150 u32 evm2;
151};
152
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153struct ath_htc_rx_status {
154 u64 rs_tstamp;
155 u16 rs_datalen;
156 u8 rs_status;
157 u8 rs_phyerr;
158 int8_t rs_rssi;
159 int8_t rs_rssi_ctl0;
160 int8_t rs_rssi_ctl1;
161 int8_t rs_rssi_ctl2;
162 int8_t rs_rssi_ext0;
163 int8_t rs_rssi_ext1;
164 int8_t rs_rssi_ext2;
165 u8 rs_keyix;
166 u8 rs_rate;
167 u8 rs_antenna;
168 u8 rs_more;
169 u8 rs_isaggr;
170 u8 rs_moreaggr;
171 u8 rs_num_delims;
172 u8 rs_flags;
173 u8 rs_dummy;
174 u32 evm0;
175 u32 evm1;
176 u32 evm2;
177};
178
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179#define ATH9K_RXERR_CRC 0x01
180#define ATH9K_RXERR_PHY 0x02
181#define ATH9K_RXERR_FIFO 0x04
182#define ATH9K_RXERR_DECRYPT 0x08
183#define ATH9K_RXERR_MIC 0x10
184
185#define ATH9K_RX_MORE 0x01
186#define ATH9K_RX_MORE_AGGR 0x02
187#define ATH9K_RX_GI 0x04
188#define ATH9K_RX_2040 0x08
189#define ATH9K_RX_DELIM_CRC_PRE 0x10
190#define ATH9K_RX_DELIM_CRC_POST 0x20
191#define ATH9K_RX_DECRYPT_BUSY 0x40
192
193#define ATH9K_RXKEYIX_INVALID ((u8)-1)
194#define ATH9K_TXKEYIX_INVALID ((u32)-1)
195
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196enum ath9k_phyerr {
197 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */
198 ATH9K_PHYERR_TIMING = 1, /* Timing error */
199 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */
200 ATH9K_PHYERR_RATE = 3, /* Illegal rate */
201 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */
202 ATH9K_PHYERR_RADAR = 5, /* Radar detect */
203 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */
204 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */
205
206 ATH9K_PHYERR_OFDM_TIMING = 17,
207 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18,
208 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19,
209 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20,
210 ATH9K_PHYERR_OFDM_POWER_DROP = 21,
211 ATH9K_PHYERR_OFDM_SERVICE = 22,
212 ATH9K_PHYERR_OFDM_RESTART = 23,
213 ATH9K_PHYERR_FALSE_RADAR_EXT = 24,
214
215 ATH9K_PHYERR_CCK_TIMING = 25,
216 ATH9K_PHYERR_CCK_HEADER_CRC = 26,
217 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27,
218 ATH9K_PHYERR_CCK_SERVICE = 30,
219 ATH9K_PHYERR_CCK_RESTART = 31,
220 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32,
221 ATH9K_PHYERR_CCK_POWER_DROP = 33,
222
223 ATH9K_PHYERR_HT_CRC_ERROR = 34,
224 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35,
225 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36,
226
227 ATH9K_PHYERR_MAX = 37,
228};
229
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230struct ath_desc {
231 u32 ds_link;
232 u32 ds_data;
233 u32 ds_ctl0;
234 u32 ds_ctl1;
235 u32 ds_hw[20];
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236 void *ds_vdata;
237} __packed;
238
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239#define ATH9K_TXDESC_CLRDMASK 0x0001
240#define ATH9K_TXDESC_NOACK 0x0002
241#define ATH9K_TXDESC_RTSENA 0x0004
242#define ATH9K_TXDESC_CTSENA 0x0008
243/* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
244 * the descriptor its marked on. We take a tx interrupt to reap
245 * descriptors when the h/w hits an EOL condition or
246 * when the descriptor is specifically marked to generate
247 * an interrupt with this flag. Descriptors should be
248 * marked periodically to insure timely replenishing of the
249 * supply needed for sending frames. Defering interrupts
250 * reduces system load and potentially allows more concurrent
251 * work to be done but if done to aggressively can cause
252 * senders to backup. When the hardware queue is left too
253 * large rate control information may also be too out of
254 * date. An Alternative for this is TX interrupt mitigation
255 * but this needs more testing. */
256#define ATH9K_TXDESC_INTREQ 0x0010
257#define ATH9K_TXDESC_VEOL 0x0020
258#define ATH9K_TXDESC_EXT_ONLY 0x0040
259#define ATH9K_TXDESC_EXT_AND_CTL 0x0080
260#define ATH9K_TXDESC_VMF 0x0100
261#define ATH9K_TXDESC_FRAG_IS_ON 0x0200
262#define ATH9K_TXDESC_CAB 0x0400
263
264#define ATH9K_RXDESC_INTREQ 0x0020
265
266struct ar5416_desc {
267 u32 ds_link;
268 u32 ds_data;
269 u32 ds_ctl0;
270 u32 ds_ctl1;
271 union {
272 struct {
273 u32 ctl2;
274 u32 ctl3;
275 u32 ctl4;
276 u32 ctl5;
277 u32 ctl6;
278 u32 ctl7;
279 u32 ctl8;
280 u32 ctl9;
281 u32 ctl10;
282 u32 ctl11;
283 u32 status0;
284 u32 status1;
285 u32 status2;
286 u32 status3;
287 u32 status4;
288 u32 status5;
289 u32 status6;
290 u32 status7;
291 u32 status8;
292 u32 status9;
293 } tx;
294 struct {
295 u32 status0;
296 u32 status1;
297 u32 status2;
298 u32 status3;
299 u32 status4;
300 u32 status5;
301 u32 status6;
302 u32 status7;
303 u32 status8;
304 } rx;
305 } u;
306} __packed;
307
308#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
309#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
310
311#define ds_ctl2 u.tx.ctl2
312#define ds_ctl3 u.tx.ctl3
313#define ds_ctl4 u.tx.ctl4
314#define ds_ctl5 u.tx.ctl5
315#define ds_ctl6 u.tx.ctl6
316#define ds_ctl7 u.tx.ctl7
317#define ds_ctl8 u.tx.ctl8
318#define ds_ctl9 u.tx.ctl9
319#define ds_ctl10 u.tx.ctl10
320#define ds_ctl11 u.tx.ctl11
321
322#define ds_txstatus0 u.tx.status0
323#define ds_txstatus1 u.tx.status1
324#define ds_txstatus2 u.tx.status2
325#define ds_txstatus3 u.tx.status3
326#define ds_txstatus4 u.tx.status4
327#define ds_txstatus5 u.tx.status5
328#define ds_txstatus6 u.tx.status6
329#define ds_txstatus7 u.tx.status7
330#define ds_txstatus8 u.tx.status8
331#define ds_txstatus9 u.tx.status9
332
333#define ds_rxstatus0 u.rx.status0
334#define ds_rxstatus1 u.rx.status1
335#define ds_rxstatus2 u.rx.status2
336#define ds_rxstatus3 u.rx.status3
337#define ds_rxstatus4 u.rx.status4
338#define ds_rxstatus5 u.rx.status5
339#define ds_rxstatus6 u.rx.status6
340#define ds_rxstatus7 u.rx.status7
341#define ds_rxstatus8 u.rx.status8
342
343#define AR_FrameLen 0x00000fff
344#define AR_VirtMoreFrag 0x00001000
345#define AR_TxCtlRsvd00 0x0000e000
346#define AR_XmitPower 0x003f0000
347#define AR_XmitPower_S 16
348#define AR_RTSEnable 0x00400000
349#define AR_VEOL 0x00800000
350#define AR_ClrDestMask 0x01000000
351#define AR_TxCtlRsvd01 0x1e000000
352#define AR_TxIntrReq 0x20000000
353#define AR_DestIdxValid 0x40000000
354#define AR_CTSEnable 0x80000000
355
356#define AR_BufLen 0x00000fff
357#define AR_TxMore 0x00001000
358#define AR_DestIdx 0x000fe000
359#define AR_DestIdx_S 13
360#define AR_FrameType 0x00f00000
361#define AR_FrameType_S 20
362#define AR_NoAck 0x01000000
363#define AR_InsertTS 0x02000000
364#define AR_CorruptFCS 0x04000000
365#define AR_ExtOnly 0x08000000
366#define AR_ExtAndCtl 0x10000000
367#define AR_MoreAggr 0x20000000
368#define AR_IsAggr 0x40000000
369
370#define AR_BurstDur 0x00007fff
371#define AR_BurstDur_S 0
372#define AR_DurUpdateEna 0x00008000
373#define AR_XmitDataTries0 0x000f0000
374#define AR_XmitDataTries0_S 16
375#define AR_XmitDataTries1 0x00f00000
376#define AR_XmitDataTries1_S 20
377#define AR_XmitDataTries2 0x0f000000
378#define AR_XmitDataTries2_S 24
379#define AR_XmitDataTries3 0xf0000000
380#define AR_XmitDataTries3_S 28
381
382#define AR_XmitRate0 0x000000ff
383#define AR_XmitRate0_S 0
384#define AR_XmitRate1 0x0000ff00
385#define AR_XmitRate1_S 8
386#define AR_XmitRate2 0x00ff0000
387#define AR_XmitRate2_S 16
388#define AR_XmitRate3 0xff000000
389#define AR_XmitRate3_S 24
390
391#define AR_PacketDur0 0x00007fff
392#define AR_PacketDur0_S 0
393#define AR_RTSCTSQual0 0x00008000
394#define AR_PacketDur1 0x7fff0000
395#define AR_PacketDur1_S 16
396#define AR_RTSCTSQual1 0x80000000
397
398#define AR_PacketDur2 0x00007fff
399#define AR_PacketDur2_S 0
400#define AR_RTSCTSQual2 0x00008000
401#define AR_PacketDur3 0x7fff0000
402#define AR_PacketDur3_S 16
403#define AR_RTSCTSQual3 0x80000000
404
405#define AR_AggrLen 0x0000ffff
406#define AR_AggrLen_S 0
407#define AR_TxCtlRsvd60 0x00030000
408#define AR_PadDelim 0x03fc0000
409#define AR_PadDelim_S 18
410#define AR_EncrType 0x0c000000
411#define AR_EncrType_S 26
412#define AR_TxCtlRsvd61 0xf0000000
413
414#define AR_2040_0 0x00000001
415#define AR_GI0 0x00000002
416#define AR_ChainSel0 0x0000001c
417#define AR_ChainSel0_S 2
418#define AR_2040_1 0x00000020
419#define AR_GI1 0x00000040
420#define AR_ChainSel1 0x00000380
421#define AR_ChainSel1_S 7
422#define AR_2040_2 0x00000400
423#define AR_GI2 0x00000800
424#define AR_ChainSel2 0x00007000
425#define AR_ChainSel2_S 12
426#define AR_2040_3 0x00008000
427#define AR_GI3 0x00010000
428#define AR_ChainSel3 0x000e0000
429#define AR_ChainSel3_S 17
430#define AR_RTSCTSRate 0x0ff00000
431#define AR_RTSCTSRate_S 20
432#define AR_TxCtlRsvd70 0xf0000000
433
434#define AR_TxRSSIAnt00 0x000000ff
435#define AR_TxRSSIAnt00_S 0
436#define AR_TxRSSIAnt01 0x0000ff00
437#define AR_TxRSSIAnt01_S 8
438#define AR_TxRSSIAnt02 0x00ff0000
439#define AR_TxRSSIAnt02_S 16
440#define AR_TxStatusRsvd00 0x3f000000
441#define AR_TxBaStatus 0x40000000
442#define AR_TxStatusRsvd01 0x80000000
443
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444/*
445 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
446 * transmitted successfully. If clear, no ACK or BA was received to indicate
447 * successful transmission when we were expecting an ACK or BA.
448 */
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449#define AR_FrmXmitOK 0x00000001
450#define AR_ExcessiveRetries 0x00000002
451#define AR_FIFOUnderrun 0x00000004
452#define AR_Filtered 0x00000008
453#define AR_RTSFailCnt 0x000000f0
454#define AR_RTSFailCnt_S 4
455#define AR_DataFailCnt 0x00000f00
456#define AR_DataFailCnt_S 8
457#define AR_VirtRetryCnt 0x0000f000
458#define AR_VirtRetryCnt_S 12
459#define AR_TxDelimUnderrun 0x00010000
460#define AR_TxDataUnderrun 0x00020000
461#define AR_DescCfgErr 0x00040000
462#define AR_TxTimerExpired 0x00080000
463#define AR_TxStatusRsvd10 0xfff00000
464
465#define AR_SendTimestamp ds_txstatus2
466#define AR_BaBitmapLow ds_txstatus3
467#define AR_BaBitmapHigh ds_txstatus4
468
469#define AR_TxRSSIAnt10 0x000000ff
470#define AR_TxRSSIAnt10_S 0
471#define AR_TxRSSIAnt11 0x0000ff00
472#define AR_TxRSSIAnt11_S 8
473#define AR_TxRSSIAnt12 0x00ff0000
474#define AR_TxRSSIAnt12_S 16
475#define AR_TxRSSICombined 0xff000000
476#define AR_TxRSSICombined_S 24
477
478#define AR_TxEVM0 ds_txstatus5
479#define AR_TxEVM1 ds_txstatus6
480#define AR_TxEVM2 ds_txstatus7
481
482#define AR_TxDone 0x00000001
483#define AR_SeqNum 0x00001ffe
484#define AR_SeqNum_S 1
485#define AR_TxStatusRsvd80 0x0001e000
486#define AR_TxOpExceeded 0x00020000
487#define AR_TxStatusRsvd81 0x001c0000
488#define AR_FinalTxIdx 0x00600000
489#define AR_FinalTxIdx_S 21
490#define AR_TxStatusRsvd82 0x01800000
491#define AR_PowerMgmt 0x02000000
492#define AR_TxStatusRsvd83 0xfc000000
493
494#define AR_RxCTLRsvd00 0xffffffff
495
496#define AR_BufLen 0x00000fff
497#define AR_RxCtlRsvd00 0x00001000
498#define AR_RxIntrReq 0x00002000
499#define AR_RxCtlRsvd01 0xffffc000
500
501#define AR_RxRSSIAnt00 0x000000ff
502#define AR_RxRSSIAnt00_S 0
503#define AR_RxRSSIAnt01 0x0000ff00
504#define AR_RxRSSIAnt01_S 8
505#define AR_RxRSSIAnt02 0x00ff0000
506#define AR_RxRSSIAnt02_S 16
507#define AR_RxRate 0xff000000
508#define AR_RxRate_S 24
509#define AR_RxStatusRsvd00 0xff000000
510
511#define AR_DataLen 0x00000fff
512#define AR_RxMore 0x00001000
513#define AR_NumDelim 0x003fc000
514#define AR_NumDelim_S 14
515#define AR_RxStatusRsvd10 0xff800000
516
517#define AR_RcvTimestamp ds_rxstatus2
518
519#define AR_GI 0x00000001
520#define AR_2040 0x00000002
521#define AR_Parallel40 0x00000004
522#define AR_Parallel40_S 2
523#define AR_RxStatusRsvd30 0x000000f8
524#define AR_RxAntenna 0xffffff00
525#define AR_RxAntenna_S 8
526
527#define AR_RxRSSIAnt10 0x000000ff
528#define AR_RxRSSIAnt10_S 0
529#define AR_RxRSSIAnt11 0x0000ff00
530#define AR_RxRSSIAnt11_S 8
531#define AR_RxRSSIAnt12 0x00ff0000
532#define AR_RxRSSIAnt12_S 16
533#define AR_RxRSSICombined 0xff000000
534#define AR_RxRSSICombined_S 24
535
536#define AR_RxEVM0 ds_rxstatus4
537#define AR_RxEVM1 ds_rxstatus5
538#define AR_RxEVM2 ds_rxstatus6
539
540#define AR_RxDone 0x00000001
541#define AR_RxFrameOK 0x00000002
542#define AR_CRCErr 0x00000004
543#define AR_DecryptCRCErr 0x00000008
544#define AR_PHYErr 0x00000010
545#define AR_MichaelErr 0x00000020
546#define AR_PreDelimCRCErr 0x00000040
547#define AR_RxStatusRsvd70 0x00000080
548#define AR_RxKeyIdxValid 0x00000100
549#define AR_KeyIdx 0x0000fe00
550#define AR_KeyIdx_S 9
551#define AR_PHYErrCode 0x0000ff00
552#define AR_PHYErrCode_S 8
553#define AR_RxMoreAggr 0x00010000
554#define AR_RxAggr 0x00020000
555#define AR_PostDelimCRCErr 0x00040000
556#define AR_RxStatusRsvd71 0x3ff80000
557#define AR_DecryptBusyErr 0x40000000
558#define AR_KeyMiss 0x80000000
559
560enum ath9k_tx_queue {
561 ATH9K_TX_QUEUE_INACTIVE = 0,
562 ATH9K_TX_QUEUE_DATA,
563 ATH9K_TX_QUEUE_BEACON,
564 ATH9K_TX_QUEUE_CAB,
565 ATH9K_TX_QUEUE_UAPSD,
566 ATH9K_TX_QUEUE_PSPOLL
567};
568
569#define ATH9K_NUM_TX_QUEUES 10
570
571enum ath9k_tx_queue_subtype {
572 ATH9K_WME_AC_BK = 0,
573 ATH9K_WME_AC_BE,
574 ATH9K_WME_AC_VI,
575 ATH9K_WME_AC_VO,
576 ATH9K_WME_UPSD
577};
578
579enum ath9k_tx_queue_flags {
580 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
581 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
582 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
583 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
584 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
585 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
586 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
587 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
588 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
589};
590
591#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
592#define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
593
594#define ATH9K_DECOMP_MASK_SIZE 128
595#define ATH9K_READY_TIME_LO_BOUND 50
596#define ATH9K_READY_TIME_HI_BOUND 96
597
598enum ath9k_pkt_type {
599 ATH9K_PKT_TYPE_NORMAL = 0,
600 ATH9K_PKT_TYPE_ATIM,
601 ATH9K_PKT_TYPE_PSPOLL,
602 ATH9K_PKT_TYPE_BEACON,
603 ATH9K_PKT_TYPE_PROBE_RESP,
604 ATH9K_PKT_TYPE_CHIRP,
605 ATH9K_PKT_TYPE_GRP_POLL,
606};
607
608struct ath9k_tx_queue_info {
609 u32 tqi_ver;
610 enum ath9k_tx_queue tqi_type;
611 enum ath9k_tx_queue_subtype tqi_subtype;
612 enum ath9k_tx_queue_flags tqi_qflags;
613 u32 tqi_priority;
614 u32 tqi_aifs;
615 u32 tqi_cwmin;
616 u32 tqi_cwmax;
617 u16 tqi_shretry;
618 u16 tqi_lgretry;
619 u32 tqi_cbrPeriod;
620 u32 tqi_cbrOverflowLimit;
621 u32 tqi_burstTime;
622 u32 tqi_readyTime;
623 u32 tqi_physCompBuf;
624 u32 tqi_intFlags;
625};
626
627enum ath9k_rx_filter {
628 ATH9K_RX_FILTER_UCAST = 0x00000001,
629 ATH9K_RX_FILTER_MCAST = 0x00000002,
630 ATH9K_RX_FILTER_BCAST = 0x00000004,
631 ATH9K_RX_FILTER_CONTROL = 0x00000008,
632 ATH9K_RX_FILTER_BEACON = 0x00000010,
633 ATH9K_RX_FILTER_PROM = 0x00000020,
634 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
394cf0a1 635 ATH9K_RX_FILTER_PHYERR = 0x00000100,
dbaaa147 636 ATH9K_RX_FILTER_MYBEACON = 0x00000200,
7ea310be 637 ATH9K_RX_FILTER_COMP_BAR = 0x00000400,
dbaaa147 638 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
394cf0a1 639 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
b93bce2a 640 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000,
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641};
642
643#define ATH9K_RATESERIES_RTS_CTS 0x0001
644#define ATH9K_RATESERIES_2040 0x0002
645#define ATH9K_RATESERIES_HALFGI 0x0004
646
647struct ath9k_11n_rate_series {
648 u32 Tries;
649 u32 Rate;
650 u32 PktDuration;
651 u32 ChSel;
652 u32 RateFlags;
653};
654
655struct ath9k_keyval {
656 u8 kv_type;
657 u8 kv_pad;
658 u16 kv_len;
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659 u8 kv_val[16]; /* TK */
660 u8 kv_mic[8]; /* Michael MIC key */
661 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
662 * supports both MIC keys in the same key cache entry;
663 * in that case, kv_mic is the RX key) */
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664};
665
666enum ath9k_key_type {
667 ATH9K_KEY_TYPE_CLEAR,
668 ATH9K_KEY_TYPE_WEP,
669 ATH9K_KEY_TYPE_AES,
670 ATH9K_KEY_TYPE_TKIP,
671};
672
673enum ath9k_cipher {
674 ATH9K_CIPHER_WEP = 0,
675 ATH9K_CIPHER_AES_OCB = 1,
676 ATH9K_CIPHER_AES_CCM = 2,
677 ATH9K_CIPHER_CKIP = 3,
678 ATH9K_CIPHER_TKIP = 4,
679 ATH9K_CIPHER_CLR = 5,
680 ATH9K_CIPHER_MIC = 127
681};
682
cbe61d8a 683struct ath_hw;
394cf0a1 684struct ath9k_channel;
394cf0a1 685
cbe61d8a 686u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q);
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687void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp);
688void ath9k_hw_txstart(struct ath_hw *ah, u32 q);
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689u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q);
690bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel);
691bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q);
54e4cec6 692void ath9k_hw_filltxdesc(struct ath_hw *ah, struct ath_desc *ds,
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693 u32 segLen, bool firstSeg,
694 bool lastSeg, const struct ath_desc *ds0);
cbe61d8a 695void ath9k_hw_cleartxdesc(struct ath_hw *ah, struct ath_desc *ds);
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696int ath9k_hw_txprocdesc(struct ath_hw *ah, struct ath_desc *ds,
697 struct ath_tx_status *ts);
cbe61d8a 698void ath9k_hw_set11n_txdesc(struct ath_hw *ah, struct ath_desc *ds,
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699 u32 pktLen, enum ath9k_pkt_type type, u32 txPower,
700 u32 keyIx, enum ath9k_key_type keyType, u32 flags);
cbe61d8a 701void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, struct ath_desc *ds,
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702 struct ath_desc *lastds,
703 u32 durUpdateEn, u32 rtsctsRate,
704 u32 rtsctsDuration,
705 struct ath9k_11n_rate_series series[],
706 u32 nseries, u32 flags);
cbe61d8a 707void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, struct ath_desc *ds,
394cf0a1 708 u32 aggrLen);
cbe61d8a 709void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, struct ath_desc *ds,
394cf0a1 710 u32 numDelims);
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711void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, struct ath_desc *ds);
712void ath9k_hw_clr11n_aggr(struct ath_hw *ah, struct ath_desc *ds);
713void ath9k_hw_set11n_burstduration(struct ath_hw *ah, struct ath_desc *ds,
394cf0a1 714 u32 burstDuration);
cbe61d8a 715void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, struct ath_desc *ds,
394cf0a1 716 u32 vmf);
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717void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs);
718bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
394cf0a1 719 const struct ath9k_tx_queue_info *qinfo);
cbe61d8a 720bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
394cf0a1 721 struct ath9k_tx_queue_info *qinfo);
cbe61d8a 722int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
394cf0a1 723 const struct ath9k_tx_queue_info *qinfo);
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724bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q);
725bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q);
726int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
8e6f5aa2 727 struct ath_rx_status *rs, u64 tsf);
54e4cec6 728void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds,
394cf0a1 729 u32 size, u32 flags);
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730bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set);
731void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp);
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732void ath9k_hw_startpcureceive(struct ath_hw *ah);
733void ath9k_hw_stoppcurecv(struct ath_hw *ah);
734bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
536b3a7a 735int ath9k_hw_beaconq_setup(struct ath_hw *ah);
394cf0a1 736
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737void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
738
394cf0a1 739#endif /* MAC_H */