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ath9k: fix regression which prevents chip sleep after CAB data
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / init.c
CommitLineData
55624204
S		 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
5a0e3ad6
TH		 17#include <linux/slab.h>
18
55624204
S		 19#include "ath9k.h"
20
21static char *dev_info = "ath9k";
22
23MODULE_AUTHOR("Atheros Communications");
24MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26MODULE_LICENSE("Dual BSD/GPL");
27
28static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
29module_param_named(debug, ath9k_debug, uint, 0);
30MODULE_PARM_DESC(debug, "Debugging mask");
31
32int modparam_nohwcrypt;
33module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
34MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
35
93dbbcc4 36int led_blink;
9a75c2ff
VN		 37module_param_named(blink, led_blink, int, 0444);
38MODULE_PARM_DESC(blink, "Enable LED blink on activity");
39
55624204
S		 40/* We use the hw_value as an index into our private channel structure */
41
42#define CHAN2G(_freq, _idx) { \
43 .center_freq = (_freq), \
44 .hw_value = (_idx), \
45 .max_power = 20, \
46}
47
48#define CHAN5G(_freq, _idx) { \
49 .band = IEEE80211_BAND_5GHZ, \
50 .center_freq = (_freq), \
51 .hw_value = (_idx), \
52 .max_power = 20, \
53}
54
55/* Some 2 GHz radios are actually tunable on 2312-2732
56 * on 5 MHz steps, we support the channels which we know
57 * we have calibration data for all cards though to make
58 * this static */
59static struct ieee80211_channel ath9k_2ghz_chantable[] = {
60 CHAN2G(2412, 0), /* Channel 1 */
61 CHAN2G(2417, 1), /* Channel 2 */
62 CHAN2G(2422, 2), /* Channel 3 */
63 CHAN2G(2427, 3), /* Channel 4 */
64 CHAN2G(2432, 4), /* Channel 5 */
65 CHAN2G(2437, 5), /* Channel 6 */
66 CHAN2G(2442, 6), /* Channel 7 */
67 CHAN2G(2447, 7), /* Channel 8 */
68 CHAN2G(2452, 8), /* Channel 9 */
69 CHAN2G(2457, 9), /* Channel 10 */
70 CHAN2G(2462, 10), /* Channel 11 */
71 CHAN2G(2467, 11), /* Channel 12 */
72 CHAN2G(2472, 12), /* Channel 13 */
73 CHAN2G(2484, 13), /* Channel 14 */
74};
75
76/* Some 5 GHz radios are actually tunable on XXXX-YYYY
77 * on 5 MHz steps, we support the channels which we know
78 * we have calibration data for all cards though to make
79 * this static */
80static struct ieee80211_channel ath9k_5ghz_chantable[] = {
81 /* _We_ call this UNII 1 */
82 CHAN5G(5180, 14), /* Channel 36 */
83 CHAN5G(5200, 15), /* Channel 40 */
84 CHAN5G(5220, 16), /* Channel 44 */
85 CHAN5G(5240, 17), /* Channel 48 */
86 /* _We_ call this UNII 2 */
87 CHAN5G(5260, 18), /* Channel 52 */
88 CHAN5G(5280, 19), /* Channel 56 */
89 CHAN5G(5300, 20), /* Channel 60 */
90 CHAN5G(5320, 21), /* Channel 64 */
91 /* _We_ call this "Middle band" */
92 CHAN5G(5500, 22), /* Channel 100 */
93 CHAN5G(5520, 23), /* Channel 104 */
94 CHAN5G(5540, 24), /* Channel 108 */
95 CHAN5G(5560, 25), /* Channel 112 */
96 CHAN5G(5580, 26), /* Channel 116 */
97 CHAN5G(5600, 27), /* Channel 120 */
98 CHAN5G(5620, 28), /* Channel 124 */
99 CHAN5G(5640, 29), /* Channel 128 */
100 CHAN5G(5660, 30), /* Channel 132 */
101 CHAN5G(5680, 31), /* Channel 136 */
102 CHAN5G(5700, 32), /* Channel 140 */
103 /* _We_ call this UNII 3 */
104 CHAN5G(5745, 33), /* Channel 149 */
105 CHAN5G(5765, 34), /* Channel 153 */
106 CHAN5G(5785, 35), /* Channel 157 */
107 CHAN5G(5805, 36), /* Channel 161 */
108 CHAN5G(5825, 37), /* Channel 165 */
109};
110
111/* Atheros hardware rate code addition for short premble */
112#define SHPCHECK(__hw_rate, __flags) \
113 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
114
115#define RATE(_bitrate, _hw_rate, _flags) { \
116 .bitrate = (_bitrate), \
117 .flags = (_flags), \
118 .hw_value = (_hw_rate), \
119 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
120}
121
122static struct ieee80211_rate ath9k_legacy_rates[] = {
123 RATE(10, 0x1b, 0),
124 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
126 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
127 RATE(60, 0x0b, 0),
128 RATE(90, 0x0f, 0),
129 RATE(120, 0x0a, 0),
130 RATE(180, 0x0e, 0),
131 RATE(240, 0x09, 0),
132 RATE(360, 0x0d, 0),
133 RATE(480, 0x08, 0),
134 RATE(540, 0x0c, 0),
135};
136
285f2dda 137static void ath9k_deinit_softc(struct ath_softc *sc);
55624204
S		 138
139/*
140 * Read and write, they both share the same lock. We do this to serialize
141 * reads and writes on Atheros 802.11n PCI devices only. This is required
142 * as the FIFO on these devices can only accept sanely 2 requests.
143 */
144
145static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
146{
147 struct ath_hw *ah = (struct ath_hw *) hw_priv;
148 struct ath_common *common = ath9k_hw_common(ah);
149 struct ath_softc *sc = (struct ath_softc *) common->priv;
150
151 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
152 unsigned long flags;
153 spin_lock_irqsave(&sc->sc_serial_rw, flags);
154 iowrite32(val, sc->mem + reg_offset);
155 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
156 } else
157 iowrite32(val, sc->mem + reg_offset);
158}
159
160static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
161{
162 struct ath_hw *ah = (struct ath_hw *) hw_priv;
163 struct ath_common *common = ath9k_hw_common(ah);
164 struct ath_softc *sc = (struct ath_softc *) common->priv;
165 u32 val;
166
167 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
168 unsigned long flags;
169 spin_lock_irqsave(&sc->sc_serial_rw, flags);
170 val = ioread32(sc->mem + reg_offset);
171 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
172 } else
173 val = ioread32(sc->mem + reg_offset);
174 return val;
175}
176
177static const struct ath_ops ath9k_common_ops = {
178 .read = ath9k_ioread32,
179 .write = ath9k_iowrite32,
180};
181
182/**************************/
183/* Initialization */
184/**************************/
185
186static void setup_ht_cap(struct ath_softc *sc,
187 struct ieee80211_sta_ht_cap *ht_info)
188{
3bb065a7
FF		 189 struct ath_hw *ah = sc->sc_ah;
190 struct ath_common *common = ath9k_hw_common(ah);
55624204 191 u8 tx_streams, rx_streams;
3bb065a7 192 int i, max_streams;
55624204
S		 193
194 ht_info->ht_supported = true;
195 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
196 IEEE80211_HT_CAP_SM_PS |
197 IEEE80211_HT_CAP_SGI_40 |
198 IEEE80211_HT_CAP_DSSSCCK40;
199
b0a33448
LR		 200 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
201 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
202
6473d24d
VT		 203 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
204 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
205
55624204
S		 206 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
207 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
208
3bb065a7
FF		 209 if (AR_SREV_9300_20_OR_LATER(ah))
210 max_streams = 3;
211 else
212 max_streams = 2;
213
074a8c0d
FF		 214 if (AR_SREV_9280_10_OR_LATER(ah)) {
215 if (max_streams >= 2)
216 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
217 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
218 }
219
55624204
S		 220 /* set up supported mcs set */
221 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
61389f3e
S		 222 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
223 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
3bb065a7
FF		 224
225 ath_print(common, ATH_DBG_CONFIG,
226 "TX streams %d, RX streams: %d\n",
227 tx_streams, rx_streams);
55624204
S		 228
229 if (tx_streams != rx_streams) {
55624204
S		 230 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
231 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
232 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
233 }
234
3bb065a7
FF		 235 for (i = 0; i < rx_streams; i++)
236 ht_info->mcs.rx_mask[i] = 0xff;
55624204
S		 237
238 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
239}
240
241static int ath9k_reg_notifier(struct wiphy *wiphy,
242 struct regulatory_request *request)
243{
244 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
245 struct ath_wiphy *aphy = hw->priv;
246 struct ath_softc *sc = aphy->sc;
247 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
248
249 return ath_reg_notifier_apply(wiphy, request, reg);
250}
251
252/*
253 * This function will allocate both the DMA descriptor structure, and the
254 * buffers it contains. These are used to contain the descriptors used
255 * by the system.
256*/
257int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
258 struct list_head *head, const char *name,
4adfcded 259 int nbuf, int ndesc, bool is_tx)
55624204
S		 260{
261#define DS2PHYS(_dd, _ds) \
262 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
263#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
264#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
265 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
4adfcded 266 u8 *ds;
55624204 267 struct ath_buf *bf;
4adfcded 268 int i, bsize, error, desc_len;
55624204
S		 269
270 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
271 name, nbuf, ndesc);
272
273 INIT_LIST_HEAD(head);
4adfcded
VT		 274
275 if (is_tx)
276 desc_len = sc->sc_ah->caps.tx_desc_len;
277 else
278 desc_len = sizeof(struct ath_desc);
279
55624204 280 /* ath_desc must be a multiple of DWORDs */
4adfcded 281 if ((desc_len % 4) != 0) {
55624204
S		 282 ath_print(common, ATH_DBG_FATAL,
283 "ath_desc not DWORD aligned\n");
4adfcded 284 BUG_ON((desc_len % 4) != 0);
55624204
S		 285 error = -ENOMEM;
286 goto fail;
287 }
288
4adfcded 289 dd->dd_desc_len = desc_len * nbuf * ndesc;
55624204
S		 290
291 /*
292 * Need additional DMA memory because we can't use
293 * descriptors that cross the 4K page boundary. Assume
294 * one skipped descriptor per 4K page.
295 */
296 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
297 u32 ndesc_skipped =
298 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
299 u32 dma_len;
300
301 while (ndesc_skipped) {
4adfcded 302 dma_len = ndesc_skipped * desc_len;
55624204
S		 303 dd->dd_desc_len += dma_len;
304
305 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
ee289b64 306 }
55624204
S		 307 }
308
309 /* allocate descriptors */
310 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
311 &dd->dd_desc_paddr, GFP_KERNEL);
312 if (dd->dd_desc == NULL) {
313 error = -ENOMEM;
314 goto fail;
315 }
4adfcded 316 ds = (u8 *) dd->dd_desc;
55624204
S		 317 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
318 name, ds, (u32) dd->dd_desc_len,
319 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
320
321 /* allocate buffers */
322 bsize = sizeof(struct ath_buf) * nbuf;
323 bf = kzalloc(bsize, GFP_KERNEL);
324 if (bf == NULL) {
325 error = -ENOMEM;
326 goto fail2;
327 }
328 dd->dd_bufptr = bf;
329
4adfcded 330 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
55624204
S		 331 bf->bf_desc = ds;
332 bf->bf_daddr = DS2PHYS(dd, ds);
333
334 if (!(sc->sc_ah->caps.hw_caps &
335 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
336 /*
337 * Skip descriptor addresses which can cause 4KB
338 * boundary crossing (addr + length) with a 32 dword
339 * descriptor fetch.
340 */
341 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
342 BUG_ON((caddr_t) bf->bf_desc >=
343 ((caddr_t) dd->dd_desc +
344 dd->dd_desc_len));
345
4adfcded 346 ds += (desc_len * ndesc);
55624204
S		 347 bf->bf_desc = ds;
348 bf->bf_daddr = DS2PHYS(dd, ds);
349 }
350 }
351 list_add_tail(&bf->list, head);
352 }
353 return 0;
354fail2:
355 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
356 dd->dd_desc_paddr);
357fail:
358 memset(dd, 0, sizeof(*dd));
359 return error;
360#undef ATH_DESC_4KB_BOUND_CHECK
361#undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
362#undef DS2PHYS
363}
364
285f2dda 365static void ath9k_init_crypto(struct ath_softc *sc)
55624204 366{
285f2dda
S		 367 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
368 int i = 0;
55624204
S		 369
370 /* Get the hardware key cache size. */
285f2dda 371 common->keymax = sc->sc_ah->caps.keycache_size;
55624204
S		 372 if (common->keymax > ATH_KEYMAX) {
373 ath_print(common, ATH_DBG_ANY,
374 "Warning, using only %u entries in %u key cache\n",
375 ATH_KEYMAX, common->keymax);
376 common->keymax = ATH_KEYMAX;
377 }
378
379 /*
380 * Reset the key cache since some parts do not
381 * reset the contents on initial power up.
382 */
383 for (i = 0; i < common->keymax; i++)
040e539e 384 ath_hw_keyreset(common, (u16) i);
55624204 385
55624204 386 /*
285f2dda
S		 387 * Check whether the separate key cache entries
388 * are required to handle both tx+rx MIC keys.
389 * With split mic keys the number of stations is limited
390 * to 27 otherwise 59.
55624204 391 */
117675d0
BR		 392 if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
393 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
285f2dda
S		 394}
395
396static int ath9k_init_btcoex(struct ath_softc *sc)
397{
398 int r, qnum;
399
400 switch (sc->sc_ah->btcoex_hw.scheme) {
401 case ATH_BTCOEX_CFG_NONE:
402 break;
403 case ATH_BTCOEX_CFG_2WIRE:
404 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
405 break;
406 case ATH_BTCOEX_CFG_3WIRE:
407 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
408 r = ath_init_btcoex_timer(sc);
409 if (r)
410 return -1;
1d2231e2 411 qnum = sc->tx.hwq_map[WME_AC_BE];
285f2dda
S		 412 ath9k_hw_init_btcoex_hw(sc->sc_ah, qnum);
413 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
414 break;
415 default:
416 WARN_ON(1);
417 break;
418 }
419
420 return 0;
421}
422
423static int ath9k_init_queues(struct ath_softc *sc)
424{
425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
426 int i = 0;
427
428 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
429 sc->tx.hwq_map[i] = -1;
430
431 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
55624204
S		 432 if (sc->beacon.beaconq == -1) {
433 ath_print(common, ATH_DBG_FATAL,
434 "Unable to setup a beacon xmit queue\n");
285f2dda 435 goto err;
55624204 436 }
285f2dda 437
55624204
S		 438 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
439 if (sc->beacon.cabq == NULL) {
440 ath_print(common, ATH_DBG_FATAL,
441 "Unable to setup CAB xmit queue\n");
285f2dda 442 goto err;
55624204
S		 443 }
444
445 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
446 ath_cabq_update(sc);
447
1d2231e2 448 if (!ath_tx_setup(sc, WME_AC_BK)) {
55624204
S		 449 ath_print(common, ATH_DBG_FATAL,
450 "Unable to setup xmit queue for BK traffic\n");
285f2dda 451 goto err;
55624204
S		 452 }
453
1d2231e2 454 if (!ath_tx_setup(sc, WME_AC_BE)) {
55624204
S		 455 ath_print(common, ATH_DBG_FATAL,
456 "Unable to setup xmit queue for BE traffic\n");
285f2dda 457 goto err;
55624204 458 }
1d2231e2 459 if (!ath_tx_setup(sc, WME_AC_VI)) {
55624204
S		 460 ath_print(common, ATH_DBG_FATAL,
461 "Unable to setup xmit queue for VI traffic\n");
285f2dda 462 goto err;
55624204 463 }
1d2231e2 464 if (!ath_tx_setup(sc, WME_AC_VO)) {
55624204
S		 465 ath_print(common, ATH_DBG_FATAL,
466 "Unable to setup xmit queue for VO traffic\n");
285f2dda 467 goto err;
55624204
S		 468 }
469
285f2dda 470 return 0;
55624204 471
285f2dda
S		 472err:
473 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
474 if (ATH_TXQ_SETUP(sc, i))
475 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
55624204 476
285f2dda
S		 477 return -EIO;
478}
479
480static void ath9k_init_channels_rates(struct ath_softc *sc)
481{
482 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes)) {
483 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
484 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
485 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
486 ARRAY_SIZE(ath9k_2ghz_chantable);
487 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
488 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
489 ARRAY_SIZE(ath9k_legacy_rates);
55624204
S		 490 }
491
285f2dda
S		 492 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
493 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
494 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
495 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
496 ARRAY_SIZE(ath9k_5ghz_chantable);
497 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
498 ath9k_legacy_rates + 4;
499 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
500 ARRAY_SIZE(ath9k_legacy_rates) - 4;
501 }
502}
55624204 503
285f2dda
S		 504static void ath9k_init_misc(struct ath_softc *sc)
505{
506 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
507 int i = 0;
508
509 common->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
510 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
55624204
S		 511
512 sc->config.txpowlimit = ATH_TXPOWER_MAX;
513
285f2dda 514 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
55624204
S		 515 sc->sc_flags |= SC_OP_TXAGGR;
516 sc->sc_flags |= SC_OP_RXAGGR;
517 }
518
285f2dda
S		 519 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
520 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
55624204 521
8fe65368 522 ath9k_hw_set_diversity(sc->sc_ah, true);
285f2dda 523 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
55624204 524
364734fa 525 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
55624204 526
285f2dda 527 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
55624204 528
55624204
S		 529 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
530 sc->beacon.bslot[i] = NULL;
531 sc->beacon.bslot_aphy[i] = NULL;
532 }
102885a5
VT		 533
534 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
535 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
285f2dda 536}
55624204 537
285f2dda
S		 538static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
539 const struct ath_bus_ops *bus_ops)
540{
541 struct ath_hw *ah = NULL;
542 struct ath_common *common;
543 int ret = 0, i;
544 int csz = 0;
55624204 545
285f2dda
S		 546 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
547 if (!ah)
548 return -ENOMEM;
549
550 ah->hw_version.devid = devid;
551 ah->hw_version.subsysid = subsysid;
552 sc->sc_ah = ah;
553
554 common = ath9k_hw_common(ah);
555 common->ops = &ath9k_common_ops;
556 common->bus_ops = bus_ops;
557 common->ah = ah;
558 common->hw = sc->hw;
559 common->priv = sc;
560 common->debug_mask = ath9k_debug;
561
562 spin_lock_init(&sc->wiphy_lock);
563 spin_lock_init(&sc->sc_resetlock);
564 spin_lock_init(&sc->sc_serial_rw);
565 spin_lock_init(&sc->sc_pm_lock);
566 mutex_init(&sc->mutex);
567 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
568 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
569 (unsigned long)sc);
570
571 /*
572 * Cache line size is used to size and align various
573 * structures used to communicate with the hardware.
574 */
575 ath_read_cachesize(common, &csz);
576 common->cachelsz = csz << 2; /* convert to bytes */
577
d70357d5 578 /* Initializes the hardware for all supported chipsets */
285f2dda 579 ret = ath9k_hw_init(ah);
d70357d5 580 if (ret)
285f2dda 581 goto err_hw;
55624204 582
285f2dda
S		 583 ret = ath9k_init_debug(ah);
584 if (ret) {
585 ath_print(common, ATH_DBG_FATAL,
586 "Unable to create debugfs files\n");
587 goto err_debug;
55624204
S		 588 }
589
285f2dda
S		 590 ret = ath9k_init_queues(sc);
591 if (ret)
592 goto err_queues;
593
594 ret = ath9k_init_btcoex(sc);
595 if (ret)
596 goto err_btcoex;
597
598 ath9k_init_crypto(sc);
599 ath9k_init_channels_rates(sc);
600 ath9k_init_misc(sc);
601
55624204 602 return 0;
285f2dda
S		 603
604err_btcoex:
55624204
S		 605 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
606 if (ATH_TXQ_SETUP(sc, i))
607 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
285f2dda
S		 608err_queues:
609 ath9k_exit_debug(ah);
610err_debug:
611 ath9k_hw_deinit(ah);
612err_hw:
613 tasklet_kill(&sc->intr_tq);
614 tasklet_kill(&sc->bcon_tasklet);
55624204 615
285f2dda
S		 616 kfree(ah);
617 sc->sc_ah = NULL;
618
619 return ret;
55624204
S		 620}
621
285f2dda 622void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
55624204 623{
285f2dda
S		 624 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
625
55624204
S		 626 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
627 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
628 IEEE80211_HW_SIGNAL_DBM |
55624204
S		 629 IEEE80211_HW_SUPPORTS_PS |
630 IEEE80211_HW_PS_NULLFUNC_STACK |
05df4986
VN		 631 IEEE80211_HW_SPECTRUM_MGMT |
632 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
55624204 633
5ffaf8a3
LR		 634 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
635 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
636
55624204
S		 637 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
638 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
639
640 hw->wiphy->interface_modes =
641 BIT(NL80211_IFTYPE_AP) |
642 BIT(NL80211_IFTYPE_STATION) |
643 BIT(NL80211_IFTYPE_ADHOC) |
644 BIT(NL80211_IFTYPE_MESH_POINT);
645
646 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
647
648 hw->queues = 4;
649 hw->max_rates = 4;
650 hw->channel_change_time = 5000;
651 hw->max_listen_interval = 10;
65896510 652 hw->max_rate_tries = 10;
55624204
S		 653 hw->sta_data_size = sizeof(struct ath_node);
654 hw->vif_data_size = sizeof(struct ath_vif);
655
656 hw->rate_control_algorithm = "ath9k_rate_control";
657
658 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
659 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
660 &sc->sbands[IEEE80211_BAND_2GHZ];
661 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
662 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
663 &sc->sbands[IEEE80211_BAND_5GHZ];
285f2dda
S		 664
665 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
666 if (test_bit(ATH9K_MODE_11G, sc->sc_ah->caps.wireless_modes))
667 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
668 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
669 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
670 }
671
672 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
55624204
S		 673}
674
285f2dda 675int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
55624204
S		 676 const struct ath_bus_ops *bus_ops)
677{
678 struct ieee80211_hw *hw = sc->hw;
679 struct ath_common *common;
680 struct ath_hw *ah;
285f2dda 681 int error = 0;
55624204
S		 682 struct ath_regulatory *reg;
683
285f2dda
S		 684 /* Bring up device */
685 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
55624204 686 if (error != 0)
285f2dda 687 goto error_init;
55624204
S		 688
689 ah = sc->sc_ah;
690 common = ath9k_hw_common(ah);
285f2dda 691 ath9k_set_hw_capab(sc, hw);
55624204 692
285f2dda 693 /* Initialize regulatory */
55624204
S		 694 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
695 ath9k_reg_notifier);
696 if (error)
285f2dda 697 goto error_regd;
55624204
S		 698
699 reg = &common->regulatory;
700
285f2dda 701 /* Setup TX DMA */
55624204
S		 702 error = ath_tx_init(sc, ATH_TXBUF);
703 if (error != 0)
285f2dda 704 goto error_tx;
55624204 705
285f2dda 706 /* Setup RX DMA */
55624204
S		 707 error = ath_rx_init(sc, ATH_RXBUF);
708 if (error != 0)
285f2dda 709 goto error_rx;
55624204 710
285f2dda 711 /* Register with mac80211 */
55624204 712 error = ieee80211_register_hw(hw);
285f2dda
S		 713 if (error)
714 goto error_register;
55624204 715
285f2dda 716 /* Handle world regulatory */
55624204
S		 717 if (!ath_is_world_regd(reg)) {
718 error = regulatory_hint(hw->wiphy, reg->alpha2);
719 if (error)
285f2dda 720 goto error_world;
55624204
S		 721 }
722
347809fc 723 INIT_WORK(&sc->hw_check_work, ath_hw_check);
9f42c2b6 724 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
285f2dda
S		 725 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
726 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
727 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
55624204 728
285f2dda 729 ath_init_leds(sc);
55624204
S		 730 ath_start_rfkill_poll(sc);
731
732 return 0;
733
285f2dda
S		 734error_world:
735 ieee80211_unregister_hw(hw);
736error_register:
737 ath_rx_cleanup(sc);
738error_rx:
739 ath_tx_cleanup(sc);
740error_tx:
741 /* Nothing */
742error_regd:
743 ath9k_deinit_softc(sc);
744error_init:
55624204
S		 745 return error;
746}
747
748/*****************************/
749/* De-Initialization */
750/*****************************/
751
285f2dda 752static void ath9k_deinit_softc(struct ath_softc *sc)
55624204 753{
285f2dda 754 int i = 0;
55624204 755
285f2dda
S		 756 if ((sc->btcoex.no_stomp_timer) &&
757 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
758 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
55624204 759
285f2dda
S		 760 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
761 if (ATH_TXQ_SETUP(sc, i))
762 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
763
764 ath9k_exit_debug(sc->sc_ah);
765 ath9k_hw_deinit(sc->sc_ah);
766
767 tasklet_kill(&sc->intr_tq);
768 tasklet_kill(&sc->bcon_tasklet);
736b3a27
S		 769
770 kfree(sc->sc_ah);
771 sc->sc_ah = NULL;
55624204
S		 772}
773
285f2dda 774void ath9k_deinit_device(struct ath_softc *sc)
55624204
S		 775{
776 struct ieee80211_hw *hw = sc->hw;
55624204
S		 777 int i = 0;
778
779 ath9k_ps_wakeup(sc);
780
55624204 781 wiphy_rfkill_stop_polling(sc->hw->wiphy);
285f2dda 782 ath_deinit_leds(sc);
55624204
S		 783
784 for (i = 0; i < sc->num_sec_wiphy; i++) {
785 struct ath_wiphy *aphy = sc->sec_wiphy[i];
786 if (aphy == NULL)
787 continue;
788 sc->sec_wiphy[i] = NULL;
789 ieee80211_unregister_hw(aphy->hw);
790 ieee80211_free_hw(aphy->hw);
791 }
285f2dda 792
55624204
S		 793 ieee80211_unregister_hw(hw);
794 ath_rx_cleanup(sc);
795 ath_tx_cleanup(sc);
285f2dda 796 ath9k_deinit_softc(sc);
447a42c2 797 kfree(sc->sec_wiphy);
55624204
S		 798}
799
800void ath_descdma_cleanup(struct ath_softc *sc,
801 struct ath_descdma *dd,
802 struct list_head *head)
803{
804 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
805 dd->dd_desc_paddr);
806
807 INIT_LIST_HEAD(head);
808 kfree(dd->dd_bufptr);
809 memset(dd, 0, sizeof(*dd));
810}
811
55624204
S		 812/************************/
813/* Module Hooks */
814/************************/
815
816static int __init ath9k_init(void)
817{
818 int error;
819
820 /* Register rate control algorithm */
821 error = ath_rate_control_register();
822 if (error != 0) {
823 printk(KERN_ERR
824 "ath9k: Unable to register rate control "
825 "algorithm: %d\n",
826 error);
827 goto err_out;
828 }
829
830 error = ath9k_debug_create_root();
831 if (error) {
832 printk(KERN_ERR
833 "ath9k: Unable to create debugfs root: %d\n",
834 error);
835 goto err_rate_unregister;
836 }
837
838 error = ath_pci_init();
839 if (error < 0) {
840 printk(KERN_ERR
841 "ath9k: No PCI devices found, driver not installed.\n");
842 error = -ENODEV;
843 goto err_remove_root;
844 }
845
846 error = ath_ahb_init();
847 if (error < 0) {
848 error = -ENODEV;
849 goto err_pci_exit;
850 }
851
852 return 0;
853
854 err_pci_exit:
855 ath_pci_exit();
856
857 err_remove_root:
858 ath9k_debug_remove_root();
859 err_rate_unregister:
860 ath_rate_control_unregister();
861 err_out:
862 return error;
863}
864module_init(ath9k_init);
865
866static void __exit ath9k_exit(void)
867{
868 ath_ahb_exit();
869 ath_pci_exit();
870 ath9k_debug_remove_root();
871 ath_rate_control_unregister();
872 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
873}
874module_exit(ath9k_exit);
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