]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/wireless/ath/ath9k/hw.h
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'master' of /repos/git/net-next-2.6
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / hw.h
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1 35#define ATHEROS_VENDOR_ID 0x168c
7976b426 36
394cf0a1
S		 37#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 43#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 44#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030
7976b426 47
394cf0a1 48#define AR5416_AR9100_DEVID 0x000b
7976b426 49
394cf0a1
S		 50#define AR_SUBVENDOR_ID_NOG 0x0e11
51#define AR_SUBVENDOR_ID_NEW_A 0x7065
52#define AR5416_MAGIC 0x19641014
53
fe12946e
VT		 54#define AR9280_COEX2WIRE_SUBSYSID 0x309b
55#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
e3d01bfc
LR		 58#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
cfe8cba9
LR		 60#define ATH_DEFAULT_NOISE_FLOOR -95
61
04658fba 62#define ATH9K_RSSI_BAD -128
990b70ab 63
394cf0a1 64/* Register read/write primitives */
9e4bffd2
LR		 65#define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
67
68#define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1 70
20b3efd9
S		 71#define ENABLE_REGWRITE_BUFFER(_ah) \
72 do { \
73 if (AR_SREV_9271(_ah)) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
75 } while (0)
76
77#define DISABLE_REGWRITE_BUFFER(_ah) \
78 do { \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
81 } while (0)
82
83#define REGWRITE_BUFFER_FLUSH(_ah) \
84 do { \
85 if (AR_SREV_9271(_ah)) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
87 } while (0)
88
394cf0a1
S		 89#define SM(_v, _f) (((_v) << _f##_S) & _f)
90#define MS(_v, _f) (((_v) & _f) >> _f##_S)
91#define REG_RMW(_a, _r, _set, _clr) \
92 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
93#define REG_RMW_FIELD(_a, _r, _f, _v) \
94 REG_WRITE(_a, _r, \
95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
1547da37
LR		 96#define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1
S		 98#define REG_SET_BIT(_a, _r, _f) \
99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
100#define REG_CLR_BIT(_a, _r, _f) \
101 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 102
394cf0a1
S		 103#define DO_DELAY(x) do { \
104 if ((++(x) % 64) == 0) \
105 udelay(1); \
106 } while (0)
f078f209 107
394cf0a1
S		 108#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
109 int r; \
110 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
111 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
112 INI_RA((iniarray), r, (column))); \
113 DO_DELAY(regWr); \
114 } \
115 } while (0)
f078f209 116
394cf0a1
S		 117#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
118#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
119#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
120#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 121#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 122#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
123#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 124
394cf0a1
S		 125#define AR_GPIOD_MASK 0x00001FFF
126#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 127
394cf0a1 128#define BASE_ACTIVATE_DELAY 100
63a75b91 129#define RTC_PLL_SETTLE_DELAY 100
394cf0a1
S		 130#define COEF_SCALE_S 24
131#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 132
394cf0a1
S		 133#define ATH9K_ANTENNA0_CHAINMASK 0x1
134#define ATH9K_ANTENNA1_CHAINMASK 0x2
135
136#define ATH9K_NUM_DMA_DEBUG_REGS 8
137#define ATH9K_NUM_QUEUES 10
138
139#define MAX_RATE_POWER 63
0caa7b14 140#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 141#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 142#define AH_TIME_QUANTUM 10
143#define AR_KEYTABLE_SIZE 128
d8caa839 144#define POWER_UP_TIME 10000
394cf0a1
S		 145#define SPUR_RSSI_THRESH 40
146
147#define CAB_TIMEOUT_VAL 10
148#define BEACON_TIMEOUT_VAL 10
149#define MIN_BEACON_TIMEOUT_VAL 1
150#define SLEEP_SLOP 3
151
152#define INIT_CONFIG_STATUS 0x00000000
153#define INIT_RSSI_THR 0x00000700
154#define INIT_BCON_CNTRL_REG 0x00000000
155
156#define TU_TO_USEC(_tu) ((_tu) << 10)
157
ceb26445
VT		 158#define ATH9K_HW_RX_HP_QDEPTH 16
159#define ATH9K_HW_RX_LP_QDEPTH 128
160
13ce3e99
LR		 161enum ath_ini_subsys {
162 ATH_INI_PRE = 0,
163 ATH_INI_CORE,
164 ATH_INI_POST,
165 ATH_INI_NUM_SPLIT,
166};
167
394cf0a1
S		 168enum wireless_mode {
169 ATH9K_MODE_11A = 0,
b9b6e15a
LR		 170 ATH9K_MODE_11G,
171 ATH9K_MODE_11NA_HT20,
172 ATH9K_MODE_11NG_HT20,
173 ATH9K_MODE_11NA_HT40PLUS,
174 ATH9K_MODE_11NA_HT40MINUS,
175 ATH9K_MODE_11NG_HT40PLUS,
176 ATH9K_MODE_11NG_HT40MINUS,
177 ATH9K_MODE_MAX,
394cf0a1 178};
f078f209 179
394cf0a1 180enum ath9k_hw_caps {
bdbdf46d
S		 181 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
182 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
183 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
184 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
185 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
186 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
187 ATH9K_HW_CAP_VEOL = BIT(6),
188 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
189 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
190 ATH9K_HW_CAP_HT = BIT(9),
191 ATH9K_HW_CAP_GTT = BIT(10),
192 ATH9K_HW_CAP_FASTCC = BIT(11),
193 ATH9K_HW_CAP_RFSILENT = BIT(12),
194 ATH9K_HW_CAP_CST = BIT(13),
195 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
196 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
197 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
1adf02ff 198 ATH9K_HW_CAP_EDMA = BIT(17),
6c84ce08 199 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
ce01805a 200 ATH9K_HW_CAP_LDPC = BIT(19),
e5553724 201 ATH9K_HW_CAP_FASTCLOCK = BIT(20),
394cf0a1 202};
f078f209 203
394cf0a1
S		 204enum ath9k_capability_type {
205 ATH9K_CAP_CIPHER = 0,
206 ATH9K_CAP_TKIP_MIC,
207 ATH9K_CAP_TKIP_SPLIT,
394cf0a1 208 ATH9K_CAP_TXPOW,
394cf0a1 209 ATH9K_CAP_MCAST_KEYSRCH,
8bd1d07f 210 ATH9K_CAP_DS
394cf0a1 211};
f078f209 212
394cf0a1
S		 213struct ath9k_hw_capabilities {
214 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
215 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
216 u16 total_queues;
217 u16 keycache_size;
218 u16 low_5ghz_chan, high_5ghz_chan;
219 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 220 u16 rts_aggr_limit;
221 u8 tx_chainmask;
222 u8 rx_chainmask;
223 u16 tx_triglevel_max;
224 u16 reg_cap;
225 u8 num_gpio_pins;
226 u8 num_antcfg_2ghz;
227 u8 num_antcfg_5ghz;
ceb26445
VT		 228 u8 rx_hp_qdepth;
229 u8 rx_lp_qdepth;
230 u8 rx_status_len;
162c3be3 231 u8 tx_desc_len;
5088c2f1 232 u8 txs_len;
394cf0a1 233};
f078f209 234
394cf0a1
S		 235struct ath9k_ops_config {
236 int dma_beacon_response_time;
237 int sw_beacon_response_time;
238 int additional_swba_backoff;
239 int ack_6mb;
240 int cwm_ignore_extcca;
241 u8 pcie_powersave_enable;
394cf0a1
S		 242 u8 pcie_clock_req;
243 u32 pcie_waen;
394cf0a1
S		 244 u8 analog_shiftreg;
245 u8 ht_enable;
246 u32 ofdm_trig_low;
247 u32 ofdm_trig_high;
248 u32 cck_trig_high;
249 u32 cck_trig_low;
250 u32 enable_ani;
394cf0a1 251 int serialize_regmode;
0ce024cb 252 bool rx_intr_mitigation;
55e82df4 253 bool tx_intr_mitigation;
394cf0a1
S		 254#define SPUR_DISABLE 0
255#define SPUR_ENABLE_IOCTL 1
256#define SPUR_ENABLE_EEPROM 2
257#define AR_EEPROM_MODAL_SPURS 5
258#define AR_SPUR_5413_1 1640
259#define AR_SPUR_5413_2 1200
260#define AR_NO_SPUR 0x8000
261#define AR_BASE_FREQ_2GHZ 2300
262#define AR_BASE_FREQ_5GHZ 4900
263#define AR_SPUR_FEEQ_BOUND_HT40 19
264#define AR_SPUR_FEEQ_BOUND_HT20 10
b360a884 265 bool tx_iq_calibration; /* Only available for >= AR9003 */
394cf0a1
S		 266 int spurmode;
267 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 268 u8 max_txtrig_level;
394cf0a1 269};
f078f209 270
394cf0a1
S		 271enum ath9k_int {
272 ATH9K_INT_RX = 0x00000001,
273 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 274 ATH9K_INT_RXHP = 0x00000001,
275 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 276 ATH9K_INT_RXNOFRM = 0x00000008,
277 ATH9K_INT_RXEOL = 0x00000010,
278 ATH9K_INT_RXORN = 0x00000020,
279 ATH9K_INT_TX = 0x00000040,
280 ATH9K_INT_TXDESC = 0x00000080,
281 ATH9K_INT_TIM_TIMER = 0x00000100,
282 ATH9K_INT_TXURN = 0x00000800,
283 ATH9K_INT_MIB = 0x00001000,
284 ATH9K_INT_RXPHY = 0x00004000,
285 ATH9K_INT_RXKCM = 0x00008000,
286 ATH9K_INT_SWBA = 0x00010000,
287 ATH9K_INT_BMISS = 0x00040000,
288 ATH9K_INT_BNR = 0x00100000,
289 ATH9K_INT_TIM = 0x00200000,
290 ATH9K_INT_DTIM = 0x00400000,
291 ATH9K_INT_DTIMSYNC = 0x00800000,
292 ATH9K_INT_GPIO = 0x01000000,
293 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 294 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 295 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 296 ATH9K_INT_CST = 0x10000000,
297 ATH9K_INT_GTT = 0x20000000,
298 ATH9K_INT_FATAL = 0x40000000,
299 ATH9K_INT_GLOBAL = 0x80000000,
300 ATH9K_INT_BMISC = ATH9K_INT_TIM |
301 ATH9K_INT_DTIM |
302 ATH9K_INT_DTIMSYNC |
4af9cf4f 303 ATH9K_INT_TSFOOR |
394cf0a1
S		 304 ATH9K_INT_CABEND,
305 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
306 ATH9K_INT_RXDESC |
307 ATH9K_INT_RXEOL |
308 ATH9K_INT_RXORN |
309 ATH9K_INT_TXURN |
310 ATH9K_INT_TXDESC |
311 ATH9K_INT_MIB |
312 ATH9K_INT_RXPHY |
313 ATH9K_INT_RXKCM |
314 ATH9K_INT_SWBA |
315 ATH9K_INT_BMISS |
316 ATH9K_INT_GPIO,
317 ATH9K_INT_NOCARD = 0xffffffff
318};
f078f209 319
394cf0a1
S		 320#define CHANNEL_CW_INT 0x00002
321#define CHANNEL_CCK 0x00020
322#define CHANNEL_OFDM 0x00040
323#define CHANNEL_2GHZ 0x00080
324#define CHANNEL_5GHZ 0x00100
325#define CHANNEL_PASSIVE 0x00200
326#define CHANNEL_DYN 0x00400
327#define CHANNEL_HALF 0x04000
328#define CHANNEL_QUARTER 0x08000
329#define CHANNEL_HT20 0x10000
330#define CHANNEL_HT40PLUS 0x20000
331#define CHANNEL_HT40MINUS 0x40000
332
394cf0a1
S		 333#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
334#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
335#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
336#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
337#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
338#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
339#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
340#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
341#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
342#define CHANNEL_ALL \
343 (CHANNEL_OFDM| \
344 CHANNEL_CCK| \
345 CHANNEL_2GHZ | \
346 CHANNEL_5GHZ | \
347 CHANNEL_HT20 | \
348 CHANNEL_HT40PLUS | \
349 CHANNEL_HT40MINUS)
350
351struct ath9k_channel {
352 struct ieee80211_channel *chan;
353 u16 channel;
354 u32 channelFlags;
355 u32 chanmode;
356 int32_t CalValid;
357 bool oneTimeCalsDone;
358 int8_t iCoff;
359 int8_t qCoff;
360 int16_t rawNoiseFloor;
361};
f078f209 362
394cf0a1
S		 363#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
364 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
365 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
366 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
367#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
368#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
369#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 370#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
371#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 372#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 373 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 374 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 375
376/* These macros check chanmode and not channelFlags */
377#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
378#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
379 ((_c)->chanmode == CHANNEL_G_HT20))
380#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
381 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
382 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
383 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
384#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
385
386enum ath9k_power_mode {
387 ATH9K_PM_AWAKE = 0,
388 ATH9K_PM_FULL_SLEEP,
389 ATH9K_PM_NETWORK_SLEEP,
390 ATH9K_PM_UNDEFINED
391};
f078f209 392
394cf0a1
S		 393enum ath9k_tp_scale {
394 ATH9K_TP_SCALE_MAX = 0,
395 ATH9K_TP_SCALE_50,
396 ATH9K_TP_SCALE_25,
397 ATH9K_TP_SCALE_12,
398 ATH9K_TP_SCALE_MIN
399};
f078f209 400
394cf0a1
S		 401enum ser_reg_mode {
402 SER_REG_MODE_OFF = 0,
403 SER_REG_MODE_ON = 1,
404 SER_REG_MODE_AUTO = 2,
405};
f078f209 406
ad7b8060
VT		 407enum ath9k_rx_qtype {
408 ATH9K_RX_QUEUE_HP,
409 ATH9K_RX_QUEUE_LP,
410 ATH9K_RX_QUEUE_MAX,
411};
412
394cf0a1
S		 413struct ath9k_beacon_state {
414 u32 bs_nexttbtt;
415 u32 bs_nextdtim;
416 u32 bs_intval;
417#define ATH9K_BEACON_PERIOD 0x0000ffff
418#define ATH9K_BEACON_ENA 0x00800000
419#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 420#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 421 u32 bs_dtimperiod;
422 u16 bs_cfpperiod;
423 u16 bs_cfpmaxduration;
424 u32 bs_cfpnext;
425 u16 bs_timoffset;
426 u16 bs_bmissthreshold;
427 u32 bs_sleepduration;
4af9cf4f 428 u32 bs_tsfoor_threshold;
394cf0a1 429};
f078f209 430
394cf0a1
S		 431struct chan_centers {
432 u16 synth_center;
433 u16 ctl_center;
434 u16 ext_center;
435};
f078f209 436
394cf0a1
S		 437enum {
438 ATH9K_RESET_POWER_ON,
439 ATH9K_RESET_WARM,
440 ATH9K_RESET_COLD,
441};
f078f209 442
d535a42a
S		 443struct ath9k_hw_version {
444 u32 magic;
445 u16 devid;
446 u16 subvendorid;
447 u32 macVersion;
448 u16 macRev;
449 u16 phyRev;
450 u16 analog5GhzRev;
451 u16 analog2GhzRev;
aeac355d 452 u16 subsysid;
d535a42a 453};
394cf0a1 454
ff155a45
VT		 455/* Generic TSF timer definitions */
456
457#define ATH_MAX_GEN_TIMER 16
458
459#define AR_GENTMR_BIT(_index) (1 << (_index))
460
461/*
462 * Using de Bruijin sequence to to look up 1's index in a 32 bit number
463 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
464 */
c90017dd 465#define debruijn32 0x077CB531U
ff155a45
VT		 466
467struct ath_gen_timer_configuration {
468 u32 next_addr;
469 u32 period_addr;
470 u32 mode_addr;
471 u32 mode_mask;
472};
473
474struct ath_gen_timer {
475 void (*trigger)(void *arg);
476 void (*overflow)(void *arg);
477 void *arg;
478 u8 index;
479};
480
481struct ath_gen_timer_table {
482 u32 gen_timer_index[32];
483 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
484 union {
485 unsigned long timer_bits;
486 u16 val;
487 } timer_mask;
488};
489
d70357d5
LR		 490/**
491 * struct ath_hw_private_ops - callbacks used internally by hardware code
492 *
493 * This structure contains private callbacks designed to only be used internally
494 * by the hardware core.
495 *
795f5e2c
LR		 496 * @init_cal_settings: setup types of calibrations supported
497 * @init_cal: starts actual calibration
498 *
d70357d5 499 * @init_mode_regs: Initializes mode registers
991312d8 500 * @init_mode_gain_regs: Initialize TX/RX gain registers
d70357d5 501 * @macversion_supported: If this specific mac revision is supported
8fe65368
LR		 502 *
503 * @rf_set_freq: change frequency
504 * @spur_mitigate_freq: spur mitigation
505 * @rf_alloc_ext_banks:
506 * @rf_free_ext_banks:
507 * @set_rf_regs:
64773964
LR		 508 * @compute_pll_control: compute the PLL control value to use for
509 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 510 * @setup_calibration: set up calibration
511 * @iscal_supported: used to query if a type of calibration is supported
77d6d39a 512 * @loadnf: load noise floor read from each chain on the CCA registers
d70357d5
LR		 513 */
514struct ath_hw_private_ops {
795f5e2c 515 /* Calibration ops */
d70357d5 516 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 517 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
518
d70357d5 519 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 520 void (*init_mode_gain_regs)(struct ath_hw *ah);
d70357d5 521 bool (*macversion_supported)(u32 macversion);
795f5e2c
LR		 522 void (*setup_calibration)(struct ath_hw *ah,
523 struct ath9k_cal_list *currCal);
524 bool (*iscal_supported)(struct ath_hw *ah,
525 enum ath9k_cal_types calType);
8fe65368
LR		 526
527 /* PHY ops */
528 int (*rf_set_freq)(struct ath_hw *ah,
529 struct ath9k_channel *chan);
530 void (*spur_mitigate_freq)(struct ath_hw *ah,
531 struct ath9k_channel *chan);
532 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
533 void (*rf_free_ext_banks)(struct ath_hw *ah);
534 bool (*set_rf_regs)(struct ath_hw *ah,
535 struct ath9k_channel *chan,
536 u16 modesIndex);
537 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
538 void (*init_bb)(struct ath_hw *ah,
539 struct ath9k_channel *chan);
540 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
541 void (*olc_init)(struct ath_hw *ah);
542 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
543 void (*mark_phy_inactive)(struct ath_hw *ah);
544 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
545 bool (*rfbus_req)(struct ath_hw *ah);
546 void (*rfbus_done)(struct ath_hw *ah);
547 void (*enable_rfkill)(struct ath_hw *ah);
548 void (*restore_chainmask)(struct ath_hw *ah);
549 void (*set_diversity)(struct ath_hw *ah, bool value);
64773964
LR		 550 u32 (*compute_pll_control)(struct ath_hw *ah,
551 struct ath9k_channel *chan);
c16fcb49
FF		 552 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
553 int param);
641d9921 554 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
77d6d39a 555 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
d70357d5
LR		 556};
557
558/**
559 * struct ath_hw_ops - callbacks used by hardware code and driver code
560 *
561 * This structure contains callbacks designed to to be used internally by
562 * hardware code and also by the lower level driver.
563 *
564 * @config_pci_powersave:
795f5e2c 565 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 566 */
567struct ath_hw_ops {
568 void (*config_pci_powersave)(struct ath_hw *ah,
569 int restore,
570 int power_off);
cee1f625 571 void (*rx_enable)(struct ath_hw *ah);
87d5efbb
VT		 572 void (*set_desc_link)(void *ds, u32 link);
573 void (*get_desc_link)(void *ds, u32 **link);
795f5e2c
LR		 574 bool (*calibrate)(struct ath_hw *ah,
575 struct ath9k_channel *chan,
576 u8 rxchainmask,
577 bool longcal);
55e82df4 578 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
cc610ac0
VT		 579 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
580 bool is_firstseg, bool is_is_lastseg,
581 const void *ds0, dma_addr_t buf_addr,
582 unsigned int qcu);
583 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
584 struct ath_tx_status *ts);
585 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
586 u32 pktLen, enum ath9k_pkt_type type,
587 u32 txPower, u32 keyIx,
588 enum ath9k_key_type keyType,
589 u32 flags);
590 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
591 void *lastds,
592 u32 durUpdateEn, u32 rtsctsRate,
593 u32 rtsctsDuration,
594 struct ath9k_11n_rate_series series[],
595 u32 nseries, u32 flags);
596 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
597 u32 aggrLen);
598 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
599 u32 numDelims);
600 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
601 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
602 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
603 u32 burstDuration);
604 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
605 u32 vmf);
d70357d5
LR		 606};
607
cbe61d8a 608struct ath_hw {
b002a4a9 609 struct ieee80211_hw *hw;
27c51f1a 610 struct ath_common common;
cbe61d8a 611 struct ath9k_hw_version hw_version;
2660b81a
S		 612 struct ath9k_ops_config config;
613 struct ath9k_hw_capabilities caps;
2660b81a
S		 614 struct ath9k_channel channels[38];
615 struct ath9k_channel *curchan;
394cf0a1 616
cbe61d8a
S		 617 union {
618 struct ar5416_eeprom_def def;
619 struct ar5416_eeprom_4k map4k;
475f5989 620 struct ar9287_eeprom map9287;
15c9ee7a 621 struct ar9300_eeprom ar9300_eep;
2660b81a 622 } eeprom;
f74df6fb 623 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 624
625 bool sw_mgmt_crypto;
2660b81a 626 bool is_pciexpress;
2eb46d9b 627 bool need_an_top2_fixup;
2660b81a 628 u16 tx_trig_level;
641d9921
FF		 629 s16 nf_2g_max;
630 s16 nf_2g_min;
631 s16 nf_5g_max;
632 s16 nf_5g_min;
2660b81a
S		 633 u16 rfsilent;
634 u32 rfkill_gpio;
635 u32 rfkill_polarity;
cbe61d8a 636 u32 ah_flags;
394cf0a1 637
d7e7d229
LR		 638 bool htc_reset_init;
639
2660b81a
S		 640 enum nl80211_iftype opmode;
641 enum ath9k_power_mode power_mode;
f078f209 642
cbe61d8a 643 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
a13883b0 644 struct ath9k_pacal_info pacal_info;
2660b81a
S		 645 struct ar5416Stats stats;
646 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
647
648 int16_t curchan_rad_index;
3069168c 649 enum ath9k_int imask;
74bad5cb 650 u32 imrs2_reg;
2660b81a
S		 651 u32 txok_interrupt_mask;
652 u32 txerr_interrupt_mask;
653 u32 txdesc_interrupt_mask;
654 u32 txeol_interrupt_mask;
655 u32 txurn_interrupt_mask;
656 bool chip_fullsleep;
657 u32 atim_window;
6a2b9e8c
S		 658
659 /* Calibration */
cbfe9468
S		 660 enum ath9k_cal_types supp_cals;
661 struct ath9k_cal_list iq_caldata;
662 struct ath9k_cal_list adcgain_caldata;
663 struct ath9k_cal_list adcdc_calinitdata;
664 struct ath9k_cal_list adcdc_caldata;
df23acaa 665 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 666 struct ath9k_cal_list *cal_list;
667 struct ath9k_cal_list *cal_list_last;
668 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 669#define totalPowerMeasI meas0.unsign
670#define totalPowerMeasQ meas1.unsign
671#define totalIqCorrMeas meas2.sign
672#define totalAdcIOddPhase meas0.unsign
673#define totalAdcIEvenPhase meas1.unsign
674#define totalAdcQOddPhase meas2.unsign
675#define totalAdcQEvenPhase meas3.unsign
676#define totalAdcDcOffsetIOddPhase meas0.sign
677#define totalAdcDcOffsetIEvenPhase meas1.sign
678#define totalAdcDcOffsetQOddPhase meas2.sign
679#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 680 union {
681 u32 unsign[AR5416_MAX_CHAINS];
682 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 683 } meas0;
f078f209
LR		 684 union {
685 u32 unsign[AR5416_MAX_CHAINS];
686 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 687 } meas1;
f078f209
LR		 688 union {
689 u32 unsign[AR5416_MAX_CHAINS];
690 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 691 } meas2;
f078f209
LR		 692 union {
693 u32 unsign[AR5416_MAX_CHAINS];
694 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 695 } meas3;
696 u16 cal_samples;
6a2b9e8c 697
2660b81a
S		 698 u32 sta_id1_defaults;
699 u32 misc_mode;
f078f209
LR		 700 enum {
701 AUTO_32KHZ,
702 USE_32KHZ,
703 DONT_USE_32KHZ,
2660b81a 704 } enable_32kHz_clock;
6a2b9e8c 705
d70357d5
LR		 706 /* Private to hardware code */
707 struct ath_hw_private_ops private_ops;
708 /* Accessed by the lower level driver */
709 struct ath_hw_ops ops;
710
e68a060b 711 /* Used to program the radio on non single-chip devices */
2660b81a
S		 712 u32 *analogBank0Data;
713 u32 *analogBank1Data;
714 u32 *analogBank2Data;
715 u32 *analogBank3Data;
716 u32 *analogBank6Data;
717 u32 *analogBank6TPCData;
718 u32 *analogBank7Data;
719 u32 *addac5416_21;
720 u32 *bank6Temp;
721
597a94b3 722 u8 txpower_limit;
2660b81a 723 int16_t txpower_indexoffset;
e239d859 724 int coverage_class;
2660b81a
S		 725 u32 beacon_interval;
726 u32 slottime;
2660b81a 727 u32 globaltxtimeout;
6a2b9e8c
S		 728
729 /* ANI */
2660b81a 730 u32 proc_phyerr;
2660b81a
S		 731 u32 aniperiod;
732 struct ar5416AniState *curani;
733 struct ar5416AniState ani[255];
734 int totalSizeDesired[5];
735 int coarse_high[5];
736 int coarse_low[5];
737 int firpwr[5];
738 enum ath9k_ani_cmd ani_function;
739
af03abec 740 /* Bluetooth coexistance */
766ec4a9 741 struct ath_btcoex_hw btcoex_hw;
af03abec 742
2660b81a 743 u32 intr_txqs;
2660b81a
S		 744 u8 txchainmask;
745 u8 rxchainmask;
746
8bd1d07f
SB		 747 u32 originalGain[22];
748 int initPDADC;
749 int PDADCdelta;
08fc5c1b 750 u8 led_pin;
8bd1d07f 751
2660b81a
S		 752 struct ar5416IniArray iniModes;
753 struct ar5416IniArray iniCommon;
754 struct ar5416IniArray iniBank0;
755 struct ar5416IniArray iniBB_RfGain;
756 struct ar5416IniArray iniBank1;
757 struct ar5416IniArray iniBank2;
758 struct ar5416IniArray iniBank3;
759 struct ar5416IniArray iniBank6;
760 struct ar5416IniArray iniBank6TPC;
761 struct ar5416IniArray iniBank7;
762 struct ar5416IniArray iniAddac;
763 struct ar5416IniArray iniPcieSerdes;
13ce3e99 764 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a
S		 765 struct ar5416IniArray iniModesAdditional;
766 struct ar5416IniArray iniModesRxGain;
767 struct ar5416IniArray iniModesTxGain;
8564328d 768 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 769 struct ar5416IniArray iniCckfirNormal;
770 struct ar5416IniArray iniCckfirJapan2484;
70807e99
S		 771 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
772 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
773 struct ar5416IniArray iniModes_9271_ANI_reg;
774 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
775 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ff155a45 776
13ce3e99
LR		 777 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
778 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
779 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
780 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
781
ff155a45
VT		 782 u32 intr_gen_timer_trigger;
783 u32 intr_gen_timer_thresh;
784 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 785
786 struct ar9003_txs *ts_ring;
787 void *ts_start;
788 u32 ts_paddr_start;
789 u32 ts_paddr_end;
790 u16 ts_tail;
791 u8 ts_size;
f078f209 792};
f078f209 793
9e4bffd2
LR		 794static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
795{
796 return &ah->common;
797}
798
799static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
800{
801 return &(ath9k_hw_common(ah)->regulatory);
802}
803
d70357d5
LR		 804static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
805{
806 return &ah->private_ops;
807}
808
809static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
810{
811 return &ah->ops;
812}
813
f637cfd6 814/* Initialization, Detach, Reset */
394cf0a1 815const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 816void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 817int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 818int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
394cf0a1 819 bool bChannelChange);
a9a29ce6 820int ath9k_hw_fill_cap_info(struct ath_hw *ah);
cbe61d8a 821bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 822 u32 capability, u32 *result);
cbe61d8a 823bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
394cf0a1 824 u32 capability, u32 setting, int *status);
8fe65368 825u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1
S		 826
827/* Key Cache Management */
cbe61d8a
S		 828bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
829bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
830bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
394cf0a1 831 const struct ath9k_keyval *k,
e0caf9ea 832 const u8 *mac);
cbe61d8a 833bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
394cf0a1
S		 834
835/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 836void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
837u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
838void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 839 u32 ah_signal_type);
cbe61d8a 840void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 841u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
842void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
394cf0a1
S		 843
844/* General Operation */
0caa7b14 845bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 846u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 847bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3 848u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 849 u8 phy, int kbps,
394cf0a1 850 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 851void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 852 struct ath9k_channel *chan,
853 struct chan_centers *centers);
cbe61d8a
S		 854u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
855void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
856bool ath9k_hw_phy_disable(struct ath_hw *ah);
857bool ath9k_hw_disable(struct ath_hw *ah);
8fbff4b8 858void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
cbe61d8a
S		 859void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac);
860void ath9k_hw_setopmode(struct ath_hw *ah);
861void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 862void ath9k_hw_setbssidmask(struct ath_hw *ah);
863void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 864u64 ath9k_hw_gettsf64(struct ath_hw *ah);
865void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
866void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 867void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
30cbd422 868u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp);
0005baf4 869void ath9k_hw_init_global_settings(struct ath_hw *ah);
25c56eec 870void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 871void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
872void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 873 const struct ath9k_beacon_state *bs);
c9c99e5e 874bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 875
9ecdef4b 876bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 877
ff155a45
VT		 878/* Generic hw timer primitives */
879struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
880 void (*trigger)(void *),
881 void (*overflow)(void *),
882 void *arg,
883 u8 timer_index);
cd9bf689
LR		 884void ath9k_hw_gen_timer_start(struct ath_hw *ah,
885 struct ath_gen_timer *timer,
886 u32 timer_next,
887 u32 timer_period);
888void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
889
ff155a45
VT		 890void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
891void ath_gen_timer_isr(struct ath_hw *hw);
1773912b 892u32 ath9k_hw_gettsf32(struct ath_hw *ah);
ff155a45 893
f934c4d9 894void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 895
05020d23
S		 896/* HTC */
897void ath9k_hw_htc_resetinit(struct ath_hw *ah);
898
8fe65368
LR		 899/* PHY */
900void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
901 u32 *coef_mantissa, u32 *coef_exponent);
902
ebd5a14a
LR		 903/*
904 * Code Specific to AR5008, AR9001 or AR9002,
905 * we stuff these here to avoid callbacks for AR9003.
906 */
d8f492b7 907void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 908int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 909void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
6c94fdc9 910void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
d8f492b7 911
641d9921
FF		 912/*
913 * Code specifric to AR9003, we stuff these here to avoid callbacks
914 * for older families
915 */
916void ar9003_hw_set_nf_limits(struct ath_hw *ah);
917
918/* Hardware family op attach helpers */
8fe65368 919void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 920void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
921void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 922
795f5e2c
LR		 923void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
924void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
925
b3950e6a
LR		 926void ar9002_hw_attach_ops(struct ath_hw *ah);
927void ar9003_hw_attach_ops(struct ath_hw *ah);
928
7b6840ab
VT		 929#define ATH_PCIE_CAP_LINK_CTRL 0x70
930#define ATH_PCIE_CAP_LINK_L0S 1
931#define ATH_PCIE_CAP_LINK_L1 2
932
f078f209 933#endif
Clone of davem's net-next-2.6 tree