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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / hw.h
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f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef HW_H
18#define HW_H
19
20#include <linux/if_ether.h>
21#include <linux/delay.h>
394cf0a1
S		 22#include <linux/io.h>
23
24#include "mac.h"
25#include "ani.h"
26#include "eeprom.h"
27#include "calib.h"
394cf0a1
S		 28#include "reg.h"
29#include "phy.h"
af03abec 30#include "btcoex.h"
394cf0a1 31
203c4805 32#include "../regd.h"
c46917bb 33#include "../debug.h"
3a702e49 34
394cf0a1 35#define ATHEROS_VENDOR_ID 0x168c
7976b426 36
394cf0a1
S		 37#define AR5416_DEVID_PCI 0x0023
38#define AR5416_DEVID_PCIE 0x0024
39#define AR9160_DEVID_PCI 0x0027
40#define AR9280_DEVID_PCI 0x0029
41#define AR9280_DEVID_PCIE 0x002a
42#define AR9285_DEVID_PCIE 0x002b
5ffaf8a3 43#define AR2427_DEVID_PCIE 0x002c
db3cc53a
SB		 44#define AR9287_DEVID_PCI 0x002d
45#define AR9287_DEVID_PCIE 0x002e
46#define AR9300_DEVID_PCIE 0x0030
7976b426 47
394cf0a1 48#define AR5416_AR9100_DEVID 0x000b
7976b426 49
394cf0a1
S		 50#define AR_SUBVENDOR_ID_NOG 0x0e11
51#define AR_SUBVENDOR_ID_NEW_A 0x7065
52#define AR5416_MAGIC 0x19641014
53
fe12946e
VT		 54#define AR9280_COEX2WIRE_SUBSYSID 0x309b
55#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
e3d01bfc
LR		 58#define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
cfe8cba9
LR		 60#define ATH_DEFAULT_NOISE_FLOOR -95
61
04658fba 62#define ATH9K_RSSI_BAD -128
990b70ab 63
cac4220b
FF		 64#define ATH9K_NUM_CHANNELS 38
65
394cf0a1 66/* Register read/write primitives */
9e4bffd2
LR		 67#define REG_WRITE(_ah, _reg, _val) \
68 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
69
70#define REG_READ(_ah, _reg) \
71 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
394cf0a1 72
20b3efd9
S		 73#define ENABLE_REGWRITE_BUFFER(_ah) \
74 do { \
435c1610 75 if (ath9k_hw_common(_ah)->ops->enable_write_buffer) \
20b3efd9
S		 76 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
77 } while (0)
78
20b3efd9
S		 79#define REGWRITE_BUFFER_FLUSH(_ah) \
80 do { \
435c1610 81 if (ath9k_hw_common(_ah)->ops->write_flush) \
20b3efd9
S		 82 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
83 } while (0)
84
394cf0a1
S		 85#define SM(_v, _f) (((_v) << _f##_S) & _f)
86#define MS(_v, _f) (((_v) & _f) >> _f##_S)
87#define REG_RMW(_a, _r, _set, _clr) \
88 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
89#define REG_RMW_FIELD(_a, _r, _f, _v) \
90 REG_WRITE(_a, _r, \
91 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
1547da37
LR		 92#define REG_READ_FIELD(_a, _r, _f) \
93 (((REG_READ(_a, _r) & _f) >> _f##_S))
394cf0a1
S		 94#define REG_SET_BIT(_a, _r, _f) \
95 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
96#define REG_CLR_BIT(_a, _r, _f) \
97 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
f078f209 98
394cf0a1
S		 99#define DO_DELAY(x) do { \
100 if ((++(x) % 64) == 0) \
101 udelay(1); \
102 } while (0)
f078f209 103
394cf0a1
S		 104#define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
105 int r; \
106 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
107 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
108 INI_RA((iniarray), r, (column))); \
109 DO_DELAY(regWr); \
110 } \
111 } while (0)
f078f209 112
394cf0a1
S		 113#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
114#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
115#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
116#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
1773912b 117#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
394cf0a1
S		 118#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
119#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
f078f209 120
394cf0a1
S		 121#define AR_GPIOD_MASK 0x00001FFF
122#define AR_GPIO_BIT(_gpio) (1 << (_gpio))
f078f209 123
394cf0a1 124#define BASE_ACTIVATE_DELAY 100
63a75b91 125#define RTC_PLL_SETTLE_DELAY 100
394cf0a1
S		 126#define COEF_SCALE_S 24
127#define HT40_CHANNEL_CENTER_SHIFT 10
f078f209 128
394cf0a1
S		 129#define ATH9K_ANTENNA0_CHAINMASK 0x1
130#define ATH9K_ANTENNA1_CHAINMASK 0x2
131
132#define ATH9K_NUM_DMA_DEBUG_REGS 8
133#define ATH9K_NUM_QUEUES 10
134
135#define MAX_RATE_POWER 63
0caa7b14 136#define AH_WAIT_TIMEOUT 100000 /* (us) */
f9b604f6 137#define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
394cf0a1
S		 138#define AH_TIME_QUANTUM 10
139#define AR_KEYTABLE_SIZE 128
d8caa839 140#define POWER_UP_TIME 10000
394cf0a1
S		 141#define SPUR_RSSI_THRESH 40
142
143#define CAB_TIMEOUT_VAL 10
144#define BEACON_TIMEOUT_VAL 10
145#define MIN_BEACON_TIMEOUT_VAL 1
146#define SLEEP_SLOP 3
147
148#define INIT_CONFIG_STATUS 0x00000000
149#define INIT_RSSI_THR 0x00000700
150#define INIT_BCON_CNTRL_REG 0x00000000
151
152#define TU_TO_USEC(_tu) ((_tu) << 10)
153
ceb26445
VT		 154#define ATH9K_HW_RX_HP_QDEPTH 16
155#define ATH9K_HW_RX_LP_QDEPTH 128
156
717f6bed
FF		 157#define PAPRD_GAIN_TABLE_ENTRIES 32
158#define PAPRD_TABLE_SZ 24
159
066dae93
FF		 160enum ath_hw_txq_subtype {
161 ATH_TXQ_AC_BE = 0,
162 ATH_TXQ_AC_BK = 1,
163 ATH_TXQ_AC_VI = 2,
164 ATH_TXQ_AC_VO = 3,
165};
166
13ce3e99
LR		 167enum ath_ini_subsys {
168 ATH_INI_PRE = 0,
169 ATH_INI_CORE,
170 ATH_INI_POST,
171 ATH_INI_NUM_SPLIT,
172};
173
394cf0a1 174enum ath9k_hw_caps {
364734fa
FF		 175 ATH9K_HW_CAP_HT = BIT(0),
176 ATH9K_HW_CAP_RFSILENT = BIT(1),
177 ATH9K_HW_CAP_CST = BIT(2),
178 ATH9K_HW_CAP_ENHANCEDPM = BIT(3),
179 ATH9K_HW_CAP_AUTOSLEEP = BIT(4),
180 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(5),
181 ATH9K_HW_CAP_EDMA = BIT(6),
182 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(7),
183 ATH9K_HW_CAP_LDPC = BIT(8),
184 ATH9K_HW_CAP_FASTCLOCK = BIT(9),
185 ATH9K_HW_CAP_SGI_20 = BIT(10),
186 ATH9K_HW_CAP_PAPRD = BIT(11),
187 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(12),
d4659912
FF		 188 ATH9K_HW_CAP_2GHZ = BIT(13),
189 ATH9K_HW_CAP_5GHZ = BIT(14),
394cf0a1 190};
f078f209 191
394cf0a1
S		 192struct ath9k_hw_capabilities {
193 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
394cf0a1
S		 194 u16 total_queues;
195 u16 keycache_size;
196 u16 low_5ghz_chan, high_5ghz_chan;
197 u16 low_2ghz_chan, high_2ghz_chan;
394cf0a1
S		 198 u16 rts_aggr_limit;
199 u8 tx_chainmask;
200 u8 rx_chainmask;
201 u16 tx_triglevel_max;
202 u16 reg_cap;
203 u8 num_gpio_pins;
204 u8 num_antcfg_2ghz;
205 u8 num_antcfg_5ghz;
ceb26445
VT		 206 u8 rx_hp_qdepth;
207 u8 rx_lp_qdepth;
208 u8 rx_status_len;
162c3be3 209 u8 tx_desc_len;
5088c2f1 210 u8 txs_len;
394cf0a1 211};
f078f209 212
394cf0a1
S		 213struct ath9k_ops_config {
214 int dma_beacon_response_time;
215 int sw_beacon_response_time;
216 int additional_swba_backoff;
217 int ack_6mb;
41f3e54d 218 u32 cwm_ignore_extcca;
394cf0a1 219 u8 pcie_powersave_enable;
6a0ec30a 220 bool pcieSerDesWrite;
394cf0a1
S		 221 u8 pcie_clock_req;
222 u32 pcie_waen;
394cf0a1
S		 223 u8 analog_shiftreg;
224 u8 ht_enable;
225 u32 ofdm_trig_low;
226 u32 ofdm_trig_high;
227 u32 cck_trig_high;
228 u32 cck_trig_low;
229 u32 enable_ani;
394cf0a1 230 int serialize_regmode;
0ce024cb 231 bool rx_intr_mitigation;
55e82df4 232 bool tx_intr_mitigation;
394cf0a1
S		 233#define SPUR_DISABLE 0
234#define SPUR_ENABLE_IOCTL 1
235#define SPUR_ENABLE_EEPROM 2
236#define AR_EEPROM_MODAL_SPURS 5
237#define AR_SPUR_5413_1 1640
238#define AR_SPUR_5413_2 1200
239#define AR_NO_SPUR 0x8000
240#define AR_BASE_FREQ_2GHZ 2300
241#define AR_BASE_FREQ_5GHZ 4900
242#define AR_SPUR_FEEQ_BOUND_HT40 19
243#define AR_SPUR_FEEQ_BOUND_HT20 10
244 int spurmode;
245 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
f4709fdf 246 u8 max_txtrig_level;
e36b27af 247 u16 ani_poll_interval; /* ANI poll interval in ms */
394cf0a1 248};
f078f209 249
394cf0a1
S		 250enum ath9k_int {
251 ATH9K_INT_RX = 0x00000001,
252 ATH9K_INT_RXDESC = 0x00000002,
b5c80475
FF		 253 ATH9K_INT_RXHP = 0x00000001,
254 ATH9K_INT_RXLP = 0x00000002,
394cf0a1
S		 255 ATH9K_INT_RXNOFRM = 0x00000008,
256 ATH9K_INT_RXEOL = 0x00000010,
257 ATH9K_INT_RXORN = 0x00000020,
258 ATH9K_INT_TX = 0x00000040,
259 ATH9K_INT_TXDESC = 0x00000080,
260 ATH9K_INT_TIM_TIMER = 0x00000100,
aea702b7 261 ATH9K_INT_BB_WATCHDOG = 0x00000400,
394cf0a1
S		 262 ATH9K_INT_TXURN = 0x00000800,
263 ATH9K_INT_MIB = 0x00001000,
264 ATH9K_INT_RXPHY = 0x00004000,
265 ATH9K_INT_RXKCM = 0x00008000,
266 ATH9K_INT_SWBA = 0x00010000,
267 ATH9K_INT_BMISS = 0x00040000,
268 ATH9K_INT_BNR = 0x00100000,
269 ATH9K_INT_TIM = 0x00200000,
270 ATH9K_INT_DTIM = 0x00400000,
271 ATH9K_INT_DTIMSYNC = 0x00800000,
272 ATH9K_INT_GPIO = 0x01000000,
273 ATH9K_INT_CABEND = 0x02000000,
4af9cf4f 274 ATH9K_INT_TSFOOR = 0x04000000,
ff155a45 275 ATH9K_INT_GENTIMER = 0x08000000,
394cf0a1
S		 276 ATH9K_INT_CST = 0x10000000,
277 ATH9K_INT_GTT = 0x20000000,
278 ATH9K_INT_FATAL = 0x40000000,
279 ATH9K_INT_GLOBAL = 0x80000000,
280 ATH9K_INT_BMISC = ATH9K_INT_TIM |
281 ATH9K_INT_DTIM |
282 ATH9K_INT_DTIMSYNC |
4af9cf4f 283 ATH9K_INT_TSFOOR |
394cf0a1
S		 284 ATH9K_INT_CABEND,
285 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
286 ATH9K_INT_RXDESC |
287 ATH9K_INT_RXEOL |
288 ATH9K_INT_RXORN |
289 ATH9K_INT_TXURN |
290 ATH9K_INT_TXDESC |
291 ATH9K_INT_MIB |
292 ATH9K_INT_RXPHY |
293 ATH9K_INT_RXKCM |
294 ATH9K_INT_SWBA |
295 ATH9K_INT_BMISS |
296 ATH9K_INT_GPIO,
297 ATH9K_INT_NOCARD = 0xffffffff
298};
f078f209 299
394cf0a1
S		 300#define CHANNEL_CW_INT 0x00002
301#define CHANNEL_CCK 0x00020
302#define CHANNEL_OFDM 0x00040
303#define CHANNEL_2GHZ 0x00080
304#define CHANNEL_5GHZ 0x00100
305#define CHANNEL_PASSIVE 0x00200
306#define CHANNEL_DYN 0x00400
307#define CHANNEL_HALF 0x04000
308#define CHANNEL_QUARTER 0x08000
309#define CHANNEL_HT20 0x10000
310#define CHANNEL_HT40PLUS 0x20000
311#define CHANNEL_HT40MINUS 0x40000
312
394cf0a1
S		 313#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
314#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
315#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
316#define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
317#define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
318#define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
319#define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
320#define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
321#define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
322#define CHANNEL_ALL \
323 (CHANNEL_OFDM| \
324 CHANNEL_CCK| \
325 CHANNEL_2GHZ | \
326 CHANNEL_5GHZ | \
327 CHANNEL_HT20 | \
328 CHANNEL_HT40PLUS | \
329 CHANNEL_HT40MINUS)
330
20bd2a09 331struct ath9k_hw_cal_data {
394cf0a1
S		 332 u16 channel;
333 u32 channelFlags;
394cf0a1 334 int32_t CalValid;
394cf0a1
S		 335 int8_t iCoff;
336 int8_t qCoff;
717f6bed 337 bool paprd_done;
4254bc1c 338 bool nfcal_pending;
70cf1533 339 bool nfcal_interference;
717f6bed
FF		 340 u16 small_signal_gain[AR9300_MAX_CHAINS];
341 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
20bd2a09
FF		 342 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
343};
344
345struct ath9k_channel {
346 struct ieee80211_channel *chan;
093115b7 347 struct ar5416AniState ani;
20bd2a09
FF		 348 u16 channel;
349 u32 channelFlags;
350 u32 chanmode;
d9891c78 351 s16 noisefloor;
394cf0a1 352};
f078f209 353
394cf0a1
S		 354#define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
355 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
356 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
357 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
358#define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
359#define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
360#define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
394cf0a1
S		 361#define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
362#define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
6b42e8d0 363#define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
394cf0a1 364 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
6b42e8d0 365 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
394cf0a1
S		 366
367/* These macros check chanmode and not channelFlags */
368#define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
369#define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
370 ((_c)->chanmode == CHANNEL_G_HT20))
371#define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
372 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
373 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
374 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
375#define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
376
377enum ath9k_power_mode {
378 ATH9K_PM_AWAKE = 0,
379 ATH9K_PM_FULL_SLEEP,
380 ATH9K_PM_NETWORK_SLEEP,
381 ATH9K_PM_UNDEFINED
382};
f078f209 383
394cf0a1
S		 384enum ath9k_tp_scale {
385 ATH9K_TP_SCALE_MAX = 0,
386 ATH9K_TP_SCALE_50,
387 ATH9K_TP_SCALE_25,
388 ATH9K_TP_SCALE_12,
389 ATH9K_TP_SCALE_MIN
390};
f078f209 391
394cf0a1
S		 392enum ser_reg_mode {
393 SER_REG_MODE_OFF = 0,
394 SER_REG_MODE_ON = 1,
395 SER_REG_MODE_AUTO = 2,
396};
f078f209 397
ad7b8060
VT		 398enum ath9k_rx_qtype {
399 ATH9K_RX_QUEUE_HP,
400 ATH9K_RX_QUEUE_LP,
401 ATH9K_RX_QUEUE_MAX,
402};
403
394cf0a1
S		 404struct ath9k_beacon_state {
405 u32 bs_nexttbtt;
406 u32 bs_nextdtim;
407 u32 bs_intval;
408#define ATH9K_BEACON_PERIOD 0x0000ffff
409#define ATH9K_BEACON_ENA 0x00800000
410#define ATH9K_BEACON_RESET_TSF 0x01000000
4af9cf4f 411#define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
394cf0a1
S		 412 u32 bs_dtimperiod;
413 u16 bs_cfpperiod;
414 u16 bs_cfpmaxduration;
415 u32 bs_cfpnext;
416 u16 bs_timoffset;
417 u16 bs_bmissthreshold;
418 u32 bs_sleepduration;
4af9cf4f 419 u32 bs_tsfoor_threshold;
394cf0a1 420};
f078f209 421
394cf0a1
S		 422struct chan_centers {
423 u16 synth_center;
424 u16 ctl_center;
425 u16 ext_center;
426};
f078f209 427
394cf0a1
S		 428enum {
429 ATH9K_RESET_POWER_ON,
430 ATH9K_RESET_WARM,
431 ATH9K_RESET_COLD,
432};
f078f209 433
d535a42a
S		 434struct ath9k_hw_version {
435 u32 magic;
436 u16 devid;
437 u16 subvendorid;
438 u32 macVersion;
439 u16 macRev;
440 u16 phyRev;
441 u16 analog5GhzRev;
442 u16 analog2GhzRev;
aeac355d 443 u16 subsysid;
d535a42a 444};
394cf0a1 445
ff155a45
VT		 446/* Generic TSF timer definitions */
447
448#define ATH_MAX_GEN_TIMER 16
449
450#define AR_GENTMR_BIT(_index) (1 << (_index))
451
452/*
77c2061d 453 * Using de Bruijin sequence to look up 1's index in a 32 bit number
ff155a45
VT		 454 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
455 */
c90017dd 456#define debruijn32 0x077CB531U
ff155a45
VT		 457
458struct ath_gen_timer_configuration {
459 u32 next_addr;
460 u32 period_addr;
461 u32 mode_addr;
462 u32 mode_mask;
463};
464
465struct ath_gen_timer {
466 void (*trigger)(void *arg);
467 void (*overflow)(void *arg);
468 void *arg;
469 u8 index;
470};
471
472struct ath_gen_timer_table {
473 u32 gen_timer_index[32];
474 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
475 union {
476 unsigned long timer_bits;
477 u16 val;
478 } timer_mask;
479};
480
21cc630f
VT		 481struct ath_hw_antcomb_conf {
482 u8 main_lna_conf;
483 u8 alt_lna_conf;
484 u8 fast_div_bias;
485};
486
d70357d5
LR		 487/**
488 * struct ath_hw_private_ops - callbacks used internally by hardware code
489 *
490 * This structure contains private callbacks designed to only be used internally
491 * by the hardware core.
492 *
795f5e2c
LR		 493 * @init_cal_settings: setup types of calibrations supported
494 * @init_cal: starts actual calibration
495 *
d70357d5 496 * @init_mode_regs: Initializes mode registers
991312d8 497 * @init_mode_gain_regs: Initialize TX/RX gain registers
d70357d5 498 * @macversion_supported: If this specific mac revision is supported
8fe65368
LR		 499 *
500 * @rf_set_freq: change frequency
501 * @spur_mitigate_freq: spur mitigation
502 * @rf_alloc_ext_banks:
503 * @rf_free_ext_banks:
504 * @set_rf_regs:
64773964
LR		 505 * @compute_pll_control: compute the PLL control value to use for
506 * AR_RTC_PLL_CONTROL for a given channel
795f5e2c
LR		 507 * @setup_calibration: set up calibration
508 * @iscal_supported: used to query if a type of calibration is supported
ac0bb767 509 *
e36b27af
LR		 510 * @ani_cache_ini_regs: cache the values for ANI from the initial
511 * register settings through the register initialization.
d70357d5
LR		 512 */
513struct ath_hw_private_ops {
795f5e2c 514 /* Calibration ops */
d70357d5 515 void (*init_cal_settings)(struct ath_hw *ah);
795f5e2c
LR		 516 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
517
d70357d5 518 void (*init_mode_regs)(struct ath_hw *ah);
991312d8 519 void (*init_mode_gain_regs)(struct ath_hw *ah);
d70357d5 520 bool (*macversion_supported)(u32 macversion);
795f5e2c
LR		 521 void (*setup_calibration)(struct ath_hw *ah,
522 struct ath9k_cal_list *currCal);
8fe65368
LR		 523
524 /* PHY ops */
525 int (*rf_set_freq)(struct ath_hw *ah,
526 struct ath9k_channel *chan);
527 void (*spur_mitigate_freq)(struct ath_hw *ah,
528 struct ath9k_channel *chan);
529 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
530 void (*rf_free_ext_banks)(struct ath_hw *ah);
531 bool (*set_rf_regs)(struct ath_hw *ah,
532 struct ath9k_channel *chan,
533 u16 modesIndex);
534 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
535 void (*init_bb)(struct ath_hw *ah,
536 struct ath9k_channel *chan);
537 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
538 void (*olc_init)(struct ath_hw *ah);
539 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
540 void (*mark_phy_inactive)(struct ath_hw *ah);
541 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
542 bool (*rfbus_req)(struct ath_hw *ah);
543 void (*rfbus_done)(struct ath_hw *ah);
544 void (*enable_rfkill)(struct ath_hw *ah);
545 void (*restore_chainmask)(struct ath_hw *ah);
546 void (*set_diversity)(struct ath_hw *ah, bool value);
64773964
LR		 547 u32 (*compute_pll_control)(struct ath_hw *ah,
548 struct ath9k_channel *chan);
c16fcb49
FF		 549 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
550 int param);
641d9921 551 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
ac0bb767
LR		 552
553 /* ANI */
e36b27af 554 void (*ani_cache_ini_regs)(struct ath_hw *ah);
d70357d5
LR		 555};
556
557/**
558 * struct ath_hw_ops - callbacks used by hardware code and driver code
559 *
560 * This structure contains callbacks designed to to be used internally by
561 * hardware code and also by the lower level driver.
562 *
563 * @config_pci_powersave:
795f5e2c 564 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
d70357d5
LR		 565 */
566struct ath_hw_ops {
567 void (*config_pci_powersave)(struct ath_hw *ah,
568 int restore,
569 int power_off);
cee1f625 570 void (*rx_enable)(struct ath_hw *ah);
87d5efbb
VT		 571 void (*set_desc_link)(void *ds, u32 link);
572 void (*get_desc_link)(void *ds, u32 **link);
795f5e2c
LR		 573 bool (*calibrate)(struct ath_hw *ah,
574 struct ath9k_channel *chan,
575 u8 rxchainmask,
576 bool longcal);
55e82df4 577 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
cc610ac0
VT		 578 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
579 bool is_firstseg, bool is_is_lastseg,
580 const void *ds0, dma_addr_t buf_addr,
581 unsigned int qcu);
582 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
583 struct ath_tx_status *ts);
584 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
585 u32 pktLen, enum ath9k_pkt_type type,
586 u32 txPower, u32 keyIx,
587 enum ath9k_key_type keyType,
588 u32 flags);
589 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
590 void *lastds,
591 u32 durUpdateEn, u32 rtsctsRate,
592 u32 rtsctsDuration,
593 struct ath9k_11n_rate_series series[],
594 u32 nseries, u32 flags);
595 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
596 u32 aggrLen);
597 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
598 u32 numDelims);
599 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
600 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
601 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
602 u32 burstDuration);
603 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
604 u32 vmf);
d70357d5
LR		 605};
606
f2552e28
FF		 607struct ath_nf_limits {
608 s16 max;
609 s16 min;
610 s16 nominal;
611};
612
cbe61d8a 613struct ath_hw {
b002a4a9 614 struct ieee80211_hw *hw;
27c51f1a 615 struct ath_common common;
cbe61d8a 616 struct ath9k_hw_version hw_version;
2660b81a
S		 617 struct ath9k_ops_config config;
618 struct ath9k_hw_capabilities caps;
cac4220b 619 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
2660b81a 620 struct ath9k_channel *curchan;
394cf0a1 621
cbe61d8a
S		 622 union {
623 struct ar5416_eeprom_def def;
624 struct ar5416_eeprom_4k map4k;
475f5989 625 struct ar9287_eeprom map9287;
15c9ee7a 626 struct ar9300_eeprom ar9300_eep;
2660b81a 627 } eeprom;
f74df6fb 628 const struct eeprom_ops *eep_ops;
cbe61d8a
S		 629
630 bool sw_mgmt_crypto;
2660b81a 631 bool is_pciexpress;
5f841b41 632 bool is_monitoring;
2eb46d9b 633 bool need_an_top2_fixup;
2660b81a 634 u16 tx_trig_level;
f2552e28 635
bbacee13 636 u32 nf_regs[6];
f2552e28
FF		 637 struct ath_nf_limits nf_2g;
638 struct ath_nf_limits nf_5g;
2660b81a
S		 639 u16 rfsilent;
640 u32 rfkill_gpio;
641 u32 rfkill_polarity;
cbe61d8a 642 u32 ah_flags;
394cf0a1 643
d7e7d229
LR		 644 bool htc_reset_init;
645
2660b81a
S		 646 enum nl80211_iftype opmode;
647 enum ath9k_power_mode power_mode;
f078f209 648
20bd2a09 649 struct ath9k_hw_cal_data *caldata;
a13883b0 650 struct ath9k_pacal_info pacal_info;
2660b81a
S		 651 struct ar5416Stats stats;
652 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
653
654 int16_t curchan_rad_index;
3069168c 655 enum ath9k_int imask;
74bad5cb 656 u32 imrs2_reg;
2660b81a
S		 657 u32 txok_interrupt_mask;
658 u32 txerr_interrupt_mask;
659 u32 txdesc_interrupt_mask;
660 u32 txeol_interrupt_mask;
661 u32 txurn_interrupt_mask;
662 bool chip_fullsleep;
663 u32 atim_window;
6a2b9e8c
S		 664
665 /* Calibration */
6497827f 666 u32 supp_cals;
cbfe9468
S		 667 struct ath9k_cal_list iq_caldata;
668 struct ath9k_cal_list adcgain_caldata;
cbfe9468 669 struct ath9k_cal_list adcdc_caldata;
df23acaa 670 struct ath9k_cal_list tempCompCalData;
cbfe9468
S		 671 struct ath9k_cal_list *cal_list;
672 struct ath9k_cal_list *cal_list_last;
673 struct ath9k_cal_list *cal_list_curr;
2660b81a
S		 674#define totalPowerMeasI meas0.unsign
675#define totalPowerMeasQ meas1.unsign
676#define totalIqCorrMeas meas2.sign
677#define totalAdcIOddPhase meas0.unsign
678#define totalAdcIEvenPhase meas1.unsign
679#define totalAdcQOddPhase meas2.unsign
680#define totalAdcQEvenPhase meas3.unsign
681#define totalAdcDcOffsetIOddPhase meas0.sign
682#define totalAdcDcOffsetIEvenPhase meas1.sign
683#define totalAdcDcOffsetQOddPhase meas2.sign
684#define totalAdcDcOffsetQEvenPhase meas3.sign
f078f209
LR		 685 union {
686 u32 unsign[AR5416_MAX_CHAINS];
687 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 688 } meas0;
f078f209
LR		 689 union {
690 u32 unsign[AR5416_MAX_CHAINS];
691 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 692 } meas1;
f078f209
LR		 693 union {
694 u32 unsign[AR5416_MAX_CHAINS];
695 int32_t sign[AR5416_MAX_CHAINS];
2660b81a 696 } meas2;
f078f209
LR		 697 union {
698 u32 unsign[AR5416_MAX_CHAINS];
699 int32_t sign[AR5416_MAX_CHAINS];
2660b81a
S		 700 } meas3;
701 u16 cal_samples;
6a2b9e8c 702
2660b81a
S		 703 u32 sta_id1_defaults;
704 u32 misc_mode;
f078f209
LR		 705 enum {
706 AUTO_32KHZ,
707 USE_32KHZ,
708 DONT_USE_32KHZ,
2660b81a 709 } enable_32kHz_clock;
6a2b9e8c 710
d70357d5
LR		 711 /* Private to hardware code */
712 struct ath_hw_private_ops private_ops;
713 /* Accessed by the lower level driver */
714 struct ath_hw_ops ops;
715
e68a060b 716 /* Used to program the radio on non single-chip devices */
2660b81a
S		 717 u32 *analogBank0Data;
718 u32 *analogBank1Data;
719 u32 *analogBank2Data;
720 u32 *analogBank3Data;
721 u32 *analogBank6Data;
722 u32 *analogBank6TPCData;
723 u32 *analogBank7Data;
724 u32 *addac5416_21;
725 u32 *bank6Temp;
726
597a94b3 727 u8 txpower_limit;
2660b81a 728 int16_t txpower_indexoffset;
e239d859 729 int coverage_class;
2660b81a
S		 730 u32 beacon_interval;
731 u32 slottime;
2660b81a 732 u32 globaltxtimeout;
6a2b9e8c
S		 733
734 /* ANI */
2660b81a 735 u32 proc_phyerr;
2660b81a 736 u32 aniperiod;
2660b81a
S		 737 int totalSizeDesired[5];
738 int coarse_high[5];
739 int coarse_low[5];
740 int firpwr[5];
741 enum ath9k_ani_cmd ani_function;
742
af03abec 743 /* Bluetooth coexistance */
766ec4a9 744 struct ath_btcoex_hw btcoex_hw;
af03abec 745
2660b81a 746 u32 intr_txqs;
2660b81a
S		 747 u8 txchainmask;
748 u8 rxchainmask;
749
8bd1d07f
SB		 750 u32 originalGain[22];
751 int initPDADC;
752 int PDADCdelta;
08fc5c1b 753 u8 led_pin;
8bd1d07f 754
2660b81a
S		 755 struct ar5416IniArray iniModes;
756 struct ar5416IniArray iniCommon;
757 struct ar5416IniArray iniBank0;
758 struct ar5416IniArray iniBB_RfGain;
759 struct ar5416IniArray iniBank1;
760 struct ar5416IniArray iniBank2;
761 struct ar5416IniArray iniBank3;
762 struct ar5416IniArray iniBank6;
763 struct ar5416IniArray iniBank6TPC;
764 struct ar5416IniArray iniBank7;
765 struct ar5416IniArray iniAddac;
766 struct ar5416IniArray iniPcieSerdes;
13ce3e99 767 struct ar5416IniArray iniPcieSerdesLowPower;
2660b81a
S		 768 struct ar5416IniArray iniModesAdditional;
769 struct ar5416IniArray iniModesRxGain;
770 struct ar5416IniArray iniModesTxGain;
8564328d 771 struct ar5416IniArray iniModes_9271_1_0_only;
193cd458
S		 772 struct ar5416IniArray iniCckfirNormal;
773 struct ar5416IniArray iniCckfirJapan2484;
70807e99
S		 774 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
775 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
776 struct ar5416IniArray iniModes_9271_ANI_reg;
777 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
778 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
ff155a45 779
13ce3e99
LR		 780 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
781 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
782 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
783 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
784
ff155a45
VT		 785 u32 intr_gen_timer_trigger;
786 u32 intr_gen_timer_thresh;
787 struct ath_gen_timer_table hw_gen_timers;
744d4025
VT		 788
789 struct ar9003_txs *ts_ring;
790 void *ts_start;
791 u32 ts_paddr_start;
792 u32 ts_paddr_end;
793 u16 ts_tail;
794 u8 ts_size;
aea702b7
LR		 795
796 u32 bb_watchdog_last_status;
797 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
717f6bed
FF		 798
799 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
800 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
9a658d2b
LR		 801 /*
802 * Store the permanent value of Reg 0x4004in WARegVal
803 * so we dont have to R/M/W. We should not be reading
804 * this register when in sleep states.
805 */
806 u32 WARegVal;
f078f209 807};
f078f209 808
9e4bffd2
LR		 809static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
810{
811 return &ah->common;
812}
813
814static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
815{
816 return &(ath9k_hw_common(ah)->regulatory);
817}
818
d70357d5
LR		 819static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
820{
821 return &ah->private_ops;
822}
823
824static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
825{
826 return &ah->ops;
827}
828
f637cfd6 829/* Initialization, Detach, Reset */
394cf0a1 830const char *ath9k_hw_probe(u16 vendorid, u16 devid);
285f2dda 831void ath9k_hw_deinit(struct ath_hw *ah);
f637cfd6 832int ath9k_hw_init(struct ath_hw *ah);
cbe61d8a 833int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
20bd2a09 834 struct ath9k_hw_cal_data *caldata, bool bChannelChange);
a9a29ce6 835int ath9k_hw_fill_cap_info(struct ath_hw *ah);
8fe65368 836u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
394cf0a1 837
394cf0a1 838/* GPIO / RFKILL / Antennae */
cbe61d8a
S		 839void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
840u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
841void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
394cf0a1 842 u32 ah_signal_type);
cbe61d8a 843void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
cbe61d8a
S		 844u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
845void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
21cc630f
VT		 846void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
847 struct ath_hw_antcomb_conf *antconf);
848void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
849 struct ath_hw_antcomb_conf *antconf);
394cf0a1
S		 850
851/* General Operation */
0caa7b14 852bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
394cf0a1 853u32 ath9k_hw_reverse_bits(u32 val, u32 n);
cbe61d8a 854bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
4f0fc7c3 855u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 856 u8 phy, int kbps,
394cf0a1 857 u32 frameLen, u16 rateix, bool shortPreamble);
cbe61d8a 858void ath9k_hw_get_channel_centers(struct ath_hw *ah,
394cf0a1
S		 859 struct ath9k_channel *chan,
860 struct chan_centers *centers);
cbe61d8a
S		 861u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
862void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
863bool ath9k_hw_phy_disable(struct ath_hw *ah);
864bool ath9k_hw_disable(struct ath_hw *ah);
de40f316 865void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
cbe61d8a
S		 866void ath9k_hw_setopmode(struct ath_hw *ah);
867void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
f2b2143e
LR		 868void ath9k_hw_setbssidmask(struct ath_hw *ah);
869void ath9k_hw_write_associd(struct ath_hw *ah);
cbe61d8a
S		 870u64 ath9k_hw_gettsf64(struct ath_hw *ah);
871void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
872void ath9k_hw_reset_tsf(struct ath_hw *ah);
54e4cec6 873void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
0005baf4 874void ath9k_hw_init_global_settings(struct ath_hw *ah);
25c56eec 875void ath9k_hw_set11nmac2040(struct ath_hw *ah);
cbe61d8a
S		 876void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
877void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
394cf0a1 878 const struct ath9k_beacon_state *bs);
c9c99e5e 879bool ath9k_hw_check_alive(struct ath_hw *ah);
a91d75ae 880
9ecdef4b 881bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
a91d75ae 882
ff155a45
VT		 883/* Generic hw timer primitives */
884struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
885 void (*trigger)(void *),
886 void (*overflow)(void *),
887 void *arg,
888 u8 timer_index);
cd9bf689
LR		 889void ath9k_hw_gen_timer_start(struct ath_hw *ah,
890 struct ath_gen_timer *timer,
891 u32 timer_next,
892 u32 timer_period);
893void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
894
ff155a45
VT		 895void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
896void ath_gen_timer_isr(struct ath_hw *hw);
897
f934c4d9 898void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
2da4f01a 899
05020d23
S		 900/* HTC */
901void ath9k_hw_htc_resetinit(struct ath_hw *ah);
902
8fe65368
LR		 903/* PHY */
904void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
905 u32 *coef_mantissa, u32 *coef_exponent);
906
ebd5a14a
LR		 907/*
908 * Code Specific to AR5008, AR9001 or AR9002,
909 * we stuff these here to avoid callbacks for AR9003.
910 */
d8f492b7 911void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
ebd5a14a 912int ar9002_hw_rf_claim(struct ath_hw *ah);
78ec2677 913void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
e9141f71 914void ar9002_hw_update_async_fifo(struct ath_hw *ah);
6c94fdc9 915void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
d8f492b7 916
641d9921 917/*
aea702b7 918 * Code specific to AR9003, we stuff these here to avoid callbacks
641d9921
FF		 919 * for older families
920 */
aea702b7
LR		 921void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
922void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
923void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
717f6bed
FF		 924void ar9003_paprd_enable(struct ath_hw *ah, bool val);
925void ar9003_paprd_populate_single_table(struct ath_hw *ah,
20bd2a09
FF		 926 struct ath9k_hw_cal_data *caldata,
927 int chain);
928int ar9003_paprd_create_curve(struct ath_hw *ah,
929 struct ath9k_hw_cal_data *caldata, int chain);
717f6bed
FF		 930int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
931int ar9003_paprd_init_table(struct ath_hw *ah);
932bool ar9003_paprd_is_done(struct ath_hw *ah);
933void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
641d9921
FF		 934
935/* Hardware family op attach helpers */
8fe65368 936void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
8525f280
LR		 937void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
938void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
8fe65368 939
795f5e2c
LR		 940void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
941void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
942
b3950e6a
LR		 943void ar9002_hw_attach_ops(struct ath_hw *ah);
944void ar9003_hw_attach_ops(struct ath_hw *ah);
945
c2ba3342 946void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767
LR		 947/*
948 * ANI work can be shared between all families but a next
949 * generation implementation of ANI will be used only for AR9003 only
950 * for now as the other families still need to be tested with the same
e36b27af
LR		 951 * next generation ANI. Feel free to start testing it though for the
952 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
ac0bb767 953 */
e36b27af 954extern int modparam_force_new_ani;
8eb4980c 955void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
bfc472bb 956void ath9k_hw_proc_mib_event(struct ath_hw *ah);
95792178 957void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
ac0bb767 958
7b6840ab
VT		 959#define ATH_PCIE_CAP_LINK_CTRL 0x70
960#define ATH_PCIE_CAP_LINK_L0S 1
961#define ATH_PCIE_CAP_LINK_L1 2
962
73377256
LR		 963#define ATH9K_CLOCK_RATE_CCK 22
964#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
965#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
966#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
967
f078f209 968#endif
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