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ath9k_hw: restore mac address reading logic
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
CommitLineData
f078f209 1/*
b3950e6a 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
f078f209
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/io.h>
18#include <asm/unaligned.h>
19
af03abec 20#include "hw.h"
d70357d5 21#include "hw-ops.h"
cfe8cba9 22#include "rc.h"
f078f209 23
4febf7b8
LR		 24#define ATH9K_CLOCK_RATE_CCK 22
25#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
f078f209 27
cbe61d8a 28static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
f078f209 29
7322fd19
LR		 30MODULE_AUTHOR("Atheros Communications");
31MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
32MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
33MODULE_LICENSE("Dual BSD/GPL");
34
35static int __init ath9k_init(void)
36{
37 return 0;
38}
39module_init(ath9k_init);
40
41static void __exit ath9k_exit(void)
42{
43 return;
44}
45module_exit(ath9k_exit);
46
d70357d5
LR		 47/* Private hardware callbacks */
48
49static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
50{
51 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
52}
53
54static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
55{
56 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
57}
58
59static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
60{
61 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
62
63 return priv_ops->macversion_supported(ah->hw_version.macVersion);
64}
65
64773964
LR		 66static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
67 struct ath9k_channel *chan)
68{
69 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
70}
71
991312d8
LR		 72static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
73{
74 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
78}
79
f1dc5600
S		 80/********************/
81/* Helper Functions */
82/********************/
f078f209 83
cbe61d8a 84static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 85{
b002a4a9 86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 87
2660b81a 88 if (!ah->curchan) /* should really check for CCK instead */
4febf7b8
LR		 89 return usecs *ATH9K_CLOCK_RATE_CCK;
90 if (conf->channel->band == IEEE80211_BAND_2GHZ)
91 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
92 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
f1dc5600
S		 93}
94
cbe61d8a 95static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
f1dc5600 96{
b002a4a9 97 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
cbe61d8a 98
4febf7b8 99 if (conf_is_ht40(conf))
f1dc5600
S		 100 return ath9k_hw_mac_clks(ah, usecs) * 2;
101 else
102 return ath9k_hw_mac_clks(ah, usecs);
103}
f078f209 104
0caa7b14 105bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
f078f209
LR		 106{
107 int i;
108
0caa7b14
S		 109 BUG_ON(timeout < AH_TIME_QUANTUM);
110
111 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
f078f209
LR		 112 if ((REG_READ(ah, reg) & mask) == val)
113 return true;
114
115 udelay(AH_TIME_QUANTUM);
116 }
04bd4638 117
c46917bb
LR		 118 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
119 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
120 timeout, reg, REG_READ(ah, reg), mask, val);
f078f209 121
f1dc5600 122 return false;
f078f209 123}
7322fd19 124EXPORT_SYMBOL(ath9k_hw_wait);
f078f209
LR		 125
126u32 ath9k_hw_reverse_bits(u32 val, u32 n)
127{
128 u32 retval;
129 int i;
130
131 for (i = 0, retval = 0; i < n; i++) {
132 retval = (retval << 1) | (val & 1);
133 val >>= 1;
134 }
135 return retval;
136}
137
cbe61d8a 138bool ath9k_get_channel_edges(struct ath_hw *ah,
f1dc5600
S		 139 u16 flags, u16 *low,
140 u16 *high)
f078f209 141{
2660b81a 142 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 143
f1dc5600
S		 144 if (flags & CHANNEL_5GHZ) {
145 *low = pCap->low_5ghz_chan;
146 *high = pCap->high_5ghz_chan;
147 return true;
f078f209 148 }
f1dc5600
S		 149 if ((flags & CHANNEL_2GHZ)) {
150 *low = pCap->low_2ghz_chan;
151 *high = pCap->high_2ghz_chan;
152 return true;
153 }
154 return false;
f078f209
LR		 155}
156
cbe61d8a 157u16 ath9k_hw_computetxtime(struct ath_hw *ah,
545750d3 158 u8 phy, int kbps,
f1dc5600
S		 159 u32 frameLen, u16 rateix,
160 bool shortPreamble)
f078f209 161{
f1dc5600 162 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
f078f209 163
f1dc5600
S		 164 if (kbps == 0)
165 return 0;
f078f209 166
545750d3 167 switch (phy) {
46d14a58 168 case WLAN_RC_PHY_CCK:
f1dc5600 169 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
545750d3 170 if (shortPreamble)
f1dc5600
S		 171 phyTime >>= 1;
172 numBits = frameLen << 3;
173 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
174 break;
46d14a58 175 case WLAN_RC_PHY_OFDM:
2660b81a 176 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
f1dc5600
S		 177 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
178 numBits = OFDM_PLCP_BITS + (frameLen << 3);
179 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
180 txTime = OFDM_SIFS_TIME_QUARTER
181 + OFDM_PREAMBLE_TIME_QUARTER
182 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
2660b81a
S		 183 } else if (ah->curchan &&
184 IS_CHAN_HALF_RATE(ah->curchan)) {
f1dc5600
S		 185 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
186 numBits = OFDM_PLCP_BITS + (frameLen << 3);
187 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
188 txTime = OFDM_SIFS_TIME_HALF +
189 OFDM_PREAMBLE_TIME_HALF
190 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
191 } else {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
196 + (numSymbols * OFDM_SYMBOL_TIME);
197 }
198 break;
199 default:
c46917bb 200 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
545750d3 201 "Unknown phy %u (rate ix %u)\n", phy, rateix);
f1dc5600
S		 202 txTime = 0;
203 break;
204 }
f078f209 205
f1dc5600
S		 206 return txTime;
207}
7322fd19 208EXPORT_SYMBOL(ath9k_hw_computetxtime);
f078f209 209
cbe61d8a 210void ath9k_hw_get_channel_centers(struct ath_hw *ah,
f1dc5600
S		 211 struct ath9k_channel *chan,
212 struct chan_centers *centers)
f078f209 213{
f1dc5600 214 int8_t extoff;
f078f209 215
f1dc5600
S		 216 if (!IS_CHAN_HT40(chan)) {
217 centers->ctl_center = centers->ext_center =
218 centers->synth_center = chan->channel;
219 return;
f078f209 220 }
f078f209 221
f1dc5600
S		 222 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
223 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
224 centers->synth_center =
225 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
226 extoff = 1;
227 } else {
228 centers->synth_center =
229 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
230 extoff = -1;
231 }
f078f209 232
f1dc5600
S		 233 centers->ctl_center =
234 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
6420014c 235 /* 25 MHz spacing is supported by hw but not on upper layers */
f1dc5600 236 centers->ext_center =
6420014c 237 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
f078f209
LR		 238}
239
f1dc5600
S		 240/******************/
241/* Chip Revisions */
242/******************/
243
cbe61d8a 244static void ath9k_hw_read_revisions(struct ath_hw *ah)
f078f209 245{
f1dc5600 246 u32 val;
f078f209 247
f1dc5600 248 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
f078f209 249
f1dc5600
S		 250 if (val == 0xFF) {
251 val = REG_READ(ah, AR_SREV);
d535a42a
S		 252 ah->hw_version.macVersion =
253 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
254 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
2660b81a 255 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
f1dc5600
S		 256 } else {
257 if (!AR_SREV_9100(ah))
d535a42a 258 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
f078f209 259
d535a42a 260 ah->hw_version.macRev = val & AR_SREV_REVISION;
f078f209 261
d535a42a 262 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
2660b81a 263 ah->is_pciexpress = true;
f1dc5600 264 }
f078f209
LR		 265}
266
cbe61d8a 267static int ath9k_hw_get_radiorev(struct ath_hw *ah)
f078f209 268{
f1dc5600
S		 269 u32 val;
270 int i;
f078f209 271
f1dc5600 272 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
f078f209 273
f1dc5600
S		 274 for (i = 0; i < 8; i++)
275 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
276 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
277 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
f078f209 278
f1dc5600 279 return ath9k_hw_reverse_bits(val, 8);
f078f209
LR		 280}
281
f1dc5600
S		 282/************************************/
283/* HW Attach, Detach, Init Routines */
284/************************************/
285
cbe61d8a 286static void ath9k_hw_disablepcie(struct ath_hw *ah)
f078f209 287{
feed029c 288 if (AR_SREV_9100(ah))
f1dc5600 289 return;
f078f209 290
f1dc5600
S		 291 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
294 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
295 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
296 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
297 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
298 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
299 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
f078f209 300
f1dc5600 301 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
f078f209
LR		 302}
303
1f3f0618 304/* This should work for all families including legacy */
cbe61d8a 305static bool ath9k_hw_chip_test(struct ath_hw *ah)
f078f209 306{
c46917bb 307 struct ath_common *common = ath9k_hw_common(ah);
1f3f0618 308 u32 regAddr[2] = { AR_STA_ID0 };
f1dc5600
S		 309 u32 regHold[2];
310 u32 patternData[4] = { 0x55555555,
311 0xaaaaaaaa,
312 0x66666666,
313 0x99999999 };
1f3f0618 314 int i, j, loop_max;
f078f209 315
1f3f0618
SB		 316 if (!AR_SREV_9300_20_OR_LATER(ah)) {
317 loop_max = 2;
318 regAddr[1] = AR_PHY_BASE + (8 << 2);
319 } else
320 loop_max = 1;
321
322 for (i = 0; i < loop_max; i++) {
f1dc5600
S		 323 u32 addr = regAddr[i];
324 u32 wrData, rdData;
f078f209 325
f1dc5600
S		 326 regHold[i] = REG_READ(ah, addr);
327 for (j = 0; j < 0x100; j++) {
328 wrData = (j << 16) | j;
329 REG_WRITE(ah, addr, wrData);
330 rdData = REG_READ(ah, addr);
331 if (rdData != wrData) {
c46917bb
LR		 332 ath_print(common, ATH_DBG_FATAL,
333 "address test failed "
334 "addr: 0x%08x - wr:0x%08x != "
335 "rd:0x%08x\n",
336 addr, wrData, rdData);
f1dc5600
S		 337 return false;
338 }
339 }
340 for (j = 0; j < 4; j++) {
341 wrData = patternData[j];
342 REG_WRITE(ah, addr, wrData);
343 rdData = REG_READ(ah, addr);
344 if (wrData != rdData) {
c46917bb
LR		 345 ath_print(common, ATH_DBG_FATAL,
346 "address test failed "
347 "addr: 0x%08x - wr:0x%08x != "
348 "rd:0x%08x\n",
349 addr, wrData, rdData);
f1dc5600
S		 350 return false;
351 }
f078f209 352 }
f1dc5600 353 REG_WRITE(ah, regAddr[i], regHold[i]);
f078f209 354 }
f1dc5600 355 udelay(100);
cbe61d8a 356
f078f209
LR		 357 return true;
358}
359
b8b0f377 360static void ath9k_hw_init_config(struct ath_hw *ah)
f1dc5600
S		 361{
362 int i;
f078f209 363
2660b81a
S		 364 ah->config.dma_beacon_response_time = 2;
365 ah->config.sw_beacon_response_time = 10;
366 ah->config.additional_swba_backoff = 0;
367 ah->config.ack_6mb = 0x0;
368 ah->config.cwm_ignore_extcca = 0;
369 ah->config.pcie_powersave_enable = 0;
2660b81a 370 ah->config.pcie_clock_req = 0;
2660b81a
S		 371 ah->config.pcie_waen = 0;
372 ah->config.analog_shiftreg = 1;
2660b81a
S		 373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
31a0bd3c
LR		 377
378 /*
379 * For now ANI is disabled for AR9003, it is still
380 * being tested.
381 */
382 if (!AR_SREV_9300_20_OR_LATER(ah))
383 ah->config.enable_ani = 1;
f078f209 384
f1dc5600 385 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2660b81a
S		 386 ah->config.spurchans[i][0] = AR_NO_SPUR;
387 ah->config.spurchans[i][1] = AR_NO_SPUR;
f078f209
LR		 388 }
389
5ffaf8a3
LR		 390 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
391 ah->config.ht_enable = 1;
392 else
393 ah->config.ht_enable = 0;
394
0ce024cb 395 ah->config.rx_intr_mitigation = true;
6158425b
LR		 396
397 /*
398 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
399 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
400 * This means we use it for all AR5416 devices, and the few
401 * minor PCI AR9280 devices out there.
402 *
403 * Serialization is required because these devices do not handle
404 * well the case of two concurrent reads/writes due to the latency
405 * involved. During one read/write another read/write can be issued
406 * on another CPU while the previous read/write may still be working
407 * on our hardware, if we hit this case the hardware poops in a loop.
408 * We prevent this by serializing reads and writes.
409 *
410 * This issue is not present on PCI-Express devices or pre-AR5416
411 * devices (legacy, 802.11abg).
412 */
413 if (num_possible_cpus() > 1)
2d6a5e95 414 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
f078f209
LR		 415}
416
50aca25b 417static void ath9k_hw_init_defaults(struct ath_hw *ah)
f078f209 418{
608b88cb
LR		 419 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
420
421 regulatory->country_code = CTRY_DEFAULT;
422 regulatory->power_limit = MAX_RATE_POWER;
423 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
424
d535a42a 425 ah->hw_version.magic = AR5416_MAGIC;
d535a42a 426 ah->hw_version.subvendorid = 0;
f078f209
LR		 427
428 ah->ah_flags = 0;
f078f209
LR		 429 if (!AR_SREV_9100(ah))
430 ah->ah_flags = AH_USE_EEPROM;
431
2660b81a 432 ah->atim_window = 0;
2660b81a
S		 433 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
434 ah->beacon_interval = 100;
435 ah->enable_32kHz_clock = DONT_USE_32KHZ;
436 ah->slottime = (u32) -1;
2660b81a 437 ah->globaltxtimeout = (u32) -1;
cbdec975 438 ah->power_mode = ATH9K_PM_UNDEFINED;
f078f209
LR		 439}
440
cbe61d8a 441static int ath9k_hw_rf_claim(struct ath_hw *ah)
f078f209 442{
f1dc5600
S		 443 u32 val;
444
445 REG_WRITE(ah, AR_PHY(0), 0x00000007);
446
447 val = ath9k_hw_get_radiorev(ah);
448 switch (val & AR_RADIO_SREV_MAJOR) {
449 case 0:
450 val = AR_RAD5133_SREV_MAJOR;
451 break;
452 case AR_RAD5133_SREV_MAJOR:
453 case AR_RAD5122_SREV_MAJOR:
454 case AR_RAD2133_SREV_MAJOR:
455 case AR_RAD2122_SREV_MAJOR:
456 break;
f078f209 457 default:
c46917bb
LR		 458 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
459 "Radio Chip Rev 0x%02X not supported\n",
460 val & AR_RADIO_SREV_MAJOR);
f1dc5600 461 return -EOPNOTSUPP;
f078f209 462 }
f078f209 463
d535a42a 464 ah->hw_version.analog5GhzRev = val;
f078f209 465
f1dc5600 466 return 0;
f078f209
LR		 467}
468
cbe61d8a 469static int ath9k_hw_init_macaddr(struct ath_hw *ah)
f078f209 470{
1510718d 471 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 472 u32 sum;
473 int i;
474 u16 eeval;
49101676 475 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
f078f209
LR		 476
477 sum = 0;
478 for (i = 0; i < 3; i++) {
49101676 479 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
f078f209 480 sum += eeval;
1510718d
LR		 481 common->macaddr[2 * i] = eeval >> 8;
482 common->macaddr[2 * i + 1] = eeval & 0xff;
f078f209 483 }
d8baa939 484 if (sum == 0 || sum == 0xffff * 3)
f078f209 485 return -EADDRNOTAVAIL;
f078f209
LR		 486
487 return 0;
488}
489
f637cfd6 490static int ath9k_hw_post_init(struct ath_hw *ah)
f078f209 491{
f1dc5600 492 int ecode;
f078f209 493
527d485f
S		 494 if (!AR_SREV_9271(ah)) {
495 if (!ath9k_hw_chip_test(ah))
496 return -ENODEV;
497 }
f078f209 498
f1dc5600
S		 499 ecode = ath9k_hw_rf_claim(ah);
500 if (ecode != 0)
f078f209 501 return ecode;
f078f209 502
f637cfd6 503 ecode = ath9k_hw_eeprom_init(ah);
f1dc5600
S		 504 if (ecode != 0)
505 return ecode;
7d01b221 506
c46917bb
LR		 507 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
508 "Eeprom VER: %d, REV: %d\n",
509 ah->eep_ops->get_eeprom_ver(ah),
510 ah->eep_ops->get_eeprom_rev(ah));
7d01b221 511
8fe65368
LR		 512 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
513 if (ecode) {
514 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
515 "Failed allocating banks for "
516 "external radio\n");
517 return ecode;
574d6b12 518 }
f078f209 519
f1dc5600
S		 520 if (!AR_SREV_9100(ah)) {
521 ath9k_hw_ani_setup(ah);
f637cfd6 522 ath9k_hw_ani_init(ah);
f078f209
LR		 523 }
524
f078f209
LR		 525 return 0;
526}
527
aa8bc9ef 528static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
aa4058ae 529{
2eb46d9b
PR		 530 struct base_eep_header *pBase = &(ah->eeprom.def.baseEepHeader);
531 struct ath_common *common = ath9k_hw_common(ah);
f078f209 532
2eb46d9b 533 ah->need_an_top2_fixup = (ah->hw_version.devid == AR9280_DEVID_PCI) &&
939ad86d 534 !AR_SREV_9285(ah) && !AR_SREV_9271(ah) &&
2eb46d9b
PR		 535 ((pBase->version & 0xff) > 0x0a) &&
536 (pBase->pwdclkind == 0);
f078f209 537
2eb46d9b
PR		 538 if (ah->need_an_top2_fixup)
539 ath_print(common, ATH_DBG_EEPROM,
540 "needs fixup for AR_AN_TOP2 register\n");
aa4058ae
LR		 541}
542
8525f280
LR		 543static void ath9k_hw_attach_ops(struct ath_hw *ah)
544{
545 if (AR_SREV_9300_20_OR_LATER(ah))
546 ar9003_hw_attach_ops(ah);
547 else
548 ar9002_hw_attach_ops(ah);
549}
550
d70357d5
LR		 551/* Called for all hardware families */
552static int __ath9k_hw_init(struct ath_hw *ah)
aa4058ae 553{
c46917bb 554 struct ath_common *common = ath9k_hw_common(ah);
95fafca2 555 int r = 0;
aa4058ae 556
bab1f62e
LR		 557 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
558 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
aa4058ae
LR		 559
560 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
c46917bb
LR		 561 ath_print(common, ATH_DBG_FATAL,
562 "Couldn't reset chip\n");
95fafca2 563 return -EIO;
aa4058ae
LR		 564 }
565
bab1f62e
LR		 566 ath9k_hw_init_defaults(ah);
567 ath9k_hw_init_config(ah);
568
8525f280 569 ath9k_hw_attach_ops(ah);
d70357d5 570
9ecdef4b 571 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
c46917bb 572 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
95fafca2 573 return -EIO;
aa4058ae
LR		 574 }
575
576 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
577 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
578 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
579 ah->config.serialize_regmode =
580 SER_REG_MODE_ON;
581 } else {
582 ah->config.serialize_regmode =
583 SER_REG_MODE_OFF;
584 }
585 }
586
c46917bb 587 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
aa4058ae
LR		 588 ah->config.serialize_regmode);
589
f4709fdf
LR		 590 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
591 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
592 else
593 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
594
d70357d5 595 if (!ath9k_hw_macversion_supported(ah)) {
c46917bb
LR		 596 ath_print(common, ATH_DBG_FATAL,
597 "Mac Chip Rev 0x%02x.%x is not supported by "
598 "this driver\n", ah->hw_version.macVersion,
599 ah->hw_version.macRev);
95fafca2 600 return -EOPNOTSUPP;
aa4058ae
LR		 601 }
602
0df13da4 603 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
d7e7d229
LR		 604 ah->is_pciexpress = false;
605
aa4058ae 606 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
aa4058ae
LR		 607 ath9k_hw_init_cal_settings(ah);
608
609 ah->ani_function = ATH9K_ANI_ALL;
31a0bd3c 610 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
aa4058ae
LR		 611 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
612
613 ath9k_hw_init_mode_regs(ah);
614
615 if (ah->is_pciexpress)
93b1b37f 616 ath9k_hw_configpcipowersave(ah, 0, 0);
aa4058ae
LR		 617 else
618 ath9k_hw_disablepcie(ah);
619
d8f492b7
LR		 620 if (!AR_SREV_9300_20_OR_LATER(ah))
621 ar9002_hw_cck_chan14_spread(ah);
193cd458 622
f637cfd6 623 r = ath9k_hw_post_init(ah);
aa4058ae 624 if (r)
95fafca2 625 return r;
aa4058ae
LR		 626
627 ath9k_hw_init_mode_gain_regs(ah);
a9a29ce6
GJ		 628 r = ath9k_hw_fill_cap_info(ah);
629 if (r)
630 return r;
631
aa8bc9ef 632 ath9k_hw_init_eeprom_fix(ah);
f6688cd8 633
4f3acf81
LR		 634 r = ath9k_hw_init_macaddr(ah);
635 if (r) {
c46917bb
LR		 636 ath_print(common, ATH_DBG_FATAL,
637 "Failed to initialize MAC address\n");
95fafca2 638 return r;
f078f209
LR		 639 }
640
d7e7d229 641 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2660b81a 642 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
f1dc5600 643 else
2660b81a 644 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
f078f209 645
641d9921
FF		 646 if (AR_SREV_9300_20_OR_LATER(ah))
647 ar9003_hw_set_nf_limits(ah);
648
f1dc5600 649 ath9k_init_nfcal_hist_buffer(ah);
f078f209 650
211f5859
LR		 651 common->state = ATH_HW_INITIALIZED;
652
4f3acf81 653 return 0;
f078f209
LR		 654}
655
d70357d5
LR		 656int ath9k_hw_init(struct ath_hw *ah)
657{
658 int ret;
659 struct ath_common *common = ath9k_hw_common(ah);
660
661 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
662 switch (ah->hw_version.devid) {
663 case AR5416_DEVID_PCI:
664 case AR5416_DEVID_PCIE:
665 case AR5416_AR9100_DEVID:
666 case AR9160_DEVID_PCI:
667 case AR9280_DEVID_PCI:
668 case AR9280_DEVID_PCIE:
669 case AR9285_DEVID_PCIE:
db3cc53a
SB		 670 case AR9287_DEVID_PCI:
671 case AR9287_DEVID_PCIE:
d70357d5 672 case AR2427_DEVID_PCIE:
db3cc53a 673 case AR9300_DEVID_PCIE:
d70357d5
LR		 674 break;
675 default:
676 if (common->bus_ops->ath_bus_type == ATH_USB)
677 break;
678 ath_print(common, ATH_DBG_FATAL,
679 "Hardware device ID 0x%04x not supported\n",
680 ah->hw_version.devid);
681 return -EOPNOTSUPP;
682 }
683
684 ret = __ath9k_hw_init(ah);
685 if (ret) {
686 ath_print(common, ATH_DBG_FATAL,
687 "Unable to initialize hardware; "
688 "initialization status: %d\n", ret);
689 return ret;
690 }
691
692 return 0;
693}
694EXPORT_SYMBOL(ath9k_hw_init);
695
cbe61d8a 696static void ath9k_hw_init_qos(struct ath_hw *ah)
f078f209 697{
f1dc5600
S		 698 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
699 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
f078f209 700
f1dc5600
S		 701 REG_WRITE(ah, AR_QOS_NO_ACK,
702 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
703 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
704 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
705
706 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
707 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
708 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
709 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
710 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
f078f209
LR		 711}
712
cbe61d8a 713static void ath9k_hw_init_pll(struct ath_hw *ah,
f1dc5600 714 struct ath9k_channel *chan)
f078f209 715{
64773964 716 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
f078f209 717
d03a66c1 718 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
f078f209 719
c75724d1
LR		 720 /* Switch the core clock for ar9271 to 117Mhz */
721 if (AR_SREV_9271(ah)) {
25e2ab17
S		 722 udelay(500);
723 REG_WRITE(ah, 0x50040, 0x304);
c75724d1
LR		 724 }
725
f1dc5600
S		 726 udelay(RTC_PLL_SETTLE_DELAY);
727
728 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
f078f209
LR		 729}
730
cbe61d8a 731static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
d97809db 732 enum nl80211_iftype opmode)
f078f209 733{
152d530d 734 u32 imr_reg = AR_IMR_TXERR |
f1dc5600
S		 735 AR_IMR_TXURN |
736 AR_IMR_RXERR |
737 AR_IMR_RXORN |
738 AR_IMR_BCNMISC;
f078f209 739
66860240
VT		 740 if (AR_SREV_9300_20_OR_LATER(ah)) {
741 imr_reg |= AR_IMR_RXOK_HP;
742 if (ah->config.rx_intr_mitigation)
743 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
744 else
745 imr_reg |= AR_IMR_RXOK_LP;
f078f209 746
66860240
VT		 747 } else {
748 if (ah->config.rx_intr_mitigation)
749 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
750 else
751 imr_reg |= AR_IMR_RXOK;
752 }
753
754 if (ah->config.tx_intr_mitigation)
755 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
756 else
757 imr_reg |= AR_IMR_TXOK;
f078f209 758
d97809db 759 if (opmode == NL80211_IFTYPE_AP)
152d530d 760 imr_reg |= AR_IMR_MIB;
f078f209 761
152d530d 762 REG_WRITE(ah, AR_IMR, imr_reg);
74bad5cb
PR		 763 ah->imrs2_reg |= AR_IMR_S2_GTT;
764 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
f078f209 765
f1dc5600
S		 766 if (!AR_SREV_9100(ah)) {
767 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
768 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
769 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
770 }
66860240
VT		 771
772 if (AR_SREV_9300_20_OR_LATER(ah)) {
773 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
774 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
775 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
776 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
777 }
f078f209
LR		 778}
779
0005baf4 780static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
f078f209 781{
0005baf4
FF		 782 u32 val = ath9k_hw_mac_to_clks(ah, us);
783 val = min(val, (u32) 0xFFFF);
784 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
f078f209
LR		 785}
786
0005baf4 787static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
f078f209 788{
0005baf4
FF		 789 u32 val = ath9k_hw_mac_to_clks(ah, us);
790 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
791 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
792}
793
794static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
795{
796 u32 val = ath9k_hw_mac_to_clks(ah, us);
797 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
798 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
f078f209 799}
f1dc5600 800
cbe61d8a 801static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
f078f209 802{
f078f209 803 if (tu > 0xFFFF) {
c46917bb
LR		 804 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
805 "bad global tx timeout %u\n", tu);
2660b81a 806 ah->globaltxtimeout = (u32) -1;
f078f209
LR		 807 return false;
808 } else {
809 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
2660b81a 810 ah->globaltxtimeout = tu;
f078f209
LR		 811 return true;
812 }
813}
814
0005baf4 815void ath9k_hw_init_global_settings(struct ath_hw *ah)
f078f209 816{
0005baf4
FF		 817 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
818 int acktimeout;
e239d859 819 int slottime;
0005baf4
FF		 820 int sifstime;
821
c46917bb
LR		 822 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
823 ah->misc_mode);
f078f209 824
2660b81a 825 if (ah->misc_mode != 0)
f1dc5600 826 REG_WRITE(ah, AR_PCU_MISC,
2660b81a 827 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
0005baf4
FF		 828
829 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
830 sifstime = 16;
831 else
832 sifstime = 10;
833
e239d859
FF		 834 /* As defined by IEEE 802.11-2007 17.3.8.6 */
835 slottime = ah->slottime + 3 * ah->coverage_class;
836 acktimeout = slottime + sifstime;
42c4568a
FF		 837
838 /*
839 * Workaround for early ACK timeouts, add an offset to match the
840 * initval's 64us ack timeout value.
841 * This was initially only meant to work around an issue with delayed
842 * BA frames in some implementations, but it has been found to fix ACK
843 * timeout issues in other cases as well.
844 */
845 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
846 acktimeout += 64 - sifstime - ah->slottime;
847
e239d859 848 ath9k_hw_setslottime(ah, slottime);
0005baf4
FF		 849 ath9k_hw_set_ack_timeout(ah, acktimeout);
850 ath9k_hw_set_cts_timeout(ah, acktimeout);
2660b81a
S		 851 if (ah->globaltxtimeout != (u32) -1)
852 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
f1dc5600 853}
0005baf4 854EXPORT_SYMBOL(ath9k_hw_init_global_settings);
f1dc5600 855
285f2dda 856void ath9k_hw_deinit(struct ath_hw *ah)
f1dc5600 857{
211f5859
LR		 858 struct ath_common *common = ath9k_hw_common(ah);
859
736b3a27 860 if (common->state < ATH_HW_INITIALIZED)
211f5859
LR		 861 goto free_hw;
862
f1dc5600 863 if (!AR_SREV_9100(ah))
e70c0cfd 864 ath9k_hw_ani_disable(ah);
f1dc5600 865
9ecdef4b 866 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
211f5859
LR		 867
868free_hw:
8fe65368 869 ath9k_hw_rf_free_ext_banks(ah);
f1dc5600 870}
285f2dda 871EXPORT_SYMBOL(ath9k_hw_deinit);
f1dc5600 872
f1dc5600
S		 873/*******/
874/* INI */
875/*******/
876
8fe65368 877u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
3a702e49
BC		 878{
879 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
880
881 if (IS_CHAN_B(chan))
882 ctl |= CTL_11B;
883 else if (IS_CHAN_G(chan))
884 ctl |= CTL_11G;
885 else
886 ctl |= CTL_11A;
887
888 return ctl;
889}
890
f1dc5600
S		 891/****************************************/
892/* Reset and Channel Switching Routines */
893/****************************************/
894
cbe61d8a 895static inline void ath9k_hw_set_dma(struct ath_hw *ah)
f1dc5600
S		 896{
897 u32 regval;
898
d7e7d229
LR		 899 /*
900 * set AHB_MODE not to do cacheline prefetches
901 */
f1dc5600
S		 902 regval = REG_READ(ah, AR_AHB_MODE);
903 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
904
d7e7d229
LR		 905 /*
906 * let mac dma reads be in 128 byte chunks
907 */
f1dc5600
S		 908 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
909 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
910
d7e7d229
LR		 911 /*
912 * Restore TX Trigger Level to its pre-reset value.
913 * The initial value depends on whether aggregation is enabled, and is
914 * adjusted whenever underruns are detected.
915 */
2660b81a 916 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
f1dc5600 917
d7e7d229
LR		 918 /*
919 * let mac dma writes be in 128 byte chunks
920 */
f1dc5600
S		 921 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
922 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
923
d7e7d229
LR		 924 /*
925 * Setup receive FIFO threshold to hold off TX activities
926 */
f1dc5600
S		 927 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
928
d7e7d229
LR		 929 /*
930 * reduce the number of usable entries in PCU TXBUF to avoid
931 * wrap around issues.
932 */
f1dc5600 933 if (AR_SREV_9285(ah)) {
d7e7d229
LR		 934 /* For AR9285 the number of Fifos are reduced to half.
935 * So set the usable tx buf size also to half to
936 * avoid data/delimiter underruns
937 */
f1dc5600
S		 938 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
939 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
d7e7d229 940 } else if (!AR_SREV_9271(ah)) {
f1dc5600
S		 941 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
942 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
943 }
944}
945
cbe61d8a 946static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
f1dc5600
S		 947{
948 u32 val;
949
950 val = REG_READ(ah, AR_STA_ID1);
951 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
952 switch (opmode) {
d97809db 953 case NL80211_IFTYPE_AP:
f1dc5600
S		 954 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
955 | AR_STA_ID1_KSRCH_MODE);
956 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 957 break;
d97809db 958 case NL80211_IFTYPE_ADHOC:
9cb5412b 959 case NL80211_IFTYPE_MESH_POINT:
f1dc5600
S		 960 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
961 | AR_STA_ID1_KSRCH_MODE);
962 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
f078f209 963 break;
d97809db
CM		 964 case NL80211_IFTYPE_STATION:
965 case NL80211_IFTYPE_MONITOR:
f1dc5600 966 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
f078f209 967 break;
f1dc5600
S		 968 }
969}
970
8fe65368
LR		 971void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
972 u32 *coef_mantissa, u32 *coef_exponent)
f1dc5600
S		 973{
974 u32 coef_exp, coef_man;
975
976 for (coef_exp = 31; coef_exp > 0; coef_exp--)
977 if ((coef_scaled >> coef_exp) & 0x1)
978 break;
979
980 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
981
982 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
983
984 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
985 *coef_exponent = coef_exp - 16;
986}
987
cbe61d8a 988static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
f1dc5600
S		 989{
990 u32 rst_flags;
991 u32 tmpReg;
992
70768496
S		 993 if (AR_SREV_9100(ah)) {
994 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
995 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
996 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
997 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
998 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
999 }
1000
f1dc5600
S		 1001 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1002 AR_RTC_FORCE_WAKE_ON_INT);
1003
1004 if (AR_SREV_9100(ah)) {
1005 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1006 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1007 } else {
1008 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1009 if (tmpReg &
1010 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1011 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
42d5bc3f 1012 u32 val;
f1dc5600 1013 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
42d5bc3f
LR		 1014
1015 val = AR_RC_HOSTIF;
1016 if (!AR_SREV_9300_20_OR_LATER(ah))
1017 val |= AR_RC_AHB;
1018 REG_WRITE(ah, AR_RC, val);
1019
1020 } else if (!AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1021 REG_WRITE(ah, AR_RC, AR_RC_AHB);
f1dc5600
S		 1022
1023 rst_flags = AR_RTC_RC_MAC_WARM;
1024 if (type == ATH9K_RESET_COLD)
1025 rst_flags |= AR_RTC_RC_MAC_COLD;
1026 }
1027
d03a66c1 1028 REG_WRITE(ah, AR_RTC_RC, rst_flags);
f1dc5600
S		 1029 udelay(50);
1030
d03a66c1 1031 REG_WRITE(ah, AR_RTC_RC, 0);
0caa7b14 1032 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1033 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1034 "RTC stuck in MAC reset\n");
f1dc5600
S		 1035 return false;
1036 }
1037
1038 if (!AR_SREV_9100(ah))
1039 REG_WRITE(ah, AR_RC, 0);
1040
f1dc5600
S		 1041 if (AR_SREV_9100(ah))
1042 udelay(50);
1043
1044 return true;
1045}
1046
cbe61d8a 1047static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
f1dc5600
S		 1048{
1049 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1050 AR_RTC_FORCE_WAKE_ON_INT);
1051
42d5bc3f 1052 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1053 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1054
d03a66c1 1055 REG_WRITE(ah, AR_RTC_RESET, 0);
1c29ce67 1056
84e2169b
SB		 1057 if (!AR_SREV_9300_20_OR_LATER(ah))
1058 udelay(2);
1059
1060 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1c29ce67
VT		 1061 REG_WRITE(ah, AR_RC, 0);
1062
d03a66c1 1063 REG_WRITE(ah, AR_RTC_RESET, 1);
f1dc5600
S		 1064
1065 if (!ath9k_hw_wait(ah,
1066 AR_RTC_STATUS,
1067 AR_RTC_STATUS_M,
0caa7b14
S		 1068 AR_RTC_STATUS_ON,
1069 AH_WAIT_TIMEOUT)) {
c46917bb
LR		 1070 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1071 "RTC not waking up\n");
f1dc5600 1072 return false;
f078f209
LR		 1073 }
1074
f1dc5600
S		 1075 ath9k_hw_read_revisions(ah);
1076
1077 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1078}
1079
cbe61d8a 1080static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
f1dc5600
S		 1081{
1082 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1083 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1084
1085 switch (type) {
1086 case ATH9K_RESET_POWER_ON:
1087 return ath9k_hw_set_reset_power_on(ah);
f1dc5600
S		 1088 case ATH9K_RESET_WARM:
1089 case ATH9K_RESET_COLD:
1090 return ath9k_hw_set_reset(ah, type);
f1dc5600
S		 1091 default:
1092 return false;
1093 }
f078f209
LR		 1094}
1095
cbe61d8a 1096static bool ath9k_hw_chip_reset(struct ath_hw *ah,
f1dc5600 1097 struct ath9k_channel *chan)
f078f209 1098{
42abfbee 1099 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
8bd1d07f
SB		 1100 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1101 return false;
1102 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
f1dc5600 1103 return false;
f078f209 1104
9ecdef4b 1105 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 1106 return false;
f078f209 1107
2660b81a 1108 ah->chip_fullsleep = false;
f1dc5600 1109 ath9k_hw_init_pll(ah, chan);
f1dc5600 1110 ath9k_hw_set_rfmode(ah, chan);
f078f209 1111
f1dc5600 1112 return true;
f078f209
LR		 1113}
1114
cbe61d8a 1115static bool ath9k_hw_channel_change(struct ath_hw *ah,
25c56eec 1116 struct ath9k_channel *chan)
f078f209 1117{
608b88cb 1118 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1119 struct ath_common *common = ath9k_hw_common(ah);
5f8e077c 1120 struct ieee80211_channel *channel = chan->chan;
8fe65368 1121 u32 qnum;
0a3b7bac 1122 int r;
f078f209
LR		 1123
1124 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1125 if (ath9k_hw_numtxpending(ah, qnum)) {
c46917bb
LR		 1126 ath_print(common, ATH_DBG_QUEUE,
1127 "Transmit frames pending on "
1128 "queue %d\n", qnum);
f078f209
LR		 1129 return false;
1130 }
1131 }
1132
8fe65368 1133 if (!ath9k_hw_rfbus_req(ah)) {
c46917bb
LR		 1134 ath_print(common, ATH_DBG_FATAL,
1135 "Could not kill baseband RX\n");
f078f209
LR		 1136 return false;
1137 }
1138
8fe65368 1139 ath9k_hw_set_channel_regs(ah, chan);
f078f209 1140
8fe65368 1141 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1142 if (r) {
1143 ath_print(common, ATH_DBG_FATAL,
1144 "Failed to set channel\n");
1145 return false;
f078f209
LR		 1146 }
1147
8fbff4b8 1148 ah->eep_ops->set_txpower(ah, chan,
608b88cb 1149 ath9k_regd_get_ctl(regulatory, chan),
f74df6fb
S		 1150 channel->max_antenna_gain * 2,
1151 channel->max_power * 2,
1152 min((u32) MAX_RATE_POWER,
608b88cb 1153 (u32) regulatory->power_limit));
f078f209 1154
8fe65368 1155 ath9k_hw_rfbus_done(ah);
f078f209 1156
f1dc5600
S		 1157 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1158 ath9k_hw_set_delta_slope(ah, chan);
1159
8fe65368 1160 ath9k_hw_spur_mitigate_freq(ah, chan);
f1dc5600
S		 1161
1162 if (!chan->oneTimeCalsDone)
1163 chan->oneTimeCalsDone = true;
1164
1165 return true;
1166}
1167
cbe61d8a 1168int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
ae8d2858 1169 bool bChannelChange)
f078f209 1170{
1510718d 1171 struct ath_common *common = ath9k_hw_common(ah);
f078f209 1172 u32 saveLedState;
2660b81a 1173 struct ath9k_channel *curchan = ah->curchan;
f078f209
LR		 1174 u32 saveDefAntenna;
1175 u32 macStaId1;
46fe782c 1176 u64 tsf = 0;
8fe65368 1177 int i, r;
f078f209 1178
43c27613
LR		 1179 ah->txchainmask = common->tx_chainmask;
1180 ah->rxchainmask = common->rx_chainmask;
f078f209 1181
9ecdef4b 1182 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
ae8d2858 1183 return -EIO;
f078f209 1184
9ebef799 1185 if (curchan && !ah->chip_fullsleep)
f078f209
LR		 1186 ath9k_hw_getnf(ah, curchan);
1187
1188 if (bChannelChange &&
2660b81a
S		 1189 (ah->chip_fullsleep != true) &&
1190 (ah->curchan != NULL) &&
1191 (chan->channel != ah->curchan->channel) &&
f078f209 1192 ((chan->channelFlags & CHANNEL_ALL) ==
2660b81a 1193 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
0a475cc6
VT		 1194 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1195 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
f078f209 1196
25c56eec 1197 if (ath9k_hw_channel_change(ah, chan)) {
2660b81a 1198 ath9k_hw_loadnf(ah, ah->curchan);
f078f209 1199 ath9k_hw_start_nfcal(ah);
ae8d2858 1200 return 0;
f078f209
LR		 1201 }
1202 }
1203
1204 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1205 if (saveDefAntenna == 0)
1206 saveDefAntenna = 1;
1207
1208 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1209
46fe782c
S		 1210 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1211 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1212 tsf = ath9k_hw_gettsf64(ah);
1213
f078f209
LR		 1214 saveLedState = REG_READ(ah, AR_CFG_LED) &
1215 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1216 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1217
1218 ath9k_hw_mark_phy_inactive(ah);
1219
05020d23 1220 /* Only required on the first reset */
d7e7d229
LR		 1221 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1222 REG_WRITE(ah,
1223 AR9271_RESET_POWER_DOWN_CONTROL,
1224 AR9271_RADIO_RF_RST);
1225 udelay(50);
1226 }
1227
f078f209 1228 if (!ath9k_hw_chip_reset(ah, chan)) {
c46917bb 1229 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
ae8d2858 1230 return -EINVAL;
f078f209
LR		 1231 }
1232
05020d23 1233 /* Only required on the first reset */
d7e7d229
LR		 1234 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1235 ah->htc_reset_init = false;
1236 REG_WRITE(ah,
1237 AR9271_RESET_POWER_DOWN_CONTROL,
1238 AR9271_GATE_MAC_CTL);
1239 udelay(50);
1240 }
1241
46fe782c
S		 1242 /* Restore TSF */
1243 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1244 ath9k_hw_settsf64(ah, tsf);
1245
369391db
VT		 1246 if (AR_SREV_9280_10_OR_LATER(ah))
1247 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
f078f209 1248
25c56eec 1249 r = ath9k_hw_process_ini(ah, chan);
ae8d2858
LR		 1250 if (r)
1251 return r;
f078f209 1252
0ced0e17
JM		 1253 /* Setup MFP options for CCMP */
1254 if (AR_SREV_9280_20_OR_LATER(ah)) {
1255 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1256 * frames when constructing CCMP AAD. */
1257 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1258 0xc7ff);
1259 ah->sw_mgmt_crypto = false;
1260 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1261 /* Disable hardware crypto for management frames */
1262 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1263 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1264 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1265 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1266 ah->sw_mgmt_crypto = true;
1267 } else
1268 ah->sw_mgmt_crypto = true;
1269
f078f209
LR		 1270 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1271 ath9k_hw_set_delta_slope(ah, chan);
1272
8fe65368 1273 ath9k_hw_spur_mitigate_freq(ah, chan);
d6509151 1274 ah->eep_ops->set_board_values(ah, chan);
a7765828 1275
1510718d
LR		 1276 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1277 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
f078f209
LR		 1278 | macStaId1
1279 | AR_STA_ID1_RTS_USE_DEF
2660b81a 1280 | (ah->config.
60b67f51 1281 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2660b81a
S		 1282 | ah->sta_id1_defaults);
1283 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 1284
13b81559 1285 ath_hw_setbssidmask(common);
f078f209
LR		 1286
1287 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1288
3453ad88 1289 ath9k_hw_write_associd(ah);
f078f209
LR		 1290
1291 REG_WRITE(ah, AR_ISR, ~0);
1292
1293 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1294
8fe65368 1295 r = ath9k_hw_rf_set_freq(ah, chan);
0a3b7bac
LR		 1296 if (r)
1297 return r;
f078f209
LR		 1298
1299 for (i = 0; i < AR_NUM_DCU; i++)
1300 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1301
2660b81a
S		 1302 ah->intr_txqs = 0;
1303 for (i = 0; i < ah->caps.total_queues; i++)
f078f209
LR		 1304 ath9k_hw_resettxqueue(ah, i);
1305
2660b81a 1306 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
f078f209
LR		 1307 ath9k_hw_init_qos(ah);
1308
2660b81a 1309 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
500c064d 1310 ath9k_enable_rfkill(ah);
3b319aae 1311
0005baf4 1312 ath9k_hw_init_global_settings(ah);
f078f209 1313
326bebbc 1314 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1315 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
1316 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
1317 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
1318 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
1319 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
1320 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
1321
1322 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
1323 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
1324
1325 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1326 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1327 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1328 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1329 }
326bebbc 1330 if (AR_SREV_9287_12_OR_LATER(ah)) {
ac88b6ec
VN		 1331 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1332 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1333 }
1334
f078f209
LR		 1335 REG_WRITE(ah, AR_STA_ID1,
1336 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1337
1338 ath9k_hw_set_dma(ah);
1339
1340 REG_WRITE(ah, AR_OBS, 8);
1341
0ce024cb 1342 if (ah->config.rx_intr_mitigation) {
f078f209
LR		 1343 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1344 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1345 }
1346
1347 ath9k_hw_init_bb(ah, chan);
1348
ae8d2858 1349 if (!ath9k_hw_init_cal(ah, chan))
6badaaf7 1350 return -EIO;
f078f209 1351
8fe65368 1352 ath9k_hw_restore_chainmask(ah);
f078f209
LR		 1353 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1354
d7e7d229
LR		 1355 /*
1356 * For big endian systems turn on swapping for descriptors
1357 */
f078f209
LR		 1358 if (AR_SREV_9100(ah)) {
1359 u32 mask;
1360 mask = REG_READ(ah, AR_CFG);
1361 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
c46917bb 1362 ath_print(common, ATH_DBG_RESET,
04bd4638 1363 "CFG Byte Swap Set 0x%x\n", mask);
f078f209
LR		 1364 } else {
1365 mask =
1366 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1367 REG_WRITE(ah, AR_CFG, mask);
c46917bb 1368 ath_print(common, ATH_DBG_RESET,
04bd4638 1369 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
f078f209
LR		 1370 }
1371 } else {
d7e7d229
LR		 1372 /* Configure AR9271 target WLAN */
1373 if (AR_SREV_9271(ah))
1374 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
f078f209 1375#ifdef __BIG_ENDIAN
d7e7d229
LR		 1376 else
1377 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
f078f209
LR		 1378#endif
1379 }
1380
766ec4a9 1381 if (ah->btcoex_hw.enabled)
42cc41ed
VT		 1382 ath9k_hw_btcoex_enable(ah);
1383
ae8d2858 1384 return 0;
f078f209 1385}
7322fd19 1386EXPORT_SYMBOL(ath9k_hw_reset);
f078f209 1387
f1dc5600
S		 1388/************************/
1389/* Key Cache Management */
1390/************************/
f078f209 1391
cbe61d8a 1392bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
f078f209 1393{
f1dc5600 1394 u32 keyType;
f078f209 1395
2660b81a 1396 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1397 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1398 "keychache entry %u out of range\n", entry);
f078f209
LR		 1399 return false;
1400 }
1401
f1dc5600 1402 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
f078f209 1403
f1dc5600
S		 1404 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1405 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1406 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1407 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1408 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1409 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1410 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1411 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
f078f209 1412
f1dc5600
S		 1413 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1414 u16 micentry = entry + 64;
f078f209 1415
f1dc5600
S		 1416 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1417 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1418 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1419 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
f078f209 1420
f078f209
LR		 1421 }
1422
f078f209
LR		 1423 return true;
1424}
7322fd19 1425EXPORT_SYMBOL(ath9k_hw_keyreset);
f078f209 1426
cbe61d8a 1427bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
f078f209 1428{
f1dc5600 1429 u32 macHi, macLo;
f078f209 1430
2660b81a 1431 if (entry >= ah->caps.keycache_size) {
c46917bb
LR		 1432 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1433 "keychache entry %u out of range\n", entry);
f1dc5600 1434 return false;
f078f209
LR		 1435 }
1436
f1dc5600
S		 1437 if (mac != NULL) {
1438 macHi = (mac[5] << 8) | mac[4];
1439 macLo = (mac[3] << 24) |
1440 (mac[2] << 16) |
1441 (mac[1] << 8) |
1442 mac[0];
1443 macLo >>= 1;
1444 macLo |= (macHi & 1) << 31;
1445 macHi >>= 1;
f078f209 1446 } else {
f1dc5600 1447 macLo = macHi = 0;
f078f209 1448 }
f1dc5600
S		 1449 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1450 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
f078f209 1451
f1dc5600 1452 return true;
f078f209 1453}
7322fd19 1454EXPORT_SYMBOL(ath9k_hw_keysetmac);
f078f209 1455
cbe61d8a 1456bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
f1dc5600 1457 const struct ath9k_keyval *k,
e0caf9ea 1458 const u8 *mac)
f078f209 1459{
2660b81a 1460 const struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1461 struct ath_common *common = ath9k_hw_common(ah);
f1dc5600
S		 1462 u32 key0, key1, key2, key3, key4;
1463 u32 keyType;
f078f209 1464
f1dc5600 1465 if (entry >= pCap->keycache_size) {
c46917bb
LR		 1466 ath_print(common, ATH_DBG_FATAL,
1467 "keycache entry %u out of range\n", entry);
f1dc5600 1468 return false;
f078f209
LR		 1469 }
1470
f1dc5600
S		 1471 switch (k->kv_type) {
1472 case ATH9K_CIPHER_AES_OCB:
1473 keyType = AR_KEYTABLE_TYPE_AES;
1474 break;
1475 case ATH9K_CIPHER_AES_CCM:
1476 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
c46917bb
LR		 1477 ath_print(common, ATH_DBG_ANY,
1478 "AES-CCM not supported by mac rev 0x%x\n",
1479 ah->hw_version.macRev);
f1dc5600
S		 1480 return false;
1481 }
1482 keyType = AR_KEYTABLE_TYPE_CCM;
1483 break;
1484 case ATH9K_CIPHER_TKIP:
1485 keyType = AR_KEYTABLE_TYPE_TKIP;
1486 if (ATH9K_IS_MIC_ENABLED(ah)
1487 && entry + 64 >= pCap->keycache_size) {
c46917bb
LR		 1488 ath_print(common, ATH_DBG_ANY,
1489 "entry %u inappropriate for TKIP\n", entry);
f1dc5600
S		 1490 return false;
1491 }
1492 break;
1493 case ATH9K_CIPHER_WEP:
e31a16d6 1494 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
c46917bb
LR		 1495 ath_print(common, ATH_DBG_ANY,
1496 "WEP key length %u too small\n", k->kv_len);
f1dc5600
S		 1497 return false;
1498 }
e31a16d6 1499 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
f1dc5600 1500 keyType = AR_KEYTABLE_TYPE_40;
e31a16d6 1501 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600
S		 1502 keyType = AR_KEYTABLE_TYPE_104;
1503 else
1504 keyType = AR_KEYTABLE_TYPE_128;
1505 break;
1506 case ATH9K_CIPHER_CLR:
1507 keyType = AR_KEYTABLE_TYPE_CLR;
1508 break;
1509 default:
c46917bb
LR		 1510 ath_print(common, ATH_DBG_FATAL,
1511 "cipher %u not supported\n", k->kv_type);
f1dc5600 1512 return false;
f078f209
LR		 1513 }
1514
e0caf9ea
JM		 1515 key0 = get_unaligned_le32(k->kv_val + 0);
1516 key1 = get_unaligned_le16(k->kv_val + 4);
1517 key2 = get_unaligned_le32(k->kv_val + 6);
1518 key3 = get_unaligned_le16(k->kv_val + 10);
1519 key4 = get_unaligned_le32(k->kv_val + 12);
e31a16d6 1520 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
f1dc5600 1521 key4 &= 0xff;
f078f209 1522
672903b3
JM		 1523 /*
1524 * Note: Key cache registers access special memory area that requires
1525 * two 32-bit writes to actually update the values in the internal
1526 * memory. Consequently, the exact order and pairs used here must be
1527 * maintained.
1528 */
1529
f1dc5600
S		 1530 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1531 u16 micentry = entry + 64;
f078f209 1532
672903b3
JM		 1533 /*
1534 * Write inverted key[47:0] first to avoid Michael MIC errors
1535 * on frames that could be sent or received at the same time.
1536 * The correct key will be written in the end once everything
1537 * else is ready.
1538 */
f1dc5600
S		 1539 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1540 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
672903b3
JM		 1541
1542 /* Write key[95:48] */
f1dc5600
S		 1543 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1544 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1545
1546 /* Write key[127:96] and key type */
f1dc5600
S		 1547 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1548 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
672903b3
JM		 1549
1550 /* Write MAC address for the entry */
f1dc5600 1551 (void) ath9k_hw_keysetmac(ah, entry, mac);
f078f209 1552
2660b81a 1553 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
672903b3
JM		 1554 /*
1555 * TKIP uses two key cache entries:
1556 * Michael MIC TX/RX keys in the same key cache entry
1557 * (idx = main index + 64):
1558 * key0 [31:0] = RX key [31:0]
1559 * key1 [15:0] = TX key [31:16]
1560 * key1 [31:16] = reserved
1561 * key2 [31:0] = RX key [63:32]
1562 * key3 [15:0] = TX key [15:0]
1563 * key3 [31:16] = reserved
1564 * key4 [31:0] = TX key [63:32]
1565 */
f1dc5600 1566 u32 mic0, mic1, mic2, mic3, mic4;
f078f209 1567
f1dc5600
S		 1568 mic0 = get_unaligned_le32(k->kv_mic + 0);
1569 mic2 = get_unaligned_le32(k->kv_mic + 4);
1570 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1571 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1572 mic4 = get_unaligned_le32(k->kv_txmic + 4);
672903b3
JM		 1573
1574 /* Write RX[31:0] and TX[31:16] */
f1dc5600
S		 1575 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1576 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
672903b3
JM		 1577
1578 /* Write RX[63:32] and TX[15:0] */
f1dc5600
S		 1579 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1580 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
672903b3
JM		 1581
1582 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1583 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1584 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1585 AR_KEYTABLE_TYPE_CLR);
f078f209 1586
f1dc5600 1587 } else {
672903b3
JM		 1588 /*
1589 * TKIP uses four key cache entries (two for group
1590 * keys):
1591 * Michael MIC TX/RX keys are in different key cache
1592 * entries (idx = main index + 64 for TX and
1593 * main index + 32 + 96 for RX):
1594 * key0 [31:0] = TX/RX MIC key [31:0]
1595 * key1 [31:0] = reserved
1596 * key2 [31:0] = TX/RX MIC key [63:32]
1597 * key3 [31:0] = reserved
1598 * key4 [31:0] = reserved
1599 *
1600 * Upper layer code will call this function separately
1601 * for TX and RX keys when these registers offsets are
1602 * used.
1603 */
f1dc5600 1604 u32 mic0, mic2;
f078f209 1605
f1dc5600
S		 1606 mic0 = get_unaligned_le32(k->kv_mic + 0);
1607 mic2 = get_unaligned_le32(k->kv_mic + 4);
672903b3
JM		 1608
1609 /* Write MIC key[31:0] */
f1dc5600
S		 1610 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1611 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
672903b3
JM		 1612
1613 /* Write MIC key[63:32] */
f1dc5600
S		 1614 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1615 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
672903b3
JM		 1616
1617 /* Write TX[63:32] and keyType(reserved) */
f1dc5600
S		 1618 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1619 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1620 AR_KEYTABLE_TYPE_CLR);
1621 }
672903b3
JM		 1622
1623 /* MAC address registers are reserved for the MIC entry */
f1dc5600
S		 1624 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1625 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
672903b3
JM		 1626
1627 /*
1628 * Write the correct (un-inverted) key[47:0] last to enable
1629 * TKIP now that all other registers are set with correct
1630 * values.
1631 */
f1dc5600
S		 1632 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1633 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1634 } else {
672903b3 1635 /* Write key[47:0] */
f1dc5600
S		 1636 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1637 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
672903b3
JM		 1638
1639 /* Write key[95:48] */
f1dc5600
S		 1640 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1641 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
672903b3
JM		 1642
1643 /* Write key[127:96] and key type */
f1dc5600
S		 1644 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1645 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
f078f209 1646
672903b3 1647 /* Write MAC address for the entry */
f1dc5600
S		 1648 (void) ath9k_hw_keysetmac(ah, entry, mac);
1649 }
f078f209 1650
f078f209
LR		 1651 return true;
1652}
7322fd19 1653EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
f078f209 1654
cbe61d8a 1655bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
f078f209 1656{
2660b81a 1657 if (entry < ah->caps.keycache_size) {
f1dc5600
S		 1658 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1659 if (val & AR_KEYTABLE_VALID)
1660 return true;
1661 }
1662 return false;
f078f209 1663}
7322fd19 1664EXPORT_SYMBOL(ath9k_hw_keyisvalid);
f078f209 1665
f1dc5600
S		 1666/******************************/
1667/* Power Management (Chipset) */
1668/******************************/
1669
42d5bc3f
LR		 1670/*
1671 * Notify Power Mgt is disabled in self-generated frames.
1672 * If requested, force chip to sleep.
1673 */
cbe61d8a 1674static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
f078f209 1675{
f1dc5600
S		 1676 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1677 if (setChip) {
42d5bc3f
LR		 1678 /*
1679 * Clear the RTC force wake bit to allow the
1680 * mac to go to sleep.
1681 */
f1dc5600
S		 1682 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1683 AR_RTC_FORCE_WAKE_EN);
42d5bc3f 1684 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
f1dc5600 1685 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
f078f209 1686
42d5bc3f 1687 /* Shutdown chip. Active low */
14b3af38 1688 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
4921be80
S		 1689 REG_CLR_BIT(ah, (AR_RTC_RESET),
1690 AR_RTC_RESET_EN);
f1dc5600 1691 }
f078f209
LR		 1692}
1693
bbd79af5
LR		 1694/*
1695 * Notify Power Management is enabled in self-generating
1696 * frames. If request, set power mode of chip to
1697 * auto/normal. Duration in units of 128us (1/8 TU).
1698 */
cbe61d8a 1699static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
f078f209 1700{
f1dc5600
S		 1701 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1702 if (setChip) {
2660b81a 1703 struct ath9k_hw_capabilities *pCap = &ah->caps;
f078f209 1704
f1dc5600 1705 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
bbd79af5 1706 /* Set WakeOnInterrupt bit; clear ForceWake bit */
f1dc5600
S		 1707 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1708 AR_RTC_FORCE_WAKE_ON_INT);
1709 } else {
bbd79af5
LR		 1710 /*
1711 * Clear the RTC force wake bit to allow the
1712 * mac to go to sleep.
1713 */
f1dc5600
S		 1714 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1715 AR_RTC_FORCE_WAKE_EN);
f078f209 1716 }
f078f209 1717 }
f078f209
LR		 1718}
1719
cbe61d8a 1720static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
f078f209 1721{
f1dc5600
S		 1722 u32 val;
1723 int i;
f078f209 1724
f1dc5600
S		 1725 if (setChip) {
1726 if ((REG_READ(ah, AR_RTC_STATUS) &
1727 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1728 if (ath9k_hw_set_reset_reg(ah,
1729 ATH9K_RESET_POWER_ON) != true) {
1730 return false;
1731 }
e041228f
LR		 1732 if (!AR_SREV_9300_20_OR_LATER(ah))
1733 ath9k_hw_init_pll(ah, NULL);
f1dc5600
S		 1734 }
1735 if (AR_SREV_9100(ah))
1736 REG_SET_BIT(ah, AR_RTC_RESET,
1737 AR_RTC_RESET_EN);
f078f209 1738
f1dc5600
S		 1739 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1740 AR_RTC_FORCE_WAKE_EN);
1741 udelay(50);
f078f209 1742
f1dc5600
S		 1743 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1744 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1745 if (val == AR_RTC_STATUS_ON)
1746 break;
1747 udelay(50);
1748 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1749 AR_RTC_FORCE_WAKE_EN);
f078f209 1750 }
f1dc5600 1751 if (i == 0) {
c46917bb
LR		 1752 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1753 "Failed to wakeup in %uus\n",
1754 POWER_UP_TIME / 20);
f1dc5600 1755 return false;
f078f209 1756 }
f078f209
LR		 1757 }
1758
f1dc5600 1759 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
f078f209 1760
f1dc5600 1761 return true;
f078f209
LR		 1762}
1763
9ecdef4b 1764bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
f078f209 1765{
c46917bb 1766 struct ath_common *common = ath9k_hw_common(ah);
cbe61d8a 1767 int status = true, setChip = true;
f1dc5600
S		 1768 static const char *modes[] = {
1769 "AWAKE",
1770 "FULL-SLEEP",
1771 "NETWORK SLEEP",
1772 "UNDEFINED"
1773 };
f1dc5600 1774
cbdec975
GJ		 1775 if (ah->power_mode == mode)
1776 return status;
1777
c46917bb
LR		 1778 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1779 modes[ah->power_mode], modes[mode]);
f1dc5600
S		 1780
1781 switch (mode) {
1782 case ATH9K_PM_AWAKE:
1783 status = ath9k_hw_set_power_awake(ah, setChip);
1784 break;
1785 case ATH9K_PM_FULL_SLEEP:
1786 ath9k_set_power_sleep(ah, setChip);
2660b81a 1787 ah->chip_fullsleep = true;
f1dc5600
S		 1788 break;
1789 case ATH9K_PM_NETWORK_SLEEP:
1790 ath9k_set_power_network_sleep(ah, setChip);
1791 break;
f078f209 1792 default:
c46917bb
LR		 1793 ath_print(common, ATH_DBG_FATAL,
1794 "Unknown power mode %u\n", mode);
f078f209
LR		 1795 return false;
1796 }
2660b81a 1797 ah->power_mode = mode;
f1dc5600
S		 1798
1799 return status;
f078f209 1800}
7322fd19 1801EXPORT_SYMBOL(ath9k_hw_setpower);
f078f209 1802
f1dc5600
S		 1803/*******************/
1804/* Beacon Handling */
1805/*******************/
1806
cbe61d8a 1807void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
f078f209 1808{
f078f209
LR		 1809 int flags = 0;
1810
2660b81a 1811 ah->beacon_interval = beacon_period;
f078f209 1812
2660b81a 1813 switch (ah->opmode) {
d97809db
CM		 1814 case NL80211_IFTYPE_STATION:
1815 case NL80211_IFTYPE_MONITOR:
f078f209
LR		 1816 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1817 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1818 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1819 flags |= AR_TBTT_TIMER_EN;
1820 break;
d97809db 1821 case NL80211_IFTYPE_ADHOC:
9cb5412b 1822 case NL80211_IFTYPE_MESH_POINT:
f078f209
LR		 1823 REG_SET_BIT(ah, AR_TXCFG,
1824 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1825 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1826 TU_TO_USEC(next_beacon +
2660b81a
S		 1827 (ah->atim_window ? ah->
1828 atim_window : 1)));
f078f209 1829 flags |= AR_NDP_TIMER_EN;
d97809db 1830 case NL80211_IFTYPE_AP:
f078f209
LR		 1831 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1832 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1833 TU_TO_USEC(next_beacon -
2660b81a 1834 ah->config.
60b67f51 1835 dma_beacon_response_time));
f078f209
LR		 1836 REG_WRITE(ah, AR_NEXT_SWBA,
1837 TU_TO_USEC(next_beacon -
2660b81a 1838 ah->config.
60b67f51 1839 sw_beacon_response_time));
f078f209
LR		 1840 flags |=
1841 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1842 break;
d97809db 1843 default:
c46917bb
LR		 1844 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1845 "%s: unsupported opmode: %d\n",
1846 __func__, ah->opmode);
d97809db
CM		 1847 return;
1848 break;
f078f209
LR		 1849 }
1850
1851 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1852 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1853 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1854 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1855
1856 beacon_period &= ~ATH9K_BEACON_ENA;
1857 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
f078f209
LR		 1858 ath9k_hw_reset_tsf(ah);
1859 }
1860
1861 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1862}
7322fd19 1863EXPORT_SYMBOL(ath9k_hw_beaconinit);
f078f209 1864
cbe61d8a 1865void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
f1dc5600 1866 const struct ath9k_beacon_state *bs)
f078f209
LR		 1867{
1868 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2660b81a 1869 struct ath9k_hw_capabilities *pCap = &ah->caps;
c46917bb 1870 struct ath_common *common = ath9k_hw_common(ah);
f078f209
LR		 1871
1872 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1873
1874 REG_WRITE(ah, AR_BEACON_PERIOD,
1875 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1876 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1877 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1878
1879 REG_RMW_FIELD(ah, AR_RSSI_THR,
1880 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1881
1882 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1883
1884 if (bs->bs_sleepduration > beaconintval)
1885 beaconintval = bs->bs_sleepduration;
1886
1887 dtimperiod = bs->bs_dtimperiod;
1888 if (bs->bs_sleepduration > dtimperiod)
1889 dtimperiod = bs->bs_sleepduration;
1890
1891 if (beaconintval == dtimperiod)
1892 nextTbtt = bs->bs_nextdtim;
1893 else
1894 nextTbtt = bs->bs_nexttbtt;
1895
c46917bb
LR		 1896 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1897 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1898 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1899 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
f078f209 1900
f1dc5600
S		 1901 REG_WRITE(ah, AR_NEXT_DTIM,
1902 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1903 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
f078f209 1904
f1dc5600
S		 1905 REG_WRITE(ah, AR_SLEEP1,
1906 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1907 | AR_SLEEP1_ASSUME_DTIM);
f078f209 1908
f1dc5600
S		 1909 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1910 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1911 else
1912 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
f078f209 1913
f1dc5600
S		 1914 REG_WRITE(ah, AR_SLEEP2,
1915 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
f078f209 1916
f1dc5600
S		 1917 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1918 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
f078f209 1919
f1dc5600
S		 1920 REG_SET_BIT(ah, AR_TIMER_MODE,
1921 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1922 AR_DTIM_TIMER_EN);
f078f209 1923
4af9cf4f
S		 1924 /* TSF Out of Range Threshold */
1925 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
f078f209 1926}
7322fd19 1927EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
f078f209 1928
f1dc5600
S		 1929/*******************/
1930/* HW Capabilities */
1931/*******************/
1932
a9a29ce6 1933int ath9k_hw_fill_cap_info(struct ath_hw *ah)
f078f209 1934{
2660b81a 1935 struct ath9k_hw_capabilities *pCap = &ah->caps;
608b88cb 1936 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
c46917bb 1937 struct ath_common *common = ath9k_hw_common(ah);
766ec4a9 1938 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
608b88cb 1939
f1dc5600 1940 u16 capField = 0, eeval;
f078f209 1941
f74df6fb 1942 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
608b88cb 1943 regulatory->current_rd = eeval;
f078f209 1944
f74df6fb 1945 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
fec0de11
S		 1946 if (AR_SREV_9285_10_OR_LATER(ah))
1947 eeval |= AR9285_RDEXT_DEFAULT;
608b88cb 1948 regulatory->current_rd_ext = eeval;
f078f209 1949
f74df6fb 1950 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
f1dc5600 1951
2660b81a 1952 if (ah->opmode != NL80211_IFTYPE_AP &&
d535a42a 1953 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
608b88cb
LR		 1954 if (regulatory->current_rd == 0x64 ||
1955 regulatory->current_rd == 0x65)
1956 regulatory->current_rd += 5;
1957 else if (regulatory->current_rd == 0x41)
1958 regulatory->current_rd = 0x43;
c46917bb
LR		 1959 ath_print(common, ATH_DBG_REGULATORY,
1960 "regdomain mapped to 0x%x\n", regulatory->current_rd);
f1dc5600 1961 }
f078f209 1962
f74df6fb 1963 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
a9a29ce6
GJ		 1964 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
1965 ath_print(common, ATH_DBG_FATAL,
1966 "no band has been marked as supported in EEPROM.\n");
1967 return -EINVAL;
1968 }
1969
f1dc5600 1970 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
f078f209 1971
f1dc5600
S		 1972 if (eeval & AR5416_OPFLAGS_11A) {
1973 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2660b81a 1974 if (ah->config.ht_enable) {
f1dc5600
S		 1975 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
1976 set_bit(ATH9K_MODE_11NA_HT20,
1977 pCap->wireless_modes);
1978 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
1979 set_bit(ATH9K_MODE_11NA_HT40PLUS,
1980 pCap->wireless_modes);
1981 set_bit(ATH9K_MODE_11NA_HT40MINUS,
1982 pCap->wireless_modes);
1983 }
f078f209 1984 }
f078f209
LR		 1985 }
1986
f1dc5600 1987 if (eeval & AR5416_OPFLAGS_11G) {
f1dc5600 1988 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2660b81a 1989 if (ah->config.ht_enable) {
f1dc5600
S		 1990 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
1991 set_bit(ATH9K_MODE_11NG_HT20,
1992 pCap->wireless_modes);
1993 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
1994 set_bit(ATH9K_MODE_11NG_HT40PLUS,
1995 pCap->wireless_modes);
1996 set_bit(ATH9K_MODE_11NG_HT40MINUS,
1997 pCap->wireless_modes);
1998 }
1999 }
f078f209 2000 }
f1dc5600 2001
f74df6fb 2002 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
d7e7d229
LR		 2003 /*
2004 * For AR9271 we will temporarilly uses the rx chainmax as read from
2005 * the EEPROM.
2006 */
8147f5de 2007 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
d7e7d229
LR		 2008 !(eeval & AR5416_OPFLAGS_11A) &&
2009 !(AR_SREV_9271(ah)))
2010 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
8147f5de
S		 2011 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2012 else
d7e7d229 2013 /* Use rx_chainmask from EEPROM. */
8147f5de 2014 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
f078f209 2015
d535a42a 2016 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2660b81a 2017 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
f078f209 2018
f1dc5600
S		 2019 pCap->low_2ghz_chan = 2312;
2020 pCap->high_2ghz_chan = 2732;
f078f209 2021
f1dc5600
S		 2022 pCap->low_5ghz_chan = 4920;
2023 pCap->high_5ghz_chan = 6100;
f078f209 2024
f1dc5600
S		 2025 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2026 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2027 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
f078f209 2028
f1dc5600
S		 2029 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2030 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2031 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
f078f209 2032
2660b81a 2033 if (ah->config.ht_enable)
f1dc5600
S		 2034 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2035 else
2036 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
f078f209 2037
f1dc5600
S		 2038 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2039 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2040 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2041 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
f078f209 2042
f1dc5600
S		 2043 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2044 pCap->total_queues =
2045 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2046 else
2047 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
f078f209 2048
f1dc5600
S		 2049 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2050 pCap->keycache_size =
2051 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2052 else
2053 pCap->keycache_size = AR_KEYTABLE_SIZE;
f078f209 2054
f1dc5600 2055 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
f4709fdf
LR		 2056
2057 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2058 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2059 else
2060 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
f078f209 2061
5b5fa355
S		 2062 if (AR_SREV_9271(ah))
2063 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2064 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2065 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2066 else if (AR_SREV_9280_10_OR_LATER(ah))
f1dc5600
S		 2067 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2068 else
2069 pCap->num_gpio_pins = AR_NUM_GPIO;
f078f209 2070
f1dc5600
S		 2071 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2072 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2073 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2074 } else {
2075 pCap->rts_aggr_limit = (8 * 1024);
f078f209
LR		 2076 }
2077
f1dc5600
S		 2078 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2079
e97275cb 2080#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2660b81a
S		 2081 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2082 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2083 ah->rfkill_gpio =
2084 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2085 ah->rfkill_polarity =
2086 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
f1dc5600
S		 2087
2088 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
f078f209 2089 }
f1dc5600 2090#endif
bde748a4
VN		 2091 if (AR_SREV_9271(ah))
2092 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2093 else
2094 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
f078f209 2095
e7594072 2096 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
f1dc5600
S		 2097 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2098 else
2099 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
f078f209 2100
608b88cb 2101 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
f1dc5600
S		 2102 pCap->reg_cap =
2103 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2104 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2105 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2106 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
f078f209 2107 } else {
f1dc5600
S		 2108 pCap->reg_cap =
2109 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2110 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
f078f209 2111 }
f078f209 2112
ebb90cfc
SB		 2113 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2114 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2115 AR_SREV_5416(ah))
2116 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
f1dc5600
S		 2117
2118 pCap->num_antcfg_5ghz =
f74df6fb 2119 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
f1dc5600 2120 pCap->num_antcfg_2ghz =
f74df6fb 2121 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
f078f209 2122
fe12946e 2123 if (AR_SREV_9280_10_OR_LATER(ah) &&
a36cfbca 2124 ath9k_hw_btcoex_supported(ah)) {
766ec4a9
LR		 2125 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2126 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
22f25d0d 2127
8c8f9ba7 2128 if (AR_SREV_9285(ah)) {
766ec4a9
LR		 2129 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2130 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
8c8f9ba7 2131 } else {
766ec4a9 2132 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
8c8f9ba7 2133 }
22f25d0d 2134 } else {
766ec4a9 2135 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
c97c92d9 2136 }
a9a29ce6 2137
ceb26445 2138 if (AR_SREV_9300_20_OR_LATER(ah)) {
1adf02ff 2139 pCap->hw_caps |= ATH9K_HW_CAP_EDMA;
ceb26445
VT		 2140 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2141 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2142 pCap->rx_status_len = sizeof(struct ar9003_rxs);
162c3be3
VT		 2143 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2144 } else {
2145 pCap->tx_desc_len = sizeof(struct ath_desc);
ceb26445 2146 }
1adf02ff 2147
a9a29ce6 2148 return 0;
f078f209
LR		 2149}
2150
cbe61d8a 2151bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2152 u32 capability, u32 *result)
f078f209 2153{
608b88cb 2154 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
f1dc5600
S		 2155 switch (type) {
2156 case ATH9K_CAP_CIPHER:
2157 switch (capability) {
2158 case ATH9K_CIPHER_AES_CCM:
2159 case ATH9K_CIPHER_AES_OCB:
2160 case ATH9K_CIPHER_TKIP:
2161 case ATH9K_CIPHER_WEP:
2162 case ATH9K_CIPHER_MIC:
2163 case ATH9K_CIPHER_CLR:
2164 return true;
2165 default:
2166 return false;
2167 }
2168 case ATH9K_CAP_TKIP_MIC:
2169 switch (capability) {
2170 case 0:
2171 return true;
2172 case 1:
2660b81a 2173 return (ah->sta_id1_defaults &
f1dc5600
S		 2174 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2175 false;
2176 }
2177 case ATH9K_CAP_TKIP_SPLIT:
2660b81a 2178 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
f1dc5600 2179 false : true;
f1dc5600
S		 2180 case ATH9K_CAP_MCAST_KEYSRCH:
2181 switch (capability) {
2182 case 0:
2183 return true;
2184 case 1:
2185 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2186 return false;
2187 } else {
2660b81a 2188 return (ah->sta_id1_defaults &
f1dc5600
S		 2189 AR_STA_ID1_MCAST_KSRCH) ? true :
2190 false;
2191 }
2192 }
2193 return false;
f1dc5600
S		 2194 case ATH9K_CAP_TXPOW:
2195 switch (capability) {
2196 case 0:
2197 return 0;
2198 case 1:
608b88cb 2199 *result = regulatory->power_limit;
f1dc5600
S		 2200 return 0;
2201 case 2:
608b88cb 2202 *result = regulatory->max_power_level;
f1dc5600
S		 2203 return 0;
2204 case 3:
608b88cb 2205 *result = regulatory->tp_scale;
f1dc5600
S		 2206 return 0;
2207 }
2208 return false;
8bd1d07f
SB		 2209 case ATH9K_CAP_DS:
2210 return (AR_SREV_9280_20_OR_LATER(ah) &&
2211 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2212 ? false : true;
f1dc5600
S		 2213 default:
2214 return false;
f078f209 2215 }
f078f209 2216}
7322fd19 2217EXPORT_SYMBOL(ath9k_hw_getcapability);
f078f209 2218
cbe61d8a 2219bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
f1dc5600 2220 u32 capability, u32 setting, int *status)
f078f209 2221{
f1dc5600
S		 2222 switch (type) {
2223 case ATH9K_CAP_TKIP_MIC:
2224 if (setting)
2660b81a 2225 ah->sta_id1_defaults |=
f1dc5600
S		 2226 AR_STA_ID1_CRPT_MIC_ENABLE;
2227 else
2660b81a 2228 ah->sta_id1_defaults &=
f1dc5600
S		 2229 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2230 return true;
f1dc5600
S		 2231 case ATH9K_CAP_MCAST_KEYSRCH:
2232 if (setting)
2660b81a 2233 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2234 else
2660b81a 2235 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
f1dc5600 2236 return true;
f1dc5600
S		 2237 default:
2238 return false;
f078f209
LR		 2239 }
2240}
7322fd19 2241EXPORT_SYMBOL(ath9k_hw_setcapability);
f078f209 2242
f1dc5600
S		 2243/****************************/
2244/* GPIO / RFKILL / Antennae */
2245/****************************/
f078f209 2246
cbe61d8a 2247static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
f1dc5600
S		 2248 u32 gpio, u32 type)
2249{
2250 int addr;
2251 u32 gpio_shift, tmp;
f078f209 2252
f1dc5600
S		 2253 if (gpio > 11)
2254 addr = AR_GPIO_OUTPUT_MUX3;
2255 else if (gpio > 5)
2256 addr = AR_GPIO_OUTPUT_MUX2;
2257 else
2258 addr = AR_GPIO_OUTPUT_MUX1;
f078f209 2259
f1dc5600 2260 gpio_shift = (gpio % 6) * 5;
f078f209 2261
f1dc5600
S		 2262 if (AR_SREV_9280_20_OR_LATER(ah)
2263 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2264 REG_RMW(ah, addr, (type << gpio_shift),
2265 (0x1f << gpio_shift));
f078f209 2266 } else {
f1dc5600
S		 2267 tmp = REG_READ(ah, addr);
2268 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2269 tmp &= ~(0x1f << gpio_shift);
2270 tmp |= (type << gpio_shift);
2271 REG_WRITE(ah, addr, tmp);
f078f209 2272 }
f078f209
LR		 2273}
2274
cbe61d8a 2275void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
f078f209 2276{
f1dc5600 2277 u32 gpio_shift;
f078f209 2278
9680e8a3 2279 BUG_ON(gpio >= ah->caps.num_gpio_pins);
f078f209 2280
f1dc5600 2281 gpio_shift = gpio << 1;
f078f209 2282
f1dc5600
S		 2283 REG_RMW(ah,
2284 AR_GPIO_OE_OUT,
2285 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2286 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2287}
7322fd19 2288EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
f078f209 2289
cbe61d8a 2290u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
f078f209 2291{
cb33c412
SB		 2292#define MS_REG_READ(x, y) \
2293 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2294
2660b81a 2295 if (gpio >= ah->caps.num_gpio_pins)
f1dc5600 2296 return 0xffffffff;
f078f209 2297
783dfca1
FF		 2298 if (AR_SREV_9300_20_OR_LATER(ah))
2299 return MS_REG_READ(AR9300, gpio) != 0;
2300 else if (AR_SREV_9271(ah))
5b5fa355
S		 2301 return MS_REG_READ(AR9271, gpio) != 0;
2302 else if (AR_SREV_9287_10_OR_LATER(ah))
ac88b6ec
VN		 2303 return MS_REG_READ(AR9287, gpio) != 0;
2304 else if (AR_SREV_9285_10_OR_LATER(ah))
cb33c412
SB		 2305 return MS_REG_READ(AR9285, gpio) != 0;
2306 else if (AR_SREV_9280_10_OR_LATER(ah))
2307 return MS_REG_READ(AR928X, gpio) != 0;
2308 else
2309 return MS_REG_READ(AR, gpio) != 0;
f078f209 2310}
7322fd19 2311EXPORT_SYMBOL(ath9k_hw_gpio_get);
f078f209 2312
cbe61d8a 2313void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
f1dc5600 2314 u32 ah_signal_type)
f078f209 2315{
f1dc5600 2316 u32 gpio_shift;
f078f209 2317
f1dc5600 2318 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
f078f209 2319
f1dc5600 2320 gpio_shift = 2 * gpio;
f078f209 2321
f1dc5600
S		 2322 REG_RMW(ah,
2323 AR_GPIO_OE_OUT,
2324 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2325 (AR_GPIO_OE_OUT_DRV << gpio_shift));
f078f209 2326}
7322fd19 2327EXPORT_SYMBOL(ath9k_hw_cfg_output);
f078f209 2328
cbe61d8a 2329void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
f078f209 2330{
5b5fa355
S		 2331 if (AR_SREV_9271(ah))
2332 val = ~val;
2333
f1dc5600
S		 2334 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2335 AR_GPIO_BIT(gpio));
f078f209 2336}
7322fd19 2337EXPORT_SYMBOL(ath9k_hw_set_gpio);
f078f209 2338
cbe61d8a 2339u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
f078f209 2340{
f1dc5600 2341 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
f078f209 2342}
7322fd19 2343EXPORT_SYMBOL(ath9k_hw_getdefantenna);
f078f209 2344
cbe61d8a 2345void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
f078f209 2346{
f1dc5600 2347 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
f078f209 2348}
7322fd19 2349EXPORT_SYMBOL(ath9k_hw_setantenna);
f078f209 2350
f1dc5600
S		 2351/*********************/
2352/* General Operation */
2353/*********************/
2354
cbe61d8a 2355u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
f078f209 2356{
f1dc5600
S		 2357 u32 bits = REG_READ(ah, AR_RX_FILTER);
2358 u32 phybits = REG_READ(ah, AR_PHY_ERR);
f078f209 2359
f1dc5600
S		 2360 if (phybits & AR_PHY_ERR_RADAR)
2361 bits |= ATH9K_RX_FILTER_PHYRADAR;
2362 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2363 bits |= ATH9K_RX_FILTER_PHYERR;
dc2222a8 2364
f1dc5600 2365 return bits;
f078f209 2366}
7322fd19 2367EXPORT_SYMBOL(ath9k_hw_getrxfilter);
f078f209 2368
cbe61d8a 2369void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
f078f209 2370{
f1dc5600 2371 u32 phybits;
f078f209 2372
7ea310be
S		 2373 REG_WRITE(ah, AR_RX_FILTER, bits);
2374
f1dc5600
S		 2375 phybits = 0;
2376 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2377 phybits |= AR_PHY_ERR_RADAR;
2378 if (bits & ATH9K_RX_FILTER_PHYERR)
2379 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2380 REG_WRITE(ah, AR_PHY_ERR, phybits);
f078f209 2381
f1dc5600
S		 2382 if (phybits)
2383 REG_WRITE(ah, AR_RXCFG,
2384 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2385 else
2386 REG_WRITE(ah, AR_RXCFG,
2387 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2388}
7322fd19 2389EXPORT_SYMBOL(ath9k_hw_setrxfilter);
f078f209 2390
cbe61d8a 2391bool ath9k_hw_phy_disable(struct ath_hw *ah)
f1dc5600 2392{
63a75b91
SB		 2393 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2394 return false;
2395
2396 ath9k_hw_init_pll(ah, NULL);
2397 return true;
f1dc5600 2398}
7322fd19 2399EXPORT_SYMBOL(ath9k_hw_phy_disable);
f078f209 2400
cbe61d8a 2401bool ath9k_hw_disable(struct ath_hw *ah)
f1dc5600 2402{
9ecdef4b 2403 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
f1dc5600 2404 return false;
f078f209 2405
63a75b91
SB		 2406 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2407 return false;
2408
2409 ath9k_hw_init_pll(ah, NULL);
2410 return true;
f078f209 2411}
7322fd19 2412EXPORT_SYMBOL(ath9k_hw_disable);
f078f209 2413
8fbff4b8 2414void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
f078f209 2415{
608b88cb 2416 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2660b81a 2417 struct ath9k_channel *chan = ah->curchan;
5f8e077c 2418 struct ieee80211_channel *channel = chan->chan;
f078f209 2419
608b88cb 2420 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
6f255425 2421
8fbff4b8 2422 ah->eep_ops->set_txpower(ah, chan,
608b88cb 2423 ath9k_regd_get_ctl(regulatory, chan),
8fbff4b8
VT		 2424 channel->max_antenna_gain * 2,
2425 channel->max_power * 2,
2426 min((u32) MAX_RATE_POWER,
608b88cb 2427 (u32) regulatory->power_limit));
6f255425 2428}
7322fd19 2429EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
6f255425 2430
cbe61d8a 2431void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
f078f209 2432{
1510718d 2433 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
f078f209 2434}
7322fd19 2435EXPORT_SYMBOL(ath9k_hw_setmac);
f078f209 2436
cbe61d8a 2437void ath9k_hw_setopmode(struct ath_hw *ah)
f078f209 2438{
2660b81a 2439 ath9k_hw_set_operating_mode(ah, ah->opmode);
f078f209 2440}
7322fd19 2441EXPORT_SYMBOL(ath9k_hw_setopmode);
f078f209 2442
cbe61d8a 2443void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
f078f209 2444{
f1dc5600
S		 2445 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2446 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
f078f209 2447}
7322fd19 2448EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
f078f209 2449
f2b2143e 2450void ath9k_hw_write_associd(struct ath_hw *ah)
f078f209 2451{
1510718d
LR		 2452 struct ath_common *common = ath9k_hw_common(ah);
2453
2454 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2455 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2456 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
f078f209 2457}
7322fd19 2458EXPORT_SYMBOL(ath9k_hw_write_associd);
f078f209 2459
cbe61d8a 2460u64 ath9k_hw_gettsf64(struct ath_hw *ah)
f078f209 2461{
f1dc5600 2462 u64 tsf;
f078f209 2463
f1dc5600
S		 2464 tsf = REG_READ(ah, AR_TSF_U32);
2465 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
f078f209 2466
f1dc5600
S		 2467 return tsf;
2468}
7322fd19 2469EXPORT_SYMBOL(ath9k_hw_gettsf64);
f078f209 2470
cbe61d8a 2471void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
27abe060 2472{
27abe060 2473 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
b9a16197 2474 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
27abe060 2475}
7322fd19 2476EXPORT_SYMBOL(ath9k_hw_settsf64);
27abe060 2477
cbe61d8a 2478void ath9k_hw_reset_tsf(struct ath_hw *ah)
f1dc5600 2479{
f9b604f6
GJ		 2480 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2481 AH_TSF_WRITE_TIMEOUT))
c46917bb
LR		 2482 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2483 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
f9b604f6 2484
f1dc5600
S		 2485 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2486}
7322fd19 2487EXPORT_SYMBOL(ath9k_hw_reset_tsf);
f078f209 2488
54e4cec6 2489void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
f1dc5600 2490{
f1dc5600 2491 if (setting)
2660b81a 2492 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
f1dc5600 2493 else
2660b81a 2494 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
f1dc5600 2495}
7322fd19 2496EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
f078f209 2497
30cbd422
LR		 2498/*
2499 * Extend 15-bit time stamp from rx descriptor to
2500 * a full 64-bit TSF using the current h/w TSF.
2501*/
2502u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2503{
2504 u64 tsf;
2505
2506 tsf = ath9k_hw_gettsf64(ah);
2507 if ((tsf & 0x7fff) < rstamp)
2508 tsf -= 0x8000;
2509 return (tsf & ~0x7fff) | rstamp;
2510}
2511EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2512
25c56eec 2513void ath9k_hw_set11nmac2040(struct ath_hw *ah)
f1dc5600 2514{
25c56eec 2515 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
f1dc5600
S		 2516 u32 macmode;
2517
25c56eec 2518 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
f1dc5600
S		 2519 macmode = AR_2040_JOINED_RX_CLEAR;
2520 else
2521 macmode = 0;
f078f209 2522
f1dc5600 2523 REG_WRITE(ah, AR_2040_MODE, macmode);
f078f209 2524}
ff155a45
VT		 2525
2526/* HW Generic timers configuration */
2527
2528static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2529{
2530 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2531 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2532 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2533 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2534 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2535 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2536 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2537 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2538 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2539 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2540 AR_NDP2_TIMER_MODE, 0x0002},
2541 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2542 AR_NDP2_TIMER_MODE, 0x0004},
2543 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2544 AR_NDP2_TIMER_MODE, 0x0008},
2545 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2546 AR_NDP2_TIMER_MODE, 0x0010},
2547 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2548 AR_NDP2_TIMER_MODE, 0x0020},
2549 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2550 AR_NDP2_TIMER_MODE, 0x0040},
2551 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2552 AR_NDP2_TIMER_MODE, 0x0080}
2553};
2554
2555/* HW generic timer primitives */
2556
2557/* compute and clear index of rightmost 1 */
2558static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2559{
2560 u32 b;
2561
2562 b = *mask;
2563 b &= (0-b);
2564 *mask &= ~b;
2565 b *= debruijn32;
2566 b >>= 27;
2567
2568 return timer_table->gen_timer_index[b];
2569}
2570
1773912b 2571u32 ath9k_hw_gettsf32(struct ath_hw *ah)
ff155a45
VT		 2572{
2573 return REG_READ(ah, AR_TSF_L32);
2574}
7322fd19 2575EXPORT_SYMBOL(ath9k_hw_gettsf32);
ff155a45
VT		 2576
2577struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2578 void (*trigger)(void *),
2579 void (*overflow)(void *),
2580 void *arg,
2581 u8 timer_index)
2582{
2583 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2584 struct ath_gen_timer *timer;
2585
2586 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2587
2588 if (timer == NULL) {
c46917bb
LR		 2589 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2590 "Failed to allocate memory"
2591 "for hw timer[%d]\n", timer_index);
ff155a45
VT		 2592 return NULL;
2593 }
2594
2595 /* allocate a hardware generic timer slot */
2596 timer_table->timers[timer_index] = timer;
2597 timer->index = timer_index;
2598 timer->trigger = trigger;
2599 timer->overflow = overflow;
2600 timer->arg = arg;
2601
2602 return timer;
2603}
7322fd19 2604EXPORT_SYMBOL(ath_gen_timer_alloc);
ff155a45 2605
cd9bf689
LR		 2606void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2607 struct ath_gen_timer *timer,
2608 u32 timer_next,
2609 u32 timer_period)
ff155a45
VT		 2610{
2611 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2612 u32 tsf;
2613
2614 BUG_ON(!timer_period);
2615
2616 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2617
2618 tsf = ath9k_hw_gettsf32(ah);
2619
c46917bb
LR		 2620 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2621 "curent tsf %x period %x"
2622 "timer_next %x\n", tsf, timer_period, timer_next);
ff155a45
VT		 2623
2624 /*
2625 * Pull timer_next forward if the current TSF already passed it
2626 * because of software latency
2627 */
2628 if (timer_next < tsf)
2629 timer_next = tsf + timer_period;
2630
2631 /*
2632 * Program generic timer registers
2633 */
2634 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2635 timer_next);
2636 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2637 timer_period);
2638 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2639 gen_tmr_configuration[timer->index].mode_mask);
2640
2641 /* Enable both trigger and thresh interrupt masks */
2642 REG_SET_BIT(ah, AR_IMR_S5,
2643 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2644 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
ff155a45 2645}
7322fd19 2646EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
ff155a45 2647
cd9bf689 2648void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
ff155a45
VT		 2649{
2650 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2651
2652 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2653 (timer->index >= ATH_MAX_GEN_TIMER)) {
2654 return;
2655 }
2656
2657 /* Clear generic timer enable bits. */
2658 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2659 gen_tmr_configuration[timer->index].mode_mask);
2660
2661 /* Disable both trigger and thresh interrupt masks */
2662 REG_CLR_BIT(ah, AR_IMR_S5,
2663 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2664 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2665
2666 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
ff155a45 2667}
7322fd19 2668EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
ff155a45
VT		 2669
2670void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2671{
2672 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2673
2674 /* free the hardware generic timer slot */
2675 timer_table->timers[timer->index] = NULL;
2676 kfree(timer);
2677}
7322fd19 2678EXPORT_SYMBOL(ath_gen_timer_free);
ff155a45
VT		 2679
2680/*
2681 * Generic Timer Interrupts handling
2682 */
2683void ath_gen_timer_isr(struct ath_hw *ah)
2684{
2685 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2686 struct ath_gen_timer *timer;
c46917bb 2687 struct ath_common *common = ath9k_hw_common(ah);
ff155a45
VT		 2688 u32 trigger_mask, thresh_mask, index;
2689
2690 /* get hardware generic timer interrupt status */
2691 trigger_mask = ah->intr_gen_timer_trigger;
2692 thresh_mask = ah->intr_gen_timer_thresh;
2693 trigger_mask &= timer_table->timer_mask.val;
2694 thresh_mask &= timer_table->timer_mask.val;
2695
2696 trigger_mask &= ~thresh_mask;
2697
2698 while (thresh_mask) {
2699 index = rightmost_index(timer_table, &thresh_mask);
2700 timer = timer_table->timers[index];
2701 BUG_ON(!timer);
c46917bb
LR		 2702 ath_print(common, ATH_DBG_HWTIMER,
2703 "TSF overflow for Gen timer %d\n", index);
ff155a45
VT		 2704 timer->overflow(timer->arg);
2705 }
2706
2707 while (trigger_mask) {
2708 index = rightmost_index(timer_table, &trigger_mask);
2709 timer = timer_table->timers[index];
2710 BUG_ON(!timer);
c46917bb
LR		 2711 ath_print(common, ATH_DBG_HWTIMER,
2712 "Gen timer[%d] trigger\n", index);
ff155a45
VT		 2713 timer->trigger(timer->arg);
2714 }
2715}
7322fd19 2716EXPORT_SYMBOL(ath_gen_timer_isr);
2da4f01a 2717
05020d23
S		 2718/********/
2719/* HTC */
2720/********/
2721
2722void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2723{
2724 ah->htc_reset_init = true;
2725}
2726EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2727
2da4f01a
LR		 2728static struct {
2729 u32 version;
2730 const char * name;
2731} ath_mac_bb_names[] = {
2732 /* Devices with external radios */
2733 { AR_SREV_VERSION_5416_PCI, "5416" },
2734 { AR_SREV_VERSION_5416_PCIE, "5418" },
2735 { AR_SREV_VERSION_9100, "9100" },
2736 { AR_SREV_VERSION_9160, "9160" },
2737 /* Single-chip solutions */
2738 { AR_SREV_VERSION_9280, "9280" },
2739 { AR_SREV_VERSION_9285, "9285" },
11158472
LR		 2740 { AR_SREV_VERSION_9287, "9287" },
2741 { AR_SREV_VERSION_9271, "9271" },
2da4f01a
LR		 2742};
2743
2744/* For devices with external radios */
2745static struct {
2746 u16 version;
2747 const char * name;
2748} ath_rf_names[] = {
2749 { 0, "5133" },
2750 { AR_RAD5133_SREV_MAJOR, "5133" },
2751 { AR_RAD5122_SREV_MAJOR, "5122" },
2752 { AR_RAD2133_SREV_MAJOR, "2133" },
2753 { AR_RAD2122_SREV_MAJOR, "2122" }
2754};
2755
2756/*
2757 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2758 */
f934c4d9 2759static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2da4f01a
LR		 2760{
2761 int i;
2762
2763 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2764 if (ath_mac_bb_names[i].version == mac_bb_version) {
2765 return ath_mac_bb_names[i].name;
2766 }
2767 }
2768
2769 return "????";
2770}
2da4f01a
LR		 2771
2772/*
2773 * Return the RF name. "????" is returned if the RF is unknown.
2774 * Used for devices with external radios.
2775 */
f934c4d9 2776static const char *ath9k_hw_rf_name(u16 rf_version)
2da4f01a
LR		 2777{
2778 int i;
2779
2780 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2781 if (ath_rf_names[i].version == rf_version) {
2782 return ath_rf_names[i].name;
2783 }
2784 }
2785
2786 return "????";
2787}
f934c4d9
LR		 2788
2789void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2790{
2791 int used;
2792
2793 /* chipsets >= AR9280 are single-chip */
2794 if (AR_SREV_9280_10_OR_LATER(ah)) {
2795 used = snprintf(hw_name, len,
2796 "Atheros AR%s Rev:%x",
2797 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2798 ah->hw_version.macRev);
2799 }
2800 else {
2801 used = snprintf(hw_name, len,
2802 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2803 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2804 ah->hw_version.macRev,
2805 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2806 AR_RADIO_SREV_MAJOR)),
2807 ah->hw_version.phyRev);
2808 }
2809
2810 hw_name[used] = '\0';
2811}
2812EXPORT_SYMBOL(ath9k_hw_name);
Clone of davem's net-next-2.6 tree