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ath9k_hw: Optimize ath9k_hw_ar9287_set_board_values
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_9287.c
CommitLineData
b5aec950
S		 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
c46917bb 17#include "hw.h"
8fe65368 18#include "ar9002_phy.h"
b5aec950 19
16c94ac6
S		 20#define NUM_EEP_WORDS (sizeof(struct ar9287_eeprom) / sizeof(u16))
21
22static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
b5aec950
S		 23{
24 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
25}
26
16c94ac6 27static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
b5aec950
S		 28{
29 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
30}
31
16c94ac6 32static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
b5aec950
S		 33{
34 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
c46917bb 35 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 36 u16 *eep_data;
37 int addr, eep_start_loc = AR9287_EEP_START_LOC;
38 eep_data = (u16 *)eep;
39
40 if (!ath9k_hw_use_flash(ah)) {
c46917bb
LR		 41 ath_print(common, ATH_DBG_EEPROM,
42 "Reading from EEPROM, not flash\n");
b5aec950
S		 43 }
44
16c94ac6
S		 45 for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
46 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
47 eep_data)) {
c46917bb 48 ath_print(common, ATH_DBG_EEPROM,
60ece404 49 "Unable to read eeprom region\n");
b5aec950
S		 50 return false;
51 }
52 eep_data++;
53 }
16c94ac6 54
b5aec950
S		 55 return true;
56}
57
16c94ac6 58static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
b5aec950
S		 59{
60 u32 sum = 0, el, integer;
61 u16 temp, word, magic, magic2, *eepdata;
62 int i, addr;
63 bool need_swap = false;
64 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
c46917bb 65 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 66
67 if (!ath9k_hw_use_flash(ah)) {
16c94ac6
S		 68 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
69 &magic)) {
c46917bb
LR		 70 ath_print(common, ATH_DBG_FATAL,
71 "Reading Magic # failed\n");
b5aec950
S		 72 return false;
73 }
74
c46917bb
LR		 75 ath_print(common, ATH_DBG_EEPROM,
76 "Read Magic = 0x%04X\n", magic);
16c94ac6 77
b5aec950
S		 78 if (magic != AR5416_EEPROM_MAGIC) {
79 magic2 = swab16(magic);
80
81 if (magic2 == AR5416_EEPROM_MAGIC) {
82 need_swap = true;
83 eepdata = (u16 *)(&ah->eeprom);
84
16c94ac6 85 for (addr = 0; addr < NUM_EEP_WORDS; addr++) {
b5aec950
S		 86 temp = swab16(*eepdata);
87 *eepdata = temp;
88 eepdata++;
89 }
90 } else {
c46917bb
LR		 91 ath_print(common, ATH_DBG_FATAL,
92 "Invalid EEPROM Magic. "
16c94ac6 93 "Endianness mismatch.\n");
b5aec950
S		 94 return -EINVAL;
95 }
96 }
97 }
16c94ac6
S		 98
99 ath_print(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
100 need_swap ? "True" : "False");
b5aec950
S		 101
102 if (need_swap)
103 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
104 else
105 el = ah->eeprom.map9287.baseEepHeader.length;
106
107 if (el > sizeof(struct ar9287_eeprom))
108 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
109 else
110 el = el / sizeof(u16);
111
112 eepdata = (u16 *)(&ah->eeprom);
16c94ac6 113
b5aec950
S		 114 for (i = 0; i < el; i++)
115 sum ^= *eepdata++;
116
117 if (need_swap) {
118 word = swab16(eep->baseEepHeader.length);
119 eep->baseEepHeader.length = word;
120
121 word = swab16(eep->baseEepHeader.checksum);
122 eep->baseEepHeader.checksum = word;
123
124 word = swab16(eep->baseEepHeader.version);
125 eep->baseEepHeader.version = word;
126
127 word = swab16(eep->baseEepHeader.regDmn[0]);
128 eep->baseEepHeader.regDmn[0] = word;
129
130 word = swab16(eep->baseEepHeader.regDmn[1]);
131 eep->baseEepHeader.regDmn[1] = word;
132
133 word = swab16(eep->baseEepHeader.rfSilent);
134 eep->baseEepHeader.rfSilent = word;
135
136 word = swab16(eep->baseEepHeader.blueToothOptions);
137 eep->baseEepHeader.blueToothOptions = word;
138
139 word = swab16(eep->baseEepHeader.deviceCap);
140 eep->baseEepHeader.deviceCap = word;
141
142 integer = swab32(eep->modalHeader.antCtrlCommon);
143 eep->modalHeader.antCtrlCommon = integer;
144
145 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
146 integer = swab32(eep->modalHeader.antCtrlChain[i]);
147 eep->modalHeader.antCtrlChain[i] = integer;
148 }
149
150 for (i = 0; i < AR9287_EEPROM_MODAL_SPURS; i++) {
151 word = swab16(eep->modalHeader.spurChans[i].spurChan);
152 eep->modalHeader.spurChans[i].spurChan = word;
153 }
154 }
155
156 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
157 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
c46917bb
LR		 158 ath_print(common, ATH_DBG_FATAL,
159 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
160 sum, ah->eep_ops->get_eeprom_ver(ah));
b5aec950
S		 161 return -EINVAL;
162 }
163
164 return 0;
165}
166
16c94ac6 167static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
b5aec950
S		 168 enum eeprom_param param)
169{
170 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
171 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
172 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
173 u16 ver_minor;
174
175 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
16c94ac6 176
b5aec950
S		 177 switch (param) {
178 case EEP_NFTHRESH_2:
179 return pModal->noiseFloorThreshCh[0];
49101676 180 case EEP_MAC_LSW:
b5aec950 181 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
49101676 182 case EEP_MAC_MID:
b5aec950 183 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
49101676 184 case EEP_MAC_MSW:
b5aec950
S		 185 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
186 case EEP_REG_0:
187 return pBase->regDmn[0];
188 case EEP_REG_1:
189 return pBase->regDmn[1];
190 case EEP_OP_CAP:
191 return pBase->deviceCap;
192 case EEP_OP_MODE:
193 return pBase->opCapFlags;
194 case EEP_RF_SILENT:
195 return pBase->rfSilent;
196 case EEP_MINOR_REV:
197 return ver_minor;
198 case EEP_TX_MASK:
199 return pBase->txMask;
200 case EEP_RX_MASK:
201 return pBase->rxMask;
202 case EEP_DEV_TYPE:
203 return pBase->deviceType;
204 case EEP_OL_PWRCTRL:
205 return pBase->openLoopPwrCntl;
206 case EEP_TEMPSENSE_SLOPE:
207 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
208 return pBase->tempSensSlope;
209 else
210 return 0;
211 case EEP_TEMPSENSE_SLOPE_PAL_ON:
212 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
213 return pBase->tempSensSlopePalOn;
214 else
215 return 0;
216 default:
217 return 0;
218 }
219}
220
16c94ac6
S		 221static void ath9k_hw_get_ar9287_gain_boundaries_pdadcs(struct ath_hw *ah,
222 struct ath9k_channel *chan,
223 struct cal_data_per_freq_ar9287 *pRawDataSet,
224 u8 *bChans, u16 availPiers,
225 u16 tPdGainOverlap,
226 int16_t *pMinCalPower,
227 u16 *pPdGainBoundaries,
228 u8 *pPDADCValues,
229 u16 numXpdGains)
b5aec950 230{
16c94ac6 231#define TMP_VAL_VPD_TABLE \
b5aec950
S		 232 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
233
16c94ac6
S		 234 int i, j, k;
235 int16_t ss;
236 u16 idxL = 0, idxR = 0, numPiers;
237 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
238 u8 minPwrT4[AR9287_NUM_PD_GAINS];
239 u8 maxPwrT4[AR9287_NUM_PD_GAINS];
240 int16_t vpdStep;
241 int16_t tmpVal;
242 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
243 bool match;
244 int16_t minDelta = 0;
b5aec950
S		 245 struct chan_centers centers;
246 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
247 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
248 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
249 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
250 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
251 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
252
253 ath9k_hw_get_channel_centers(ah, chan, &centers);
254
255 for (numPiers = 0; numPiers < availPiers; numPiers++) {
256 if (bChans[numPiers] == AR9287_BCHAN_UNUSED)
257 break;
258 }
259
260 match = ath9k_hw_get_lower_upper_index(
16c94ac6
S		 261 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
262 bChans, numPiers, &idxL, &idxR);
b5aec950
S		 263
264 if (match) {
265 for (i = 0; i < numXpdGains; i++) {
266 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
267 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
268 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
16c94ac6
S		 269 pRawDataSet[idxL].pwrPdg[i],
270 pRawDataSet[idxL].vpdPdg[i],
271 AR9287_PD_GAIN_ICEPTS,
272 vpdTableI[i]);
b5aec950
S		 273 }
274 } else {
275 for (i = 0; i < numXpdGains; i++) {
276 pVpdL = pRawDataSet[idxL].vpdPdg[i];
277 pPwrL = pRawDataSet[idxL].pwrPdg[i];
278 pVpdR = pRawDataSet[idxR].vpdPdg[i];
279 pPwrR = pRawDataSet[idxR].pwrPdg[i];
280
281 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
282
16c94ac6
S		 283 maxPwrT4[i] = min(pPwrL[AR9287_PD_GAIN_ICEPTS - 1],
284 pPwrR[AR9287_PD_GAIN_ICEPTS - 1]);
b5aec950
S		 285
286 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
16c94ac6
S		 287 pPwrL, pVpdL,
288 AR9287_PD_GAIN_ICEPTS,
289 vpdTableL[i]);
b5aec950 290 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
16c94ac6
S		 291 pPwrR, pVpdR,
292 AR9287_PD_GAIN_ICEPTS,
293 vpdTableR[i]);
b5aec950
S		 294
295 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
16c94ac6
S		 296 vpdTableI[i][j] = (u8)(ath9k_hw_interpolate(
297 (u16)FREQ2FBIN(centers. synth_center,
298 IS_CHAN_2GHZ(chan)),
299 bChans[idxL], bChans[idxR],
300 vpdTableL[i][j], vpdTableR[i][j]));
b5aec950
S		 301 }
302 }
303 }
b5aec950 304
16c94ac6 305 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
b5aec950 306 k = 0;
16c94ac6 307
b5aec950
S		 308 for (i = 0; i < numXpdGains; i++) {
309 if (i == (numXpdGains - 1))
16c94ac6
S		 310 pPdGainBoundaries[i] =
311 (u16)(maxPwrT4[i] / 2);
b5aec950 312 else
16c94ac6
S		 313 pPdGainBoundaries[i] =
314 (u16)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
b5aec950
S		 315
316 pPdGainBoundaries[i] = min((u16)AR5416_MAX_RATE_POWER,
16c94ac6 317 pPdGainBoundaries[i]);
b5aec950
S		 318
319
320 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
321 minDelta = pPdGainBoundaries[0] - 23;
322 pPdGainBoundaries[0] = 23;
323 } else
324 minDelta = 0;
325
326 if (i == 0) {
327 if (AR_SREV_9280_10_OR_LATER(ah))
328 ss = (int16_t)(0 - (minPwrT4[i] / 2));
329 else
330 ss = 0;
331 } else
332 ss = (int16_t)((pPdGainBoundaries[i-1] -
16c94ac6 333 (minPwrT4[i] / 2)) -
b5aec950
S		 334 tPdGainOverlap + 1 + minDelta);
335
336 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
337 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
16c94ac6 338
b5aec950
S		 339 while ((ss < 0) && (k < (AR9287_NUM_PDADC_VALUES - 1))) {
340 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
341 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
342 ss++;
343 }
344
345 sizeCurrVpdTable = (u8)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
346 tgtIndex = (u8)(pPdGainBoundaries[i] +
347 tPdGainOverlap - (minPwrT4[i] / 2));
348 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
349 tgtIndex : sizeCurrVpdTable;
350
351 while ((ss < maxIndex) && (k < (AR9287_NUM_PDADC_VALUES - 1)))
352 pPDADCValues[k++] = vpdTableI[i][ss++];
353
354 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
355 vpdTableI[i][sizeCurrVpdTable - 2]);
356 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
16c94ac6 357
b5aec950
S		 358 if (tgtIndex > maxIndex) {
359 while ((ss <= tgtIndex) &&
360 (k < (AR9287_NUM_PDADC_VALUES - 1))) {
361 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
16c94ac6
S		 362 pPDADCValues[k++] =
363 (u8)((tmpVal > 255) ? 255 : tmpVal);
b5aec950
S		 364 ss++;
365 }
366 }
367 }
368
369 while (i < AR9287_PD_GAINS_IN_MASK) {
370 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
371 i++;
372 }
373
374 while (k < AR9287_NUM_PDADC_VALUES) {
375 pPDADCValues[k] = pPDADCValues[k-1];
376 k++;
377 }
378
379#undef TMP_VAL_VPD_TABLE
380}
381
382static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
383 struct ath9k_channel *chan,
384 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
16c94ac6 385 u8 *pCalChans, u16 availPiers, int8_t *pPwr)
b5aec950 386{
16c94ac6 387 u16 idxL = 0, idxR = 0, numPiers;
b5aec950
S		 388 bool match;
389 struct chan_centers centers;
390
391 ath9k_hw_get_channel_centers(ah, chan, &centers);
392
393 for (numPiers = 0; numPiers < availPiers; numPiers++) {
394 if (pCalChans[numPiers] == AR9287_BCHAN_UNUSED)
395 break;
396 }
397
398 match = ath9k_hw_get_lower_upper_index(
399 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
16c94ac6 400 pCalChans, numPiers, &idxL, &idxR);
b5aec950
S		 401
402 if (match) {
d4fe5afa 403 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
b5aec950 404 } else {
d4fe5afa 405 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
16c94ac6 406 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
b5aec950
S		 407 }
408
b5aec950
S		 409}
410
411static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
412 int32_t txPower, u16 chain)
413{
414 u32 tmpVal;
415 u32 a;
416
16c94ac6
S		 417 /* Enable OLPC for chain 0 */
418
b5aec950
S		 419 tmpVal = REG_READ(ah, 0xa270);
420 tmpVal = tmpVal & 0xFCFFFFFF;
421 tmpVal = tmpVal | (0x3 << 24);
422 REG_WRITE(ah, 0xa270, tmpVal);
423
16c94ac6
S		 424 /* Enable OLPC for chain 1 */
425
b5aec950
S		 426 tmpVal = REG_READ(ah, 0xb270);
427 tmpVal = tmpVal & 0xFCFFFFFF;
428 tmpVal = tmpVal | (0x3 << 24);
429 REG_WRITE(ah, 0xb270, tmpVal);
430
16c94ac6
S		 431 /* Write the OLPC ref power for chain 0 */
432
b5aec950
S		 433 if (chain == 0) {
434 tmpVal = REG_READ(ah, 0xa398);
435 tmpVal = tmpVal & 0xff00ffff;
436 a = (txPower)&0xff;
437 tmpVal = tmpVal | (a << 16);
438 REG_WRITE(ah, 0xa398, tmpVal);
439 }
440
16c94ac6
S		 441 /* Write the OLPC ref power for chain 1 */
442
b5aec950
S		 443 if (chain == 1) {
444 tmpVal = REG_READ(ah, 0xb398);
445 tmpVal = tmpVal & 0xff00ffff;
446 a = (txPower)&0xff;
447 tmpVal = tmpVal | (a << 16);
448 REG_WRITE(ah, 0xb398, tmpVal);
449 }
450}
451
16c94ac6 452static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
b5aec950
S		 453 struct ath9k_channel *chan,
454 int16_t *pTxPowerIndexOffset)
455{
456 struct cal_data_per_freq_ar9287 *pRawDataset;
457 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
16c94ac6 458 u8 *pCalBChans = NULL;
b5aec950 459 u16 pdGainOverlap_t2;
16c94ac6 460 u8 pdadcValues[AR9287_NUM_PDADC_VALUES];
b5aec950
S		 461 u16 gainBoundaries[AR9287_PD_GAINS_IN_MASK];
462 u16 numPiers = 0, i, j;
16c94ac6 463 int16_t tMinCalPower;
b5aec950
S		 464 u16 numXpdGain, xpdMask;
465 u16 xpdGainValues[AR9287_NUM_PD_GAINS] = {0, 0, 0, 0};
466 u32 reg32, regOffset, regChainOffset;
16c94ac6 467 int16_t modalIdx, diff = 0;
b5aec950 468 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
16c94ac6 469
b5aec950
S		 470 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
471 xpdMask = pEepData->modalHeader.xpdGain;
16c94ac6 472
b5aec950
S		 473 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
474 AR9287_EEP_MINOR_VER_2)
475 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
476 else
477 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
478 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
479
480 if (IS_CHAN_2GHZ(chan)) {
481 pCalBChans = pEepData->calFreqPier2G;
482 numPiers = AR9287_NUM_2G_CAL_PIERS;
16c94ac6 483 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
b5aec950
S		 484 pRawDatasetOpenLoop =
485 (struct cal_data_op_loop_ar9287 *)
486 pEepData->calPierData2G[0];
487 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
488 }
489 }
490
491 numXpdGain = 0;
16c94ac6 492
b5aec950
S		 493 for (i = 1; i <= AR9287_PD_GAINS_IN_MASK; i++) {
494 if ((xpdMask >> (AR9287_PD_GAINS_IN_MASK - i)) & 1) {
495 if (numXpdGain >= AR9287_NUM_PD_GAINS)
496 break;
497 xpdGainValues[numXpdGain] =
498 (u16)(AR9287_PD_GAINS_IN_MASK-i);
499 numXpdGain++;
500 }
501 }
502
503 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
504 (numXpdGain - 1) & 0x3);
505 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
506 xpdGainValues[0]);
507 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
508 xpdGainValues[1]);
509 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
510 xpdGainValues[2]);
511
512 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
513 regChainOffset = i * 0x1000;
514 if (pEepData->baseEepHeader.txMask & (1 << i)) {
515 pRawDatasetOpenLoop = (struct cal_data_op_loop_ar9287 *)
516 pEepData->calPierData2G[i];
16c94ac6 517 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
b5aec950
S		 518 int8_t txPower;
519 ar9287_eeprom_get_tx_gain_index(ah, chan,
520 pRawDatasetOpenLoop,
521 pCalBChans, numPiers,
522 &txPower);
523 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
524 } else {
525 pRawDataset =
526 (struct cal_data_per_freq_ar9287 *)
527 pEepData->calPierData2G[i];
16c94ac6 528 ath9k_hw_get_ar9287_gain_boundaries_pdadcs(
b5aec950
S		 529 ah, chan, pRawDataset,
530 pCalBChans, numPiers,
531 pdGainOverlap_t2,
532 &tMinCalPower, gainBoundaries,
533 pdadcValues, numXpdGain);
534 }
535
536 if (i == 0) {
16c94ac6 537 if (!ath9k_hw_ar9287_get_eeprom(
b5aec950
S		 538 ah, EEP_OL_PWRCTRL)) {
539 REG_WRITE(ah, AR_PHY_TPCRG5 +
540 regChainOffset,
541 SM(pdGainOverlap_t2,
542 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
543 SM(gainBoundaries[0],
544 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
545 | SM(gainBoundaries[1],
546 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
547 | SM(gainBoundaries[2],
548 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
549 | SM(gainBoundaries[3],
550 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
551 }
552 }
553
554 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
555 pEepData->baseEepHeader.pwrTableOffset) {
556 diff = (u16)
557 (pEepData->baseEepHeader.pwrTableOffset
558 - (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
559 diff *= 2;
560
561 for (j = 0;
562 j < ((u16)AR9287_NUM_PDADC_VALUES-diff);
563 j++)
564 pdadcValues[j] = pdadcValues[j+diff];
565
566 for (j = (u16)(AR9287_NUM_PDADC_VALUES-diff);
567 j < AR9287_NUM_PDADC_VALUES; j++)
568 pdadcValues[j] =
569 pdadcValues[
570 AR9287_NUM_PDADC_VALUES-diff];
571 }
572
16c94ac6 573 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
b5aec950
S		 574 regOffset = AR_PHY_BASE + (672 << 2) +
575 regChainOffset;
576 for (j = 0; j < 32; j++) {
577 reg32 = ((pdadcValues[4*j + 0]
578 & 0xFF) << 0) |
579 ((pdadcValues[4*j + 1]
580 & 0xFF) << 8) |
581 ((pdadcValues[4*j + 2]
582 & 0xFF) << 16) |
583 ((pdadcValues[4*j + 3]
584 & 0xFF) << 24) ;
585 REG_WRITE(ah, regOffset, reg32);
b5aec950
S		 586 regOffset += 4;
587 }
588 }
589 }
590 }
591
592 *pTxPowerIndexOffset = 0;
593}
594
16c94ac6
S		 595static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
596 struct ath9k_channel *chan,
597 int16_t *ratesArray,
598 u16 cfgCtl,
599 u16 AntennaReduction,
600 u16 twiceMaxRegulatoryPower,
601 u16 powerLimit)
b5aec950
S		 602{
603#define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
604#define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
16c94ac6 605
608b88cb 606 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 607 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
608 static const u16 tpScaleReductionTable[5] =
609 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
610 int i;
16c94ac6 611 int16_t twiceLargestAntenna;
b5aec950
S		 612 struct cal_ctl_data_ar9287 *rep;
613 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
614 targetPowerCck = {0, {0, 0, 0, 0} };
615 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
616 targetPowerCckExt = {0, {0, 0, 0, 0} };
16c94ac6 617 struct cal_target_power_ht targetPowerHt20,
b5aec950
S		 618 targetPowerHt40 = {0, {0, 0, 0, 0} };
619 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
620 u16 ctlModesFor11g[] =
621 {CTL_11B, CTL_11G, CTL_2GHT20,
622 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40};
623 u16 numCtlModes = 0, *pCtlMode = NULL, ctlMode, freq;
624 struct chan_centers centers;
625 int tx_chainmask;
626 u16 twiceMinEdgePower;
627 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
628 tx_chainmask = ah->txchainmask;
629
630 ath9k_hw_get_channel_centers(ah, chan, &centers);
631
632 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
633 pEepData->modalHeader.antennaGainCh[1]);
634
16c94ac6
S		 635 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
636 twiceLargestAntenna, 0);
b5aec950
S		 637
638 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
608b88cb 639 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
b5aec950 640 maxRegAllowedPower -=
608b88cb 641 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
b5aec950
S		 642
643 scaledPower = min(powerLimit, maxRegAllowedPower);
644
645 switch (ar5416_get_ntxchains(tx_chainmask)) {
646 case 1:
647 break;
648 case 2:
649 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
650 break;
651 case 3:
652 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
653 break;
654 }
655 scaledPower = max((u16)0, scaledPower);
656
657 if (IS_CHAN_2GHZ(chan)) {
658 numCtlModes =
659 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
16c94ac6 660
b5aec950
S		 661 pCtlMode = ctlModesFor11g;
662
663 ath9k_hw_get_legacy_target_powers(ah, chan,
664 pEepData->calTargetPowerCck,
665 AR9287_NUM_2G_CCK_TARGET_POWERS,
666 &targetPowerCck, 4, false);
667 ath9k_hw_get_legacy_target_powers(ah, chan,
668 pEepData->calTargetPower2G,
669 AR9287_NUM_2G_20_TARGET_POWERS,
670 &targetPowerOfdm, 4, false);
671 ath9k_hw_get_target_powers(ah, chan,
672 pEepData->calTargetPower2GHT20,
673 AR9287_NUM_2G_20_TARGET_POWERS,
674 &targetPowerHt20, 8, false);
675
676 if (IS_CHAN_HT40(chan)) {
677 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
678 ath9k_hw_get_target_powers(ah, chan,
679 pEepData->calTargetPower2GHT40,
680 AR9287_NUM_2G_40_TARGET_POWERS,
681 &targetPowerHt40, 8, true);
682 ath9k_hw_get_legacy_target_powers(ah, chan,
683 pEepData->calTargetPowerCck,
684 AR9287_NUM_2G_CCK_TARGET_POWERS,
685 &targetPowerCckExt, 4, true);
686 ath9k_hw_get_legacy_target_powers(ah, chan,
687 pEepData->calTargetPower2G,
688 AR9287_NUM_2G_20_TARGET_POWERS,
689 &targetPowerOfdmExt, 4, true);
690 }
691 }
692
693 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
694 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
695 (pCtlMode[ctlMode] == CTL_2GHT40);
696 if (isHt40CtlMode)
697 freq = centers.synth_center;
698 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
699 freq = centers.ext_center;
700 else
701 freq = centers.ctl_center;
702
703 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
704 ah->eep_ops->get_eeprom_rev(ah) <= 2)
705 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
706
707 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
708 if ((((cfgCtl & ~CTL_MODE_M) |
709 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
710 pEepData->ctlIndex[i]) ||
711 (((cfgCtl & ~CTL_MODE_M) |
712 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
713 ((pEepData->ctlIndex[i] &
714 CTL_MODE_M) | SD_NO_CTL))) {
715
716 rep = &(pEepData->ctlData[i]);
717 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
718 freq,
719 rep->ctlEdges[ar5416_get_ntxchains(
720 tx_chainmask) - 1],
721 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
722
723 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
724 twiceMaxEdgePower = min(
725 twiceMaxEdgePower,
726 twiceMinEdgePower);
727 else {
728 twiceMaxEdgePower = twiceMinEdgePower;
729 break;
730 }
731 }
732 }
733
734 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
735
736 switch (pCtlMode[ctlMode]) {
737 case CTL_11B:
738 for (i = 0;
739 i < ARRAY_SIZE(targetPowerCck.tPow2x);
740 i++) {
741 targetPowerCck.tPow2x[i] = (u8)min(
742 (u16)targetPowerCck.tPow2x[i],
743 minCtlPower);
744 }
745 break;
746 case CTL_11A:
747 case CTL_11G:
748 for (i = 0;
749 i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
750 i++) {
751 targetPowerOfdm.tPow2x[i] = (u8)min(
752 (u16)targetPowerOfdm.tPow2x[i],
753 minCtlPower);
754 }
755 break;
756 case CTL_5GHT20:
757 case CTL_2GHT20:
758 for (i = 0;
759 i < ARRAY_SIZE(targetPowerHt20.tPow2x);
760 i++) {
761 targetPowerHt20.tPow2x[i] = (u8)min(
762 (u16)targetPowerHt20.tPow2x[i],
763 minCtlPower);
764 }
765 break;
766 case CTL_11B_EXT:
767 targetPowerCckExt.tPow2x[0] = (u8)min(
768 (u16)targetPowerCckExt.tPow2x[0],
769 minCtlPower);
770 break;
771 case CTL_11A_EXT:
772 case CTL_11G_EXT:
773 targetPowerOfdmExt.tPow2x[0] = (u8)min(
774 (u16)targetPowerOfdmExt.tPow2x[0],
775 minCtlPower);
776 break;
777 case CTL_5GHT40:
778 case CTL_2GHT40:
779 for (i = 0;
780 i < ARRAY_SIZE(targetPowerHt40.tPow2x);
781 i++) {
782 targetPowerHt40.tPow2x[i] = (u8)min(
783 (u16)targetPowerHt40.tPow2x[i],
784 minCtlPower);
785 }
786 break;
787 default:
788 break;
789 }
790 }
791
792 ratesArray[rate6mb] =
793 ratesArray[rate9mb] =
794 ratesArray[rate12mb] =
795 ratesArray[rate18mb] =
796 ratesArray[rate24mb] =
797 targetPowerOfdm.tPow2x[0];
798
799 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
800 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
801 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
802 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
803
804 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
805 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
806
807 if (IS_CHAN_2GHZ(chan)) {
808 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
809 ratesArray[rate2s] = ratesArray[rate2l] =
810 targetPowerCck.tPow2x[1];
811 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
812 targetPowerCck.tPow2x[2];
813 ratesArray[rate11s] = ratesArray[rate11l] =
814 targetPowerCck.tPow2x[3];
815 }
816 if (IS_CHAN_HT40(chan)) {
817 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
818 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
819
820 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
821 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
822 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
823 if (IS_CHAN_2GHZ(chan))
824 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
825 }
826
827#undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
828#undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
829}
830
16c94ac6 831static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
b5aec950
S		 832 struct ath9k_channel *chan, u16 cfgCtl,
833 u8 twiceAntennaReduction,
834 u8 twiceMaxRegulatoryPower,
835 u8 powerLimit)
836{
837#define INCREASE_MAXPOW_BY_TWO_CHAIN 6
838#define INCREASE_MAXPOW_BY_THREE_CHAIN 10
16c94ac6 839
c46917bb 840 struct ath_common *common = ath9k_hw_common(ah);
608b88cb 841 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
b5aec950
S		 842 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
843 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
844 int16_t ratesArray[Ar5416RateSize];
16c94ac6 845 int16_t txPowerIndexOffset = 0;
b5aec950
S		 846 u8 ht40PowerIncForPdadc = 2;
847 int i;
848
849 memset(ratesArray, 0, sizeof(ratesArray));
850
851 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
852 AR9287_EEP_MINOR_VER_2)
853 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
854
16c94ac6 855 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
b5aec950
S		 856 &ratesArray[0], cfgCtl,
857 twiceAntennaReduction,
858 twiceMaxRegulatoryPower,
859 powerLimit);
860
16c94ac6 861 ath9k_hw_set_ar9287_power_cal_table(ah, chan, &txPowerIndexOffset);
b5aec950
S		 862
863 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
864 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
865 if (ratesArray[i] > AR9287_MAX_RATE_POWER)
866 ratesArray[i] = AR9287_MAX_RATE_POWER;
867 }
868
869 if (AR_SREV_9280_10_OR_LATER(ah)) {
870 for (i = 0; i < Ar5416RateSize; i++)
871 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
872 }
873
874 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
875 ATH9K_POW_SM(ratesArray[rate18mb], 24)
876 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
877 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
878 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
879
880 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
881 ATH9K_POW_SM(ratesArray[rate54mb], 24)
882 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
883 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
884 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
885
886 if (IS_CHAN_2GHZ(chan)) {
887 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
888 ATH9K_POW_SM(ratesArray[rate2s], 24)
889 | ATH9K_POW_SM(ratesArray[rate2l], 16)
890 | ATH9K_POW_SM(ratesArray[rateXr], 8)
891 | ATH9K_POW_SM(ratesArray[rate1l], 0));
892 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
893 ATH9K_POW_SM(ratesArray[rate11s], 24)
894 | ATH9K_POW_SM(ratesArray[rate11l], 16)
895 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
896 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
897 }
898
899 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
900 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
901 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
902 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
903 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
904
905 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
906 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
907 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
908 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
909 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
910
911 if (IS_CHAN_HT40(chan)) {
16c94ac6 912 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
b5aec950
S		 913 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
914 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
915 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
916 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
917 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
918
919 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
920 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
921 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
922 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
923 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
924 } else {
925 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
926 ATH9K_POW_SM(ratesArray[rateHt40_3] +
927 ht40PowerIncForPdadc, 24)
928 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
929 ht40PowerIncForPdadc, 16)
930 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
931 ht40PowerIncForPdadc, 8)
932 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
933 ht40PowerIncForPdadc, 0));
934
935 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
936 ATH9K_POW_SM(ratesArray[rateHt40_7] +
937 ht40PowerIncForPdadc, 24)
938 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
939 ht40PowerIncForPdadc, 16)
940 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
941 ht40PowerIncForPdadc, 8)
942 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
943 ht40PowerIncForPdadc, 0));
944 }
945
946 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
947 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
948 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
949 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
950 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
951 }
952
953 if (IS_CHAN_2GHZ(chan))
954 i = rate1l;
955 else
956 i = rate6mb;
957
958 if (AR_SREV_9280_10_OR_LATER(ah))
608b88cb 959 regulatory->max_power_level =
b5aec950
S		 960 ratesArray[i] + AR9287_PWR_TABLE_OFFSET_DB * 2;
961 else
608b88cb 962 regulatory->max_power_level = ratesArray[i];
b5aec950
S		 963
964 switch (ar5416_get_ntxchains(ah->txchainmask)) {
965 case 1:
966 break;
967 case 2:
16c94ac6 968 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
b5aec950
S		 969 break;
970 case 3:
16c94ac6 971 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
b5aec950
S		 972 break;
973 default:
c46917bb
LR		 974 ath_print(common, ATH_DBG_EEPROM,
975 "Invalid chainmask configuration\n");
b5aec950
S		 976 break;
977 }
978}
979
16c94ac6 980static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
b5aec950
S		 981 struct ath9k_channel *chan)
982{
983}
984
16c94ac6 985static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
b5aec950
S		 986 struct ath9k_channel *chan)
987{
988 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
989 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
990 u16 antWrites[AR9287_ANT_16S];
79d7f4bc 991 u32 regChainOffset, regval;
b5aec950
S		 992 u8 txRxAttenLocal;
993 int i, j, offset_num;
994
995 pModal = &eep->modalHeader;
996
997 antWrites[0] = (u16)((pModal->antCtrlCommon >> 28) & 0xF);
998 antWrites[1] = (u16)((pModal->antCtrlCommon >> 24) & 0xF);
999 antWrites[2] = (u16)((pModal->antCtrlCommon >> 20) & 0xF);
1000 antWrites[3] = (u16)((pModal->antCtrlCommon >> 16) & 0xF);
1001 antWrites[4] = (u16)((pModal->antCtrlCommon >> 12) & 0xF);
1002 antWrites[5] = (u16)((pModal->antCtrlCommon >> 8) & 0xF);
1003 antWrites[6] = (u16)((pModal->antCtrlCommon >> 4) & 0xF);
1004 antWrites[7] = (u16)(pModal->antCtrlCommon & 0xF);
1005
1006 offset_num = 8;
1007
1008 for (i = 0, j = offset_num; i < AR9287_MAX_CHAINS; i++) {
1009 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 28) & 0xf);
1010 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 10) & 0x3);
1011 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 8) & 0x3);
1012 antWrites[j++] = 0;
1013 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 6) & 0x3);
1014 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 4) & 0x3);
1015 antWrites[j++] = (u16)((pModal->antCtrlChain[i] >> 2) & 0x3);
1016 antWrites[j++] = (u16)(pModal->antCtrlChain[i] & 0x3);
1017 }
1018
1019 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1020 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1021
1022 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
1023 regChainOffset = i * 0x1000;
1024
1025 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1026 pModal->antCtrlChain[i]);
1027
1028 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1029 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
1030 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1031 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1032 SM(pModal->iqCalICh[i],
1033 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1034 SM(pModal->iqCalQCh[i],
1035 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1036
1037 txRxAttenLocal = pModal->txRxAttenCh[i];
1038
1039 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1040 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1041 pModal->bswMargin[i]);
1042 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1043 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1044 pModal->bswAtten[i]);
1045 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1046 AR9280_PHY_RXGAIN_TXRX_ATTEN,
1047 txRxAttenLocal);
1048 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1049 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1050 pModal->rxTxMarginCh[i]);
1051 }
1052
1053
1054 if (IS_CHAN_HT40(chan))
1055 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1056 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
1057 else
1058 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1059 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
1060
1061 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1062 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
1063
1064 REG_WRITE(ah, AR_PHY_RF_CTL4,
1065 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1066 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1067 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1068 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1069
1070 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
1071 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
1072
1073 REG_RMW_FIELD(ah, AR_PHY_CCA,
1074 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
1075 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1076 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
1077
79d7f4bc
S		 1078 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
1079 regval &= ~(AR9287_AN_RF2G3_DB1 |
1080 AR9287_AN_RF2G3_DB2 |
1081 AR9287_AN_RF2G3_OB_CCK |
1082 AR9287_AN_RF2G3_OB_PSK |
1083 AR9287_AN_RF2G3_OB_QAM |
1084 AR9287_AN_RF2G3_OB_PAL_OFF);
1085 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1086 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1087 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1088 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1089 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1090 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1091
1092 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
1093
1094 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
1095 regval &= ~(AR9287_AN_RF2G3_DB1 |
1096 AR9287_AN_RF2G3_DB2 |
1097 AR9287_AN_RF2G3_OB_CCK |
1098 AR9287_AN_RF2G3_OB_PSK |
1099 AR9287_AN_RF2G3_OB_QAM |
1100 AR9287_AN_RF2G3_OB_PAL_OFF);
1101 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
1102 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
1103 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
1104 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
1105 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
1106 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
1107
1108 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
b5aec950
S		 1109
1110 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1111 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
1112 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1113 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
1114
1115 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
1116 AR9287_AN_TOP2_XPABIAS_LVL,
1117 AR9287_AN_TOP2_XPABIAS_LVL_S,
1118 pModal->xpaBiasLvl);
1119}
1120
16c94ac6 1121static u8 ath9k_hw_ar9287_get_num_ant_config(struct ath_hw *ah,
b5aec950
S		 1122 enum ieee80211_band freq_band)
1123{
1124 return 1;
1125}
1126
16c94ac6 1127static u16 ath9k_hw_ar9287_get_eeprom_antenna_cfg(struct ath_hw *ah,
b5aec950
S		 1128 struct ath9k_channel *chan)
1129{
1130 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
1131 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
1132
1133 return pModal->antCtrlCommon & 0xFFFF;
1134}
1135
16c94ac6 1136static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
b5aec950
S		 1137 u16 i, bool is2GHz)
1138{
1139#define EEP_MAP9287_SPURCHAN \
1140 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
16c94ac6 1141
c46917bb 1142 struct ath_common *common = ath9k_hw_common(ah);
b5aec950
S		 1143 u16 spur_val = AR_NO_SPUR;
1144
c46917bb
LR		 1145 ath_print(common, ATH_DBG_ANI,
1146 "Getting spur idx %d is2Ghz. %d val %x\n",
1147 i, is2GHz, ah->config.spurchans[i][is2GHz]);
b5aec950
S		 1148
1149 switch (ah->config.spurmode) {
1150 case SPUR_DISABLE:
1151 break;
1152 case SPUR_ENABLE_IOCTL:
1153 spur_val = ah->config.spurchans[i][is2GHz];
c46917bb
LR		 1154 ath_print(common, ATH_DBG_ANI,
1155 "Getting spur val from new loc. %d\n", spur_val);
b5aec950
S		 1156 break;
1157 case SPUR_ENABLE_EEPROM:
1158 spur_val = EEP_MAP9287_SPURCHAN;
1159 break;
1160 }
1161
1162 return spur_val;
1163
1164#undef EEP_MAP9287_SPURCHAN
1165}
1166
0b8f6f2b 1167const struct eeprom_ops eep_ar9287_ops = {
16c94ac6
S		 1168 .check_eeprom = ath9k_hw_ar9287_check_eeprom,
1169 .get_eeprom = ath9k_hw_ar9287_get_eeprom,
1170 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
1171 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
1172 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
1173 .get_num_ant_config = ath9k_hw_ar9287_get_num_ant_config,
1174 .get_eeprom_antenna_cfg = ath9k_hw_ar9287_get_eeprom_antenna_cfg,
1175 .set_board_values = ath9k_hw_ar9287_set_board_values,
1176 .set_addac = ath9k_hw_ar9287_set_addac,
1177 .set_txpower = ath9k_hw_ar9287_set_txpower,
1178 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel
b5aec950 1179};
Clone of davem's net-next-2.6 tree