[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / debug.h

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef DEBUG_H
#define DEBUG_H

#include "hw.h"
#include "rc.h"

struct ath_txq;
struct ath_buf;

#ifdef CONFIG_ATH9K_DEBUGFS
#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
#else
#define TX_STAT_INC(q, c) do { } while (0)
#endif

#ifdef CONFIG_ATH9K_DEBUGFS

/**
 * struct ath_interrupt_stats - Contains statistics about interrupts
 * @total: Total no. of interrupts generated so far
 * @rxok: RX with no errors
 * @rxlp: RX with low priority RX
 * @rxhp: RX with high priority, uapsd only
 * @rxeol: RX with no more RXDESC available
 * @rxorn: RX FIFO overrun
 * @txok: TX completed at the requested rate
 * @txurn: TX FIFO underrun
 * @mib: MIB regs reaching its threshold
 * @rxphyerr: RX with phy errors
 * @rx_keycache_miss: RX with key cache misses
 * @swba: Software Beacon Alert
 * @bmiss: Beacon Miss
 * @bnr: Beacon Not Ready
 * @cst: Carrier Sense TImeout
 * @gtt: Global TX Timeout
 * @tim: RX beacon TIM occurrence
 * @cabend: RX End of CAB traffic
 * @dtimsync: DTIM sync lossage
 * @dtim: RX Beacon with DTIM
 * @bb_watchdog: Baseband watchdog
 */
struct ath_interrupt_stats {
	u32 total;
	u32 rxok;
	u32 rxlp;
	u32 rxhp;
	u32 rxeol;
	u32 rxorn;
	u32 txok;
	u32 txeol;
	u32 txurn;
	u32 mib;
	u32 rxphyerr;
	u32 rx_keycache_miss;
	u32 swba;
	u32 bmiss;
	u32 bnr;
	u32 cst;
	u32 gtt;
	u32 tim;
	u32 cabend;
	u32 dtimsync;
	u32 dtim;
	u32 bb_watchdog;
};

struct ath_rc_stats {
	u32 success;
	u32 retries;
	u32 xretries;
	u8 per;
};

/**
 * struct ath_tx_stats - Statistics about TX
 * @queued: Total MPDUs (non-aggr) queued
 * @completed: Total MPDUs (non-aggr) completed
 * @a_aggr: Total no. of aggregates queued
 * @a_queued: Total AMPDUs queued
 * @a_completed: Total AMPDUs completed
 * @a_retries: No. of AMPDUs retried (SW)
 * @a_xretries: No. of AMPDUs dropped due to xretries
 * @fifo_underrun: FIFO underrun occurrences
	Valid only for:
		- non-aggregate condition.
		- first packet of aggregate.
 * @xtxop: No. of frames filtered because of TXOP limit
 * @timer_exp: Transmit timer expiry
 * @desc_cfg_err: Descriptor configuration errors
 * @data_urn: TX data underrun errors
 * @delim_urn: TX delimiter underrun errors
 */
struct ath_tx_stats {
	u32 queued;
	u32 completed;
	u32 a_aggr;
	u32 a_queued;
	u32 a_completed;
	u32 a_retries;
	u32 a_xretries;
	u32 fifo_underrun;
	u32 xtxop;
	u32 timer_exp;
	u32 desc_cfg_err;
	u32 data_underrun;
	u32 delim_underrun;
};

/**
 * struct ath_rx_stats - RX Statistics
 * @crc_err: No. of frames with incorrect CRC value
 * @decrypt_crc_err: No. of frames whose CRC check failed after
	decryption process completed
 * @phy_err: No. of frames whose reception failed because the PHY
	encountered an error
 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 * @decrypt_busy_err: Decryption interruptions counter
 * @phy_err_stats: Individual PHY error statistics
 */
struct ath_rx_stats {
	u32 crc_err;
	u32 decrypt_crc_err;
	u32 phy_err;
	u32 mic_err;
	u32 pre_delim_crc_err;
	u32 post_delim_crc_err;
	u32 decrypt_busy_err;
	u32 phy_err_stats[ATH9K_PHYERR_MAX];
};

struct ath_stats {
	struct ath_interrupt_stats istats;
	struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
	struct ath_rx_stats rxstats;
};

struct ath9k_debug {
	struct dentry *debugfs_phy;
	u32 regidx;
	struct ath_stats stats;
};

int ath9k_init_debug(struct ath_hw *ah);
void ath9k_exit_debug(struct ath_hw *ah);

int ath9k_debug_create_root(void);
void ath9k_debug_remove_root(void);
void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
void ath_debug_stat_rc(struct ath_softc *sc, int final_rate);
void ath_debug_stat_tx(struct ath_softc *sc, struct ath_txq *txq,
		       struct ath_buf *bf, struct ath_tx_status *ts);
void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
void ath_debug_stat_retries(struct ath_softc *sc, int rix,
			    int xretries, int retries, u8 per);

#else

static inline int ath9k_init_debug(struct ath_hw *ah)
{
	return 0;
}

static inline void ath9k_exit_debug(struct ath_hw *ah)
{
}

static inline int ath9k_debug_create_root(void)
{
	return 0;
}

static inline void ath9k_debug_remove_root(void)
{
}

static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
					    enum ath9k_int status)
{
}

static inline void ath_debug_stat_rc(struct ath_softc *sc,
				     int final_rate)
{
}

static inline void ath_debug_stat_tx(struct ath_softc *sc,
				     struct ath_txq *txq,
				     struct ath_buf *bf,
				     struct ath_tx_status *ts)
{
}

static inline void ath_debug_stat_rx(struct ath_softc *sc,
				     struct ath_rx_status *rs)
{
}

static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
					  int xretries, int retries, u8 per)
{
}

#endif /* CONFIG_ATH9K_DEBUGFS */

#endif /* DEBUG_H */
Commit	Line	Data
394cf0a1	1	/*
cee075a2	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
394cf0a1 S	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef DEBUG_H
	18	#define DEBUG_H
	19
4d6b228d	20	#include "hw.h"
545750d3	21	#include "rc.h"
4d6b228d	22
fec247c0 S	23	struct ath_txq;
	24	struct ath_buf;
	25
a830df07	26	#ifdef CONFIG_ATH9K_DEBUGFS
fec247c0 S	27	#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
	28	#else
	29	#define TX_STAT_INC(q, c) do { } while (0)
	30	#endif
	31
a830df07	32	#ifdef CONFIG_ATH9K_DEBUGFS
394cf0a1 S	33
	34	/**
	35	* struct ath_interrupt_stats - Contains statistics about interrupts
	36	* @total: Total no. of interrupts generated so far
	37	* @rxok: RX with no errors
a9616f41 LR	38	* @rxlp: RX with low priority RX
a9616f41 LR	39	* @rxhp: RX with high priority, uapsd only
394cf0a1 S	40	* @rxeol: RX with no more RXDESC available
	41	* @rxorn: RX FIFO overrun
	42	* @txok: TX completed at the requested rate
	43	* @txurn: TX FIFO underrun
	44	* @mib: MIB regs reaching its threshold
	45	* @rxphyerr: RX with phy errors
	46	* @rx_keycache_miss: RX with key cache misses
	47	* @swba: Software Beacon Alert
	48	* @bmiss: Beacon Miss
	49	* @bnr: Beacon Not Ready
	50	* @cst: Carrier Sense TImeout
	51	* @gtt: Global TX Timeout
	52	* @tim: RX beacon TIM occurrence
	53	* @cabend: RX End of CAB traffic
	54	* @dtimsync: DTIM sync lossage
	55	* @dtim: RX Beacon with DTIM
08578b8f	56	* @bb_watchdog: Baseband watchdog
394cf0a1 S	57	*/
	58	struct ath_interrupt_stats {
	59	u32 total;
	60	u32 rxok;
a9616f41 LR	61	u32 rxlp;
a9616f41 LR	62	u32 rxhp;
394cf0a1 S	63	u32 rxeol;
	64	u32 rxorn;
	65	u32 txok;
	66	u32 txeol;
	67	u32 txurn;
	68	u32 mib;
	69	u32 rxphyerr;
	70	u32 rx_keycache_miss;
	71	u32 swba;
	72	u32 bmiss;
	73	u32 bnr;
	74	u32 cst;
	75	u32 gtt;
	76	u32 tim;
	77	u32 cabend;
	78	u32 dtimsync;
	79	u32 dtim;
08578b8f	80	u32 bb_watchdog;
394cf0a1 S	81	};
394cf0a1 S	82
bedf087a	83	struct ath_rc_stats {
394cf0a1 S	84	u32 success;
	85	u32 retries;
	86	u32 xretries;
9e712790	87	u8 per;
394cf0a1 S	88	};
394cf0a1 S	89
fec247c0 S	90	/**
	91	* struct ath_tx_stats - Statistics about TX
	92	* @queued: Total MPDUs (non-aggr) queued
	93	* @completed: Total MPDUs (non-aggr) completed
	94	* @a_aggr: Total no. of aggregates queued
	95	* @a_queued: Total AMPDUs queued
	96	* @a_completed: Total AMPDUs completed
	97	* @a_retries: No. of AMPDUs retried (SW)
	98	* @a_xretries: No. of AMPDUs dropped due to xretries
	99	* @fifo_underrun: FIFO underrun occurrences
	100	Valid only for:
	101	- non-aggregate condition.
	102	- first packet of aggregate.
	103	* @xtxop: No. of frames filtered because of TXOP limit
	104	* @timer_exp: Transmit timer expiry
	105	* @desc_cfg_err: Descriptor configuration errors
	106	* @data_urn: TX data underrun errors
	107	* @delim_urn: TX delimiter underrun errors
	108	*/
	109	struct ath_tx_stats {
	110	u32 queued;
	111	u32 completed;
	112	u32 a_aggr;
	113	u32 a_queued;
	114	u32 a_completed;
	115	u32 a_retries;
	116	u32 a_xretries;
	117	u32 fifo_underrun;
	118	u32 xtxop;
	119	u32 timer_exp;
	120	u32 desc_cfg_err;
	121	u32 data_underrun;
	122	u32 delim_underrun;
	123	};
	124
1395d3f0 S	125	/**
	126	* struct ath_rx_stats - RX Statistics
	127	* @crc_err: No. of frames with incorrect CRC value
	128	* @decrypt_crc_err: No. of frames whose CRC check failed after
	129	decryption process completed
	130	* @phy_err: No. of frames whose reception failed because the PHY
	131	encountered an error
	132	* @mic_err: No. of frames with incorrect TKIP MIC verification failure
	133	* @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
	134	* @post_delim_crc_err: Post-Frame delimiter CRC error detections
	135	* @decrypt_busy_err: Decryption interruptions counter
	136	* @phy_err_stats: Individual PHY error statistics
	137	*/
	138	struct ath_rx_stats {
	139	u32 crc_err;
	140	u32 decrypt_crc_err;
	141	u32 phy_err;
	142	u32 mic_err;
	143	u32 pre_delim_crc_err;
	144	u32 post_delim_crc_err;
	145	u32 decrypt_busy_err;
	146	u32 phy_err_stats[ATH9K_PHYERR_MAX];
	147	};
	148
394cf0a1 S	149	struct ath_stats {
394cf0a1 S	150	struct ath_interrupt_stats istats;
bedf087a	151	struct ath_rc_stats rcstats[RATE_TABLE_SIZE];
fec247c0	152	struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
1395d3f0	153	struct ath_rx_stats rxstats;
394cf0a1 S	154	};
	155
	156	struct ath9k_debug {
394cf0a1	157	struct dentry *debugfs_phy;
9bff0bc4	158	u32 regidx;
394cf0a1 S	159	struct ath_stats stats;
	160	};
	161
4d6b228d LR	162	int ath9k_init_debug(struct ath_hw *ah);
	163	void ath9k_exit_debug(struct ath_hw *ah);
	164
19d8bc22 GJ	165	int ath9k_debug_create_root(void);
19d8bc22 GJ	166	void ath9k_debug_remove_root(void);
394cf0a1	167	void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
545750d3	168	void ath_debug_stat_rc(struct ath_softc *sc, int final_rate);
fec247c0	169	void ath_debug_stat_tx(struct ath_softc sc, struct ath_txq txq,
db1a052b	170	struct ath_buf bf, struct ath_tx_status ts);
8e6f5aa2	171	void ath_debug_stat_rx(struct ath_softc sc, struct ath_rx_status rs);
394cf0a1	172	void ath_debug_stat_retries(struct ath_softc *sc, int rix,
9e712790	173	int xretries, int retries, u8 per);
394cf0a1 S	174
	175	#else
	176
4d6b228d	177	static inline int ath9k_init_debug(struct ath_hw *ah)
394cf0a1 S	178	{
	179	return 0;
	180	}
	181
4d6b228d	182	static inline void ath9k_exit_debug(struct ath_hw *ah)
394cf0a1 S	183	{
	184	}
	185
19d8bc22 GJ	186	static inline int ath9k_debug_create_root(void)
	187	{
	188	return 0;
	189	}
	190
	191	static inline void ath9k_debug_remove_root(void)
	192	{
	193	}
	194
394cf0a1 S	195	static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
	196	enum ath9k_int status)
	197	{
	198	}
	199
	200	static inline void ath_debug_stat_rc(struct ath_softc *sc,
545750d3	201	int final_rate)
394cf0a1 S	202	{
	203	}
	204
fec247c0 S	205	static inline void ath_debug_stat_tx(struct ath_softc *sc,
fec247c0 S	206	struct ath_txq *txq,
32ffb1f4 FF	207	struct ath_buf *bf,
32ffb1f4 FF	208	struct ath_tx_status *ts)
fec247c0 S	209	{
	210	}
	211
1395d3f0	212	static inline void ath_debug_stat_rx(struct ath_softc *sc,
32ffb1f4	213	struct ath_rx_status *rs)
1395d3f0 S	214	{
	215	}
	216
394cf0a1	217	static inline void ath_debug_stat_retries(struct ath_softc *sc, int rix,
9e712790	218	int xretries, int retries, u8 per)
394cf0a1 S	219	{
	220	}
	221
a830df07	222	#endif /* CONFIG_ATH9K_DEBUGFS */
394cf0a1 S	223
394cf0a1 S	224	#endif /* DEBUG_H */