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Commit | Line | Data |
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f078f209 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
f078f209 LR |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ATH9K_H | |
18 | #define ATH9K_H | |
19 | ||
394cf0a1 S |
20 | #include <linux/etherdevice.h> |
21 | #include <linux/device.h> | |
394cf0a1 | 22 | #include <linux/leds.h> |
9f42c2b6 | 23 | #include <linux/completion.h> |
394cf0a1 | 24 | |
394cf0a1 | 25 | #include "debug.h" |
db86f07e LR |
26 | #include "common.h" |
27 | ||
28 | /* | |
29 | * Header for the ath9k.ko driver core *only* -- hw code nor any other driver | |
30 | * should rely on this file or its contents. | |
31 | */ | |
394cf0a1 S |
32 | |
33 | struct ath_node; | |
34 | ||
35 | /* Macro to expand scalars to 64-bit objects */ | |
36 | ||
13bda122 | 37 | #define ito64(x) (sizeof(x) == 1) ? \ |
394cf0a1 | 38 | (((unsigned long long int)(x)) & (0xff)) : \ |
13bda122 | 39 | (sizeof(x) == 2) ? \ |
394cf0a1 | 40 | (((unsigned long long int)(x)) & 0xffff) : \ |
13bda122 | 41 | ((sizeof(x) == 4) ? \ |
394cf0a1 S |
42 | (((unsigned long long int)(x)) & 0xffffffff) : \ |
43 | (unsigned long long int)(x)) | |
44 | ||
45 | /* increment with wrap-around */ | |
46 | #define INCR(_l, _sz) do { \ | |
47 | (_l)++; \ | |
48 | (_l) &= ((_sz) - 1); \ | |
49 | } while (0) | |
50 | ||
51 | /* decrement with wrap-around */ | |
52 | #define DECR(_l, _sz) do { \ | |
53 | (_l)--; \ | |
54 | (_l) &= ((_sz) - 1); \ | |
55 | } while (0) | |
56 | ||
57 | #define A_MAX(a, b) ((a) > (b) ? (a) : (b)) | |
58 | ||
394cf0a1 S |
59 | #define TSF_TO_TU(_h,_l) \ |
60 | ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10)) | |
61 | ||
62 | #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i)) | |
63 | ||
394cf0a1 S |
64 | struct ath_config { |
65 | u32 ath_aggr_prot; | |
66 | u16 txpowlimit; | |
67 | u8 cabqReadytime; | |
394cf0a1 S |
68 | }; |
69 | ||
70 | /*************************/ | |
71 | /* Descriptor Management */ | |
72 | /*************************/ | |
73 | ||
74 | #define ATH_TXBUF_RESET(_bf) do { \ | |
a119cc49 | 75 | (_bf)->bf_stale = false; \ |
394cf0a1 S |
76 | (_bf)->bf_lastbf = NULL; \ |
77 | (_bf)->bf_next = NULL; \ | |
78 | memset(&((_bf)->bf_state), 0, \ | |
79 | sizeof(struct ath_buf_state)); \ | |
80 | } while (0) | |
81 | ||
a119cc49 S |
82 | #define ATH_RXBUF_RESET(_bf) do { \ |
83 | (_bf)->bf_stale = false; \ | |
84 | } while (0) | |
85 | ||
394cf0a1 S |
86 | /** |
87 | * enum buffer_type - Buffer type flags | |
88 | * | |
89 | * @BUF_HT: Send this buffer using HT capabilities | |
90 | * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX) | |
91 | * @BUF_AGGR: Indicates whether the buffer can be aggregated | |
92 | * (used in aggregation scheduling) | |
93 | * @BUF_RETRY: Indicates whether the buffer is retried | |
94 | * @BUF_XRETRY: To denote excessive retries of the buffer | |
95 | */ | |
96 | enum buffer_type { | |
97 | BUF_HT = BIT(1), | |
98 | BUF_AMPDU = BIT(2), | |
99 | BUF_AGGR = BIT(3), | |
100 | BUF_RETRY = BIT(4), | |
101 | BUF_XRETRY = BIT(5), | |
102 | }; | |
103 | ||
394cf0a1 S |
104 | #define bf_nframes bf_state.bfs_nframes |
105 | #define bf_al bf_state.bfs_al | |
106 | #define bf_frmlen bf_state.bfs_frmlen | |
107 | #define bf_retries bf_state.bfs_retries | |
108 | #define bf_seqno bf_state.bfs_seqno | |
109 | #define bf_tidno bf_state.bfs_tidno | |
110 | #define bf_keyix bf_state.bfs_keyix | |
111 | #define bf_keytype bf_state.bfs_keytype | |
112 | #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT) | |
113 | #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU) | |
114 | #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR) | |
115 | #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY) | |
116 | #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY) | |
f078f209 | 117 | |
5088c2f1 VT |
118 | #define ATH_TXSTATUS_RING_SIZE 64 |
119 | ||
394cf0a1 | 120 | struct ath_descdma { |
5088c2f1 | 121 | void *dd_desc; |
17d7904d S |
122 | dma_addr_t dd_desc_paddr; |
123 | u32 dd_desc_len; | |
124 | struct ath_buf *dd_bufptr; | |
394cf0a1 S |
125 | }; |
126 | ||
127 | int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd, | |
128 | struct list_head *head, const char *name, | |
4adfcded | 129 | int nbuf, int ndesc, bool is_tx); |
394cf0a1 S |
130 | void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd, |
131 | struct list_head *head); | |
132 | ||
133 | /***********/ | |
134 | /* RX / TX */ | |
135 | /***********/ | |
136 | ||
137 | #define ATH_MAX_ANTENNA 3 | |
138 | #define ATH_RXBUF 512 | |
394cf0a1 | 139 | #define ATH_TXBUF 512 |
84642d6b FF |
140 | #define ATH_TXBUF_RESERVE 5 |
141 | #define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE) | |
394cf0a1 | 142 | #define ATH_TXMAXTRY 13 |
394cf0a1 | 143 | #define ATH_MGT_TXMAXTRY 4 |
394cf0a1 S |
144 | |
145 | #define TID_TO_WME_AC(_tid) \ | |
146 | ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \ | |
147 | (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \ | |
148 | (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \ | |
149 | WME_AC_VO) | |
150 | ||
394cf0a1 S |
151 | #define ADDBA_EXCHANGE_ATTEMPTS 10 |
152 | #define ATH_AGGR_DELIM_SZ 4 | |
153 | #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */ | |
154 | /* number of delimiters for encryption padding */ | |
155 | #define ATH_AGGR_ENCRYPTDELIM 10 | |
156 | /* minimum h/w qdepth to be sustained to maximize aggregation */ | |
157 | #define ATH_AGGR_MIN_QDEPTH 2 | |
158 | #define ATH_AMPDU_SUBFRAME_DEFAULT 32 | |
394cf0a1 S |
159 | |
160 | #define IEEE80211_SEQ_SEQ_SHIFT 4 | |
161 | #define IEEE80211_SEQ_MAX 4096 | |
394cf0a1 S |
162 | #define IEEE80211_WEP_IVLEN 3 |
163 | #define IEEE80211_WEP_KIDLEN 1 | |
164 | #define IEEE80211_WEP_CRCLEN 4 | |
165 | #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \ | |
166 | (IEEE80211_WEP_IVLEN + \ | |
167 | IEEE80211_WEP_KIDLEN + \ | |
168 | IEEE80211_WEP_CRCLEN)) | |
169 | ||
170 | /* return whether a bit at index _n in bitmap _bm is set | |
171 | * _sz is the size of the bitmap */ | |
172 | #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \ | |
173 | ((_bm)[(_n) >> 5] & (1 << ((_n) & 31)))) | |
174 | ||
175 | /* return block-ack bitmap index given sequence and starting sequence */ | |
176 | #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1)) | |
177 | ||
178 | /* returns delimiter padding required given the packet length */ | |
179 | #define ATH_AGGR_GET_NDELIM(_len) \ | |
180 | (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \ | |
181 | (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2) | |
182 | ||
183 | #define BAW_WITHIN(_start, _bawsz, _seqno) \ | |
184 | ((((_seqno) - (_start)) & 4095) < (_bawsz)) | |
185 | ||
394cf0a1 S |
186 | #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)]) |
187 | ||
164ace38 SB |
188 | #define ATH_TX_COMPLETE_POLL_INT 1000 |
189 | ||
394cf0a1 S |
190 | enum ATH_AGGR_STATUS { |
191 | ATH_AGGR_DONE, | |
192 | ATH_AGGR_BAW_CLOSED, | |
193 | ATH_AGGR_LIMITED, | |
194 | }; | |
195 | ||
e5003249 | 196 | #define ATH_TXFIFO_DEPTH 8 |
394cf0a1 | 197 | struct ath_txq { |
293f2ba8 | 198 | int axq_class; |
17d7904d S |
199 | u32 axq_qnum; |
200 | u32 *axq_link; | |
201 | struct list_head axq_q; | |
394cf0a1 | 202 | spinlock_t axq_lock; |
17d7904d | 203 | u32 axq_depth; |
17d7904d | 204 | bool stopped; |
164ace38 | 205 | bool axq_tx_inprogress; |
394cf0a1 | 206 | struct list_head axq_acq; |
e5003249 VT |
207 | struct list_head txq_fifo[ATH_TXFIFO_DEPTH]; |
208 | struct list_head txq_fifo_pending; | |
209 | u8 txq_headidx; | |
210 | u8 txq_tailidx; | |
394cf0a1 S |
211 | }; |
212 | ||
93ef24b2 S |
213 | struct ath_atx_ac { |
214 | int sched; | |
215 | int qnum; | |
216 | struct list_head list; | |
217 | struct list_head tid_q; | |
218 | }; | |
219 | ||
220 | struct ath_buf_state { | |
221 | int bfs_nframes; | |
222 | u16 bfs_al; | |
223 | u16 bfs_frmlen; | |
224 | int bfs_seqno; | |
225 | int bfs_tidno; | |
226 | int bfs_retries; | |
227 | u8 bf_type; | |
9f42c2b6 | 228 | u8 bfs_paprd; |
ca369eb4 | 229 | unsigned long bfs_paprd_timestamp; |
93ef24b2 S |
230 | u32 bfs_keyix; |
231 | enum ath9k_key_type bfs_keytype; | |
232 | }; | |
233 | ||
234 | struct ath_buf { | |
235 | struct list_head list; | |
236 | struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or | |
237 | an aggregate) */ | |
238 | struct ath_buf *bf_next; /* next subframe in the aggregate */ | |
239 | struct sk_buff *bf_mpdu; /* enclosing frame structure */ | |
240 | void *bf_desc; /* virtual addr of desc */ | |
241 | dma_addr_t bf_daddr; /* physical addr of desc */ | |
c1739eb3 | 242 | dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */ |
93ef24b2 | 243 | bool bf_stale; |
93ef24b2 S |
244 | bool bf_tx_aborted; |
245 | u16 bf_flags; | |
246 | struct ath_buf_state bf_state; | |
93ef24b2 S |
247 | struct ath_wiphy *aphy; |
248 | }; | |
249 | ||
250 | struct ath_atx_tid { | |
251 | struct list_head list; | |
252 | struct list_head buf_q; | |
253 | struct ath_node *an; | |
254 | struct ath_atx_ac *ac; | |
81ee13ba | 255 | unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)]; |
93ef24b2 S |
256 | u16 seq_start; |
257 | u16 seq_next; | |
258 | u16 baw_size; | |
259 | int tidno; | |
260 | int baw_head; /* first un-acked tx buffer */ | |
261 | int baw_tail; /* next unused tx buffer slot */ | |
262 | int sched; | |
263 | int paused; | |
264 | u8 state; | |
265 | }; | |
266 | ||
267 | struct ath_node { | |
268 | struct ath_common *common; | |
269 | struct ath_atx_tid tid[WME_NUM_TID]; | |
270 | struct ath_atx_ac ac[WME_NUM_AC]; | |
271 | u16 maxampdu; | |
272 | u8 mpdudensity; | |
93ef24b2 S |
273 | }; |
274 | ||
394cf0a1 S |
275 | #define AGGR_CLEANUP BIT(1) |
276 | #define AGGR_ADDBA_COMPLETE BIT(2) | |
277 | #define AGGR_ADDBA_PROGRESS BIT(3) | |
278 | ||
394cf0a1 S |
279 | struct ath_tx_control { |
280 | struct ath_txq *txq; | |
281 | int if_id; | |
f0ed85c6 | 282 | enum ath9k_internal_frame_type frame_type; |
9f42c2b6 | 283 | u8 paprd; |
394cf0a1 S |
284 | }; |
285 | ||
394cf0a1 S |
286 | #define ATH_TX_ERROR 0x01 |
287 | #define ATH_TX_XRETRY 0x02 | |
288 | #define ATH_TX_BAR 0x04 | |
394cf0a1 | 289 | |
394cf0a1 S |
290 | struct ath_tx { |
291 | u16 seq_no; | |
292 | u32 txqsetup; | |
1d2231e2 | 293 | int hwq_map[WME_NUM_AC]; |
394cf0a1 S |
294 | spinlock_t txbuflock; |
295 | struct list_head txbuf; | |
296 | struct ath_txq txq[ATH9K_NUM_TX_QUEUES]; | |
297 | struct ath_descdma txdma; | |
97923b14 | 298 | int pending_frames[WME_NUM_AC]; |
394cf0a1 S |
299 | }; |
300 | ||
b5c80475 FF |
301 | struct ath_rx_edma { |
302 | struct sk_buff_head rx_fifo; | |
303 | struct sk_buff_head rx_buffers; | |
304 | u32 rx_fifo_hwsize; | |
305 | }; | |
306 | ||
394cf0a1 S |
307 | struct ath_rx { |
308 | u8 defant; | |
309 | u8 rxotherant; | |
310 | u32 *rxlink; | |
394cf0a1 | 311 | unsigned int rxfilter; |
b79b33c4 | 312 | spinlock_t pcu_lock; |
394cf0a1 S |
313 | spinlock_t rxbuflock; |
314 | struct list_head rxbuf; | |
315 | struct ath_descdma rxdma; | |
b5c80475 FF |
316 | struct ath_buf *rx_bufptr; |
317 | struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX]; | |
394cf0a1 S |
318 | }; |
319 | ||
320 | int ath_startrecv(struct ath_softc *sc); | |
321 | bool ath_stoprecv(struct ath_softc *sc); | |
322 | void ath_flushrecv(struct ath_softc *sc); | |
323 | u32 ath_calcrxfilter(struct ath_softc *sc); | |
324 | int ath_rx_init(struct ath_softc *sc, int nbufs); | |
325 | void ath_rx_cleanup(struct ath_softc *sc); | |
b5c80475 | 326 | int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp); |
394cf0a1 S |
327 | struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype); |
328 | void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq); | |
329 | int ath_tx_setup(struct ath_softc *sc, int haltype); | |
330 | void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx); | |
331 | void ath_draintxq(struct ath_softc *sc, | |
332 | struct ath_txq *txq, bool retry_tx); | |
333 | void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an); | |
334 | void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an); | |
335 | void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq); | |
336 | int ath_tx_init(struct ath_softc *sc, int nbufs); | |
797fe5cb | 337 | void ath_tx_cleanup(struct ath_softc *sc); |
394cf0a1 S |
338 | int ath_txq_update(struct ath_softc *sc, int qnum, |
339 | struct ath9k_tx_queue_info *q); | |
c52f33d0 | 340 | int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb, |
394cf0a1 S |
341 | struct ath_tx_control *txctl); |
342 | void ath_tx_tasklet(struct ath_softc *sc); | |
e5003249 | 343 | void ath_tx_edma_tasklet(struct ath_softc *sc); |
c52f33d0 | 344 | void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb); |
231c3a1f FF |
345 | int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta, |
346 | u16 tid, u16 *ssn); | |
f83da965 | 347 | void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
394cf0a1 S |
348 | void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid); |
349 | ||
350 | /********/ | |
17d7904d | 351 | /* VIFs */ |
394cf0a1 | 352 | /********/ |
f078f209 | 353 | |
17d7904d | 354 | struct ath_vif { |
394cf0a1 | 355 | int av_bslot; |
4ed96f04 | 356 | __le64 tsf_adjust; /* TSF adjustment for staggered beacons */ |
394cf0a1 S |
357 | enum nl80211_iftype av_opmode; |
358 | struct ath_buf *av_bcbuf; | |
359 | struct ath_tx_control av_btxctl; | |
f0ed85c6 | 360 | u8 bssid[ETH_ALEN]; /* current BSSID from config_interface */ |
f078f209 LR |
361 | }; |
362 | ||
394cf0a1 S |
363 | /*******************/ |
364 | /* Beacon Handling */ | |
365 | /*******************/ | |
f078f209 | 366 | |
394cf0a1 S |
367 | /* |
368 | * Regardless of the number of beacons we stagger, (i.e. regardless of the | |
369 | * number of BSSIDs) if a given beacon does not go out even after waiting this | |
370 | * number of beacon intervals, the game's up. | |
371 | */ | |
372 | #define BSTUCK_THRESH (9 * ATH_BCBUF) | |
4ed96f04 | 373 | #define ATH_BCBUF 4 |
394cf0a1 S |
374 | #define ATH_DEFAULT_BINTVAL 100 /* TU */ |
375 | #define ATH_DEFAULT_BMISS_LIMIT 10 | |
376 | #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024) | |
377 | ||
378 | struct ath_beacon_config { | |
379 | u16 beacon_interval; | |
380 | u16 listen_interval; | |
381 | u16 dtim_period; | |
382 | u16 bmiss_timeout; | |
383 | u8 dtim_count; | |
394cf0a1 S |
384 | }; |
385 | ||
386 | struct ath_beacon { | |
387 | enum { | |
388 | OK, /* no change needed */ | |
389 | UPDATE, /* update pending */ | |
390 | COMMIT /* beacon sent, commit change */ | |
391 | } updateslot; /* slot time update fsm */ | |
392 | ||
393 | u32 beaconq; | |
394 | u32 bmisscnt; | |
395 | u32 ast_be_xmit; | |
396 | u64 bc_tstamp; | |
2c3db3d5 | 397 | struct ieee80211_vif *bslot[ATH_BCBUF]; |
c52f33d0 | 398 | struct ath_wiphy *bslot_aphy[ATH_BCBUF]; |
394cf0a1 S |
399 | int slottime; |
400 | int slotupdate; | |
401 | struct ath9k_tx_queue_info beacon_qi; | |
402 | struct ath_descdma bdma; | |
403 | struct ath_txq *cabq; | |
404 | struct list_head bbuf; | |
405 | }; | |
406 | ||
9fc9ab0a | 407 | void ath_beacon_tasklet(unsigned long data); |
2c3db3d5 | 408 | void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif); |
c52f33d0 | 409 | int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif); |
17d7904d | 410 | void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp); |
94db2936 | 411 | int ath_beaconq_config(struct ath_softc *sc); |
394cf0a1 S |
412 | |
413 | /*******/ | |
414 | /* ANI */ | |
415 | /*******/ | |
f078f209 | 416 | |
20977d3e S |
417 | #define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */ |
418 | #define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */ | |
e36b27af LR |
419 | #define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */ |
420 | #define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */ | |
6044474e | 421 | #define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */ |
20977d3e S |
422 | #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */ |
423 | #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */ | |
f078f209 | 424 | |
ca369eb4 VT |
425 | #define ATH_PAPRD_TIMEOUT 100 /* msecs */ |
426 | ||
347809fc | 427 | void ath_hw_check(struct work_struct *work); |
9f42c2b6 | 428 | void ath_paprd_calibrate(struct work_struct *work); |
55624204 S |
429 | void ath_ani_calibrate(unsigned long data); |
430 | ||
0fca65c1 S |
431 | /**********/ |
432 | /* BTCOEX */ | |
433 | /**********/ | |
434 | ||
2e20250a LR |
435 | struct ath_btcoex { |
436 | bool hw_timer_enabled; | |
437 | spinlock_t btcoex_lock; | |
438 | struct timer_list period_timer; /* Timer for BT period */ | |
439 | u32 bt_priority_cnt; | |
440 | unsigned long bt_priority_time; | |
e08a6ace | 441 | int bt_stomp_type; /* Types of BT stomping */ |
2e20250a LR |
442 | u32 btcoex_no_stomp; /* in usec */ |
443 | u32 btcoex_period; /* in usec */ | |
58da1318 | 444 | u32 btscan_no_stomp; /* in usec */ |
75d7839f | 445 | struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */ |
2e20250a LR |
446 | }; |
447 | ||
0fca65c1 S |
448 | int ath_init_btcoex_timer(struct ath_softc *sc); |
449 | void ath9k_btcoex_timer_resume(struct ath_softc *sc); | |
450 | void ath9k_btcoex_timer_pause(struct ath_softc *sc); | |
451 | ||
394cf0a1 S |
452 | /********************/ |
453 | /* LED Control */ | |
454 | /********************/ | |
f078f209 | 455 | |
08fc5c1b VN |
456 | #define ATH_LED_PIN_DEF 1 |
457 | #define ATH_LED_PIN_9287 8 | |
394cf0a1 S |
458 | #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */ |
459 | #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */ | |
f078f209 | 460 | |
394cf0a1 S |
461 | enum ath_led_type { |
462 | ATH_LED_RADIO, | |
463 | ATH_LED_ASSOC, | |
464 | ATH_LED_TX, | |
465 | ATH_LED_RX | |
f078f209 LR |
466 | }; |
467 | ||
394cf0a1 S |
468 | struct ath_led { |
469 | struct ath_softc *sc; | |
470 | struct led_classdev led_cdev; | |
471 | enum ath_led_type led_type; | |
472 | char name[32]; | |
473 | bool registered; | |
f078f209 LR |
474 | }; |
475 | ||
0fca65c1 S |
476 | void ath_init_leds(struct ath_softc *sc); |
477 | void ath_deinit_leds(struct ath_softc *sc); | |
478 | ||
102885a5 VT |
479 | /* Antenna diversity/combining */ |
480 | #define ATH_ANT_RX_CURRENT_SHIFT 4 | |
481 | #define ATH_ANT_RX_MAIN_SHIFT 2 | |
482 | #define ATH_ANT_RX_MASK 0x3 | |
483 | ||
484 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50 | |
485 | #define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100 | |
486 | #define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200 | |
487 | #define ATH_ANT_DIV_COMB_INIT_COUNT 95 | |
488 | #define ATH_ANT_DIV_COMB_MAX_COUNT 100 | |
489 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30 | |
490 | #define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20 | |
491 | ||
492 | #define ATH_ANT_DIV_COMB_LNA1_LNA2_DELTA -3 | |
493 | #define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1 | |
494 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4 | |
495 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2 | |
496 | #define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2 | |
497 | ||
498 | enum ath9k_ant_div_comb_lna_conf { | |
499 | ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2, | |
500 | ATH_ANT_DIV_COMB_LNA2, | |
501 | ATH_ANT_DIV_COMB_LNA1, | |
502 | ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2, | |
503 | }; | |
504 | ||
505 | struct ath_ant_comb { | |
506 | u16 count; | |
507 | u16 total_pkt_count; | |
508 | bool scan; | |
509 | bool scan_not_start; | |
510 | int main_total_rssi; | |
511 | int alt_total_rssi; | |
512 | int alt_recv_cnt; | |
513 | int main_recv_cnt; | |
514 | int rssi_lna1; | |
515 | int rssi_lna2; | |
516 | int rssi_add; | |
517 | int rssi_sub; | |
518 | int rssi_first; | |
519 | int rssi_second; | |
520 | int rssi_third; | |
521 | bool alt_good; | |
522 | int quick_scan_cnt; | |
523 | int main_conf; | |
524 | enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf; | |
525 | enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf; | |
526 | int first_bias; | |
527 | int second_bias; | |
528 | bool first_ratio; | |
529 | bool second_ratio; | |
530 | unsigned long scan_start_time; | |
531 | }; | |
532 | ||
394cf0a1 S |
533 | /********************/ |
534 | /* Main driver core */ | |
535 | /********************/ | |
f078f209 | 536 | |
394cf0a1 S |
537 | /* |
538 | * Default cache line size, in bytes. | |
539 | * Used when PCI device not fully initialized by bootrom/BIOS | |
540 | */ | |
541 | #define DEFAULT_CACHELINE 32 | |
394cf0a1 S |
542 | #define ATH_REGCLASSIDS_MAX 10 |
543 | #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */ | |
544 | #define ATH_MAX_SW_RETRIES 10 | |
545 | #define ATH_CHAN_MAX 255 | |
546 | #define IEEE80211_WEP_NKID 4 /* number of key ids */ | |
f1dc5600 | 547 | |
394cf0a1 | 548 | #define ATH_TXPOWER_MAX 100 /* .5 dBm units */ |
394cf0a1 S |
549 | #define ATH_RATE_DUMMY_MARKER 0 |
550 | ||
1b04b930 S |
551 | #define SC_OP_INVALID BIT(0) |
552 | #define SC_OP_BEACONS BIT(1) | |
553 | #define SC_OP_RXAGGR BIT(2) | |
554 | #define SC_OP_TXAGGR BIT(3) | |
5ee08656 | 555 | #define SC_OP_OFFCHANNEL BIT(4) |
1b04b930 S |
556 | #define SC_OP_PREAMBLE_SHORT BIT(5) |
557 | #define SC_OP_PROTECT_ENABLE BIT(6) | |
558 | #define SC_OP_RXFLUSH BIT(7) | |
559 | #define SC_OP_LED_ASSOCIATED BIT(8) | |
560 | #define SC_OP_LED_ON BIT(9) | |
1b04b930 S |
561 | #define SC_OP_TSF_RESET BIT(11) |
562 | #define SC_OP_BT_PRIORITY_DETECTED BIT(12) | |
58da1318 | 563 | #define SC_OP_BT_SCAN BIT(13) |
6c3118e2 | 564 | #define SC_OP_ANI_RUN BIT(14) |
1b04b930 S |
565 | |
566 | /* Powersave flags */ | |
567 | #define PS_WAIT_FOR_BEACON BIT(0) | |
568 | #define PS_WAIT_FOR_CAB BIT(1) | |
569 | #define PS_WAIT_FOR_PSPOLL_DATA BIT(2) | |
570 | #define PS_WAIT_FOR_TX_ACK BIT(3) | |
571 | #define PS_BEACON_SYNC BIT(4) | |
394cf0a1 | 572 | |
bce048d7 | 573 | struct ath_wiphy; |
545750d3 | 574 | struct ath_rate_table; |
bce048d7 | 575 | |
394cf0a1 S |
576 | struct ath_softc { |
577 | struct ieee80211_hw *hw; | |
578 | struct device *dev; | |
c52f33d0 JM |
579 | |
580 | spinlock_t wiphy_lock; /* spinlock to protect ath_wiphy data */ | |
bce048d7 | 581 | struct ath_wiphy *pri_wiphy; |
c52f33d0 JM |
582 | struct ath_wiphy **sec_wiphy; /* secondary wiphys (virtual radios); may |
583 | * have NULL entries */ | |
584 | int num_sec_wiphy; /* number of sec_wiphy pointers in the array */ | |
0e2dedf9 JM |
585 | int chan_idx; |
586 | int chan_is_ht; | |
587 | struct ath_wiphy *next_wiphy; | |
588 | struct work_struct chan_work; | |
7ec3e514 JM |
589 | int wiphy_select_failures; |
590 | unsigned long wiphy_select_first_fail; | |
f98c3bd2 JM |
591 | struct delayed_work wiphy_work; |
592 | unsigned long wiphy_scheduler_int; | |
593 | int wiphy_scheduler_index; | |
3430098a FF |
594 | struct survey_info *cur_survey; |
595 | struct survey_info survey[ATH9K_NUM_CHANNELS]; | |
0e2dedf9 | 596 | |
394cf0a1 S |
597 | struct tasklet_struct intr_tq; |
598 | struct tasklet_struct bcon_tasklet; | |
cbe61d8a | 599 | struct ath_hw *sc_ah; |
394cf0a1 S |
600 | void __iomem *mem; |
601 | int irq; | |
2d6a5e95 | 602 | spinlock_t sc_serial_rw; |
04717ccd | 603 | spinlock_t sc_pm_lock; |
394cf0a1 | 604 | struct mutex mutex; |
9f42c2b6 | 605 | struct work_struct paprd_work; |
347809fc | 606 | struct work_struct hw_check_work; |
9f42c2b6 | 607 | struct completion paprd_complete; |
394cf0a1 | 608 | |
17d7904d | 609 | u32 intrstatus; |
394cf0a1 | 610 | u32 sc_flags; /* SC_OP_* */ |
1b04b930 | 611 | u16 ps_flags; /* PS_* */ |
17d7904d | 612 | u16 curtxpow; |
17d7904d S |
613 | u8 nbcnvifs; |
614 | u16 nvifs; | |
96148326 | 615 | bool ps_enabled; |
1dbfd9d4 | 616 | bool ps_idle; |
709ade9e | 617 | unsigned long ps_usecount; |
394cf0a1 | 618 | |
17d7904d | 619 | struct ath_config config; |
394cf0a1 S |
620 | struct ath_rx rx; |
621 | struct ath_tx tx; | |
622 | struct ath_beacon beacon; | |
394cf0a1 S |
623 | struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS]; |
624 | ||
625 | struct ath_led radio_led; | |
626 | struct ath_led assoc_led; | |
627 | struct ath_led tx_led; | |
628 | struct ath_led rx_led; | |
629 | struct delayed_work ath_led_blink_work; | |
630 | int led_on_duration; | |
631 | int led_off_duration; | |
632 | int led_on_cnt; | |
633 | int led_off_cnt; | |
634 | ||
57c4d7b4 JB |
635 | int beacon_interval; |
636 | ||
a830df07 | 637 | #ifdef CONFIG_ATH9K_DEBUGFS |
17d7904d | 638 | struct ath9k_debug debug; |
394cf0a1 | 639 | #endif |
6b96f93e | 640 | struct ath_beacon_config cur_beacon_conf; |
164ace38 | 641 | struct delayed_work tx_complete_work; |
2e20250a | 642 | struct ath_btcoex btcoex; |
5088c2f1 VT |
643 | |
644 | struct ath_descdma txsdma; | |
102885a5 VT |
645 | |
646 | struct ath_ant_comb ant_comb; | |
394cf0a1 S |
647 | }; |
648 | ||
bce048d7 JM |
649 | struct ath_wiphy { |
650 | struct ath_softc *sc; /* shared for all virtual wiphys */ | |
651 | struct ieee80211_hw *hw; | |
20bd2a09 | 652 | struct ath9k_hw_cal_data caldata; |
f0ed85c6 | 653 | enum ath_wiphy_state { |
9580a222 | 654 | ATH_WIPHY_INACTIVE, |
f0ed85c6 JM |
655 | ATH_WIPHY_ACTIVE, |
656 | ATH_WIPHY_PAUSING, | |
657 | ATH_WIPHY_PAUSED, | |
8089cc47 | 658 | ATH_WIPHY_SCAN, |
f0ed85c6 | 659 | } state; |
194b7c13 | 660 | bool idle; |
0e2dedf9 JM |
661 | int chan_idx; |
662 | int chan_is_ht; | |
9fa23e17 | 663 | int last_rssi; |
bce048d7 JM |
664 | }; |
665 | ||
55624204 | 666 | void ath9k_tasklet(unsigned long data); |
394cf0a1 | 667 | int ath_reset(struct ath_softc *sc, bool retry_tx); |
394cf0a1 S |
668 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); |
669 | int ath_cabq_update(struct ath_softc *); | |
670 | ||
5bb12791 | 671 | static inline void ath_read_cachesize(struct ath_common *common, int *csz) |
394cf0a1 | 672 | { |
5bb12791 | 673 | common->bus_ops->read_cachesize(common, csz); |
394cf0a1 S |
674 | } |
675 | ||
394cf0a1 | 676 | extern struct ieee80211_ops ath9k_ops; |
55624204 | 677 | extern int modparam_nohwcrypt; |
9a75c2ff | 678 | extern int led_blink; |
394cf0a1 S |
679 | |
680 | irqreturn_t ath_isr(int irq, void *dev); | |
285f2dda | 681 | int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid, |
5bb12791 | 682 | const struct ath_bus_ops *bus_ops); |
285f2dda | 683 | void ath9k_deinit_device(struct ath_softc *sc); |
285f2dda | 684 | void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw); |
0e2dedf9 JM |
685 | void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw, |
686 | struct ath9k_channel *ichan); | |
687 | void ath_update_chainmask(struct ath_softc *sc, int is_ht); | |
688 | int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |
689 | struct ath9k_channel *hchan); | |
68a89116 LR |
690 | |
691 | void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
692 | void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw); | |
55624204 | 693 | bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode); |
394cf0a1 S |
694 | |
695 | #ifdef CONFIG_PCI | |
696 | int ath_pci_init(void); | |
697 | void ath_pci_exit(void); | |
698 | #else | |
699 | static inline int ath_pci_init(void) { return 0; }; | |
700 | static inline void ath_pci_exit(void) {}; | |
f1dc5600 | 701 | #endif |
f1dc5600 | 702 | |
394cf0a1 S |
703 | #ifdef CONFIG_ATHEROS_AR71XX |
704 | int ath_ahb_init(void); | |
705 | void ath_ahb_exit(void); | |
706 | #else | |
707 | static inline int ath_ahb_init(void) { return 0; }; | |
708 | static inline void ath_ahb_exit(void) {}; | |
f078f209 | 709 | #endif |
394cf0a1 | 710 | |
0bc0798b GJ |
711 | void ath9k_ps_wakeup(struct ath_softc *sc); |
712 | void ath9k_ps_restore(struct ath_softc *sc); | |
8ca21f01 | 713 | |
31a01645 | 714 | void ath9k_set_bssid_mask(struct ieee80211_hw *hw, struct ieee80211_vif *vif); |
c52f33d0 JM |
715 | int ath9k_wiphy_add(struct ath_softc *sc); |
716 | int ath9k_wiphy_del(struct ath_wiphy *aphy); | |
f0ed85c6 JM |
717 | void ath9k_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb); |
718 | int ath9k_wiphy_pause(struct ath_wiphy *aphy); | |
719 | int ath9k_wiphy_unpause(struct ath_wiphy *aphy); | |
0e2dedf9 | 720 | int ath9k_wiphy_select(struct ath_wiphy *aphy); |
f98c3bd2 | 721 | void ath9k_wiphy_set_scheduler(struct ath_softc *sc, unsigned int msec_int); |
0e2dedf9 | 722 | void ath9k_wiphy_chan_work(struct work_struct *work); |
9580a222 | 723 | bool ath9k_wiphy_started(struct ath_softc *sc); |
18eb62f8 JM |
724 | void ath9k_wiphy_pause_all_forced(struct ath_softc *sc, |
725 | struct ath_wiphy *selected); | |
8089cc47 | 726 | bool ath9k_wiphy_scanning(struct ath_softc *sc); |
f98c3bd2 | 727 | void ath9k_wiphy_work(struct work_struct *work); |
64839170 | 728 | bool ath9k_all_wiphys_idle(struct ath_softc *sc); |
194b7c13 | 729 | void ath9k_set_wiphy_idle(struct ath_wiphy *aphy, bool idle); |
8ca21f01 | 730 | |
f52de03b | 731 | void ath_mac80211_stop_queue(struct ath_softc *sc, u16 skb_queue); |
68e8f2fa | 732 | bool ath_mac80211_start_queue(struct ath_softc *sc, u16 skb_queue); |
f52de03b | 733 | |
0fca65c1 S |
734 | void ath_start_rfkill_poll(struct ath_softc *sc); |
735 | extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw); | |
736 | ||
394cf0a1 | 737 | #endif /* ATH9K_H */ |