[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / ar9002_phy.c

/*
 * Copyright (c) 2008-2010 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/**
 * DOC: Programming Atheros 802.11n analog front end radios
 *
 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
 * devices have either an external AR2133 analog front end radio for single
 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
 * band 2.4 GHz / 5 GHz communication.
 *
 * All devices after the AR5416 and AR5418 family starting with the AR9280
 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
 * into a single-chip and require less programming.
 *
 * The following single-chips exist with a respective embedded radio:
 *
 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
 * AR9281 - 11n single-band 1x2 MIMO for PCIe
 * AR9285 - 11n single-band 1x1 for PCIe
 * AR9287 - 11n single-band 2x2 MIMO for PCIe
 *
 * AR9220 - 11n dual-band 2x2 MIMO for PCI
 * AR9223 - 11n single-band 2x2 MIMO for PCI
 *
 * AR9287 - 11n single-band 1x1 MIMO for USB
 */

#include "hw.h"
#include "ar9002_phy.h"

/**
 * ar9002_hw_set_channel - set channel on single-chip device
 * @ah: atheros hardware structure
 * @chan:
 *
 * This is the function to change channel on single-chip devices, that is
 * all devices after ar9280.
 *
 * This function takes the channel value in MHz and sets
 * hardware channel value. Assumes writes have been enabled to analog bus.
 *
 * Actual Expression,
 *
 * For 2GHz channel,
 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
 * (freq_ref = 40MHz)
 *
 * For 5GHz channel,
 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
 * (freq_ref = 40MHz/(24>>amodeRefSel))
 */
static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
{
	u16 bMode, fracMode, aModeRefSel = 0;
	u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
	struct chan_centers centers;
	u32 refDivA = 24;

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	freq = centers.synth_center;

	reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
	reg32 &= 0xc0000000;

	if (freq < 4800) { /* 2 GHz, fractional mode */
		u32 txctl;
		int regWrites = 0;

		bMode = 1;
		fracMode = 1;
		aModeRefSel = 0;
		channelSel = CHANSEL_2G(freq);

		if (AR_SREV_9287_11_OR_LATER(ah)) {
			if (freq == 2484) {
				/* Enable channel spreading for channel 14 */
				REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
						1, regWrites);
			} else {
				REG_WRITE_ARRAY(&ah->iniCckfirNormal,
						1, regWrites);
			}
		} else {
			txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
			if (freq == 2484) {
				/* Enable channel spreading for channel 14 */
				REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
					  txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
			} else {
				REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
					  txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
			}
		}
	} else {
		bMode = 0;
		fracMode = 0;

		switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
		case 0:
			if ((freq % 20) == 0)
				aModeRefSel = 3;
			else if ((freq % 10) == 0)
				aModeRefSel = 2;
			if (aModeRefSel)
				break;
		case 1:
		default:
			aModeRefSel = 0;
			/*
			 * Enable 2G (fractional) mode for channels
			 * which are 5MHz spaced.
			 */
			fracMode = 1;
			refDivA = 1;
			channelSel = CHANSEL_5G(freq);

			/* RefDivA setting */
			REG_RMW_FIELD(ah, AR_AN_SYNTH9,
				      AR_AN_SYNTH9_REFDIVA, refDivA);

		}

		if (!fracMode) {
			ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
			channelSel = ndiv & 0x1ff;
			channelFrac = (ndiv & 0xfffffe00) * 2;
			channelSel = (channelSel << 17) | channelFrac;
		}
	}

	reg32 = reg32 |
	    (bMode << 29) |
	    (fracMode << 28) | (aModeRefSel << 26) | (channelSel);

	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);

	ah->curchan = chan;
	ah->curchan_rad_index = -1;

	return 0;
}

/**
 * ar9002_hw_spur_mitigate - convert baseband spur frequency
 * @ah: atheros hardware structure
 * @chan:
 *
 * For single-chip solutions. Converts to baseband spur frequency given the
 * input channel frequency and compute register settings below.
 */
static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
				    struct ath9k_channel *chan)
{
	int bb_spur = AR_NO_SPUR;
	int freq;
	int bin, cur_bin;
	int bb_spur_off, spur_subchannel_sd;
	int spur_freq_sd;
	int spur_delta_phase;
	int denominator;
	int upper, lower, cur_vit_mask;
	int tmp, newVal;
	int i;
	int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
			  AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
	};
	int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
			 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
	};
	int inc[4] = { 0, 100, 0, 0 };
	struct chan_centers centers;

	int8_t mask_m[123];
	int8_t mask_p[123];
	int8_t mask_amt;
	int tmp_mask;
	int cur_bb_spur;
	bool is2GHz = IS_CHAN_2GHZ(chan);

	memset(&mask_m, 0, sizeof(int8_t) * 123);
	memset(&mask_p, 0, sizeof(int8_t) * 123);

	ath9k_hw_get_channel_centers(ah, chan, &centers);
	freq = centers.synth_center;

	ah->config.spurmode = SPUR_ENABLE_EEPROM;
	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);

		if (is2GHz)
			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
		else
			cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;

		if (AR_NO_SPUR == cur_bb_spur)
			break;
		cur_bb_spur = cur_bb_spur - freq;

		if (IS_CHAN_HT40(chan)) {
			if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
			    (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
				bb_spur = cur_bb_spur;
				break;
			}
		} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
			   (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
			bb_spur = cur_bb_spur;
			break;
		}
	}

	if (AR_NO_SPUR == bb_spur) {
		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
		return;
	} else {
		REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
			    AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
	}

	bin = bb_spur * 320;

	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));

	ENABLE_REGWRITE_BUFFER(ah);

	newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
			AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
			AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
			AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);

	newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
		  AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
		  AR_PHY_SPUR_REG_MASK_RATE_SELECT |
		  AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
		  SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);

	if (IS_CHAN_HT40(chan)) {
		if (bb_spur < 0) {
			spur_subchannel_sd = 1;
			bb_spur_off = bb_spur + 10;
		} else {
			spur_subchannel_sd = 0;
			bb_spur_off = bb_spur - 10;
		}
	} else {
		spur_subchannel_sd = 0;
		bb_spur_off = bb_spur;
	}

	if (IS_CHAN_HT40(chan))
		spur_delta_phase =
			((bb_spur * 262144) /
			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
	else
		spur_delta_phase =
			((bb_spur * 524288) /
			 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;

	denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
	spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;

	newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
		  SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
		  SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
	REG_WRITE(ah, AR_PHY_TIMING11, newVal);

	newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);

	cur_bin = -6000;
	upper = bin + 100;
	lower = bin - 100;

	for (i = 0; i < 4; i++) {
		int pilot_mask = 0;
		int chan_mask = 0;
		int bp = 0;
		for (bp = 0; bp < 30; bp++) {
			if ((cur_bin > lower) && (cur_bin < upper)) {
				pilot_mask = pilot_mask | 0x1 << bp;
				chan_mask = chan_mask | 0x1 << bp;
			}
			cur_bin += 100;
		}
		cur_bin += inc[i];
		REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
		REG_WRITE(ah, chan_mask_reg[i], chan_mask);
	}

	cur_vit_mask = 6100;
	upper = bin + 120;
	lower = bin - 120;

	for (i = 0; i < 123; i++) {
		if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {

			/* workaround for gcc bug #37014 */
			volatile int tmp_v = abs(cur_vit_mask - bin);

			if (tmp_v < 75)
				mask_amt = 1;
			else
				mask_amt = 0;
			if (cur_vit_mask < 0)
				mask_m[abs(cur_vit_mask / 100)] = mask_amt;
			else
				mask_p[cur_vit_mask / 100] = mask_amt;
		}
		cur_vit_mask -= 100;
	}

	tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
		| (mask_m[48] << 26) | (mask_m[49] << 24)
		| (mask_m[50] << 22) | (mask_m[51] << 20)
		| (mask_m[52] << 18) | (mask_m[53] << 16)
		| (mask_m[54] << 14) | (mask_m[55] << 12)
		| (mask_m[56] << 10) | (mask_m[57] << 8)
		| (mask_m[58] << 6) | (mask_m[59] << 4)
		| (mask_m[60] << 2) | (mask_m[61] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);

	tmp_mask = (mask_m[31] << 28)
		| (mask_m[32] << 26) | (mask_m[33] << 24)
		| (mask_m[34] << 22) | (mask_m[35] << 20)
		| (mask_m[36] << 18) | (mask_m[37] << 16)
		| (mask_m[48] << 14) | (mask_m[39] << 12)
		| (mask_m[40] << 10) | (mask_m[41] << 8)
		| (mask_m[42] << 6) | (mask_m[43] << 4)
		| (mask_m[44] << 2) | (mask_m[45] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);

	tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
		| (mask_m[18] << 26) | (mask_m[18] << 24)
		| (mask_m[20] << 22) | (mask_m[20] << 20)
		| (mask_m[22] << 18) | (mask_m[22] << 16)
		| (mask_m[24] << 14) | (mask_m[24] << 12)
		| (mask_m[25] << 10) | (mask_m[26] << 8)
		| (mask_m[27] << 6) | (mask_m[28] << 4)
		| (mask_m[29] << 2) | (mask_m[30] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);

	tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
		| (mask_m[2] << 26) | (mask_m[3] << 24)
		| (mask_m[4] << 22) | (mask_m[5] << 20)
		| (mask_m[6] << 18) | (mask_m[7] << 16)
		| (mask_m[8] << 14) | (mask_m[9] << 12)
		| (mask_m[10] << 10) | (mask_m[11] << 8)
		| (mask_m[12] << 6) | (mask_m[13] << 4)
		| (mask_m[14] << 2) | (mask_m[15] << 0);
	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);

	tmp_mask = (mask_p[15] << 28)
		| (mask_p[14] << 26) | (mask_p[13] << 24)
		| (mask_p[12] << 22) | (mask_p[11] << 20)
		| (mask_p[10] << 18) | (mask_p[9] << 16)
		| (mask_p[8] << 14) | (mask_p[7] << 12)
		| (mask_p[6] << 10) | (mask_p[5] << 8)
		| (mask_p[4] << 6) | (mask_p[3] << 4)
		| (mask_p[2] << 2) | (mask_p[1] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);

	tmp_mask = (mask_p[30] << 28)
		| (mask_p[29] << 26) | (mask_p[28] << 24)
		| (mask_p[27] << 22) | (mask_p[26] << 20)
		| (mask_p[25] << 18) | (mask_p[24] << 16)
		| (mask_p[23] << 14) | (mask_p[22] << 12)
		| (mask_p[21] << 10) | (mask_p[20] << 8)
		| (mask_p[19] << 6) | (mask_p[18] << 4)
		| (mask_p[17] << 2) | (mask_p[16] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);

	tmp_mask = (mask_p[45] << 28)
		| (mask_p[44] << 26) | (mask_p[43] << 24)
		| (mask_p[42] << 22) | (mask_p[41] << 20)
		| (mask_p[40] << 18) | (mask_p[39] << 16)
		| (mask_p[38] << 14) | (mask_p[37] << 12)
		| (mask_p[36] << 10) | (mask_p[35] << 8)
		| (mask_p[34] << 6) | (mask_p[33] << 4)
		| (mask_p[32] << 2) | (mask_p[31] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);

	tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
		| (mask_p[59] << 26) | (mask_p[58] << 24)
		| (mask_p[57] << 22) | (mask_p[56] << 20)
		| (mask_p[55] << 18) | (mask_p[54] << 16)
		| (mask_p[53] << 14) | (mask_p[52] << 12)
		| (mask_p[51] << 10) | (mask_p[50] << 8)
		| (mask_p[49] << 6) | (mask_p[48] << 4)
		| (mask_p[47] << 2) | (mask_p[46] << 0);
	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);

	REGWRITE_BUFFER_FLUSH(ah);
}

static void ar9002_olc_init(struct ath_hw *ah)
{
	u32 i;

	if (!OLC_FOR_AR9280_20_LATER)
		return;

	if (OLC_FOR_AR9287_10_LATER) {
		REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
				AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
		ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
				AR9287_AN_TXPC0_TXPCMODE,
				AR9287_AN_TXPC0_TXPCMODE_S,
				AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
		udelay(100);
	} else {
		for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
			ah->originalGain[i] =
				MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
						AR_PHY_TX_GAIN);
		ah->PDADCdelta = 0;
	}
}

static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
					 struct ath9k_channel *chan)
{
	u32 pll;

	pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);

	if (chan && IS_CHAN_HALF_RATE(chan))
		pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
	else if (chan && IS_CHAN_QUARTER_RATE(chan))
		pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);

	if (chan && IS_CHAN_5GHZ(chan)) {
		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
			pll = 0x142c;
		else if (AR_SREV_9280_20(ah))
			pll = 0x2850;
		else
			pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
	} else {
		pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
	}

	return pll;
}

static void ar9002_hw_do_getnf(struct ath_hw *ah,
			      int16_t nfarray[NUM_NF_READINGS])
{
	int16_t nf;

	nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
	nfarray[0] = sign_extend(nf, 9);

	nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
	if (IS_CHAN_HT40(ah->curchan))
		nfarray[3] = sign_extend(nf, 9);

	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
		return;

	nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
	nfarray[1] = sign_extend(nf, 9);

	nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
	if (IS_CHAN_HT40(ah->curchan))
		nfarray[4] = sign_extend(nf, 9);
}

static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
{
	if (AR_SREV_9285(ah)) {
		ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
	} else if (AR_SREV_9287(ah)) {
		ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
	} else if (AR_SREV_9271(ah)) {
		ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
	} else {
		ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
		ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
		ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
		ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
		ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
		ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
	}
}

void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
{
	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);

	priv_ops->set_rf_regs = NULL;
	priv_ops->rf_alloc_ext_banks = NULL;
	priv_ops->rf_free_ext_banks = NULL;
	priv_ops->rf_set_freq = ar9002_hw_set_channel;
	priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
	priv_ops->olc_init = ar9002_olc_init;
	priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
	priv_ops->do_getnf = ar9002_hw_do_getnf;

	ar9002_hw_set_nf_limits(ah);
}

void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
				   struct ath_hw_antcomb_conf *antconf)
{
	u32 regval;

	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
	antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
				  AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
	antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
				 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
	antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
				  AR_PHY_9285_FAST_DIV_BIAS_S;
}
EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_get);

void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
				   struct ath_hw_antcomb_conf *antconf)
{
	u32 regval;

	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
	regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
		    AR_PHY_9285_ANT_DIV_ALT_LNACONF |
		    AR_PHY_9285_FAST_DIV_BIAS);
	regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
		   & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
	regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
		   & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
	regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
		   & AR_PHY_9285_FAST_DIV_BIAS);

	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
}
EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_set);
Commit	Line	Data
8fe65368 LR	1	/*
	2	* Copyright (c) 2008-2010 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	/**
	18	* DOC: Programming Atheros 802.11n analog front end radios
	19	*
	20	* AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
	21	* devices have either an external AR2133 analog front end radio for single
	22	* band 2.4 GHz communication or an AR5133 analog front end radio for dual
	23	* band 2.4 GHz / 5 GHz communication.
	24	*
	25	* All devices after the AR5416 and AR5418 family starting with the AR9280
	26	* have their analog front radios, MAC/BB and host PCIe/USB interface embedded
	27	* into a single-chip and require less programming.
	28	*
	29	* The following single-chips exist with a respective embedded radio:
	30	*
	31	* AR9280 - 11n dual-band 2x2 MIMO for PCIe
	32	* AR9281 - 11n single-band 1x2 MIMO for PCIe
	33	* AR9285 - 11n single-band 1x1 for PCIe
	34	* AR9287 - 11n single-band 2x2 MIMO for PCIe
	35	*
	36	* AR9220 - 11n dual-band 2x2 MIMO for PCI
	37	* AR9223 - 11n single-band 2x2 MIMO for PCI
	38	*
	39	* AR9287 - 11n single-band 1x1 MIMO for USB
	40	*/
	41
	42	#include "hw.h"
	43	#include "ar9002_phy.h"
	44
	45	/**
	46	* ar9002_hw_set_channel - set channel on single-chip device
	47	* @ah: atheros hardware structure
	48	* @chan:
	49	*
	50	* This is the function to change channel on single-chip devices, that is
	51	* all devices after ar9280.
	52	*
	53	* This function takes the channel value in MHz and sets
	54	* hardware channel value. Assumes writes have been enabled to analog bus.
	55	*
	56	* Actual Expression,
	57	*
	58	* For 2GHz channel,
	59	* Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
	60	* (freq_ref = 40MHz)
	61	*
	62	* For 5GHz channel,
	63	* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
	64	* (freq_ref = 40MHz/(24>>amodeRefSel))
65	*/
66	static int ar9002_hw_set_channel(struct ath_hw ah, struct ath9k_channel chan)
67	{
68	u16 bMode, fracMode, aModeRefSel = 0;
69	u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
70	struct chan_centers centers;
71	u32 refDivA = 24;
72
73	ath9k_hw_get_channel_centers(ah, chan, &centers);
74	freq = centers.synth_center;
75
76	reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
77	reg32 &= 0xc0000000;
78
79	if (freq < 4800) { /* 2 GHz, fractional mode */
80	u32 txctl;
81	int regWrites = 0;
82
83	bMode = 1;
84	fracMode = 1;
85	aModeRefSel = 0;
7152451a	86	channelSel = CHANSEL_2G(freq);
8fe65368 LR	87
	88	if (AR_SREV_9287_11_OR_LATER(ah)) {
	89	if (freq == 2484) {
	90	/* Enable channel spreading for channel 14 */
	91	REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
	92	1, regWrites);
	93	} else {
	94	REG_WRITE_ARRAY(&ah->iniCckfirNormal,
	95	1, regWrites);
	96	}
	97	} else {
	98	txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
	99	if (freq == 2484) {
	100	/* Enable channel spreading for channel 14 */
	101	REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
	102	txctl \| AR_PHY_CCK_TX_CTRL_JAPAN);
	103	} else {
	104	REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
	105	txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
	106	}
	107	}
	108	} else {
	109	bMode = 0;
	110	fracMode = 0;
	111
	112	switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
	113	case 0:
	114	if ((freq % 20) == 0)
	115	aModeRefSel = 3;
	116	else if ((freq % 10) == 0)
	117	aModeRefSel = 2;
	118	if (aModeRefSel)
	119	break;
	120	case 1:
	121	default:
	122	aModeRefSel = 0;
	123	/*
	124	* Enable 2G (fractional) mode for channels
	125	* which are 5MHz spaced.
	126	*/
	127	fracMode = 1;
	128	refDivA = 1;
7152451a	129	channelSel = CHANSEL_5G(freq);
8fe65368 LR	130
	131	/* RefDivA setting */
	132	REG_RMW_FIELD(ah, AR_AN_SYNTH9,
	133	AR_AN_SYNTH9_REFDIVA, refDivA);
	134
	135	}
	136
	137	if (!fracMode) {
	138	ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
	139	channelSel = ndiv & 0x1ff;
	140	channelFrac = (ndiv & 0xfffffe00) * 2;
	141	channelSel = (channelSel << 17) \| channelFrac;
	142	}
	143	}
	144
	145	reg32 = reg32 \|
	146	(bMode << 29) \|
	147	(fracMode << 28) \| (aModeRefSel << 26) \| (channelSel);
	148
	149	REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
	150
	151	ah->curchan = chan;
	152	ah->curchan_rad_index = -1;
	153
	154	return 0;
	155	}
	156
	157	/**
	158	* ar9002_hw_spur_mitigate - convert baseband spur frequency
	159	* @ah: atheros hardware structure
	160	* @chan:
	161	*
	162	* For single-chip solutions. Converts to baseband spur frequency given the
	163	* input channel frequency and compute register settings below.
	164	*/
	165	static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
	166	struct ath9k_channel *chan)
	167	{
	168	int bb_spur = AR_NO_SPUR;
	169	int freq;
	170	int bin, cur_bin;
	171	int bb_spur_off, spur_subchannel_sd;
	172	int spur_freq_sd;
	173	int spur_delta_phase;
	174	int denominator;
	175	int upper, lower, cur_vit_mask;
	176	int tmp, newVal;
	177	int i;
	178	int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
	179	AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
	180	};
	181	int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
	182	AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
	183	};
	184	int inc[4] = { 0, 100, 0, 0 };
	185	struct chan_centers centers;
	186
	187	int8_t mask_m[123];
	188	int8_t mask_p[123];
	189	int8_t mask_amt;
	190	int tmp_mask;
	191	int cur_bb_spur;
	192	bool is2GHz = IS_CHAN_2GHZ(chan);
	193
194	memset(&mask_m, 0, sizeof(int8_t) * 123);
195	memset(&mask_p, 0, sizeof(int8_t) * 123);
196
197	ath9k_hw_get_channel_centers(ah, chan, &centers);
198	freq = centers.synth_center;
199
200	ah->config.spurmode = SPUR_ENABLE_EEPROM;
201	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
202	cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
203
204	if (is2GHz)
205	cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
206	else
207	cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
208
209	if (AR_NO_SPUR == cur_bb_spur)
210	break;
211	cur_bb_spur = cur_bb_spur - freq;
212
213	if (IS_CHAN_HT40(chan)) {
214	if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
215	(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
216	bb_spur = cur_bb_spur;
217	break;
218	}
219	} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
220	(cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
221	bb_spur = cur_bb_spur;
222	break;
223	}
224	}
225
226	if (AR_NO_SPUR == bb_spur) {
227	REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
228	AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
229	return;
230	} else {
231	REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
232	AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
233	}
234
235	bin = bb_spur * 320;
236
237	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
238
7d0d0df0 S	239	ENABLE_REGWRITE_BUFFER(ah);
7d0d0df0 S	240
8fe65368 LR	241	newVal = tmp \| (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI \|
	242	AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER \|
	243	AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK \|
	244	AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
	245	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
	246
	247	newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL \|
	248	AR_PHY_SPUR_REG_ENABLE_MASK_PPM \|
	249	AR_PHY_SPUR_REG_MASK_RATE_SELECT \|
	250	AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI \|
	251	SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
	252	REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
	253
	254	if (IS_CHAN_HT40(chan)) {
	255	if (bb_spur < 0) {
	256	spur_subchannel_sd = 1;
	257	bb_spur_off = bb_spur + 10;
	258	} else {
	259	spur_subchannel_sd = 0;
	260	bb_spur_off = bb_spur - 10;
	261	}
	262	} else {
	263	spur_subchannel_sd = 0;
	264	bb_spur_off = bb_spur;
	265	}
	266
	267	if (IS_CHAN_HT40(chan))
	268	spur_delta_phase =
	269	((bb_spur * 262144) /
	270	10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
	271	else
	272	spur_delta_phase =
	273	((bb_spur * 524288) /
	274	10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
	275
	276	denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
	277	spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
	278
	279	newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC \|
	280	SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) \|
	281	SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
	282	REG_WRITE(ah, AR_PHY_TIMING11, newVal);
	283
	284	newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
	285	REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
	286
	287	cur_bin = -6000;
	288	upper = bin + 100;
	289	lower = bin - 100;
	290
	291	for (i = 0; i < 4; i++) {
	292	int pilot_mask = 0;
	293	int chan_mask = 0;
	294	int bp = 0;
	295	for (bp = 0; bp < 30; bp++) {
	296	if ((cur_bin > lower) && (cur_bin < upper)) {
	297	pilot_mask = pilot_mask \| 0x1 << bp;
	298	chan_mask = chan_mask \| 0x1 << bp;
	299	}
	300	cur_bin += 100;
	301	}
	302	cur_bin += inc[i];
	303	REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
	304	REG_WRITE(ah, chan_mask_reg[i], chan_mask);
305	}
306
307	cur_vit_mask = 6100;
308	upper = bin + 120;
309	lower = bin - 120;
310
311	for (i = 0; i < 123; i++) {
312	if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
313
314	/* workaround for gcc bug #37014 */
315	volatile int tmp_v = abs(cur_vit_mask - bin);
316
317	if (tmp_v < 75)
318	mask_amt = 1;
319	else
320	mask_amt = 0;
321	if (cur_vit_mask < 0)
322	mask_m[abs(cur_vit_mask / 100)] = mask_amt;
323	else
324	mask_p[cur_vit_mask / 100] = mask_amt;
325	}
326	cur_vit_mask -= 100;
327	}
328
329	tmp_mask = (mask_m[46] << 30) \| (mask_m[47] << 28)
330	\| (mask_m[48] << 26) \| (mask_m[49] << 24)
331	\| (mask_m[50] << 22) \| (mask_m[51] << 20)
332	\| (mask_m[52] << 18) \| (mask_m[53] << 16)
333	\| (mask_m[54] << 14) \| (mask_m[55] << 12)
334	\| (mask_m[56] << 10) \| (mask_m[57] << 8)
335	\| (mask_m[58] << 6) \| (mask_m[59] << 4)
336	\| (mask_m[60] << 2) \| (mask_m[61] << 0);
337	REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
338	REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
339
340	tmp_mask = (mask_m[31] << 28)
341	\| (mask_m[32] << 26) \| (mask_m[33] << 24)
342	\| (mask_m[34] << 22) \| (mask_m[35] << 20)
343	\| (mask_m[36] << 18) \| (mask_m[37] << 16)
344	\| (mask_m[48] << 14) \| (mask_m[39] << 12)
345	\| (mask_m[40] << 10) \| (mask_m[41] << 8)
346	\| (mask_m[42] << 6) \| (mask_m[43] << 4)
347	\| (mask_m[44] << 2) \| (mask_m[45] << 0);
348	REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
349	REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
350
351	tmp_mask = (mask_m[16] << 30) \| (mask_m[16] << 28)
352	\| (mask_m[18] << 26) \| (mask_m[18] << 24)
353	\| (mask_m[20] << 22) \| (mask_m[20] << 20)
354	\| (mask_m[22] << 18) \| (mask_m[22] << 16)
355	\| (mask_m[24] << 14) \| (mask_m[24] << 12)
356	\| (mask_m[25] << 10) \| (mask_m[26] << 8)
357	\| (mask_m[27] << 6) \| (mask_m[28] << 4)
358	\| (mask_m[29] << 2) \| (mask_m[30] << 0);
359	REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
360	REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
361
362	tmp_mask = (mask_m[0] << 30) \| (mask_m[1] << 28)
363	\| (mask_m[2] << 26) \| (mask_m[3] << 24)
364	\| (mask_m[4] << 22) \| (mask_m[5] << 20)
365	\| (mask_m[6] << 18) \| (mask_m[7] << 16)
366	\| (mask_m[8] << 14) \| (mask_m[9] << 12)
367	\| (mask_m[10] << 10) \| (mask_m[11] << 8)
368	\| (mask_m[12] << 6) \| (mask_m[13] << 4)
369	\| (mask_m[14] << 2) \| (mask_m[15] << 0);
370	REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
371	REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
372
373	tmp_mask = (mask_p[15] << 28)
374	\| (mask_p[14] << 26) \| (mask_p[13] << 24)
375	\| (mask_p[12] << 22) \| (mask_p[11] << 20)
376	\| (mask_p[10] << 18) \| (mask_p[9] << 16)
377	\| (mask_p[8] << 14) \| (mask_p[7] << 12)
378	\| (mask_p[6] << 10) \| (mask_p[5] << 8)
379	\| (mask_p[4] << 6) \| (mask_p[3] << 4)
380	\| (mask_p[2] << 2) \| (mask_p[1] << 0);
381	REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
382	REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
383
384	tmp_mask = (mask_p[30] << 28)
385	\| (mask_p[29] << 26) \| (mask_p[28] << 24)
386	\| (mask_p[27] << 22) \| (mask_p[26] << 20)
387	\| (mask_p[25] << 18) \| (mask_p[24] << 16)
388	\| (mask_p[23] << 14) \| (mask_p[22] << 12)
389	\| (mask_p[21] << 10) \| (mask_p[20] << 8)
390	\| (mask_p[19] << 6) \| (mask_p[18] << 4)
391	\| (mask_p[17] << 2) \| (mask_p[16] << 0);
392	REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
393	REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
394
395	tmp_mask = (mask_p[45] << 28)
396	\| (mask_p[44] << 26) \| (mask_p[43] << 24)
397	\| (mask_p[42] << 22) \| (mask_p[41] << 20)
398	\| (mask_p[40] << 18) \| (mask_p[39] << 16)
399	\| (mask_p[38] << 14) \| (mask_p[37] << 12)
400	\| (mask_p[36] << 10) \| (mask_p[35] << 8)
401	\| (mask_p[34] << 6) \| (mask_p[33] << 4)
402	\| (mask_p[32] << 2) \| (mask_p[31] << 0);
403	REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
404	REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
405
406	tmp_mask = (mask_p[61] << 30) \| (mask_p[60] << 28)
407	\| (mask_p[59] << 26) \| (mask_p[58] << 24)
408	\| (mask_p[57] << 22) \| (mask_p[56] << 20)
409	\| (mask_p[55] << 18) \| (mask_p[54] << 16)
410	\| (mask_p[53] << 14) \| (mask_p[52] << 12)
411	\| (mask_p[51] << 10) \| (mask_p[50] << 8)
412	\| (mask_p[49] << 6) \| (mask_p[48] << 4)
413	\| (mask_p[47] << 2) \| (mask_p[46] << 0);
414	REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
415	REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
7d0d0df0 S	416
7d0d0df0 S	417	REGWRITE_BUFFER_FLUSH(ah);
8fe65368 LR	418	}
	419
	420	static void ar9002_olc_init(struct ath_hw *ah)
	421	{
	422	u32 i;
	423
	424	if (!OLC_FOR_AR9280_20_LATER)
	425	return;
	426
	427	if (OLC_FOR_AR9287_10_LATER) {
	428	REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
	429	AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
	430	ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
	431	AR9287_AN_TXPC0_TXPCMODE,
	432	AR9287_AN_TXPC0_TXPCMODE_S,
	433	AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
	434	udelay(100);
	435	} else {
	436	for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
	437	ah->originalGain[i] =
	438	MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
	439	AR_PHY_TX_GAIN);
	440	ah->PDADCdelta = 0;
	441	}
	442	}
	443
64773964 LR	444	static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
	445	struct ath9k_channel *chan)
	446	{
	447	u32 pll;
	448
	449	pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
	450
	451	if (chan && IS_CHAN_HALF_RATE(chan))
	452	pll \|= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
	453	else if (chan && IS_CHAN_QUARTER_RATE(chan))
	454	pll \|= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
	455
	456	if (chan && IS_CHAN_5GHZ(chan)) {
6b42e8d0 FF	457	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
	458	pll = 0x142c;
	459	else if (AR_SREV_9280_20(ah))
	460	pll = 0x2850;
	461	else
	462	pll \|= SM(0x28, AR_RTC_9160_PLL_DIV);
64773964 LR	463	} else {
	464	pll \|= SM(0x2c, AR_RTC_9160_PLL_DIV);
	465	}
	466
	467	return pll;
	468	}
	469
641d9921 FF	470	static void ar9002_hw_do_getnf(struct ath_hw *ah,
	471	int16_t nfarray[NUM_NF_READINGS])
	472	{
641d9921 FF	473	int16_t nf;
	474
	475	nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
54bd5006	476	nfarray[0] = sign_extend(nf, 9);
641d9921	477
54bd5006	478	nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
866b7780 FF	479	if (IS_CHAN_HT40(ah->curchan))
866b7780 FF	480	nfarray[3] = sign_extend(nf, 9);
641d9921	481
54bd5006 FF	482	if (AR_SREV_9285(ah) \|\| AR_SREV_9271(ah))
54bd5006 FF	483	return;
641d9921	484
54bd5006 FF	485	nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
54bd5006 FF	486	nfarray[1] = sign_extend(nf, 9);
641d9921	487
54bd5006	488	nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
866b7780 FF	489	if (IS_CHAN_HT40(ah->curchan))
866b7780 FF	490	nfarray[4] = sign_extend(nf, 9);
641d9921 FF	491	}
641d9921 FF	492
f2552e28 FF	493	static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
	494	{
	495	if (AR_SREV_9285(ah)) {
	496	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
	497	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
	498	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
	499	} else if (AR_SREV_9287(ah)) {
	500	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
	501	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
	502	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
	503	} else if (AR_SREV_9271(ah)) {
	504	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
	505	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
	506	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
	507	} else {
	508	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
	509	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
	510	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
	511	ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
	512	ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
	513	ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
	514	}
	515	}
	516
8fe65368 LR	517	void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
	518	{
	519	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
	520
	521	priv_ops->set_rf_regs = NULL;
	522	priv_ops->rf_alloc_ext_banks = NULL;
	523	priv_ops->rf_free_ext_banks = NULL;
	524	priv_ops->rf_set_freq = ar9002_hw_set_channel;
	525	priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
	526	priv_ops->olc_init = ar9002_olc_init;
64773964	527	priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
641d9921	528	priv_ops->do_getnf = ar9002_hw_do_getnf;
f2552e28 FF	529
f2552e28 FF	530	ar9002_hw_set_nf_limits(ah);
8fe65368	531	}
21cc630f VT	532
	533	void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
	534	struct ath_hw_antcomb_conf *antconf)
	535	{
	536	u32 regval;
	537
	538	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
	539	antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
	540	AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
	541	antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
	542	AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
	543	antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
	544	AR_PHY_9285_FAST_DIV_BIAS_S;
	545	}
	546	EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_get);
	547
	548	void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
	549	struct ath_hw_antcomb_conf *antconf)
	550	{
	551	u32 regval;
	552
	553	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
	554	regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF \|
	555	AR_PHY_9285_ANT_DIV_ALT_LNACONF \|
	556	AR_PHY_9285_FAST_DIV_BIAS);
	557	regval \|= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
	558	& AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
	559	regval \|= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
	560	& AR_PHY_9285_ANT_DIV_ALT_LNACONF);
	561	regval \|= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
	562	& AR_PHY_9285_FAST_DIV_BIAS);
	563
	564	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
	565	}
	566	EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_set);