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Merge branch 'master' of /repos/git/net-next-2.6
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / pcu.c
CommitLineData
c6e387a2
NK		 1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23/*********************************\
24* Protocol Control Unit Functions *
25\*********************************/
26
bcd8f54a
LR		 27#include <asm/unaligned.h>
28
c6e387a2
NK		 29#include "ath5k.h"
30#include "reg.h"
31#include "debug.h"
32#include "base.h"
33
34/*******************\
35* Generic functions *
36\*******************/
37
38/**
39 * ath5k_hw_set_opmode - Set PCU operating mode
40 *
41 * @ah: The &struct ath5k_hw
ccfe5552 42 * @op_mode: &enum nl80211_iftype operating mode
c6e387a2
NK		 43 *
44 * Initialize PCU for the various operating modes (AP/STA etc)
c6e387a2 45 */
ccfe5552 46int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
c6e387a2 47{
954fecea 48 struct ath_common *common = ath5k_hw_common(ah);
c6e387a2
NK		 49 u32 pcu_reg, beacon_reg, low_id, high_id;
50
ccfe5552 51 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
f07a6c49
NK		 52
53 /* Preserve rest settings */
54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
55 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
56 | AR5K_STA_ID1_KEYSRCH_MODE
57 | (ah->ah_version == AR5K_AR5210 ?
58 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
59
c6e387a2
NK		 60 beacon_reg = 0;
61
62 ATH5K_TRACE(ah->ah_sc);
63
ccfe5552 64 switch (op_mode) {
05c914fe 65 case NL80211_IFTYPE_ADHOC:
f07a6c49 66 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
c6e387a2 67 beacon_reg |= AR5K_BCR_ADHOC;
f07a6c49
NK		 68 if (ah->ah_version == AR5K_AR5210)
69 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
70 else
4fb7404e 71 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
c6e387a2
NK		 72 break;
73
05c914fe
JB		 74 case NL80211_IFTYPE_AP:
75 case NL80211_IFTYPE_MESH_POINT:
f07a6c49 76 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
c6e387a2 77 beacon_reg |= AR5K_BCR_AP;
f07a6c49
NK		 78 if (ah->ah_version == AR5K_AR5210)
79 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
80 else
4fb7404e 81 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
c6e387a2
NK		 82 break;
83
05c914fe 84 case NL80211_IFTYPE_STATION:
f07a6c49
NK		 85 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
86 | (ah->ah_version == AR5K_AR5210 ?
c6e387a2 87 AR5K_STA_ID1_PWR_SV : 0);
05c914fe 88 case NL80211_IFTYPE_MONITOR:
f07a6c49
NK		 89 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
90 | (ah->ah_version == AR5K_AR5210 ?
c6e387a2
NK		 91 AR5K_STA_ID1_NO_PSPOLL : 0);
92 break;
93
94 default:
95 return -EINVAL;
96 }
97
98 /*
99 * Set PCU registers
100 */
954fecea
LR		 101 low_id = get_unaligned_le32(common->macaddr);
102 high_id = get_unaligned_le16(common->macaddr + 4);
c6e387a2
NK		 103 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
104 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
105
106 /*
107 * Set Beacon Control Register on 5210
108 */
109 if (ah->ah_version == AR5K_AR5210)
110 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
111
112 return 0;
113}
114
115/**
495391d7 116 * ath5k_hw_update - Update MIB counters (mac layer statistics)
c6e387a2
NK		 117 *
118 * @ah: The &struct ath5k_hw
c6e387a2 119 *
495391d7
BR		 120 * Reads MIB counters from PCU and updates sw statistics. Is called after a
121 * MIB interrupt, because one of these counters might have reached their maximum
122 * and triggered the MIB interrupt, to let us read and clear the counter.
123 *
124 * Is called in interrupt context!
c6e387a2 125 */
495391d7 126void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
c6e387a2 127{
495391d7 128 struct ath5k_statistics *stats = &ah->ah_sc->stats;
c6e387a2
NK		 129
130 /* Read-And-Clear */
495391d7
BR		 131 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
132 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
133 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
134 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
135 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
c6e387a2
NK		 136}
137
138/**
139 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
140 *
141 * @ah: The &struct ath5k_hw
142 * @high: Flag to determine if we want to use high transmition rate
143 * for ACKs or not
144 *
145 * If high flag is set, we tell hw to use a set of control rates based on
146 * the current transmition rate (check out control_rates array inside reset.c).
147 * If not hw just uses the lowest rate available for the current modulation
148 * scheme being used (1Mbit for CCK and 6Mbits for OFDM).
149 */
150void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
151{
152 if (ah->ah_version != AR5K_AR5212)
153 return;
154 else {
155 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
156 if (high)
c6e387a2 157 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
0edc9a67
BR		 158 else
159 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
c6e387a2
NK		 160 }
161}
162
163
164/******************\
165* ACK/CTS Timeouts *
166\******************/
167
c6e387a2
NK		 168/**
169 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
170 *
171 * @ah: The &struct ath5k_hw
172 * @timeout: Timeout in usec
173 */
626ede6b 174static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
c6e387a2
NK		 175{
176 ATH5K_TRACE(ah->ah_sc);
3578e6eb
LT		 177 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
178 <= timeout)
c6e387a2
NK		 179 return -EINVAL;
180
181 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
3578e6eb 182 ath5k_hw_htoclock(ah, timeout));
c6e387a2
NK		 183
184 return 0;
185}
186
c6e387a2
NK		 187/**
188 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
189 *
190 * @ah: The &struct ath5k_hw
191 * @timeout: Timeout in usec
192 */
626ede6b 193static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
c6e387a2
NK		 194{
195 ATH5K_TRACE(ah->ah_sc);
3578e6eb
LT		 196 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
197 <= timeout)
c6e387a2
NK		 198 return -EINVAL;
199
200 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
3578e6eb 201 ath5k_hw_htoclock(ah, timeout));
c6e387a2
NK		 202
203 return 0;
204}
205
3578e6eb
LT		 206/**
207 * ath5k_hw_htoclock - Translate usec to hw clock units
208 *
209 * @ah: The &struct ath5k_hw
210 * @usec: value in microseconds
211 */
212unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
213{
214 return usec * ath5k_hw_get_clockrate(ah);
215}
216
217/**
218 * ath5k_hw_clocktoh - Translate hw clock units to usec
219 * @clock: value in hw clock units
220 */
221unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
222{
223 return clock / ath5k_hw_get_clockrate(ah);
224}
225
226/**
227 * ath5k_hw_get_clockrate - Get the clock rate for current mode
228 *
229 * @ah: The &struct ath5k_hw
230 */
231unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah)
232{
233 struct ieee80211_channel *channel = ah->ah_current_channel;
234 int clock;
235
236 if (channel->hw_value & CHANNEL_5GHZ)
237 clock = 40; /* 802.11a */
238 else if (channel->hw_value & CHANNEL_CCK)
239 clock = 22; /* 802.11b */
240 else
241 clock = 44; /* 802.11g */
242
243 /* Clock rate in turbo modes is twice the normal rate */
244 if (channel->hw_value & CHANNEL_TURBO)
245 clock *= 2;
246
247 return clock;
248}
249
6e08d228
LT		 250/**
251 * ath5k_hw_get_default_slottime - Get the default slot time for current mode
252 *
253 * @ah: The &struct ath5k_hw
254 */
626ede6b 255static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
6e08d228
LT		 256{
257 struct ieee80211_channel *channel = ah->ah_current_channel;
258
259 if (channel->hw_value & CHANNEL_TURBO)
260 return 6; /* both turbo modes */
261
262 if (channel->hw_value & CHANNEL_CCK)
263 return 20; /* 802.11b */
264
265 return 9; /* 802.11 a/g */
266}
267
268/**
269 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
270 *
271 * @ah: The &struct ath5k_hw
272 */
626ede6b 273static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
6e08d228
LT		 274{
275 struct ieee80211_channel *channel = ah->ah_current_channel;
276
277 if (channel->hw_value & CHANNEL_TURBO)
278 return 8; /* both turbo modes */
279
280 if (channel->hw_value & CHANNEL_5GHZ)
281 return 16; /* 802.11a */
282
283 return 10; /* 802.11 b/g */
284}
285
c6e387a2
NK		 286/**
287 * ath5k_hw_set_lladdr - Set station id
288 *
289 * @ah: The &struct ath5k_hw
290 * @mac: The card's mac address
291 *
292 * Set station id on hw using the provided mac address
293 */
294int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
295{
954fecea 296 struct ath_common *common = ath5k_hw_common(ah);
c6e387a2 297 u32 low_id, high_id;
f6bac3ea 298 u32 pcu_reg;
c6e387a2
NK		 299
300 ATH5K_TRACE(ah->ah_sc);
301 /* Set new station ID */
954fecea 302 memcpy(common->macaddr, mac, ETH_ALEN);
c6e387a2 303
f6bac3ea
BC		 304 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
305
bcd8f54a
LR		 306 low_id = get_unaligned_le32(mac);
307 high_id = get_unaligned_le16(mac + 4);
c6e387a2
NK		 308
309 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
f6bac3ea 310 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
c6e387a2
NK		 311
312 return 0;
313}
314
315/**
316 * ath5k_hw_set_associd - Set BSSID for association
317 *
318 * @ah: The &struct ath5k_hw
319 * @bssid: BSSID
320 * @assoc_id: Assoc id
321 *
322 * Sets the BSSID which trigers the "SME Join" operation
323 */
be5d6b75 324void ath5k_hw_set_associd(struct ath5k_hw *ah)
c6e387a2 325{
954fecea 326 struct ath_common *common = ath5k_hw_common(ah);
c6e387a2
NK		 327 u16 tim_offset = 0;
328
329 /*
330 * Set simple BSSID mask on 5212
331 */
a72d57a8
LR		 332 if (ah->ah_version == AR5K_AR5212)
333 ath_hw_setbssidmask(common);
c6e387a2
NK		 334
335 /*
336 * Set BSSID which triggers the "SME Join" operation
337 */
abba0686
LR		 338 ath5k_hw_reg_write(ah,
339 get_unaligned_le32(common->curbssid),
a3f86bff 340 AR5K_BSS_ID0);
abba0686
LR		 341 ath5k_hw_reg_write(ah,
342 get_unaligned_le16(common->curbssid + 4) |
343 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S),
a3f86bff 344 AR5K_BSS_ID1);
c6e387a2 345
be5d6b75 346 if (common->curaid == 0) {
c6e387a2
NK		 347 ath5k_hw_disable_pspoll(ah);
348 return;
349 }
350
351 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
abba0686 352 tim_offset ? tim_offset + 4 : 0);
c6e387a2
NK		 353
354 ath5k_hw_enable_pspoll(ah, NULL, 0);
355}
356
13b81559 357void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
c6e387a2 358{
954fecea 359 struct ath_common *common = ath5k_hw_common(ah);
c6e387a2
NK		 360 ATH5K_TRACE(ah->ah_sc);
361
f07a6c49
NK		 362 /* Cache bssid mask so that we can restore it
363 * on reset */
954fecea 364 memcpy(common->bssidmask, mask, ETH_ALEN);
13b81559
LR		 365 if (ah->ah_version == AR5K_AR5212)
366 ath_hw_setbssidmask(common);
c6e387a2
NK		 367}
368
c6e387a2
NK		 369/************\
370* RX Control *
371\************/
372
373/**
374 * ath5k_hw_start_rx_pcu - Start RX engine
375 *
376 * @ah: The &struct ath5k_hw
377 *
378 * Starts RX engine on PCU so that hw can process RXed frames
379 * (ACK etc).
380 *
381 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
c6e387a2
NK		 382 */
383void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
384{
385 ATH5K_TRACE(ah->ah_sc);
386 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
387}
388
389/**
390 * at5k_hw_stop_rx_pcu - Stop RX engine
391 *
392 * @ah: The &struct ath5k_hw
393 *
394 * Stops RX engine on PCU
395 *
396 * TODO: Detach ANI here
397 */
398void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
399{
400 ATH5K_TRACE(ah->ah_sc);
401 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
402}
403
404/*
405 * Set multicast filter
406 */
407void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
408{
409 ATH5K_TRACE(ah->ah_sc);
410 /* Set the multicat filter */
411 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
412 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
413}
414
c6e387a2
NK		 415/**
416 * ath5k_hw_get_rx_filter - Get current rx filter
417 *
418 * @ah: The &struct ath5k_hw
419 *
420 * Returns the RX filter by reading rx filter and
421 * phy error filter registers. RX filter is used
422 * to set the allowed frame types that PCU will accept
423 * and pass to the driver. For a list of frame types
424 * check out reg.h.
425 */
426u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
427{
428 u32 data, filter = 0;
429
430 ATH5K_TRACE(ah->ah_sc);
431 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
432
433 /*Radar detection for 5212*/
434 if (ah->ah_version == AR5K_AR5212) {
435 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
436
437 if (data & AR5K_PHY_ERR_FIL_RADAR)
438 filter |= AR5K_RX_FILTER_RADARERR;
439 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
440 filter |= AR5K_RX_FILTER_PHYERR;
441 }
442
443 return filter;
444}
445
446/**
447 * ath5k_hw_set_rx_filter - Set rx filter
448 *
449 * @ah: The &struct ath5k_hw
450 * @filter: RX filter mask (see reg.h)
451 *
452 * Sets RX filter register and also handles PHY error filter
453 * register on 5212 and newer chips so that we have proper PHY
454 * error reporting.
455 */
456void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
457{
458 u32 data = 0;
459
460 ATH5K_TRACE(ah->ah_sc);
461
462 /* Set PHY error filter register on 5212*/
463 if (ah->ah_version == AR5K_AR5212) {
464 if (filter & AR5K_RX_FILTER_RADARERR)
465 data |= AR5K_PHY_ERR_FIL_RADAR;
466 if (filter & AR5K_RX_FILTER_PHYERR)
467 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
468 }
469
470 /*
471 * The AR5210 uses promiscous mode to detect radar activity
472 */
473 if (ah->ah_version == AR5K_AR5210 &&
474 (filter & AR5K_RX_FILTER_RADARERR)) {
475 filter &= ~AR5K_RX_FILTER_RADARERR;
476 filter |= AR5K_RX_FILTER_PROM;
477 }
478
f07a6c49 479 /*Zero length DMA (phy error reporting) */
c6e387a2
NK		 480 if (data)
481 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
482 else
483 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
484
485 /*Write RX Filter register*/
486 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
487
488 /*Write PHY error filter register on 5212*/
489 if (ah->ah_version == AR5K_AR5212)
490 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
491
492}
493
494
495/****************\
496* Beacon control *
497\****************/
498
1c0fc65e
BP		 499#define ATH5K_MAX_TSF_READ 10
500
c6e387a2
NK		 501/**
502 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
503 *
504 * @ah: The &struct ath5k_hw
505 *
506 * Returns the current TSF
507 */
508u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
509{
1c0fc65e
BP		 510 u32 tsf_lower, tsf_upper1, tsf_upper2;
511 int i;
512
513 /*
514 * While reading TSF upper and then lower part, the clock is still
515 * counting (or jumping in case of IBSS merge) so we might get
516 * inconsistent values. To avoid this, we read the upper part again
517 * and check it has not been changed. We make the hypothesis that a
518 * maximum of 3 changes can happens in a row (we use 10 as a safe
519 * value).
520 *
521 * Impact on performance is pretty small, since in most cases, only
522 * 3 register reads are needed.
523 */
524
525 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
526 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {
527 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
528 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
529 if (tsf_upper2 == tsf_upper1)
530 break;
531 tsf_upper1 = tsf_upper2;
532 }
533
534 WARN_ON( i == ATH5K_MAX_TSF_READ );
535
c6e387a2
NK		 536 ATH5K_TRACE(ah->ah_sc);
537
1c0fc65e 538 return (((u64)tsf_upper1 << 32) | tsf_lower);
c6e387a2
NK		 539}
540
8cab7581
AF		 541/**
542 * ath5k_hw_set_tsf64 - Set a new 64bit TSF
543 *
544 * @ah: The &struct ath5k_hw
545 * @tsf64: The new 64bit TSF
546 *
547 * Sets the new TSF
548 */
549void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
550{
551 ATH5K_TRACE(ah->ah_sc);
552
8cab7581 553 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
0ad65bd7 554 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
8cab7581
AF		 555}
556
c6e387a2
NK		 557/**
558 * ath5k_hw_reset_tsf - Force a TSF reset
559 *
560 * @ah: The &struct ath5k_hw
561 *
562 * Forces a TSF reset on PCU
563 */
564void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
565{
14be9947
BC		 566 u32 val;
567
c6e387a2 568 ATH5K_TRACE(ah->ah_sc);
14be9947
BC		 569
570 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
571
572 /*
573 * Each write to the RESET_TSF bit toggles a hardware internal
574 * signal to reset TSF, but if left high it will cause a TSF reset
575 * on the next chip reset as well. Thus we always write the value
576 * twice to clear the signal.
577 */
578 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
579 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
c6e387a2
NK		 580}
581
582/*
583 * Initialize beacon timers
584 */
585void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
586{
587 u32 timer1, timer2, timer3;
588
589 ATH5K_TRACE(ah->ah_sc);
590 /*
591 * Set the additional timers by mode
592 */
ccfe5552 593 switch (ah->ah_sc->opmode) {
f07a6c49 594 case NL80211_IFTYPE_MONITOR:
05c914fe 595 case NL80211_IFTYPE_STATION:
f07a6c49
NK		 596 /* In STA mode timer1 is used as next wakeup
597 * timer and timer2 as next CFP duration start
598 * timer. Both in 1/8TUs. */
599 /* TODO: PCF handling */
c6e387a2
NK		 600 if (ah->ah_version == AR5K_AR5210) {
601 timer1 = 0xffffffff;
602 timer2 = 0xffffffff;
603 } else {
604 timer1 = 0x0000ffff;
605 timer2 = 0x0007ffff;
606 }
f07a6c49
NK		 607 /* Mark associated AP as PCF incapable for now */
608 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
c6e387a2 609 break;
f07a6c49
NK		 610 case NL80211_IFTYPE_ADHOC:
611 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
c6e387a2 612 default:
f07a6c49
NK		 613 /* On non-STA modes timer1 is used as next DMA
614 * beacon alert (DBA) timer and timer2 as next
615 * software beacon alert. Both in 1/8TUs. */
c6e387a2
NK		 616 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
617 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
f07a6c49 618 break;
c6e387a2
NK		 619 }
620
f07a6c49
NK		 621 /* Timer3 marks the end of our ATIM window
622 * a zero length window is not allowed because
623 * we 'll get no beacons */
c6e387a2
NK		 624 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
625
626 /*
627 * Set the beacon register and enable all timers.
c6e387a2 628 */
35edf8aa 629 /* When in AP or Mesh Point mode zero timer0 to start TSF */
ccfe5552
BR		 630 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP ||
631 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT)
f07a6c49 632 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
428cbd4f
NK		 633
634 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
c6e387a2
NK		 635 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
636 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
637 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
638
f07a6c49
NK		 639 /* Force a TSF reset if requested and enable beacons */
640 if (interval & AR5K_BEACON_RESET_TSF)
641 ath5k_hw_reset_tsf(ah);
642
c6e387a2 643 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
f07a6c49
NK		 644 AR5K_BEACON_ENABLE),
645 AR5K_BEACON);
646
647 /* Flush any pending BMISS interrupts on ISR by
648 * performing a clear-on-write operation on PISR
649 * register for the BMISS bit (writing a bit on
650 * ISR togles a reset for that bit and leaves
651 * the rest bits intact) */
652 if (ah->ah_version == AR5K_AR5210)
653 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
654 else
655 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
656
657 /* TODO: Set enchanced sleep registers on AR5212
658 * based on vif->bss_conf params, until then
659 * disable power save reporting.*/
660 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
661
c6e387a2
NK		 662}
663
c6e387a2
NK		 664
665/*********************\
666* Key table functions *
667\*********************/
668
669/*
670 * Reset a key entry on the table
671 */
672int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
673{
f07a6c49 674 unsigned int i, type;
17683c65 675 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
c6e387a2
NK		 676
677 ATH5K_TRACE(ah->ah_sc);
678 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
679
f07a6c49
NK		 680 type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
681
c6e387a2
NK		 682 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
683 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
684
f07a6c49
NK		 685 /* Reset associated MIC entry if TKIP
686 * is enabled located at offset (entry + 64) */
687 if (type == AR5K_KEYTABLE_TYPE_TKIP) {
17683c65 688 AR5K_ASSERT_ENTRY(micentry, AR5K_KEYTABLE_SIZE);
f07a6c49 689 for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++)
17683c65
BC		 690 ath5k_hw_reg_write(ah, 0,
691 AR5K_KEYTABLE_OFF(micentry, i));
f07a6c49
NK		 692 }
693
c6e387a2
NK		 694 /*
695 * Set NULL encryption on AR5212+
696 *
697 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
698 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
699 *
700 * Note2: Windows driver (ndiswrapper) sets this to
701 * 0x00000714 instead of 0x00000007
702 */
ded7a7ea 703 if (ah->ah_version >= AR5K_AR5211) {
c6e387a2
NK		 704 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
705 AR5K_KEYTABLE_TYPE(entry));
706
17683c65
BC		 707 if (type == AR5K_KEYTABLE_TYPE_TKIP) {
708 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
709 AR5K_KEYTABLE_TYPE(micentry));
710 }
711 }
712
c6e387a2
NK		 713 return 0;
714}
715
67143490
BC		 716static
717int ath5k_keycache_type(const struct ieee80211_key_conf *key)
718{
719 switch (key->alg) {
720 case ALG_TKIP:
721 return AR5K_KEYTABLE_TYPE_TKIP;
722 case ALG_CCMP:
723 return AR5K_KEYTABLE_TYPE_CCM;
724 case ALG_WEP:
e31a16d6 725 if (key->keylen == WLAN_KEY_LEN_WEP40)
67143490 726 return AR5K_KEYTABLE_TYPE_40;
e31a16d6 727 else if (key->keylen == WLAN_KEY_LEN_WEP104)
67143490 728 return AR5K_KEYTABLE_TYPE_104;
3cfcf6ac
JM		 729 return -EINVAL;
730 default:
731 return -EINVAL;
67143490
BC		 732 }
733 return -EINVAL;
734}
735
c6e387a2
NK		 736/*
737 * Set a key entry on the table
738 */
739int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
740 const struct ieee80211_key_conf *key, const u8 *mac)
741{
742 unsigned int i;
3f64b435 743 int keylen;
c6e387a2 744 __le32 key_v[5] = {};
3f64b435
BC		 745 __le32 key0 = 0, key1 = 0;
746 __le32 *rxmic, *txmic;
672cf3ce 747 int keytype;
3f64b435
BC		 748 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
749 bool is_tkip;
67143490 750 const u8 *key_ptr;
c6e387a2
NK		 751
752 ATH5K_TRACE(ah->ah_sc);
753
3f64b435
BC		 754 is_tkip = (key->alg == ALG_TKIP);
755
756 /*
757 * key->keylen comes in from mac80211 in bytes.
758 * TKIP is 128 bit + 128 bit mic
759 */
760 keylen = (is_tkip) ? (128 / 8) : key->keylen;
c6e387a2 761
3f64b435
BC		 762 if (entry > AR5K_KEYTABLE_SIZE ||
763 (is_tkip && micentry > AR5K_KEYTABLE_SIZE))
c6e387a2
NK		 764 return -EOPNOTSUPP;
765
67143490
BC		 766 if (unlikely(keylen > 16))
767 return -EOPNOTSUPP;
c6e387a2 768
67143490
BC		 769 keytype = ath5k_keycache_type(key);
770 if (keytype < 0)
771 return keytype;
c6e387a2 772
67143490
BC		 773 /*
774 * each key block is 6 bytes wide, written as pairs of
775 * alternating 32 and 16 bit le values.
776 */
777 key_ptr = key->key;
778 for (i = 0; keylen >= 6; keylen -= 6) {
779 memcpy(&key_v[i], key_ptr, 6);
780 i += 2;
781 key_ptr += 6;
c6e387a2 782 }
67143490
BC		 783 if (keylen)
784 memcpy(&key_v[i], key_ptr, keylen);
c6e387a2 785
3f64b435
BC		 786 /* intentionally corrupt key until mic is installed */
787 if (is_tkip) {
788 key0 = key_v[0] = ~key_v[0];
789 key1 = key_v[1] = ~key_v[1];
790 }
791
c6e387a2
NK		 792 for (i = 0; i < ARRAY_SIZE(key_v); i++)
793 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
794 AR5K_KEYTABLE_OFF(entry, i));
795
796 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
797
3f64b435
BC		 798 if (is_tkip) {
799 /* Install rx/tx MIC */
800 rxmic = (__le32 *) &key->key[16];
801 txmic = (__le32 *) &key->key[24];
f650470a
BC		 802
803 if (ah->ah_combined_mic) {
804 key_v[0] = rxmic[0];
388cdf31 805 key_v[1] = cpu_to_le32(le32_to_cpu(txmic[0]) >> 16);
f650470a 806 key_v[2] = rxmic[1];
388cdf31 807 key_v[3] = cpu_to_le32(le32_to_cpu(txmic[0]) & 0xffff);
f650470a
BC		 808 key_v[4] = txmic[1];
809 } else {
810 key_v[0] = rxmic[0];
811 key_v[1] = 0;
812 key_v[2] = rxmic[1];
813 key_v[3] = 0;
814 key_v[4] = 0;
815 }
3f64b435
BC		 816 for (i = 0; i < ARRAY_SIZE(key_v); i++)
817 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
818 AR5K_KEYTABLE_OFF(micentry, i));
819
820 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
821 AR5K_KEYTABLE_TYPE(micentry));
822 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry));
823 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry));
824
825 /* restore first 2 words of key */
826 ath5k_hw_reg_write(ah, le32_to_cpu(~key0),
827 AR5K_KEYTABLE_OFF(entry, 0));
828 ath5k_hw_reg_write(ah, le32_to_cpu(~key1),
829 AR5K_KEYTABLE_OFF(entry, 1));
830 }
831
c6e387a2
NK		 832 return ath5k_hw_set_key_lladdr(ah, entry, mac);
833}
834
835int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
836{
837 u32 low_id, high_id;
838
839 ATH5K_TRACE(ah->ah_sc);
840 /* Invalid entry (key table overflow) */
841 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
842
bcd8f54a
LR		 843 /*
844 * MAC may be NULL if it's a broadcast key. In this case no need to
845 * to compute get_unaligned_le32 and get_unaligned_le16 as we
846 * already know it.
847 */
dc822b5d 848 if (!mac) {
c6e387a2
NK		 849 low_id = 0xffffffff;
850 high_id = 0xffff | AR5K_KEYTABLE_VALID;
851 } else {
bcd8f54a
LR		 852 low_id = get_unaligned_le32(mac);
853 high_id = get_unaligned_le16(mac + 4) | AR5K_KEYTABLE_VALID;
c6e387a2
NK		 854 }
855
856 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
857 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
858
859 return 0;
860}
861
6e08d228
LT		 862/**
863 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
864 *
865 * @ah: The &struct ath5k_hw
866 * @coverage_class: IEEE 802.11 coverage class number
867 *
868 * Sets slot time, ACK timeout and CTS timeout for given coverage class.
869 */
870void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
871{
872 /* As defined by IEEE 802.11-2007 17.3.8.6 */
873 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
874 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
875 int cts_timeout = ack_timeout;
876
877 ath5k_hw_set_slot_time(ah, slot_time);
878 ath5k_hw_set_ack_timeout(ah, ack_timeout);
879 ath5k_hw_set_cts_timeout(ah, cts_timeout);
880
881 ah->ah_coverage_class = coverage_class;
882}
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