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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
6ccf15a1 51#include <linux/pci-aspm.h>
fa1c114f
JS		 52#include <linux/ethtool.h>
53#include <linux/uaccess.h>
5a0e3ad6 54#include <linux/slab.h>
fa1c114f
JS		 55
56#include <net/ieee80211_radiotap.h>
57
58#include <asm/unaligned.h>
59
60#include "base.h"
61#include "reg.h"
62#include "debug.h"
2111ac0d 63#include "ani.h"
fa1c114f 64
9ad9a26e 65static int modparam_nohwcrypt;
46802a4f 66module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 67MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 68
42639fcd 69static int modparam_all_channels;
46802a4f 70module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 71MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
72
fa1c114f
JS		 73/* Module info */
74MODULE_AUTHOR("Jiri Slaby");
75MODULE_AUTHOR("Nick Kossifidis");
76MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 79MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f 80
8a63facc
BC		 81static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
82static int ath5k_beacon_update(struct ieee80211_hw *hw,
83 struct ieee80211_vif *vif);
84static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 85
86/* Known PCI ids */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 106 { 0 }
107};
108MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
109
110/* Known SREVs */
2c91108c 111static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148};
149
2c91108c 150static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 /* XR missing */
190};
191
9e4e43f2 192static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 193 struct ath5k_buf *bf)
194{
195 BUG_ON(!bf);
196 if (!bf->skb)
197 return;
198 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
199 PCI_DMA_TODEVICE);
00482973 200 dev_kfree_skb_any(bf->skb);
fa1c114f 201 bf->skb = NULL;
39d63f2a
BR		 202 bf->skbaddr = 0;
203 bf->desc->ds_data = 0;
fa1c114f
JS		 204}
205
9e4e43f2 206static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 207 struct ath5k_buf *bf)
208{
cc861f74
LR		 209 struct ath5k_hw *ah = sc->ah;
210 struct ath_common *common = ath5k_hw_common(ah);
211
a6c8d375
FF		 212 BUG_ON(!bf);
213 if (!bf->skb)
214 return;
cc861f74 215 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 216 PCI_DMA_FROMDEVICE);
217 dev_kfree_skb_any(bf->skb);
218 bf->skb = NULL;
39d63f2a
BR		 219 bf->skbaddr = 0;
220 bf->desc->ds_data = 0;
a6c8d375
FF		 221}
222
223
fa1c114f
JS		 224static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
225{
226 u64 tsf = ath5k_hw_get_tsf64(ah);
227
228 if ((tsf & 0x7fff) < rstamp)
229 tsf -= 0x8000;
230
231 return (tsf & ~0x7fff) | rstamp;
232}
233
fa1c114f
JS		 234static const char *
235ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
236{
237 const char *name = "xxxxx";
238 unsigned int i;
239
240 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
241 if (srev_names[i].sr_type != type)
242 continue;
75d0edb8
NK		 243
244 if ((val & 0xf0) == srev_names[i].sr_val)
245 name = srev_names[i].sr_name;
246
247 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 248 name = srev_names[i].sr_name;
249 break;
250 }
251 }
252
253 return name;
254}
e5aa8474
LR		 255static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
256{
257 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
258 return ath5k_hw_reg_read(ah, reg_offset);
259}
260
261static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
262{
263 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
264 ath5k_hw_reg_write(ah, val, reg_offset);
265}
266
267static const struct ath_ops ath5k_common_ops = {
268 .read = ath5k_ioread32,
269 .write = ath5k_iowrite32,
270};
fa1c114f 271
8a63facc
BC		 272/***********************\
273* Driver Initialization *
274\***********************/
fa1c114f 275
8a63facc 276static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 277{
8a63facc
BC		 278 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
279 struct ath5k_softc *sc = hw->priv;
280 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
6ccf15a1 281
8a63facc
BC		 282 return ath_reg_notifier_apply(wiphy, request, regulatory);
283}
fa1c114f 284
8a63facc
BC		 285/********************\
286* Channel/mode setup *
287\********************/
fa1c114f 288
8a63facc
BC		 289/*
290 * Convert IEEE channel number to MHz frequency.
291 */
292static inline short
293ath5k_ieee2mhz(short chan)
294{
295 if (chan <= 14 || chan >= 27)
296 return ieee80211chan2mhz(chan);
297 else
298 return 2212 + chan * 20;
299}
fa1c114f 300
8a63facc
BC		 301/*
302 * Returns true for the channel numbers used without all_channels modparam.
303 */
304static bool ath5k_is_standard_channel(short chan)
305{
306 return ((chan <= 14) ||
307 /* UNII 1,2 */
308 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
309 /* midband */
310 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
311 /* UNII-3 */
312 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
313}
fa1c114f 314
8a63facc
BC		 315static unsigned int
316ath5k_copy_channels(struct ath5k_hw *ah,
317 struct ieee80211_channel *channels,
318 unsigned int mode,
319 unsigned int max)
320{
321 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f 322
8a63facc
BC		 323 if (!test_bit(mode, ah->ah_modes))
324 return 0;
fa1c114f 325
8a63facc
BC		 326 switch (mode) {
327 case AR5K_MODE_11A:
328 case AR5K_MODE_11A_TURBO:
329 /* 1..220, but 2GHz frequencies are filtered by check_channel */
330 size = 220 ;
331 chfreq = CHANNEL_5GHZ;
332 break;
333 case AR5K_MODE_11B:
334 case AR5K_MODE_11G:
335 case AR5K_MODE_11G_TURBO:
336 size = 26;
337 chfreq = CHANNEL_2GHZ;
338 break;
339 default:
340 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
341 return 0;
fa1c114f
JS		 342 }
343
8a63facc
BC		 344 for (i = 0, count = 0; i < size && max > 0; i++) {
345 ch = i + 1 ;
346 freq = ath5k_ieee2mhz(ch);
fa1c114f 347
8a63facc
BC		 348 /* Check if channel is supported by the chipset */
349 if (!ath5k_channel_ok(ah, freq, chfreq))
350 continue;
f59ac048 351
8a63facc
BC		 352 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
353 continue;
f59ac048 354
8a63facc
BC		 355 /* Write channel info and increment counter */
356 channels[count].center_freq = freq;
357 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
358 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
359 switch (mode) {
360 case AR5K_MODE_11A:
361 case AR5K_MODE_11G:
362 channels[count].hw_value = chfreq | CHANNEL_OFDM;
363 break;
364 case AR5K_MODE_11A_TURBO:
365 case AR5K_MODE_11G_TURBO:
366 channels[count].hw_value = chfreq |
367 CHANNEL_OFDM | CHANNEL_TURBO;
368 break;
369 case AR5K_MODE_11B:
370 channels[count].hw_value = CHANNEL_B;
371 }
fa1c114f 372
8a63facc
BC		 373 count++;
374 max--;
375 }
fa1c114f 376
8a63facc
BC		 377 return count;
378}
fa1c114f 379
8a63facc
BC		 380static void
381ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
382{
383 u8 i;
fa1c114f 384
8a63facc
BC		 385 for (i = 0; i < AR5K_MAX_RATES; i++)
386 sc->rate_idx[b->band][i] = -1;
fa1c114f 387
8a63facc
BC		 388 for (i = 0; i < b->n_bitrates; i++) {
389 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
390 if (b->bitrates[i].hw_value_short)
391 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 392 }
8a63facc 393}
fa1c114f 394
8a63facc
BC		 395static int
396ath5k_setup_bands(struct ieee80211_hw *hw)
397{
398 struct ath5k_softc *sc = hw->priv;
399 struct ath5k_hw *ah = sc->ah;
400 struct ieee80211_supported_band *sband;
401 int max_c, count_c = 0;
402 int i;
fa1c114f 403
8a63facc
BC		 404 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
405 max_c = ARRAY_SIZE(sc->channels);
db719718 406
8a63facc
BC		 407 /* 2GHz band */
408 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
409 sband->band = IEEE80211_BAND_2GHZ;
410 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 411
8a63facc
BC		 412 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
413 /* G mode */
414 memcpy(sband->bitrates, &ath5k_rates[0],
415 sizeof(struct ieee80211_rate) * 12);
416 sband->n_bitrates = 12;
2f7fe870 417
8a63facc
BC		 418 sband->channels = sc->channels;
419 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
420 AR5K_MODE_11G, max_c);
fa1c114f 421
8a63facc
BC		 422 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
423 count_c = sband->n_channels;
424 max_c -= count_c;
425 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
426 /* B mode */
427 memcpy(sband->bitrates, &ath5k_rates[0],
428 sizeof(struct ieee80211_rate) * 4);
429 sband->n_bitrates = 4;
fa1c114f 430
8a63facc
BC		 431 /* 5211 only supports B rates and uses 4bit rate codes
432 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
433 * fix them up here:
434 */
435 if (ah->ah_version == AR5K_AR5211) {
436 for (i = 0; i < 4; i++) {
437 sband->bitrates[i].hw_value =
438 sband->bitrates[i].hw_value & 0xF;
439 sband->bitrates[i].hw_value_short =
440 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 441 }
442 }
fa1c114f 443
8a63facc
BC		 444 sband->channels = sc->channels;
445 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
446 AR5K_MODE_11B, max_c);
fa1c114f 447
8a63facc
BC		 448 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
449 count_c = sband->n_channels;
450 max_c -= count_c;
451 }
452 ath5k_setup_rate_idx(sc, sband);
fa1c114f 453
8a63facc
BC		 454 /* 5GHz band, A mode */
455 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
456 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
457 sband->band = IEEE80211_BAND_5GHZ;
458 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 459
8a63facc
BC		 460 memcpy(sband->bitrates, &ath5k_rates[4],
461 sizeof(struct ieee80211_rate) * 8);
462 sband->n_bitrates = 8;
fa1c114f 463
8a63facc
BC		 464 sband->channels = &sc->channels[count_c];
465 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
466 AR5K_MODE_11A, max_c);
fa1c114f 467
8a63facc
BC		 468 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
469 }
470 ath5k_setup_rate_idx(sc, sband);
471
472 ath5k_debug_dump_bands(sc);
fa1c114f 473
fa1c114f
JS		 474 return 0;
475}
476
8a63facc
BC		 477/*
478 * Set/change channels. We always reset the chip.
479 * To accomplish this we must first cleanup any pending DMA,
480 * then restart stuff after a la ath5k_init.
481 *
482 * Called with sc->lock.
483 */
484static int
485ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
486{
487 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
488 "channel set, resetting (%u -> %u MHz)\n",
489 sc->curchan->center_freq, chan->center_freq);
8451d22d 490
8451d22d 491 /*
8a63facc
BC		 492 * To switch channels clear any pending DMA operations;
493 * wait long enough for the RX fifo to drain, reset the
494 * hardware at the new frequency, and then re-enable
495 * the relevant bits of the h/w.
8451d22d 496 */
8a63facc 497 return ath5k_reset(sc, chan);
fa1c114f 498}
fa1c114f 499
8a63facc
BC		 500static void
501ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 502{
8a63facc 503 sc->curmode = mode;
fa1c114f 504
8a63facc
BC		 505 if (mode == AR5K_MODE_11A) {
506 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
507 } else {
508 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
509 }
f769c36b 510}
fa1c114f 511
8a63facc
BC		 512static void
513ath5k_mode_setup(struct ath5k_softc *sc)
f769c36b 514{
fa1c114f 515 struct ath5k_hw *ah = sc->ah;
8a63facc 516 u32 rfilt;
f769c36b 517
8a63facc
BC		 518 /* configure rx filter */
519 rfilt = sc->filter_flags;
520 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f 521
8a63facc
BC		 522 if (ath5k_hw_hasbssidmask(ah))
523 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
a6668193 524
8a63facc
BC		 525 /* configure operational mode */
526 ath5k_hw_set_opmode(ah, sc->opmode);
fa1c114f 527
8a63facc
BC		 528 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
529 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
f769c36b
BC		 530}
531
8a63facc
BC		 532static inline int
533ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
fa1c114f 534{
8a63facc 535 int rix;
fa1c114f 536
8a63facc
BC		 537 /* return base rate on errors */
538 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
539 "hw_rix out of bounds: %x\n", hw_rix))
540 return 0;
fa1c114f 541
8a63facc
BC		 542 rix = sc->rate_idx[sc->curband->band][hw_rix];
543 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
544 rix = 0;
a6668193 545
8a63facc
BC		 546 return rix;
547}
fa1c114f 548
8a63facc
BC		 549/***************\
550* Buffers setup *
551\***************/
fa1c114f 552
8a63facc
BC		 553static
554struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
555{
556 struct ath_common *common = ath5k_hw_common(sc->ah);
557 struct sk_buff *skb;
fa1c114f
JS		 558
559 /*
8a63facc
BC		 560 * Allocate buffer with headroom_needed space for the
561 * fake physical layer header at the start.
fa1c114f 562 */
8a63facc
BC		 563 skb = ath_rxbuf_alloc(common,
564 common->rx_bufsize,
565 GFP_ATOMIC);
fa1c114f 566
8a63facc
BC		 567 if (!skb) {
568 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
569 common->rx_bufsize);
570 return NULL;
cec8db23 571 }
fa1c114f 572
8a63facc
BC		 573 *skb_addr = pci_map_single(sc->pdev,
574 skb->data, common->rx_bufsize,
575 PCI_DMA_FROMDEVICE);
576 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
577 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
578 dev_kfree_skb(skb);
579 return NULL;
fa1c114f 580 }
8a63facc
BC		 581 return skb;
582}
fa1c114f 583
8a63facc
BC		 584static int
585ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
586{
587 struct ath5k_hw *ah = sc->ah;
588 struct sk_buff *skb = bf->skb;
589 struct ath5k_desc *ds;
590 int ret;
5faaff74 591
8a63facc
BC		 592 if (!skb) {
593 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
594 if (!skb)
595 return -ENOMEM;
596 bf->skb = skb;
0e149cf5
BC		 597 }
598
8a63facc
BC		 599 /*
600 * Setup descriptors. For receive we always terminate
601 * the descriptor list with a self-linked entry so we'll
602 * not get overrun under high load (as can happen with a
603 * 5212 when ANI processing enables PHY error frames).
604 *
605 * To ensure the last descriptor is self-linked we create
606 * each descriptor as self-linked and add it to the end. As
607 * each additional descriptor is added the previous self-linked
608 * entry is "fixed" naturally. This should be safe even
609 * if DMA is happening. When processing RX interrupts we
610 * never remove/process the last, self-linked, entry on the
611 * descriptor list. This ensures the hardware always has
612 * someplace to write a new frame.
613 */
614 ds = bf->desc;
615 ds->ds_link = bf->daddr; /* link to self */
616 ds->ds_data = bf->skbaddr;
617 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
f769c36b 618 if (ret) {
8a63facc
BC		 619 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
620 return ret;
f769c36b
BC		 621 }
622
8a63facc
BC		 623 if (sc->rxlink != NULL)
624 *sc->rxlink = bf->daddr;
625 sc->rxlink = &ds->ds_link;
fa1c114f 626 return 0;
fa1c114f 627}
fa1c114f 628
8a63facc 629static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 630{
8a63facc
BC		 631 struct ieee80211_hdr *hdr;
632 enum ath5k_pkt_type htype;
633 __le16 fc;
f769c36b 634
8a63facc
BC		 635 hdr = (struct ieee80211_hdr *)skb->data;
636 fc = hdr->frame_control;
3a078876 637
8a63facc
BC		 638 if (ieee80211_is_beacon(fc))
639 htype = AR5K_PKT_TYPE_BEACON;
640 else if (ieee80211_is_probe_resp(fc))
641 htype = AR5K_PKT_TYPE_PROBE_RESP;
642 else if (ieee80211_is_atim(fc))
643 htype = AR5K_PKT_TYPE_ATIM;
644 else if (ieee80211_is_pspoll(fc))
645 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 646 else
8a63facc 647 htype = AR5K_PKT_TYPE_NORMAL;
40ca22ea 648
8a63facc 649 return htype;
fa1c114f
JS		 650}
651
8a63facc
BC		 652static int
653ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
654 struct ath5k_txq *txq, int padsize)
fa1c114f 655{
8a63facc
BC		 656 struct ath5k_hw *ah = sc->ah;
657 struct ath5k_desc *ds = bf->desc;
658 struct sk_buff *skb = bf->skb;
659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
660 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
661 struct ieee80211_rate *rate;
662 unsigned int mrr_rate[3], mrr_tries[3];
663 int i, ret;
664 u16 hw_rate;
665 u16 cts_rate = 0;
666 u16 duration = 0;
667 u8 rc_flags;
fa1c114f 668
8a63facc 669 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 670
8a63facc
BC		 671 /* XXX endianness */
672 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
673 PCI_DMA_TODEVICE);
fa1c114f 674
8a63facc 675 rate = ieee80211_get_tx_rate(sc->hw, info);
b618f6f8
JL		 676 if (!rate) {
677 ret = -EINVAL;
678 goto err_unmap;
679 }
fa1c114f 680
8a63facc
BC		 681 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
682 flags |= AR5K_TXDESC_NOACK;
fa1c114f 683
8a63facc
BC		 684 rc_flags = info->control.rates[0].flags;
685 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
686 rate->hw_value_short : rate->hw_value;
fa1c114f 687
8a63facc 688 pktlen = skb->len;
42639fcd 689
8a63facc
BC		 690 /* FIXME: If we are in g mode and rate is a CCK rate
691 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
692 * from tx power (value is in dB units already) */
693 if (info->control.hw_key) {
694 keyidx = info->control.hw_key->hw_key_idx;
695 pktlen += info->control.hw_key->icv_len;
696 }
697 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
698 flags |= AR5K_TXDESC_RTSENA;
699 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
700 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
701 sc->vif, pktlen, info));
702 }
703 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
704 flags |= AR5K_TXDESC_CTSENA;
705 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
706 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
707 sc->vif, pktlen, info));
708 }
709 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
710 ieee80211_get_hdrlen_from_skb(skb), padsize,
711 get_hw_packet_type(skb),
712 (sc->power_level * 2),
713 hw_rate,
714 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
715 cts_rate, duration);
716 if (ret)
717 goto err_unmap;
fa1c114f 718
8a63facc
BC		 719 memset(mrr_rate, 0, sizeof(mrr_rate));
720 memset(mrr_tries, 0, sizeof(mrr_tries));
721 for (i = 0; i < 3; i++) {
722 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
723 if (!rate)
400ec45a 724 break;
fa1c114f 725
8a63facc
BC		 726 mrr_rate[i] = rate->hw_value;
727 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 728 }
729
8a63facc
BC		 730 ath5k_hw_setup_mrr_tx_desc(ah, ds,
731 mrr_rate[0], mrr_tries[0],
732 mrr_rate[1], mrr_tries[1],
733 mrr_rate[2], mrr_tries[2]);
fa1c114f 734
8a63facc
BC		 735 ds->ds_link = 0;
736 ds->ds_data = bf->skbaddr;
42639fcd 737
8a63facc
BC		 738 spin_lock_bh(&txq->lock);
739 list_add_tail(&bf->list, &txq->q);
925e0b06 740 txq->txq_len++;
8a63facc
BC		 741 if (txq->link == NULL) /* is this first packet? */
742 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
743 else /* no, so only link it */
744 *txq->link = bf->daddr;
fa1c114f 745
8a63facc
BC		 746 txq->link = &ds->ds_link;
747 ath5k_hw_start_tx_dma(ah, txq->qnum);
748 mmiowb();
749 spin_unlock_bh(&txq->lock);
fa1c114f 750
8a63facc
BC		 751 return 0;
752err_unmap:
753 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
754 return ret;
fa1c114f
JS		 755}
756
8a63facc
BC		 757/*******************\
758* Descriptors setup *
759\*******************/
760
d8ee398d 761static int
8a63facc 762ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
63266a65 763{
8a63facc
BC		 764 struct ath5k_desc *ds;
765 struct ath5k_buf *bf;
766 dma_addr_t da;
767 unsigned int i;
768 int ret;
63266a65 769
8a63facc
BC		 770 /* allocate descriptors */
771 sc->desc_len = sizeof(struct ath5k_desc) *
772 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
773 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
774 if (sc->desc == NULL) {
775 ATH5K_ERR(sc, "can't allocate descriptors\n");
776 ret = -ENOMEM;
777 goto err;
778 }
779 ds = sc->desc;
780 da = sc->desc_daddr;
781 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
782 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
63266a65 783
8a63facc
BC		 784 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
785 sizeof(struct ath5k_buf), GFP_KERNEL);
786 if (bf == NULL) {
787 ATH5K_ERR(sc, "can't allocate bufptr\n");
788 ret = -ENOMEM;
789 goto err_free;
790 }
791 sc->bufptr = bf;
fa1c114f 792
8a63facc
BC		 793 INIT_LIST_HEAD(&sc->rxbuf);
794 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
795 bf->desc = ds;
796 bf->daddr = da;
797 list_add_tail(&bf->list, &sc->rxbuf);
798 }
d8ee398d 799
8a63facc
BC		 800 INIT_LIST_HEAD(&sc->txbuf);
801 sc->txbuf_len = ATH_TXBUF;
802 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
803 da += sizeof(*ds)) {
804 bf->desc = ds;
805 bf->daddr = da;
806 list_add_tail(&bf->list, &sc->txbuf);
63266a65 807 }
fa1c114f 808
8a63facc
BC		 809 /* beacon buffer */
810 bf->desc = ds;
811 bf->daddr = da;
812 sc->bbuf = bf;
fa1c114f 813
8a63facc
BC		 814 return 0;
815err_free:
816 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
817err:
818 sc->desc = NULL;
819 return ret;
63266a65
BR		 820}
821
8a63facc
BC		 822static void
823ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
fa1c114f 824{
8a63facc 825 struct ath5k_buf *bf;
fa1c114f 826
8a63facc
BC		 827 ath5k_txbuf_free_skb(sc, sc->bbuf);
828 list_for_each_entry(bf, &sc->txbuf, list)
829 ath5k_txbuf_free_skb(sc, bf);
830 list_for_each_entry(bf, &sc->rxbuf, list)
831 ath5k_rxbuf_free_skb(sc, bf);
d8ee398d 832
8a63facc
BC		 833 /* Free memory associated with all descriptors */
834 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
835 sc->desc = NULL;
836 sc->desc_daddr = 0;
fa1c114f 837
8a63facc
BC		 838 kfree(sc->bufptr);
839 sc->bufptr = NULL;
840 sc->bbuf = NULL;
fa1c114f 841}
fa1c114f 842
fa1c114f 843
8a63facc
BC		 844/**************\
845* Queues setup *
846\**************/
63266a65 847
8a63facc
BC		 848static struct ath5k_txq *
849ath5k_txq_setup(struct ath5k_softc *sc,
850 int qtype, int subtype)
fa1c114f 851{
8a63facc
BC		 852 struct ath5k_hw *ah = sc->ah;
853 struct ath5k_txq *txq;
854 struct ath5k_txq_info qi = {
855 .tqi_subtype = subtype,
de8af455
BR		 856 /* XXX: default values not correct for B and XR channels,
857 * but who cares? */
858 .tqi_aifs = AR5K_TUNE_AIFS,
859 .tqi_cw_min = AR5K_TUNE_CWMIN,
860 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 861 };
862 int qnum;
d8ee398d 863
e30eb4ab 864 /*
8a63facc
BC		 865 * Enable interrupts only for EOL and DESC conditions.
866 * We mark tx descriptors to receive a DESC interrupt
867 * when a tx queue gets deep; otherwise we wait for the
868 * EOL to reap descriptors. Note that this is done to
869 * reduce interrupt load and this only defers reaping
870 * descriptors, never transmitting frames. Aside from
871 * reducing interrupts this also permits more concurrency.
872 * The only potential downside is if the tx queue backs
873 * up in which case the top half of the kernel may backup
874 * due to a lack of tx descriptors.
e30eb4ab 875 */
8a63facc
BC		 876 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
877 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
878 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
879 if (qnum < 0) {
880 /*
881 * NB: don't print a message, this happens
882 * normally on parts with too few tx queues
63266a65 883 */
8a63facc
BC		 884 return ERR_PTR(qnum);
885 }
886 if (qnum >= ARRAY_SIZE(sc->txqs)) {
887 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
888 qnum, ARRAY_SIZE(sc->txqs));
889 ath5k_hw_release_tx_queue(ah, qnum);
890 return ERR_PTR(-EINVAL);
891 }
892 txq = &sc->txqs[qnum];
893 if (!txq->setup) {
894 txq->qnum = qnum;
895 txq->link = NULL;
896 INIT_LIST_HEAD(&txq->q);
897 spin_lock_init(&txq->lock);
898 txq->setup = true;
925e0b06 899 txq->txq_len = 0;
4edd761f 900 txq->txq_poll_mark = false;
923e5b3d 901 txq->txq_stuck = 0;
8a63facc
BC		 902 }
903 return &sc->txqs[qnum];
fa1c114f 904}
fa1c114f 905
8a63facc
BC		 906static int
907ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 908{
8a63facc 909 struct ath5k_txq_info qi = {
de8af455
BR		 910 /* XXX: default values not correct for B and XR channels,
911 * but who cares? */
912 .tqi_aifs = AR5K_TUNE_AIFS,
913 .tqi_cw_min = AR5K_TUNE_CWMIN,
914 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 915 /* NB: for dynamic turbo, don't enable any other interrupts */
916 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
917 };
d8ee398d 918
8a63facc 919 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f 920}
d8ee398d 921
8a63facc
BC		 922static int
923ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 924{
925 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 926 struct ath5k_txq_info qi;
927 int ret;
fa1c114f 928
8a63facc
BC		 929 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
930 if (ret)
931 goto err;
fa1c114f 932
8a63facc
BC		 933 if (sc->opmode == NL80211_IFTYPE_AP ||
934 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
935 /*
936 * Always burst out beacon and CAB traffic
937 * (aifs = cwmin = cwmax = 0)
938 */
939 qi.tqi_aifs = 0;
940 qi.tqi_cw_min = 0;
941 qi.tqi_cw_max = 0;
942 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
943 /*
944 * Adhoc mode; backoff between 0 and (2 * cw_min).
945 */
946 qi.tqi_aifs = 0;
947 qi.tqi_cw_min = 0;
de8af455 948 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 949 }
fa1c114f 950
8a63facc
BC		 951 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
952 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
953 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
d8ee398d 954
8a63facc
BC		 955 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
956 if (ret) {
957 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
958 "hardware queue!\n", __func__);
959 goto err;
d8ee398d 960 }
8a63facc
BC		 961 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
962 if (ret)
963 goto err;
d8ee398d 964
8a63facc
BC		 965 /* reconfigure cabq with ready time to 80% of beacon_interval */
966 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
967 if (ret)
968 goto err;
d8ee398d 969
8a63facc
BC		 970 qi.tqi_ready_time = (sc->bintval * 80) / 100;
971 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
972 if (ret)
973 goto err;
b7266047 974
8a63facc
BC		 975 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
976err:
977 return ret;
fa1c114f
JS		 978}
979
8a63facc
BC		 980static void
981ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
fa1c114f 982{
8a63facc 983 struct ath5k_buf *bf, *bf0;
d8ee398d 984
e30eb4ab 985 /*
8a63facc
BC		 986 * NB: this assumes output has been stopped and
987 * we do not need to block ath5k_tx_tasklet
e30eb4ab 988 */
8a63facc
BC		 989 spin_lock_bh(&txq->lock);
990 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
991 ath5k_debug_printtxbuf(sc, bf);
fa1c114f 992
8a63facc 993 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 994
8a63facc
BC		 995 spin_lock_bh(&sc->txbuflock);
996 list_move_tail(&bf->list, &sc->txbuf);
997 sc->txbuf_len++;
925e0b06 998 txq->txq_len--;
8a63facc 999 spin_unlock_bh(&sc->txbuflock);
d8ee398d 1000 }
8a63facc 1001 txq->link = NULL;
4edd761f 1002 txq->txq_poll_mark = false;
8a63facc 1003 spin_unlock_bh(&txq->lock);
fa1c114f
JS		 1004}
1005
8a63facc
BC		 1006/*
1007 * Drain the transmit queues and reclaim resources.
1008 */
fa1c114f 1009static void
8a63facc 1010ath5k_txq_cleanup(struct ath5k_softc *sc)
fa1c114f
JS		 1011{
1012 struct ath5k_hw *ah = sc->ah;
8a63facc 1013 unsigned int i;
fa1c114f 1014
8a63facc
BC		 1015 /* XXX return value */
1016 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1017 /* don't touch the hardware if marked invalid */
1018 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1019 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1020 ath5k_hw_get_txdp(ah, sc->bhalq));
1021 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1022 if (sc->txqs[i].setup) {
1023 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1024 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1025 "link %p\n",
1026 sc->txqs[i].qnum,
1027 ath5k_hw_get_txdp(ah,
1028 sc->txqs[i].qnum),
1029 sc->txqs[i].link);
1030 }
0452d4a5 1031 }
fa1c114f 1032
8a63facc
BC		 1033 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1034 if (sc->txqs[i].setup)
1035 ath5k_txq_drainq(sc, &sc->txqs[i]);
fa1c114f
JS		 1036}
1037
8a63facc
BC		 1038static void
1039ath5k_txq_release(struct ath5k_softc *sc)
63266a65 1040{
8a63facc
BC		 1041 struct ath5k_txq *txq = sc->txqs;
1042 unsigned int i;
b7266047 1043
8a63facc
BC		 1044 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1045 if (txq->setup) {
1046 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1047 txq->setup = false;
1048 }
d8ee398d
LR		 1049}
1050
b6ea0356 1051
8a63facc
BC		 1052/*************\
1053* RX Handling *
1054\*************/
b6ea0356 1055
8a63facc
BC		 1056/*
1057 * Enable the receive h/w following a reset.
1058 */
fa1c114f 1059static int
8a63facc 1060ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1061{
1062 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1063 struct ath_common *common = ath5k_hw_common(ah);
1064 struct ath5k_buf *bf;
b5eae9ff 1065 int ret;
fa1c114f 1066
8a63facc 1067 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1068
8a63facc
BC		 1069 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1070 common->cachelsz, common->rx_bufsize);
2f7fe870 1071
8a63facc
BC		 1072 spin_lock_bh(&sc->rxbuflock);
1073 sc->rxlink = NULL;
1074 list_for_each_entry(bf, &sc->rxbuf, list) {
1075 ret = ath5k_rxbuf_setup(sc, bf);
1076 if (ret != 0) {
1077 spin_unlock_bh(&sc->rxbuflock);
1078 goto err;
1079 }
0452d4a5 1080 }
8a63facc
BC		 1081 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1082 ath5k_hw_set_rxdp(ah, bf->daddr);
1083 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1084
8a63facc
BC		 1085 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1086 ath5k_mode_setup(sc); /* set filters, etc. */
1087 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f 1088
fa1c114f 1089 return 0;
8a63facc 1090err:
fa1c114f 1091 return ret;
fa1c114f
JS		 1092}
1093
8a63facc
BC		 1094/*
1095 * Disable the receive h/w in preparation for a reset.
1096 */
1097static void
1098ath5k_rx_stop(struct ath5k_softc *sc)
2ac2927a 1099{
8a63facc 1100 struct ath5k_hw *ah = sc->ah;
2ac2927a 1101
8a63facc
BC		 1102 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1103 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1104 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
2ac2927a 1105
8a63facc 1106 ath5k_debug_printrxbuffs(sc, ah);
2ac2927a
BC		 1107}
1108
8a63facc
BC		 1109static unsigned int
1110ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1111 struct ath5k_rx_status *rs)
fa1c114f
JS		 1112{
1113 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1114 struct ath_common *common = ath5k_hw_common(ah);
1115 struct ieee80211_hdr *hdr = (void *)skb->data;
1116 unsigned int keyix, hlen;
fa1c114f 1117
8a63facc
BC		 1118 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1119 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1120 return RX_FLAG_DECRYPTED;
e039fa4a 1121
8a63facc
BC		 1122 /* Apparently when a default key is used to decrypt the packet
1123 the hw does not set the index used to decrypt. In such cases
1124 get the index from the packet. */
1125 hlen = ieee80211_hdrlen(hdr->frame_control);
1126 if (ieee80211_has_protected(hdr->frame_control) &&
1127 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1128 skb->len >= hlen + 4) {
1129 keyix = skb->data[hlen + 3] >> 6;
fa1c114f 1130
8a63facc
BC		 1131 if (test_bit(keyix, common->keymap))
1132 return RX_FLAG_DECRYPTED;
d8e1ba76 1133 }
8902ff4e 1134
fa1c114f 1135 return 0;
fa1c114f 1136}
fa1c114f 1137
8902ff4e 1138
fa1c114f 1139static void
8a63facc
BC		 1140ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1141 struct ieee80211_rx_status *rxs)
fa1c114f 1142{
8a63facc
BC		 1143 struct ath_common *common = ath5k_hw_common(sc->ah);
1144 u64 tsf, bc_tstamp;
1145 u32 hw_tu;
1146 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1147
8a63facc
BC		 1148 if (ieee80211_is_beacon(mgmt->frame_control) &&
1149 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1150 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1151 /*
1152 * Received an IBSS beacon with the same BSSID. Hardware *must*
1153 * have updated the local TSF. We have to work around various
1154 * hardware bugs, though...
1155 */
1156 tsf = ath5k_hw_get_tsf64(sc->ah);
1157 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1158 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1159
8a63facc
BC		 1160 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1161 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1162 (unsigned long long)bc_tstamp,
1163 (unsigned long long)rxs->mactime,
1164 (unsigned long long)(rxs->mactime - bc_tstamp),
1165 (unsigned long long)tsf);
2f7fe870 1166
8a63facc
BC		 1167 /*
1168 * Sometimes the HW will give us a wrong tstamp in the rx
1169 * status, causing the timestamp extension to go wrong.
1170 * (This seems to happen especially with beacon frames bigger
1171 * than 78 byte (incl. FCS))
1172 * But we know that the receive timestamp must be later than the
1173 * timestamp of the beacon since HW must have synced to that.
1174 *
1175 * NOTE: here we assume mactime to be after the frame was
1176 * received, not like mac80211 which defines it at the start.
1177 */
1178 if (bc_tstamp > rxs->mactime) {
1179 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1180 "fixing mactime from %llx to %llx\n",
1181 (unsigned long long)rxs->mactime,
1182 (unsigned long long)tsf);
1183 rxs->mactime = tsf;
1184 }
2f7fe870 1185
8a63facc
BC		 1186 /*
1187 * Local TSF might have moved higher than our beacon timers,
1188 * in that case we have to update them to continue sending
1189 * beacons. This also takes care of synchronizing beacon sending
1190 * times with other stations.
1191 */
1192 if (hw_tu >= sc->nexttbtt)
1193 ath5k_beacon_update_timers(sc, bc_tstamp);
1194 }
1195}
2f7fe870 1196
8a63facc
BC		 1197static void
1198ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1199{
1200 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1201 struct ath5k_hw *ah = sc->ah;
1202 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1203
8a63facc
BC		 1204 /* only beacons from our BSSID */
1205 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1206 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1207 return;
fa1c114f 1208
8a63facc
BC		 1209 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1210 rssi);
fa1c114f 1211
8a63facc
BC		 1212 /* in IBSS mode we should keep RSSI statistics per neighbour */
1213 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
fa1c114f
JS		 1214}
1215
8a63facc
BC		 1216/*
1217 * Compute padding position. skb must contain an IEEE 802.11 frame
1218 */
1219static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1220{
8a63facc
BC		 1221 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1222 __le16 frame_control = hdr->frame_control;
1223 int padpos = 24;
fa1c114f 1224
8a63facc
BC		 1225 if (ieee80211_has_a4(frame_control)) {
1226 padpos += ETH_ALEN;
fa1c114f 1227 }
8a63facc
BC		 1228 if (ieee80211_is_data_qos(frame_control)) {
1229 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1230 }
8a63facc
BC		 1231
1232 return padpos;
fa1c114f
JS		 1233}
1234
8a63facc
BC		 1235/*
1236 * This function expects an 802.11 frame and returns the number of
1237 * bytes added, or -1 if we don't have enough header room.
1238 */
1239static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1240{
8a63facc
BC		 1241 int padpos = ath5k_common_padpos(skb);
1242 int padsize = padpos & 3;
fa1c114f 1243
8a63facc 1244 if (padsize && skb->len>padpos) {
fa1c114f 1245
8a63facc
BC		 1246 if (skb_headroom(skb) < padsize)
1247 return -1;
fa1c114f 1248
8a63facc
BC		 1249 skb_push(skb, padsize);
1250 memmove(skb->data, skb->data+padsize, padpos);
1251 return padsize;
fa1c114f
JS		 1252 }
1253
8a63facc
BC		 1254 return 0;
1255}
fa1c114f 1256
8a63facc
BC		 1257/*
1258 * The MAC header is padded to have 32-bit boundary if the
1259 * packet payload is non-zero. The general calculation for
1260 * padsize would take into account odd header lengths:
1261 * padsize = 4 - (hdrlen & 3); however, since only
1262 * even-length headers are used, padding can only be 0 or 2
1263 * bytes and we can optimize this a bit. We must not try to
1264 * remove padding from short control frames that do not have a
1265 * payload.
1266 *
1267 * This function expects an 802.11 frame and returns the number of
1268 * bytes removed.
1269 */
1270static int ath5k_remove_padding(struct sk_buff *skb)
1271{
1272 int padpos = ath5k_common_padpos(skb);
1273 int padsize = padpos & 3;
6d91e1d8 1274
8a63facc
BC		 1275 if (padsize && skb->len>=padpos+padsize) {
1276 memmove(skb->data + padsize, skb->data, padpos);
1277 skb_pull(skb, padsize);
1278 return padsize;
fa1c114f 1279 }
fa1c114f
JS		 1280
1281 return 0;
fa1c114f
JS		 1282}
1283
1284static void
8a63facc
BC		 1285ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1286 struct ath5k_rx_status *rs)
fa1c114f 1287{
8a63facc 1288 struct ieee80211_rx_status *rxs;
fa1c114f 1289
8a63facc 1290 ath5k_remove_padding(skb);
fa1c114f 1291
8a63facc 1292 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 1293
8a63facc
BC		 1294 rxs->flag = 0;
1295 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1296 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f 1297
fa1c114f 1298 /*
8a63facc
BC		 1299 * always extend the mac timestamp, since this information is
1300 * also needed for proper IBSS merging.
1301 *
1302 * XXX: it might be too late to do it here, since rs_tstamp is
1303 * 15bit only. that means TSF extension has to be done within
1304 * 32768usec (about 32ms). it might be necessary to move this to
1305 * the interrupt handler, like it is done in madwifi.
1306 *
1307 * Unfortunately we don't know when the hardware takes the rx
1308 * timestamp (beginning of phy frame, data frame, end of rx?).
1309 * The only thing we know is that it is hardware specific...
1310 * On AR5213 it seems the rx timestamp is at the end of the
1311 * frame, but i'm not sure.
1312 *
1313 * NOTE: mac80211 defines mactime at the beginning of the first
1314 * data symbol. Since we don't have any time references it's
1315 * impossible to comply to that. This affects IBSS merge only
1316 * right now, so it's not too bad...
fa1c114f 1317 */
8a63facc
BC		 1318 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1319 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1320
8a63facc
BC		 1321 rxs->freq = sc->curchan->center_freq;
1322 rxs->band = sc->curband->band;
fa1c114f 1323
8a63facc 1324 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1325
8a63facc 1326 rxs->antenna = rs->rs_antenna;
fa1c114f 1327
8a63facc
BC		 1328 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1329 sc->stats.antenna_rx[rs->rs_antenna]++;
1330 else
1331 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1332
8a63facc
BC		 1333 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1334 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1335
8a63facc
BC		 1336 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1337 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1338 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1339
8a63facc 1340 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1341
8a63facc 1342 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1343
8a63facc
BC		 1344 /* check beacons in IBSS mode */
1345 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1346 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1347
8a63facc
BC		 1348 ieee80211_rx(sc->hw, skb);
1349}
a951ae21 1350
8a63facc
BC		 1351/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1352 *
1353 * Check if we want to further process this frame or not. Also update
1354 * statistics. Return true if we want this frame, false if not.
fa1c114f 1355 */
8a63facc
BC		 1356static bool
1357ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1358{
8a63facc 1359 sc->stats.rx_all_count++;
fa1c114f 1360
8a63facc
BC		 1361 if (unlikely(rs->rs_status)) {
1362 if (rs->rs_status & AR5K_RXERR_CRC)
1363 sc->stats.rxerr_crc++;
1364 if (rs->rs_status & AR5K_RXERR_FIFO)
1365 sc->stats.rxerr_fifo++;
1366 if (rs->rs_status & AR5K_RXERR_PHY) {
1367 sc->stats.rxerr_phy++;
1368 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1369 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1370 return false;
1371 }
1372 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1373 /*
1374 * Decrypt error. If the error occurred
1375 * because there was no hardware key, then
1376 * let the frame through so the upper layers
1377 * can process it. This is necessary for 5210
1378 * parts which have no way to setup a ``clear''
1379 * key cache entry.
1380 *
1381 * XXX do key cache faulting
1382 */
1383 sc->stats.rxerr_decrypt++;
1384 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1385 !(rs->rs_status & AR5K_RXERR_CRC))
1386 return true;
1387 }
1388 if (rs->rs_status & AR5K_RXERR_MIC) {
1389 sc->stats.rxerr_mic++;
1390 return true;
fa1c114f 1391 }
6d91e1d8 1392
8a63facc
BC		 1393 /* reject any frames with non-crypto errors */
1394 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1395 return false;
fa1c114f 1396 }
a951ae21 1397
8a63facc
BC		 1398 if (unlikely(rs->rs_more)) {
1399 sc->stats.rxerr_jumbo++;
1400 return false;
1401 }
1402 return true;
fa1c114f
JS		 1403}
1404
1405static void
8a63facc 1406ath5k_tasklet_rx(unsigned long data)
fa1c114f 1407{
8a63facc
BC		 1408 struct ath5k_rx_status rs = {};
1409 struct sk_buff *skb, *next_skb;
1410 dma_addr_t next_skb_addr;
1411 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1412 struct ath5k_hw *ah = sc->ah;
1413 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1414 struct ath5k_buf *bf;
1415 struct ath5k_desc *ds;
1416 int ret;
fa1c114f 1417
8a63facc
BC		 1418 spin_lock(&sc->rxbuflock);
1419 if (list_empty(&sc->rxbuf)) {
1420 ATH5K_WARN(sc, "empty rx buf pool\n");
1421 goto unlock;
1422 }
1423 do {
1424 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1425 BUG_ON(bf->skb == NULL);
1426 skb = bf->skb;
1427 ds = bf->desc;
fa1c114f 1428
8a63facc
BC		 1429 /* bail if HW is still using self-linked descriptor */
1430 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1431 break;
fa1c114f 1432
8a63facc
BC		 1433 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1434 if (unlikely(ret == -EINPROGRESS))
1435 break;
1436 else if (unlikely(ret)) {
1437 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1438 sc->stats.rxerr_proc++;
1439 break;
1440 }
fa1c114f 1441
8a63facc
BC		 1442 if (ath5k_receive_frame_ok(sc, &rs)) {
1443 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1444
8a63facc
BC		 1445 /*
1446 * If we can't replace bf->skb with a new skb under
1447 * memory pressure, just skip this packet
1448 */
1449 if (!next_skb)
1450 goto next;
fa1c114f 1451
8a63facc
BC		 1452 pci_unmap_single(sc->pdev, bf->skbaddr,
1453 common->rx_bufsize,
1454 PCI_DMA_FROMDEVICE);
fa1c114f 1455
8a63facc 1456 skb_put(skb, rs.rs_datalen);
fa1c114f 1457
8a63facc 1458 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1459
8a63facc
BC		 1460 bf->skb = next_skb;
1461 bf->skbaddr = next_skb_addr;
fa1c114f 1462 }
8a63facc
BC		 1463next:
1464 list_move_tail(&bf->list, &sc->rxbuf);
1465 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1466unlock:
1467 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1468}
1469
1470
fa1c114f 1471/*************\
8a63facc 1472* TX Handling *
fa1c114f
JS		 1473\*************/
1474
8a63facc
BC		 1475static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1476 struct ath5k_txq *txq)
fa1c114f 1477{
8a63facc 1478 struct ath5k_softc *sc = hw->priv;
fa1c114f 1479 struct ath5k_buf *bf;
8a63facc
BC		 1480 unsigned long flags;
1481 int padsize;
fa1c114f 1482
8a63facc 1483 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
fa1c114f 1484
8a63facc
BC		 1485 /*
1486 * The hardware expects the header padded to 4 byte boundaries.
1487 * If this is not the case, we add the padding after the header.
1488 */
1489 padsize = ath5k_add_padding(skb);
1490 if (padsize < 0) {
1491 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1492 " headroom to pad");
1493 goto drop_packet;
1494 }
fa1c114f 1495
925e0b06
BR		 1496 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1497 ieee80211_stop_queue(hw, txq->qnum);
1498
8a63facc
BC		 1499 spin_lock_irqsave(&sc->txbuflock, flags);
1500 if (list_empty(&sc->txbuf)) {
1501 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1502 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1503 ieee80211_stop_queues(hw);
8a63facc 1504 goto drop_packet;
fa1c114f 1505 }
8a63facc
BC		 1506 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1507 list_del(&bf->list);
1508 sc->txbuf_len--;
1509 if (list_empty(&sc->txbuf))
1510 ieee80211_stop_queues(hw);
1511 spin_unlock_irqrestore(&sc->txbuflock, flags);
fa1c114f 1512
8a63facc 1513 bf->skb = skb;
fa1c114f 1514
8a63facc
BC		 1515 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1516 bf->skb = NULL;
1517 spin_lock_irqsave(&sc->txbuflock, flags);
1518 list_add_tail(&bf->list, &sc->txbuf);
1519 sc->txbuf_len++;
1520 spin_unlock_irqrestore(&sc->txbuflock, flags);
1521 goto drop_packet;
8127fbdc 1522 }
8a63facc 1523 return NETDEV_TX_OK;
8127fbdc 1524
8a63facc
BC		 1525drop_packet:
1526 dev_kfree_skb_any(skb);
1527 return NETDEV_TX_OK;
fa1c114f
JS		 1528}
1529
fa1c114f 1530static void
1440401e
BR		 1531ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1532 struct ath5k_tx_status *ts)
fa1c114f 1533{
1440401e
BR		 1534 struct ieee80211_tx_info *info;
1535 int i;
fa1c114f 1536
1440401e
BR		 1537 sc->stats.tx_all_count++;
1538 info = IEEE80211_SKB_CB(skb);
fa1c114f 1539
1440401e
BR		 1540 ieee80211_tx_info_clear_status(info);
1541 for (i = 0; i < 4; i++) {
1542 struct ieee80211_tx_rate *r =
1543 &info->status.rates[i];
fa1c114f 1544
1440401e
BR		 1545 if (ts->ts_rate[i]) {
1546 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1547 r->count = ts->ts_retry[i];
1548 } else {
1549 r->idx = -1;
1550 r->count = 0;
1551 }
1552 }
fa1c114f 1553
1440401e
BR		 1554 /* count the successful attempt as well */
1555 info->status.rates[ts->ts_final_idx].count++;
fa1c114f 1556
1440401e
BR		 1557 if (unlikely(ts->ts_status)) {
1558 sc->stats.ack_fail++;
1559 if (ts->ts_status & AR5K_TXERR_FILT) {
1560 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1561 sc->stats.txerr_filt++;
1562 }
1563 if (ts->ts_status & AR5K_TXERR_XRETRY)
1564 sc->stats.txerr_retry++;
1565 if (ts->ts_status & AR5K_TXERR_FIFO)
1566 sc->stats.txerr_fifo++;
1567 } else {
1568 info->flags |= IEEE80211_TX_STAT_ACK;
1569 info->status.ack_signal = ts->ts_rssi;
fa1c114f
JS		 1570 }
1571
1440401e
BR		 1572 /*
1573 * Remove MAC header padding before giving the frame
1574 * back to mac80211.
1575 */
1576 ath5k_remove_padding(skb);
1577
1578 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1579 sc->stats.antenna_tx[ts->ts_antenna]++;
1580 else
1581 sc->stats.antenna_tx[0]++; /* invalid */
fa1c114f 1582
1440401e
BR		 1583 ieee80211_tx_status(sc->hw, skb);
1584}
036cd1ec
BR		 1585
1586static void
8a63facc 1587ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
036cd1ec 1588{
8a63facc
BC		 1589 struct ath5k_tx_status ts = {};
1590 struct ath5k_buf *bf, *bf0;
1591 struct ath5k_desc *ds;
1592 struct sk_buff *skb;
1440401e 1593 int ret;
036cd1ec 1594
8a63facc
BC		 1595 spin_lock(&txq->lock);
1596 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
6ba81c2c 1597
23413296 1598 txq->txq_poll_mark = false;
6ba81c2c 1599
23413296
BR		 1600 /* skb might already have been processed last time. */
1601 if (bf->skb != NULL) {
1602 ds = bf->desc;
1603
1604 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1605 if (unlikely(ret == -EINPROGRESS))
1606 break;
1607 else if (unlikely(ret)) {
1608 ATH5K_ERR(sc,
1609 "error %d while processing "
1610 "queue %u\n", ret, txq->qnum);
1611 break;
1612 }
1613
1614 skb = bf->skb;
1615 bf->skb = NULL;
1616 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1617 PCI_DMA_TODEVICE);
1618 ath5k_tx_frame_completed(sc, skb, &ts);
036cd1ec 1619 }
6ba81c2c
BR		 1620
1621 /*
8a63facc
BC		 1622 * It's possible that the hardware can say the buffer is
1623 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1624 * host memory and moved on.
1625 * Always keep the last descriptor to avoid HW races...
6ba81c2c 1626 */
23413296
BR		 1627 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1628 spin_lock(&sc->txbuflock);
1629 list_move_tail(&bf->list, &sc->txbuf);
1630 sc->txbuf_len++;
1631 txq->txq_len--;
1632 spin_unlock(&sc->txbuflock);
8a63facc 1633 }
036cd1ec 1634 }
fa1c114f 1635 spin_unlock(&txq->lock);
925e0b06
BR		 1636 if (txq->txq_len < ATH5K_TXQ_LEN_LOW)
1637 ieee80211_wake_queue(sc->hw, txq->qnum);
036cd1ec
BR		 1638}
1639
b4ea449d 1640static void
fa1c114f 1641ath5k_tasklet_tx(unsigned long data)
b4ea449d 1642{
8784d2ee 1643 int i;
fa1c114f
JS		 1644 struct ath5k_softc *sc = (void *)data;
1645
8784d2ee
BC		 1646 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1647 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1648 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1649}
1650
1651
fa1c114f
JS		 1652/*****************\
1653* Beacon handling *
1654\*****************/
1655
1656/*
1657 * Setup the beacon frame for transmit.
1658 */
1659static int
e039fa4a 1660ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1661{
1662 struct sk_buff *skb = bf->skb;
a888d52d 1663 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
b4ea449d 1664 struct ath5k_hw *ah = sc->ah;
fa1c114f 1665 struct ath5k_desc *ds;
2bed03eb
NK		 1666 int ret = 0;
1667 u8 antenna;
fa1c114f 1668 u32 flags;
8127fbdc 1669 const int padsize = 0;
b4ea449d 1670
fa1c114f
JS		 1671 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1672 PCI_DMA_TODEVICE);
1673 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1674 "skbaddr %llx\n", skb, skb->data, skb->len,
1675 (unsigned long long)bf->skbaddr);
8d8bb39b 1676 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1677 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1678 return -EIO;
1679 }
b4ea449d 1680
fa1c114f 1681 ds = bf->desc;
2bed03eb 1682 antenna = ah->ah_tx_ant;
b4ea449d 1683
fa1c114f 1684 flags = AR5K_TXDESC_NOACK;
05c914fe 1685 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1686 ds->ds_link = bf->daddr; /* self-linked */
1687 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1688 } else
fa1c114f 1689 ds->ds_link = 0;
2bed03eb
NK		 1690
1691 /*
1692 * If we use multiple antennas on AP and use
1693 * the Sectored AP scenario, switch antenna every
1694 * 4 beacons to make sure everybody hears our AP.
1695 * When a client tries to associate, hw will keep
1696 * track of the tx antenna to be used for this client
1697 * automaticaly, based on ACKed packets.
1698 *
1699 * Note: AP still listens and transmits RTS on the
1700 * default antenna which is supposed to be an omni.
1701 *
1702 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1703 * multiple antennas (1 omni -- the default -- and 14
1704 * sectors), so if we choose to actually support this
1705 * mode, we need to allow the user to set how many antennas
1706 * we have and tweak the code below to send beacons
1707 * on all of them.
2bed03eb
NK		 1708 */
1709 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1710 antenna = sc->bsent & 4 ? 2 : 1;
1711
fa1c114f 1712
8f655dde
NK		 1713 /* FIXME: If we are in g mode and rate is a CCK rate
1714 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1715 * from tx power (value is in dB units already) */
fa1c114f 1716 ds->ds_data = bf->skbaddr;
281c56dd 1717 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1718 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1719 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1720 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1721 1, AR5K_TXKEYIX_INVALID,
400ec45a 1722 antenna, flags, 0, 0);
fa1c114f
JS		 1723 if (ret)
1724 goto err_unmap;
1725
1726 return 0;
1727err_unmap:
1728 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1729 return ret;
b4ea449d
BR		 1730}
1731
8127fbdc 1732/*
8a63facc
BC		 1733 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1734 * this is called only once at config_bss time, for AP we do it every
1735 * SWBA interrupt so that the TIM will reflect buffered frames.
1736 *
1737 * Called with the beacon lock.
8127fbdc 1738 */
8a63facc
BC		 1739static int
1740ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
8127fbdc 1741{
8a63facc
BC		 1742 int ret;
1743 struct ath5k_softc *sc = hw->priv;
1744 struct sk_buff *skb;
8127fbdc 1745
8a63facc
BC		 1746 if (WARN_ON(!vif)) {
1747 ret = -EINVAL;
1748 goto out;
8127fbdc 1749 }
8a63facc
BC		 1750
1751 skb = ieee80211_beacon_get(hw, vif);
1752
1753 if (!skb) {
1754 ret = -ENOMEM;
1755 goto out;
8127fbdc
BP		 1756 }
1757
8a63facc
BC		 1758 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1759
1760 ath5k_txbuf_free_skb(sc, sc->bbuf);
1761 sc->bbuf->skb = skb;
1762 ret = ath5k_beacon_setup(sc, sc->bbuf);
1763 if (ret)
1764 sc->bbuf->skb = NULL;
1765out:
1766 return ret;
8127fbdc
BP		 1767}
1768
1769/*
fa1c114f
JS		 1770 * Transmit a beacon frame at SWBA. Dynamic updates to the
1771 * frame contents are done as needed and the slot time is
1772 * also adjusted based on current state.
1773 *
5faaff74
BC		 1774 * This is called from software irq context (beacontq tasklets)
1775 * or user context from ath5k_beacon_config.
8127fbdc 1776 */
fa1c114f
JS		 1777static void
1778ath5k_beacon_send(struct ath5k_softc *sc)
8127fbdc 1779{
fa1c114f
JS		 1780 struct ath5k_buf *bf = sc->bbuf;
1781 struct ath5k_hw *ah = sc->ah;
cec8db23 1782 struct sk_buff *skb;
fa1c114f 1783
be9b7259 1784 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1785
4afd89d9 1786 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION)) {
fa1c114f
JS		 1787 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1788 return;
1789 }
1790 /*
1791 * Check if the previous beacon has gone out. If
a180a130 1792 * not, don't don't try to post another: skip this
fa1c114f
JS		 1793 * period and wait for the next. Missed beacons
1794 * indicate a problem and should not occur. If we
1795 * miss too many consecutive beacons reset the device.
1796 */
1797 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1798 sc->bmisscount++;
be9b7259 1799 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1800 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1801 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1802 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1803 "stuck beacon time (%u missed)\n",
1804 sc->bmisscount);
8d67a031
BR		 1805 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1806 "stuck beacon, resetting\n");
5faaff74 1807 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1808 }
1809 return;
1810 }
1811 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1812 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1813 "resume beacon xmit after %u misses\n",
1814 sc->bmisscount);
1815 sc->bmisscount = 0;
1816 }
1817
1818 /*
1819 * Stop any current dma and put the new frame on the queue.
1820 * This should never fail since we check above that no frames
1821 * are still pending on the queue.
1822 */
1823 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 1824 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1825 /* NB: hw still stops DMA, so proceed */
1826 }
8127fbdc 1827
1071db86
BC		 1828 /* refresh the beacon for AP mode */
1829 if (sc->opmode == NL80211_IFTYPE_AP)
1830 ath5k_beacon_update(sc->hw, sc->vif);
8127fbdc 1831
c6e387a2
NK		 1832 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1833 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1834 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f 1835 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
8127fbdc 1836
cec8db23
BC		 1837 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
1838 while (skb) {
1839 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1840 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
8127fbdc
BP		 1841 }
1842
fa1c114f 1843 sc->bsent++;
8127fbdc
BP		 1844}
1845
9804b98d
BR		 1846/**
1847 * ath5k_beacon_update_timers - update beacon timers
a180a130 1848 *
9804b98d
BR		 1849 * @sc: struct ath5k_softc pointer we are operating on
1850 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1851 * beacon timer update based on the current HW TSF.
1852 *
1853 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1854 * of a received beacon or the current local hardware TSF and write it to the
1855 * beacon timer registers.
1856 *
1857 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1858 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1859 * when we otherwise know we have to update the timers, but we keep it in this
1860 * function to have it all together in one place.
8127fbdc 1861 */
fa1c114f 1862static void
9804b98d 1863ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
8127fbdc 1864{
fa1c114f 1865 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1866 u32 nexttbtt, intval, hw_tu, bc_tu;
1867 u64 hw_tsf;
8127fbdc 1868
fa1c114f
JS		 1869 intval = sc->bintval & AR5K_BEACON_PERIOD;
1870 if (WARN_ON(!intval))
1871 return;
8127fbdc 1872
9804b98d
BR		 1873 /* beacon TSF converted to TU */
1874 bc_tu = TSF_TO_TU(bc_tsf);
8127fbdc 1875
9804b98d
BR		 1876 /* current TSF converted to TU */
1877 hw_tsf = ath5k_hw_get_tsf64(ah);
1878 hw_tu = TSF_TO_TU(hw_tsf);
8a89f063 1879
9804b98d
BR		 1880#define FUDGE 3
1881 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
1882 if (bc_tsf == -1) {
1883 /*
1884 * no beacons received, called internally.
1885 * just need to refresh timers based on HW TSF.
1886 */
1887 nexttbtt = roundup(hw_tu + FUDGE, intval);
1888 } else if (bc_tsf == 0) {
1889 /*
1890 * no beacon received, probably called by ath5k_reset_tsf().
1891 * reset TSF to start with 0.
1892 */
1893 nexttbtt = intval;
1894 intval |= AR5K_BEACON_RESET_TSF;
1895 } else if (bc_tsf > hw_tsf) {
1896 /*
1897 * beacon received, SW merge happend but HW TSF not yet updated.
1898 * not possible to reconfigure timers yet, but next time we
1899 * receive a beacon with the same BSSID, the hardware will
1900 * automatically update the TSF and then we need to reconfigure
1901 * the timers.
1902 */
1903 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1904 "need to wait for HW TSF sync\n");
1905 return;
1906 } else {
1907 /*
1908 * most important case for beacon synchronization between STA.
1909 *
1910 * beacon received and HW TSF has been already updated by HW.
1911 * update next TBTT based on the TSF of the beacon, but make
1912 * sure it is ahead of our local TSF timer.
1913 */
1914 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
1915 }
1916#undef FUDGE
8a89f063 1917
036cd1ec 1918 sc->nexttbtt = nexttbtt;
8a89f063 1919
fa1c114f 1920 intval |= AR5K_BEACON_ENA;
fa1c114f 1921 ath5k_hw_init_beacon(ah, nexttbtt, intval);
8a89f063
BR		 1922
1923 /*
9804b98d
BR		 1924 * debugging output last in order to preserve the time critical aspect
1925 * of this function
8a89f063 1926 */
9804b98d
BR		 1927 if (bc_tsf == -1)
1928 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1929 "reconfigured timers based on HW TSF\n");
1930 else if (bc_tsf == 0)
1931 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1932 "reset HW TSF and timers\n");
8a89f063 1933 else
9804b98d
BR		 1934 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1935 "updated timers based on beacon TSF\n");
8a89f063 1936
9804b98d 1937 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 1938 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
1939 (unsigned long long) bc_tsf,
1940 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 1941 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
1942 intval & AR5K_BEACON_PERIOD,
1943 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
1944 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
8a89f063
BR		 1945}
1946
036cd1ec
BR		 1947/**
1948 * ath5k_beacon_config - Configure the beacon queues and interrupts
02a78b42 1949 *
036cd1ec 1950 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 1951 *
036cd1ec 1952 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 1953 * interrupts to detect TSF updates only.
02a78b42 1954 */
fa1c114f
JS		 1955static void
1956ath5k_beacon_config(struct ath5k_softc *sc)
02a78b42 1957{
fa1c114f 1958 struct ath5k_hw *ah = sc->ah;
b5f03956 1959 unsigned long flags;
02a78b42 1960
21800491 1961 spin_lock_irqsave(&sc->block, flags);
fa1c114f 1962 sc->bmisscount = 0;
dc1968e7 1963 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
02a78b42 1964
21800491 1965 if (sc->enable_beacon) {
fa1c114f 1966 /*
036cd1ec
BR		 1967 * In IBSS mode we use a self-linked tx descriptor and let the
1968 * hardware send the beacons automatically. We have to load it
fa1c114f 1969 * only once here.
036cd1ec 1970 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 1971 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 1972 */
1973 ath5k_beaconq_config(sc);
fa1c114f 1974
036cd1ec
BR		 1975 sc->imask |= AR5K_INT_SWBA;
1976
da966bca 1977 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 1978 if (ath5k_hw_hasveol(ah))
da966bca 1979 ath5k_beacon_send(sc);
da966bca
JS		 1980 } else
1981 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 1982 } else {
1983 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
02a78b42
BR		 1984 }
1985
c6e387a2 1986 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 1987 mmiowb();
1988 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 1989}
1990
428cbd4f
NK		 1991static void ath5k_tasklet_beacon(unsigned long data)
1992{
1993 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1994
1995 /*
1996 * Software beacon alert--time to send a beacon.
1997 *
1998 * In IBSS mode we use this interrupt just to
1999 * keep track of the next TBTT (target beacon
2000 * transmission time) in order to detect wether
2001 * automatic TSF updates happened.
2002 */
2003 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2004 /* XXX: only if VEOL suppported */
2005 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2006 sc->nexttbtt += sc->bintval;
2007 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2008 "SWBA nexttbtt: %x hw_tu: %x "
2009 "TSF: %llx\n",
2010 sc->nexttbtt,
2011 TSF_TO_TU(tsf),
2012 (unsigned long long) tsf);
2013 } else {
2014 spin_lock(&sc->block);
2015 ath5k_beacon_send(sc);
2016 spin_unlock(&sc->block);
02a78b42 2017 }
02a78b42
BR		 2018}
2019
fa1c114f
JS		 2020
2021/********************\
2022* Interrupt handling *
2023\********************/
2024
8a89f063 2025static void
6a8a3f6b 2026ath5k_intr_calibration_poll(struct ath5k_hw *ah)
8a89f063 2027{
2111ac0d
BR		 2028 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2029 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2030 /* run ANI only when full calibration is not active */
2031 ah->ah_cal_next_ani = jiffies +
2032 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2033 tasklet_schedule(&ah->ah_sc->ani_tasklet);
fa1c114f 2034
2111ac0d 2035 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2036 ah->ah_cal_next_full = jiffies +
2037 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2038 tasklet_schedule(&ah->ah_sc->calib);
3a0f2c87 2039 }
6a8a3f6b
BR		 2040 /* we could use SWI to generate enough interrupts to meet our
2041 * calibration interval requirements, if necessary:
2042 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2043}
fa1c114f 2044
fa1c114f
JS		 2045static irqreturn_t
2046ath5k_intr(int irq, void *dev_id)
2047{
2048 struct ath5k_softc *sc = dev_id;
2049 struct ath5k_hw *ah = sc->ah;
2050 enum ath5k_int status;
2051 unsigned int counter = 1000;
fa1c114f 2052
fa1c114f
JS		 2053 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2054 !ath5k_hw_is_intr_pending(ah)))
2055 return IRQ_NONE;
fa1c114f 2056
fa1c114f 2057 do {
fa1c114f
JS		 2058 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2059 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2060 status, sc->imask);
fa1c114f 2061 if (unlikely(status & AR5K_INT_FATAL)) {
02a78b42 2062 /*
fa1c114f
JS		 2063 * Fatal errors are unrecoverable.
2064 * Typically these are caused by DMA errors.
02a78b42 2065 */
8d67a031
BR		 2066 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2067 "fatal int, resetting\n");
5faaff74 2068 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2069 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2070 /*
2071 * Receive buffers are full. Either the bus is busy or
2072 * the CPU is not fast enough to process all received
2073 * frames.
2074 * Older chipsets need a reset to come out of this
2075 * condition, but we treat it as RX for newer chips.
2076 * We don't know exactly which versions need a reset -
2077 * this guess is copied from the HAL.
2078 */
2079 sc->stats.rxorn_intr++;
8d67a031
BR		 2080 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2081 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2082 "rx overrun, resetting\n");
5faaff74 2083 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2084 }
87d77c4e
BR		 2085 else
2086 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2087 } else {
2088 if (status & AR5K_INT_SWBA) {
56d2ac76 2089 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2090 }
2091 if (status & AR5K_INT_RXEOL) {
2092 /*
2093 * NB: the hardware should re-read the link when
2094 * RXE bit is written, but it doesn't work at
2095 * least on older hardware revs.
2096 */
b3f194e5 2097 sc->stats.rxeol_intr++;
fa1c114f
JS		 2098 }
2099 if (status & AR5K_INT_TXURN) {
2100 /* bump tx trigger level */
2101 ath5k_hw_update_tx_triglevel(ah, true);
2102 }
4c674c60 2103 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2104 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2105 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2106 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2107 tasklet_schedule(&sc->txtq);
2108 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2109 /* TODO */
fa1c114f
JS		 2110 }
2111 if (status & AR5K_INT_MIB) {
2111ac0d 2112 sc->stats.mib_intr++;
495391d7 2113 ath5k_hw_update_mib_counters(ah);
2111ac0d 2114 ath5k_ani_mib_intr(ah);
fa1c114f 2115 }
e6a3b616 2116 if (status & AR5K_INT_GPIO)
e6a3b616 2117 tasklet_schedule(&sc->rf_kill.toggleq);
b6ea0356 2118
fa1c114f 2119 }
2516baa6 2120 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
b6ea0356 2121
fa1c114f
JS		 2122 if (unlikely(!counter))
2123 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
fa1c114f 2124
6a8a3f6b 2125 ath5k_intr_calibration_poll(ah);
b6ea0356 2126
fa1c114f 2127 return IRQ_HANDLED;
fa1c114f
JS		 2128}
2129
fa1c114f
JS		 2130/*
2131 * Periodically recalibrate the PHY to account
2132 * for temperature/environment changes.
2133 */
fa1c114f 2134static void
6e220662 2135ath5k_tasklet_calibrate(unsigned long data)
fa1c114f 2136{
fa1c114f
JS		 2137 struct ath5k_softc *sc = (void *)data;
2138 struct ath5k_hw *ah = sc->ah;
fa1c114f 2139
6e220662 2140 /* Only full calibration for now */
e65e1d77 2141 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2142
fa1c114f 2143 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2144 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2145 sc->curchan->hw_value);
fa1c114f 2146
6f3b414a 2147 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
a05988bb 2148 /*
fa1c114f
JS		 2149 * Rfgain is out of bounds, reset the chip
2150 * to load new gain values.
a05988bb 2151 */
fa1c114f 2152 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2153 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2154 }
2155 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2156 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2157 ieee80211_frequency_to_channel(
2158 sc->curchan->center_freq));
e6a9854b 2159
0e8e02dd 2160 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2161 * doesn't.
2162 * TODO: We should stop TX here, so that it doesn't interfere.
2163 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2164 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2165 ah->ah_cal_next_nf = jiffies +
2166 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2167 ath5k_hw_update_noise_floor(ah);
afe86286 2168 }
fa1c114f 2169
e65e1d77 2170 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f 2171}
8127fbdc 2172
604eeadd 2173
2111ac0d
BR		 2174static void
2175ath5k_tasklet_ani(unsigned long data)
2176{
2177 struct ath5k_softc *sc = (void *)data;
2178 struct ath5k_hw *ah = sc->ah;
fa1c114f 2179
2111ac0d
BR		 2180 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2181 ath5k_ani_calibration(ah);
2182 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2183}
2184
fa1c114f 2185
fa1c114f 2186static void
4edd761f 2187ath5k_tx_complete_poll_work(struct work_struct *work)
fa1c114f 2188{
4edd761f
BR		 2189 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2190 tx_complete_work.work);
2191 struct ath5k_txq *txq;
8784d2ee 2192 int i;
4edd761f
BR		 2193 bool needreset = false;
2194
2195 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2196 if (sc->txqs[i].setup) {
2197 txq = &sc->txqs[i];
2198 spin_lock_bh(&txq->lock);
23413296 2199 if (txq->txq_len > 1) {
4edd761f
BR		 2200 if (txq->txq_poll_mark) {
2201 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2202 "TX queue stuck %d\n",
2203 txq->qnum);
2204 needreset = true;
923e5b3d 2205 txq->txq_stuck++;
4edd761f
BR		 2206 spin_unlock_bh(&txq->lock);
2207 break;
2208 } else {
2209 txq->txq_poll_mark = true;
2210 }
2211 }
2212 spin_unlock_bh(&txq->lock);
2213 }
2214 }
fa1c114f 2215
4edd761f
BR		 2216 if (needreset) {
2217 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2218 "TX queues stuck, resetting\n");
2219 ath5k_reset(sc, sc->curchan);
2220 }
2221
2222 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2223 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
fa1c114f
JS		 2224}
2225
2226
8a63facc
BC		 2227/*************************\
2228* Initialization routines *
2229\*************************/
fa1c114f 2230
fa1c114f 2231static int
8a63facc 2232ath5k_stop_locked(struct ath5k_softc *sc)
fa1c114f 2233{
fa1c114f 2234 struct ath5k_hw *ah = sc->ah;
fa1c114f 2235
8a63facc
BC		 2236 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2237 test_bit(ATH_STAT_INVALID, sc->status));
2bed03eb
NK		 2238
2239 /*
8a63facc
BC		 2240 * Shutdown the hardware and driver:
2241 * stop output from above
2242 * disable interrupts
2243 * turn off timers
2244 * turn off the radio
2245 * clear transmit machinery
2246 * clear receive machinery
2247 * drain and release tx queues
2248 * reclaim beacon resources
2249 * power down hardware
2bed03eb 2250 *
8a63facc
BC		 2251 * Note that some of this work is not possible if the
2252 * hardware is gone (invalid).
2bed03eb 2253 */
8a63facc 2254 ieee80211_stop_queues(sc->hw);
fa1c114f 2255
8a63facc
BC		 2256 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2257 ath5k_led_off(sc);
2258 ath5k_hw_set_imr(ah, 0);
2259 synchronize_irq(sc->pdev->irq);
2260 }
2261 ath5k_txq_cleanup(sc);
2262 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2263 ath5k_rx_stop(sc);
2264 ath5k_hw_phy_disable(ah);
2265 }
fa1c114f
JS		 2266
2267 return 0;
fa1c114f
JS		 2268}
2269
8a63facc
BC		 2270static int
2271ath5k_init(struct ath5k_softc *sc)
fa1c114f 2272{
fa1c114f 2273 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 2274 struct ath_common *common = ath5k_hw_common(ah);
2275 int ret, i;
fa1c114f 2276
8a63facc
BC		 2277 mutex_lock(&sc->lock);
2278
2279 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2280
fa1c114f 2281 /*
8a63facc
BC		 2282 * Stop anything previously setup. This is safe
2283 * no matter this is the first time through or not.
fa1c114f 2284 */
8a63facc 2285 ath5k_stop_locked(sc);
fa1c114f
JS		 2286
2287 /*
8a63facc
BC		 2288 * The basic interface to setting the hardware in a good
2289 * state is ``reset''. On return the hardware is known to
2290 * be powered up and with interrupts disabled. This must
2291 * be followed by initialization of the appropriate bits
2292 * and then setup of the interrupt mask.
fa1c114f 2293 */
8a63facc
BC		 2294 sc->curchan = sc->hw->conf.channel;
2295 sc->curband = &sc->sbands[sc->curchan->band];
2296 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2297 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2298 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2299
8a63facc
BC		 2300 ret = ath5k_reset(sc, NULL);
2301 if (ret)
2302 goto done;
fa1c114f 2303
8a63facc
BC		 2304 ath5k_rfkill_hw_start(ah);
2305
2306 /*
2307 * Reset the key cache since some parts do not reset the
2308 * contents on initial power up or resume from suspend.
2309 */
2310 for (i = 0; i < common->keymax; i++)
2311 ath_hw_keyreset(common, (u16) i);
2312
2313 ath5k_hw_set_ack_bitrate_high(ah, true);
2314 ret = 0;
2315done:
2316 mmiowb();
2317 mutex_unlock(&sc->lock);
4edd761f
BR		 2318
2319 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2320 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2321
8a63facc
BC		 2322 return ret;
2323}
2324
2325static void stop_tasklets(struct ath5k_softc *sc)
2326{
2327 tasklet_kill(&sc->rxtq);
2328 tasklet_kill(&sc->txtq);
2329 tasklet_kill(&sc->calib);
2330 tasklet_kill(&sc->beacontq);
2331 tasklet_kill(&sc->ani_tasklet);
2332}
2333
2334/*
2335 * Stop the device, grabbing the top-level lock to protect
2336 * against concurrent entry through ath5k_init (which can happen
2337 * if another thread does a system call and the thread doing the
2338 * stop is preempted).
2339 */
2340static int
2341ath5k_stop_hw(struct ath5k_softc *sc)
2342{
2343 int ret;
2344
2345 mutex_lock(&sc->lock);
2346 ret = ath5k_stop_locked(sc);
2347 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2348 /*
2349 * Don't set the card in full sleep mode!
2350 *
2351 * a) When the device is in this state it must be carefully
2352 * woken up or references to registers in the PCI clock
2353 * domain may freeze the bus (and system). This varies
2354 * by chip and is mostly an issue with newer parts
2355 * (madwifi sources mentioned srev >= 0x78) that go to
2356 * sleep more quickly.
2357 *
2358 * b) On older chips full sleep results a weird behaviour
2359 * during wakeup. I tested various cards with srev < 0x78
2360 * and they don't wake up after module reload, a second
2361 * module reload is needed to bring the card up again.
2362 *
2363 * Until we figure out what's going on don't enable
2364 * full chip reset on any chip (this is what Legacy HAL
2365 * and Sam's HAL do anyway). Instead Perform a full reset
2366 * on the device (same as initial state after attach) and
2367 * leave it idle (keep MAC/BB on warm reset) */
2368 ret = ath5k_hw_on_hold(sc->ah);
2369
2370 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2371 "putting device to sleep\n");
fa1c114f 2372 }
8a63facc 2373 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 2374
8a63facc
BC		 2375 mmiowb();
2376 mutex_unlock(&sc->lock);
1071db86 2377
8a63facc 2378 stop_tasklets(sc);
fa1c114f 2379
4edd761f 2380 cancel_delayed_work_sync(&sc->tx_complete_work);
cec8db23 2381
8a63facc 2382 ath5k_rfkill_hw_stop(sc->ah);
fa1c114f 2383
8a63facc 2384 return ret;
fa1c114f 2385}
fa1c114f 2386
209d889b
BC		 2387/*
2388 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2389 * and change to the given channel.
9804b98d 2390 *
5faaff74 2391 * This should be called with sc->lock.
9804b98d 2392 */
fa1c114f 2393static int
209d889b 2394ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f
JS		 2395{
2396 struct ath5k_hw *ah = sc->ah;
fa1c114f 2397 int ret;
fa1c114f 2398
fa1c114f 2399 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2400
450464de
BC		 2401 ath5k_hw_set_imr(ah, 0);
2402 synchronize_irq(sc->pdev->irq);
2403 stop_tasklets(sc);
fa1c114f 2404
209d889b 2405 if (chan) {
d7dc1003
JS		 2406 ath5k_txq_cleanup(sc);
2407 ath5k_rx_stop(sc);
fa1c114f 2408
209d889b
BC		 2409 sc->curchan = chan;
2410 sc->curband = &sc->sbands[chan->band];
d7dc1003 2411 }
3355443a 2412 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2413 if (ret) {
fa1c114f
JS		 2414 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2415 goto err;
9804b98d 2416 }
fa1c114f 2417
fa1c114f 2418 ret = ath5k_rx_start(sc);
d7dc1003 2419 if (ret) {
fa1c114f
JS		 2420 ATH5K_ERR(sc, "can't start recv logic\n");
2421 goto err;
2422 }
036cd1ec 2423
2111ac0d
BR		 2424 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2425
ac559526
BR		 2426 ah->ah_cal_next_full = jiffies;
2427 ah->ah_cal_next_ani = jiffies;
afe86286 2428 ah->ah_cal_next_nf = jiffies;
9804b98d
BR		 2429
2430 /*
d7dc1003
JS		 2431 * Change channels and update the h/w rate map if we're switching;
2432 * e.g. 11a to 11b/g.
2433 *
2434 * We may be doing a reset in response to an ioctl that changes the
2435 * channel so update any state that might change as a result.
fa1c114f
JS		 2436 *
2437 * XXX needed?
9804b98d 2438 */
fa1c114f 2439/* ath5k_chan_change(sc, c); */
9804b98d 2440
d7dc1003
JS		 2441 ath5k_beacon_config(sc);
2442 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2443
397f385b
BR		 2444 ieee80211_wake_queues(sc->hw);
2445
fa1c114f
JS		 2446 return 0;
2447err:
2448 return ret;
fa1c114f
JS		 2449}
2450
5faaff74
BC		 2451static void ath5k_reset_work(struct work_struct *work)
2452{
2453 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2454 reset_work);
fa1c114f 2455
5faaff74
BC		 2456 mutex_lock(&sc->lock);
2457 ath5k_reset(sc, sc->curchan);
2458 mutex_unlock(&sc->lock);
2459}
2460
8a63facc
BC		 2461static int
2462ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
fa1c114f 2463{
fa1c114f 2464 struct ath5k_softc *sc = hw->priv;
fa1c114f 2465 struct ath5k_hw *ah = sc->ah;
8a63facc 2466 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2467 struct ath5k_txq *txq;
8a63facc 2468 u8 mac[ETH_ALEN] = {};
fa1c114f 2469 int ret;
fa1c114f 2470
8a63facc 2471 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
fa1c114f 2472
8a63facc
BC		 2473 /*
2474 * Check if the MAC has multi-rate retry support.
2475 * We do this by trying to setup a fake extended
2476 * descriptor. MACs that don't have support will
2477 * return false w/o doing anything. MACs that do
2478 * support it will return true w/o doing anything.
2479 */
2480 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2481
8a63facc
BC		 2482 if (ret < 0)
2483 goto err;
2484 if (ret > 0)
2485 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2486
8a63facc
BC		 2487 /*
2488 * Collect the channel list. The 802.11 layer
2489 * is resposible for filtering this list based
2490 * on settings like the phy mode and regulatory
2491 * domain restrictions.
2492 */
2493 ret = ath5k_setup_bands(hw);
2494 if (ret) {
2495 ATH5K_ERR(sc, "can't get channels\n");
2496 goto err;
2497 }
67d2e2df 2498
8a63facc
BC		 2499 /* NB: setup here so ath5k_rate_update is happy */
2500 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2501 ath5k_setcurmode(sc, AR5K_MODE_11A);
2502 else
2503 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2504
8a63facc
BC		 2505 /*
2506 * Allocate tx+rx descriptors and populate the lists.
2507 */
2508 ret = ath5k_desc_alloc(sc, pdev);
2509 if (ret) {
2510 ATH5K_ERR(sc, "can't allocate descriptors\n");
2511 goto err;
2512 }
fa1c114f 2513
8a63facc
BC		 2514 /*
2515 * Allocate hardware transmit queues: one queue for
2516 * beacon frames and one data queue for each QoS
2517 * priority. Note that hw functions handle resetting
2518 * these queues at the needed time.
2519 */
2520 ret = ath5k_beaconq_setup(ah);
2521 if (ret < 0) {
2522 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2523 goto err_desc;
2524 }
2525 sc->bhalq = ret;
2526 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2527 if (IS_ERR(sc->cabq)) {
2528 ATH5K_ERR(sc, "can't setup cab queue\n");
2529 ret = PTR_ERR(sc->cabq);
2530 goto err_bhal;
2531 }
fa1c114f 2532
925e0b06
BR		 2533 /* This order matches mac80211's queue priority, so we can
2534 * directly use the mac80211 queue number without any mapping */
2535 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2536 if (IS_ERR(txq)) {
2537 ATH5K_ERR(sc, "can't setup xmit queue\n");
2538 ret = PTR_ERR(txq);
2539 goto err_queues;
2540 }
2541 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2542 if (IS_ERR(txq)) {
8a63facc 2543 ATH5K_ERR(sc, "can't setup xmit queue\n");
925e0b06 2544 ret = PTR_ERR(txq);
8a63facc
BC		 2545 goto err_queues;
2546 }
925e0b06
BR		 2547 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2548 if (IS_ERR(txq)) {
2549 ATH5K_ERR(sc, "can't setup xmit queue\n");
2550 ret = PTR_ERR(txq);
2551 goto err_queues;
2552 }
2553 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2554 if (IS_ERR(txq)) {
2555 ATH5K_ERR(sc, "can't setup xmit queue\n");
2556 ret = PTR_ERR(txq);
2557 goto err_queues;
2558 }
2559 hw->queues = 4;
fa1c114f 2560
8a63facc
BC		 2561 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2562 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2563 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2564 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2565 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
036cd1ec 2566
8a63facc 2567 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2568 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2569
8a63facc
BC		 2570 ret = ath5k_eeprom_read_mac(ah, mac);
2571 if (ret) {
2572 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
2573 sc->pdev->device);
2574 goto err_queues;
e30eb4ab 2575 }
fa1c114f 2576
8a63facc
BC		 2577 SET_IEEE80211_PERM_ADDR(hw, mac);
2578 /* All MAC address bits matter for ACKs */
2579 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
2580 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
428cbd4f 2581
8a63facc
BC		 2582 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2583 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2584 if (ret) {
2585 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2586 goto err_queues;
428cbd4f 2587 }
428cbd4f 2588
8a63facc
BC		 2589 ret = ieee80211_register_hw(hw);
2590 if (ret) {
2591 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2592 goto err_queues;
2593 }
fa1c114f 2594
8a63facc
BC		 2595 if (!ath_is_world_regd(regulatory))
2596 regulatory_hint(hw->wiphy, regulatory->alpha2);
fa1c114f 2597
8a63facc 2598 ath5k_init_leds(sc);
fa1c114f 2599
8a63facc 2600 ath5k_sysfs_register(sc);
fa1c114f 2601
8a63facc
BC		 2602 return 0;
2603err_queues:
2604 ath5k_txq_release(sc);
2605err_bhal:
2606 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2607err_desc:
2608 ath5k_desc_free(sc, pdev);
2609err:
2610 return ret;
2611}
fa1c114f 2612
8a63facc
BC		 2613static void
2614ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2615{
2616 struct ath5k_softc *sc = hw->priv;
fa1c114f
JS		 2617
2618 /*
8a63facc
BC		 2619 * NB: the order of these is important:
2620 * o call the 802.11 layer before detaching ath5k_hw to
2621 * ensure callbacks into the driver to delete global
2622 * key cache entries can be handled
2623 * o reclaim the tx queue data structures after calling
2624 * the 802.11 layer as we'll get called back to reclaim
2625 * node state and potentially want to use them
2626 * o to cleanup the tx queues the hal is called, so detach
2627 * it last
2628 * XXX: ??? detach ath5k_hw ???
2629 * Other than that, it's straightforward...
fa1c114f 2630 */
8a63facc
BC		 2631 ieee80211_unregister_hw(hw);
2632 ath5k_desc_free(sc, pdev);
2633 ath5k_txq_release(sc);
2634 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2635 ath5k_unregister_leds(sc);
e6a3b616 2636
8a63facc 2637 ath5k_sysfs_unregister(sc);
bc1b32d6 2638 /*
8a63facc
BC		 2639 * NB: can't reclaim these until after ieee80211_ifdetach
2640 * returns because we'll get called back to reclaim node
2641 * state and potentially want to use them.
bc1b32d6 2642 */
fa1c114f
JS		 2643}
2644
8a63facc
BC		 2645/********************\
2646* Mac80211 functions *
2647\********************/
2648
fa1c114f 2649static int
8a63facc 2650ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f 2651{
8a63facc 2652 struct ath5k_softc *sc = hw->priv;
925e0b06 2653 u16 qnum = skb_get_queue_mapping(skb);
fa1c114f 2654
925e0b06
BR		 2655 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2656 dev_kfree_skb_any(skb);
2657 return 0;
b3f194e5 2658 }
fa1c114f 2659
925e0b06 2660 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
fa1c114f
JS		 2661}
2662
8a63facc 2663static int ath5k_start(struct ieee80211_hw *hw)
450464de 2664{
8a63facc 2665 return ath5k_init(hw->priv);
450464de
BC		 2666}
2667
8a63facc
BC		 2668static void ath5k_stop(struct ieee80211_hw *hw)
2669{
2670 ath5k_stop_hw(hw->priv);
2671}
2672
2673static int ath5k_add_interface(struct ieee80211_hw *hw,
2674 struct ieee80211_vif *vif)
fa1c114f 2675{
8a63facc 2676 struct ath5k_softc *sc = hw->priv;
fa1c114f
JS		 2677 int ret;
2678
2679 mutex_lock(&sc->lock);
8a63facc
BC		 2680 if (sc->vif) {
2681 ret = 0;
2682 goto end;
fa1c114f 2683 }
8bdd5b9c 2684
8a63facc 2685 sc->vif = vif;
fa1c114f 2686
8a63facc
BC		 2687 switch (vif->type) {
2688 case NL80211_IFTYPE_AP:
2689 case NL80211_IFTYPE_STATION:
2690 case NL80211_IFTYPE_ADHOC:
2691 case NL80211_IFTYPE_MESH_POINT:
2692 sc->opmode = vif->type;
2693 break;
2694 default:
2695 ret = -EOPNOTSUPP;
2696 goto end;
2697 }
2698
2699 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
fa1c114f 2700
8a63facc
BC		 2701 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2702 ath5k_mode_setup(sc);
e6a3b616 2703
8a63facc
BC		 2704 ret = 0;
2705end:
2706 mutex_unlock(&sc->lock);
fa1c114f
JS		 2707 return ret;
2708}
2709
6a8a3f6b 2710static void
8a63facc
BC		 2711ath5k_remove_interface(struct ieee80211_hw *hw,
2712 struct ieee80211_vif *vif)
6a8a3f6b 2713{
8a63facc
BC		 2714 struct ath5k_softc *sc = hw->priv;
2715 u8 mac[ETH_ALEN] = {};
2111ac0d 2716
8a63facc
BC		 2717 mutex_lock(&sc->lock);
2718 if (sc->vif != vif)
2719 goto end;
2720
2721 ath5k_hw_set_lladdr(sc->ah, mac);
2722 sc->vif = NULL;
2723end:
2724 mutex_unlock(&sc->lock);
6a8a3f6b
BR		 2725}
2726
8a63facc
BC		 2727/*
2728 * TODO: Phy disable/diversity etc
2729 */
2730static int
2731ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f 2732{
8a63facc 2733 struct ath5k_softc *sc = hw->priv;
fa1c114f 2734 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 2735 struct ieee80211_conf *conf = &hw->conf;
2736 int ret = 0;
fa1c114f 2737
8a63facc 2738 mutex_lock(&sc->lock);
fa1c114f 2739
8a63facc
BC		 2740 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2741 ret = ath5k_chan_set(sc, conf->channel);
2742 if (ret < 0)
2743 goto unlock;
2744 }
a6ae0716 2745
8a63facc
BC		 2746 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2747 (sc->power_level != conf->power_level)) {
a0823810 2748 sc->power_level = conf->power_level;
fa1c114f 2749
a0823810
NK		 2750 /* Half dB steps */
2751 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2752 }
fa1c114f 2753
2bed03eb
NK		 2754 /* TODO:
2755 * 1) Move this on config_interface and handle each case
2756 * separately eg. when we have only one STA vif, use
2757 * AR5K_ANTMODE_SINGLE_AP
2758 *
2759 * 2) Allow the user to change antenna mode eg. when only
2760 * one antenna is present
2761 *
2762 * 3) Allow the user to set default/tx antenna when possible
2763 *
2764 * 4) Default mode should handle 90% of the cases, together
2765 * with fixed a/b and single AP modes we should be able to
2766 * handle 99%. Sectored modes are extreme cases and i still
2767 * haven't found a usage for them. If we decide to support them,
2768 * then we must allow the user to set how many tx antennas we
2769 * have available
2770 */
caec9112 2771 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
6e220662 2772
55aa4e0f 2773unlock:
be009370 2774 mutex_unlock(&sc->lock);
55aa4e0f 2775 return ret;
fa1c114f
JS		 2776}
2777
3ac64bee 2778static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 2779 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 2780{
2781 u32 mfilt[2], val;
3ac64bee 2782 u8 pos;
22bedad3 2783 struct netdev_hw_addr *ha;
3ac64bee
JB		 2784
2785 mfilt[0] = 0;
2786 mfilt[1] = 1;
2787
22bedad3 2788 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 2789 /* calculate XOR of eight 6-bit values */
22bedad3 2790 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 2791 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 2792 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 2793 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2794 pos &= 0x3f;
2795 mfilt[pos / 32] |= (1 << (pos % 32));
2796 /* XXX: we might be able to just do this instead,
2797 * but not sure, needs testing, if we do use this we'd
2798 * neet to inform below to not reset the mcast */
2799 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 2800 * ha->addr[5]); */
3ac64bee
JB		 2801 }
2802
2803 return ((u64)(mfilt[1]) << 32) | mfilt[0];
fa1c114f
JS		 2804}
2805
fa1c114f
JS		 2806#define SUPPORTED_FIF_FLAGS \
2807 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2808 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2809 FIF_BCN_PRBRESP_PROMISC
fa1c114f 2810/*
fa1c114f
JS		 2811 * o always accept unicast, broadcast, and multicast traffic
2812 * o multicast traffic for all BSSIDs will be enabled if mac80211
2813 * says it should be
2814 * o maintain current state of phy ofdm or phy cck error reception.
2815 * If the hardware detects any of these type of errors then
2816 * ath5k_hw_get_rx_filter() will pass to us the respective
2817 * hardware filters to be able to receive these type of frames.
2818 * o probe request frames are accepted only when operating in
2819 * hostap, adhoc, or monitor modes
2820 * o enable promiscuous mode according to the interface state
2821 * o accept beacons:
2822 * - when operating in adhoc mode so the 802.11 layer creates
2823 * node table entries for peers,
2824 * - when operating in station mode for collecting rssi data when
2825 * the station is otherwise quiet, or
2826 * - when scanning
fa1c114f 2827 */
fa1c114f
JS		 2828static void ath5k_configure_filter(struct ieee80211_hw *hw,
2829 unsigned int changed_flags,
2830 unsigned int *new_flags,
3ac64bee 2831 u64 multicast)
fa1c114f 2832{
fa1c114f 2833 struct ath5k_softc *sc = hw->priv;
fa1c114f 2834 struct ath5k_hw *ah = sc->ah;
3ac64bee 2835 u32 mfilt[2], rfilt;
fa1c114f 2836
56d1de0a 2837 mutex_lock(&sc->lock);
6e220662 2838
3ac64bee
JB		 2839 mfilt[0] = multicast;
2840 mfilt[1] = multicast >> 32;
fa1c114f 2841
fa1c114f
JS		 2842 /* Only deal with supported flags */
2843 changed_flags &= SUPPORTED_FIF_FLAGS;
2844 *new_flags &= SUPPORTED_FIF_FLAGS;
2845
2846 /* If HW detects any phy or radar errors, leave those filters on.
2847 * Also, always enable Unicast, Broadcasts and Multicast
2848 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2849 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2850 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2851 AR5K_RX_FILTER_MCAST);
2852
2853 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2854 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 2855 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2856 } else {
fa1c114f 2857 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2858 }
fa1c114f 2859 }
fa1c114f 2860
6b5dcccb
BC		 2861 if (test_bit(ATH_STAT_PROMISC, sc->status))
2862 rfilt |= AR5K_RX_FILTER_PROM;
2863
fa1c114f
JS		 2864 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2865 if (*new_flags & FIF_ALLMULTI) {
2866 mfilt[0] = ~0;
2867 mfilt[1] = ~0;
afe86286 2868 }
6e220662 2869
fa1c114f
JS		 2870 /* This is the best we can do */
2871 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2872 rfilt |= AR5K_RX_FILTER_PHYERR;
fa1c114f 2873
fa1c114f 2874 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
30bf4169 2875 * and probes for any BSSID */
fa1c114f 2876 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
30bf4169 2877 rfilt |= AR5K_RX_FILTER_BEACON;
fa1c114f 2878
fa1c114f
JS		 2879 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2880 * set we should only pass on control frames for this
2881 * station. This needs testing. I believe right now this
2882 * enables *all* control frames, which is OK.. but
2883 * but we should see if we can improve on granularity */
2884 if (*new_flags & FIF_CONTROL)
2885 rfilt |= AR5K_RX_FILTER_CONTROL;
2111ac0d 2886
fa1c114f 2887 /* Additional settings per mode -- this is per ath5k */
fa1c114f 2888
fa1c114f 2889 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
fa1c114f 2890
56d1de0a
BC		 2891 switch (sc->opmode) {
2892 case NL80211_IFTYPE_MESH_POINT:
56d1de0a
BC		 2893 rfilt |= AR5K_RX_FILTER_CONTROL |
2894 AR5K_RX_FILTER_BEACON |
2895 AR5K_RX_FILTER_PROBEREQ |
2896 AR5K_RX_FILTER_PROM;
2897 break;
2898 case NL80211_IFTYPE_AP:
2899 case NL80211_IFTYPE_ADHOC:
2900 rfilt |= AR5K_RX_FILTER_PROBEREQ |
2901 AR5K_RX_FILTER_BEACON;
2902 break;
2903 case NL80211_IFTYPE_STATION:
2904 if (sc->assoc)
2905 rfilt |= AR5K_RX_FILTER_BEACON;
2906 default:
2907 break;
2908 }
fa1c114f 2909
fa1c114f 2910 /* Set filters */
0bbac08f 2911 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2912
2913 /* Set multicast bits */
2914 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
a180a130 2915 /* Set the cached hw filter flags, this will later actually
fa1c114f
JS		 2916 * be set in HW */
2917 sc->filter_flags = rfilt;
cec8db23 2918
56d1de0a 2919 mutex_unlock(&sc->lock);
cec8db23
BC		 2920}
2921
fa1c114f
JS		 2922static int
2923ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2924 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2925 struct ieee80211_key_conf *key)
fa1c114f
JS		 2926{
2927 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 2928 struct ath5k_hw *ah = sc->ah;
2929 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 2930 int ret = 0;
fa1c114f 2931
9ad9a26e
BC		 2932 if (modparam_nohwcrypt)
2933 return -EOPNOTSUPP;
fa1c114f 2934
97359d12
JB		 2935 switch (key->cipher) {
2936 case WLAN_CIPHER_SUITE_WEP40:
2937 case WLAN_CIPHER_SUITE_WEP104:
2938 case WLAN_CIPHER_SUITE_TKIP:
3f64b435 2939 break;
97359d12 2940 case WLAN_CIPHER_SUITE_CCMP:
781f3136 2941 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
1c818740 2942 break;
fa1c114f
JS		 2943 return -EOPNOTSUPP;
2944 default:
2945 WARN_ON(1);
2946 return -EINVAL;
fa1c114f 2947 }
fa1c114f 2948
fa1c114f 2949 mutex_lock(&sc->lock);
fa1c114f 2950
fa1c114f
JS		 2951 switch (cmd) {
2952 case SET_KEY:
e0f8c2a9
BR		 2953 ret = ath_key_config(common, vif, sta, key);
2954 if (ret >= 0) {
2955 key->hw_key_idx = ret;
2956 /* push IV and Michael MIC generation to stack */
2957 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2958 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
2959 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2960 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
2961 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2962 ret = 0;
fa1c114f 2963 }
fa1c114f
JS		 2964 break;
2965 case DISABLE_KEY:
e0f8c2a9 2966 ath_key_delete(common, key);
fa1c114f
JS		 2967 break;
2968 default:
2969 ret = -EINVAL;
fa1c114f
JS		 2970 }
2971
8a63facc
BC		 2972 mmiowb();
2973 mutex_unlock(&sc->lock);
2974 return ret;
fa1c114f
JS		 2975}
2976
2977static int
8a63facc
BC		 2978ath5k_get_stats(struct ieee80211_hw *hw,
2979 struct ieee80211_low_level_stats *stats)
fa1c114f 2980{
8a63facc 2981 struct ath5k_softc *sc = hw->priv;
450464de 2982
8a63facc
BC		 2983 /* Force update */
2984 ath5k_hw_update_mib_counters(sc->ah);
209d889b 2985
8a63facc
BC		 2986 stats->dot11ACKFailureCount = sc->stats.ack_fail;
2987 stats->dot11RTSFailureCount = sc->stats.rts_fail;
2988 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
2989 stats->dot11FCSErrorCount = sc->stats.fcs_error;
d7dc1003 2990
8a63facc
BC		 2991 return 0;
2992}
d7dc1003 2993
8a63facc
BC		 2994static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
2995 struct survey_info *survey)
2996{
2997 struct ath5k_softc *sc = hw->priv;
2998 struct ieee80211_conf *conf = &hw->conf;
2111ac0d 2999
8a63facc
BC		 3000 if (idx != 0)
3001 return -ENOENT;
afe86286 3002
8a63facc
BC		 3003 survey->channel = conf->channel;
3004 survey->filled = SURVEY_INFO_NOISE_DBM;
3005 survey->noise = sc->ah->ah_noise_floor;
fa1c114f 3006
8a63facc
BC		 3007 return 0;
3008}
fa1c114f 3009
8a63facc
BC		 3010static u64
3011ath5k_get_tsf(struct ieee80211_hw *hw)
3012{
3013 struct ath5k_softc *sc = hw->priv;
397f385b 3014
8a63facc 3015 return ath5k_hw_get_tsf64(sc->ah);
fa1c114f
JS		 3016}
3017
8a63facc
BC		 3018static void
3019ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
5faaff74 3020{
8a63facc 3021 struct ath5k_softc *sc = hw->priv;
5faaff74 3022
8a63facc 3023 ath5k_hw_set_tsf64(sc->ah, tsf);
5faaff74
BC		 3024}
3025
8a63facc
BC		 3026static void
3027ath5k_reset_tsf(struct ieee80211_hw *hw)
fa1c114f 3028{
8a63facc
BC		 3029 struct ath5k_softc *sc = hw->priv;
3030
3031 /*
3032 * in IBSS mode we need to update the beacon timers too.
3033 * this will also reset the TSF if we call it with 0
3034 */
3035 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3036 ath5k_beacon_update_timers(sc, 0);
3037 else
3038 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3039}
3040
8a63facc
BC		 3041static void
3042set_beacon_filter(struct ieee80211_hw *hw, bool enable)
fa1c114f 3043{
8a63facc
BC		 3044 struct ath5k_softc *sc = hw->priv;
3045 struct ath5k_hw *ah = sc->ah;
3046 u32 rfilt;
3047 rfilt = ath5k_hw_get_rx_filter(ah);
3048 if (enable)
3049 rfilt |= AR5K_RX_FILTER_BEACON;
3050 else
3051 rfilt &= ~AR5K_RX_FILTER_BEACON;
3052 ath5k_hw_set_rx_filter(ah, rfilt);
3053 sc->filter_flags = rfilt;
fa1c114f
JS		 3054}
3055
8a63facc
BC		 3056static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3057 struct ieee80211_vif *vif,
3058 struct ieee80211_bss_conf *bss_conf,
3059 u32 changes)
fa1c114f
JS		 3060{
3061 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 3062 struct ath5k_hw *ah = sc->ah;
3063 struct ath_common *common = ath5k_hw_common(ah);
3064 unsigned long flags;
fa1c114f
JS		 3065
3066 mutex_lock(&sc->lock);
8a63facc
BC		 3067 if (WARN_ON(sc->vif != vif))
3068 goto unlock;
3069
3070 if (changes & BSS_CHANGED_BSSID) {
3071 /* Cache for later use during resets */
3072 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3073 common->curaid = 0;
3074 ath5k_hw_set_bssid(ah);
3075 mmiowb();
fa1c114f
JS		 3076 }
3077
8a63facc
BC		 3078 if (changes & BSS_CHANGED_BEACON_INT)
3079 sc->bintval = bss_conf->beacon_int;
fa1c114f 3080
8a63facc
BC		 3081 if (changes & BSS_CHANGED_ASSOC) {
3082 sc->assoc = bss_conf->assoc;
3083 if (sc->opmode == NL80211_IFTYPE_STATION)
3084 set_beacon_filter(hw, sc->assoc);
3085 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3086 AR5K_LED_ASSOC : AR5K_LED_INIT);
3087 if (bss_conf->assoc) {
3088 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3089 "Bss Info ASSOC %d, bssid: %pM\n",
3090 bss_conf->aid, common->curbssid);
3091 common->curaid = bss_conf->aid;
3092 ath5k_hw_set_bssid(ah);
3093 /* Once ANI is available you would start it here */
3094 }
fa1c114f 3095 }
67d2e2df 3096
8a63facc
BC		 3097 if (changes & BSS_CHANGED_BEACON) {
3098 spin_lock_irqsave(&sc->block, flags);
3099 ath5k_beacon_update(hw, vif);
3100 spin_unlock_irqrestore(&sc->block, flags);
3101 }
ccfe5552 3102
8a63facc
BC		 3103 if (changes & BSS_CHANGED_BEACON_ENABLED)
3104 sc->enable_beacon = bss_conf->enable_beacon;
67d2e2df 3105
8a63facc
BC		 3106 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3107 BSS_CHANGED_BEACON_INT))
3108 ath5k_beacon_config(sc);
3109
3110 unlock:
fa1c114f 3111 mutex_unlock(&sc->lock);
fa1c114f
JS		 3112}
3113
8a63facc 3114static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
fa1c114f
JS		 3115{
3116 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 3117 if (!sc->assoc)
3118 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3119}
fa1c114f 3120
8a63facc
BC		 3121static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3122{
3123 struct ath5k_softc *sc = hw->priv;
3124 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3125 AR5K_LED_ASSOC : AR5K_LED_INIT);
3126}
fa1c114f 3127
8a63facc
BC		 3128/**
3129 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3130 *
3131 * @hw: struct ieee80211_hw pointer
3132 * @coverage_class: IEEE 802.11 coverage class number
3133 *
3134 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3135 * coverage class. The values are persistent, they are restored after device
3136 * reset.
3137 */
3138static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3139{
3140 struct ath5k_softc *sc = hw->priv;
3141
3142 mutex_lock(&sc->lock);
3143 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
fa1c114f
JS		 3144 mutex_unlock(&sc->lock);
3145}
3146
e0b1cc52
BR		 3147static int ath5k_conf_tx(struct ieee80211_hw *hw, u16 queue,
3148 const struct ieee80211_tx_queue_params *params)
fa1c114f
JS		 3149{
3150 struct ath5k_softc *sc = hw->priv;
a0823810 3151 struct ath5k_hw *ah = sc->ah;
e0b1cc52 3152 struct ath5k_txq_info qi;
2bed03eb 3153 int ret = 0;
be009370 3154
e0b1cc52
BR		 3155 if (queue >= ah->ah_capabilities.cap_queues.q_tx_num)
3156 return 0;
3157
be009370 3158 mutex_lock(&sc->lock);
fa1c114f 3159
e0b1cc52 3160 ath5k_hw_get_tx_queueprops(ah, queue, &qi);
2bed03eb 3161
e0b1cc52
BR		 3162 qi.tqi_aifs = params->aifs;
3163 qi.tqi_cw_min = params->cw_min;
3164 qi.tqi_cw_max = params->cw_max;
3165 qi.tqi_burst_time = params->txop;
a0823810 3166
e0b1cc52
BR		 3167 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3168 "Configure tx [queue %d], "
3169 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
3170 queue, params->aifs, params->cw_min,
3171 params->cw_max, params->txop);
fa1c114f 3172
e0b1cc52
BR		 3173 if (ath5k_hw_set_tx_queueprops(ah, queue, &qi)) {
3174 ATH5K_ERR(sc,
3175 "Unable to update hardware queue %u!\n", queue);
3176 ret = -EIO;
3177 } else
3178 ath5k_hw_reset_tx_queue(ah, queue);
be009370
BC		 3179
3180 mutex_unlock(&sc->lock);
e0b1cc52 3181
55aa4e0f 3182 return ret;
fa1c114f
JS		 3183}
3184
8a63facc
BC		 3185static const struct ieee80211_ops ath5k_hw_ops = {
3186 .tx = ath5k_tx,
3187 .start = ath5k_start,
3188 .stop = ath5k_stop,
3189 .add_interface = ath5k_add_interface,
3190 .remove_interface = ath5k_remove_interface,
3191 .config = ath5k_config,
3192 .prepare_multicast = ath5k_prepare_multicast,
3193 .configure_filter = ath5k_configure_filter,
3194 .set_key = ath5k_set_key,
3195 .get_stats = ath5k_get_stats,
3196 .get_survey = ath5k_get_survey,
e0b1cc52 3197 .conf_tx = ath5k_conf_tx,
8a63facc
BC		 3198 .get_tsf = ath5k_get_tsf,
3199 .set_tsf = ath5k_set_tsf,
3200 .reset_tsf = ath5k_reset_tsf,
3201 .bss_info_changed = ath5k_bss_info_changed,
3202 .sw_scan_start = ath5k_sw_scan_start,
3203 .sw_scan_complete = ath5k_sw_scan_complete,
3204 .set_coverage_class = ath5k_set_coverage_class,
3205};
3ac64bee 3206
8a63facc
BC		 3207/********************\
3208* PCI Initialization *
3209\********************/
3ac64bee 3210
8a63facc
BC		 3211static int __devinit
3212ath5k_pci_probe(struct pci_dev *pdev,
3213 const struct pci_device_id *id)
3214{
3215 void __iomem *mem;
3216 struct ath5k_softc *sc;
3217 struct ath_common *common;
3218 struct ieee80211_hw *hw;
3219 int ret;
3220 u8 csz;
3ac64bee 3221
8a63facc
BC		 3222 /*
3223 * L0s needs to be disabled on all ath5k cards.
3224 *
3225 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3226 * by default in the future in 2.6.36) this will also mean both L1 and
3227 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3228 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3229 * though but cannot currently undue the effect of a blacklist, for
3230 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3231 * the device link capability.
3232 *
3233 * It may be possible in the future to implement some PCI API to allow
3234 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3235 * best to accept that both L0s and L1 will be disabled completely for
3236 * distributions shipping with CONFIG_PCIEASPM rather than having this
3237 * issue present. Motivation for adding this new API will be to help
3238 * with power consumption for some of these devices.
3239 */
3240 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
3ac64bee 3241
8a63facc
BC		 3242 ret = pci_enable_device(pdev);
3243 if (ret) {
3244 dev_err(&pdev->dev, "can't enable device\n");
3245 goto err;
3246 }
fa1c114f 3247
8a63facc
BC		 3248 /* XXX 32-bit addressing only */
3249 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3250 if (ret) {
3251 dev_err(&pdev->dev, "32-bit DMA not available\n");
3252 goto err_dis;
3253 }
56d1de0a 3254
8a63facc
BC		 3255 /*
3256 * Cache line size is used to size and align various
3257 * structures used to communicate with the hardware.
3258 */
3259 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
3260 if (csz == 0) {
3261 /*
3262 * Linux 2.4.18 (at least) writes the cache line size
3263 * register as a 16-bit wide register which is wrong.
3264 * We must have this setup properly for rx buffer
3265 * DMA to work so force a reasonable value here if it
3266 * comes up zero.
3267 */
3268 csz = L1_CACHE_BYTES >> 2;
3269 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
3270 }
3271 /*
3272 * The default setting of latency timer yields poor results,
3273 * set it to the value used by other systems. It may be worth
3274 * tweaking this setting more.
3275 */
3276 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
fa1c114f 3277
8a63facc
BC		 3278 /* Enable bus mastering */
3279 pci_set_master(pdev);
fa1c114f 3280
8a63facc
BC		 3281 /*
3282 * Disable the RETRY_TIMEOUT register (0x41) to keep
3283 * PCI Tx retries from interfering with C3 CPU state.
3284 */
3285 pci_write_config_byte(pdev, 0x41, 0);
fa1c114f 3286
8a63facc
BC		 3287 ret = pci_request_region(pdev, 0, "ath5k");
3288 if (ret) {
3289 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
3290 goto err_dis;
fa1c114f
JS		 3291 }
3292
8a63facc
BC		 3293 mem = pci_iomap(pdev, 0, 0);
3294 if (!mem) {
3295 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
3296 ret = -EIO;
3297 goto err_reg;
fa1c114f
JS		 3298 }
3299
8a63facc
BC		 3300 /*
3301 * Allocate hw (mac80211 main struct)
3302 * and hw->priv (driver private data)
3303 */
3304 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
3305 if (hw == NULL) {
3306 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
3307 ret = -ENOMEM;
3308 goto err_map;
3309 }
fa1c114f 3310
8a63facc 3311 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
fa1c114f 3312
8a63facc
BC		 3313 /* Initialize driver private data */
3314 SET_IEEE80211_DEV(hw, &pdev->dev);
3315 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3316 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3317 IEEE80211_HW_SIGNAL_DBM;
fa1c114f 3318
8a63facc
BC		 3319 hw->wiphy->interface_modes =
3320 BIT(NL80211_IFTYPE_AP) |
3321 BIT(NL80211_IFTYPE_STATION) |
3322 BIT(NL80211_IFTYPE_ADHOC) |
3323 BIT(NL80211_IFTYPE_MESH_POINT);
fa1c114f 3324
8a63facc
BC		 3325 hw->extra_tx_headroom = 2;
3326 hw->channel_change_time = 5000;
3327 sc = hw->priv;
3328 sc->hw = hw;
3329 sc->pdev = pdev;
fa1c114f 3330
8a63facc 3331 ath5k_debug_init_device(sc);
fa1c114f 3332
8a63facc
BC		 3333 /*
3334 * Mark the device as detached to avoid processing
3335 * interrupts until setup is complete.
3336 */
3337 __set_bit(ATH_STAT_INVALID, sc->status);
fa1c114f 3338
8a63facc
BC		 3339 sc->iobase = mem; /* So we can unmap it on detach */
3340 sc->opmode = NL80211_IFTYPE_STATION;
3341 sc->bintval = 1000;
3342 mutex_init(&sc->lock);
3343 spin_lock_init(&sc->rxbuflock);
3344 spin_lock_init(&sc->txbuflock);
3345 spin_lock_init(&sc->block);
56d1de0a 3346
8a63facc
BC		 3347 /* Set private data */
3348 pci_set_drvdata(pdev, sc);
fa1c114f 3349
8a63facc
BC		 3350 /* Setup interrupt handler */
3351 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
3352 if (ret) {
3353 ATH5K_ERR(sc, "request_irq failed\n");
3354 goto err_free;
3355 }
fa1c114f 3356
8a63facc
BC		 3357 /* If we passed the test, malloc an ath5k_hw struct */
3358 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
3359 if (!sc->ah) {
3360 ret = -ENOMEM;
3361 ATH5K_ERR(sc, "out of memory\n");
3362 goto err_irq;
3363 }
9ad9a26e 3364
8a63facc
BC		 3365 sc->ah->ah_sc = sc;
3366 sc->ah->ah_iobase = sc->iobase;
3367 common = ath5k_hw_common(sc->ah);
3368 common->ops = &ath5k_common_ops;
3369 common->ah = sc->ah;
3370 common->hw = hw;
3371 common->cachelsz = csz << 2; /* convert to bytes */
65b5a698 3372
8a63facc
BC		 3373 /* Initialize device */
3374 ret = ath5k_hw_attach(sc);
3375 if (ret) {
3376 goto err_free_ah;
3377 }
1c818740 3378
8a63facc
BC		 3379 /* set up multi-rate retry capabilities */
3380 if (sc->ah->ah_version == AR5K_AR5212) {
3381 hw->max_rates = 4;
3382 hw->max_rate_tries = 11;
fa1c114f
JS		 3383 }
3384
8a63facc
BC		 3385 /* Finish private driver data initialization */
3386 ret = ath5k_attach(pdev, hw);
3387 if (ret)
3388 goto err_ah;
fa1c114f 3389
8a63facc
BC		 3390 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3391 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
3392 sc->ah->ah_mac_srev,
3393 sc->ah->ah_phy_revision);
3394
3395 if (!sc->ah->ah_single_chip) {
3396 /* Single chip radio (!RF5111) */
3397 if (sc->ah->ah_radio_5ghz_revision &&
3398 !sc->ah->ah_radio_2ghz_revision) {
3399 /* No 5GHz support -> report 2GHz radio */
3400 if (!test_bit(AR5K_MODE_11A,
3401 sc->ah->ah_capabilities.cap_mode)) {
3402 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3403 ath5k_chip_name(AR5K_VERSION_RAD,
3404 sc->ah->ah_radio_5ghz_revision),
3405 sc->ah->ah_radio_5ghz_revision);
3406 /* No 2GHz support (5110 and some
3407 * 5Ghz only cards) -> report 5Ghz radio */
3408 } else if (!test_bit(AR5K_MODE_11B,
3409 sc->ah->ah_capabilities.cap_mode)) {
3410 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3411 ath5k_chip_name(AR5K_VERSION_RAD,
3412 sc->ah->ah_radio_5ghz_revision),
3413 sc->ah->ah_radio_5ghz_revision);
3414 /* Multiband radio */
3415 } else {
3416 ATH5K_INFO(sc, "RF%s multiband radio found"
3417 " (0x%x)\n",
3418 ath5k_chip_name(AR5K_VERSION_RAD,
3419 sc->ah->ah_radio_5ghz_revision),
3420 sc->ah->ah_radio_5ghz_revision);
3421 }
3422 }
3423 /* Multi chip radio (RF5111 - RF2111) ->
3424 * report both 2GHz/5GHz radios */
3425 else if (sc->ah->ah_radio_5ghz_revision &&
3426 sc->ah->ah_radio_2ghz_revision){
3427 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3428 ath5k_chip_name(AR5K_VERSION_RAD,
3429 sc->ah->ah_radio_5ghz_revision),
3430 sc->ah->ah_radio_5ghz_revision);
3431 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3432 ath5k_chip_name(AR5K_VERSION_RAD,
3433 sc->ah->ah_radio_2ghz_revision),
3434 sc->ah->ah_radio_2ghz_revision);
fa1c114f 3435 }
fa1c114f
JS		 3436 }
3437
55ee82b5 3438
8a63facc
BC		 3439 /* ready to process interrupts */
3440 __clear_bit(ATH_STAT_INVALID, sc->status);
55ee82b5
HS		 3441
3442 return 0;
8a63facc
BC		 3443err_ah:
3444 ath5k_hw_detach(sc->ah);
3445err_free_ah:
3446 kfree(sc->ah);
3447err_irq:
3448 free_irq(pdev->irq, sc);
3449err_free:
3450 ieee80211_free_hw(hw);
3451err_map:
3452 pci_iounmap(pdev, mem);
3453err_reg:
3454 pci_release_region(pdev, 0);
3455err_dis:
3456 pci_disable_device(pdev);
3457err:
3458 return ret;
55ee82b5
HS		 3459}
3460
8a63facc
BC		 3461static void __devexit
3462ath5k_pci_remove(struct pci_dev *pdev)
fa1c114f 3463{
8a63facc 3464 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3465
8a63facc
BC		 3466 ath5k_debug_finish_device(sc);
3467 ath5k_detach(pdev, sc->hw);
3468 ath5k_hw_detach(sc->ah);
3469 kfree(sc->ah);
3470 free_irq(pdev->irq, sc);
3471 pci_iounmap(pdev, sc->iobase);
3472 pci_release_region(pdev, 0);
3473 pci_disable_device(pdev);
3474 ieee80211_free_hw(sc->hw);
fa1c114f
JS		 3475}
3476
8a63facc
BC		 3477#ifdef CONFIG_PM_SLEEP
3478static int ath5k_pci_suspend(struct device *dev)
3b5d665b 3479{
8a63facc 3480 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
3b5d665b 3481
8a63facc
BC		 3482 ath5k_led_off(sc);
3483 return 0;
3b5d665b
AF		 3484}
3485
8a63facc 3486static int ath5k_pci_resume(struct device *dev)
fa1c114f 3487{
8a63facc
BC		 3488 struct pci_dev *pdev = to_pci_dev(dev);
3489 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3490
9804b98d 3491 /*
8a63facc
BC		 3492 * Suspend/Resume resets the PCI configuration space, so we have to
3493 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3494 * PCI Tx retries from interfering with C3 CPU state
9804b98d 3495 */
8a63facc
BC		 3496 pci_write_config_byte(pdev, 0x41, 0);
3497
3498 ath5k_led_enable(sc);
3499 return 0;
fa1c114f
JS		 3500}
3501
8a63facc
BC		 3502static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
3503#define ATH5K_PM_OPS (&ath5k_pm_ops)
3504#else
3505#define ATH5K_PM_OPS NULL
3506#endif /* CONFIG_PM_SLEEP */
3507
3508static struct pci_driver ath5k_pci_driver = {
3509 .name = KBUILD_MODNAME,
3510 .id_table = ath5k_pci_id_table,
3511 .probe = ath5k_pci_probe,
3512 .remove = __devexit_p(ath5k_pci_remove),
3513 .driver.pm = ATH5K_PM_OPS,
3514};
3515
1071db86 3516/*
8a63facc 3517 * Module init/exit functions
1071db86 3518 */
8a63facc
BC		 3519static int __init
3520init_ath5k_pci(void)
fa1c114f 3521{
fa1c114f 3522 int ret;
57c4d7b4 3523
8a63facc 3524 ath5k_debug_init();
2d0ddec5 3525
8a63facc
BC		 3526 ret = pci_register_driver(&ath5k_pci_driver);
3527 if (ret) {
3528 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
3529 return ret;
2d0ddec5
JB		 3530 }
3531
8a63facc 3532 return 0;
02969b38 3533}
f0f3d388 3534
8a63facc
BC		 3535static void __exit
3536exit_ath5k_pci(void)
f0f3d388 3537{
8a63facc 3538 pci_unregister_driver(&ath5k_pci_driver);
f0f3d388 3539
8a63facc 3540 ath5k_debug_finish();
f0f3d388 3541}
6e08d228 3542
8a63facc
BC		 3543module_init(init_ath5k_pci);
3544module_exit(exit_ath5k_pci);
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