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ath/ath5k/ath9k: Fix crypto capabilities merge issue
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
6ccf15a1 51#include <linux/pci-aspm.h>
fa1c114f
JS		 52#include <linux/ethtool.h>
53#include <linux/uaccess.h>
5a0e3ad6 54#include <linux/slab.h>
fa1c114f
JS		 55
56#include <net/ieee80211_radiotap.h>
57
58#include <asm/unaligned.h>
59
60#include "base.h"
61#include "reg.h"
62#include "debug.h"
2111ac0d 63#include "ani.h"
fa1c114f 64
9ad9a26e 65static int modparam_nohwcrypt;
46802a4f 66module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 67MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 68
42639fcd 69static int modparam_all_channels;
46802a4f 70module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 71MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
72
fa1c114f
JS		 73
74/******************\
75* Internal defines *
76\******************/
77
78/* Module info */
79MODULE_AUTHOR("Jiri Slaby");
80MODULE_AUTHOR("Nick Kossifidis");
81MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
82MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
83MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 84MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 85
86
87/* Known PCI ids */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 89 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
90 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
91 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
92 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
93 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
94 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
95 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
97 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
104 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
105 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
106 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 107 { 0 }
108};
109MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110
111/* Known SREVs */
2c91108c 112static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 113 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
114 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
115 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
116 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
117 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
118 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
119 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
120 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
121 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
122 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
123 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
124 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
125 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
126 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
127 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
128 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
129 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
130 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
131 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 132 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
133 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 134 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 135 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
136 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
137 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 138 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 139 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
140 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 141 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
142 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
143 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
144 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
145 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
146 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 147 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
148 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149};
150
2c91108c 151static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 152 { .bitrate = 10,
153 .hw_value = ATH5K_RATE_CODE_1M, },
154 { .bitrate = 20,
155 .hw_value = ATH5K_RATE_CODE_2M,
156 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
157 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
158 { .bitrate = 55,
159 .hw_value = ATH5K_RATE_CODE_5_5M,
160 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
161 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
162 { .bitrate = 110,
163 .hw_value = ATH5K_RATE_CODE_11M,
164 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
165 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
166 { .bitrate = 60,
167 .hw_value = ATH5K_RATE_CODE_6M,
168 .flags = 0 },
169 { .bitrate = 90,
170 .hw_value = ATH5K_RATE_CODE_9M,
171 .flags = 0 },
172 { .bitrate = 120,
173 .hw_value = ATH5K_RATE_CODE_12M,
174 .flags = 0 },
175 { .bitrate = 180,
176 .hw_value = ATH5K_RATE_CODE_18M,
177 .flags = 0 },
178 { .bitrate = 240,
179 .hw_value = ATH5K_RATE_CODE_24M,
180 .flags = 0 },
181 { .bitrate = 360,
182 .hw_value = ATH5K_RATE_CODE_36M,
183 .flags = 0 },
184 { .bitrate = 480,
185 .hw_value = ATH5K_RATE_CODE_48M,
186 .flags = 0 },
187 { .bitrate = 540,
188 .hw_value = ATH5K_RATE_CODE_54M,
189 .flags = 0 },
190 /* XR missing */
191};
192
fa1c114f
JS		 193/*
194 * Prototypes - PCI stack related functions
195 */
196static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
197 const struct pci_device_id *id);
198static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
e307139d 199#ifdef CONFIG_PM_SLEEP
baee1f3c
RW		 200static int ath5k_pci_suspend(struct device *dev);
201static int ath5k_pci_resume(struct device *dev);
202
626ede6b 203static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
baee1f3c 204#define ATH5K_PM_OPS (&ath5k_pm_ops)
fa1c114f 205#else
baee1f3c 206#define ATH5K_PM_OPS NULL
e307139d 207#endif /* CONFIG_PM_SLEEP */
fa1c114f 208
04a9e451 209static struct pci_driver ath5k_pci_driver = {
9764f3f9 210 .name = KBUILD_MODNAME,
fa1c114f
JS		 211 .id_table = ath5k_pci_id_table,
212 .probe = ath5k_pci_probe,
213 .remove = __devexit_p(ath5k_pci_remove),
baee1f3c 214 .driver.pm = ATH5K_PM_OPS,
fa1c114f
JS		 215};
216
217
218
219/*
220 * Prototypes - MAC 802.11 stack related functions
221 */
e039fa4a 222static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 223static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
224 struct ath5k_txq *txq);
209d889b 225static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
fa1c114f
JS		 226static int ath5k_start(struct ieee80211_hw *hw);
227static void ath5k_stop(struct ieee80211_hw *hw);
228static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 229 struct ieee80211_vif *vif);
fa1c114f 230static void ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 231 struct ieee80211_vif *vif);
e8975581 232static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee 233static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 234 struct netdev_hw_addr_list *mc_list);
fa1c114f
JS		 235static void ath5k_configure_filter(struct ieee80211_hw *hw,
236 unsigned int changed_flags,
237 unsigned int *new_flags,
3ac64bee 238 u64 multicast);
fa1c114f
JS		 239static int ath5k_set_key(struct ieee80211_hw *hw,
240 enum set_key_cmd cmd,
dc822b5d 241 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 242 struct ieee80211_key_conf *key);
243static int ath5k_get_stats(struct ieee80211_hw *hw,
244 struct ieee80211_low_level_stats *stats);
55ee82b5
HS		 245static int ath5k_get_survey(struct ieee80211_hw *hw,
246 int idx, struct survey_info *survey);
fa1c114f 247static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 248static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 249static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 250static int ath5k_beacon_update(struct ieee80211_hw *hw,
251 struct ieee80211_vif *vif);
02969b38
MX		 252static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
253 struct ieee80211_vif *vif,
254 struct ieee80211_bss_conf *bss_conf,
255 u32 changes);
f0f3d388
BC		 256static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
257static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
6e08d228
LT		 258static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
259 u8 coverage_class);
fa1c114f 260
2c91108c 261static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 262 .tx = ath5k_tx,
263 .start = ath5k_start,
264 .stop = ath5k_stop,
265 .add_interface = ath5k_add_interface,
266 .remove_interface = ath5k_remove_interface,
267 .config = ath5k_config,
3ac64bee 268 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 269 .configure_filter = ath5k_configure_filter,
270 .set_key = ath5k_set_key,
271 .get_stats = ath5k_get_stats,
55ee82b5 272 .get_survey = ath5k_get_survey,
fa1c114f 273 .conf_tx = NULL,
fa1c114f 274 .get_tsf = ath5k_get_tsf,
3b5d665b 275 .set_tsf = ath5k_set_tsf,
fa1c114f 276 .reset_tsf = ath5k_reset_tsf,
02969b38 277 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 278 .sw_scan_start = ath5k_sw_scan_start,
279 .sw_scan_complete = ath5k_sw_scan_complete,
6e08d228 280 .set_coverage_class = ath5k_set_coverage_class,
fa1c114f
JS		 281};
282
283/*
284 * Prototypes - Internal functions
285 */
286/* Attach detach */
287static int ath5k_attach(struct pci_dev *pdev,
288 struct ieee80211_hw *hw);
289static void ath5k_detach(struct pci_dev *pdev,
290 struct ieee80211_hw *hw);
291/* Channel/mode setup */
292static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 293static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
294 struct ieee80211_channel *channels,
295 unsigned int mode,
296 unsigned int max);
63266a65 297static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 298static int ath5k_chan_set(struct ath5k_softc *sc,
299 struct ieee80211_channel *chan);
300static void ath5k_setcurmode(struct ath5k_softc *sc,
301 unsigned int mode);
302static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 303
fa1c114f
JS		 304/* Descriptor setup */
305static int ath5k_desc_alloc(struct ath5k_softc *sc,
306 struct pci_dev *pdev);
307static void ath5k_desc_free(struct ath5k_softc *sc,
308 struct pci_dev *pdev);
309/* Buffers setup */
310static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
311 struct ath5k_buf *bf);
312static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23 313 struct ath5k_buf *bf,
8127fbdc 314 struct ath5k_txq *txq, int padsize);
9e4e43f2
BR		 315
316static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 317 struct ath5k_buf *bf)
318{
319 BUG_ON(!bf);
320 if (!bf->skb)
321 return;
322 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
323 PCI_DMA_TODEVICE);
00482973 324 dev_kfree_skb_any(bf->skb);
fa1c114f 325 bf->skb = NULL;
39d63f2a
BR		 326 bf->skbaddr = 0;
327 bf->desc->ds_data = 0;
fa1c114f
JS		 328}
329
9e4e43f2 330static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 331 struct ath5k_buf *bf)
332{
cc861f74
LR		 333 struct ath5k_hw *ah = sc->ah;
334 struct ath_common *common = ath5k_hw_common(ah);
335
a6c8d375
FF		 336 BUG_ON(!bf);
337 if (!bf->skb)
338 return;
cc861f74 339 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 340 PCI_DMA_FROMDEVICE);
341 dev_kfree_skb_any(bf->skb);
342 bf->skb = NULL;
39d63f2a
BR		 343 bf->skbaddr = 0;
344 bf->desc->ds_data = 0;
a6c8d375
FF		 345}
346
347
fa1c114f
JS		 348/* Queues setup */
349static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
350 int qtype, int subtype);
351static int ath5k_beaconq_setup(struct ath5k_hw *ah);
352static int ath5k_beaconq_config(struct ath5k_softc *sc);
353static void ath5k_txq_drainq(struct ath5k_softc *sc,
354 struct ath5k_txq *txq);
355static void ath5k_txq_cleanup(struct ath5k_softc *sc);
356static void ath5k_txq_release(struct ath5k_softc *sc);
357/* Rx handling */
358static int ath5k_rx_start(struct ath5k_softc *sc);
359static void ath5k_rx_stop(struct ath5k_softc *sc);
360static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
b47f407b
BR		 361 struct sk_buff *skb,
362 struct ath5k_rx_status *rs);
fa1c114f
JS		 363static void ath5k_tasklet_rx(unsigned long data);
364/* Tx handling */
365static void ath5k_tx_processq(struct ath5k_softc *sc,
366 struct ath5k_txq *txq);
367static void ath5k_tasklet_tx(unsigned long data);
368/* Beacon handling */
369static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 370 struct ath5k_buf *bf);
fa1c114f
JS		 371static void ath5k_beacon_send(struct ath5k_softc *sc);
372static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 373static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 374static void ath5k_tasklet_beacon(unsigned long data);
2111ac0d 375static void ath5k_tasklet_ani(unsigned long data);
fa1c114f
JS		 376
377static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
378{
379 u64 tsf = ath5k_hw_get_tsf64(ah);
380
381 if ((tsf & 0x7fff) < rstamp)
382 tsf -= 0x8000;
383
384 return (tsf & ~0x7fff) | rstamp;
385}
386
387/* Interrupt handling */
bb2becac 388static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 389static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 390static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f 391static irqreturn_t ath5k_intr(int irq, void *dev_id);
5faaff74 392static void ath5k_reset_work(struct work_struct *work);
fa1c114f 393
6e220662 394static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 395
396/*
397 * Module init/exit functions
398 */
399static int __init
400init_ath5k_pci(void)
401{
402 int ret;
403
404 ath5k_debug_init();
405
04a9e451 406 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 407 if (ret) {
408 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
409 return ret;
410 }
411
412 return 0;
413}
414
415static void __exit
416exit_ath5k_pci(void)
417{
04a9e451 418 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 419
420 ath5k_debug_finish();
421}
422
423module_init(init_ath5k_pci);
424module_exit(exit_ath5k_pci);
425
426
427/********************\
428* PCI Initialization *
429\********************/
430
431static const char *
432ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
433{
434 const char *name = "xxxxx";
435 unsigned int i;
436
437 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
438 if (srev_names[i].sr_type != type)
439 continue;
75d0edb8
NK		 440
441 if ((val & 0xf0) == srev_names[i].sr_val)
442 name = srev_names[i].sr_name;
443
444 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 445 name = srev_names[i].sr_name;
446 break;
447 }
448 }
449
450 return name;
451}
e5aa8474
LR		 452static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
453{
454 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
455 return ath5k_hw_reg_read(ah, reg_offset);
456}
457
458static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
459{
460 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
461 ath5k_hw_reg_write(ah, val, reg_offset);
462}
463
464static const struct ath_ops ath5k_common_ops = {
465 .read = ath5k_ioread32,
466 .write = ath5k_iowrite32,
467};
fa1c114f
JS		 468
469static int __devinit
470ath5k_pci_probe(struct pci_dev *pdev,
471 const struct pci_device_id *id)
472{
473 void __iomem *mem;
474 struct ath5k_softc *sc;
db719718 475 struct ath_common *common;
fa1c114f
JS		 476 struct ieee80211_hw *hw;
477 int ret;
478 u8 csz;
479
6ccf15a1
ML		 480 /*
481 * L0s needs to be disabled on all ath5k cards.
482 *
483 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
484 * by default in the future in 2.6.36) this will also mean both L1 and
485 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
486 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
487 * though but cannot currently undue the effect of a blacklist, for
488 * details you can read pcie_aspm_sanity_check() and see how it adjusts
489 * the device link capability.
490 *
491 * It may be possible in the future to implement some PCI API to allow
492 * drivers to override blacklists for pre 1.1 PCIe but for now it is
493 * best to accept that both L0s and L1 will be disabled completely for
494 * distributions shipping with CONFIG_PCIEASPM rather than having this
495 * issue present. Motivation for adding this new API will be to help
496 * with power consumption for some of these devices.
497 */
498 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
499
fa1c114f
JS		 500 ret = pci_enable_device(pdev);
501 if (ret) {
502 dev_err(&pdev->dev, "can't enable device\n");
503 goto err;
504 }
505
506 /* XXX 32-bit addressing only */
284901a9 507 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 508 if (ret) {
509 dev_err(&pdev->dev, "32-bit DMA not available\n");
510 goto err_dis;
511 }
512
513 /*
514 * Cache line size is used to size and align various
515 * structures used to communicate with the hardware.
516 */
517 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
518 if (csz == 0) {
519 /*
520 * Linux 2.4.18 (at least) writes the cache line size
521 * register as a 16-bit wide register which is wrong.
522 * We must have this setup properly for rx buffer
523 * DMA to work so force a reasonable value here if it
524 * comes up zero.
525 */
13311b00 526 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 527 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
528 }
529 /*
530 * The default setting of latency timer yields poor results,
531 * set it to the value used by other systems. It may be worth
532 * tweaking this setting more.
533 */
534 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
535
536 /* Enable bus mastering */
537 pci_set_master(pdev);
538
539 /*
540 * Disable the RETRY_TIMEOUT register (0x41) to keep
541 * PCI Tx retries from interfering with C3 CPU state.
542 */
543 pci_write_config_byte(pdev, 0x41, 0);
544
545 ret = pci_request_region(pdev, 0, "ath5k");
546 if (ret) {
547 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
548 goto err_dis;
549 }
550
551 mem = pci_iomap(pdev, 0, 0);
552 if (!mem) {
553 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
554 ret = -EIO;
555 goto err_reg;
556 }
557
558 /*
559 * Allocate hw (mac80211 main struct)
560 * and hw->priv (driver private data)
561 */
562 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
563 if (hw == NULL) {
564 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
565 ret = -ENOMEM;
566 goto err_map;
567 }
568
569 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
570
571 /* Initialize driver private data */
572 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 573 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 574 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
f5c044e5 575 IEEE80211_HW_SIGNAL_DBM;
f59ac048
LR		 576
577 hw->wiphy->interface_modes =
6f5f39c9 578 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 579 BIT(NL80211_IFTYPE_STATION) |
580 BIT(NL80211_IFTYPE_ADHOC) |
581 BIT(NL80211_IFTYPE_MESH_POINT);
582
fa1c114f
JS		 583 hw->extra_tx_headroom = 2;
584 hw->channel_change_time = 5000;
fa1c114f
JS		 585 sc = hw->priv;
586 sc->hw = hw;
587 sc->pdev = pdev;
588
589 ath5k_debug_init_device(sc);
590
591 /*
592 * Mark the device as detached to avoid processing
593 * interrupts until setup is complete.
594 */
595 __set_bit(ATH_STAT_INVALID, sc->status);
596
597 sc->iobase = mem; /* So we can unmap it on detach */
05c914fe 598 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 599 sc->bintval = 1000;
fa1c114f
JS		 600 mutex_init(&sc->lock);
601 spin_lock_init(&sc->rxbuflock);
602 spin_lock_init(&sc->txbuflock);
00482973 603 spin_lock_init(&sc->block);
fa1c114f
JS		 604
605 /* Set private data */
6673e2e8 606 pci_set_drvdata(pdev, sc);
fa1c114f 607
fa1c114f
JS		 608 /* Setup interrupt handler */
609 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
610 if (ret) {
611 ATH5K_ERR(sc, "request_irq failed\n");
612 goto err_free;
613 }
614
a180a130 615 /* If we passed the test, malloc an ath5k_hw struct */
9adca126
LR		 616 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
617 if (!sc->ah) {
618 ret = -ENOMEM;
619 ATH5K_ERR(sc, "out of memory\n");
fa1c114f
JS		 620 goto err_irq;
621 }
622
9adca126
LR		 623 sc->ah->ah_sc = sc;
624 sc->ah->ah_iobase = sc->iobase;
db719718 625 common = ath5k_hw_common(sc->ah);
e5aa8474 626 common->ops = &ath5k_common_ops;
13b81559 627 common->ah = sc->ah;
b002a4a9 628 common->hw = hw;
db719718
LR		 629 common->cachelsz = csz << 2; /* convert to bytes */
630
9adca126
LR		 631 /* Initialize device */
632 ret = ath5k_hw_attach(sc);
633 if (ret) {
634 goto err_free_ah;
635 }
636
2f7fe870
FF		 637 /* set up multi-rate retry capabilities */
638 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 639 hw->max_rates = 4;
640 hw->max_rate_tries = 11;
2f7fe870
FF		 641 }
642
fa1c114f
JS		 643 /* Finish private driver data initialization */
644 ret = ath5k_attach(pdev, hw);
645 if (ret)
646 goto err_ah;
647
648 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 649 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 650 sc->ah->ah_mac_srev,
651 sc->ah->ah_phy_revision);
652
400ec45a 653 if (!sc->ah->ah_single_chip) {
fa1c114f 654 /* Single chip radio (!RF5111) */
400ec45a
LR		 655 if (sc->ah->ah_radio_5ghz_revision &&
656 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 657 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 658 if (!test_bit(AR5K_MODE_11A,
659 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 660 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 661 ath5k_chip_name(AR5K_VERSION_RAD,
662 sc->ah->ah_radio_5ghz_revision),
663 sc->ah->ah_radio_5ghz_revision);
664 /* No 2GHz support (5110 and some
665 * 5Ghz only cards) -> report 5Ghz radio */
666 } else if (!test_bit(AR5K_MODE_11B,
667 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 668 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 669 ath5k_chip_name(AR5K_VERSION_RAD,
670 sc->ah->ah_radio_5ghz_revision),
671 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 672 /* Multiband radio */
673 } else {
674 ATH5K_INFO(sc, "RF%s multiband radio found"
675 " (0x%x)\n",
400ec45a
LR		 676 ath5k_chip_name(AR5K_VERSION_RAD,
677 sc->ah->ah_radio_5ghz_revision),
678 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 679 }
680 }
400ec45a
LR		 681 /* Multi chip radio (RF5111 - RF2111) ->
682 * report both 2GHz/5GHz radios */
683 else if (sc->ah->ah_radio_5ghz_revision &&
684 sc->ah->ah_radio_2ghz_revision){
fa1c114f 685 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 686 ath5k_chip_name(AR5K_VERSION_RAD,
687 sc->ah->ah_radio_5ghz_revision),
688 sc->ah->ah_radio_5ghz_revision);
fa1c114f 689 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 690 ath5k_chip_name(AR5K_VERSION_RAD,
691 sc->ah->ah_radio_2ghz_revision),
692 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 693 }
694 }
695
696
697 /* ready to process interrupts */
698 __clear_bit(ATH_STAT_INVALID, sc->status);
699
700 return 0;
701err_ah:
702 ath5k_hw_detach(sc->ah);
9adca126
LR		 703err_free_ah:
704 kfree(sc->ah);
df1c2986
DC		 705err_irq:
706 free_irq(pdev->irq, sc);
fa1c114f 707err_free:
fa1c114f
JS		 708 ieee80211_free_hw(hw);
709err_map:
710 pci_iounmap(pdev, mem);
711err_reg:
712 pci_release_region(pdev, 0);
713err_dis:
714 pci_disable_device(pdev);
715err:
716 return ret;
717}
718
719static void __devexit
720ath5k_pci_remove(struct pci_dev *pdev)
721{
6673e2e8 722 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f
JS		 723
724 ath5k_debug_finish_device(sc);
6673e2e8 725 ath5k_detach(pdev, sc->hw);
fa1c114f 726 ath5k_hw_detach(sc->ah);
9adca126 727 kfree(sc->ah);
fa1c114f 728 free_irq(pdev->irq, sc);
fa1c114f
JS		 729 pci_iounmap(pdev, sc->iobase);
730 pci_release_region(pdev, 0);
731 pci_disable_device(pdev);
6673e2e8 732 ieee80211_free_hw(sc->hw);
fa1c114f
JS		 733}
734
e307139d 735#ifdef CONFIG_PM_SLEEP
baee1f3c 736static int ath5k_pci_suspend(struct device *dev)
fa1c114f 737{
6673e2e8 738 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
fa1c114f 739
3a078876 740 ath5k_led_off(sc);
fa1c114f
JS		 741 return 0;
742}
743
baee1f3c 744static int ath5k_pci_resume(struct device *dev)
fa1c114f 745{
baee1f3c 746 struct pci_dev *pdev = to_pci_dev(dev);
6673e2e8 747 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 748
8451d22d
JM		 749 /*
750 * Suspend/Resume resets the PCI configuration space, so we have to
751 * re-disable the RETRY_TIMEOUT register (0x41) to keep
752 * PCI Tx retries from interfering with C3 CPU state
753 */
754 pci_write_config_byte(pdev, 0x41, 0);
755
3a078876 756 ath5k_led_enable(sc);
fa1c114f
JS		 757 return 0;
758}
e307139d 759#endif /* CONFIG_PM_SLEEP */
fa1c114f
JS		 760
761
fa1c114f
JS		 762/***********************\
763* Driver Initialization *
764\***********************/
765
f769c36b
BC		 766static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
767{
768 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
769 struct ath5k_softc *sc = hw->priv;
db719718 770 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
f769c36b 771
608b88cb 772 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 773}
774
fa1c114f
JS		 775static int
776ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
777{
778 struct ath5k_softc *sc = hw->priv;
779 struct ath5k_hw *ah = sc->ah;
db719718 780 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
0e149cf5 781 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 782 int ret;
783
784 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
785
786 /*
787 * Check if the MAC has multi-rate retry support.
788 * We do this by trying to setup a fake extended
a180a130
BC		 789 * descriptor. MACs that don't have support will
790 * return false w/o doing anything. MACs that do
fa1c114f
JS		 791 * support it will return true w/o doing anything.
792 */
a6668193
BR		 793 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
794
b9887638
JS		 795 if (ret < 0)
796 goto err;
797 if (ret > 0)
fa1c114f
JS		 798 __set_bit(ATH_STAT_MRRETRY, sc->status);
799
fa1c114f
JS		 800 /*
801 * Collect the channel list. The 802.11 layer
802 * is resposible for filtering this list based
803 * on settings like the phy mode and regulatory
804 * domain restrictions.
805 */
63266a65 806 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 807 if (ret) {
808 ATH5K_ERR(sc, "can't get channels\n");
809 goto err;
810 }
811
812 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 813 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
814 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 815 else
d8ee398d 816 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 817
818 /*
819 * Allocate tx+rx descriptors and populate the lists.
820 */
821 ret = ath5k_desc_alloc(sc, pdev);
822 if (ret) {
823 ATH5K_ERR(sc, "can't allocate descriptors\n");
824 goto err;
825 }
826
827 /*
828 * Allocate hardware transmit queues: one queue for
829 * beacon frames and one data queue for each QoS
a180a130 830 * priority. Note that hw functions handle resetting
fa1c114f
JS		 831 * these queues at the needed time.
832 */
833 ret = ath5k_beaconq_setup(ah);
834 if (ret < 0) {
835 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
836 goto err_desc;
837 }
838 sc->bhalq = ret;
cec8db23
BC		 839 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
840 if (IS_ERR(sc->cabq)) {
841 ATH5K_ERR(sc, "can't setup cab queue\n");
842 ret = PTR_ERR(sc->cabq);
843 goto err_bhal;
844 }
fa1c114f
JS		 845
846 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
847 if (IS_ERR(sc->txq)) {
848 ATH5K_ERR(sc, "can't setup xmit queue\n");
849 ret = PTR_ERR(sc->txq);
cec8db23 850 goto err_queues;
fa1c114f
JS		 851 }
852
853 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
854 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
6e220662 855 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 856 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2111ac0d 857 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
fa1c114f 858
5faaff74
BC		 859 INIT_WORK(&sc->reset_work, ath5k_reset_work);
860
0e149cf5
BC		 861 ret = ath5k_eeprom_read_mac(ah, mac);
862 if (ret) {
863 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
864 sc->pdev->device);
865 goto err_queues;
866 }
867
fa1c114f
JS		 868 SET_IEEE80211_PERM_ADDR(hw, mac);
869 /* All MAC address bits matter for ACKs */
17753748 870 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 871 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
872
608b88cb
LR		 873 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
874 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 875 if (ret) {
876 ATH5K_ERR(sc, "can't initialize regulatory system\n");
877 goto err_queues;
878 }
879
fa1c114f
JS		 880 ret = ieee80211_register_hw(hw);
881 if (ret) {
882 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
883 goto err_queues;
884 }
885
608b88cb
LR		 886 if (!ath_is_world_regd(regulatory))
887 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 888
3a078876
BC		 889 ath5k_init_leds(sc);
890
40ca22ea
BR		 891 ath5k_sysfs_register(sc);
892
fa1c114f
JS		 893 return 0;
894err_queues:
895 ath5k_txq_release(sc);
896err_bhal:
897 ath5k_hw_release_tx_queue(ah, sc->bhalq);
898err_desc:
899 ath5k_desc_free(sc, pdev);
900err:
901 return ret;
902}
903
904static void
905ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
906{
907 struct ath5k_softc *sc = hw->priv;
908
909 /*
910 * NB: the order of these is important:
911 * o call the 802.11 layer before detaching ath5k_hw to
a180a130 912 * ensure callbacks into the driver to delete global
fa1c114f
JS		 913 * key cache entries can be handled
914 * o reclaim the tx queue data structures after calling
915 * the 802.11 layer as we'll get called back to reclaim
916 * node state and potentially want to use them
917 * o to cleanup the tx queues the hal is called, so detach
918 * it last
919 * XXX: ??? detach ath5k_hw ???
920 * Other than that, it's straightforward...
921 */
922 ieee80211_unregister_hw(hw);
923 ath5k_desc_free(sc, pdev);
924 ath5k_txq_release(sc);
925 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 926 ath5k_unregister_leds(sc);
fa1c114f 927
40ca22ea 928 ath5k_sysfs_unregister(sc);
fa1c114f
JS		 929 /*
930 * NB: can't reclaim these until after ieee80211_ifdetach
931 * returns because we'll get called back to reclaim node
932 * state and potentially want to use them.
933 */
934}
935
936
937
938
939/********************\
940* Channel/mode setup *
941\********************/
942
943/*
944 * Convert IEEE channel number to MHz frequency.
945 */
946static inline short
947ath5k_ieee2mhz(short chan)
948{
949 if (chan <= 14 || chan >= 27)
950 return ieee80211chan2mhz(chan);
951 else
952 return 2212 + chan * 20;
953}
954
42639fcd
BC		 955/*
956 * Returns true for the channel numbers used without all_channels modparam.
957 */
958static bool ath5k_is_standard_channel(short chan)
959{
960 return ((chan <= 14) ||
961 /* UNII 1,2 */
962 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
963 /* midband */
964 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
965 /* UNII-3 */
966 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
967}
968
fa1c114f
JS		 969static unsigned int
970ath5k_copy_channels(struct ath5k_hw *ah,
971 struct ieee80211_channel *channels,
972 unsigned int mode,
973 unsigned int max)
974{
d8ee398d 975 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 976
977 if (!test_bit(mode, ah->ah_modes))
978 return 0;
979
fa1c114f 980 switch (mode) {
d8ee398d
LR		 981 case AR5K_MODE_11A:
982 case AR5K_MODE_11A_TURBO:
fa1c114f 983 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 984 size = 220 ;
fa1c114f
JS		 985 chfreq = CHANNEL_5GHZ;
986 break;
d8ee398d
LR		 987 case AR5K_MODE_11B:
988 case AR5K_MODE_11G:
989 case AR5K_MODE_11G_TURBO:
990 size = 26;
fa1c114f
JS		 991 chfreq = CHANNEL_2GHZ;
992 break;
993 default:
994 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
995 return 0;
996 }
997
998 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 999 ch = i + 1 ;
1000 freq = ath5k_ieee2mhz(ch);
fa1c114f 1001
d8ee398d
LR		 1002 /* Check if channel is supported by the chipset */
1003 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 1004 continue;
1005
42639fcd
BC		 1006 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
1007 continue;
1008
d8ee398d
LR		 1009 /* Write channel info and increment counter */
1010 channels[count].center_freq = freq;
a3f4b914
LR		 1011 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
1012 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 1013 switch (mode) {
1014 case AR5K_MODE_11A:
1015 case AR5K_MODE_11G:
1016 channels[count].hw_value = chfreq | CHANNEL_OFDM;
1017 break;
1018 case AR5K_MODE_11A_TURBO:
1019 case AR5K_MODE_11G_TURBO:
1020 channels[count].hw_value = chfreq |
1021 CHANNEL_OFDM | CHANNEL_TURBO;
1022 break;
1023 case AR5K_MODE_11B:
d8ee398d
LR		 1024 channels[count].hw_value = CHANNEL_B;
1025 }
fa1c114f 1026
fa1c114f
JS		 1027 count++;
1028 max--;
1029 }
1030
1031 return count;
1032}
1033
63266a65
BR		 1034static void
1035ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1036{
1037 u8 i;
1038
1039 for (i = 0; i < AR5K_MAX_RATES; i++)
1040 sc->rate_idx[b->band][i] = -1;
1041
1042 for (i = 0; i < b->n_bitrates; i++) {
1043 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1044 if (b->bitrates[i].hw_value_short)
1045 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1046 }
1047}
1048
d8ee398d 1049static int
63266a65 1050ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1051{
1052 struct ath5k_softc *sc = hw->priv;
d8ee398d 1053 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1054 struct ieee80211_supported_band *sband;
1055 int max_c, count_c = 0;
1056 int i;
fa1c114f 1057
d8ee398d 1058 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1059 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1060
1061 /* 2GHz band */
63266a65
BR		 1062 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1063 sband->band = IEEE80211_BAND_2GHZ;
1064 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1065
63266a65
BR		 1066 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1067 /* G mode */
1068 memcpy(sband->bitrates, &ath5k_rates[0],
1069 sizeof(struct ieee80211_rate) * 12);
1070 sband->n_bitrates = 12;
fa1c114f 1071
d8ee398d 1072 sband->channels = sc->channels;
d8ee398d 1073 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1074 AR5K_MODE_11G, max_c);
fa1c114f 1075
63266a65 1076 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1077 count_c = sband->n_channels;
63266a65
BR		 1078 max_c -= count_c;
1079 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1080 /* B mode */
1081 memcpy(sband->bitrates, &ath5k_rates[0],
1082 sizeof(struct ieee80211_rate) * 4);
1083 sband->n_bitrates = 4;
1084
1085 /* 5211 only supports B rates and uses 4bit rate codes
1086 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1087 * fix them up here:
1088 */
1089 if (ah->ah_version == AR5K_AR5211) {
1090 for (i = 0; i < 4; i++) {
1091 sband->bitrates[i].hw_value =
1092 sband->bitrates[i].hw_value & 0xF;
1093 sband->bitrates[i].hw_value_short =
1094 sband->bitrates[i].hw_value_short & 0xF;
1095 }
1096 }
fa1c114f 1097
63266a65
BR		 1098 sband->channels = sc->channels;
1099 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1100 AR5K_MODE_11B, max_c);
d8ee398d 1101
63266a65
BR		 1102 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1103 count_c = sband->n_channels;
d8ee398d 1104 max_c -= count_c;
fa1c114f 1105 }
63266a65 1106 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1107
63266a65 1108 /* 5GHz band, A mode */
400ec45a 1109 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1110 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1111 sband->band = IEEE80211_BAND_5GHZ;
1112 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1113
63266a65
BR		 1114 memcpy(sband->bitrates, &ath5k_rates[4],
1115 sizeof(struct ieee80211_rate) * 8);
1116 sband->n_bitrates = 8;
fa1c114f 1117
63266a65 1118 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1119 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1120 AR5K_MODE_11A, max_c);
1121
d8ee398d
LR		 1122 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1123 }
63266a65 1124 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1125
b446197c 1126 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1127
1128 return 0;
fa1c114f
JS		 1129}
1130
1131/*
e30eb4ab
JA		 1132 * Set/change channels. We always reset the chip.
1133 * To accomplish this we must first cleanup any pending DMA,
1134 * then restart stuff after a la ath5k_init.
be009370
BC		 1135 *
1136 * Called with sc->lock.
fa1c114f
JS		 1137 */
1138static int
1139ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1140{
8d67a031
BR		 1141 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1142 "channel set, resetting (%u -> %u MHz)\n",
1143 sc->curchan->center_freq, chan->center_freq);
d8ee398d 1144
e30eb4ab
JA		 1145 /*
1146 * To switch channels clear any pending DMA operations;
1147 * wait long enough for the RX fifo to drain, reset the
1148 * hardware at the new frequency, and then re-enable
1149 * the relevant bits of the h/w.
1150 */
1151 return ath5k_reset(sc, chan);
fa1c114f
JS		 1152}
1153
1154static void
1155ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1156{
fa1c114f 1157 sc->curmode = mode;
d8ee398d 1158
400ec45a 1159 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1160 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1161 } else {
1162 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1163 }
fa1c114f
JS		 1164}
1165
1166static void
1167ath5k_mode_setup(struct ath5k_softc *sc)
1168{
1169 struct ath5k_hw *ah = sc->ah;
1170 u32 rfilt;
1171
1172 /* configure rx filter */
1173 rfilt = sc->filter_flags;
1174 ath5k_hw_set_rx_filter(ah, rfilt);
1175
1176 if (ath5k_hw_hasbssidmask(ah))
1177 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1178
1179 /* configure operational mode */
ccfe5552 1180 ath5k_hw_set_opmode(ah, sc->opmode);
fa1c114f 1181
ccfe5552 1182 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
fa1c114f
JS		 1183 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1184}
1185
d8ee398d 1186static inline int
63266a65
BR		 1187ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1188{
b7266047
BC		 1189 int rix;
1190
1191 /* return base rate on errors */
1192 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1193 "hw_rix out of bounds: %x\n", hw_rix))
1194 return 0;
1195
1196 rix = sc->rate_idx[sc->curband->band][hw_rix];
1197 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1198 rix = 0;
1199
1200 return rix;
d8ee398d
LR		 1201}
1202
fa1c114f
JS		 1203/***************\
1204* Buffers setup *
1205\***************/
1206
b6ea0356
BC		 1207static
1208struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1209{
db719718 1210 struct ath_common *common = ath5k_hw_common(sc->ah);
b6ea0356 1211 struct sk_buff *skb;
b6ea0356
BC		 1212
1213 /*
1214 * Allocate buffer with headroom_needed space for the
1215 * fake physical layer header at the start.
1216 */
db719718 1217 skb = ath_rxbuf_alloc(common,
dd849782 1218 common->rx_bufsize,
aeb63cfd 1219 GFP_ATOMIC);
b6ea0356
BC		 1220
1221 if (!skb) {
1222 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
dd849782 1223 common->rx_bufsize);
b6ea0356
BC		 1224 return NULL;
1225 }
b6ea0356
BC		 1226
1227 *skb_addr = pci_map_single(sc->pdev,
cc861f74
LR		 1228 skb->data, common->rx_bufsize,
1229 PCI_DMA_FROMDEVICE);
b6ea0356
BC		 1230 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1231 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1232 dev_kfree_skb(skb);
1233 return NULL;
1234 }
1235 return skb;
1236}
1237
fa1c114f
JS		 1238static int
1239ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1240{
1241 struct ath5k_hw *ah = sc->ah;
1242 struct sk_buff *skb = bf->skb;
1243 struct ath5k_desc *ds;
b5eae9ff 1244 int ret;
fa1c114f 1245
b6ea0356
BC		 1246 if (!skb) {
1247 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1248 if (!skb)
fa1c114f 1249 return -ENOMEM;
fa1c114f 1250 bf->skb = skb;
fa1c114f
JS		 1251 }
1252
1253 /*
1254 * Setup descriptors. For receive we always terminate
1255 * the descriptor list with a self-linked entry so we'll
1256 * not get overrun under high load (as can happen with a
1257 * 5212 when ANI processing enables PHY error frames).
1258 *
beade636 1259 * To ensure the last descriptor is self-linked we create
fa1c114f
JS		 1260 * each descriptor as self-linked and add it to the end. As
1261 * each additional descriptor is added the previous self-linked
beade636 1262 * entry is "fixed" naturally. This should be safe even
fa1c114f
JS		 1263 * if DMA is happening. When processing RX interrupts we
1264 * never remove/process the last, self-linked, entry on the
beade636 1265 * descriptor list. This ensures the hardware always has
fa1c114f
JS		 1266 * someplace to write a new frame.
1267 */
1268 ds = bf->desc;
1269 ds->ds_link = bf->daddr; /* link to self */
1270 ds->ds_data = bf->skbaddr;
a6668193 1271 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
0452d4a5
BR		 1272 if (ret) {
1273 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
b5eae9ff 1274 return ret;
0452d4a5 1275 }
fa1c114f
JS		 1276
1277 if (sc->rxlink != NULL)
1278 *sc->rxlink = bf->daddr;
1279 sc->rxlink = &ds->ds_link;
1280 return 0;
1281}
1282
2ac2927a
BC		 1283static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1284{
1285 struct ieee80211_hdr *hdr;
1286 enum ath5k_pkt_type htype;
1287 __le16 fc;
1288
1289 hdr = (struct ieee80211_hdr *)skb->data;
1290 fc = hdr->frame_control;
1291
1292 if (ieee80211_is_beacon(fc))
1293 htype = AR5K_PKT_TYPE_BEACON;
1294 else if (ieee80211_is_probe_resp(fc))
1295 htype = AR5K_PKT_TYPE_PROBE_RESP;
1296 else if (ieee80211_is_atim(fc))
1297 htype = AR5K_PKT_TYPE_ATIM;
1298 else if (ieee80211_is_pspoll(fc))
1299 htype = AR5K_PKT_TYPE_PSPOLL;
1300 else
1301 htype = AR5K_PKT_TYPE_NORMAL;
1302
1303 return htype;
1304}
1305
fa1c114f 1306static int
cec8db23 1307ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
8127fbdc 1308 struct ath5k_txq *txq, int padsize)
fa1c114f
JS		 1309{
1310 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1311 struct ath5k_desc *ds = bf->desc;
1312 struct sk_buff *skb = bf->skb;
a888d52d 1313 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1314 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1315 struct ieee80211_rate *rate;
1316 unsigned int mrr_rate[3], mrr_tries[3];
1317 int i, ret;
8902ff4e 1318 u16 hw_rate;
07c1e852
BC		 1319 u16 cts_rate = 0;
1320 u16 duration = 0;
8902ff4e 1321 u8 rc_flags;
fa1c114f
JS		 1322
1323 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1324
fa1c114f
JS		 1325 /* XXX endianness */
1326 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1327 PCI_DMA_TODEVICE);
1328
8902ff4e
BC		 1329 rate = ieee80211_get_tx_rate(sc->hw, info);
1330
e039fa4a 1331 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1332 flags |= AR5K_TXDESC_NOACK;
1333
8902ff4e
BC		 1334 rc_flags = info->control.rates[0].flags;
1335 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1336 rate->hw_value_short : rate->hw_value;
1337
281c56dd 1338 pktlen = skb->len;
fa1c114f 1339
8f655dde
NK		 1340 /* FIXME: If we are in g mode and rate is a CCK rate
1341 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1342 * from tx power (value is in dB units already) */
362695e1
BC		 1343 if (info->control.hw_key) {
1344 keyidx = info->control.hw_key->hw_key_idx;
1345 pktlen += info->control.hw_key->icv_len;
1346 }
07c1e852
BC		 1347 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1348 flags |= AR5K_TXDESC_RTSENA;
1349 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1350 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1351 sc->vif, pktlen, info));
1352 }
1353 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1354 flags |= AR5K_TXDESC_CTSENA;
1355 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1356 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1357 sc->vif, pktlen, info));
1358 }
fa1c114f 1359 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
8127fbdc 1360 ieee80211_get_hdrlen_from_skb(skb), padsize,
2ac2927a 1361 get_hw_packet_type(skb),
2e92e6f2 1362 (sc->power_level * 2),
8902ff4e 1363 hw_rate,
2bed03eb 1364 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1365 cts_rate, duration);
fa1c114f
JS		 1366 if (ret)
1367 goto err_unmap;
1368
2f7fe870
FF		 1369 memset(mrr_rate, 0, sizeof(mrr_rate));
1370 memset(mrr_tries, 0, sizeof(mrr_tries));
1371 for (i = 0; i < 3; i++) {
1372 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1373 if (!rate)
1374 break;
1375
1376 mrr_rate[i] = rate->hw_value;
e6a9854b 1377 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1378 }
1379
a6668193 1380 ath5k_hw_setup_mrr_tx_desc(ah, ds,
2f7fe870
FF		 1381 mrr_rate[0], mrr_tries[0],
1382 mrr_rate[1], mrr_tries[1],
1383 mrr_rate[2], mrr_tries[2]);
1384
fa1c114f
JS		 1385 ds->ds_link = 0;
1386 ds->ds_data = bf->skbaddr;
1387
1388 spin_lock_bh(&txq->lock);
1389 list_add_tail(&bf->list, &txq->q);
fa1c114f 1390 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1391 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1392 else /* no, so only link it */
1393 *txq->link = bf->daddr;
1394
1395 txq->link = &ds->ds_link;
c6e387a2 1396 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1397 mmiowb();
fa1c114f
JS		 1398 spin_unlock_bh(&txq->lock);
1399
1400 return 0;
1401err_unmap:
1402 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1403 return ret;
1404}
1405
1406/*******************\
1407* Descriptors setup *
1408\*******************/
1409
1410static int
1411ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1412{
1413 struct ath5k_desc *ds;
1414 struct ath5k_buf *bf;
1415 dma_addr_t da;
1416 unsigned int i;
1417 int ret;
1418
1419 /* allocate descriptors */
1420 sc->desc_len = sizeof(struct ath5k_desc) *
1421 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1422 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1423 if (sc->desc == NULL) {
1424 ATH5K_ERR(sc, "can't allocate descriptors\n");
1425 ret = -ENOMEM;
1426 goto err;
1427 }
1428 ds = sc->desc;
1429 da = sc->desc_daddr;
1430 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1431 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1432
1433 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1434 sizeof(struct ath5k_buf), GFP_KERNEL);
1435 if (bf == NULL) {
1436 ATH5K_ERR(sc, "can't allocate bufptr\n");
1437 ret = -ENOMEM;
1438 goto err_free;
1439 }
1440 sc->bufptr = bf;
1441
1442 INIT_LIST_HEAD(&sc->rxbuf);
1443 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1444 bf->desc = ds;
1445 bf->daddr = da;
1446 list_add_tail(&bf->list, &sc->rxbuf);
1447 }
1448
1449 INIT_LIST_HEAD(&sc->txbuf);
1450 sc->txbuf_len = ATH_TXBUF;
1451 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1452 da += sizeof(*ds)) {
1453 bf->desc = ds;
1454 bf->daddr = da;
1455 list_add_tail(&bf->list, &sc->txbuf);
1456 }
1457
1458 /* beacon buffer */
1459 bf->desc = ds;
1460 bf->daddr = da;
1461 sc->bbuf = bf;
1462
1463 return 0;
1464err_free:
1465 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1466err:
1467 sc->desc = NULL;
1468 return ret;
1469}
1470
1471static void
1472ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1473{
1474 struct ath5k_buf *bf;
1475
9e4e43f2 1476 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 1477 list_for_each_entry(bf, &sc->txbuf, list)
9e4e43f2 1478 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1479 list_for_each_entry(bf, &sc->rxbuf, list)
9e4e43f2 1480 ath5k_rxbuf_free_skb(sc, bf);
fa1c114f
JS		 1481
1482 /* Free memory associated with all descriptors */
1483 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
39d63f2a
BR		 1484 sc->desc = NULL;
1485 sc->desc_daddr = 0;
fa1c114f
JS		 1486
1487 kfree(sc->bufptr);
1488 sc->bufptr = NULL;
39d63f2a 1489 sc->bbuf = NULL;
fa1c114f
JS		 1490}
1491
1492
1493
1494
1495
1496/**************\
1497* Queues setup *
1498\**************/
1499
1500static struct ath5k_txq *
1501ath5k_txq_setup(struct ath5k_softc *sc,
1502 int qtype, int subtype)
1503{
1504 struct ath5k_hw *ah = sc->ah;
1505 struct ath5k_txq *txq;
1506 struct ath5k_txq_info qi = {
1507 .tqi_subtype = subtype,
1508 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1509 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1510 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1511 };
1512 int qnum;
1513
1514 /*
1515 * Enable interrupts only for EOL and DESC conditions.
1516 * We mark tx descriptors to receive a DESC interrupt
a180a130 1517 * when a tx queue gets deep; otherwise we wait for the
fa1c114f
JS		 1518 * EOL to reap descriptors. Note that this is done to
1519 * reduce interrupt load and this only defers reaping
1520 * descriptors, never transmitting frames. Aside from
1521 * reducing interrupts this also permits more concurrency.
1522 * The only potential downside is if the tx queue backs
1523 * up in which case the top half of the kernel may backup
1524 * due to a lack of tx descriptors.
1525 */
1526 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1527 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1528 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1529 if (qnum < 0) {
1530 /*
1531 * NB: don't print a message, this happens
1532 * normally on parts with too few tx queues
1533 */
1534 return ERR_PTR(qnum);
1535 }
1536 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1537 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1538 qnum, ARRAY_SIZE(sc->txqs));
1539 ath5k_hw_release_tx_queue(ah, qnum);
1540 return ERR_PTR(-EINVAL);
1541 }
1542 txq = &sc->txqs[qnum];
1543 if (!txq->setup) {
1544 txq->qnum = qnum;
1545 txq->link = NULL;
1546 INIT_LIST_HEAD(&txq->q);
1547 spin_lock_init(&txq->lock);
1548 txq->setup = true;
1549 }
1550 return &sc->txqs[qnum];
1551}
1552
1553static int
1554ath5k_beaconq_setup(struct ath5k_hw *ah)
1555{
1556 struct ath5k_txq_info qi = {
1557 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1558 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1559 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1560 /* NB: for dynamic turbo, don't enable any other interrupts */
1561 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1562 };
1563
1564 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1565}
1566
1567static int
1568ath5k_beaconq_config(struct ath5k_softc *sc)
1569{
1570 struct ath5k_hw *ah = sc->ah;
1571 struct ath5k_txq_info qi;
1572 int ret;
1573
1574 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1575 if (ret)
a951ae21
BC		 1576 goto err;
1577
05c914fe
JB		 1578 if (sc->opmode == NL80211_IFTYPE_AP ||
1579 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1580 /*
1581 * Always burst out beacon and CAB traffic
1582 * (aifs = cwmin = cwmax = 0)
1583 */
1584 qi.tqi_aifs = 0;
1585 qi.tqi_cw_min = 0;
1586 qi.tqi_cw_max = 0;
05c914fe 1587 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1588 /*
1589 * Adhoc mode; backoff between 0 and (2 * cw_min).
1590 */
1591 qi.tqi_aifs = 0;
1592 qi.tqi_cw_min = 0;
1593 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1594 }
1595
6d91e1d8
BR		 1596 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1597 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1598 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1599
c6e387a2 1600 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1601 if (ret) {
1602 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1603 "hardware queue!\n", __func__);
a951ae21 1604 goto err;
fa1c114f 1605 }
a951ae21
BC		 1606 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1607 if (ret)
1608 goto err;
fa1c114f 1609
a951ae21
BC		 1610 /* reconfigure cabq with ready time to 80% of beacon_interval */
1611 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1612 if (ret)
1613 goto err;
1614
1615 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1616 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1617 if (ret)
1618 goto err;
1619
1620 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1621err:
1622 return ret;
fa1c114f
JS		 1623}
1624
1625static void
1626ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1627{
1628 struct ath5k_buf *bf, *bf0;
1629
1630 /*
1631 * NB: this assumes output has been stopped and
1632 * we do not need to block ath5k_tx_tasklet
1633 */
1634 spin_lock_bh(&txq->lock);
1635 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1636 ath5k_debug_printtxbuf(sc, bf);
fa1c114f 1637
9e4e43f2 1638 ath5k_txbuf_free_skb(sc, bf);
fa1c114f
JS		 1639
1640 spin_lock_bh(&sc->txbuflock);
fa1c114f
JS		 1641 list_move_tail(&bf->list, &sc->txbuf);
1642 sc->txbuf_len++;
1643 spin_unlock_bh(&sc->txbuflock);
1644 }
1645 txq->link = NULL;
1646 spin_unlock_bh(&txq->lock);
1647}
1648
1649/*
1650 * Drain the transmit queues and reclaim resources.
1651 */
1652static void
1653ath5k_txq_cleanup(struct ath5k_softc *sc)
1654{
1655 struct ath5k_hw *ah = sc->ah;
1656 unsigned int i;
1657
1658 /* XXX return value */
1659 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1660 /* don't touch the hardware if marked invalid */
1661 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1662 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1663 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1664 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1665 if (sc->txqs[i].setup) {
1666 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1667 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1668 "link %p\n",
1669 sc->txqs[i].qnum,
c6e387a2 1670 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1671 sc->txqs[i].qnum),
1672 sc->txqs[i].link);
1673 }
1674 }
fa1c114f
JS		 1675
1676 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1677 if (sc->txqs[i].setup)
1678 ath5k_txq_drainq(sc, &sc->txqs[i]);
1679}
1680
1681static void
1682ath5k_txq_release(struct ath5k_softc *sc)
1683{
1684 struct ath5k_txq *txq = sc->txqs;
1685 unsigned int i;
1686
1687 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1688 if (txq->setup) {
1689 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1690 txq->setup = false;
1691 }
1692}
1693
1694
1695
1696
1697/*************\
1698* RX Handling *
1699\*************/
1700
1701/*
1702 * Enable the receive h/w following a reset.
1703 */
1704static int
1705ath5k_rx_start(struct ath5k_softc *sc)
1706{
1707 struct ath5k_hw *ah = sc->ah;
db719718 1708 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 1709 struct ath5k_buf *bf;
1710 int ret;
1711
b6127980 1712 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1713
cc861f74
LR		 1714 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1715 common->cachelsz, common->rx_bufsize);
fa1c114f 1716
fa1c114f 1717 spin_lock_bh(&sc->rxbuflock);
26925042 1718 sc->rxlink = NULL;
fa1c114f
JS		 1719 list_for_each_entry(bf, &sc->rxbuf, list) {
1720 ret = ath5k_rxbuf_setup(sc, bf);
1721 if (ret != 0) {
1722 spin_unlock_bh(&sc->rxbuflock);
1723 goto err;
1724 }
1725 }
1726 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1727 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1728 spin_unlock_bh(&sc->rxbuflock);
1729
c6e387a2 1730 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1731 ath5k_mode_setup(sc); /* set filters, etc. */
1732 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1733
1734 return 0;
1735err:
1736 return ret;
1737}
1738
1739/*
1740 * Disable the receive h/w in preparation for a reset.
1741 */
1742static void
1743ath5k_rx_stop(struct ath5k_softc *sc)
1744{
1745 struct ath5k_hw *ah = sc->ah;
1746
c6e387a2 1747 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1748 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1749 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1750
1751 ath5k_debug_printrxbuffs(sc, ah);
fa1c114f
JS		 1752}
1753
1754static unsigned int
8a89f063
BR		 1755ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1756 struct ath5k_rx_status *rs)
fa1c114f 1757{
dc1e001b
LR		 1758 struct ath5k_hw *ah = sc->ah;
1759 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1760 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1761 unsigned int keyix, hlen;
fa1c114f 1762
b47f407b
BR		 1763 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1764 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1765 return RX_FLAG_DECRYPTED;
1766
1767 /* Apparently when a default key is used to decrypt the packet
1768 the hw does not set the index used to decrypt. In such cases
1769 get the index from the packet. */
798ee985 1770 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1771 if (ieee80211_has_protected(hdr->frame_control) &&
1772 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1773 skb->len >= hlen + 4) {
fa1c114f
JS		 1774 keyix = skb->data[hlen + 3] >> 6;
1775
dc1e001b 1776 if (test_bit(keyix, common->keymap))
fa1c114f
JS		 1777 return RX_FLAG_DECRYPTED;
1778 }
1779
1780 return 0;
1781}
1782
036cd1ec
BR		 1783
1784static void
6ba81c2c
BR		 1785ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1786 struct ieee80211_rx_status *rxs)
036cd1ec 1787{
954fecea 1788 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1789 u64 tsf, bc_tstamp;
036cd1ec
BR		 1790 u32 hw_tu;
1791 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1792
24b56e70 1793 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1794 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1795 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1796 /*
6ba81c2c
BR		 1797 * Received an IBSS beacon with the same BSSID. Hardware *must*
1798 * have updated the local TSF. We have to work around various
1799 * hardware bugs, though...
036cd1ec 1800 */
6ba81c2c
BR		 1801 tsf = ath5k_hw_get_tsf64(sc->ah);
1802 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1803 hw_tu = TSF_TO_TU(tsf);
1804
1805 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1806 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1807 (unsigned long long)bc_tstamp,
1808 (unsigned long long)rxs->mactime,
1809 (unsigned long long)(rxs->mactime - bc_tstamp),
1810 (unsigned long long)tsf);
6ba81c2c
BR		 1811
1812 /*
1813 * Sometimes the HW will give us a wrong tstamp in the rx
1814 * status, causing the timestamp extension to go wrong.
1815 * (This seems to happen especially with beacon frames bigger
1816 * than 78 byte (incl. FCS))
1817 * But we know that the receive timestamp must be later than the
1818 * timestamp of the beacon since HW must have synced to that.
1819 *
1820 * NOTE: here we assume mactime to be after the frame was
1821 * received, not like mac80211 which defines it at the start.
1822 */
1823 if (bc_tstamp > rxs->mactime) {
036cd1ec 1824 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1825 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1826 (unsigned long long)rxs->mactime,
1827 (unsigned long long)tsf);
6ba81c2c 1828 rxs->mactime = tsf;
036cd1ec 1829 }
6ba81c2c
BR		 1830
1831 /*
1832 * Local TSF might have moved higher than our beacon timers,
1833 * in that case we have to update them to continue sending
1834 * beacons. This also takes care of synchronizing beacon sending
1835 * times with other stations.
1836 */
1837 if (hw_tu >= sc->nexttbtt)
1838 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1839 }
1840}
1841
b4ea449d
BR		 1842static void
1843ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1844{
1845 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1846 struct ath5k_hw *ah = sc->ah;
1847 struct ath_common *common = ath5k_hw_common(ah);
1848
1849 /* only beacons from our BSSID */
1850 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1851 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1852 return;
1853
1854 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1855 rssi);
1856
1857 /* in IBSS mode we should keep RSSI statistics per neighbour */
1858 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1859}
1860
8127fbdc 1861/*
a180a130 1862 * Compute padding position. skb must contain an IEEE 802.11 frame
8127fbdc
BP		 1863 */
1864static int ath5k_common_padpos(struct sk_buff *skb)
1865{
1866 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1867 __le16 frame_control = hdr->frame_control;
1868 int padpos = 24;
1869
1870 if (ieee80211_has_a4(frame_control)) {
1871 padpos += ETH_ALEN;
1872 }
1873 if (ieee80211_is_data_qos(frame_control)) {
1874 padpos += IEEE80211_QOS_CTL_LEN;
1875 }
1876
1877 return padpos;
1878}
1879
1880/*
a180a130
BC		 1881 * This function expects an 802.11 frame and returns the number of
1882 * bytes added, or -1 if we don't have enough header room.
8127fbdc 1883 */
8127fbdc
BP		 1884static int ath5k_add_padding(struct sk_buff *skb)
1885{
1886 int padpos = ath5k_common_padpos(skb);
1887 int padsize = padpos & 3;
1888
1889 if (padsize && skb->len>padpos) {
1890
1891 if (skb_headroom(skb) < padsize)
1892 return -1;
1893
1894 skb_push(skb, padsize);
1895 memmove(skb->data, skb->data+padsize, padpos);
1896 return padsize;
1897 }
1898
1899 return 0;
1900}
1901
1902/*
a180a130
BC		 1903 * The MAC header is padded to have 32-bit boundary if the
1904 * packet payload is non-zero. The general calculation for
1905 * padsize would take into account odd header lengths:
1906 * padsize = 4 - (hdrlen & 3); however, since only
1907 * even-length headers are used, padding can only be 0 or 2
1908 * bytes and we can optimize this a bit. We must not try to
1909 * remove padding from short control frames that do not have a
1910 * payload.
1911 *
1912 * This function expects an 802.11 frame and returns the number of
1913 * bytes removed.
8127fbdc 1914 */
8127fbdc
BP		 1915static int ath5k_remove_padding(struct sk_buff *skb)
1916{
1917 int padpos = ath5k_common_padpos(skb);
1918 int padsize = padpos & 3;
1919
1920 if (padsize && skb->len>=padpos+padsize) {
1921 memmove(skb->data + padsize, skb->data, padpos);
1922 skb_pull(skb, padsize);
1923 return padsize;
1924 }
1925
1926 return 0;
1927}
1928
fa1c114f 1929static void
8a89f063
BR		 1930ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1931 struct ath5k_rx_status *rs)
fa1c114f 1932{
1c5256bb 1933 struct ieee80211_rx_status *rxs;
8a89f063 1934
8a89f063
BR		 1935 ath5k_remove_padding(skb);
1936
1937 rxs = IEEE80211_SKB_RXCB(skb);
1938
1939 rxs->flag = 0;
1940 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1941 rxs->flag |= RX_FLAG_MMIC_ERROR;
1942
1943 /*
1944 * always extend the mac timestamp, since this information is
1945 * also needed for proper IBSS merging.
1946 *
1947 * XXX: it might be too late to do it here, since rs_tstamp is
1948 * 15bit only. that means TSF extension has to be done within
1949 * 32768usec (about 32ms). it might be necessary to move this to
1950 * the interrupt handler, like it is done in madwifi.
1951 *
1952 * Unfortunately we don't know when the hardware takes the rx
1953 * timestamp (beginning of phy frame, data frame, end of rx?).
1954 * The only thing we know is that it is hardware specific...
1955 * On AR5213 it seems the rx timestamp is at the end of the
1956 * frame, but i'm not sure.
1957 *
1958 * NOTE: mac80211 defines mactime at the beginning of the first
1959 * data symbol. Since we don't have any time references it's
1960 * impossible to comply to that. This affects IBSS merge only
1961 * right now, so it's not too bad...
1962 */
1963 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1964 rxs->flag |= RX_FLAG_TSFT;
1965
1966 rxs->freq = sc->curchan->center_freq;
1967 rxs->band = sc->curband->band;
1968
1969 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
1970
1971 rxs->antenna = rs->rs_antenna;
1972
1973 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1974 sc->stats.antenna_rx[rs->rs_antenna]++;
1975 else
1976 sc->stats.antenna_rx[0]++; /* invalid */
1977
1978 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1979 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
1980
1981 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1982 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1983 rxs->flag |= RX_FLAG_SHORTPRE;
1984
1985 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1986
1987 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
1988
1989 /* check beacons in IBSS mode */
1990 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1991 ath5k_check_ibss_tsf(sc, skb, rxs);
1992
1993 ieee80211_rx(sc->hw, skb);
1994}
1995
02a78b42
BR		 1996/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1997 *
1998 * Check if we want to further process this frame or not. Also update
1999 * statistics. Return true if we want this frame, false if not.
2000 */
2001static bool
2002ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
2003{
2004 sc->stats.rx_all_count++;
2005
2006 if (unlikely(rs->rs_status)) {
2007 if (rs->rs_status & AR5K_RXERR_CRC)
2008 sc->stats.rxerr_crc++;
2009 if (rs->rs_status & AR5K_RXERR_FIFO)
2010 sc->stats.rxerr_fifo++;
2011 if (rs->rs_status & AR5K_RXERR_PHY) {
2012 sc->stats.rxerr_phy++;
2013 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
2014 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
2015 return false;
2016 }
2017 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
2018 /*
2019 * Decrypt error. If the error occurred
2020 * because there was no hardware key, then
2021 * let the frame through so the upper layers
2022 * can process it. This is necessary for 5210
2023 * parts which have no way to setup a ``clear''
2024 * key cache entry.
2025 *
2026 * XXX do key cache faulting
2027 */
2028 sc->stats.rxerr_decrypt++;
2029 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
2030 !(rs->rs_status & AR5K_RXERR_CRC))
2031 return true;
2032 }
2033 if (rs->rs_status & AR5K_RXERR_MIC) {
2034 sc->stats.rxerr_mic++;
2035 return true;
2036 }
2037
23538c26
BC		 2038 /* reject any frames with non-crypto errors */
2039 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
02a78b42
BR		 2040 return false;
2041 }
2042
2043 if (unlikely(rs->rs_more)) {
2044 sc->stats.rxerr_jumbo++;
2045 return false;
2046 }
2047 return true;
2048}
2049
8a89f063
BR		 2050static void
2051ath5k_tasklet_rx(unsigned long data)
2052{
b47f407b 2053 struct ath5k_rx_status rs = {};
b6ea0356
BC		 2054 struct sk_buff *skb, *next_skb;
2055 dma_addr_t next_skb_addr;
fa1c114f 2056 struct ath5k_softc *sc = (void *)data;
cc861f74
LR		 2057 struct ath5k_hw *ah = sc->ah;
2058 struct ath_common *common = ath5k_hw_common(ah);
c57ca815 2059 struct ath5k_buf *bf;
fa1c114f 2060 struct ath5k_desc *ds;
fa1c114f 2061 int ret;
fa1c114f
JS		 2062
2063 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 2064 if (list_empty(&sc->rxbuf)) {
2065 ATH5K_WARN(sc, "empty rx buf pool\n");
2066 goto unlock;
2067 }
fa1c114f 2068 do {
fa1c114f
JS		 2069 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
2070 BUG_ON(bf->skb == NULL);
2071 skb = bf->skb;
2072 ds = bf->desc;
2073
c57ca815
BC		 2074 /* bail if HW is still using self-linked descriptor */
2075 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
2076 break;
fa1c114f 2077
b47f407b 2078 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 2079 if (unlikely(ret == -EINPROGRESS))
2080 break;
2081 else if (unlikely(ret)) {
2082 ATH5K_ERR(sc, "error in processing rx descriptor\n");
7644395f 2083 sc->stats.rxerr_proc++;
b16062fa 2084 break;
fa1c114f
JS		 2085 }
2086
02a78b42
BR		 2087 if (ath5k_receive_frame_ok(sc, &rs)) {
2088 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 2089
02a78b42
BR		 2090 /*
2091 * If we can't replace bf->skb with a new skb under
2092 * memory pressure, just skip this packet
2093 */
2094 if (!next_skb)
fa1c114f 2095 goto next;
b6ea0356 2096
02a78b42
BR		 2097 pci_unmap_single(sc->pdev, bf->skbaddr,
2098 common->rx_bufsize,
2099 PCI_DMA_FROMDEVICE);
b6ea0356 2100
02a78b42 2101 skb_put(skb, rs.rs_datalen);
fa1c114f 2102
02a78b42 2103 ath5k_receive_frame(sc, skb, &rs);
b6ea0356 2104
02a78b42
BR		 2105 bf->skb = next_skb;
2106 bf->skbaddr = next_skb_addr;
2107 }
fa1c114f
JS		 2108next:
2109 list_move_tail(&bf->list, &sc->rxbuf);
2110 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 2111unlock:
fa1c114f
JS		 2112 spin_unlock(&sc->rxbuflock);
2113}
2114
2115
fa1c114f
JS		 2116/*************\
2117* TX Handling *
2118\*************/
2119
2120static void
2121ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2122{
b47f407b 2123 struct ath5k_tx_status ts = {};
fa1c114f
JS		 2124 struct ath5k_buf *bf, *bf0;
2125 struct ath5k_desc *ds;
2126 struct sk_buff *skb;
e039fa4a 2127 struct ieee80211_tx_info *info;
2f7fe870 2128 int i, ret;
fa1c114f
JS		 2129
2130 spin_lock(&txq->lock);
2131 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2132 ds = bf->desc;
2133
a05988bb
BC		 2134 /*
2135 * It's possible that the hardware can say the buffer is
2136 * completed when it hasn't yet loaded the ds_link from
2137 * host memory and moved on. If there are more TX
2138 * descriptors in the queue, wait for TXDP to change
2139 * before processing this one.
2140 */
2141 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2142 !list_is_last(&bf->list, &txq->q))
2143 break;
2144
b47f407b 2145 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 2146 if (unlikely(ret == -EINPROGRESS))
2147 break;
2148 else if (unlikely(ret)) {
2149 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2150 ret, txq->qnum);
2151 break;
2152 }
2153
7644395f 2154 sc->stats.tx_all_count++;
fa1c114f 2155 skb = bf->skb;
a888d52d 2156 info = IEEE80211_SKB_CB(skb);
fa1c114f 2157 bf->skb = NULL;
e039fa4a 2158
fa1c114f
JS		 2159 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2160 PCI_DMA_TODEVICE);
2161
e6a9854b 2162 ieee80211_tx_info_clear_status(info);
2f7fe870 2163 for (i = 0; i < 4; i++) {
e6a9854b
JB		 2164 struct ieee80211_tx_rate *r =
2165 &info->status.rates[i];
2f7fe870
FF		 2166
2167 if (ts.ts_rate[i]) {
e6a9854b
JB		 2168 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2169 r->count = ts.ts_retry[i];
2f7fe870 2170 } else {
e6a9854b
JB		 2171 r->idx = -1;
2172 r->count = 0;
2f7fe870
FF		 2173 }
2174 }
2175
e6a9854b
JB		 2176 /* count the successful attempt as well */
2177 info->status.rates[ts.ts_final_idx].count++;
2178
b47f407b 2179 if (unlikely(ts.ts_status)) {
495391d7 2180 sc->stats.ack_fail++;
7644395f 2181 if (ts.ts_status & AR5K_TXERR_FILT) {
e039fa4a 2182 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
7644395f
BR		 2183 sc->stats.txerr_filt++;
2184 }
2185 if (ts.ts_status & AR5K_TXERR_XRETRY)
2186 sc->stats.txerr_retry++;
2187 if (ts.ts_status & AR5K_TXERR_FIFO)
2188 sc->stats.txerr_fifo++;
fa1c114f 2189 } else {
e039fa4a
JB		 2190 info->flags |= IEEE80211_TX_STAT_ACK;
2191 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2192 }
2193
8127fbdc
BP		 2194 /*
2195 * Remove MAC header padding before giving the frame
2196 * back to mac80211.
2197 */
2198 ath5k_remove_padding(skb);
2199
604eeadd
BR		 2200 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2201 sc->stats.antenna_tx[ts.ts_antenna]++;
2202 else
2203 sc->stats.antenna_tx[0]++; /* invalid */
2204
e039fa4a 2205 ieee80211_tx_status(sc->hw, skb);
fa1c114f
JS		 2206
2207 spin_lock(&sc->txbuflock);
fa1c114f
JS		 2208 list_move_tail(&bf->list, &sc->txbuf);
2209 sc->txbuf_len++;
2210 spin_unlock(&sc->txbuflock);
2211 }
2212 if (likely(list_empty(&txq->q)))
2213 txq->link = NULL;
2214 spin_unlock(&txq->lock);
2215 if (sc->txbuf_len > ATH_TXBUF / 5)
2216 ieee80211_wake_queues(sc->hw);
2217}
2218
2219static void
2220ath5k_tasklet_tx(unsigned long data)
2221{
8784d2ee 2222 int i;
fa1c114f
JS		 2223 struct ath5k_softc *sc = (void *)data;
2224
8784d2ee
BC		 2225 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2226 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2227 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2228}
2229
2230
fa1c114f
JS		 2231/*****************\
2232* Beacon handling *
2233\*****************/
2234
2235/*
2236 * Setup the beacon frame for transmit.
2237 */
2238static int
e039fa4a 2239ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2240{
2241 struct sk_buff *skb = bf->skb;
a888d52d 2242 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2243 struct ath5k_hw *ah = sc->ah;
2244 struct ath5k_desc *ds;
2bed03eb
NK		 2245 int ret = 0;
2246 u8 antenna;
fa1c114f 2247 u32 flags;
8127fbdc 2248 const int padsize = 0;
fa1c114f
JS		 2249
2250 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2251 PCI_DMA_TODEVICE);
2252 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2253 "skbaddr %llx\n", skb, skb->data, skb->len,
2254 (unsigned long long)bf->skbaddr);
8d8bb39b 2255 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2256 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2257 return -EIO;
2258 }
2259
2260 ds = bf->desc;
2bed03eb 2261 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2262
2263 flags = AR5K_TXDESC_NOACK;
05c914fe 2264 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2265 ds->ds_link = bf->daddr; /* self-linked */
2266 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2267 } else
fa1c114f 2268 ds->ds_link = 0;
2bed03eb
NK		 2269
2270 /*
2271 * If we use multiple antennas on AP and use
2272 * the Sectored AP scenario, switch antenna every
2273 * 4 beacons to make sure everybody hears our AP.
2274 * When a client tries to associate, hw will keep
2275 * track of the tx antenna to be used for this client
2276 * automaticaly, based on ACKed packets.
2277 *
2278 * Note: AP still listens and transmits RTS on the
2279 * default antenna which is supposed to be an omni.
2280 *
2281 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 2282 * multiple antennas (1 omni -- the default -- and 14
2283 * sectors), so if we choose to actually support this
2284 * mode, we need to allow the user to set how many antennas
2285 * we have and tweak the code below to send beacons
2286 * on all of them.
2bed03eb
NK		 2287 */
2288 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2289 antenna = sc->bsent & 4 ? 2 : 1;
2290
fa1c114f 2291
8f655dde
NK		 2292 /* FIXME: If we are in g mode and rate is a CCK rate
2293 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2294 * from tx power (value is in dB units already) */
fa1c114f 2295 ds->ds_data = bf->skbaddr;
281c56dd 2296 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 2297 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 2298 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2299 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2300 1, AR5K_TXKEYIX_INVALID,
400ec45a 2301 antenna, flags, 0, 0);
fa1c114f
JS		 2302 if (ret)
2303 goto err_unmap;
2304
2305 return 0;
2306err_unmap:
2307 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2308 return ret;
2309}
2310
2311/*
2312 * Transmit a beacon frame at SWBA. Dynamic updates to the
2313 * frame contents are done as needed and the slot time is
2314 * also adjusted based on current state.
2315 *
5faaff74
BC		 2316 * This is called from software irq context (beacontq tasklets)
2317 * or user context from ath5k_beacon_config.
fa1c114f
JS		 2318 */
2319static void
2320ath5k_beacon_send(struct ath5k_softc *sc)
2321{
2322 struct ath5k_buf *bf = sc->bbuf;
2323 struct ath5k_hw *ah = sc->ah;
cec8db23 2324 struct sk_buff *skb;
fa1c114f 2325
be9b7259 2326 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2327
4afd89d9 2328 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION)) {
fa1c114f
JS		 2329 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2330 return;
2331 }
2332 /*
2333 * Check if the previous beacon has gone out. If
a180a130 2334 * not, don't don't try to post another: skip this
fa1c114f
JS		 2335 * period and wait for the next. Missed beacons
2336 * indicate a problem and should not occur. If we
2337 * miss too many consecutive beacons reset the device.
2338 */
2339 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2340 sc->bmisscount++;
be9b7259 2341 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2342 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2343 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2344 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2345 "stuck beacon time (%u missed)\n",
2346 sc->bmisscount);
8d67a031
BR		 2347 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2348 "stuck beacon, resetting\n");
5faaff74 2349 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2350 }
2351 return;
2352 }
2353 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2354 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2355 "resume beacon xmit after %u misses\n",
2356 sc->bmisscount);
2357 sc->bmisscount = 0;
2358 }
2359
2360 /*
2361 * Stop any current dma and put the new frame on the queue.
2362 * This should never fail since we check above that no frames
2363 * are still pending on the queue.
2364 */
2365 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2366 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2367 /* NB: hw still stops DMA, so proceed */
2368 }
fa1c114f 2369
1071db86
BC		 2370 /* refresh the beacon for AP mode */
2371 if (sc->opmode == NL80211_IFTYPE_AP)
2372 ath5k_beacon_update(sc->hw, sc->vif);
2373
c6e387a2
NK		 2374 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2375 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2376 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2377 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2378
cec8db23
BC		 2379 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2380 while (skb) {
2381 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2382 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2383 }
2384
fa1c114f
JS		 2385 sc->bsent++;
2386}
2387
2388
9804b98d
BR		 2389/**
2390 * ath5k_beacon_update_timers - update beacon timers
2391 *
2392 * @sc: struct ath5k_softc pointer we are operating on
2393 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2394 * beacon timer update based on the current HW TSF.
2395 *
2396 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2397 * of a received beacon or the current local hardware TSF and write it to the
2398 * beacon timer registers.
2399 *
2400 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2401 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2402 * when we otherwise know we have to update the timers, but we keep it in this
2403 * function to have it all together in one place.
2404 */
fa1c114f 2405static void
9804b98d 2406ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2407{
2408 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2409 u32 nexttbtt, intval, hw_tu, bc_tu;
2410 u64 hw_tsf;
fa1c114f
JS		 2411
2412 intval = sc->bintval & AR5K_BEACON_PERIOD;
2413 if (WARN_ON(!intval))
2414 return;
2415
9804b98d
BR		 2416 /* beacon TSF converted to TU */
2417 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2418
9804b98d
BR		 2419 /* current TSF converted to TU */
2420 hw_tsf = ath5k_hw_get_tsf64(ah);
2421 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2422
9804b98d
BR		 2423#define FUDGE 3
2424 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2425 if (bc_tsf == -1) {
2426 /*
2427 * no beacons received, called internally.
2428 * just need to refresh timers based on HW TSF.
2429 */
2430 nexttbtt = roundup(hw_tu + FUDGE, intval);
2431 } else if (bc_tsf == 0) {
2432 /*
2433 * no beacon received, probably called by ath5k_reset_tsf().
2434 * reset TSF to start with 0.
2435 */
2436 nexttbtt = intval;
2437 intval |= AR5K_BEACON_RESET_TSF;
2438 } else if (bc_tsf > hw_tsf) {
2439 /*
2440 * beacon received, SW merge happend but HW TSF not yet updated.
2441 * not possible to reconfigure timers yet, but next time we
2442 * receive a beacon with the same BSSID, the hardware will
2443 * automatically update the TSF and then we need to reconfigure
2444 * the timers.
2445 */
2446 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2447 "need to wait for HW TSF sync\n");
2448 return;
2449 } else {
2450 /*
2451 * most important case for beacon synchronization between STA.
2452 *
2453 * beacon received and HW TSF has been already updated by HW.
2454 * update next TBTT based on the TSF of the beacon, but make
2455 * sure it is ahead of our local TSF timer.
2456 */
2457 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2458 }
2459#undef FUDGE
fa1c114f 2460
036cd1ec
BR		 2461 sc->nexttbtt = nexttbtt;
2462
fa1c114f 2463 intval |= AR5K_BEACON_ENA;
fa1c114f 2464 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2465
2466 /*
2467 * debugging output last in order to preserve the time critical aspect
2468 * of this function
2469 */
2470 if (bc_tsf == -1)
2471 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2472 "reconfigured timers based on HW TSF\n");
2473 else if (bc_tsf == 0)
2474 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2475 "reset HW TSF and timers\n");
2476 else
2477 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2478 "updated timers based on beacon TSF\n");
2479
2480 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2481 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2482 (unsigned long long) bc_tsf,
2483 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2484 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2485 intval & AR5K_BEACON_PERIOD,
2486 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2487 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2488}
2489
2490
036cd1ec
BR		 2491/**
2492 * ath5k_beacon_config - Configure the beacon queues and interrupts
2493 *
2494 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2495 *
036cd1ec 2496 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2497 * interrupts to detect TSF updates only.
fa1c114f
JS		 2498 */
2499static void
2500ath5k_beacon_config(struct ath5k_softc *sc)
2501{
2502 struct ath5k_hw *ah = sc->ah;
b5f03956 2503 unsigned long flags;
fa1c114f 2504
21800491 2505 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2506 sc->bmisscount = 0;
dc1968e7 2507 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2508
21800491 2509 if (sc->enable_beacon) {
fa1c114f 2510 /*
036cd1ec
BR		 2511 * In IBSS mode we use a self-linked tx descriptor and let the
2512 * hardware send the beacons automatically. We have to load it
fa1c114f 2513 * only once here.
036cd1ec 2514 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2515 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2516 */
2517 ath5k_beaconq_config(sc);
fa1c114f 2518
036cd1ec
BR		 2519 sc->imask |= AR5K_INT_SWBA;
2520
da966bca 2521 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2522 if (ath5k_hw_hasveol(ah))
da966bca 2523 ath5k_beacon_send(sc);
da966bca
JS		 2524 } else
2525 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2526 } else {
2527 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2528 }
fa1c114f 2529
c6e387a2 2530 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2531 mmiowb();
2532 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2533}
2534
428cbd4f
NK		 2535static void ath5k_tasklet_beacon(unsigned long data)
2536{
2537 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2538
2539 /*
2540 * Software beacon alert--time to send a beacon.
2541 *
2542 * In IBSS mode we use this interrupt just to
2543 * keep track of the next TBTT (target beacon
2544 * transmission time) in order to detect wether
2545 * automatic TSF updates happened.
2546 */
2547 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2548 /* XXX: only if VEOL suppported */
2549 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2550 sc->nexttbtt += sc->bintval;
2551 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2552 "SWBA nexttbtt: %x hw_tu: %x "
2553 "TSF: %llx\n",
2554 sc->nexttbtt,
2555 TSF_TO_TU(tsf),
2556 (unsigned long long) tsf);
2557 } else {
2558 spin_lock(&sc->block);
2559 ath5k_beacon_send(sc);
2560 spin_unlock(&sc->block);
2561 }
2562}
2563
fa1c114f
JS		 2564
2565/********************\
2566* Interrupt handling *
2567\********************/
2568
2569static int
bb2becac 2570ath5k_init(struct ath5k_softc *sc)
fa1c114f 2571{
bc1b32d6 2572 struct ath5k_hw *ah = sc->ah;
e0f8c2a9 2573 struct ath_common *common = ath5k_hw_common(ah);
bc1b32d6 2574 int ret, i;
fa1c114f
JS		 2575
2576 mutex_lock(&sc->lock);
2577
2578 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2579
2580 /*
2581 * Stop anything previously setup. This is safe
2582 * no matter this is the first time through or not.
2583 */
2584 ath5k_stop_locked(sc);
2585
2586 /*
2587 * The basic interface to setting the hardware in a good
2588 * state is ``reset''. On return the hardware is known to
2589 * be powered up and with interrupts disabled. This must
2590 * be followed by initialization of the appropriate bits
2591 * and then setup of the interrupt mask.
2592 */
d8ee398d
LR		 2593 sc->curchan = sc->hw->conf.channel;
2594 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2595 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2596 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2111ac0d
BR		 2597 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2598
209d889b 2599 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2600 if (ret)
2601 goto done;
fa1c114f 2602
e6a3b616
TD		 2603 ath5k_rfkill_hw_start(ah);
2604
bc1b32d6
EO		 2605 /*
2606 * Reset the key cache since some parts do not reset the
2607 * contents on initial power up or resume from suspend.
2608 */
e0f8c2a9
BR		 2609 for (i = 0; i < common->keymax; i++)
2610 ath_hw_keyreset(common, (u16)i);
bc1b32d6 2611
0edc9a67 2612 ath5k_hw_set_ack_bitrate_high(ah, true);
fa1c114f
JS		 2613 ret = 0;
2614done:
274c7c36 2615 mmiowb();
fa1c114f
JS		 2616 mutex_unlock(&sc->lock);
2617 return ret;
2618}
2619
2620static int
2621ath5k_stop_locked(struct ath5k_softc *sc)
2622{
2623 struct ath5k_hw *ah = sc->ah;
2624
2625 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2626 test_bit(ATH_STAT_INVALID, sc->status));
2627
2628 /*
2629 * Shutdown the hardware and driver:
2630 * stop output from above
2631 * disable interrupts
2632 * turn off timers
2633 * turn off the radio
2634 * clear transmit machinery
2635 * clear receive machinery
2636 * drain and release tx queues
2637 * reclaim beacon resources
2638 * power down hardware
2639 *
2640 * Note that some of this work is not possible if the
2641 * hardware is gone (invalid).
2642 */
2643 ieee80211_stop_queues(sc->hw);
2644
2645 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2646 ath5k_led_off(sc);
c6e387a2 2647 ath5k_hw_set_imr(ah, 0);
274c7c36 2648 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2649 }
2650 ath5k_txq_cleanup(sc);
2651 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2652 ath5k_rx_stop(sc);
2653 ath5k_hw_phy_disable(ah);
b3f194e5 2654 }
fa1c114f
JS		 2655
2656 return 0;
2657}
2658
450464de
BC		 2659static void stop_tasklets(struct ath5k_softc *sc)
2660{
2661 tasklet_kill(&sc->rxtq);
2662 tasklet_kill(&sc->txtq);
2663 tasklet_kill(&sc->calib);
2664 tasklet_kill(&sc->beacontq);
2665 tasklet_kill(&sc->ani_tasklet);
2666}
2667
fa1c114f
JS		 2668/*
2669 * Stop the device, grabbing the top-level lock to protect
2670 * against concurrent entry through ath5k_init (which can happen
2671 * if another thread does a system call and the thread doing the
2672 * stop is preempted).
2673 */
2674static int
bb2becac 2675ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2676{
2677 int ret;
2678
2679 mutex_lock(&sc->lock);
2680 ret = ath5k_stop_locked(sc);
2681 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2682 /*
edd7fc70
NK		 2683 * Don't set the card in full sleep mode!
2684 *
2685 * a) When the device is in this state it must be carefully
2686 * woken up or references to registers in the PCI clock
2687 * domain may freeze the bus (and system). This varies
2688 * by chip and is mostly an issue with newer parts
2689 * (madwifi sources mentioned srev >= 0x78) that go to
2690 * sleep more quickly.
2691 *
2692 * b) On older chips full sleep results a weird behaviour
2693 * during wakeup. I tested various cards with srev < 0x78
2694 * and they don't wake up after module reload, a second
2695 * module reload is needed to bring the card up again.
2696 *
2697 * Until we figure out what's going on don't enable
2698 * full chip reset on any chip (this is what Legacy HAL
2699 * and Sam's HAL do anyway). Instead Perform a full reset
2700 * on the device (same as initial state after attach) and
2701 * leave it idle (keep MAC/BB on warm reset) */
2702 ret = ath5k_hw_on_hold(sc->ah);
2703
2704 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2705 "putting device to sleep\n");
fa1c114f 2706 }
9e4e43f2 2707 ath5k_txbuf_free_skb(sc, sc->bbuf);
8bdd5b9c 2708
274c7c36 2709 mmiowb();
fa1c114f
JS		 2710 mutex_unlock(&sc->lock);
2711
450464de 2712 stop_tasklets(sc);
fa1c114f 2713
e6a3b616
TD		 2714 ath5k_rfkill_hw_stop(sc->ah);
2715
fa1c114f
JS		 2716 return ret;
2717}
2718
6a8a3f6b
BR		 2719static void
2720ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2721{
2111ac0d
BR		 2722 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2723 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2724 /* run ANI only when full calibration is not active */
2725 ah->ah_cal_next_ani = jiffies +
2726 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2727 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2728
2729 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2730 ah->ah_cal_next_full = jiffies +
2731 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2732 tasklet_schedule(&ah->ah_sc->calib);
2733 }
2734 /* we could use SWI to generate enough interrupts to meet our
2735 * calibration interval requirements, if necessary:
2736 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2737}
2738
fa1c114f
JS		 2739static irqreturn_t
2740ath5k_intr(int irq, void *dev_id)
2741{
2742 struct ath5k_softc *sc = dev_id;
2743 struct ath5k_hw *ah = sc->ah;
2744 enum ath5k_int status;
2745 unsigned int counter = 1000;
2746
2747 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2748 !ath5k_hw_is_intr_pending(ah)))
2749 return IRQ_NONE;
2750
2751 do {
fa1c114f
JS		 2752 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2753 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2754 status, sc->imask);
fa1c114f
JS		 2755 if (unlikely(status & AR5K_INT_FATAL)) {
2756 /*
2757 * Fatal errors are unrecoverable.
2758 * Typically these are caused by DMA errors.
2759 */
8d67a031
BR		 2760 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2761 "fatal int, resetting\n");
5faaff74 2762 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2763 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2764 /*
2765 * Receive buffers are full. Either the bus is busy or
2766 * the CPU is not fast enough to process all received
2767 * frames.
2768 * Older chipsets need a reset to come out of this
2769 * condition, but we treat it as RX for newer chips.
2770 * We don't know exactly which versions need a reset -
2771 * this guess is copied from the HAL.
2772 */
2773 sc->stats.rxorn_intr++;
8d67a031
BR		 2774 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2775 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2776 "rx overrun, resetting\n");
5faaff74 2777 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2778 }
87d77c4e
BR		 2779 else
2780 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2781 } else {
2782 if (status & AR5K_INT_SWBA) {
56d2ac76 2783 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2784 }
2785 if (status & AR5K_INT_RXEOL) {
2786 /*
2787 * NB: the hardware should re-read the link when
2788 * RXE bit is written, but it doesn't work at
2789 * least on older hardware revs.
2790 */
b3f194e5 2791 sc->stats.rxeol_intr++;
fa1c114f
JS		 2792 }
2793 if (status & AR5K_INT_TXURN) {
2794 /* bump tx trigger level */
2795 ath5k_hw_update_tx_triglevel(ah, true);
2796 }
4c674c60 2797 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2798 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2799 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2800 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2801 tasklet_schedule(&sc->txtq);
2802 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2803 /* TODO */
fa1c114f
JS		 2804 }
2805 if (status & AR5K_INT_MIB) {
2111ac0d 2806 sc->stats.mib_intr++;
495391d7 2807 ath5k_hw_update_mib_counters(ah);
2111ac0d 2808 ath5k_ani_mib_intr(ah);
fa1c114f 2809 }
e6a3b616 2810 if (status & AR5K_INT_GPIO)
e6a3b616 2811 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2812
fa1c114f 2813 }
2516baa6 2814 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2815
2816 if (unlikely(!counter))
2817 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2818
6a8a3f6b 2819 ath5k_intr_calibration_poll(ah);
6e220662 2820
fa1c114f
JS		 2821 return IRQ_HANDLED;
2822}
2823
fa1c114f
JS		 2824/*
2825 * Periodically recalibrate the PHY to account
2826 * for temperature/environment changes.
2827 */
2828static void
6e220662 2829ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2830{
2831 struct ath5k_softc *sc = (void *)data;
2832 struct ath5k_hw *ah = sc->ah;
2833
6e220662 2834 /* Only full calibration for now */
e65e1d77 2835 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2836
fa1c114f 2837 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2838 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2839 sc->curchan->hw_value);
fa1c114f 2840
6f3b414a 2841 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2842 /*
2843 * Rfgain is out of bounds, reset the chip
2844 * to load new gain values.
2845 */
2846 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2847 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2848 }
2849 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2850 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2851 ieee80211_frequency_to_channel(
2852 sc->curchan->center_freq));
fa1c114f 2853
0e8e02dd 2854 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
afe86286
BR		 2855 * doesn't. We stop the queues so that calibration doesn't interfere
2856 * with TX and don't run it as often */
2857 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2858 ah->ah_cal_next_nf = jiffies +
2859 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2860 ieee80211_stop_queues(sc->hw);
2861 ath5k_hw_update_noise_floor(ah);
2862 ieee80211_wake_queues(sc->hw);
2863 }
6e220662 2864
e65e1d77 2865 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2866}
2867
2868
2111ac0d
BR		 2869static void
2870ath5k_tasklet_ani(unsigned long data)
2871{
2872 struct ath5k_softc *sc = (void *)data;
2873 struct ath5k_hw *ah = sc->ah;
2874
2875 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2876 ath5k_ani_calibration(ah);
2877 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2878}
2879
2880
fa1c114f
JS		 2881/********************\
2882* Mac80211 functions *
2883\********************/
2884
2885static int
e039fa4a 2886ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2887{
2888 struct ath5k_softc *sc = hw->priv;
2889
2890 return ath5k_tx_queue(hw, skb, sc->txq);
2891}
2892
2893static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2894 struct ath5k_txq *txq)
fa1c114f
JS		 2895{
2896 struct ath5k_softc *sc = hw->priv;
2897 struct ath5k_buf *bf;
2898 unsigned long flags;
0fe45b1d 2899 int padsize;
fa1c114f
JS		 2900
2901 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2902
fa1c114f 2903 /*
a180a130
BC		 2904 * The hardware expects the header padded to 4 byte boundaries.
2905 * If this is not the case, we add the padding after the header.
fa1c114f 2906 */
8127fbdc
BP		 2907 padsize = ath5k_add_padding(skb);
2908 if (padsize < 0) {
2909 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2910 " headroom to pad");
2911 goto drop_packet;
fa1c114f
JS		 2912 }
2913
fa1c114f
JS		 2914 spin_lock_irqsave(&sc->txbuflock, flags);
2915 if (list_empty(&sc->txbuf)) {
2916 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2917 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2918 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2919 goto drop_packet;
fa1c114f
JS		 2920 }
2921 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2922 list_del(&bf->list);
2923 sc->txbuf_len--;
2924 if (list_empty(&sc->txbuf))
2925 ieee80211_stop_queues(hw);
2926 spin_unlock_irqrestore(&sc->txbuflock, flags);
2927
2928 bf->skb = skb;
2929
8127fbdc 2930 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
fa1c114f
JS		 2931 bf->skb = NULL;
2932 spin_lock_irqsave(&sc->txbuflock, flags);
2933 list_add_tail(&bf->list, &sc->txbuf);
2934 sc->txbuf_len++;
2935 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2936 goto drop_packet;
fa1c114f 2937 }
5a0fe8ac 2938 return NETDEV_TX_OK;
fa1c114f 2939
5a0fe8ac
BC		 2940drop_packet:
2941 dev_kfree_skb_any(skb);
71ef99c8 2942 return NETDEV_TX_OK;
fa1c114f
JS		 2943}
2944
209d889b
BC		 2945/*
2946 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2947 * and change to the given channel.
5faaff74
BC		 2948 *
2949 * This should be called with sc->lock.
209d889b 2950 */
fa1c114f 2951static int
209d889b 2952ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2953{
fa1c114f
JS		 2954 struct ath5k_hw *ah = sc->ah;
2955 int ret;
2956
2957 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2958
450464de
BC		 2959 ath5k_hw_set_imr(ah, 0);
2960 synchronize_irq(sc->pdev->irq);
2961 stop_tasklets(sc);
2962
209d889b 2963 if (chan) {
d7dc1003
JS		 2964 ath5k_txq_cleanup(sc);
2965 ath5k_rx_stop(sc);
209d889b
BC		 2966
2967 sc->curchan = chan;
2968 sc->curband = &sc->sbands[chan->band];
d7dc1003 2969 }
3355443a 2970 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2971 if (ret) {
fa1c114f
JS		 2972 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2973 goto err;
2974 }
d7dc1003 2975
fa1c114f 2976 ret = ath5k_rx_start(sc);
d7dc1003 2977 if (ret) {
fa1c114f
JS		 2978 ATH5K_ERR(sc, "can't start recv logic\n");
2979 goto err;
2980 }
d7dc1003 2981
2111ac0d
BR		 2982 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2983
ac559526
BR		 2984 ah->ah_cal_next_full = jiffies;
2985 ah->ah_cal_next_ani = jiffies;
afe86286
BR		 2986 ah->ah_cal_next_nf = jiffies;
2987
fa1c114f 2988 /*
d7dc1003
JS		 2989 * Change channels and update the h/w rate map if we're switching;
2990 * e.g. 11a to 11b/g.
2991 *
2992 * We may be doing a reset in response to an ioctl that changes the
2993 * channel so update any state that might change as a result.
fa1c114f
JS		 2994 *
2995 * XXX needed?
2996 */
2997/* ath5k_chan_change(sc, c); */
fa1c114f 2998
d7dc1003
JS		 2999 ath5k_beacon_config(sc);
3000 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 3001
397f385b
BR		 3002 ieee80211_wake_queues(sc->hw);
3003
fa1c114f
JS		 3004 return 0;
3005err:
3006 return ret;
3007}
3008
5faaff74
BC		 3009static void ath5k_reset_work(struct work_struct *work)
3010{
3011 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
3012 reset_work);
3013
3014 mutex_lock(&sc->lock);
3015 ath5k_reset(sc, sc->curchan);
3016 mutex_unlock(&sc->lock);
3017}
3018
fa1c114f
JS		 3019static int ath5k_start(struct ieee80211_hw *hw)
3020{
bb2becac 3021 return ath5k_init(hw->priv);
fa1c114f
JS		 3022}
3023
3024static void ath5k_stop(struct ieee80211_hw *hw)
3025{
bb2becac 3026 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 3027}
3028
3029static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 3030 struct ieee80211_vif *vif)
fa1c114f
JS		 3031{
3032 struct ath5k_softc *sc = hw->priv;
3033 int ret;
3034
3035 mutex_lock(&sc->lock);
32bfd35d 3036 if (sc->vif) {
fa1c114f
JS		 3037 ret = 0;
3038 goto end;
3039 }
3040
1ed32e4f 3041 sc->vif = vif;
fa1c114f 3042
1ed32e4f 3043 switch (vif->type) {
da966bca 3044 case NL80211_IFTYPE_AP:
05c914fe
JB		 3045 case NL80211_IFTYPE_STATION:
3046 case NL80211_IFTYPE_ADHOC:
b706e65b 3047 case NL80211_IFTYPE_MESH_POINT:
1ed32e4f 3048 sc->opmode = vif->type;
fa1c114f
JS		 3049 break;
3050 default:
3051 ret = -EOPNOTSUPP;
3052 goto end;
3053 }
67d2e2df 3054
ccfe5552
BR		 3055 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
3056
1ed32e4f 3057 ath5k_hw_set_lladdr(sc->ah, vif->addr);
ae6f53f2 3058 ath5k_mode_setup(sc);
67d2e2df 3059
fa1c114f
JS		 3060 ret = 0;
3061end:
3062 mutex_unlock(&sc->lock);
3063 return ret;
3064}
3065
3066static void
3067ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3068 struct ieee80211_vif *vif)
fa1c114f
JS		 3069{
3070 struct ath5k_softc *sc = hw->priv;
0e149cf5 3071 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 3072
3073 mutex_lock(&sc->lock);
1ed32e4f 3074 if (sc->vif != vif)
fa1c114f
JS		 3075 goto end;
3076
0e149cf5 3077 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 3078 sc->vif = NULL;
fa1c114f
JS		 3079end:
3080 mutex_unlock(&sc->lock);
3081}
3082
d8ee398d
LR		 3083/*
3084 * TODO: Phy disable/diversity etc
3085 */
fa1c114f 3086static int
e8975581 3087ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 3088{
3089 struct ath5k_softc *sc = hw->priv;
a0823810 3090 struct ath5k_hw *ah = sc->ah;
e8975581 3091 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 3092 int ret = 0;
be009370
BC		 3093
3094 mutex_lock(&sc->lock);
fa1c114f 3095
e30eb4ab
JA		 3096 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3097 ret = ath5k_chan_set(sc, conf->channel);
3098 if (ret < 0)
3099 goto unlock;
3100 }
2bed03eb 3101
a0823810
NK		 3102 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3103 (sc->power_level != conf->power_level)) {
3104 sc->power_level = conf->power_level;
3105
3106 /* Half dB steps */
3107 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3108 }
fa1c114f 3109
2bed03eb
NK		 3110 /* TODO:
3111 * 1) Move this on config_interface and handle each case
3112 * separately eg. when we have only one STA vif, use
3113 * AR5K_ANTMODE_SINGLE_AP
3114 *
3115 * 2) Allow the user to change antenna mode eg. when only
3116 * one antenna is present
3117 *
3118 * 3) Allow the user to set default/tx antenna when possible
3119 *
3120 * 4) Default mode should handle 90% of the cases, together
3121 * with fixed a/b and single AP modes we should be able to
3122 * handle 99%. Sectored modes are extreme cases and i still
3123 * haven't found a usage for them. If we decide to support them,
3124 * then we must allow the user to set how many tx antennas we
3125 * have available
3126 */
caec9112 3127 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 3128
55aa4e0f 3129unlock:
be009370 3130 mutex_unlock(&sc->lock);
55aa4e0f 3131 return ret;
fa1c114f
JS		 3132}
3133
3ac64bee 3134static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 3135 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 3136{
3137 u32 mfilt[2], val;
3ac64bee 3138 u8 pos;
22bedad3 3139 struct netdev_hw_addr *ha;
3ac64bee
JB		 3140
3141 mfilt[0] = 0;
3142 mfilt[1] = 1;
3143
22bedad3 3144 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 3145 /* calculate XOR of eight 6-bit values */
22bedad3 3146 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 3147 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 3148 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 3149 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3150 pos &= 0x3f;
3151 mfilt[pos / 32] |= (1 << (pos % 32));
3152 /* XXX: we might be able to just do this instead,
3153 * but not sure, needs testing, if we do use this we'd
3154 * neet to inform below to not reset the mcast */
3155 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 3156 * ha->addr[5]); */
3ac64bee
JB		 3157 }
3158
3159 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3160}
3161
fa1c114f
JS		 3162#define SUPPORTED_FIF_FLAGS \
3163 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3164 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3165 FIF_BCN_PRBRESP_PROMISC
3166/*
3167 * o always accept unicast, broadcast, and multicast traffic
3168 * o multicast traffic for all BSSIDs will be enabled if mac80211
3169 * says it should be
3170 * o maintain current state of phy ofdm or phy cck error reception.
3171 * If the hardware detects any of these type of errors then
3172 * ath5k_hw_get_rx_filter() will pass to us the respective
3173 * hardware filters to be able to receive these type of frames.
3174 * o probe request frames are accepted only when operating in
3175 * hostap, adhoc, or monitor modes
3176 * o enable promiscuous mode according to the interface state
3177 * o accept beacons:
3178 * - when operating in adhoc mode so the 802.11 layer creates
3179 * node table entries for peers,
3180 * - when operating in station mode for collecting rssi data when
3181 * the station is otherwise quiet, or
3182 * - when scanning
3183 */
3184static void ath5k_configure_filter(struct ieee80211_hw *hw,
3185 unsigned int changed_flags,
3186 unsigned int *new_flags,
3ac64bee 3187 u64 multicast)
fa1c114f
JS		 3188{
3189 struct ath5k_softc *sc = hw->priv;
3190 struct ath5k_hw *ah = sc->ah;
3ac64bee 3191 u32 mfilt[2], rfilt;
fa1c114f 3192
56d1de0a
BC		 3193 mutex_lock(&sc->lock);
3194
3ac64bee
JB		 3195 mfilt[0] = multicast;
3196 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3197
3198 /* Only deal with supported flags */
3199 changed_flags &= SUPPORTED_FIF_FLAGS;
3200 *new_flags &= SUPPORTED_FIF_FLAGS;
3201
3202 /* If HW detects any phy or radar errors, leave those filters on.
3203 * Also, always enable Unicast, Broadcasts and Multicast
3204 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3205 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3206 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3207 AR5K_RX_FILTER_MCAST);
3208
3209 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3210 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 3211 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3212 } else {
fa1c114f 3213 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3214 }
fa1c114f
JS		 3215 }
3216
6b5dcccb
BC		 3217 if (test_bit(ATH_STAT_PROMISC, sc->status))
3218 rfilt |= AR5K_RX_FILTER_PROM;
3219
fa1c114f
JS		 3220 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3221 if (*new_flags & FIF_ALLMULTI) {
3222 mfilt[0] = ~0;
3223 mfilt[1] = ~0;
fa1c114f
JS		 3224 }
3225
3226 /* This is the best we can do */
3227 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3228 rfilt |= AR5K_RX_FILTER_PHYERR;
3229
3230 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
30bf4169 3231 * and probes for any BSSID */
fa1c114f 3232 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
30bf4169 3233 rfilt |= AR5K_RX_FILTER_BEACON;
fa1c114f
JS		 3234
3235 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3236 * set we should only pass on control frames for this
3237 * station. This needs testing. I believe right now this
3238 * enables *all* control frames, which is OK.. but
3239 * but we should see if we can improve on granularity */
3240 if (*new_flags & FIF_CONTROL)
3241 rfilt |= AR5K_RX_FILTER_CONTROL;
3242
3243 /* Additional settings per mode -- this is per ath5k */
3244
3245 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3246
56d1de0a
BC		 3247 switch (sc->opmode) {
3248 case NL80211_IFTYPE_MESH_POINT:
56d1de0a
BC		 3249 rfilt |= AR5K_RX_FILTER_CONTROL |
3250 AR5K_RX_FILTER_BEACON |
3251 AR5K_RX_FILTER_PROBEREQ |
3252 AR5K_RX_FILTER_PROM;
3253 break;
3254 case NL80211_IFTYPE_AP:
3255 case NL80211_IFTYPE_ADHOC:
3256 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3257 AR5K_RX_FILTER_BEACON;
3258 break;
3259 case NL80211_IFTYPE_STATION:
3260 if (sc->assoc)
3261 rfilt |= AR5K_RX_FILTER_BEACON;
3262 default:
3263 break;
3264 }
fa1c114f
JS		 3265
3266 /* Set filters */
0bbac08f 3267 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3268
3269 /* Set multicast bits */
3270 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
a180a130 3271 /* Set the cached hw filter flags, this will later actually
fa1c114f
JS		 3272 * be set in HW */
3273 sc->filter_flags = rfilt;
56d1de0a
BC		 3274
3275 mutex_unlock(&sc->lock);
fa1c114f
JS		 3276}
3277
3278static int
3279ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3280 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3281 struct ieee80211_key_conf *key)
fa1c114f
JS		 3282{
3283 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3284 struct ath5k_hw *ah = sc->ah;
3285 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3286 int ret = 0;
3287
9ad9a26e
BC		 3288 if (modparam_nohwcrypt)
3289 return -EOPNOTSUPP;
3290
97359d12
JB		 3291 switch (key->cipher) {
3292 case WLAN_CIPHER_SUITE_WEP40:
3293 case WLAN_CIPHER_SUITE_WEP104:
3294 case WLAN_CIPHER_SUITE_TKIP:
3f64b435 3295 break;
97359d12 3296 case WLAN_CIPHER_SUITE_CCMP:
781f3136 3297 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
1c818740 3298 break;
fa1c114f
JS		 3299 return -EOPNOTSUPP;
3300 default:
3301 WARN_ON(1);
3302 return -EINVAL;
3303 }
3304
3305 mutex_lock(&sc->lock);
3306
3307 switch (cmd) {
3308 case SET_KEY:
e0f8c2a9
BR		 3309 ret = ath_key_config(common, vif, sta, key);
3310 if (ret >= 0) {
3311 key->hw_key_idx = ret;
3312 /* push IV and Michael MIC generation to stack */
3313 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3314 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
3315 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3316 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
3317 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
3318 ret = 0;
fa1c114f 3319 }
fa1c114f
JS		 3320 break;
3321 case DISABLE_KEY:
e0f8c2a9 3322 ath_key_delete(common, key);
fa1c114f
JS		 3323 break;
3324 default:
3325 ret = -EINVAL;
fa1c114f
JS		 3326 }
3327
274c7c36 3328 mmiowb();
fa1c114f
JS		 3329 mutex_unlock(&sc->lock);
3330 return ret;
3331}
3332
3333static int
3334ath5k_get_stats(struct ieee80211_hw *hw,
3335 struct ieee80211_low_level_stats *stats)
3336{
3337 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3338
3339 /* Force update */
495391d7 3340 ath5k_hw_update_mib_counters(sc->ah);
fa1c114f 3341
495391d7
BR		 3342 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3343 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3344 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3345 stats->dot11FCSErrorCount = sc->stats.fcs_error;
fa1c114f
JS		 3346
3347 return 0;
3348}
3349
55ee82b5
HS		 3350static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3351 struct survey_info *survey)
3352{
3353 struct ath5k_softc *sc = hw->priv;
3354 struct ieee80211_conf *conf = &hw->conf;
3355
3356 if (idx != 0)
3357 return -ENOENT;
3358
3359 survey->channel = conf->channel;
3360 survey->filled = SURVEY_INFO_NOISE_DBM;
3361 survey->noise = sc->ah->ah_noise_floor;
3362
3363 return 0;
3364}
3365
fa1c114f
JS		 3366static u64
3367ath5k_get_tsf(struct ieee80211_hw *hw)
3368{
3369 struct ath5k_softc *sc = hw->priv;
3370
3371 return ath5k_hw_get_tsf64(sc->ah);
3372}
3373
3b5d665b
AF		 3374static void
3375ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3376{
3377 struct ath5k_softc *sc = hw->priv;
3378
3379 ath5k_hw_set_tsf64(sc->ah, tsf);
3380}
3381
fa1c114f
JS		 3382static void
3383ath5k_reset_tsf(struct ieee80211_hw *hw)
3384{
3385 struct ath5k_softc *sc = hw->priv;
3386
9804b98d
BR		 3387 /*
3388 * in IBSS mode we need to update the beacon timers too.
3389 * this will also reset the TSF if we call it with 0
3390 */
05c914fe 3391 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3392 ath5k_beacon_update_timers(sc, 0);
3393 else
3394 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3395}
3396
1071db86
BC		 3397/*
3398 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3399 * this is called only once at config_bss time, for AP we do it every
3400 * SWBA interrupt so that the TIM will reflect buffered frames.
3401 *
3402 * Called with the beacon lock.
3403 */
fa1c114f 3404static int
1071db86 3405ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3406{
fa1c114f 3407 int ret;
1071db86 3408 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3409 struct sk_buff *skb;
3410
3411 if (WARN_ON(!vif)) {
3412 ret = -EINVAL;
3413 goto out;
3414 }
3415
3416 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3417
3418 if (!skb) {
3419 ret = -ENOMEM;
3420 goto out;
3421 }
fa1c114f
JS		 3422
3423 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3424
9e4e43f2 3425 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 3426 sc->bbuf->skb = skb;
e039fa4a 3427 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3428 if (ret)
3429 sc->bbuf->skb = NULL;
1071db86
BC		 3430out:
3431 return ret;
3432}
3433
02969b38
MX		 3434static void
3435set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3436{
3437 struct ath5k_softc *sc = hw->priv;
3438 struct ath5k_hw *ah = sc->ah;
3439 u32 rfilt;
3440 rfilt = ath5k_hw_get_rx_filter(ah);
3441 if (enable)
3442 rfilt |= AR5K_RX_FILTER_BEACON;
3443 else
3444 rfilt &= ~AR5K_RX_FILTER_BEACON;
3445 ath5k_hw_set_rx_filter(ah, rfilt);
3446 sc->filter_flags = rfilt;
3447}
fa1c114f 3448
02969b38
MX		 3449static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3450 struct ieee80211_vif *vif,
3451 struct ieee80211_bss_conf *bss_conf,
3452 u32 changes)
3453{
3454 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3455 struct ath5k_hw *ah = sc->ah;
954fecea 3456 struct ath_common *common = ath5k_hw_common(ah);
21800491 3457 unsigned long flags;
2d0ddec5
JB		 3458
3459 mutex_lock(&sc->lock);
3460 if (WARN_ON(sc->vif != vif))
3461 goto unlock;
3462
3463 if (changes & BSS_CHANGED_BSSID) {
3464 /* Cache for later use during resets */
954fecea 3465 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
8ce54c5a 3466 common->curaid = 0;
418de6d9 3467 ath5k_hw_set_bssid(ah);
2d0ddec5
JB		 3468 mmiowb();
3469 }
57c4d7b4
JB		 3470
3471 if (changes & BSS_CHANGED_BEACON_INT)
3472 sc->bintval = bss_conf->beacon_int;
3473
02969b38 3474 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3475 sc->assoc = bss_conf->assoc;
3476 if (sc->opmode == NL80211_IFTYPE_STATION)
3477 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3478 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3479 AR5K_LED_ASSOC : AR5K_LED_INIT);
8ce54c5a
LR		 3480 if (bss_conf->assoc) {
3481 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3482 "Bss Info ASSOC %d, bssid: %pM\n",
3483 bss_conf->aid, common->curbssid);
3484 common->curaid = bss_conf->aid;
418de6d9 3485 ath5k_hw_set_bssid(ah);
8ce54c5a
LR		 3486 /* Once ANI is available you would start it here */
3487 }
02969b38 3488 }
2d0ddec5 3489
21800491
BC		 3490 if (changes & BSS_CHANGED_BEACON) {
3491 spin_lock_irqsave(&sc->block, flags);
3492 ath5k_beacon_update(hw, vif);
3493 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3494 }
3495
21800491
BC		 3496 if (changes & BSS_CHANGED_BEACON_ENABLED)
3497 sc->enable_beacon = bss_conf->enable_beacon;
3498
3499 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3500 BSS_CHANGED_BEACON_INT))
3501 ath5k_beacon_config(sc);
3502
2d0ddec5
JB		 3503 unlock:
3504 mutex_unlock(&sc->lock);
02969b38 3505}
f0f3d388
BC		 3506
3507static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3508{
3509 struct ath5k_softc *sc = hw->priv;
3510 if (!sc->assoc)
3511 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3512}
3513
3514static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3515{
3516 struct ath5k_softc *sc = hw->priv;
3517 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3518 AR5K_LED_ASSOC : AR5K_LED_INIT);
3519}
6e08d228
LT		 3520
3521/**
3522 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3523 *
3524 * @hw: struct ieee80211_hw pointer
3525 * @coverage_class: IEEE 802.11 coverage class number
3526 *
3527 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3528 * coverage class. The values are persistent, they are restored after device
3529 * reset.
3530 */
3531static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3532{
3533 struct ath5k_softc *sc = hw->priv;
3534
3535 mutex_lock(&sc->lock);
3536 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3537 mutex_unlock(&sc->lock);
3538}
Clone of davem's net-next-2.6 tree