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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
5a0e3ad6 53#include <linux/slab.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
62
6e220662 63static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e 64static int modparam_nohwcrypt;
46802a4f 65module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 66MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 67
42639fcd 68static int modparam_all_channels;
46802a4f 69module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 70MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
fa1c114f
JS		 72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 83MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 84
85
86/* Known PCI ids */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 106 { 0 }
107};
108MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
109
110/* Known SREVs */
2c91108c 111static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148};
149
2c91108c 150static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 /* XR missing */
190};
191
fa1c114f
JS		 192/*
193 * Prototypes - PCI stack related functions
194 */
195static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
196 const struct pci_device_id *id);
197static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198#ifdef CONFIG_PM
baee1f3c
RW		 199static int ath5k_pci_suspend(struct device *dev);
200static int ath5k_pci_resume(struct device *dev);
201
202SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
203#define ATH5K_PM_OPS (&ath5k_pm_ops)
fa1c114f 204#else
baee1f3c 205#define ATH5K_PM_OPS NULL
fa1c114f
JS		 206#endif /* CONFIG_PM */
207
04a9e451 208static struct pci_driver ath5k_pci_driver = {
9764f3f9 209 .name = KBUILD_MODNAME,
fa1c114f
JS		 210 .id_table = ath5k_pci_id_table,
211 .probe = ath5k_pci_probe,
212 .remove = __devexit_p(ath5k_pci_remove),
baee1f3c 213 .driver.pm = ATH5K_PM_OPS,
fa1c114f
JS		 214};
215
216
217
218/*
219 * Prototypes - MAC 802.11 stack related functions
220 */
e039fa4a 221static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 222static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
223 struct ath5k_txq *txq);
209d889b 224static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 225static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 226static int ath5k_start(struct ieee80211_hw *hw);
227static void ath5k_stop(struct ieee80211_hw *hw);
228static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 229 struct ieee80211_vif *vif);
fa1c114f 230static void ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 231 struct ieee80211_vif *vif);
e8975581 232static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee
JB		 233static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
234 int mc_count, struct dev_addr_list *mc_list);
fa1c114f
JS		 235static void ath5k_configure_filter(struct ieee80211_hw *hw,
236 unsigned int changed_flags,
237 unsigned int *new_flags,
3ac64bee 238 u64 multicast);
fa1c114f
JS		 239static int ath5k_set_key(struct ieee80211_hw *hw,
240 enum set_key_cmd cmd,
dc822b5d 241 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 242 struct ieee80211_key_conf *key);
243static int ath5k_get_stats(struct ieee80211_hw *hw,
244 struct ieee80211_low_level_stats *stats);
fa1c114f 245static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 246static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 247static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 248static int ath5k_beacon_update(struct ieee80211_hw *hw,
249 struct ieee80211_vif *vif);
02969b38
MX		 250static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
251 struct ieee80211_vif *vif,
252 struct ieee80211_bss_conf *bss_conf,
253 u32 changes);
f0f3d388
BC		 254static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
255static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
6e08d228
LT		 256static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
257 u8 coverage_class);
fa1c114f 258
2c91108c 259static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 260 .tx = ath5k_tx,
261 .start = ath5k_start,
262 .stop = ath5k_stop,
263 .add_interface = ath5k_add_interface,
264 .remove_interface = ath5k_remove_interface,
265 .config = ath5k_config,
3ac64bee 266 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 267 .configure_filter = ath5k_configure_filter,
268 .set_key = ath5k_set_key,
269 .get_stats = ath5k_get_stats,
270 .conf_tx = NULL,
fa1c114f 271 .get_tsf = ath5k_get_tsf,
3b5d665b 272 .set_tsf = ath5k_set_tsf,
fa1c114f 273 .reset_tsf = ath5k_reset_tsf,
02969b38 274 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 275 .sw_scan_start = ath5k_sw_scan_start,
276 .sw_scan_complete = ath5k_sw_scan_complete,
6e08d228 277 .set_coverage_class = ath5k_set_coverage_class,
fa1c114f
JS		 278};
279
280/*
281 * Prototypes - Internal functions
282 */
283/* Attach detach */
284static int ath5k_attach(struct pci_dev *pdev,
285 struct ieee80211_hw *hw);
286static void ath5k_detach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288/* Channel/mode setup */
289static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 290static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
291 struct ieee80211_channel *channels,
292 unsigned int mode,
293 unsigned int max);
63266a65 294static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 295static int ath5k_chan_set(struct ath5k_softc *sc,
296 struct ieee80211_channel *chan);
297static void ath5k_setcurmode(struct ath5k_softc *sc,
298 unsigned int mode);
299static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 300
fa1c114f
JS		 301/* Descriptor setup */
302static int ath5k_desc_alloc(struct ath5k_softc *sc,
303 struct pci_dev *pdev);
304static void ath5k_desc_free(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
306/* Buffers setup */
307static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
308 struct ath5k_buf *bf);
309static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23
BC		 310 struct ath5k_buf *bf,
311 struct ath5k_txq *txq);
fa1c114f
JS		 312static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
313 struct ath5k_buf *bf)
314{
315 BUG_ON(!bf);
316 if (!bf->skb)
317 return;
318 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
319 PCI_DMA_TODEVICE);
00482973 320 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 321 bf->skb = NULL;
322}
323
a6c8d375
FF		 324static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
325 struct ath5k_buf *bf)
326{
cc861f74
LR		 327 struct ath5k_hw *ah = sc->ah;
328 struct ath_common *common = ath5k_hw_common(ah);
329
a6c8d375
FF		 330 BUG_ON(!bf);
331 if (!bf->skb)
332 return;
cc861f74 333 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 334 PCI_DMA_FROMDEVICE);
335 dev_kfree_skb_any(bf->skb);
336 bf->skb = NULL;
337}
338
339
fa1c114f
JS		 340/* Queues setup */
341static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
342 int qtype, int subtype);
343static int ath5k_beaconq_setup(struct ath5k_hw *ah);
344static int ath5k_beaconq_config(struct ath5k_softc *sc);
345static void ath5k_txq_drainq(struct ath5k_softc *sc,
346 struct ath5k_txq *txq);
347static void ath5k_txq_cleanup(struct ath5k_softc *sc);
348static void ath5k_txq_release(struct ath5k_softc *sc);
349/* Rx handling */
350static int ath5k_rx_start(struct ath5k_softc *sc);
351static void ath5k_rx_stop(struct ath5k_softc *sc);
352static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
353 struct ath5k_desc *ds,
b47f407b
BR		 354 struct sk_buff *skb,
355 struct ath5k_rx_status *rs);
fa1c114f
JS		 356static void ath5k_tasklet_rx(unsigned long data);
357/* Tx handling */
358static void ath5k_tx_processq(struct ath5k_softc *sc,
359 struct ath5k_txq *txq);
360static void ath5k_tasklet_tx(unsigned long data);
361/* Beacon handling */
362static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 363 struct ath5k_buf *bf);
fa1c114f
JS		 364static void ath5k_beacon_send(struct ath5k_softc *sc);
365static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 366static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 367static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 368
369static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
370{
371 u64 tsf = ath5k_hw_get_tsf64(ah);
372
373 if ((tsf & 0x7fff) < rstamp)
374 tsf -= 0x8000;
375
376 return (tsf & ~0x7fff) | rstamp;
377}
378
379/* Interrupt handling */
bb2becac 380static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 381static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 382static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 383static irqreturn_t ath5k_intr(int irq, void *dev_id);
384static void ath5k_tasklet_reset(unsigned long data);
385
6e220662 386static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 387
388/*
389 * Module init/exit functions
390 */
391static int __init
392init_ath5k_pci(void)
393{
394 int ret;
395
396 ath5k_debug_init();
397
04a9e451 398 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 399 if (ret) {
400 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
401 return ret;
402 }
403
404 return 0;
405}
406
407static void __exit
408exit_ath5k_pci(void)
409{
04a9e451 410 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 411
412 ath5k_debug_finish();
413}
414
415module_init(init_ath5k_pci);
416module_exit(exit_ath5k_pci);
417
418
419/********************\
420* PCI Initialization *
421\********************/
422
423static const char *
424ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
425{
426 const char *name = "xxxxx";
427 unsigned int i;
428
429 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
430 if (srev_names[i].sr_type != type)
431 continue;
75d0edb8
NK		 432
433 if ((val & 0xf0) == srev_names[i].sr_val)
434 name = srev_names[i].sr_name;
435
436 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 437 name = srev_names[i].sr_name;
438 break;
439 }
440 }
441
442 return name;
443}
e5aa8474
LR		 444static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
445{
446 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
447 return ath5k_hw_reg_read(ah, reg_offset);
448}
449
450static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
451{
452 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
453 ath5k_hw_reg_write(ah, val, reg_offset);
454}
455
456static const struct ath_ops ath5k_common_ops = {
457 .read = ath5k_ioread32,
458 .write = ath5k_iowrite32,
459};
fa1c114f
JS		 460
461static int __devinit
462ath5k_pci_probe(struct pci_dev *pdev,
463 const struct pci_device_id *id)
464{
465 void __iomem *mem;
466 struct ath5k_softc *sc;
db719718 467 struct ath_common *common;
fa1c114f
JS		 468 struct ieee80211_hw *hw;
469 int ret;
470 u8 csz;
471
472 ret = pci_enable_device(pdev);
473 if (ret) {
474 dev_err(&pdev->dev, "can't enable device\n");
475 goto err;
476 }
477
478 /* XXX 32-bit addressing only */
284901a9 479 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 480 if (ret) {
481 dev_err(&pdev->dev, "32-bit DMA not available\n");
482 goto err_dis;
483 }
484
485 /*
486 * Cache line size is used to size and align various
487 * structures used to communicate with the hardware.
488 */
489 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
490 if (csz == 0) {
491 /*
492 * Linux 2.4.18 (at least) writes the cache line size
493 * register as a 16-bit wide register which is wrong.
494 * We must have this setup properly for rx buffer
495 * DMA to work so force a reasonable value here if it
496 * comes up zero.
497 */
13311b00 498 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 499 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
500 }
501 /*
502 * The default setting of latency timer yields poor results,
503 * set it to the value used by other systems. It may be worth
504 * tweaking this setting more.
505 */
506 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
507
508 /* Enable bus mastering */
509 pci_set_master(pdev);
510
511 /*
512 * Disable the RETRY_TIMEOUT register (0x41) to keep
513 * PCI Tx retries from interfering with C3 CPU state.
514 */
515 pci_write_config_byte(pdev, 0x41, 0);
516
517 ret = pci_request_region(pdev, 0, "ath5k");
518 if (ret) {
519 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
520 goto err_dis;
521 }
522
523 mem = pci_iomap(pdev, 0, 0);
524 if (!mem) {
525 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
526 ret = -EIO;
527 goto err_reg;
528 }
529
530 /*
531 * Allocate hw (mac80211 main struct)
532 * and hw->priv (driver private data)
533 */
534 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
535 if (hw == NULL) {
536 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
537 ret = -ENOMEM;
538 goto err_map;
539 }
540
541 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
542
543 /* Initialize driver private data */
544 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 545 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 546 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 547 IEEE80211_HW_SIGNAL_DBM |
548 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 549
550 hw->wiphy->interface_modes =
6f5f39c9 551 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 552 BIT(NL80211_IFTYPE_STATION) |
553 BIT(NL80211_IFTYPE_ADHOC) |
554 BIT(NL80211_IFTYPE_MESH_POINT);
555
fa1c114f
JS		 556 hw->extra_tx_headroom = 2;
557 hw->channel_change_time = 5000;
fa1c114f
JS		 558 sc = hw->priv;
559 sc->hw = hw;
560 sc->pdev = pdev;
561
562 ath5k_debug_init_device(sc);
563
564 /*
565 * Mark the device as detached to avoid processing
566 * interrupts until setup is complete.
567 */
568 __set_bit(ATH_STAT_INVALID, sc->status);
569
570 sc->iobase = mem; /* So we can unmap it on detach */
05c914fe 571 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 572 sc->bintval = 1000;
fa1c114f
JS		 573 mutex_init(&sc->lock);
574 spin_lock_init(&sc->rxbuflock);
575 spin_lock_init(&sc->txbuflock);
00482973 576 spin_lock_init(&sc->block);
fa1c114f
JS		 577
578 /* Set private data */
579 pci_set_drvdata(pdev, hw);
580
fa1c114f
JS		 581 /* Setup interrupt handler */
582 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
583 if (ret) {
584 ATH5K_ERR(sc, "request_irq failed\n");
585 goto err_free;
586 }
587
9adca126
LR		 588 /*If we passed the test malloc a ath5k_hw struct*/
589 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
590 if (!sc->ah) {
591 ret = -ENOMEM;
592 ATH5K_ERR(sc, "out of memory\n");
fa1c114f
JS		 593 goto err_irq;
594 }
595
9adca126
LR		 596 sc->ah->ah_sc = sc;
597 sc->ah->ah_iobase = sc->iobase;
db719718 598 common = ath5k_hw_common(sc->ah);
e5aa8474 599 common->ops = &ath5k_common_ops;
13b81559 600 common->ah = sc->ah;
b002a4a9 601 common->hw = hw;
db719718
LR		 602 common->cachelsz = csz << 2; /* convert to bytes */
603
9adca126
LR		 604 /* Initialize device */
605 ret = ath5k_hw_attach(sc);
606 if (ret) {
607 goto err_free_ah;
608 }
609
2f7fe870
FF		 610 /* set up multi-rate retry capabilities */
611 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 612 hw->max_rates = 4;
613 hw->max_rate_tries = 11;
2f7fe870
FF		 614 }
615
fa1c114f
JS		 616 /* Finish private driver data initialization */
617 ret = ath5k_attach(pdev, hw);
618 if (ret)
619 goto err_ah;
620
621 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 622 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 623 sc->ah->ah_mac_srev,
624 sc->ah->ah_phy_revision);
625
400ec45a 626 if (!sc->ah->ah_single_chip) {
fa1c114f 627 /* Single chip radio (!RF5111) */
400ec45a
LR		 628 if (sc->ah->ah_radio_5ghz_revision &&
629 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 630 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 631 if (!test_bit(AR5K_MODE_11A,
632 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 633 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 634 ath5k_chip_name(AR5K_VERSION_RAD,
635 sc->ah->ah_radio_5ghz_revision),
636 sc->ah->ah_radio_5ghz_revision);
637 /* No 2GHz support (5110 and some
638 * 5Ghz only cards) -> report 5Ghz radio */
639 } else if (!test_bit(AR5K_MODE_11B,
640 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 641 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 642 ath5k_chip_name(AR5K_VERSION_RAD,
643 sc->ah->ah_radio_5ghz_revision),
644 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 645 /* Multiband radio */
646 } else {
647 ATH5K_INFO(sc, "RF%s multiband radio found"
648 " (0x%x)\n",
400ec45a
LR		 649 ath5k_chip_name(AR5K_VERSION_RAD,
650 sc->ah->ah_radio_5ghz_revision),
651 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 652 }
653 }
400ec45a
LR		 654 /* Multi chip radio (RF5111 - RF2111) ->
655 * report both 2GHz/5GHz radios */
656 else if (sc->ah->ah_radio_5ghz_revision &&
657 sc->ah->ah_radio_2ghz_revision){
fa1c114f 658 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 659 ath5k_chip_name(AR5K_VERSION_RAD,
660 sc->ah->ah_radio_5ghz_revision),
661 sc->ah->ah_radio_5ghz_revision);
fa1c114f 662 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 663 ath5k_chip_name(AR5K_VERSION_RAD,
664 sc->ah->ah_radio_2ghz_revision),
665 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 666 }
667 }
668
669
670 /* ready to process interrupts */
671 __clear_bit(ATH_STAT_INVALID, sc->status);
672
673 return 0;
674err_ah:
675 ath5k_hw_detach(sc->ah);
676err_irq:
677 free_irq(pdev->irq, sc);
9adca126
LR		 678err_free_ah:
679 kfree(sc->ah);
fa1c114f 680err_free:
fa1c114f
JS		 681 ieee80211_free_hw(hw);
682err_map:
683 pci_iounmap(pdev, mem);
684err_reg:
685 pci_release_region(pdev, 0);
686err_dis:
687 pci_disable_device(pdev);
688err:
689 return ret;
690}
691
692static void __devexit
693ath5k_pci_remove(struct pci_dev *pdev)
694{
695 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
696 struct ath5k_softc *sc = hw->priv;
697
698 ath5k_debug_finish_device(sc);
699 ath5k_detach(pdev, hw);
700 ath5k_hw_detach(sc->ah);
9adca126 701 kfree(sc->ah);
fa1c114f 702 free_irq(pdev->irq, sc);
fa1c114f
JS		 703 pci_iounmap(pdev, sc->iobase);
704 pci_release_region(pdev, 0);
705 pci_disable_device(pdev);
706 ieee80211_free_hw(hw);
707}
708
709#ifdef CONFIG_PM
baee1f3c 710static int ath5k_pci_suspend(struct device *dev)
fa1c114f 711{
baee1f3c 712 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
fa1c114f
JS		 713 struct ath5k_softc *sc = hw->priv;
714
3a078876 715 ath5k_led_off(sc);
fa1c114f
JS		 716 return 0;
717}
718
baee1f3c 719static int ath5k_pci_resume(struct device *dev)
fa1c114f 720{
baee1f3c 721 struct pci_dev *pdev = to_pci_dev(dev);
fa1c114f
JS		 722 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
723 struct ath5k_softc *sc = hw->priv;
fa1c114f 724
8451d22d
JM		 725 /*
726 * Suspend/Resume resets the PCI configuration space, so we have to
727 * re-disable the RETRY_TIMEOUT register (0x41) to keep
728 * PCI Tx retries from interfering with C3 CPU state
729 */
730 pci_write_config_byte(pdev, 0x41, 0);
731
3a078876 732 ath5k_led_enable(sc);
fa1c114f
JS		 733 return 0;
734}
735#endif /* CONFIG_PM */
736
737
fa1c114f
JS		 738/***********************\
739* Driver Initialization *
740\***********************/
741
f769c36b
BC		 742static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
743{
744 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
745 struct ath5k_softc *sc = hw->priv;
db719718 746 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
f769c36b 747
608b88cb 748 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 749}
750
fa1c114f
JS		 751static int
752ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
753{
754 struct ath5k_softc *sc = hw->priv;
755 struct ath5k_hw *ah = sc->ah;
db719718 756 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
0e149cf5 757 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 758 int ret;
759
760 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
761
762 /*
763 * Check if the MAC has multi-rate retry support.
764 * We do this by trying to setup a fake extended
765 * descriptor. MAC's that don't have support will
766 * return false w/o doing anything. MAC's that do
767 * support it will return true w/o doing anything.
768 */
c6e387a2 769 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 770 if (ret < 0)
771 goto err;
772 if (ret > 0)
fa1c114f
JS		 773 __set_bit(ATH_STAT_MRRETRY, sc->status);
774
fa1c114f
JS		 775 /*
776 * Collect the channel list. The 802.11 layer
777 * is resposible for filtering this list based
778 * on settings like the phy mode and regulatory
779 * domain restrictions.
780 */
63266a65 781 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 782 if (ret) {
783 ATH5K_ERR(sc, "can't get channels\n");
784 goto err;
785 }
786
787 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 788 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
789 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 790 else
d8ee398d 791 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 792
793 /*
794 * Allocate tx+rx descriptors and populate the lists.
795 */
796 ret = ath5k_desc_alloc(sc, pdev);
797 if (ret) {
798 ATH5K_ERR(sc, "can't allocate descriptors\n");
799 goto err;
800 }
801
802 /*
803 * Allocate hardware transmit queues: one queue for
804 * beacon frames and one data queue for each QoS
805 * priority. Note that hw functions handle reseting
806 * these queues at the needed time.
807 */
808 ret = ath5k_beaconq_setup(ah);
809 if (ret < 0) {
810 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
811 goto err_desc;
812 }
813 sc->bhalq = ret;
cec8db23
BC		 814 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
815 if (IS_ERR(sc->cabq)) {
816 ATH5K_ERR(sc, "can't setup cab queue\n");
817 ret = PTR_ERR(sc->cabq);
818 goto err_bhal;
819 }
fa1c114f
JS		 820
821 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
822 if (IS_ERR(sc->txq)) {
823 ATH5K_ERR(sc, "can't setup xmit queue\n");
824 ret = PTR_ERR(sc->txq);
cec8db23 825 goto err_queues;
fa1c114f
JS		 826 }
827
828 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
829 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
830 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
6e220662 831 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 832 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 833
0e149cf5
BC		 834 ret = ath5k_eeprom_read_mac(ah, mac);
835 if (ret) {
836 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
837 sc->pdev->device);
838 goto err_queues;
839 }
840
fa1c114f
JS		 841 SET_IEEE80211_PERM_ADDR(hw, mac);
842 /* All MAC address bits matter for ACKs */
17753748 843 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 844 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
845
608b88cb
LR		 846 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
847 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 848 if (ret) {
849 ATH5K_ERR(sc, "can't initialize regulatory system\n");
850 goto err_queues;
851 }
852
fa1c114f
JS		 853 ret = ieee80211_register_hw(hw);
854 if (ret) {
855 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
856 goto err_queues;
857 }
858
608b88cb
LR		 859 if (!ath_is_world_regd(regulatory))
860 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 861
3a078876
BC		 862 ath5k_init_leds(sc);
863
fa1c114f
JS		 864 return 0;
865err_queues:
866 ath5k_txq_release(sc);
867err_bhal:
868 ath5k_hw_release_tx_queue(ah, sc->bhalq);
869err_desc:
870 ath5k_desc_free(sc, pdev);
871err:
872 return ret;
873}
874
875static void
876ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
877{
878 struct ath5k_softc *sc = hw->priv;
879
880 /*
881 * NB: the order of these is important:
882 * o call the 802.11 layer before detaching ath5k_hw to
883 * insure callbacks into the driver to delete global
884 * key cache entries can be handled
885 * o reclaim the tx queue data structures after calling
886 * the 802.11 layer as we'll get called back to reclaim
887 * node state and potentially want to use them
888 * o to cleanup the tx queues the hal is called, so detach
889 * it last
890 * XXX: ??? detach ath5k_hw ???
891 * Other than that, it's straightforward...
892 */
893 ieee80211_unregister_hw(hw);
894 ath5k_desc_free(sc, pdev);
895 ath5k_txq_release(sc);
896 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 897 ath5k_unregister_leds(sc);
fa1c114f
JS		 898
899 /*
900 * NB: can't reclaim these until after ieee80211_ifdetach
901 * returns because we'll get called back to reclaim node
902 * state and potentially want to use them.
903 */
904}
905
906
907
908
909/********************\
910* Channel/mode setup *
911\********************/
912
913/*
914 * Convert IEEE channel number to MHz frequency.
915 */
916static inline short
917ath5k_ieee2mhz(short chan)
918{
919 if (chan <= 14 || chan >= 27)
920 return ieee80211chan2mhz(chan);
921 else
922 return 2212 + chan * 20;
923}
924
42639fcd
BC		 925/*
926 * Returns true for the channel numbers used without all_channels modparam.
927 */
928static bool ath5k_is_standard_channel(short chan)
929{
930 return ((chan <= 14) ||
931 /* UNII 1,2 */
932 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
933 /* midband */
934 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
935 /* UNII-3 */
936 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
937}
938
fa1c114f
JS		 939static unsigned int
940ath5k_copy_channels(struct ath5k_hw *ah,
941 struct ieee80211_channel *channels,
942 unsigned int mode,
943 unsigned int max)
944{
d8ee398d 945 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 946
947 if (!test_bit(mode, ah->ah_modes))
948 return 0;
949
fa1c114f 950 switch (mode) {
d8ee398d
LR		 951 case AR5K_MODE_11A:
952 case AR5K_MODE_11A_TURBO:
fa1c114f 953 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 954 size = 220 ;
fa1c114f
JS		 955 chfreq = CHANNEL_5GHZ;
956 break;
d8ee398d
LR		 957 case AR5K_MODE_11B:
958 case AR5K_MODE_11G:
959 case AR5K_MODE_11G_TURBO:
960 size = 26;
fa1c114f
JS		 961 chfreq = CHANNEL_2GHZ;
962 break;
963 default:
964 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
965 return 0;
966 }
967
968 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 969 ch = i + 1 ;
970 freq = ath5k_ieee2mhz(ch);
fa1c114f 971
d8ee398d
LR		 972 /* Check if channel is supported by the chipset */
973 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 974 continue;
975
42639fcd
BC		 976 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
977 continue;
978
d8ee398d
LR		 979 /* Write channel info and increment counter */
980 channels[count].center_freq = freq;
a3f4b914
LR		 981 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
982 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 983 switch (mode) {
984 case AR5K_MODE_11A:
985 case AR5K_MODE_11G:
986 channels[count].hw_value = chfreq | CHANNEL_OFDM;
987 break;
988 case AR5K_MODE_11A_TURBO:
989 case AR5K_MODE_11G_TURBO:
990 channels[count].hw_value = chfreq |
991 CHANNEL_OFDM | CHANNEL_TURBO;
992 break;
993 case AR5K_MODE_11B:
d8ee398d
LR		 994 channels[count].hw_value = CHANNEL_B;
995 }
fa1c114f 996
fa1c114f
JS		 997 count++;
998 max--;
999 }
1000
1001 return count;
1002}
1003
63266a65
BR		 1004static void
1005ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1006{
1007 u8 i;
1008
1009 for (i = 0; i < AR5K_MAX_RATES; i++)
1010 sc->rate_idx[b->band][i] = -1;
1011
1012 for (i = 0; i < b->n_bitrates; i++) {
1013 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1014 if (b->bitrates[i].hw_value_short)
1015 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1016 }
1017}
1018
d8ee398d 1019static int
63266a65 1020ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1021{
1022 struct ath5k_softc *sc = hw->priv;
d8ee398d 1023 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1024 struct ieee80211_supported_band *sband;
1025 int max_c, count_c = 0;
1026 int i;
fa1c114f 1027
d8ee398d 1028 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1029 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1030
1031 /* 2GHz band */
63266a65
BR		 1032 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1033 sband->band = IEEE80211_BAND_2GHZ;
1034 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1035
63266a65
BR		 1036 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1037 /* G mode */
1038 memcpy(sband->bitrates, &ath5k_rates[0],
1039 sizeof(struct ieee80211_rate) * 12);
1040 sband->n_bitrates = 12;
fa1c114f 1041
d8ee398d 1042 sband->channels = sc->channels;
d8ee398d 1043 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1044 AR5K_MODE_11G, max_c);
fa1c114f 1045
63266a65 1046 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1047 count_c = sband->n_channels;
63266a65
BR		 1048 max_c -= count_c;
1049 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1050 /* B mode */
1051 memcpy(sband->bitrates, &ath5k_rates[0],
1052 sizeof(struct ieee80211_rate) * 4);
1053 sband->n_bitrates = 4;
1054
1055 /* 5211 only supports B rates and uses 4bit rate codes
1056 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1057 * fix them up here:
1058 */
1059 if (ah->ah_version == AR5K_AR5211) {
1060 for (i = 0; i < 4; i++) {
1061 sband->bitrates[i].hw_value =
1062 sband->bitrates[i].hw_value & 0xF;
1063 sband->bitrates[i].hw_value_short =
1064 sband->bitrates[i].hw_value_short & 0xF;
1065 }
1066 }
fa1c114f 1067
63266a65
BR		 1068 sband->channels = sc->channels;
1069 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1070 AR5K_MODE_11B, max_c);
d8ee398d 1071
63266a65
BR		 1072 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1073 count_c = sband->n_channels;
d8ee398d 1074 max_c -= count_c;
fa1c114f 1075 }
63266a65 1076 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1077
63266a65 1078 /* 5GHz band, A mode */
400ec45a 1079 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1080 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1081 sband->band = IEEE80211_BAND_5GHZ;
1082 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1083
63266a65
BR		 1084 memcpy(sband->bitrates, &ath5k_rates[4],
1085 sizeof(struct ieee80211_rate) * 8);
1086 sband->n_bitrates = 8;
fa1c114f 1087
63266a65 1088 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1089 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1090 AR5K_MODE_11A, max_c);
1091
d8ee398d
LR		 1092 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1093 }
63266a65 1094 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1095
b446197c 1096 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1097
1098 return 0;
fa1c114f
JS		 1099}
1100
1101/*
e30eb4ab
JA		 1102 * Set/change channels. We always reset the chip.
1103 * To accomplish this we must first cleanup any pending DMA,
1104 * then restart stuff after a la ath5k_init.
be009370
BC		 1105 *
1106 * Called with sc->lock.
fa1c114f
JS		 1107 */
1108static int
1109ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1110{
d8ee398d
LR		 1111 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1112 sc->curchan->center_freq, chan->center_freq);
1113
e30eb4ab
JA		 1114 /*
1115 * To switch channels clear any pending DMA operations;
1116 * wait long enough for the RX fifo to drain, reset the
1117 * hardware at the new frequency, and then re-enable
1118 * the relevant bits of the h/w.
1119 */
1120 return ath5k_reset(sc, chan);
fa1c114f
JS		 1121}
1122
1123static void
1124ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1125{
fa1c114f 1126 sc->curmode = mode;
d8ee398d 1127
400ec45a 1128 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1129 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1130 } else {
1131 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1132 }
fa1c114f
JS		 1133}
1134
1135static void
1136ath5k_mode_setup(struct ath5k_softc *sc)
1137{
1138 struct ath5k_hw *ah = sc->ah;
1139 u32 rfilt;
1140
ae6f53f2
BC		 1141 ah->ah_op_mode = sc->opmode;
1142
fa1c114f
JS		 1143 /* configure rx filter */
1144 rfilt = sc->filter_flags;
1145 ath5k_hw_set_rx_filter(ah, rfilt);
1146
1147 if (ath5k_hw_hasbssidmask(ah))
1148 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1149
1150 /* configure operational mode */
1151 ath5k_hw_set_opmode(ah);
1152
fa1c114f
JS		 1153 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1154}
1155
d8ee398d 1156static inline int
63266a65
BR		 1157ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1158{
b7266047
BC		 1159 int rix;
1160
1161 /* return base rate on errors */
1162 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1163 "hw_rix out of bounds: %x\n", hw_rix))
1164 return 0;
1165
1166 rix = sc->rate_idx[sc->curband->band][hw_rix];
1167 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1168 rix = 0;
1169
1170 return rix;
d8ee398d
LR		 1171}
1172
fa1c114f
JS		 1173/***************\
1174* Buffers setup *
1175\***************/
1176
b6ea0356
BC		 1177static
1178struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1179{
db719718 1180 struct ath_common *common = ath5k_hw_common(sc->ah);
b6ea0356 1181 struct sk_buff *skb;
b6ea0356
BC		 1182
1183 /*
1184 * Allocate buffer with headroom_needed space for the
1185 * fake physical layer header at the start.
1186 */
db719718 1187 skb = ath_rxbuf_alloc(common,
dd849782 1188 common->rx_bufsize,
aeb63cfd 1189 GFP_ATOMIC);
b6ea0356
BC		 1190
1191 if (!skb) {
1192 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
dd849782 1193 common->rx_bufsize);
b6ea0356
BC		 1194 return NULL;
1195 }
b6ea0356
BC		 1196
1197 *skb_addr = pci_map_single(sc->pdev,
cc861f74
LR		 1198 skb->data, common->rx_bufsize,
1199 PCI_DMA_FROMDEVICE);
b6ea0356
BC		 1200 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1201 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1202 dev_kfree_skb(skb);
1203 return NULL;
1204 }
1205 return skb;
1206}
1207
fa1c114f
JS		 1208static int
1209ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1210{
1211 struct ath5k_hw *ah = sc->ah;
1212 struct sk_buff *skb = bf->skb;
1213 struct ath5k_desc *ds;
1214
b6ea0356
BC		 1215 if (!skb) {
1216 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1217 if (!skb)
fa1c114f 1218 return -ENOMEM;
fa1c114f 1219 bf->skb = skb;
fa1c114f
JS		 1220 }
1221
1222 /*
1223 * Setup descriptors. For receive we always terminate
1224 * the descriptor list with a self-linked entry so we'll
1225 * not get overrun under high load (as can happen with a
1226 * 5212 when ANI processing enables PHY error frames).
1227 *
1228 * To insure the last descriptor is self-linked we create
1229 * each descriptor as self-linked and add it to the end. As
1230 * each additional descriptor is added the previous self-linked
1231 * entry is ``fixed'' naturally. This should be safe even
1232 * if DMA is happening. When processing RX interrupts we
1233 * never remove/process the last, self-linked, entry on the
1234 * descriptor list. This insures the hardware always has
1235 * someplace to write a new frame.
1236 */
1237 ds = bf->desc;
1238 ds->ds_link = bf->daddr; /* link to self */
1239 ds->ds_data = bf->skbaddr;
c6e387a2 1240 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1241 skb_tailroom(skb), /* buffer size */
1242 0);
1243
1244 if (sc->rxlink != NULL)
1245 *sc->rxlink = bf->daddr;
1246 sc->rxlink = &ds->ds_link;
1247 return 0;
1248}
1249
2ac2927a
BC		 1250static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1251{
1252 struct ieee80211_hdr *hdr;
1253 enum ath5k_pkt_type htype;
1254 __le16 fc;
1255
1256 hdr = (struct ieee80211_hdr *)skb->data;
1257 fc = hdr->frame_control;
1258
1259 if (ieee80211_is_beacon(fc))
1260 htype = AR5K_PKT_TYPE_BEACON;
1261 else if (ieee80211_is_probe_resp(fc))
1262 htype = AR5K_PKT_TYPE_PROBE_RESP;
1263 else if (ieee80211_is_atim(fc))
1264 htype = AR5K_PKT_TYPE_ATIM;
1265 else if (ieee80211_is_pspoll(fc))
1266 htype = AR5K_PKT_TYPE_PSPOLL;
1267 else
1268 htype = AR5K_PKT_TYPE_NORMAL;
1269
1270 return htype;
1271}
1272
fa1c114f 1273static int
cec8db23
BC		 1274ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1275 struct ath5k_txq *txq)
fa1c114f
JS		 1276{
1277 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1278 struct ath5k_desc *ds = bf->desc;
1279 struct sk_buff *skb = bf->skb;
a888d52d 1280 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1281 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1282 struct ieee80211_rate *rate;
1283 unsigned int mrr_rate[3], mrr_tries[3];
1284 int i, ret;
8902ff4e 1285 u16 hw_rate;
07c1e852
BC		 1286 u16 cts_rate = 0;
1287 u16 duration = 0;
8902ff4e 1288 u8 rc_flags;
fa1c114f
JS		 1289
1290 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1291
fa1c114f
JS		 1292 /* XXX endianness */
1293 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1294 PCI_DMA_TODEVICE);
1295
8902ff4e
BC		 1296 rate = ieee80211_get_tx_rate(sc->hw, info);
1297
e039fa4a 1298 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1299 flags |= AR5K_TXDESC_NOACK;
1300
8902ff4e
BC		 1301 rc_flags = info->control.rates[0].flags;
1302 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1303 rate->hw_value_short : rate->hw_value;
1304
281c56dd 1305 pktlen = skb->len;
fa1c114f 1306
8f655dde
NK		 1307 /* FIXME: If we are in g mode and rate is a CCK rate
1308 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1309 * from tx power (value is in dB units already) */
362695e1
BC		 1310 if (info->control.hw_key) {
1311 keyidx = info->control.hw_key->hw_key_idx;
1312 pktlen += info->control.hw_key->icv_len;
1313 }
07c1e852
BC		 1314 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1315 flags |= AR5K_TXDESC_RTSENA;
1316 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1317 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1318 sc->vif, pktlen, info));
1319 }
1320 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1321 flags |= AR5K_TXDESC_CTSENA;
1322 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1323 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1324 sc->vif, pktlen, info));
1325 }
fa1c114f 1326 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
2ac2927a
BC		 1327 ieee80211_get_hdrlen_from_skb(skb),
1328 get_hw_packet_type(skb),
2e92e6f2 1329 (sc->power_level * 2),
8902ff4e 1330 hw_rate,
2bed03eb 1331 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1332 cts_rate, duration);
fa1c114f
JS		 1333 if (ret)
1334 goto err_unmap;
1335
2f7fe870
FF		 1336 memset(mrr_rate, 0, sizeof(mrr_rate));
1337 memset(mrr_tries, 0, sizeof(mrr_tries));
1338 for (i = 0; i < 3; i++) {
1339 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1340 if (!rate)
1341 break;
1342
1343 mrr_rate[i] = rate->hw_value;
e6a9854b 1344 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1345 }
1346
1347 ah->ah_setup_mrr_tx_desc(ah, ds,
1348 mrr_rate[0], mrr_tries[0],
1349 mrr_rate[1], mrr_tries[1],
1350 mrr_rate[2], mrr_tries[2]);
1351
fa1c114f
JS		 1352 ds->ds_link = 0;
1353 ds->ds_data = bf->skbaddr;
1354
1355 spin_lock_bh(&txq->lock);
1356 list_add_tail(&bf->list, &txq->q);
fa1c114f 1357 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1358 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1359 else /* no, so only link it */
1360 *txq->link = bf->daddr;
1361
1362 txq->link = &ds->ds_link;
c6e387a2 1363 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1364 mmiowb();
fa1c114f
JS		 1365 spin_unlock_bh(&txq->lock);
1366
1367 return 0;
1368err_unmap:
1369 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1370 return ret;
1371}
1372
1373/*******************\
1374* Descriptors setup *
1375\*******************/
1376
1377static int
1378ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1379{
1380 struct ath5k_desc *ds;
1381 struct ath5k_buf *bf;
1382 dma_addr_t da;
1383 unsigned int i;
1384 int ret;
1385
1386 /* allocate descriptors */
1387 sc->desc_len = sizeof(struct ath5k_desc) *
1388 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1389 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1390 if (sc->desc == NULL) {
1391 ATH5K_ERR(sc, "can't allocate descriptors\n");
1392 ret = -ENOMEM;
1393 goto err;
1394 }
1395 ds = sc->desc;
1396 da = sc->desc_daddr;
1397 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1398 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1399
1400 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1401 sizeof(struct ath5k_buf), GFP_KERNEL);
1402 if (bf == NULL) {
1403 ATH5K_ERR(sc, "can't allocate bufptr\n");
1404 ret = -ENOMEM;
1405 goto err_free;
1406 }
1407 sc->bufptr = bf;
1408
1409 INIT_LIST_HEAD(&sc->rxbuf);
1410 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1411 bf->desc = ds;
1412 bf->daddr = da;
1413 list_add_tail(&bf->list, &sc->rxbuf);
1414 }
1415
1416 INIT_LIST_HEAD(&sc->txbuf);
1417 sc->txbuf_len = ATH_TXBUF;
1418 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1419 da += sizeof(*ds)) {
1420 bf->desc = ds;
1421 bf->daddr = da;
1422 list_add_tail(&bf->list, &sc->txbuf);
1423 }
1424
1425 /* beacon buffer */
1426 bf->desc = ds;
1427 bf->daddr = da;
1428 sc->bbuf = bf;
1429
1430 return 0;
1431err_free:
1432 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1433err:
1434 sc->desc = NULL;
1435 return ret;
1436}
1437
1438static void
1439ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1440{
1441 struct ath5k_buf *bf;
1442
1443 ath5k_txbuf_free(sc, sc->bbuf);
1444 list_for_each_entry(bf, &sc->txbuf, list)
1445 ath5k_txbuf_free(sc, bf);
1446 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1447 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1448
1449 /* Free memory associated with all descriptors */
1450 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1451
1452 kfree(sc->bufptr);
1453 sc->bufptr = NULL;
1454}
1455
1456
1457
1458
1459
1460/**************\
1461* Queues setup *
1462\**************/
1463
1464static struct ath5k_txq *
1465ath5k_txq_setup(struct ath5k_softc *sc,
1466 int qtype, int subtype)
1467{
1468 struct ath5k_hw *ah = sc->ah;
1469 struct ath5k_txq *txq;
1470 struct ath5k_txq_info qi = {
1471 .tqi_subtype = subtype,
1472 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1473 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1474 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1475 };
1476 int qnum;
1477
1478 /*
1479 * Enable interrupts only for EOL and DESC conditions.
1480 * We mark tx descriptors to receive a DESC interrupt
1481 * when a tx queue gets deep; otherwise waiting for the
1482 * EOL to reap descriptors. Note that this is done to
1483 * reduce interrupt load and this only defers reaping
1484 * descriptors, never transmitting frames. Aside from
1485 * reducing interrupts this also permits more concurrency.
1486 * The only potential downside is if the tx queue backs
1487 * up in which case the top half of the kernel may backup
1488 * due to a lack of tx descriptors.
1489 */
1490 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1491 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1492 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1493 if (qnum < 0) {
1494 /*
1495 * NB: don't print a message, this happens
1496 * normally on parts with too few tx queues
1497 */
1498 return ERR_PTR(qnum);
1499 }
1500 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1501 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1502 qnum, ARRAY_SIZE(sc->txqs));
1503 ath5k_hw_release_tx_queue(ah, qnum);
1504 return ERR_PTR(-EINVAL);
1505 }
1506 txq = &sc->txqs[qnum];
1507 if (!txq->setup) {
1508 txq->qnum = qnum;
1509 txq->link = NULL;
1510 INIT_LIST_HEAD(&txq->q);
1511 spin_lock_init(&txq->lock);
1512 txq->setup = true;
1513 }
1514 return &sc->txqs[qnum];
1515}
1516
1517static int
1518ath5k_beaconq_setup(struct ath5k_hw *ah)
1519{
1520 struct ath5k_txq_info qi = {
1521 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1522 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1523 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1524 /* NB: for dynamic turbo, don't enable any other interrupts */
1525 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1526 };
1527
1528 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1529}
1530
1531static int
1532ath5k_beaconq_config(struct ath5k_softc *sc)
1533{
1534 struct ath5k_hw *ah = sc->ah;
1535 struct ath5k_txq_info qi;
1536 int ret;
1537
1538 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1539 if (ret)
a951ae21
BC		 1540 goto err;
1541
05c914fe
JB		 1542 if (sc->opmode == NL80211_IFTYPE_AP ||
1543 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1544 /*
1545 * Always burst out beacon and CAB traffic
1546 * (aifs = cwmin = cwmax = 0)
1547 */
1548 qi.tqi_aifs = 0;
1549 qi.tqi_cw_min = 0;
1550 qi.tqi_cw_max = 0;
05c914fe 1551 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1552 /*
1553 * Adhoc mode; backoff between 0 and (2 * cw_min).
1554 */
1555 qi.tqi_aifs = 0;
1556 qi.tqi_cw_min = 0;
1557 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1558 }
1559
6d91e1d8
BR		 1560 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1561 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1562 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1563
c6e387a2 1564 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1565 if (ret) {
1566 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1567 "hardware queue!\n", __func__);
a951ae21 1568 goto err;
fa1c114f 1569 }
a951ae21
BC		 1570 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1571 if (ret)
1572 goto err;
fa1c114f 1573
a951ae21
BC		 1574 /* reconfigure cabq with ready time to 80% of beacon_interval */
1575 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1576 if (ret)
1577 goto err;
1578
1579 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1580 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1581 if (ret)
1582 goto err;
1583
1584 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1585err:
1586 return ret;
fa1c114f
JS		 1587}
1588
1589static void
1590ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1591{
1592 struct ath5k_buf *bf, *bf0;
1593
1594 /*
1595 * NB: this assumes output has been stopped and
1596 * we do not need to block ath5k_tx_tasklet
1597 */
1598 spin_lock_bh(&txq->lock);
1599 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1600 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1601
1602 ath5k_txbuf_free(sc, bf);
1603
1604 spin_lock_bh(&sc->txbuflock);
fa1c114f
JS		 1605 list_move_tail(&bf->list, &sc->txbuf);
1606 sc->txbuf_len++;
1607 spin_unlock_bh(&sc->txbuflock);
1608 }
1609 txq->link = NULL;
1610 spin_unlock_bh(&txq->lock);
1611}
1612
1613/*
1614 * Drain the transmit queues and reclaim resources.
1615 */
1616static void
1617ath5k_txq_cleanup(struct ath5k_softc *sc)
1618{
1619 struct ath5k_hw *ah = sc->ah;
1620 unsigned int i;
1621
1622 /* XXX return value */
1623 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1624 /* don't touch the hardware if marked invalid */
1625 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1626 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1627 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1628 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1629 if (sc->txqs[i].setup) {
1630 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1631 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1632 "link %p\n",
1633 sc->txqs[i].qnum,
c6e387a2 1634 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1635 sc->txqs[i].qnum),
1636 sc->txqs[i].link);
1637 }
1638 }
36d6825b 1639 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1640
1641 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1642 if (sc->txqs[i].setup)
1643 ath5k_txq_drainq(sc, &sc->txqs[i]);
1644}
1645
1646static void
1647ath5k_txq_release(struct ath5k_softc *sc)
1648{
1649 struct ath5k_txq *txq = sc->txqs;
1650 unsigned int i;
1651
1652 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1653 if (txq->setup) {
1654 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1655 txq->setup = false;
1656 }
1657}
1658
1659
1660
1661
1662/*************\
1663* RX Handling *
1664\*************/
1665
1666/*
1667 * Enable the receive h/w following a reset.
1668 */
1669static int
1670ath5k_rx_start(struct ath5k_softc *sc)
1671{
1672 struct ath5k_hw *ah = sc->ah;
db719718 1673 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 1674 struct ath5k_buf *bf;
1675 int ret;
1676
cc861f74 1677 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
fa1c114f 1678
cc861f74
LR		 1679 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1680 common->cachelsz, common->rx_bufsize);
fa1c114f 1681
fa1c114f 1682 spin_lock_bh(&sc->rxbuflock);
26925042 1683 sc->rxlink = NULL;
fa1c114f
JS		 1684 list_for_each_entry(bf, &sc->rxbuf, list) {
1685 ret = ath5k_rxbuf_setup(sc, bf);
1686 if (ret != 0) {
1687 spin_unlock_bh(&sc->rxbuflock);
1688 goto err;
1689 }
1690 }
1691 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1692 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1693 spin_unlock_bh(&sc->rxbuflock);
1694
c6e387a2 1695 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1696 ath5k_mode_setup(sc); /* set filters, etc. */
1697 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1698
1699 return 0;
1700err:
1701 return ret;
1702}
1703
1704/*
1705 * Disable the receive h/w in preparation for a reset.
1706 */
1707static void
1708ath5k_rx_stop(struct ath5k_softc *sc)
1709{
1710 struct ath5k_hw *ah = sc->ah;
1711
c6e387a2 1712 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1713 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1714 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1715
1716 ath5k_debug_printrxbuffs(sc, ah);
1717
1718 sc->rxlink = NULL; /* just in case */
1719}
1720
1721static unsigned int
1722ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1723 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f 1724{
dc1e001b
LR		 1725 struct ath5k_hw *ah = sc->ah;
1726 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1727 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1728 unsigned int keyix, hlen;
fa1c114f 1729
b47f407b
BR		 1730 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1731 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1732 return RX_FLAG_DECRYPTED;
1733
1734 /* Apparently when a default key is used to decrypt the packet
1735 the hw does not set the index used to decrypt. In such cases
1736 get the index from the packet. */
798ee985 1737 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1738 if (ieee80211_has_protected(hdr->frame_control) &&
1739 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1740 skb->len >= hlen + 4) {
fa1c114f
JS		 1741 keyix = skb->data[hlen + 3] >> 6;
1742
dc1e001b 1743 if (test_bit(keyix, common->keymap))
fa1c114f
JS		 1744 return RX_FLAG_DECRYPTED;
1745 }
1746
1747 return 0;
1748}
1749
036cd1ec
BR		 1750
1751static void
6ba81c2c
BR		 1752ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1753 struct ieee80211_rx_status *rxs)
036cd1ec 1754{
954fecea 1755 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1756 u64 tsf, bc_tstamp;
036cd1ec
BR		 1757 u32 hw_tu;
1758 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1759
24b56e70 1760 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1761 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1762 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1763 /*
6ba81c2c
BR		 1764 * Received an IBSS beacon with the same BSSID. Hardware *must*
1765 * have updated the local TSF. We have to work around various
1766 * hardware bugs, though...
036cd1ec 1767 */
6ba81c2c
BR		 1768 tsf = ath5k_hw_get_tsf64(sc->ah);
1769 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1770 hw_tu = TSF_TO_TU(tsf);
1771
1772 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1773 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1774 (unsigned long long)bc_tstamp,
1775 (unsigned long long)rxs->mactime,
1776 (unsigned long long)(rxs->mactime - bc_tstamp),
1777 (unsigned long long)tsf);
6ba81c2c
BR		 1778
1779 /*
1780 * Sometimes the HW will give us a wrong tstamp in the rx
1781 * status, causing the timestamp extension to go wrong.
1782 * (This seems to happen especially with beacon frames bigger
1783 * than 78 byte (incl. FCS))
1784 * But we know that the receive timestamp must be later than the
1785 * timestamp of the beacon since HW must have synced to that.
1786 *
1787 * NOTE: here we assume mactime to be after the frame was
1788 * received, not like mac80211 which defines it at the start.
1789 */
1790 if (bc_tstamp > rxs->mactime) {
036cd1ec 1791 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1792 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1793 (unsigned long long)rxs->mactime,
1794 (unsigned long long)tsf);
6ba81c2c 1795 rxs->mactime = tsf;
036cd1ec 1796 }
6ba81c2c
BR		 1797
1798 /*
1799 * Local TSF might have moved higher than our beacon timers,
1800 * in that case we have to update them to continue sending
1801 * beacons. This also takes care of synchronizing beacon sending
1802 * times with other stations.
1803 */
1804 if (hw_tu >= sc->nexttbtt)
1805 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1806 }
1807}
1808
fa1c114f
JS		 1809static void
1810ath5k_tasklet_rx(unsigned long data)
1811{
1c5256bb 1812 struct ieee80211_rx_status *rxs;
b47f407b 1813 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1814 struct sk_buff *skb, *next_skb;
1815 dma_addr_t next_skb_addr;
fa1c114f 1816 struct ath5k_softc *sc = (void *)data;
cc861f74
LR		 1817 struct ath5k_hw *ah = sc->ah;
1818 struct ath_common *common = ath5k_hw_common(ah);
c57ca815 1819 struct ath5k_buf *bf;
fa1c114f 1820 struct ath5k_desc *ds;
fa1c114f
JS		 1821 int ret;
1822 int hdrlen;
0fe45b1d 1823 int padsize;
1c5256bb 1824 int rx_flag;
fa1c114f
JS		 1825
1826 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1827 if (list_empty(&sc->rxbuf)) {
1828 ATH5K_WARN(sc, "empty rx buf pool\n");
1829 goto unlock;
1830 }
fa1c114f 1831 do {
1c5256bb 1832 rx_flag = 0;
d6894b5b 1833
fa1c114f
JS		 1834 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1835 BUG_ON(bf->skb == NULL);
1836 skb = bf->skb;
1837 ds = bf->desc;
1838
c57ca815
BC		 1839 /* bail if HW is still using self-linked descriptor */
1840 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1841 break;
fa1c114f 1842
b47f407b 1843 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1844 if (unlikely(ret == -EINPROGRESS))
1845 break;
1846 else if (unlikely(ret)) {
1847 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1848 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1849 return;
1850 }
1851
b47f407b 1852 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1853 ATH5K_WARN(sc, "unsupported jumbo\n");
1854 goto next;
1855 }
1856
b47f407b
BR		 1857 if (unlikely(rs.rs_status)) {
1858 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1859 goto next;
b47f407b 1860 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1861 /*
1862 * Decrypt error. If the error occurred
1863 * because there was no hardware key, then
1864 * let the frame through so the upper layers
1865 * can process it. This is necessary for 5210
1866 * parts which have no way to setup a ``clear''
1867 * key cache entry.
1868 *
1869 * XXX do key cache faulting
1870 */
b47f407b
BR		 1871 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1872 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1873 goto accept;
1874 }
b47f407b 1875 if (rs.rs_status & AR5K_RXERR_MIC) {
1c5256bb 1876 rx_flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1877 goto accept;
1878 }
1879
1880 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1881 if ((rs.rs_status &
1882 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1883 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1884 goto next;
1885 }
1886accept:
b6ea0356
BC		 1887 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1888
1889 /*
1890 * If we can't replace bf->skb with a new skb under memory
1891 * pressure, just skip this packet
1892 */
1893 if (!next_skb)
1894 goto next;
1895
cc861f74 1896 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
fa1c114f 1897 PCI_DMA_FROMDEVICE);
b47f407b 1898 skb_put(skb, rs.rs_datalen);
fa1c114f 1899
0fe45b1d
BP		 1900 /* The MAC header is padded to have 32-bit boundary if the
1901 * packet payload is non-zero. The general calculation for
1902 * padsize would take into account odd header lengths:
1903 * padsize = (4 - hdrlen % 4) % 4; However, since only
1904 * even-length headers are used, padding can only be 0 or 2
1905 * bytes and we can optimize this a bit. In addition, we must
1906 * not try to remove padding from short control frames that do
1907 * not have payload. */
fa1c114f 1908 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1909 padsize = ath5k_pad_size(hdrlen);
1910 if (padsize) {
0fe45b1d
BP		 1911 memmove(skb->data + padsize, skb->data, hdrlen);
1912 skb_pull(skb, padsize);
fa1c114f 1913 }
1c5256bb 1914 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 1915
c0e1899b
BR		 1916 /*
1917 * always extend the mac timestamp, since this information is
1918 * also needed for proper IBSS merging.
1919 *
1920 * XXX: it might be too late to do it here, since rs_tstamp is
1921 * 15bit only. that means TSF extension has to be done within
1922 * 32768usec (about 32ms). it might be necessary to move this to
1923 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1924 *
1925 * Unfortunately we don't know when the hardware takes the rx
1926 * timestamp (beginning of phy frame, data frame, end of rx?).
1927 * The only thing we know is that it is hardware specific...
1928 * On AR5213 it seems the rx timestamp is at the end of the
1929 * frame, but i'm not sure.
1930 *
1931 * NOTE: mac80211 defines mactime at the beginning of the first
1932 * data symbol. Since we don't have any time references it's
1933 * impossible to comply to that. This affects IBSS merge only
1934 * right now, so it's not too bad...
c0e1899b 1935 */
1c5256bb
BC		 1936 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1937 rxs->flag = rx_flag | RX_FLAG_TSFT;
c0e1899b 1938
1c5256bb
BC		 1939 rxs->freq = sc->curchan->center_freq;
1940 rxs->band = sc->curband->band;
fa1c114f 1941
1c5256bb
BC		 1942 rxs->noise = sc->ah->ah_noise_floor;
1943 rxs->signal = rxs->noise + rs.rs_rssi;
6e0e0bf8 1944
1c5256bb
BC		 1945 rxs->antenna = rs.rs_antenna;
1946 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1947 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1948
1c5256bb
BC		 1949 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1950 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1951 rxs->flag |= RX_FLAG_SHORTPRE;
06303352 1952
fa1c114f
JS		 1953 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1954
036cd1ec 1955 /* check beacons in IBSS mode */
05c914fe 1956 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1c5256bb 1957 ath5k_check_ibss_tsf(sc, skb, rxs);
036cd1ec 1958
f1d58c25 1959 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 1960
1961 bf->skb = next_skb;
1962 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1963next:
1964 list_move_tail(&bf->list, &sc->rxbuf);
1965 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1966unlock:
fa1c114f
JS		 1967 spin_unlock(&sc->rxbuflock);
1968}
1969
1970
1971
1972
1973/*************\
1974* TX Handling *
1975\*************/
1976
1977static void
1978ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1979{
b47f407b 1980 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1981 struct ath5k_buf *bf, *bf0;
1982 struct ath5k_desc *ds;
1983 struct sk_buff *skb;
e039fa4a 1984 struct ieee80211_tx_info *info;
2f7fe870 1985 int i, ret;
fa1c114f
JS		 1986
1987 spin_lock(&txq->lock);
1988 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1989 ds = bf->desc;
1990
b47f407b 1991 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1992 if (unlikely(ret == -EINPROGRESS))
1993 break;
1994 else if (unlikely(ret)) {
1995 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1996 ret, txq->qnum);
1997 break;
1998 }
1999
2000 skb = bf->skb;
a888d52d 2001 info = IEEE80211_SKB_CB(skb);
fa1c114f 2002 bf->skb = NULL;
e039fa4a 2003
fa1c114f
JS		 2004 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2005 PCI_DMA_TODEVICE);
2006
e6a9854b 2007 ieee80211_tx_info_clear_status(info);
2f7fe870 2008 for (i = 0; i < 4; i++) {
e6a9854b
JB		 2009 struct ieee80211_tx_rate *r =
2010 &info->status.rates[i];
2f7fe870
FF		 2011
2012 if (ts.ts_rate[i]) {
e6a9854b
JB		 2013 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2014 r->count = ts.ts_retry[i];
2f7fe870 2015 } else {
e6a9854b
JB		 2016 r->idx = -1;
2017 r->count = 0;
2f7fe870
FF		 2018 }
2019 }
2020
e6a9854b
JB		 2021 /* count the successful attempt as well */
2022 info->status.rates[ts.ts_final_idx].count++;
2023
b47f407b 2024 if (unlikely(ts.ts_status)) {
fa1c114f 2025 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 2026 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 2027 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 2028 } else {
e039fa4a
JB		 2029 info->flags |= IEEE80211_TX_STAT_ACK;
2030 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2031 }
2032
e039fa4a 2033 ieee80211_tx_status(sc->hw, skb);
fa1c114f
JS		 2034
2035 spin_lock(&sc->txbuflock);
fa1c114f
JS		 2036 list_move_tail(&bf->list, &sc->txbuf);
2037 sc->txbuf_len++;
2038 spin_unlock(&sc->txbuflock);
2039 }
2040 if (likely(list_empty(&txq->q)))
2041 txq->link = NULL;
2042 spin_unlock(&txq->lock);
2043 if (sc->txbuf_len > ATH_TXBUF / 5)
2044 ieee80211_wake_queues(sc->hw);
2045}
2046
2047static void
2048ath5k_tasklet_tx(unsigned long data)
2049{
8784d2ee 2050 int i;
fa1c114f
JS		 2051 struct ath5k_softc *sc = (void *)data;
2052
8784d2ee
BC		 2053 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2054 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2055 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2056}
2057
2058
fa1c114f
JS		 2059/*****************\
2060* Beacon handling *
2061\*****************/
2062
2063/*
2064 * Setup the beacon frame for transmit.
2065 */
2066static int
e039fa4a 2067ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2068{
2069 struct sk_buff *skb = bf->skb;
a888d52d 2070 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2071 struct ath5k_hw *ah = sc->ah;
2072 struct ath5k_desc *ds;
2bed03eb
NK		 2073 int ret = 0;
2074 u8 antenna;
fa1c114f
JS		 2075 u32 flags;
2076
2077 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2078 PCI_DMA_TODEVICE);
2079 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2080 "skbaddr %llx\n", skb, skb->data, skb->len,
2081 (unsigned long long)bf->skbaddr);
8d8bb39b 2082 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2083 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2084 return -EIO;
2085 }
2086
2087 ds = bf->desc;
2bed03eb 2088 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2089
2090 flags = AR5K_TXDESC_NOACK;
05c914fe 2091 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2092 ds->ds_link = bf->daddr; /* self-linked */
2093 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2094 } else
fa1c114f 2095 ds->ds_link = 0;
2bed03eb
NK		 2096
2097 /*
2098 * If we use multiple antennas on AP and use
2099 * the Sectored AP scenario, switch antenna every
2100 * 4 beacons to make sure everybody hears our AP.
2101 * When a client tries to associate, hw will keep
2102 * track of the tx antenna to be used for this client
2103 * automaticaly, based on ACKed packets.
2104 *
2105 * Note: AP still listens and transmits RTS on the
2106 * default antenna which is supposed to be an omni.
2107 *
2108 * Note2: On sectored scenarios it's possible to have
2109 * multiple antennas (1omni -the default- and 14 sectors)
2110 * so if we choose to actually support this mode we need
2111 * to allow user to set how many antennas we have and tweak
2112 * the code below to send beacons on all of them.
2113 */
2114 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2115 antenna = sc->bsent & 4 ? 2 : 1;
2116
fa1c114f 2117
8f655dde
NK		 2118 /* FIXME: If we are in g mode and rate is a CCK rate
2119 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2120 * from tx power (value is in dB units already) */
fa1c114f 2121 ds->ds_data = bf->skbaddr;
281c56dd 2122 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2123 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2124 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2125 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2126 1, AR5K_TXKEYIX_INVALID,
400ec45a 2127 antenna, flags, 0, 0);
fa1c114f
JS		 2128 if (ret)
2129 goto err_unmap;
2130
2131 return 0;
2132err_unmap:
2133 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2134 return ret;
2135}
2136
2137/*
2138 * Transmit a beacon frame at SWBA. Dynamic updates to the
2139 * frame contents are done as needed and the slot time is
2140 * also adjusted based on current state.
2141 *
acf3c1a5
BC		 2142 * This is called from software irq context (beacontq or restq
2143 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2144 */
2145static void
2146ath5k_beacon_send(struct ath5k_softc *sc)
2147{
2148 struct ath5k_buf *bf = sc->bbuf;
2149 struct ath5k_hw *ah = sc->ah;
cec8db23 2150 struct sk_buff *skb;
fa1c114f 2151
be9b7259 2152 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2153
05c914fe
JB		 2154 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2155 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2156 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2157 return;
2158 }
2159 /*
2160 * Check if the previous beacon has gone out. If
2161 * not don't don't try to post another, skip this
2162 * period and wait for the next. Missed beacons
2163 * indicate a problem and should not occur. If we
2164 * miss too many consecutive beacons reset the device.
2165 */
2166 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2167 sc->bmisscount++;
be9b7259 2168 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2169 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2170 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2171 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2172 "stuck beacon time (%u missed)\n",
2173 sc->bmisscount);
2174 tasklet_schedule(&sc->restq);
2175 }
2176 return;
2177 }
2178 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2179 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2180 "resume beacon xmit after %u misses\n",
2181 sc->bmisscount);
2182 sc->bmisscount = 0;
2183 }
2184
2185 /*
2186 * Stop any current dma and put the new frame on the queue.
2187 * This should never fail since we check above that no frames
2188 * are still pending on the queue.
2189 */
2190 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2191 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2192 /* NB: hw still stops DMA, so proceed */
2193 }
fa1c114f 2194
1071db86
BC		 2195 /* refresh the beacon for AP mode */
2196 if (sc->opmode == NL80211_IFTYPE_AP)
2197 ath5k_beacon_update(sc->hw, sc->vif);
2198
c6e387a2
NK		 2199 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2200 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2201 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2202 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2203
cec8db23
BC		 2204 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2205 while (skb) {
2206 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2207 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2208 }
2209
fa1c114f
JS		 2210 sc->bsent++;
2211}
2212
2213
9804b98d
BR		 2214/**
2215 * ath5k_beacon_update_timers - update beacon timers
2216 *
2217 * @sc: struct ath5k_softc pointer we are operating on
2218 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2219 * beacon timer update based on the current HW TSF.
2220 *
2221 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2222 * of a received beacon or the current local hardware TSF and write it to the
2223 * beacon timer registers.
2224 *
2225 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2226 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2227 * when we otherwise know we have to update the timers, but we keep it in this
2228 * function to have it all together in one place.
2229 */
fa1c114f 2230static void
9804b98d 2231ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2232{
2233 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2234 u32 nexttbtt, intval, hw_tu, bc_tu;
2235 u64 hw_tsf;
fa1c114f
JS		 2236
2237 intval = sc->bintval & AR5K_BEACON_PERIOD;
2238 if (WARN_ON(!intval))
2239 return;
2240
9804b98d
BR		 2241 /* beacon TSF converted to TU */
2242 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2243
9804b98d
BR		 2244 /* current TSF converted to TU */
2245 hw_tsf = ath5k_hw_get_tsf64(ah);
2246 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2247
9804b98d
BR		 2248#define FUDGE 3
2249 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2250 if (bc_tsf == -1) {
2251 /*
2252 * no beacons received, called internally.
2253 * just need to refresh timers based on HW TSF.
2254 */
2255 nexttbtt = roundup(hw_tu + FUDGE, intval);
2256 } else if (bc_tsf == 0) {
2257 /*
2258 * no beacon received, probably called by ath5k_reset_tsf().
2259 * reset TSF to start with 0.
2260 */
2261 nexttbtt = intval;
2262 intval |= AR5K_BEACON_RESET_TSF;
2263 } else if (bc_tsf > hw_tsf) {
2264 /*
2265 * beacon received, SW merge happend but HW TSF not yet updated.
2266 * not possible to reconfigure timers yet, but next time we
2267 * receive a beacon with the same BSSID, the hardware will
2268 * automatically update the TSF and then we need to reconfigure
2269 * the timers.
2270 */
2271 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2272 "need to wait for HW TSF sync\n");
2273 return;
2274 } else {
2275 /*
2276 * most important case for beacon synchronization between STA.
2277 *
2278 * beacon received and HW TSF has been already updated by HW.
2279 * update next TBTT based on the TSF of the beacon, but make
2280 * sure it is ahead of our local TSF timer.
2281 */
2282 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2283 }
2284#undef FUDGE
fa1c114f 2285
036cd1ec
BR		 2286 sc->nexttbtt = nexttbtt;
2287
fa1c114f 2288 intval |= AR5K_BEACON_ENA;
fa1c114f 2289 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2290
2291 /*
2292 * debugging output last in order to preserve the time critical aspect
2293 * of this function
2294 */
2295 if (bc_tsf == -1)
2296 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2297 "reconfigured timers based on HW TSF\n");
2298 else if (bc_tsf == 0)
2299 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2300 "reset HW TSF and timers\n");
2301 else
2302 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2303 "updated timers based on beacon TSF\n");
2304
2305 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2306 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2307 (unsigned long long) bc_tsf,
2308 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2309 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2310 intval & AR5K_BEACON_PERIOD,
2311 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2312 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2313}
2314
2315
036cd1ec
BR		 2316/**
2317 * ath5k_beacon_config - Configure the beacon queues and interrupts
2318 *
2319 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2320 *
036cd1ec 2321 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2322 * interrupts to detect TSF updates only.
fa1c114f
JS		 2323 */
2324static void
2325ath5k_beacon_config(struct ath5k_softc *sc)
2326{
2327 struct ath5k_hw *ah = sc->ah;
b5f03956 2328 unsigned long flags;
fa1c114f 2329
21800491 2330 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2331 sc->bmisscount = 0;
dc1968e7 2332 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2333
21800491 2334 if (sc->enable_beacon) {
fa1c114f 2335 /*
036cd1ec
BR		 2336 * In IBSS mode we use a self-linked tx descriptor and let the
2337 * hardware send the beacons automatically. We have to load it
fa1c114f 2338 * only once here.
036cd1ec 2339 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2340 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2341 */
2342 ath5k_beaconq_config(sc);
fa1c114f 2343
036cd1ec
BR		 2344 sc->imask |= AR5K_INT_SWBA;
2345
da966bca 2346 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2347 if (ath5k_hw_hasveol(ah))
da966bca 2348 ath5k_beacon_send(sc);
da966bca
JS		 2349 } else
2350 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2351 } else {
2352 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2353 }
fa1c114f 2354
c6e387a2 2355 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2356 mmiowb();
2357 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2358}
2359
428cbd4f
NK		 2360static void ath5k_tasklet_beacon(unsigned long data)
2361{
2362 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2363
2364 /*
2365 * Software beacon alert--time to send a beacon.
2366 *
2367 * In IBSS mode we use this interrupt just to
2368 * keep track of the next TBTT (target beacon
2369 * transmission time) in order to detect wether
2370 * automatic TSF updates happened.
2371 */
2372 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2373 /* XXX: only if VEOL suppported */
2374 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2375 sc->nexttbtt += sc->bintval;
2376 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2377 "SWBA nexttbtt: %x hw_tu: %x "
2378 "TSF: %llx\n",
2379 sc->nexttbtt,
2380 TSF_TO_TU(tsf),
2381 (unsigned long long) tsf);
2382 } else {
2383 spin_lock(&sc->block);
2384 ath5k_beacon_send(sc);
2385 spin_unlock(&sc->block);
2386 }
2387}
2388
fa1c114f
JS		 2389
2390/********************\
2391* Interrupt handling *
2392\********************/
2393
2394static int
bb2becac 2395ath5k_init(struct ath5k_softc *sc)
fa1c114f 2396{
bc1b32d6
EO		 2397 struct ath5k_hw *ah = sc->ah;
2398 int ret, i;
fa1c114f
JS		 2399
2400 mutex_lock(&sc->lock);
2401
2402 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2403
2404 /*
2405 * Stop anything previously setup. This is safe
2406 * no matter this is the first time through or not.
2407 */
2408 ath5k_stop_locked(sc);
2409
242ab7ad
BC		 2410 /* Set PHY calibration interval */
2411 ah->ah_cal_intval = ath5k_calinterval;
2412
fa1c114f
JS		 2413 /*
2414 * The basic interface to setting the hardware in a good
2415 * state is ``reset''. On return the hardware is known to
2416 * be powered up and with interrupts disabled. This must
2417 * be followed by initialization of the appropriate bits
2418 * and then setup of the interrupt mask.
2419 */
d8ee398d
LR		 2420 sc->curchan = sc->hw->conf.channel;
2421 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2422 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2423 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
6e220662 2424 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
209d889b 2425 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2426 if (ret)
2427 goto done;
fa1c114f 2428
e6a3b616
TD		 2429 ath5k_rfkill_hw_start(ah);
2430
bc1b32d6
EO		 2431 /*
2432 * Reset the key cache since some parts do not reset the
2433 * contents on initial power up or resume from suspend.
2434 */
2435 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2436 ath5k_hw_reset_key(ah, i);
2437
fa1c114f 2438 /* Set ack to be sent at low bit-rates */
bc1b32d6 2439 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2440 ret = 0;
2441done:
274c7c36 2442 mmiowb();
fa1c114f
JS		 2443 mutex_unlock(&sc->lock);
2444 return ret;
2445}
2446
2447static int
2448ath5k_stop_locked(struct ath5k_softc *sc)
2449{
2450 struct ath5k_hw *ah = sc->ah;
2451
2452 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2453 test_bit(ATH_STAT_INVALID, sc->status));
2454
2455 /*
2456 * Shutdown the hardware and driver:
2457 * stop output from above
2458 * disable interrupts
2459 * turn off timers
2460 * turn off the radio
2461 * clear transmit machinery
2462 * clear receive machinery
2463 * drain and release tx queues
2464 * reclaim beacon resources
2465 * power down hardware
2466 *
2467 * Note that some of this work is not possible if the
2468 * hardware is gone (invalid).
2469 */
2470 ieee80211_stop_queues(sc->hw);
2471
2472 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2473 ath5k_led_off(sc);
c6e387a2 2474 ath5k_hw_set_imr(ah, 0);
274c7c36 2475 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2476 }
2477 ath5k_txq_cleanup(sc);
2478 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2479 ath5k_rx_stop(sc);
2480 ath5k_hw_phy_disable(ah);
2481 } else
2482 sc->rxlink = NULL;
2483
2484 return 0;
2485}
2486
2487/*
2488 * Stop the device, grabbing the top-level lock to protect
2489 * against concurrent entry through ath5k_init (which can happen
2490 * if another thread does a system call and the thread doing the
2491 * stop is preempted).
2492 */
2493static int
bb2becac 2494ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2495{
2496 int ret;
2497
2498 mutex_lock(&sc->lock);
2499 ret = ath5k_stop_locked(sc);
2500 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2501 /*
edd7fc70
NK		 2502 * Don't set the card in full sleep mode!
2503 *
2504 * a) When the device is in this state it must be carefully
2505 * woken up or references to registers in the PCI clock
2506 * domain may freeze the bus (and system). This varies
2507 * by chip and is mostly an issue with newer parts
2508 * (madwifi sources mentioned srev >= 0x78) that go to
2509 * sleep more quickly.
2510 *
2511 * b) On older chips full sleep results a weird behaviour
2512 * during wakeup. I tested various cards with srev < 0x78
2513 * and they don't wake up after module reload, a second
2514 * module reload is needed to bring the card up again.
2515 *
2516 * Until we figure out what's going on don't enable
2517 * full chip reset on any chip (this is what Legacy HAL
2518 * and Sam's HAL do anyway). Instead Perform a full reset
2519 * on the device (same as initial state after attach) and
2520 * leave it idle (keep MAC/BB on warm reset) */
2521 ret = ath5k_hw_on_hold(sc->ah);
2522
2523 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2524 "putting device to sleep\n");
fa1c114f
JS		 2525 }
2526 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2527
274c7c36 2528 mmiowb();
fa1c114f
JS		 2529 mutex_unlock(&sc->lock);
2530
10488f8a
JS		 2531 tasklet_kill(&sc->rxtq);
2532 tasklet_kill(&sc->txtq);
2533 tasklet_kill(&sc->restq);
6e220662 2534 tasklet_kill(&sc->calib);
acf3c1a5 2535 tasklet_kill(&sc->beacontq);
fa1c114f 2536
e6a3b616
TD		 2537 ath5k_rfkill_hw_stop(sc->ah);
2538
fa1c114f
JS		 2539 return ret;
2540}
2541
2542static irqreturn_t
2543ath5k_intr(int irq, void *dev_id)
2544{
2545 struct ath5k_softc *sc = dev_id;
2546 struct ath5k_hw *ah = sc->ah;
2547 enum ath5k_int status;
2548 unsigned int counter = 1000;
2549
2550 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2551 !ath5k_hw_is_intr_pending(ah)))
2552 return IRQ_NONE;
2553
2554 do {
fa1c114f
JS		 2555 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2556 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2557 status, sc->imask);
fa1c114f
JS		 2558 if (unlikely(status & AR5K_INT_FATAL)) {
2559 /*
2560 * Fatal errors are unrecoverable.
2561 * Typically these are caused by DMA errors.
2562 */
2563 tasklet_schedule(&sc->restq);
2564 } else if (unlikely(status & AR5K_INT_RXORN)) {
2565 tasklet_schedule(&sc->restq);
2566 } else {
2567 if (status & AR5K_INT_SWBA) {
56d2ac76 2568 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2569 }
2570 if (status & AR5K_INT_RXEOL) {
2571 /*
2572 * NB: the hardware should re-read the link when
2573 * RXE bit is written, but it doesn't work at
2574 * least on older hardware revs.
2575 */
2576 sc->rxlink = NULL;
2577 }
2578 if (status & AR5K_INT_TXURN) {
2579 /* bump tx trigger level */
2580 ath5k_hw_update_tx_triglevel(ah, true);
2581 }
4c674c60 2582 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2583 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2584 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2585 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2586 tasklet_schedule(&sc->txtq);
2587 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2588 /* TODO */
fa1c114f 2589 }
6e220662
NK		 2590 if (status & AR5K_INT_SWI) {
2591 tasklet_schedule(&sc->calib);
2592 }
fa1c114f 2593 if (status & AR5K_INT_MIB) {
194828a2
NK		 2594 /*
2595 * These stats are also used for ANI i think
2596 * so how about updating them more often ?
2597 */
2598 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f 2599 }
e6a3b616 2600 if (status & AR5K_INT_GPIO)
e6a3b616 2601 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2602
fa1c114f 2603 }
2516baa6 2604 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2605
2606 if (unlikely(!counter))
2607 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2608
6e220662
NK		 2609 ath5k_hw_calibration_poll(ah);
2610
fa1c114f
JS		 2611 return IRQ_HANDLED;
2612}
2613
2614static void
2615ath5k_tasklet_reset(unsigned long data)
2616{
2617 struct ath5k_softc *sc = (void *)data;
2618
d7dc1003 2619 ath5k_reset_wake(sc);
fa1c114f
JS		 2620}
2621
2622/*
2623 * Periodically recalibrate the PHY to account
2624 * for temperature/environment changes.
2625 */
2626static void
6e220662 2627ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2628{
2629 struct ath5k_softc *sc = (void *)data;
2630 struct ath5k_hw *ah = sc->ah;
2631
6e220662
NK		 2632 /* Only full calibration for now */
2633 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2634 return;
2635
2636 /* Stop queues so that calibration
2637 * doesn't interfere with tx */
2638 ieee80211_stop_queues(sc->hw);
2639
fa1c114f 2640 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2641 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2642 sc->curchan->hw_value);
fa1c114f 2643
6f3b414a 2644 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2645 /*
2646 * Rfgain is out of bounds, reset the chip
2647 * to load new gain values.
2648 */
2649 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2650 ath5k_reset_wake(sc);
fa1c114f
JS		 2651 }
2652 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2653 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2654 ieee80211_frequency_to_channel(
2655 sc->curchan->center_freq));
fa1c114f 2656
6e220662
NK		 2657 ah->ah_swi_mask = 0;
2658
2659 /* Wake queues */
2660 ieee80211_wake_queues(sc->hw);
2661
fa1c114f
JS		 2662}
2663
2664
fa1c114f
JS		 2665/********************\
2666* Mac80211 functions *
2667\********************/
2668
2669static int
e039fa4a 2670ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2671{
2672 struct ath5k_softc *sc = hw->priv;
2673
2674 return ath5k_tx_queue(hw, skb, sc->txq);
2675}
2676
2677static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2678 struct ath5k_txq *txq)
fa1c114f
JS		 2679{
2680 struct ath5k_softc *sc = hw->priv;
2681 struct ath5k_buf *bf;
2682 unsigned long flags;
2683 int hdrlen;
0fe45b1d 2684 int padsize;
fa1c114f
JS		 2685
2686 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2687
05c914fe 2688 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2689 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2690
2691 /*
2692 * the hardware expects the header padded to 4 byte boundaries
2693 * if this is not the case we add the padding after the header
2694 */
2695 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2696 padsize = ath5k_pad_size(hdrlen);
2697 if (padsize) {
0fe45b1d
BP		 2698
2699 if (skb_headroom(skb) < padsize) {
fa1c114f 2700 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2701 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2702 goto drop_packet;
fa1c114f 2703 }
0fe45b1d
BP		 2704 skb_push(skb, padsize);
2705 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2706 }
2707
fa1c114f
JS		 2708 spin_lock_irqsave(&sc->txbuflock, flags);
2709 if (list_empty(&sc->txbuf)) {
2710 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2711 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2712 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2713 goto drop_packet;
fa1c114f
JS		 2714 }
2715 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2716 list_del(&bf->list);
2717 sc->txbuf_len--;
2718 if (list_empty(&sc->txbuf))
2719 ieee80211_stop_queues(hw);
2720 spin_unlock_irqrestore(&sc->txbuflock, flags);
2721
2722 bf->skb = skb;
2723
cec8db23 2724 if (ath5k_txbuf_setup(sc, bf, txq)) {
fa1c114f
JS		 2725 bf->skb = NULL;
2726 spin_lock_irqsave(&sc->txbuflock, flags);
2727 list_add_tail(&bf->list, &sc->txbuf);
2728 sc->txbuf_len++;
2729 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2730 goto drop_packet;
fa1c114f 2731 }
5a0fe8ac 2732 return NETDEV_TX_OK;
fa1c114f 2733
5a0fe8ac
BC		 2734drop_packet:
2735 dev_kfree_skb_any(skb);
71ef99c8 2736 return NETDEV_TX_OK;
fa1c114f
JS		 2737}
2738
209d889b
BC		 2739/*
2740 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2741 * and change to the given channel.
2742 */
fa1c114f 2743static int
209d889b 2744ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2745{
fa1c114f
JS		 2746 struct ath5k_hw *ah = sc->ah;
2747 int ret;
2748
2749 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2750
209d889b 2751 if (chan) {
c6e387a2 2752 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2753 ath5k_txq_cleanup(sc);
2754 ath5k_rx_stop(sc);
209d889b
BC		 2755
2756 sc->curchan = chan;
2757 sc->curband = &sc->sbands[chan->band];
d7dc1003 2758 }
3355443a 2759 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2760 if (ret) {
fa1c114f
JS		 2761 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2762 goto err;
2763 }
d7dc1003 2764
fa1c114f 2765 ret = ath5k_rx_start(sc);
d7dc1003 2766 if (ret) {
fa1c114f
JS		 2767 ATH5K_ERR(sc, "can't start recv logic\n");
2768 goto err;
2769 }
d7dc1003 2770
fa1c114f 2771 /*
d7dc1003
JS		 2772 * Change channels and update the h/w rate map if we're switching;
2773 * e.g. 11a to 11b/g.
2774 *
2775 * We may be doing a reset in response to an ioctl that changes the
2776 * channel so update any state that might change as a result.
fa1c114f
JS		 2777 *
2778 * XXX needed?
2779 */
2780/* ath5k_chan_change(sc, c); */
fa1c114f 2781
d7dc1003
JS		 2782 ath5k_beacon_config(sc);
2783 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2784
2785 return 0;
2786err:
2787 return ret;
2788}
2789
d7dc1003
JS		 2790static int
2791ath5k_reset_wake(struct ath5k_softc *sc)
2792{
2793 int ret;
2794
209d889b 2795 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2796 if (!ret)
2797 ieee80211_wake_queues(sc->hw);
2798
2799 return ret;
2800}
2801
fa1c114f
JS		 2802static int ath5k_start(struct ieee80211_hw *hw)
2803{
bb2becac 2804 return ath5k_init(hw->priv);
fa1c114f
JS		 2805}
2806
2807static void ath5k_stop(struct ieee80211_hw *hw)
2808{
bb2becac 2809 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2810}
2811
2812static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2813 struct ieee80211_vif *vif)
fa1c114f
JS		 2814{
2815 struct ath5k_softc *sc = hw->priv;
2816 int ret;
2817
2818 mutex_lock(&sc->lock);
32bfd35d 2819 if (sc->vif) {
fa1c114f
JS		 2820 ret = 0;
2821 goto end;
2822 }
2823
1ed32e4f 2824 sc->vif = vif;
fa1c114f 2825
1ed32e4f 2826 switch (vif->type) {
da966bca 2827 case NL80211_IFTYPE_AP:
05c914fe
JB		 2828 case NL80211_IFTYPE_STATION:
2829 case NL80211_IFTYPE_ADHOC:
b706e65b 2830 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2831 case NL80211_IFTYPE_MONITOR:
1ed32e4f 2832 sc->opmode = vif->type;
fa1c114f
JS		 2833 break;
2834 default:
2835 ret = -EOPNOTSUPP;
2836 goto end;
2837 }
67d2e2df 2838
1ed32e4f 2839 ath5k_hw_set_lladdr(sc->ah, vif->addr);
ae6f53f2 2840 ath5k_mode_setup(sc);
67d2e2df 2841
fa1c114f
JS		 2842 ret = 0;
2843end:
2844 mutex_unlock(&sc->lock);
2845 return ret;
2846}
2847
2848static void
2849ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 2850 struct ieee80211_vif *vif)
fa1c114f
JS		 2851{
2852 struct ath5k_softc *sc = hw->priv;
0e149cf5 2853 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2854
2855 mutex_lock(&sc->lock);
1ed32e4f 2856 if (sc->vif != vif)
fa1c114f
JS		 2857 goto end;
2858
0e149cf5 2859 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2860 sc->vif = NULL;
fa1c114f
JS		 2861end:
2862 mutex_unlock(&sc->lock);
2863}
2864
d8ee398d
LR		 2865/*
2866 * TODO: Phy disable/diversity etc
2867 */
fa1c114f 2868static int
e8975581 2869ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2870{
2871 struct ath5k_softc *sc = hw->priv;
a0823810 2872 struct ath5k_hw *ah = sc->ah;
e8975581 2873 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 2874 int ret = 0;
be009370
BC		 2875
2876 mutex_lock(&sc->lock);
fa1c114f 2877
e30eb4ab
JA		 2878 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2879 ret = ath5k_chan_set(sc, conf->channel);
2880 if (ret < 0)
2881 goto unlock;
2882 }
2bed03eb 2883
a0823810
NK		 2884 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2885 (sc->power_level != conf->power_level)) {
2886 sc->power_level = conf->power_level;
2887
2888 /* Half dB steps */
2889 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2890 }
fa1c114f 2891
2bed03eb
NK		 2892 /* TODO:
2893 * 1) Move this on config_interface and handle each case
2894 * separately eg. when we have only one STA vif, use
2895 * AR5K_ANTMODE_SINGLE_AP
2896 *
2897 * 2) Allow the user to change antenna mode eg. when only
2898 * one antenna is present
2899 *
2900 * 3) Allow the user to set default/tx antenna when possible
2901 *
2902 * 4) Default mode should handle 90% of the cases, together
2903 * with fixed a/b and single AP modes we should be able to
2904 * handle 99%. Sectored modes are extreme cases and i still
2905 * haven't found a usage for them. If we decide to support them,
2906 * then we must allow the user to set how many tx antennas we
2907 * have available
2908 */
2909 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
be009370 2910
55aa4e0f 2911unlock:
be009370 2912 mutex_unlock(&sc->lock);
55aa4e0f 2913 return ret;
fa1c114f
JS		 2914}
2915
3ac64bee
JB		 2916static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2917 int mc_count, struct dev_addr_list *mclist)
2918{
2919 u32 mfilt[2], val;
2920 int i;
2921 u8 pos;
2922
2923 mfilt[0] = 0;
2924 mfilt[1] = 1;
2925
2926 for (i = 0; i < mc_count; i++) {
2927 if (!mclist)
2928 break;
2929 /* calculate XOR of eight 6-bit values */
2930 val = get_unaligned_le32(mclist->dmi_addr + 0);
2931 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2932 val = get_unaligned_le32(mclist->dmi_addr + 3);
2933 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2934 pos &= 0x3f;
2935 mfilt[pos / 32] |= (1 << (pos % 32));
2936 /* XXX: we might be able to just do this instead,
2937 * but not sure, needs testing, if we do use this we'd
2938 * neet to inform below to not reset the mcast */
2939 /* ath5k_hw_set_mcast_filterindex(ah,
2940 * mclist->dmi_addr[5]); */
2941 mclist = mclist->next;
2942 }
2943
2944 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2945}
2946
fa1c114f
JS		 2947#define SUPPORTED_FIF_FLAGS \
2948 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2949 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2950 FIF_BCN_PRBRESP_PROMISC
2951/*
2952 * o always accept unicast, broadcast, and multicast traffic
2953 * o multicast traffic for all BSSIDs will be enabled if mac80211
2954 * says it should be
2955 * o maintain current state of phy ofdm or phy cck error reception.
2956 * If the hardware detects any of these type of errors then
2957 * ath5k_hw_get_rx_filter() will pass to us the respective
2958 * hardware filters to be able to receive these type of frames.
2959 * o probe request frames are accepted only when operating in
2960 * hostap, adhoc, or monitor modes
2961 * o enable promiscuous mode according to the interface state
2962 * o accept beacons:
2963 * - when operating in adhoc mode so the 802.11 layer creates
2964 * node table entries for peers,
2965 * - when operating in station mode for collecting rssi data when
2966 * the station is otherwise quiet, or
2967 * - when scanning
2968 */
2969static void ath5k_configure_filter(struct ieee80211_hw *hw,
2970 unsigned int changed_flags,
2971 unsigned int *new_flags,
3ac64bee 2972 u64 multicast)
fa1c114f
JS		 2973{
2974 struct ath5k_softc *sc = hw->priv;
2975 struct ath5k_hw *ah = sc->ah;
3ac64bee 2976 u32 mfilt[2], rfilt;
fa1c114f 2977
56d1de0a
BC		 2978 mutex_lock(&sc->lock);
2979
3ac64bee
JB		 2980 mfilt[0] = multicast;
2981 mfilt[1] = multicast >> 32;
fa1c114f
JS		 2982
2983 /* Only deal with supported flags */
2984 changed_flags &= SUPPORTED_FIF_FLAGS;
2985 *new_flags &= SUPPORTED_FIF_FLAGS;
2986
2987 /* If HW detects any phy or radar errors, leave those filters on.
2988 * Also, always enable Unicast, Broadcasts and Multicast
2989 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2990 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2991 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2992 AR5K_RX_FILTER_MCAST);
2993
2994 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2995 if (*new_flags & FIF_PROMISC_IN_BSS) {
2996 rfilt |= AR5K_RX_FILTER_PROM;
2997 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2998 } else {
fa1c114f 2999 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3000 }
fa1c114f
JS		 3001 }
3002
3003 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3004 if (*new_flags & FIF_ALLMULTI) {
3005 mfilt[0] = ~0;
3006 mfilt[1] = ~0;
fa1c114f
JS		 3007 }
3008
3009 /* This is the best we can do */
3010 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3011 rfilt |= AR5K_RX_FILTER_PHYERR;
3012
3013 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3014 * and probes for any BSSID, this needs testing */
3015 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3016 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3017
3018 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3019 * set we should only pass on control frames for this
3020 * station. This needs testing. I believe right now this
3021 * enables *all* control frames, which is OK.. but
3022 * but we should see if we can improve on granularity */
3023 if (*new_flags & FIF_CONTROL)
3024 rfilt |= AR5K_RX_FILTER_CONTROL;
3025
3026 /* Additional settings per mode -- this is per ath5k */
3027
3028 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3029
56d1de0a
BC		 3030 switch (sc->opmode) {
3031 case NL80211_IFTYPE_MESH_POINT:
3032 case NL80211_IFTYPE_MONITOR:
3033 rfilt |= AR5K_RX_FILTER_CONTROL |
3034 AR5K_RX_FILTER_BEACON |
3035 AR5K_RX_FILTER_PROBEREQ |
3036 AR5K_RX_FILTER_PROM;
3037 break;
3038 case NL80211_IFTYPE_AP:
3039 case NL80211_IFTYPE_ADHOC:
3040 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3041 AR5K_RX_FILTER_BEACON;
3042 break;
3043 case NL80211_IFTYPE_STATION:
3044 if (sc->assoc)
3045 rfilt |= AR5K_RX_FILTER_BEACON;
3046 default:
3047 break;
3048 }
fa1c114f
JS		 3049
3050 /* Set filters */
0bbac08f 3051 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3052
3053 /* Set multicast bits */
3054 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3055 /* Set the cached hw filter flags, this will alter actually
3056 * be set in HW */
3057 sc->filter_flags = rfilt;
56d1de0a
BC		 3058
3059 mutex_unlock(&sc->lock);
fa1c114f
JS		 3060}
3061
3062static int
3063ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3064 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3065 struct ieee80211_key_conf *key)
fa1c114f
JS		 3066{
3067 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3068 struct ath5k_hw *ah = sc->ah;
3069 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3070 int ret = 0;
3071
9ad9a26e
BC		 3072 if (modparam_nohwcrypt)
3073 return -EOPNOTSUPP;
3074
65b5a698
BC		 3075 if (sc->opmode == NL80211_IFTYPE_AP)
3076 return -EOPNOTSUPP;
3077
0bbac08f 3078 switch (key->alg) {
fa1c114f 3079 case ALG_WEP:
fa1c114f 3080 case ALG_TKIP:
3f64b435 3081 break;
fa1c114f 3082 case ALG_CCMP:
1c818740
BC		 3083 if (sc->ah->ah_aes_support)
3084 break;
3085
fa1c114f
JS		 3086 return -EOPNOTSUPP;
3087 default:
3088 WARN_ON(1);
3089 return -EINVAL;
3090 }
3091
3092 mutex_lock(&sc->lock);
3093
3094 switch (cmd) {
3095 case SET_KEY:
dc822b5d
JB		 3096 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3097 sta ? sta->addr : NULL);
fa1c114f
JS		 3098 if (ret) {
3099 ATH5K_ERR(sc, "can't set the key\n");
3100 goto unlock;
3101 }
dc1e001b 3102 __set_bit(key->keyidx, common->keymap);
fa1c114f 3103 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3104 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3105 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3106 break;
3107 case DISABLE_KEY:
3108 ath5k_hw_reset_key(sc->ah, key->keyidx);
dc1e001b 3109 __clear_bit(key->keyidx, common->keymap);
fa1c114f
JS		 3110 break;
3111 default:
3112 ret = -EINVAL;
3113 goto unlock;
3114 }
3115
3116unlock:
274c7c36 3117 mmiowb();
fa1c114f
JS		 3118 mutex_unlock(&sc->lock);
3119 return ret;
3120}
3121
3122static int
3123ath5k_get_stats(struct ieee80211_hw *hw,
3124 struct ieee80211_low_level_stats *stats)
3125{
3126 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3127 struct ath5k_hw *ah = sc->ah;
3128
3129 /* Force update */
3130 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3131
3132 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3133
3134 return 0;
3135}
3136
fa1c114f
JS		 3137static u64
3138ath5k_get_tsf(struct ieee80211_hw *hw)
3139{
3140 struct ath5k_softc *sc = hw->priv;
3141
3142 return ath5k_hw_get_tsf64(sc->ah);
3143}
3144
3b5d665b
AF		 3145static void
3146ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3147{
3148 struct ath5k_softc *sc = hw->priv;
3149
3150 ath5k_hw_set_tsf64(sc->ah, tsf);
3151}
3152
fa1c114f
JS		 3153static void
3154ath5k_reset_tsf(struct ieee80211_hw *hw)
3155{
3156 struct ath5k_softc *sc = hw->priv;
3157
9804b98d
BR		 3158 /*
3159 * in IBSS mode we need to update the beacon timers too.
3160 * this will also reset the TSF if we call it with 0
3161 */
05c914fe 3162 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3163 ath5k_beacon_update_timers(sc, 0);
3164 else
3165 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3166}
3167
1071db86
BC		 3168/*
3169 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3170 * this is called only once at config_bss time, for AP we do it every
3171 * SWBA interrupt so that the TIM will reflect buffered frames.
3172 *
3173 * Called with the beacon lock.
3174 */
fa1c114f 3175static int
1071db86 3176ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3177{
fa1c114f 3178 int ret;
1071db86 3179 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3180 struct sk_buff *skb;
3181
3182 if (WARN_ON(!vif)) {
3183 ret = -EINVAL;
3184 goto out;
3185 }
3186
3187 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3188
3189 if (!skb) {
3190 ret = -ENOMEM;
3191 goto out;
3192 }
fa1c114f
JS		 3193
3194 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3195
fa1c114f
JS		 3196 ath5k_txbuf_free(sc, sc->bbuf);
3197 sc->bbuf->skb = skb;
e039fa4a 3198 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3199 if (ret)
3200 sc->bbuf->skb = NULL;
1071db86
BC		 3201out:
3202 return ret;
3203}
3204
02969b38
MX		 3205static void
3206set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3207{
3208 struct ath5k_softc *sc = hw->priv;
3209 struct ath5k_hw *ah = sc->ah;
3210 u32 rfilt;
3211 rfilt = ath5k_hw_get_rx_filter(ah);
3212 if (enable)
3213 rfilt |= AR5K_RX_FILTER_BEACON;
3214 else
3215 rfilt &= ~AR5K_RX_FILTER_BEACON;
3216 ath5k_hw_set_rx_filter(ah, rfilt);
3217 sc->filter_flags = rfilt;
3218}
fa1c114f 3219
02969b38
MX		 3220static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3221 struct ieee80211_vif *vif,
3222 struct ieee80211_bss_conf *bss_conf,
3223 u32 changes)
3224{
3225 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3226 struct ath5k_hw *ah = sc->ah;
954fecea 3227 struct ath_common *common = ath5k_hw_common(ah);
21800491 3228 unsigned long flags;
2d0ddec5
JB		 3229
3230 mutex_lock(&sc->lock);
3231 if (WARN_ON(sc->vif != vif))
3232 goto unlock;
3233
3234 if (changes & BSS_CHANGED_BSSID) {
3235 /* Cache for later use during resets */
954fecea 3236 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
8ce54c5a 3237 common->curaid = 0;
be5d6b75 3238 ath5k_hw_set_associd(ah);
2d0ddec5
JB		 3239 mmiowb();
3240 }
57c4d7b4
JB		 3241
3242 if (changes & BSS_CHANGED_BEACON_INT)
3243 sc->bintval = bss_conf->beacon_int;
3244
02969b38 3245 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3246 sc->assoc = bss_conf->assoc;
3247 if (sc->opmode == NL80211_IFTYPE_STATION)
3248 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3249 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3250 AR5K_LED_ASSOC : AR5K_LED_INIT);
8ce54c5a
LR		 3251 if (bss_conf->assoc) {
3252 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3253 "Bss Info ASSOC %d, bssid: %pM\n",
3254 bss_conf->aid, common->curbssid);
3255 common->curaid = bss_conf->aid;
3256 ath5k_hw_set_associd(ah);
3257 /* Once ANI is available you would start it here */
3258 }
02969b38 3259 }
2d0ddec5 3260
21800491
BC		 3261 if (changes & BSS_CHANGED_BEACON) {
3262 spin_lock_irqsave(&sc->block, flags);
3263 ath5k_beacon_update(hw, vif);
3264 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3265 }
3266
21800491
BC		 3267 if (changes & BSS_CHANGED_BEACON_ENABLED)
3268 sc->enable_beacon = bss_conf->enable_beacon;
3269
3270 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3271 BSS_CHANGED_BEACON_INT))
3272 ath5k_beacon_config(sc);
3273
2d0ddec5
JB		 3274 unlock:
3275 mutex_unlock(&sc->lock);
02969b38 3276}
f0f3d388
BC		 3277
3278static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3279{
3280 struct ath5k_softc *sc = hw->priv;
3281 if (!sc->assoc)
3282 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3283}
3284
3285static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3286{
3287 struct ath5k_softc *sc = hw->priv;
3288 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3289 AR5K_LED_ASSOC : AR5K_LED_INIT);
3290}
6e08d228
LT		 3291
3292/**
3293 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3294 *
3295 * @hw: struct ieee80211_hw pointer
3296 * @coverage_class: IEEE 802.11 coverage class number
3297 *
3298 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3299 * coverage class. The values are persistent, they are restored after device
3300 * reset.
3301 */
3302static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3303{
3304 struct ath5k_softc *sc = hw->priv;
3305
3306 mutex_lock(&sc->lock);
3307 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3308 mutex_unlock(&sc->lock);
3309}
Clone of davem's net-next-2.6 tree