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Merge branch 'ebt_config_compat_v4' of git://git.breakpoint.cc/fw/nf-next-2.6
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
6e220662 62static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e 63static int modparam_nohwcrypt;
46802a4f 64module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 66
42639fcd 67static int modparam_all_channels;
46802a4f 68module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 69MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
fa1c114f
JS		 71
72/******************\
73* Internal defines *
74\******************/
75
76/* Module info */
77MODULE_AUTHOR("Jiri Slaby");
78MODULE_AUTHOR("Nick Kossifidis");
79MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 82MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 83
84
85/* Known PCI ids */
a3aa1884 86static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 105 { 0 }
106};
107MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109/* Known SREVs */
2c91108c 110static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147};
148
2c91108c 149static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189};
190
fa1c114f
JS		 191/*
192 * Prototypes - PCI stack related functions
193 */
194static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197#ifdef CONFIG_PM
baee1f3c
RW		 198static int ath5k_pci_suspend(struct device *dev);
199static int ath5k_pci_resume(struct device *dev);
200
201SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202#define ATH5K_PM_OPS (&ath5k_pm_ops)
fa1c114f 203#else
baee1f3c 204#define ATH5K_PM_OPS NULL
fa1c114f
JS		 205#endif /* CONFIG_PM */
206
04a9e451 207static struct pci_driver ath5k_pci_driver = {
9764f3f9 208 .name = KBUILD_MODNAME,
fa1c114f
JS		 209 .id_table = ath5k_pci_id_table,
210 .probe = ath5k_pci_probe,
211 .remove = __devexit_p(ath5k_pci_remove),
baee1f3c 212 .driver.pm = ATH5K_PM_OPS,
fa1c114f
JS		 213};
214
215
216
217/*
218 * Prototypes - MAC 802.11 stack related functions
219 */
e039fa4a 220static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 221static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
209d889b 223static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 224static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 225static int ath5k_start(struct ieee80211_hw *hw);
226static void ath5k_stop(struct ieee80211_hw *hw);
227static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 228 struct ieee80211_vif *vif);
fa1c114f 229static void ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 230 struct ieee80211_vif *vif);
e8975581 231static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee
JB		 232static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
fa1c114f
JS		 234static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
3ac64bee 237 u64 multicast);
fa1c114f
JS		 238static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
dc822b5d 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 241 struct ieee80211_key_conf *key);
242static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
fa1c114f 244static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 245static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 246static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 247static int ath5k_beacon_update(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif);
02969b38
MX		 249static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif,
251 struct ieee80211_bss_conf *bss_conf,
252 u32 changes);
f0f3d388
BC		 253static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
254static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
6e08d228
LT		 255static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
256 u8 coverage_class);
fa1c114f 257
2c91108c 258static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 259 .tx = ath5k_tx,
260 .start = ath5k_start,
261 .stop = ath5k_stop,
262 .add_interface = ath5k_add_interface,
263 .remove_interface = ath5k_remove_interface,
264 .config = ath5k_config,
3ac64bee 265 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 266 .configure_filter = ath5k_configure_filter,
267 .set_key = ath5k_set_key,
268 .get_stats = ath5k_get_stats,
269 .conf_tx = NULL,
fa1c114f 270 .get_tsf = ath5k_get_tsf,
3b5d665b 271 .set_tsf = ath5k_set_tsf,
fa1c114f 272 .reset_tsf = ath5k_reset_tsf,
02969b38 273 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 274 .sw_scan_start = ath5k_sw_scan_start,
275 .sw_scan_complete = ath5k_sw_scan_complete,
6e08d228 276 .set_coverage_class = ath5k_set_coverage_class,
fa1c114f
JS		 277};
278
279/*
280 * Prototypes - Internal functions
281 */
282/* Attach detach */
283static int ath5k_attach(struct pci_dev *pdev,
284 struct ieee80211_hw *hw);
285static void ath5k_detach(struct pci_dev *pdev,
286 struct ieee80211_hw *hw);
287/* Channel/mode setup */
288static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 289static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
290 struct ieee80211_channel *channels,
291 unsigned int mode,
292 unsigned int max);
63266a65 293static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 294static int ath5k_chan_set(struct ath5k_softc *sc,
295 struct ieee80211_channel *chan);
296static void ath5k_setcurmode(struct ath5k_softc *sc,
297 unsigned int mode);
298static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 299
fa1c114f
JS		 300/* Descriptor setup */
301static int ath5k_desc_alloc(struct ath5k_softc *sc,
302 struct pci_dev *pdev);
303static void ath5k_desc_free(struct ath5k_softc *sc,
304 struct pci_dev *pdev);
305/* Buffers setup */
306static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
307 struct ath5k_buf *bf);
308static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23
BC		 309 struct ath5k_buf *bf,
310 struct ath5k_txq *txq);
fa1c114f
JS		 311static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
312 struct ath5k_buf *bf)
313{
314 BUG_ON(!bf);
315 if (!bf->skb)
316 return;
317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
318 PCI_DMA_TODEVICE);
00482973 319 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 320 bf->skb = NULL;
321}
322
a6c8d375
FF		 323static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
324 struct ath5k_buf *bf)
325{
cc861f74
LR		 326 struct ath5k_hw *ah = sc->ah;
327 struct ath_common *common = ath5k_hw_common(ah);
328
a6c8d375
FF		 329 BUG_ON(!bf);
330 if (!bf->skb)
331 return;
cc861f74 332 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 333 PCI_DMA_FROMDEVICE);
334 dev_kfree_skb_any(bf->skb);
335 bf->skb = NULL;
336}
337
338
fa1c114f
JS		 339/* Queues setup */
340static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
341 int qtype, int subtype);
342static int ath5k_beaconq_setup(struct ath5k_hw *ah);
343static int ath5k_beaconq_config(struct ath5k_softc *sc);
344static void ath5k_txq_drainq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346static void ath5k_txq_cleanup(struct ath5k_softc *sc);
347static void ath5k_txq_release(struct ath5k_softc *sc);
348/* Rx handling */
349static int ath5k_rx_start(struct ath5k_softc *sc);
350static void ath5k_rx_stop(struct ath5k_softc *sc);
351static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
352 struct ath5k_desc *ds,
b47f407b
BR		 353 struct sk_buff *skb,
354 struct ath5k_rx_status *rs);
fa1c114f
JS		 355static void ath5k_tasklet_rx(unsigned long data);
356/* Tx handling */
357static void ath5k_tx_processq(struct ath5k_softc *sc,
358 struct ath5k_txq *txq);
359static void ath5k_tasklet_tx(unsigned long data);
360/* Beacon handling */
361static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 362 struct ath5k_buf *bf);
fa1c114f
JS		 363static void ath5k_beacon_send(struct ath5k_softc *sc);
364static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 365static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 366static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 367
368static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
369{
370 u64 tsf = ath5k_hw_get_tsf64(ah);
371
372 if ((tsf & 0x7fff) < rstamp)
373 tsf -= 0x8000;
374
375 return (tsf & ~0x7fff) | rstamp;
376}
377
378/* Interrupt handling */
bb2becac 379static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 380static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 381static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 382static irqreturn_t ath5k_intr(int irq, void *dev_id);
383static void ath5k_tasklet_reset(unsigned long data);
384
6e220662 385static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 386
387/*
388 * Module init/exit functions
389 */
390static int __init
391init_ath5k_pci(void)
392{
393 int ret;
394
395 ath5k_debug_init();
396
04a9e451 397 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 398 if (ret) {
399 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
400 return ret;
401 }
402
403 return 0;
404}
405
406static void __exit
407exit_ath5k_pci(void)
408{
04a9e451 409 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 410
411 ath5k_debug_finish();
412}
413
414module_init(init_ath5k_pci);
415module_exit(exit_ath5k_pci);
416
417
418/********************\
419* PCI Initialization *
420\********************/
421
422static const char *
423ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
424{
425 const char *name = "xxxxx";
426 unsigned int i;
427
428 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
429 if (srev_names[i].sr_type != type)
430 continue;
75d0edb8
NK		 431
432 if ((val & 0xf0) == srev_names[i].sr_val)
433 name = srev_names[i].sr_name;
434
435 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 436 name = srev_names[i].sr_name;
437 break;
438 }
439 }
440
441 return name;
442}
e5aa8474
LR		 443static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
444{
445 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
446 return ath5k_hw_reg_read(ah, reg_offset);
447}
448
449static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
450{
451 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
452 ath5k_hw_reg_write(ah, val, reg_offset);
453}
454
455static const struct ath_ops ath5k_common_ops = {
456 .read = ath5k_ioread32,
457 .write = ath5k_iowrite32,
458};
fa1c114f
JS		 459
460static int __devinit
461ath5k_pci_probe(struct pci_dev *pdev,
462 const struct pci_device_id *id)
463{
464 void __iomem *mem;
465 struct ath5k_softc *sc;
db719718 466 struct ath_common *common;
fa1c114f
JS		 467 struct ieee80211_hw *hw;
468 int ret;
469 u8 csz;
470
471 ret = pci_enable_device(pdev);
472 if (ret) {
473 dev_err(&pdev->dev, "can't enable device\n");
474 goto err;
475 }
476
477 /* XXX 32-bit addressing only */
284901a9 478 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 479 if (ret) {
480 dev_err(&pdev->dev, "32-bit DMA not available\n");
481 goto err_dis;
482 }
483
484 /*
485 * Cache line size is used to size and align various
486 * structures used to communicate with the hardware.
487 */
488 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
489 if (csz == 0) {
490 /*
491 * Linux 2.4.18 (at least) writes the cache line size
492 * register as a 16-bit wide register which is wrong.
493 * We must have this setup properly for rx buffer
494 * DMA to work so force a reasonable value here if it
495 * comes up zero.
496 */
13311b00 497 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 498 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
499 }
500 /*
501 * The default setting of latency timer yields poor results,
502 * set it to the value used by other systems. It may be worth
503 * tweaking this setting more.
504 */
505 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
506
507 /* Enable bus mastering */
508 pci_set_master(pdev);
509
510 /*
511 * Disable the RETRY_TIMEOUT register (0x41) to keep
512 * PCI Tx retries from interfering with C3 CPU state.
513 */
514 pci_write_config_byte(pdev, 0x41, 0);
515
516 ret = pci_request_region(pdev, 0, "ath5k");
517 if (ret) {
518 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
519 goto err_dis;
520 }
521
522 mem = pci_iomap(pdev, 0, 0);
523 if (!mem) {
524 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
525 ret = -EIO;
526 goto err_reg;
527 }
528
529 /*
530 * Allocate hw (mac80211 main struct)
531 * and hw->priv (driver private data)
532 */
533 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
534 if (hw == NULL) {
535 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
536 ret = -ENOMEM;
537 goto err_map;
538 }
539
540 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
541
542 /* Initialize driver private data */
543 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 544 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 545 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 546 IEEE80211_HW_SIGNAL_DBM |
547 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 548
549 hw->wiphy->interface_modes =
6f5f39c9 550 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 551 BIT(NL80211_IFTYPE_STATION) |
552 BIT(NL80211_IFTYPE_ADHOC) |
553 BIT(NL80211_IFTYPE_MESH_POINT);
554
fa1c114f
JS		 555 hw->extra_tx_headroom = 2;
556 hw->channel_change_time = 5000;
fa1c114f
JS		 557 sc = hw->priv;
558 sc->hw = hw;
559 sc->pdev = pdev;
560
561 ath5k_debug_init_device(sc);
562
563 /*
564 * Mark the device as detached to avoid processing
565 * interrupts until setup is complete.
566 */
567 __set_bit(ATH_STAT_INVALID, sc->status);
568
569 sc->iobase = mem; /* So we can unmap it on detach */
05c914fe 570 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 571 sc->bintval = 1000;
fa1c114f
JS		 572 mutex_init(&sc->lock);
573 spin_lock_init(&sc->rxbuflock);
574 spin_lock_init(&sc->txbuflock);
00482973 575 spin_lock_init(&sc->block);
fa1c114f
JS		 576
577 /* Set private data */
578 pci_set_drvdata(pdev, hw);
579
fa1c114f
JS		 580 /* Setup interrupt handler */
581 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
582 if (ret) {
583 ATH5K_ERR(sc, "request_irq failed\n");
584 goto err_free;
585 }
586
9adca126
LR		 587 /*If we passed the test malloc a ath5k_hw struct*/
588 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
589 if (!sc->ah) {
590 ret = -ENOMEM;
591 ATH5K_ERR(sc, "out of memory\n");
fa1c114f
JS		 592 goto err_irq;
593 }
594
9adca126
LR		 595 sc->ah->ah_sc = sc;
596 sc->ah->ah_iobase = sc->iobase;
db719718 597 common = ath5k_hw_common(sc->ah);
e5aa8474 598 common->ops = &ath5k_common_ops;
13b81559 599 common->ah = sc->ah;
b002a4a9 600 common->hw = hw;
db719718
LR		 601 common->cachelsz = csz << 2; /* convert to bytes */
602
9adca126
LR		 603 /* Initialize device */
604 ret = ath5k_hw_attach(sc);
605 if (ret) {
606 goto err_free_ah;
607 }
608
2f7fe870
FF		 609 /* set up multi-rate retry capabilities */
610 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 611 hw->max_rates = 4;
612 hw->max_rate_tries = 11;
2f7fe870
FF		 613 }
614
fa1c114f
JS		 615 /* Finish private driver data initialization */
616 ret = ath5k_attach(pdev, hw);
617 if (ret)
618 goto err_ah;
619
620 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 621 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 622 sc->ah->ah_mac_srev,
623 sc->ah->ah_phy_revision);
624
400ec45a 625 if (!sc->ah->ah_single_chip) {
fa1c114f 626 /* Single chip radio (!RF5111) */
400ec45a
LR		 627 if (sc->ah->ah_radio_5ghz_revision &&
628 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 629 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 630 if (!test_bit(AR5K_MODE_11A,
631 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 632 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 633 ath5k_chip_name(AR5K_VERSION_RAD,
634 sc->ah->ah_radio_5ghz_revision),
635 sc->ah->ah_radio_5ghz_revision);
636 /* No 2GHz support (5110 and some
637 * 5Ghz only cards) -> report 5Ghz radio */
638 } else if (!test_bit(AR5K_MODE_11B,
639 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 640 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 641 ath5k_chip_name(AR5K_VERSION_RAD,
642 sc->ah->ah_radio_5ghz_revision),
643 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 644 /* Multiband radio */
645 } else {
646 ATH5K_INFO(sc, "RF%s multiband radio found"
647 " (0x%x)\n",
400ec45a
LR		 648 ath5k_chip_name(AR5K_VERSION_RAD,
649 sc->ah->ah_radio_5ghz_revision),
650 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 651 }
652 }
400ec45a
LR		 653 /* Multi chip radio (RF5111 - RF2111) ->
654 * report both 2GHz/5GHz radios */
655 else if (sc->ah->ah_radio_5ghz_revision &&
656 sc->ah->ah_radio_2ghz_revision){
fa1c114f 657 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 658 ath5k_chip_name(AR5K_VERSION_RAD,
659 sc->ah->ah_radio_5ghz_revision),
660 sc->ah->ah_radio_5ghz_revision);
fa1c114f 661 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 662 ath5k_chip_name(AR5K_VERSION_RAD,
663 sc->ah->ah_radio_2ghz_revision),
664 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 665 }
666 }
667
668
669 /* ready to process interrupts */
670 __clear_bit(ATH_STAT_INVALID, sc->status);
671
672 return 0;
673err_ah:
674 ath5k_hw_detach(sc->ah);
675err_irq:
676 free_irq(pdev->irq, sc);
9adca126
LR		 677err_free_ah:
678 kfree(sc->ah);
fa1c114f 679err_free:
fa1c114f
JS		 680 ieee80211_free_hw(hw);
681err_map:
682 pci_iounmap(pdev, mem);
683err_reg:
684 pci_release_region(pdev, 0);
685err_dis:
686 pci_disable_device(pdev);
687err:
688 return ret;
689}
690
691static void __devexit
692ath5k_pci_remove(struct pci_dev *pdev)
693{
694 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
695 struct ath5k_softc *sc = hw->priv;
696
697 ath5k_debug_finish_device(sc);
698 ath5k_detach(pdev, hw);
699 ath5k_hw_detach(sc->ah);
9adca126 700 kfree(sc->ah);
fa1c114f 701 free_irq(pdev->irq, sc);
fa1c114f
JS		 702 pci_iounmap(pdev, sc->iobase);
703 pci_release_region(pdev, 0);
704 pci_disable_device(pdev);
705 ieee80211_free_hw(hw);
706}
707
708#ifdef CONFIG_PM
baee1f3c 709static int ath5k_pci_suspend(struct device *dev)
fa1c114f 710{
baee1f3c 711 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
fa1c114f
JS		 712 struct ath5k_softc *sc = hw->priv;
713
3a078876 714 ath5k_led_off(sc);
fa1c114f
JS		 715 return 0;
716}
717
baee1f3c 718static int ath5k_pci_resume(struct device *dev)
fa1c114f 719{
baee1f3c 720 struct pci_dev *pdev = to_pci_dev(dev);
fa1c114f
JS		 721 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
722 struct ath5k_softc *sc = hw->priv;
fa1c114f 723
8451d22d
JM		 724 /*
725 * Suspend/Resume resets the PCI configuration space, so we have to
726 * re-disable the RETRY_TIMEOUT register (0x41) to keep
727 * PCI Tx retries from interfering with C3 CPU state
728 */
729 pci_write_config_byte(pdev, 0x41, 0);
730
3a078876 731 ath5k_led_enable(sc);
fa1c114f
JS		 732 return 0;
733}
734#endif /* CONFIG_PM */
735
736
fa1c114f
JS		 737/***********************\
738* Driver Initialization *
739\***********************/
740
f769c36b
BC		 741static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
742{
743 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
744 struct ath5k_softc *sc = hw->priv;
db719718 745 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
f769c36b 746
608b88cb 747 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 748}
749
fa1c114f
JS		 750static int
751ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
752{
753 struct ath5k_softc *sc = hw->priv;
754 struct ath5k_hw *ah = sc->ah;
db719718 755 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
0e149cf5 756 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 757 int ret;
758
759 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
760
761 /*
762 * Check if the MAC has multi-rate retry support.
763 * We do this by trying to setup a fake extended
764 * descriptor. MAC's that don't have support will
765 * return false w/o doing anything. MAC's that do
766 * support it will return true w/o doing anything.
767 */
c6e387a2 768 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 769 if (ret < 0)
770 goto err;
771 if (ret > 0)
fa1c114f
JS		 772 __set_bit(ATH_STAT_MRRETRY, sc->status);
773
fa1c114f
JS		 774 /*
775 * Collect the channel list. The 802.11 layer
776 * is resposible for filtering this list based
777 * on settings like the phy mode and regulatory
778 * domain restrictions.
779 */
63266a65 780 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 781 if (ret) {
782 ATH5K_ERR(sc, "can't get channels\n");
783 goto err;
784 }
785
786 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 787 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
788 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 789 else
d8ee398d 790 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 791
792 /*
793 * Allocate tx+rx descriptors and populate the lists.
794 */
795 ret = ath5k_desc_alloc(sc, pdev);
796 if (ret) {
797 ATH5K_ERR(sc, "can't allocate descriptors\n");
798 goto err;
799 }
800
801 /*
802 * Allocate hardware transmit queues: one queue for
803 * beacon frames and one data queue for each QoS
804 * priority. Note that hw functions handle reseting
805 * these queues at the needed time.
806 */
807 ret = ath5k_beaconq_setup(ah);
808 if (ret < 0) {
809 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
810 goto err_desc;
811 }
812 sc->bhalq = ret;
cec8db23
BC		 813 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
814 if (IS_ERR(sc->cabq)) {
815 ATH5K_ERR(sc, "can't setup cab queue\n");
816 ret = PTR_ERR(sc->cabq);
817 goto err_bhal;
818 }
fa1c114f
JS		 819
820 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
821 if (IS_ERR(sc->txq)) {
822 ATH5K_ERR(sc, "can't setup xmit queue\n");
823 ret = PTR_ERR(sc->txq);
cec8db23 824 goto err_queues;
fa1c114f
JS		 825 }
826
827 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
828 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
829 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
6e220662 830 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 831 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 832
0e149cf5
BC		 833 ret = ath5k_eeprom_read_mac(ah, mac);
834 if (ret) {
835 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
836 sc->pdev->device);
837 goto err_queues;
838 }
839
fa1c114f
JS		 840 SET_IEEE80211_PERM_ADDR(hw, mac);
841 /* All MAC address bits matter for ACKs */
17753748 842 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 843 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
844
608b88cb
LR		 845 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
846 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 847 if (ret) {
848 ATH5K_ERR(sc, "can't initialize regulatory system\n");
849 goto err_queues;
850 }
851
fa1c114f
JS		 852 ret = ieee80211_register_hw(hw);
853 if (ret) {
854 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
855 goto err_queues;
856 }
857
608b88cb
LR		 858 if (!ath_is_world_regd(regulatory))
859 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 860
3a078876
BC		 861 ath5k_init_leds(sc);
862
fa1c114f
JS		 863 return 0;
864err_queues:
865 ath5k_txq_release(sc);
866err_bhal:
867 ath5k_hw_release_tx_queue(ah, sc->bhalq);
868err_desc:
869 ath5k_desc_free(sc, pdev);
870err:
871 return ret;
872}
873
874static void
875ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
876{
877 struct ath5k_softc *sc = hw->priv;
878
879 /*
880 * NB: the order of these is important:
881 * o call the 802.11 layer before detaching ath5k_hw to
882 * insure callbacks into the driver to delete global
883 * key cache entries can be handled
884 * o reclaim the tx queue data structures after calling
885 * the 802.11 layer as we'll get called back to reclaim
886 * node state and potentially want to use them
887 * o to cleanup the tx queues the hal is called, so detach
888 * it last
889 * XXX: ??? detach ath5k_hw ???
890 * Other than that, it's straightforward...
891 */
892 ieee80211_unregister_hw(hw);
893 ath5k_desc_free(sc, pdev);
894 ath5k_txq_release(sc);
895 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 896 ath5k_unregister_leds(sc);
fa1c114f
JS		 897
898 /*
899 * NB: can't reclaim these until after ieee80211_ifdetach
900 * returns because we'll get called back to reclaim node
901 * state and potentially want to use them.
902 */
903}
904
905
906
907
908/********************\
909* Channel/mode setup *
910\********************/
911
912/*
913 * Convert IEEE channel number to MHz frequency.
914 */
915static inline short
916ath5k_ieee2mhz(short chan)
917{
918 if (chan <= 14 || chan >= 27)
919 return ieee80211chan2mhz(chan);
920 else
921 return 2212 + chan * 20;
922}
923
42639fcd
BC		 924/*
925 * Returns true for the channel numbers used without all_channels modparam.
926 */
927static bool ath5k_is_standard_channel(short chan)
928{
929 return ((chan <= 14) ||
930 /* UNII 1,2 */
931 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
932 /* midband */
933 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
934 /* UNII-3 */
935 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
936}
937
fa1c114f
JS		 938static unsigned int
939ath5k_copy_channels(struct ath5k_hw *ah,
940 struct ieee80211_channel *channels,
941 unsigned int mode,
942 unsigned int max)
943{
d8ee398d 944 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 945
946 if (!test_bit(mode, ah->ah_modes))
947 return 0;
948
fa1c114f 949 switch (mode) {
d8ee398d
LR		 950 case AR5K_MODE_11A:
951 case AR5K_MODE_11A_TURBO:
fa1c114f 952 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 953 size = 220 ;
fa1c114f
JS		 954 chfreq = CHANNEL_5GHZ;
955 break;
d8ee398d
LR		 956 case AR5K_MODE_11B:
957 case AR5K_MODE_11G:
958 case AR5K_MODE_11G_TURBO:
959 size = 26;
fa1c114f
JS		 960 chfreq = CHANNEL_2GHZ;
961 break;
962 default:
963 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
964 return 0;
965 }
966
967 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 968 ch = i + 1 ;
969 freq = ath5k_ieee2mhz(ch);
fa1c114f 970
d8ee398d
LR		 971 /* Check if channel is supported by the chipset */
972 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 973 continue;
974
42639fcd
BC		 975 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
976 continue;
977
d8ee398d
LR		 978 /* Write channel info and increment counter */
979 channels[count].center_freq = freq;
a3f4b914
LR		 980 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
981 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 982 switch (mode) {
983 case AR5K_MODE_11A:
984 case AR5K_MODE_11G:
985 channels[count].hw_value = chfreq | CHANNEL_OFDM;
986 break;
987 case AR5K_MODE_11A_TURBO:
988 case AR5K_MODE_11G_TURBO:
989 channels[count].hw_value = chfreq |
990 CHANNEL_OFDM | CHANNEL_TURBO;
991 break;
992 case AR5K_MODE_11B:
d8ee398d
LR		 993 channels[count].hw_value = CHANNEL_B;
994 }
fa1c114f 995
fa1c114f
JS		 996 count++;
997 max--;
998 }
999
1000 return count;
1001}
1002
63266a65
BR		 1003static void
1004ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1005{
1006 u8 i;
1007
1008 for (i = 0; i < AR5K_MAX_RATES; i++)
1009 sc->rate_idx[b->band][i] = -1;
1010
1011 for (i = 0; i < b->n_bitrates; i++) {
1012 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1013 if (b->bitrates[i].hw_value_short)
1014 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1015 }
1016}
1017
d8ee398d 1018static int
63266a65 1019ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1020{
1021 struct ath5k_softc *sc = hw->priv;
d8ee398d 1022 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1023 struct ieee80211_supported_band *sband;
1024 int max_c, count_c = 0;
1025 int i;
fa1c114f 1026
d8ee398d 1027 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1028 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1029
1030 /* 2GHz band */
63266a65
BR		 1031 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1032 sband->band = IEEE80211_BAND_2GHZ;
1033 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1034
63266a65
BR		 1035 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1036 /* G mode */
1037 memcpy(sband->bitrates, &ath5k_rates[0],
1038 sizeof(struct ieee80211_rate) * 12);
1039 sband->n_bitrates = 12;
fa1c114f 1040
d8ee398d 1041 sband->channels = sc->channels;
d8ee398d 1042 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1043 AR5K_MODE_11G, max_c);
fa1c114f 1044
63266a65 1045 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1046 count_c = sband->n_channels;
63266a65
BR		 1047 max_c -= count_c;
1048 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1049 /* B mode */
1050 memcpy(sband->bitrates, &ath5k_rates[0],
1051 sizeof(struct ieee80211_rate) * 4);
1052 sband->n_bitrates = 4;
1053
1054 /* 5211 only supports B rates and uses 4bit rate codes
1055 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1056 * fix them up here:
1057 */
1058 if (ah->ah_version == AR5K_AR5211) {
1059 for (i = 0; i < 4; i++) {
1060 sband->bitrates[i].hw_value =
1061 sband->bitrates[i].hw_value & 0xF;
1062 sband->bitrates[i].hw_value_short =
1063 sband->bitrates[i].hw_value_short & 0xF;
1064 }
1065 }
fa1c114f 1066
63266a65
BR		 1067 sband->channels = sc->channels;
1068 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1069 AR5K_MODE_11B, max_c);
d8ee398d 1070
63266a65
BR		 1071 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1072 count_c = sband->n_channels;
d8ee398d 1073 max_c -= count_c;
fa1c114f 1074 }
63266a65 1075 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1076
63266a65 1077 /* 5GHz band, A mode */
400ec45a 1078 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1079 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1080 sband->band = IEEE80211_BAND_5GHZ;
1081 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1082
63266a65
BR		 1083 memcpy(sband->bitrates, &ath5k_rates[4],
1084 sizeof(struct ieee80211_rate) * 8);
1085 sband->n_bitrates = 8;
fa1c114f 1086
63266a65 1087 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1088 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1089 AR5K_MODE_11A, max_c);
1090
d8ee398d
LR		 1091 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1092 }
63266a65 1093 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1094
b446197c 1095 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1096
1097 return 0;
fa1c114f
JS		 1098}
1099
1100/*
e30eb4ab
JA		 1101 * Set/change channels. We always reset the chip.
1102 * To accomplish this we must first cleanup any pending DMA,
1103 * then restart stuff after a la ath5k_init.
be009370
BC		 1104 *
1105 * Called with sc->lock.
fa1c114f
JS		 1106 */
1107static int
1108ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1109{
d8ee398d
LR		 1110 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1111 sc->curchan->center_freq, chan->center_freq);
1112
e30eb4ab
JA		 1113 /*
1114 * To switch channels clear any pending DMA operations;
1115 * wait long enough for the RX fifo to drain, reset the
1116 * hardware at the new frequency, and then re-enable
1117 * the relevant bits of the h/w.
1118 */
1119 return ath5k_reset(sc, chan);
fa1c114f
JS		 1120}
1121
1122static void
1123ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1124{
fa1c114f 1125 sc->curmode = mode;
d8ee398d 1126
400ec45a 1127 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1128 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1129 } else {
1130 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1131 }
fa1c114f
JS		 1132}
1133
1134static void
1135ath5k_mode_setup(struct ath5k_softc *sc)
1136{
1137 struct ath5k_hw *ah = sc->ah;
1138 u32 rfilt;
1139
ae6f53f2
BC		 1140 ah->ah_op_mode = sc->opmode;
1141
fa1c114f
JS		 1142 /* configure rx filter */
1143 rfilt = sc->filter_flags;
1144 ath5k_hw_set_rx_filter(ah, rfilt);
1145
1146 if (ath5k_hw_hasbssidmask(ah))
1147 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1148
1149 /* configure operational mode */
1150 ath5k_hw_set_opmode(ah);
1151
fa1c114f
JS		 1152 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1153}
1154
d8ee398d 1155static inline int
63266a65
BR		 1156ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1157{
b7266047
BC		 1158 int rix;
1159
1160 /* return base rate on errors */
1161 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1162 "hw_rix out of bounds: %x\n", hw_rix))
1163 return 0;
1164
1165 rix = sc->rate_idx[sc->curband->band][hw_rix];
1166 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1167 rix = 0;
1168
1169 return rix;
d8ee398d
LR		 1170}
1171
fa1c114f
JS		 1172/***************\
1173* Buffers setup *
1174\***************/
1175
b6ea0356
BC		 1176static
1177struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1178{
db719718 1179 struct ath_common *common = ath5k_hw_common(sc->ah);
b6ea0356 1180 struct sk_buff *skb;
b6ea0356
BC		 1181
1182 /*
1183 * Allocate buffer with headroom_needed space for the
1184 * fake physical layer header at the start.
1185 */
db719718 1186 skb = ath_rxbuf_alloc(common,
dd849782 1187 common->rx_bufsize,
aeb63cfd 1188 GFP_ATOMIC);
b6ea0356
BC		 1189
1190 if (!skb) {
1191 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
dd849782 1192 common->rx_bufsize);
b6ea0356
BC		 1193 return NULL;
1194 }
b6ea0356
BC		 1195
1196 *skb_addr = pci_map_single(sc->pdev,
cc861f74
LR		 1197 skb->data, common->rx_bufsize,
1198 PCI_DMA_FROMDEVICE);
b6ea0356
BC		 1199 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1200 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1201 dev_kfree_skb(skb);
1202 return NULL;
1203 }
1204 return skb;
1205}
1206
fa1c114f
JS		 1207static int
1208ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1209{
1210 struct ath5k_hw *ah = sc->ah;
1211 struct sk_buff *skb = bf->skb;
1212 struct ath5k_desc *ds;
1213
b6ea0356
BC		 1214 if (!skb) {
1215 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1216 if (!skb)
fa1c114f 1217 return -ENOMEM;
fa1c114f 1218 bf->skb = skb;
fa1c114f
JS		 1219 }
1220
1221 /*
1222 * Setup descriptors. For receive we always terminate
1223 * the descriptor list with a self-linked entry so we'll
1224 * not get overrun under high load (as can happen with a
1225 * 5212 when ANI processing enables PHY error frames).
1226 *
1227 * To insure the last descriptor is self-linked we create
1228 * each descriptor as self-linked and add it to the end. As
1229 * each additional descriptor is added the previous self-linked
1230 * entry is ``fixed'' naturally. This should be safe even
1231 * if DMA is happening. When processing RX interrupts we
1232 * never remove/process the last, self-linked, entry on the
1233 * descriptor list. This insures the hardware always has
1234 * someplace to write a new frame.
1235 */
1236 ds = bf->desc;
1237 ds->ds_link = bf->daddr; /* link to self */
1238 ds->ds_data = bf->skbaddr;
c6e387a2 1239 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1240 skb_tailroom(skb), /* buffer size */
1241 0);
1242
1243 if (sc->rxlink != NULL)
1244 *sc->rxlink = bf->daddr;
1245 sc->rxlink = &ds->ds_link;
1246 return 0;
1247}
1248
2ac2927a
BC		 1249static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1250{
1251 struct ieee80211_hdr *hdr;
1252 enum ath5k_pkt_type htype;
1253 __le16 fc;
1254
1255 hdr = (struct ieee80211_hdr *)skb->data;
1256 fc = hdr->frame_control;
1257
1258 if (ieee80211_is_beacon(fc))
1259 htype = AR5K_PKT_TYPE_BEACON;
1260 else if (ieee80211_is_probe_resp(fc))
1261 htype = AR5K_PKT_TYPE_PROBE_RESP;
1262 else if (ieee80211_is_atim(fc))
1263 htype = AR5K_PKT_TYPE_ATIM;
1264 else if (ieee80211_is_pspoll(fc))
1265 htype = AR5K_PKT_TYPE_PSPOLL;
1266 else
1267 htype = AR5K_PKT_TYPE_NORMAL;
1268
1269 return htype;
1270}
1271
fa1c114f 1272static int
cec8db23
BC		 1273ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1274 struct ath5k_txq *txq)
fa1c114f
JS		 1275{
1276 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1277 struct ath5k_desc *ds = bf->desc;
1278 struct sk_buff *skb = bf->skb;
a888d52d 1279 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1280 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1281 struct ieee80211_rate *rate;
1282 unsigned int mrr_rate[3], mrr_tries[3];
1283 int i, ret;
8902ff4e 1284 u16 hw_rate;
07c1e852
BC		 1285 u16 cts_rate = 0;
1286 u16 duration = 0;
8902ff4e 1287 u8 rc_flags;
fa1c114f
JS		 1288
1289 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1290
fa1c114f
JS		 1291 /* XXX endianness */
1292 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1293 PCI_DMA_TODEVICE);
1294
8902ff4e
BC		 1295 rate = ieee80211_get_tx_rate(sc->hw, info);
1296
e039fa4a 1297 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1298 flags |= AR5K_TXDESC_NOACK;
1299
8902ff4e
BC		 1300 rc_flags = info->control.rates[0].flags;
1301 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1302 rate->hw_value_short : rate->hw_value;
1303
281c56dd 1304 pktlen = skb->len;
fa1c114f 1305
8f655dde
NK		 1306 /* FIXME: If we are in g mode and rate is a CCK rate
1307 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1308 * from tx power (value is in dB units already) */
362695e1
BC		 1309 if (info->control.hw_key) {
1310 keyidx = info->control.hw_key->hw_key_idx;
1311 pktlen += info->control.hw_key->icv_len;
1312 }
07c1e852
BC		 1313 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1314 flags |= AR5K_TXDESC_RTSENA;
1315 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1316 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1317 sc->vif, pktlen, info));
1318 }
1319 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1320 flags |= AR5K_TXDESC_CTSENA;
1321 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1322 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1323 sc->vif, pktlen, info));
1324 }
fa1c114f 1325 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
2ac2927a
BC		 1326 ieee80211_get_hdrlen_from_skb(skb),
1327 get_hw_packet_type(skb),
2e92e6f2 1328 (sc->power_level * 2),
8902ff4e 1329 hw_rate,
2bed03eb 1330 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1331 cts_rate, duration);
fa1c114f
JS		 1332 if (ret)
1333 goto err_unmap;
1334
2f7fe870
FF		 1335 memset(mrr_rate, 0, sizeof(mrr_rate));
1336 memset(mrr_tries, 0, sizeof(mrr_tries));
1337 for (i = 0; i < 3; i++) {
1338 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1339 if (!rate)
1340 break;
1341
1342 mrr_rate[i] = rate->hw_value;
e6a9854b 1343 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1344 }
1345
1346 ah->ah_setup_mrr_tx_desc(ah, ds,
1347 mrr_rate[0], mrr_tries[0],
1348 mrr_rate[1], mrr_tries[1],
1349 mrr_rate[2], mrr_tries[2]);
1350
fa1c114f
JS		 1351 ds->ds_link = 0;
1352 ds->ds_data = bf->skbaddr;
1353
1354 spin_lock_bh(&txq->lock);
1355 list_add_tail(&bf->list, &txq->q);
fa1c114f 1356 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1357 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1358 else /* no, so only link it */
1359 *txq->link = bf->daddr;
1360
1361 txq->link = &ds->ds_link;
c6e387a2 1362 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1363 mmiowb();
fa1c114f
JS		 1364 spin_unlock_bh(&txq->lock);
1365
1366 return 0;
1367err_unmap:
1368 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1369 return ret;
1370}
1371
1372/*******************\
1373* Descriptors setup *
1374\*******************/
1375
1376static int
1377ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1378{
1379 struct ath5k_desc *ds;
1380 struct ath5k_buf *bf;
1381 dma_addr_t da;
1382 unsigned int i;
1383 int ret;
1384
1385 /* allocate descriptors */
1386 sc->desc_len = sizeof(struct ath5k_desc) *
1387 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1388 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1389 if (sc->desc == NULL) {
1390 ATH5K_ERR(sc, "can't allocate descriptors\n");
1391 ret = -ENOMEM;
1392 goto err;
1393 }
1394 ds = sc->desc;
1395 da = sc->desc_daddr;
1396 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1397 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1398
1399 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1400 sizeof(struct ath5k_buf), GFP_KERNEL);
1401 if (bf == NULL) {
1402 ATH5K_ERR(sc, "can't allocate bufptr\n");
1403 ret = -ENOMEM;
1404 goto err_free;
1405 }
1406 sc->bufptr = bf;
1407
1408 INIT_LIST_HEAD(&sc->rxbuf);
1409 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1410 bf->desc = ds;
1411 bf->daddr = da;
1412 list_add_tail(&bf->list, &sc->rxbuf);
1413 }
1414
1415 INIT_LIST_HEAD(&sc->txbuf);
1416 sc->txbuf_len = ATH_TXBUF;
1417 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1418 da += sizeof(*ds)) {
1419 bf->desc = ds;
1420 bf->daddr = da;
1421 list_add_tail(&bf->list, &sc->txbuf);
1422 }
1423
1424 /* beacon buffer */
1425 bf->desc = ds;
1426 bf->daddr = da;
1427 sc->bbuf = bf;
1428
1429 return 0;
1430err_free:
1431 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1432err:
1433 sc->desc = NULL;
1434 return ret;
1435}
1436
1437static void
1438ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1439{
1440 struct ath5k_buf *bf;
1441
1442 ath5k_txbuf_free(sc, sc->bbuf);
1443 list_for_each_entry(bf, &sc->txbuf, list)
1444 ath5k_txbuf_free(sc, bf);
1445 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1446 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1447
1448 /* Free memory associated with all descriptors */
1449 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1450
1451 kfree(sc->bufptr);
1452 sc->bufptr = NULL;
1453}
1454
1455
1456
1457
1458
1459/**************\
1460* Queues setup *
1461\**************/
1462
1463static struct ath5k_txq *
1464ath5k_txq_setup(struct ath5k_softc *sc,
1465 int qtype, int subtype)
1466{
1467 struct ath5k_hw *ah = sc->ah;
1468 struct ath5k_txq *txq;
1469 struct ath5k_txq_info qi = {
1470 .tqi_subtype = subtype,
1471 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1472 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1473 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1474 };
1475 int qnum;
1476
1477 /*
1478 * Enable interrupts only for EOL and DESC conditions.
1479 * We mark tx descriptors to receive a DESC interrupt
1480 * when a tx queue gets deep; otherwise waiting for the
1481 * EOL to reap descriptors. Note that this is done to
1482 * reduce interrupt load and this only defers reaping
1483 * descriptors, never transmitting frames. Aside from
1484 * reducing interrupts this also permits more concurrency.
1485 * The only potential downside is if the tx queue backs
1486 * up in which case the top half of the kernel may backup
1487 * due to a lack of tx descriptors.
1488 */
1489 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1490 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1491 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1492 if (qnum < 0) {
1493 /*
1494 * NB: don't print a message, this happens
1495 * normally on parts with too few tx queues
1496 */
1497 return ERR_PTR(qnum);
1498 }
1499 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1500 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1501 qnum, ARRAY_SIZE(sc->txqs));
1502 ath5k_hw_release_tx_queue(ah, qnum);
1503 return ERR_PTR(-EINVAL);
1504 }
1505 txq = &sc->txqs[qnum];
1506 if (!txq->setup) {
1507 txq->qnum = qnum;
1508 txq->link = NULL;
1509 INIT_LIST_HEAD(&txq->q);
1510 spin_lock_init(&txq->lock);
1511 txq->setup = true;
1512 }
1513 return &sc->txqs[qnum];
1514}
1515
1516static int
1517ath5k_beaconq_setup(struct ath5k_hw *ah)
1518{
1519 struct ath5k_txq_info qi = {
1520 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1521 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1522 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1523 /* NB: for dynamic turbo, don't enable any other interrupts */
1524 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1525 };
1526
1527 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1528}
1529
1530static int
1531ath5k_beaconq_config(struct ath5k_softc *sc)
1532{
1533 struct ath5k_hw *ah = sc->ah;
1534 struct ath5k_txq_info qi;
1535 int ret;
1536
1537 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1538 if (ret)
a951ae21
BC		 1539 goto err;
1540
05c914fe
JB		 1541 if (sc->opmode == NL80211_IFTYPE_AP ||
1542 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1543 /*
1544 * Always burst out beacon and CAB traffic
1545 * (aifs = cwmin = cwmax = 0)
1546 */
1547 qi.tqi_aifs = 0;
1548 qi.tqi_cw_min = 0;
1549 qi.tqi_cw_max = 0;
05c914fe 1550 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1551 /*
1552 * Adhoc mode; backoff between 0 and (2 * cw_min).
1553 */
1554 qi.tqi_aifs = 0;
1555 qi.tqi_cw_min = 0;
1556 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1557 }
1558
6d91e1d8
BR		 1559 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1560 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1561 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1562
c6e387a2 1563 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1564 if (ret) {
1565 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1566 "hardware queue!\n", __func__);
a951ae21 1567 goto err;
fa1c114f 1568 }
a951ae21
BC		 1569 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1570 if (ret)
1571 goto err;
fa1c114f 1572
a951ae21
BC		 1573 /* reconfigure cabq with ready time to 80% of beacon_interval */
1574 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1575 if (ret)
1576 goto err;
1577
1578 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1579 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1580 if (ret)
1581 goto err;
1582
1583 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1584err:
1585 return ret;
fa1c114f
JS		 1586}
1587
1588static void
1589ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1590{
1591 struct ath5k_buf *bf, *bf0;
1592
1593 /*
1594 * NB: this assumes output has been stopped and
1595 * we do not need to block ath5k_tx_tasklet
1596 */
1597 spin_lock_bh(&txq->lock);
1598 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1599 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1600
1601 ath5k_txbuf_free(sc, bf);
1602
1603 spin_lock_bh(&sc->txbuflock);
fa1c114f
JS		 1604 list_move_tail(&bf->list, &sc->txbuf);
1605 sc->txbuf_len++;
1606 spin_unlock_bh(&sc->txbuflock);
1607 }
1608 txq->link = NULL;
1609 spin_unlock_bh(&txq->lock);
1610}
1611
1612/*
1613 * Drain the transmit queues and reclaim resources.
1614 */
1615static void
1616ath5k_txq_cleanup(struct ath5k_softc *sc)
1617{
1618 struct ath5k_hw *ah = sc->ah;
1619 unsigned int i;
1620
1621 /* XXX return value */
1622 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1623 /* don't touch the hardware if marked invalid */
1624 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1625 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1626 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1627 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1628 if (sc->txqs[i].setup) {
1629 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1630 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1631 "link %p\n",
1632 sc->txqs[i].qnum,
c6e387a2 1633 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1634 sc->txqs[i].qnum),
1635 sc->txqs[i].link);
1636 }
1637 }
36d6825b 1638 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1639
1640 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1641 if (sc->txqs[i].setup)
1642 ath5k_txq_drainq(sc, &sc->txqs[i]);
1643}
1644
1645static void
1646ath5k_txq_release(struct ath5k_softc *sc)
1647{
1648 struct ath5k_txq *txq = sc->txqs;
1649 unsigned int i;
1650
1651 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1652 if (txq->setup) {
1653 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1654 txq->setup = false;
1655 }
1656}
1657
1658
1659
1660
1661/*************\
1662* RX Handling *
1663\*************/
1664
1665/*
1666 * Enable the receive h/w following a reset.
1667 */
1668static int
1669ath5k_rx_start(struct ath5k_softc *sc)
1670{
1671 struct ath5k_hw *ah = sc->ah;
db719718 1672 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 1673 struct ath5k_buf *bf;
1674 int ret;
1675
cc861f74 1676 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
fa1c114f 1677
cc861f74
LR		 1678 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1679 common->cachelsz, common->rx_bufsize);
fa1c114f 1680
fa1c114f 1681 spin_lock_bh(&sc->rxbuflock);
26925042 1682 sc->rxlink = NULL;
fa1c114f
JS		 1683 list_for_each_entry(bf, &sc->rxbuf, list) {
1684 ret = ath5k_rxbuf_setup(sc, bf);
1685 if (ret != 0) {
1686 spin_unlock_bh(&sc->rxbuflock);
1687 goto err;
1688 }
1689 }
1690 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1691 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1692 spin_unlock_bh(&sc->rxbuflock);
1693
c6e387a2 1694 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1695 ath5k_mode_setup(sc); /* set filters, etc. */
1696 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1697
1698 return 0;
1699err:
1700 return ret;
1701}
1702
1703/*
1704 * Disable the receive h/w in preparation for a reset.
1705 */
1706static void
1707ath5k_rx_stop(struct ath5k_softc *sc)
1708{
1709 struct ath5k_hw *ah = sc->ah;
1710
c6e387a2 1711 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1712 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1713 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1714
1715 ath5k_debug_printrxbuffs(sc, ah);
1716
1717 sc->rxlink = NULL; /* just in case */
1718}
1719
1720static unsigned int
1721ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1722 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f 1723{
dc1e001b
LR		 1724 struct ath5k_hw *ah = sc->ah;
1725 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1726 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1727 unsigned int keyix, hlen;
fa1c114f 1728
b47f407b
BR		 1729 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1730 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1731 return RX_FLAG_DECRYPTED;
1732
1733 /* Apparently when a default key is used to decrypt the packet
1734 the hw does not set the index used to decrypt. In such cases
1735 get the index from the packet. */
798ee985 1736 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1737 if (ieee80211_has_protected(hdr->frame_control) &&
1738 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1739 skb->len >= hlen + 4) {
fa1c114f
JS		 1740 keyix = skb->data[hlen + 3] >> 6;
1741
dc1e001b 1742 if (test_bit(keyix, common->keymap))
fa1c114f
JS		 1743 return RX_FLAG_DECRYPTED;
1744 }
1745
1746 return 0;
1747}
1748
036cd1ec
BR		 1749
1750static void
6ba81c2c
BR		 1751ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1752 struct ieee80211_rx_status *rxs)
036cd1ec 1753{
954fecea 1754 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1755 u64 tsf, bc_tstamp;
036cd1ec
BR		 1756 u32 hw_tu;
1757 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1758
24b56e70 1759 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1760 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1761 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1762 /*
6ba81c2c
BR		 1763 * Received an IBSS beacon with the same BSSID. Hardware *must*
1764 * have updated the local TSF. We have to work around various
1765 * hardware bugs, though...
036cd1ec 1766 */
6ba81c2c
BR		 1767 tsf = ath5k_hw_get_tsf64(sc->ah);
1768 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1769 hw_tu = TSF_TO_TU(tsf);
1770
1771 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1772 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1773 (unsigned long long)bc_tstamp,
1774 (unsigned long long)rxs->mactime,
1775 (unsigned long long)(rxs->mactime - bc_tstamp),
1776 (unsigned long long)tsf);
6ba81c2c
BR		 1777
1778 /*
1779 * Sometimes the HW will give us a wrong tstamp in the rx
1780 * status, causing the timestamp extension to go wrong.
1781 * (This seems to happen especially with beacon frames bigger
1782 * than 78 byte (incl. FCS))
1783 * But we know that the receive timestamp must be later than the
1784 * timestamp of the beacon since HW must have synced to that.
1785 *
1786 * NOTE: here we assume mactime to be after the frame was
1787 * received, not like mac80211 which defines it at the start.
1788 */
1789 if (bc_tstamp > rxs->mactime) {
036cd1ec 1790 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1791 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1792 (unsigned long long)rxs->mactime,
1793 (unsigned long long)tsf);
6ba81c2c 1794 rxs->mactime = tsf;
036cd1ec 1795 }
6ba81c2c
BR		 1796
1797 /*
1798 * Local TSF might have moved higher than our beacon timers,
1799 * in that case we have to update them to continue sending
1800 * beacons. This also takes care of synchronizing beacon sending
1801 * times with other stations.
1802 */
1803 if (hw_tu >= sc->nexttbtt)
1804 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1805 }
1806}
1807
fa1c114f
JS		 1808static void
1809ath5k_tasklet_rx(unsigned long data)
1810{
1c5256bb 1811 struct ieee80211_rx_status *rxs;
b47f407b 1812 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1813 struct sk_buff *skb, *next_skb;
1814 dma_addr_t next_skb_addr;
fa1c114f 1815 struct ath5k_softc *sc = (void *)data;
cc861f74
LR		 1816 struct ath5k_hw *ah = sc->ah;
1817 struct ath_common *common = ath5k_hw_common(ah);
c57ca815 1818 struct ath5k_buf *bf;
fa1c114f 1819 struct ath5k_desc *ds;
fa1c114f
JS		 1820 int ret;
1821 int hdrlen;
0fe45b1d 1822 int padsize;
1c5256bb 1823 int rx_flag;
fa1c114f
JS		 1824
1825 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1826 if (list_empty(&sc->rxbuf)) {
1827 ATH5K_WARN(sc, "empty rx buf pool\n");
1828 goto unlock;
1829 }
fa1c114f 1830 do {
1c5256bb 1831 rx_flag = 0;
d6894b5b 1832
fa1c114f
JS		 1833 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1834 BUG_ON(bf->skb == NULL);
1835 skb = bf->skb;
1836 ds = bf->desc;
1837
c57ca815
BC		 1838 /* bail if HW is still using self-linked descriptor */
1839 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1840 break;
fa1c114f 1841
b47f407b 1842 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1843 if (unlikely(ret == -EINPROGRESS))
1844 break;
1845 else if (unlikely(ret)) {
1846 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1847 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1848 return;
1849 }
1850
b47f407b 1851 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1852 ATH5K_WARN(sc, "unsupported jumbo\n");
1853 goto next;
1854 }
1855
b47f407b
BR		 1856 if (unlikely(rs.rs_status)) {
1857 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1858 goto next;
b47f407b 1859 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1860 /*
1861 * Decrypt error. If the error occurred
1862 * because there was no hardware key, then
1863 * let the frame through so the upper layers
1864 * can process it. This is necessary for 5210
1865 * parts which have no way to setup a ``clear''
1866 * key cache entry.
1867 *
1868 * XXX do key cache faulting
1869 */
b47f407b
BR		 1870 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1871 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1872 goto accept;
1873 }
b47f407b 1874 if (rs.rs_status & AR5K_RXERR_MIC) {
1c5256bb 1875 rx_flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1876 goto accept;
1877 }
1878
1879 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1880 if ((rs.rs_status &
1881 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1882 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1883 goto next;
1884 }
1885accept:
b6ea0356
BC		 1886 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1887
1888 /*
1889 * If we can't replace bf->skb with a new skb under memory
1890 * pressure, just skip this packet
1891 */
1892 if (!next_skb)
1893 goto next;
1894
cc861f74 1895 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
fa1c114f 1896 PCI_DMA_FROMDEVICE);
b47f407b 1897 skb_put(skb, rs.rs_datalen);
fa1c114f 1898
0fe45b1d
BP		 1899 /* The MAC header is padded to have 32-bit boundary if the
1900 * packet payload is non-zero. The general calculation for
1901 * padsize would take into account odd header lengths:
1902 * padsize = (4 - hdrlen % 4) % 4; However, since only
1903 * even-length headers are used, padding can only be 0 or 2
1904 * bytes and we can optimize this a bit. In addition, we must
1905 * not try to remove padding from short control frames that do
1906 * not have payload. */
fa1c114f 1907 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1908 padsize = ath5k_pad_size(hdrlen);
1909 if (padsize) {
0fe45b1d
BP		 1910 memmove(skb->data + padsize, skb->data, hdrlen);
1911 skb_pull(skb, padsize);
fa1c114f 1912 }
1c5256bb 1913 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 1914
c0e1899b
BR		 1915 /*
1916 * always extend the mac timestamp, since this information is
1917 * also needed for proper IBSS merging.
1918 *
1919 * XXX: it might be too late to do it here, since rs_tstamp is
1920 * 15bit only. that means TSF extension has to be done within
1921 * 32768usec (about 32ms). it might be necessary to move this to
1922 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1923 *
1924 * Unfortunately we don't know when the hardware takes the rx
1925 * timestamp (beginning of phy frame, data frame, end of rx?).
1926 * The only thing we know is that it is hardware specific...
1927 * On AR5213 it seems the rx timestamp is at the end of the
1928 * frame, but i'm not sure.
1929 *
1930 * NOTE: mac80211 defines mactime at the beginning of the first
1931 * data symbol. Since we don't have any time references it's
1932 * impossible to comply to that. This affects IBSS merge only
1933 * right now, so it's not too bad...
c0e1899b 1934 */
1c5256bb
BC		 1935 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1936 rxs->flag = rx_flag | RX_FLAG_TSFT;
c0e1899b 1937
1c5256bb
BC		 1938 rxs->freq = sc->curchan->center_freq;
1939 rxs->band = sc->curband->band;
fa1c114f 1940
1c5256bb
BC		 1941 rxs->noise = sc->ah->ah_noise_floor;
1942 rxs->signal = rxs->noise + rs.rs_rssi;
6e0e0bf8 1943
1c5256bb
BC		 1944 rxs->antenna = rs.rs_antenna;
1945 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1946 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1947
1c5256bb
BC		 1948 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1949 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1950 rxs->flag |= RX_FLAG_SHORTPRE;
06303352 1951
fa1c114f
JS		 1952 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1953
036cd1ec 1954 /* check beacons in IBSS mode */
05c914fe 1955 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1c5256bb 1956 ath5k_check_ibss_tsf(sc, skb, rxs);
036cd1ec 1957
f1d58c25 1958 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 1959
1960 bf->skb = next_skb;
1961 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1962next:
1963 list_move_tail(&bf->list, &sc->rxbuf);
1964 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1965unlock:
fa1c114f
JS		 1966 spin_unlock(&sc->rxbuflock);
1967}
1968
1969
1970
1971
1972/*************\
1973* TX Handling *
1974\*************/
1975
1976static void
1977ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1978{
b47f407b 1979 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1980 struct ath5k_buf *bf, *bf0;
1981 struct ath5k_desc *ds;
1982 struct sk_buff *skb;
e039fa4a 1983 struct ieee80211_tx_info *info;
2f7fe870 1984 int i, ret;
fa1c114f
JS		 1985
1986 spin_lock(&txq->lock);
1987 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1988 ds = bf->desc;
1989
b47f407b 1990 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1991 if (unlikely(ret == -EINPROGRESS))
1992 break;
1993 else if (unlikely(ret)) {
1994 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1995 ret, txq->qnum);
1996 break;
1997 }
1998
1999 skb = bf->skb;
a888d52d 2000 info = IEEE80211_SKB_CB(skb);
fa1c114f 2001 bf->skb = NULL;
e039fa4a 2002
fa1c114f
JS		 2003 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2004 PCI_DMA_TODEVICE);
2005
e6a9854b 2006 ieee80211_tx_info_clear_status(info);
2f7fe870 2007 for (i = 0; i < 4; i++) {
e6a9854b
JB		 2008 struct ieee80211_tx_rate *r =
2009 &info->status.rates[i];
2f7fe870
FF		 2010
2011 if (ts.ts_rate[i]) {
e6a9854b
JB		 2012 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2013 r->count = ts.ts_retry[i];
2f7fe870 2014 } else {
e6a9854b
JB		 2015 r->idx = -1;
2016 r->count = 0;
2f7fe870
FF		 2017 }
2018 }
2019
e6a9854b
JB		 2020 /* count the successful attempt as well */
2021 info->status.rates[ts.ts_final_idx].count++;
2022
b47f407b 2023 if (unlikely(ts.ts_status)) {
fa1c114f 2024 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 2025 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 2026 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 2027 } else {
e039fa4a
JB		 2028 info->flags |= IEEE80211_TX_STAT_ACK;
2029 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2030 }
2031
e039fa4a 2032 ieee80211_tx_status(sc->hw, skb);
fa1c114f
JS		 2033
2034 spin_lock(&sc->txbuflock);
fa1c114f
JS		 2035 list_move_tail(&bf->list, &sc->txbuf);
2036 sc->txbuf_len++;
2037 spin_unlock(&sc->txbuflock);
2038 }
2039 if (likely(list_empty(&txq->q)))
2040 txq->link = NULL;
2041 spin_unlock(&txq->lock);
2042 if (sc->txbuf_len > ATH_TXBUF / 5)
2043 ieee80211_wake_queues(sc->hw);
2044}
2045
2046static void
2047ath5k_tasklet_tx(unsigned long data)
2048{
8784d2ee 2049 int i;
fa1c114f
JS		 2050 struct ath5k_softc *sc = (void *)data;
2051
8784d2ee
BC		 2052 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2053 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2054 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2055}
2056
2057
fa1c114f
JS		 2058/*****************\
2059* Beacon handling *
2060\*****************/
2061
2062/*
2063 * Setup the beacon frame for transmit.
2064 */
2065static int
e039fa4a 2066ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2067{
2068 struct sk_buff *skb = bf->skb;
a888d52d 2069 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2070 struct ath5k_hw *ah = sc->ah;
2071 struct ath5k_desc *ds;
2bed03eb
NK		 2072 int ret = 0;
2073 u8 antenna;
fa1c114f
JS		 2074 u32 flags;
2075
2076 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2077 PCI_DMA_TODEVICE);
2078 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2079 "skbaddr %llx\n", skb, skb->data, skb->len,
2080 (unsigned long long)bf->skbaddr);
8d8bb39b 2081 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2082 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2083 return -EIO;
2084 }
2085
2086 ds = bf->desc;
2bed03eb 2087 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2088
2089 flags = AR5K_TXDESC_NOACK;
05c914fe 2090 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2091 ds->ds_link = bf->daddr; /* self-linked */
2092 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2093 } else
fa1c114f 2094 ds->ds_link = 0;
2bed03eb
NK		 2095
2096 /*
2097 * If we use multiple antennas on AP and use
2098 * the Sectored AP scenario, switch antenna every
2099 * 4 beacons to make sure everybody hears our AP.
2100 * When a client tries to associate, hw will keep
2101 * track of the tx antenna to be used for this client
2102 * automaticaly, based on ACKed packets.
2103 *
2104 * Note: AP still listens and transmits RTS on the
2105 * default antenna which is supposed to be an omni.
2106 *
2107 * Note2: On sectored scenarios it's possible to have
2108 * multiple antennas (1omni -the default- and 14 sectors)
2109 * so if we choose to actually support this mode we need
2110 * to allow user to set how many antennas we have and tweak
2111 * the code below to send beacons on all of them.
2112 */
2113 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2114 antenna = sc->bsent & 4 ? 2 : 1;
2115
fa1c114f 2116
8f655dde
NK		 2117 /* FIXME: If we are in g mode and rate is a CCK rate
2118 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2119 * from tx power (value is in dB units already) */
fa1c114f 2120 ds->ds_data = bf->skbaddr;
281c56dd 2121 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2122 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2123 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2124 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2125 1, AR5K_TXKEYIX_INVALID,
400ec45a 2126 antenna, flags, 0, 0);
fa1c114f
JS		 2127 if (ret)
2128 goto err_unmap;
2129
2130 return 0;
2131err_unmap:
2132 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2133 return ret;
2134}
2135
2136/*
2137 * Transmit a beacon frame at SWBA. Dynamic updates to the
2138 * frame contents are done as needed and the slot time is
2139 * also adjusted based on current state.
2140 *
acf3c1a5
BC		 2141 * This is called from software irq context (beacontq or restq
2142 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2143 */
2144static void
2145ath5k_beacon_send(struct ath5k_softc *sc)
2146{
2147 struct ath5k_buf *bf = sc->bbuf;
2148 struct ath5k_hw *ah = sc->ah;
cec8db23 2149 struct sk_buff *skb;
fa1c114f 2150
be9b7259 2151 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2152
05c914fe
JB		 2153 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2154 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2155 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2156 return;
2157 }
2158 /*
2159 * Check if the previous beacon has gone out. If
2160 * not don't don't try to post another, skip this
2161 * period and wait for the next. Missed beacons
2162 * indicate a problem and should not occur. If we
2163 * miss too many consecutive beacons reset the device.
2164 */
2165 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2166 sc->bmisscount++;
be9b7259 2167 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2168 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2169 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2170 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2171 "stuck beacon time (%u missed)\n",
2172 sc->bmisscount);
2173 tasklet_schedule(&sc->restq);
2174 }
2175 return;
2176 }
2177 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2178 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2179 "resume beacon xmit after %u misses\n",
2180 sc->bmisscount);
2181 sc->bmisscount = 0;
2182 }
2183
2184 /*
2185 * Stop any current dma and put the new frame on the queue.
2186 * This should never fail since we check above that no frames
2187 * are still pending on the queue.
2188 */
2189 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2190 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2191 /* NB: hw still stops DMA, so proceed */
2192 }
fa1c114f 2193
1071db86
BC		 2194 /* refresh the beacon for AP mode */
2195 if (sc->opmode == NL80211_IFTYPE_AP)
2196 ath5k_beacon_update(sc->hw, sc->vif);
2197
c6e387a2
NK		 2198 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2199 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2200 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2201 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2202
cec8db23
BC		 2203 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2204 while (skb) {
2205 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2206 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2207 }
2208
fa1c114f
JS		 2209 sc->bsent++;
2210}
2211
2212
9804b98d
BR		 2213/**
2214 * ath5k_beacon_update_timers - update beacon timers
2215 *
2216 * @sc: struct ath5k_softc pointer we are operating on
2217 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2218 * beacon timer update based on the current HW TSF.
2219 *
2220 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2221 * of a received beacon or the current local hardware TSF and write it to the
2222 * beacon timer registers.
2223 *
2224 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2225 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2226 * when we otherwise know we have to update the timers, but we keep it in this
2227 * function to have it all together in one place.
2228 */
fa1c114f 2229static void
9804b98d 2230ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2231{
2232 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2233 u32 nexttbtt, intval, hw_tu, bc_tu;
2234 u64 hw_tsf;
fa1c114f
JS		 2235
2236 intval = sc->bintval & AR5K_BEACON_PERIOD;
2237 if (WARN_ON(!intval))
2238 return;
2239
9804b98d
BR		 2240 /* beacon TSF converted to TU */
2241 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2242
9804b98d
BR		 2243 /* current TSF converted to TU */
2244 hw_tsf = ath5k_hw_get_tsf64(ah);
2245 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2246
9804b98d
BR		 2247#define FUDGE 3
2248 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2249 if (bc_tsf == -1) {
2250 /*
2251 * no beacons received, called internally.
2252 * just need to refresh timers based on HW TSF.
2253 */
2254 nexttbtt = roundup(hw_tu + FUDGE, intval);
2255 } else if (bc_tsf == 0) {
2256 /*
2257 * no beacon received, probably called by ath5k_reset_tsf().
2258 * reset TSF to start with 0.
2259 */
2260 nexttbtt = intval;
2261 intval |= AR5K_BEACON_RESET_TSF;
2262 } else if (bc_tsf > hw_tsf) {
2263 /*
2264 * beacon received, SW merge happend but HW TSF not yet updated.
2265 * not possible to reconfigure timers yet, but next time we
2266 * receive a beacon with the same BSSID, the hardware will
2267 * automatically update the TSF and then we need to reconfigure
2268 * the timers.
2269 */
2270 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2271 "need to wait for HW TSF sync\n");
2272 return;
2273 } else {
2274 /*
2275 * most important case for beacon synchronization between STA.
2276 *
2277 * beacon received and HW TSF has been already updated by HW.
2278 * update next TBTT based on the TSF of the beacon, but make
2279 * sure it is ahead of our local TSF timer.
2280 */
2281 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2282 }
2283#undef FUDGE
fa1c114f 2284
036cd1ec
BR		 2285 sc->nexttbtt = nexttbtt;
2286
fa1c114f 2287 intval |= AR5K_BEACON_ENA;
fa1c114f 2288 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2289
2290 /*
2291 * debugging output last in order to preserve the time critical aspect
2292 * of this function
2293 */
2294 if (bc_tsf == -1)
2295 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2296 "reconfigured timers based on HW TSF\n");
2297 else if (bc_tsf == 0)
2298 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2299 "reset HW TSF and timers\n");
2300 else
2301 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2302 "updated timers based on beacon TSF\n");
2303
2304 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2305 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2306 (unsigned long long) bc_tsf,
2307 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2308 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2309 intval & AR5K_BEACON_PERIOD,
2310 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2311 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2312}
2313
2314
036cd1ec
BR		 2315/**
2316 * ath5k_beacon_config - Configure the beacon queues and interrupts
2317 *
2318 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2319 *
036cd1ec 2320 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2321 * interrupts to detect TSF updates only.
fa1c114f
JS		 2322 */
2323static void
2324ath5k_beacon_config(struct ath5k_softc *sc)
2325{
2326 struct ath5k_hw *ah = sc->ah;
b5f03956 2327 unsigned long flags;
fa1c114f 2328
21800491 2329 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2330 sc->bmisscount = 0;
dc1968e7 2331 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2332
21800491 2333 if (sc->enable_beacon) {
fa1c114f 2334 /*
036cd1ec
BR		 2335 * In IBSS mode we use a self-linked tx descriptor and let the
2336 * hardware send the beacons automatically. We have to load it
fa1c114f 2337 * only once here.
036cd1ec 2338 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2339 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2340 */
2341 ath5k_beaconq_config(sc);
fa1c114f 2342
036cd1ec
BR		 2343 sc->imask |= AR5K_INT_SWBA;
2344
da966bca 2345 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2346 if (ath5k_hw_hasveol(ah))
da966bca 2347 ath5k_beacon_send(sc);
da966bca
JS		 2348 } else
2349 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2350 } else {
2351 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2352 }
fa1c114f 2353
c6e387a2 2354 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2355 mmiowb();
2356 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2357}
2358
428cbd4f
NK		 2359static void ath5k_tasklet_beacon(unsigned long data)
2360{
2361 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2362
2363 /*
2364 * Software beacon alert--time to send a beacon.
2365 *
2366 * In IBSS mode we use this interrupt just to
2367 * keep track of the next TBTT (target beacon
2368 * transmission time) in order to detect wether
2369 * automatic TSF updates happened.
2370 */
2371 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2372 /* XXX: only if VEOL suppported */
2373 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2374 sc->nexttbtt += sc->bintval;
2375 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2376 "SWBA nexttbtt: %x hw_tu: %x "
2377 "TSF: %llx\n",
2378 sc->nexttbtt,
2379 TSF_TO_TU(tsf),
2380 (unsigned long long) tsf);
2381 } else {
2382 spin_lock(&sc->block);
2383 ath5k_beacon_send(sc);
2384 spin_unlock(&sc->block);
2385 }
2386}
2387
fa1c114f
JS		 2388
2389/********************\
2390* Interrupt handling *
2391\********************/
2392
2393static int
bb2becac 2394ath5k_init(struct ath5k_softc *sc)
fa1c114f 2395{
bc1b32d6
EO		 2396 struct ath5k_hw *ah = sc->ah;
2397 int ret, i;
fa1c114f
JS		 2398
2399 mutex_lock(&sc->lock);
2400
2401 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2402
2403 /*
2404 * Stop anything previously setup. This is safe
2405 * no matter this is the first time through or not.
2406 */
2407 ath5k_stop_locked(sc);
2408
242ab7ad
BC		 2409 /* Set PHY calibration interval */
2410 ah->ah_cal_intval = ath5k_calinterval;
2411
fa1c114f
JS		 2412 /*
2413 * The basic interface to setting the hardware in a good
2414 * state is ``reset''. On return the hardware is known to
2415 * be powered up and with interrupts disabled. This must
2416 * be followed by initialization of the appropriate bits
2417 * and then setup of the interrupt mask.
2418 */
d8ee398d
LR		 2419 sc->curchan = sc->hw->conf.channel;
2420 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2421 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2422 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
6e220662 2423 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
209d889b 2424 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2425 if (ret)
2426 goto done;
fa1c114f 2427
e6a3b616
TD		 2428 ath5k_rfkill_hw_start(ah);
2429
bc1b32d6
EO		 2430 /*
2431 * Reset the key cache since some parts do not reset the
2432 * contents on initial power up or resume from suspend.
2433 */
2434 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2435 ath5k_hw_reset_key(ah, i);
2436
fa1c114f 2437 /* Set ack to be sent at low bit-rates */
bc1b32d6 2438 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2439 ret = 0;
2440done:
274c7c36 2441 mmiowb();
fa1c114f
JS		 2442 mutex_unlock(&sc->lock);
2443 return ret;
2444}
2445
2446static int
2447ath5k_stop_locked(struct ath5k_softc *sc)
2448{
2449 struct ath5k_hw *ah = sc->ah;
2450
2451 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2452 test_bit(ATH_STAT_INVALID, sc->status));
2453
2454 /*
2455 * Shutdown the hardware and driver:
2456 * stop output from above
2457 * disable interrupts
2458 * turn off timers
2459 * turn off the radio
2460 * clear transmit machinery
2461 * clear receive machinery
2462 * drain and release tx queues
2463 * reclaim beacon resources
2464 * power down hardware
2465 *
2466 * Note that some of this work is not possible if the
2467 * hardware is gone (invalid).
2468 */
2469 ieee80211_stop_queues(sc->hw);
2470
2471 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2472 ath5k_led_off(sc);
c6e387a2 2473 ath5k_hw_set_imr(ah, 0);
274c7c36 2474 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2475 }
2476 ath5k_txq_cleanup(sc);
2477 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2478 ath5k_rx_stop(sc);
2479 ath5k_hw_phy_disable(ah);
2480 } else
2481 sc->rxlink = NULL;
2482
2483 return 0;
2484}
2485
2486/*
2487 * Stop the device, grabbing the top-level lock to protect
2488 * against concurrent entry through ath5k_init (which can happen
2489 * if another thread does a system call and the thread doing the
2490 * stop is preempted).
2491 */
2492static int
bb2becac 2493ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2494{
2495 int ret;
2496
2497 mutex_lock(&sc->lock);
2498 ret = ath5k_stop_locked(sc);
2499 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2500 /*
edd7fc70
NK		 2501 * Don't set the card in full sleep mode!
2502 *
2503 * a) When the device is in this state it must be carefully
2504 * woken up or references to registers in the PCI clock
2505 * domain may freeze the bus (and system). This varies
2506 * by chip and is mostly an issue with newer parts
2507 * (madwifi sources mentioned srev >= 0x78) that go to
2508 * sleep more quickly.
2509 *
2510 * b) On older chips full sleep results a weird behaviour
2511 * during wakeup. I tested various cards with srev < 0x78
2512 * and they don't wake up after module reload, a second
2513 * module reload is needed to bring the card up again.
2514 *
2515 * Until we figure out what's going on don't enable
2516 * full chip reset on any chip (this is what Legacy HAL
2517 * and Sam's HAL do anyway). Instead Perform a full reset
2518 * on the device (same as initial state after attach) and
2519 * leave it idle (keep MAC/BB on warm reset) */
2520 ret = ath5k_hw_on_hold(sc->ah);
2521
2522 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2523 "putting device to sleep\n");
fa1c114f
JS		 2524 }
2525 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2526
274c7c36 2527 mmiowb();
fa1c114f
JS		 2528 mutex_unlock(&sc->lock);
2529
10488f8a
JS		 2530 tasklet_kill(&sc->rxtq);
2531 tasklet_kill(&sc->txtq);
2532 tasklet_kill(&sc->restq);
6e220662 2533 tasklet_kill(&sc->calib);
acf3c1a5 2534 tasklet_kill(&sc->beacontq);
fa1c114f 2535
e6a3b616
TD		 2536 ath5k_rfkill_hw_stop(sc->ah);
2537
fa1c114f
JS		 2538 return ret;
2539}
2540
2541static irqreturn_t
2542ath5k_intr(int irq, void *dev_id)
2543{
2544 struct ath5k_softc *sc = dev_id;
2545 struct ath5k_hw *ah = sc->ah;
2546 enum ath5k_int status;
2547 unsigned int counter = 1000;
2548
2549 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2550 !ath5k_hw_is_intr_pending(ah)))
2551 return IRQ_NONE;
2552
2553 do {
fa1c114f
JS		 2554 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2555 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2556 status, sc->imask);
fa1c114f
JS		 2557 if (unlikely(status & AR5K_INT_FATAL)) {
2558 /*
2559 * Fatal errors are unrecoverable.
2560 * Typically these are caused by DMA errors.
2561 */
2562 tasklet_schedule(&sc->restq);
2563 } else if (unlikely(status & AR5K_INT_RXORN)) {
2564 tasklet_schedule(&sc->restq);
2565 } else {
2566 if (status & AR5K_INT_SWBA) {
56d2ac76 2567 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2568 }
2569 if (status & AR5K_INT_RXEOL) {
2570 /*
2571 * NB: the hardware should re-read the link when
2572 * RXE bit is written, but it doesn't work at
2573 * least on older hardware revs.
2574 */
2575 sc->rxlink = NULL;
2576 }
2577 if (status & AR5K_INT_TXURN) {
2578 /* bump tx trigger level */
2579 ath5k_hw_update_tx_triglevel(ah, true);
2580 }
4c674c60 2581 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2582 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2583 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2584 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2585 tasklet_schedule(&sc->txtq);
2586 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2587 /* TODO */
fa1c114f 2588 }
6e220662
NK		 2589 if (status & AR5K_INT_SWI) {
2590 tasklet_schedule(&sc->calib);
2591 }
fa1c114f 2592 if (status & AR5K_INT_MIB) {
194828a2
NK		 2593 /*
2594 * These stats are also used for ANI i think
2595 * so how about updating them more often ?
2596 */
2597 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f 2598 }
e6a3b616 2599 if (status & AR5K_INT_GPIO)
e6a3b616 2600 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2601
fa1c114f 2602 }
2516baa6 2603 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2604
2605 if (unlikely(!counter))
2606 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2607
6e220662
NK		 2608 ath5k_hw_calibration_poll(ah);
2609
fa1c114f
JS		 2610 return IRQ_HANDLED;
2611}
2612
2613static void
2614ath5k_tasklet_reset(unsigned long data)
2615{
2616 struct ath5k_softc *sc = (void *)data;
2617
d7dc1003 2618 ath5k_reset_wake(sc);
fa1c114f
JS		 2619}
2620
2621/*
2622 * Periodically recalibrate the PHY to account
2623 * for temperature/environment changes.
2624 */
2625static void
6e220662 2626ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2627{
2628 struct ath5k_softc *sc = (void *)data;
2629 struct ath5k_hw *ah = sc->ah;
2630
6e220662
NK		 2631 /* Only full calibration for now */
2632 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2633 return;
2634
2635 /* Stop queues so that calibration
2636 * doesn't interfere with tx */
2637 ieee80211_stop_queues(sc->hw);
2638
fa1c114f 2639 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2640 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2641 sc->curchan->hw_value);
fa1c114f 2642
6f3b414a 2643 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2644 /*
2645 * Rfgain is out of bounds, reset the chip
2646 * to load new gain values.
2647 */
2648 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2649 ath5k_reset_wake(sc);
fa1c114f
JS		 2650 }
2651 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2652 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2653 ieee80211_frequency_to_channel(
2654 sc->curchan->center_freq));
fa1c114f 2655
6e220662
NK		 2656 ah->ah_swi_mask = 0;
2657
2658 /* Wake queues */
2659 ieee80211_wake_queues(sc->hw);
2660
fa1c114f
JS		 2661}
2662
2663
fa1c114f
JS		 2664/********************\
2665* Mac80211 functions *
2666\********************/
2667
2668static int
e039fa4a 2669ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2670{
2671 struct ath5k_softc *sc = hw->priv;
2672
2673 return ath5k_tx_queue(hw, skb, sc->txq);
2674}
2675
2676static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2677 struct ath5k_txq *txq)
fa1c114f
JS		 2678{
2679 struct ath5k_softc *sc = hw->priv;
2680 struct ath5k_buf *bf;
2681 unsigned long flags;
2682 int hdrlen;
0fe45b1d 2683 int padsize;
fa1c114f
JS		 2684
2685 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2686
05c914fe 2687 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2688 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2689
2690 /*
2691 * the hardware expects the header padded to 4 byte boundaries
2692 * if this is not the case we add the padding after the header
2693 */
2694 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2695 padsize = ath5k_pad_size(hdrlen);
2696 if (padsize) {
0fe45b1d
BP		 2697
2698 if (skb_headroom(skb) < padsize) {
fa1c114f 2699 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2700 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2701 goto drop_packet;
fa1c114f 2702 }
0fe45b1d
BP		 2703 skb_push(skb, padsize);
2704 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2705 }
2706
fa1c114f
JS		 2707 spin_lock_irqsave(&sc->txbuflock, flags);
2708 if (list_empty(&sc->txbuf)) {
2709 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2710 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2711 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2712 goto drop_packet;
fa1c114f
JS		 2713 }
2714 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2715 list_del(&bf->list);
2716 sc->txbuf_len--;
2717 if (list_empty(&sc->txbuf))
2718 ieee80211_stop_queues(hw);
2719 spin_unlock_irqrestore(&sc->txbuflock, flags);
2720
2721 bf->skb = skb;
2722
cec8db23 2723 if (ath5k_txbuf_setup(sc, bf, txq)) {
fa1c114f
JS		 2724 bf->skb = NULL;
2725 spin_lock_irqsave(&sc->txbuflock, flags);
2726 list_add_tail(&bf->list, &sc->txbuf);
2727 sc->txbuf_len++;
2728 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2729 goto drop_packet;
fa1c114f 2730 }
5a0fe8ac 2731 return NETDEV_TX_OK;
fa1c114f 2732
5a0fe8ac
BC		 2733drop_packet:
2734 dev_kfree_skb_any(skb);
71ef99c8 2735 return NETDEV_TX_OK;
fa1c114f
JS		 2736}
2737
209d889b
BC		 2738/*
2739 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2740 * and change to the given channel.
2741 */
fa1c114f 2742static int
209d889b 2743ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2744{
fa1c114f
JS		 2745 struct ath5k_hw *ah = sc->ah;
2746 int ret;
2747
2748 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2749
209d889b 2750 if (chan) {
c6e387a2 2751 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2752 ath5k_txq_cleanup(sc);
2753 ath5k_rx_stop(sc);
209d889b
BC		 2754
2755 sc->curchan = chan;
2756 sc->curband = &sc->sbands[chan->band];
d7dc1003 2757 }
3355443a 2758 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2759 if (ret) {
fa1c114f
JS		 2760 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2761 goto err;
2762 }
d7dc1003 2763
fa1c114f 2764 ret = ath5k_rx_start(sc);
d7dc1003 2765 if (ret) {
fa1c114f
JS		 2766 ATH5K_ERR(sc, "can't start recv logic\n");
2767 goto err;
2768 }
d7dc1003 2769
fa1c114f 2770 /*
d7dc1003
JS		 2771 * Change channels and update the h/w rate map if we're switching;
2772 * e.g. 11a to 11b/g.
2773 *
2774 * We may be doing a reset in response to an ioctl that changes the
2775 * channel so update any state that might change as a result.
fa1c114f
JS		 2776 *
2777 * XXX needed?
2778 */
2779/* ath5k_chan_change(sc, c); */
fa1c114f 2780
d7dc1003
JS		 2781 ath5k_beacon_config(sc);
2782 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2783
2784 return 0;
2785err:
2786 return ret;
2787}
2788
d7dc1003
JS		 2789static int
2790ath5k_reset_wake(struct ath5k_softc *sc)
2791{
2792 int ret;
2793
209d889b 2794 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2795 if (!ret)
2796 ieee80211_wake_queues(sc->hw);
2797
2798 return ret;
2799}
2800
fa1c114f
JS		 2801static int ath5k_start(struct ieee80211_hw *hw)
2802{
bb2becac 2803 return ath5k_init(hw->priv);
fa1c114f
JS		 2804}
2805
2806static void ath5k_stop(struct ieee80211_hw *hw)
2807{
bb2becac 2808 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2809}
2810
2811static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2812 struct ieee80211_vif *vif)
fa1c114f
JS		 2813{
2814 struct ath5k_softc *sc = hw->priv;
2815 int ret;
2816
2817 mutex_lock(&sc->lock);
32bfd35d 2818 if (sc->vif) {
fa1c114f
JS		 2819 ret = 0;
2820 goto end;
2821 }
2822
1ed32e4f 2823 sc->vif = vif;
fa1c114f 2824
1ed32e4f 2825 switch (vif->type) {
da966bca 2826 case NL80211_IFTYPE_AP:
05c914fe
JB		 2827 case NL80211_IFTYPE_STATION:
2828 case NL80211_IFTYPE_ADHOC:
b706e65b 2829 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2830 case NL80211_IFTYPE_MONITOR:
1ed32e4f 2831 sc->opmode = vif->type;
fa1c114f
JS		 2832 break;
2833 default:
2834 ret = -EOPNOTSUPP;
2835 goto end;
2836 }
67d2e2df 2837
1ed32e4f 2838 ath5k_hw_set_lladdr(sc->ah, vif->addr);
ae6f53f2 2839 ath5k_mode_setup(sc);
67d2e2df 2840
fa1c114f
JS		 2841 ret = 0;
2842end:
2843 mutex_unlock(&sc->lock);
2844 return ret;
2845}
2846
2847static void
2848ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 2849 struct ieee80211_vif *vif)
fa1c114f
JS		 2850{
2851 struct ath5k_softc *sc = hw->priv;
0e149cf5 2852 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2853
2854 mutex_lock(&sc->lock);
1ed32e4f 2855 if (sc->vif != vif)
fa1c114f
JS		 2856 goto end;
2857
0e149cf5 2858 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2859 sc->vif = NULL;
fa1c114f
JS		 2860end:
2861 mutex_unlock(&sc->lock);
2862}
2863
d8ee398d
LR		 2864/*
2865 * TODO: Phy disable/diversity etc
2866 */
fa1c114f 2867static int
e8975581 2868ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2869{
2870 struct ath5k_softc *sc = hw->priv;
a0823810 2871 struct ath5k_hw *ah = sc->ah;
e8975581 2872 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 2873 int ret = 0;
be009370
BC		 2874
2875 mutex_lock(&sc->lock);
fa1c114f 2876
e30eb4ab
JA		 2877 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2878 ret = ath5k_chan_set(sc, conf->channel);
2879 if (ret < 0)
2880 goto unlock;
2881 }
2bed03eb 2882
a0823810
NK		 2883 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2884 (sc->power_level != conf->power_level)) {
2885 sc->power_level = conf->power_level;
2886
2887 /* Half dB steps */
2888 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2889 }
fa1c114f 2890
2bed03eb
NK		 2891 /* TODO:
2892 * 1) Move this on config_interface and handle each case
2893 * separately eg. when we have only one STA vif, use
2894 * AR5K_ANTMODE_SINGLE_AP
2895 *
2896 * 2) Allow the user to change antenna mode eg. when only
2897 * one antenna is present
2898 *
2899 * 3) Allow the user to set default/tx antenna when possible
2900 *
2901 * 4) Default mode should handle 90% of the cases, together
2902 * with fixed a/b and single AP modes we should be able to
2903 * handle 99%. Sectored modes are extreme cases and i still
2904 * haven't found a usage for them. If we decide to support them,
2905 * then we must allow the user to set how many tx antennas we
2906 * have available
2907 */
2908 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
be009370 2909
55aa4e0f 2910unlock:
be009370 2911 mutex_unlock(&sc->lock);
55aa4e0f 2912 return ret;
fa1c114f
JS		 2913}
2914
3ac64bee
JB		 2915static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2916 int mc_count, struct dev_addr_list *mclist)
2917{
2918 u32 mfilt[2], val;
2919 int i;
2920 u8 pos;
2921
2922 mfilt[0] = 0;
2923 mfilt[1] = 1;
2924
2925 for (i = 0; i < mc_count; i++) {
2926 if (!mclist)
2927 break;
2928 /* calculate XOR of eight 6-bit values */
2929 val = get_unaligned_le32(mclist->dmi_addr + 0);
2930 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2931 val = get_unaligned_le32(mclist->dmi_addr + 3);
2932 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2933 pos &= 0x3f;
2934 mfilt[pos / 32] |= (1 << (pos % 32));
2935 /* XXX: we might be able to just do this instead,
2936 * but not sure, needs testing, if we do use this we'd
2937 * neet to inform below to not reset the mcast */
2938 /* ath5k_hw_set_mcast_filterindex(ah,
2939 * mclist->dmi_addr[5]); */
2940 mclist = mclist->next;
2941 }
2942
2943 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2944}
2945
fa1c114f
JS		 2946#define SUPPORTED_FIF_FLAGS \
2947 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2948 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2949 FIF_BCN_PRBRESP_PROMISC
2950/*
2951 * o always accept unicast, broadcast, and multicast traffic
2952 * o multicast traffic for all BSSIDs will be enabled if mac80211
2953 * says it should be
2954 * o maintain current state of phy ofdm or phy cck error reception.
2955 * If the hardware detects any of these type of errors then
2956 * ath5k_hw_get_rx_filter() will pass to us the respective
2957 * hardware filters to be able to receive these type of frames.
2958 * o probe request frames are accepted only when operating in
2959 * hostap, adhoc, or monitor modes
2960 * o enable promiscuous mode according to the interface state
2961 * o accept beacons:
2962 * - when operating in adhoc mode so the 802.11 layer creates
2963 * node table entries for peers,
2964 * - when operating in station mode for collecting rssi data when
2965 * the station is otherwise quiet, or
2966 * - when scanning
2967 */
2968static void ath5k_configure_filter(struct ieee80211_hw *hw,
2969 unsigned int changed_flags,
2970 unsigned int *new_flags,
3ac64bee 2971 u64 multicast)
fa1c114f
JS		 2972{
2973 struct ath5k_softc *sc = hw->priv;
2974 struct ath5k_hw *ah = sc->ah;
3ac64bee 2975 u32 mfilt[2], rfilt;
fa1c114f 2976
56d1de0a
BC		 2977 mutex_lock(&sc->lock);
2978
3ac64bee
JB		 2979 mfilt[0] = multicast;
2980 mfilt[1] = multicast >> 32;
fa1c114f
JS		 2981
2982 /* Only deal with supported flags */
2983 changed_flags &= SUPPORTED_FIF_FLAGS;
2984 *new_flags &= SUPPORTED_FIF_FLAGS;
2985
2986 /* If HW detects any phy or radar errors, leave those filters on.
2987 * Also, always enable Unicast, Broadcasts and Multicast
2988 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2989 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2990 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2991 AR5K_RX_FILTER_MCAST);
2992
2993 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2994 if (*new_flags & FIF_PROMISC_IN_BSS) {
2995 rfilt |= AR5K_RX_FILTER_PROM;
2996 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2997 } else {
fa1c114f 2998 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2999 }
fa1c114f
JS		 3000 }
3001
3002 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3003 if (*new_flags & FIF_ALLMULTI) {
3004 mfilt[0] = ~0;
3005 mfilt[1] = ~0;
fa1c114f
JS		 3006 }
3007
3008 /* This is the best we can do */
3009 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3010 rfilt |= AR5K_RX_FILTER_PHYERR;
3011
3012 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3013 * and probes for any BSSID, this needs testing */
3014 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3015 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3016
3017 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3018 * set we should only pass on control frames for this
3019 * station. This needs testing. I believe right now this
3020 * enables *all* control frames, which is OK.. but
3021 * but we should see if we can improve on granularity */
3022 if (*new_flags & FIF_CONTROL)
3023 rfilt |= AR5K_RX_FILTER_CONTROL;
3024
3025 /* Additional settings per mode -- this is per ath5k */
3026
3027 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3028
56d1de0a
BC		 3029 switch (sc->opmode) {
3030 case NL80211_IFTYPE_MESH_POINT:
3031 case NL80211_IFTYPE_MONITOR:
3032 rfilt |= AR5K_RX_FILTER_CONTROL |
3033 AR5K_RX_FILTER_BEACON |
3034 AR5K_RX_FILTER_PROBEREQ |
3035 AR5K_RX_FILTER_PROM;
3036 break;
3037 case NL80211_IFTYPE_AP:
3038 case NL80211_IFTYPE_ADHOC:
3039 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3040 AR5K_RX_FILTER_BEACON;
3041 break;
3042 case NL80211_IFTYPE_STATION:
3043 if (sc->assoc)
3044 rfilt |= AR5K_RX_FILTER_BEACON;
3045 default:
3046 break;
3047 }
fa1c114f
JS		 3048
3049 /* Set filters */
0bbac08f 3050 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3051
3052 /* Set multicast bits */
3053 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3054 /* Set the cached hw filter flags, this will alter actually
3055 * be set in HW */
3056 sc->filter_flags = rfilt;
56d1de0a
BC		 3057
3058 mutex_unlock(&sc->lock);
fa1c114f
JS		 3059}
3060
3061static int
3062ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3063 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3064 struct ieee80211_key_conf *key)
fa1c114f
JS		 3065{
3066 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3067 struct ath5k_hw *ah = sc->ah;
3068 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3069 int ret = 0;
3070
9ad9a26e
BC		 3071 if (modparam_nohwcrypt)
3072 return -EOPNOTSUPP;
3073
65b5a698
BC		 3074 if (sc->opmode == NL80211_IFTYPE_AP)
3075 return -EOPNOTSUPP;
3076
0bbac08f 3077 switch (key->alg) {
fa1c114f 3078 case ALG_WEP:
fa1c114f 3079 case ALG_TKIP:
3f64b435 3080 break;
fa1c114f 3081 case ALG_CCMP:
1c818740
BC		 3082 if (sc->ah->ah_aes_support)
3083 break;
3084
fa1c114f
JS		 3085 return -EOPNOTSUPP;
3086 default:
3087 WARN_ON(1);
3088 return -EINVAL;
3089 }
3090
3091 mutex_lock(&sc->lock);
3092
3093 switch (cmd) {
3094 case SET_KEY:
dc822b5d
JB		 3095 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3096 sta ? sta->addr : NULL);
fa1c114f
JS		 3097 if (ret) {
3098 ATH5K_ERR(sc, "can't set the key\n");
3099 goto unlock;
3100 }
dc1e001b 3101 __set_bit(key->keyidx, common->keymap);
fa1c114f 3102 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3103 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3104 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3105 break;
3106 case DISABLE_KEY:
3107 ath5k_hw_reset_key(sc->ah, key->keyidx);
dc1e001b 3108 __clear_bit(key->keyidx, common->keymap);
fa1c114f
JS		 3109 break;
3110 default:
3111 ret = -EINVAL;
3112 goto unlock;
3113 }
3114
3115unlock:
274c7c36 3116 mmiowb();
fa1c114f
JS		 3117 mutex_unlock(&sc->lock);
3118 return ret;
3119}
3120
3121static int
3122ath5k_get_stats(struct ieee80211_hw *hw,
3123 struct ieee80211_low_level_stats *stats)
3124{
3125 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3126 struct ath5k_hw *ah = sc->ah;
3127
3128 /* Force update */
3129 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3130
3131 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3132
3133 return 0;
3134}
3135
fa1c114f
JS		 3136static u64
3137ath5k_get_tsf(struct ieee80211_hw *hw)
3138{
3139 struct ath5k_softc *sc = hw->priv;
3140
3141 return ath5k_hw_get_tsf64(sc->ah);
3142}
3143
3b5d665b
AF		 3144static void
3145ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3146{
3147 struct ath5k_softc *sc = hw->priv;
3148
3149 ath5k_hw_set_tsf64(sc->ah, tsf);
3150}
3151
fa1c114f
JS		 3152static void
3153ath5k_reset_tsf(struct ieee80211_hw *hw)
3154{
3155 struct ath5k_softc *sc = hw->priv;
3156
9804b98d
BR		 3157 /*
3158 * in IBSS mode we need to update the beacon timers too.
3159 * this will also reset the TSF if we call it with 0
3160 */
05c914fe 3161 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3162 ath5k_beacon_update_timers(sc, 0);
3163 else
3164 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3165}
3166
1071db86
BC		 3167/*
3168 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3169 * this is called only once at config_bss time, for AP we do it every
3170 * SWBA interrupt so that the TIM will reflect buffered frames.
3171 *
3172 * Called with the beacon lock.
3173 */
fa1c114f 3174static int
1071db86 3175ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3176{
fa1c114f 3177 int ret;
1071db86 3178 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3179 struct sk_buff *skb;
3180
3181 if (WARN_ON(!vif)) {
3182 ret = -EINVAL;
3183 goto out;
3184 }
3185
3186 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3187
3188 if (!skb) {
3189 ret = -ENOMEM;
3190 goto out;
3191 }
fa1c114f
JS		 3192
3193 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3194
fa1c114f
JS		 3195 ath5k_txbuf_free(sc, sc->bbuf);
3196 sc->bbuf->skb = skb;
e039fa4a 3197 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3198 if (ret)
3199 sc->bbuf->skb = NULL;
1071db86
BC		 3200out:
3201 return ret;
3202}
3203
02969b38
MX		 3204static void
3205set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3206{
3207 struct ath5k_softc *sc = hw->priv;
3208 struct ath5k_hw *ah = sc->ah;
3209 u32 rfilt;
3210 rfilt = ath5k_hw_get_rx_filter(ah);
3211 if (enable)
3212 rfilt |= AR5K_RX_FILTER_BEACON;
3213 else
3214 rfilt &= ~AR5K_RX_FILTER_BEACON;
3215 ath5k_hw_set_rx_filter(ah, rfilt);
3216 sc->filter_flags = rfilt;
3217}
fa1c114f 3218
02969b38
MX		 3219static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3220 struct ieee80211_vif *vif,
3221 struct ieee80211_bss_conf *bss_conf,
3222 u32 changes)
3223{
3224 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3225 struct ath5k_hw *ah = sc->ah;
954fecea 3226 struct ath_common *common = ath5k_hw_common(ah);
21800491 3227 unsigned long flags;
2d0ddec5
JB		 3228
3229 mutex_lock(&sc->lock);
3230 if (WARN_ON(sc->vif != vif))
3231 goto unlock;
3232
3233 if (changes & BSS_CHANGED_BSSID) {
3234 /* Cache for later use during resets */
954fecea 3235 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
8ce54c5a 3236 common->curaid = 0;
be5d6b75 3237 ath5k_hw_set_associd(ah);
2d0ddec5
JB		 3238 mmiowb();
3239 }
57c4d7b4
JB		 3240
3241 if (changes & BSS_CHANGED_BEACON_INT)
3242 sc->bintval = bss_conf->beacon_int;
3243
02969b38 3244 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3245 sc->assoc = bss_conf->assoc;
3246 if (sc->opmode == NL80211_IFTYPE_STATION)
3247 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3248 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3249 AR5K_LED_ASSOC : AR5K_LED_INIT);
8ce54c5a
LR		 3250 if (bss_conf->assoc) {
3251 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3252 "Bss Info ASSOC %d, bssid: %pM\n",
3253 bss_conf->aid, common->curbssid);
3254 common->curaid = bss_conf->aid;
3255 ath5k_hw_set_associd(ah);
3256 /* Once ANI is available you would start it here */
3257 }
02969b38 3258 }
2d0ddec5 3259
21800491
BC		 3260 if (changes & BSS_CHANGED_BEACON) {
3261 spin_lock_irqsave(&sc->block, flags);
3262 ath5k_beacon_update(hw, vif);
3263 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3264 }
3265
21800491
BC		 3266 if (changes & BSS_CHANGED_BEACON_ENABLED)
3267 sc->enable_beacon = bss_conf->enable_beacon;
3268
3269 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3270 BSS_CHANGED_BEACON_INT))
3271 ath5k_beacon_config(sc);
3272
2d0ddec5
JB		 3273 unlock:
3274 mutex_unlock(&sc->lock);
02969b38 3275}
f0f3d388
BC		 3276
3277static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3278{
3279 struct ath5k_softc *sc = hw->priv;
3280 if (!sc->assoc)
3281 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3282}
3283
3284static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3285{
3286 struct ath5k_softc *sc = hw->priv;
3287 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3288 AR5K_LED_ASSOC : AR5K_LED_INIT);
3289}
6e08d228
LT		 3290
3291/**
3292 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3293 *
3294 * @hw: struct ieee80211_hw pointer
3295 * @coverage_class: IEEE 802.11 coverage class number
3296 *
3297 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3298 * coverage class. The values are persistent, they are restored after device
3299 * reset.
3300 */
3301static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3302{
3303 struct ath5k_softc *sc = hw->priv;
3304
3305 mutex_lock(&sc->lock);
3306 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3307 mutex_unlock(&sc->lock);
3308}
Clone of davem's net-next-2.6 tree