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ath5k: write PCU registers on initial reset
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e 63static int modparam_nohwcrypt;
46802a4f 64module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 66
42639fcd 67static int modparam_all_channels;
46802a4f 68module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 69MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
fa1c114f
JS		 71
72/******************\
73* Internal defines *
74\******************/
75
76/* Module info */
77MODULE_AUTHOR("Jiri Slaby");
78MODULE_AUTHOR("Nick Kossifidis");
79MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 82MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 83
84
85/* Known PCI ids */
2c91108c 86static const struct pci_device_id ath5k_pci_id_table[] = {
fa1c114f
JS		 87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 105 { 0 }
106};
107MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109/* Known SREVs */
2c91108c 110static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147};
148
2c91108c 149static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189};
190
fa1c114f
JS		 191/*
192 * Prototypes - PCI stack related functions
193 */
194static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197#ifdef CONFIG_PM
198static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200static int ath5k_pci_resume(struct pci_dev *pdev);
201#else
202#define ath5k_pci_suspend NULL
203#define ath5k_pci_resume NULL
204#endif /* CONFIG_PM */
205
04a9e451 206static struct pci_driver ath5k_pci_driver = {
9764f3f9 207 .name = KBUILD_MODNAME,
fa1c114f
JS		 208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213};
214
215
216
217/*
218 * Prototypes - MAC 802.11 stack related functions
219 */
e039fa4a 220static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 221static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
209d889b 223static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 224static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 225static int ath5k_start(struct ieee80211_hw *hw);
226static void ath5k_stop(struct ieee80211_hw *hw);
227static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
e8975581 231static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
fa1c114f
JS		 232static void ath5k_configure_filter(struct ieee80211_hw *hw,
233 unsigned int changed_flags,
234 unsigned int *new_flags,
235 int mc_count, struct dev_mc_list *mclist);
236static int ath5k_set_key(struct ieee80211_hw *hw,
237 enum set_key_cmd cmd,
dc822b5d 238 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 239 struct ieee80211_key_conf *key);
240static int ath5k_get_stats(struct ieee80211_hw *hw,
241 struct ieee80211_low_level_stats *stats);
242static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
243 struct ieee80211_tx_queue_stats *stats);
244static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 245static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 246static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 247static int ath5k_beacon_update(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif);
02969b38
MX		 249static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif,
251 struct ieee80211_bss_conf *bss_conf,
252 u32 changes);
f0f3d388
BC		 253static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
254static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
fa1c114f 255
2c91108c 256static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 257 .tx = ath5k_tx,
258 .start = ath5k_start,
259 .stop = ath5k_stop,
260 .add_interface = ath5k_add_interface,
261 .remove_interface = ath5k_remove_interface,
262 .config = ath5k_config,
fa1c114f
JS		 263 .configure_filter = ath5k_configure_filter,
264 .set_key = ath5k_set_key,
265 .get_stats = ath5k_get_stats,
266 .conf_tx = NULL,
267 .get_tx_stats = ath5k_get_tx_stats,
268 .get_tsf = ath5k_get_tsf,
3b5d665b 269 .set_tsf = ath5k_set_tsf,
fa1c114f 270 .reset_tsf = ath5k_reset_tsf,
02969b38 271 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 272 .sw_scan_start = ath5k_sw_scan_start,
273 .sw_scan_complete = ath5k_sw_scan_complete,
fa1c114f
JS		 274};
275
276/*
277 * Prototypes - Internal functions
278 */
279/* Attach detach */
280static int ath5k_attach(struct pci_dev *pdev,
281 struct ieee80211_hw *hw);
282static void ath5k_detach(struct pci_dev *pdev,
283 struct ieee80211_hw *hw);
284/* Channel/mode setup */
285static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 286static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
287 struct ieee80211_channel *channels,
288 unsigned int mode,
289 unsigned int max);
63266a65 290static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 291static int ath5k_chan_set(struct ath5k_softc *sc,
292 struct ieee80211_channel *chan);
293static void ath5k_setcurmode(struct ath5k_softc *sc,
294 unsigned int mode);
295static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 296
fa1c114f
JS		 297/* Descriptor setup */
298static int ath5k_desc_alloc(struct ath5k_softc *sc,
299 struct pci_dev *pdev);
300static void ath5k_desc_free(struct ath5k_softc *sc,
301 struct pci_dev *pdev);
302/* Buffers setup */
303static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
304 struct ath5k_buf *bf);
305static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23
BC		 306 struct ath5k_buf *bf,
307 struct ath5k_txq *txq);
fa1c114f
JS		 308static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
309 struct ath5k_buf *bf)
310{
311 BUG_ON(!bf);
312 if (!bf->skb)
313 return;
314 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
315 PCI_DMA_TODEVICE);
00482973 316 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 317 bf->skb = NULL;
318}
319
a6c8d375
FF		 320static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
321 struct ath5k_buf *bf)
322{
323 BUG_ON(!bf);
324 if (!bf->skb)
325 return;
326 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
327 PCI_DMA_FROMDEVICE);
328 dev_kfree_skb_any(bf->skb);
329 bf->skb = NULL;
330}
331
332
fa1c114f
JS		 333/* Queues setup */
334static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
335 int qtype, int subtype);
336static int ath5k_beaconq_setup(struct ath5k_hw *ah);
337static int ath5k_beaconq_config(struct ath5k_softc *sc);
338static void ath5k_txq_drainq(struct ath5k_softc *sc,
339 struct ath5k_txq *txq);
340static void ath5k_txq_cleanup(struct ath5k_softc *sc);
341static void ath5k_txq_release(struct ath5k_softc *sc);
342/* Rx handling */
343static int ath5k_rx_start(struct ath5k_softc *sc);
344static void ath5k_rx_stop(struct ath5k_softc *sc);
345static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
346 struct ath5k_desc *ds,
b47f407b
BR		 347 struct sk_buff *skb,
348 struct ath5k_rx_status *rs);
fa1c114f
JS		 349static void ath5k_tasklet_rx(unsigned long data);
350/* Tx handling */
351static void ath5k_tx_processq(struct ath5k_softc *sc,
352 struct ath5k_txq *txq);
353static void ath5k_tasklet_tx(unsigned long data);
354/* Beacon handling */
355static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 356 struct ath5k_buf *bf);
fa1c114f
JS		 357static void ath5k_beacon_send(struct ath5k_softc *sc);
358static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 359static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 360static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 361
362static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
363{
364 u64 tsf = ath5k_hw_get_tsf64(ah);
365
366 if ((tsf & 0x7fff) < rstamp)
367 tsf -= 0x8000;
368
369 return (tsf & ~0x7fff) | rstamp;
370}
371
372/* Interrupt handling */
bb2becac 373static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 374static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 375static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 376static irqreturn_t ath5k_intr(int irq, void *dev_id);
377static void ath5k_tasklet_reset(unsigned long data);
378
379static void ath5k_calibrate(unsigned long data);
fa1c114f
JS		 380
381/*
382 * Module init/exit functions
383 */
384static int __init
385init_ath5k_pci(void)
386{
387 int ret;
388
389 ath5k_debug_init();
390
04a9e451 391 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 392 if (ret) {
393 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
394 return ret;
395 }
396
397 return 0;
398}
399
400static void __exit
401exit_ath5k_pci(void)
402{
04a9e451 403 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 404
405 ath5k_debug_finish();
406}
407
408module_init(init_ath5k_pci);
409module_exit(exit_ath5k_pci);
410
411
412/********************\
413* PCI Initialization *
414\********************/
415
416static const char *
417ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
418{
419 const char *name = "xxxxx";
420 unsigned int i;
421
422 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
423 if (srev_names[i].sr_type != type)
424 continue;
75d0edb8
NK		 425
426 if ((val & 0xf0) == srev_names[i].sr_val)
427 name = srev_names[i].sr_name;
428
429 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 430 name = srev_names[i].sr_name;
431 break;
432 }
433 }
434
435 return name;
436}
437
438static int __devinit
439ath5k_pci_probe(struct pci_dev *pdev,
440 const struct pci_device_id *id)
441{
442 void __iomem *mem;
443 struct ath5k_softc *sc;
444 struct ieee80211_hw *hw;
445 int ret;
446 u8 csz;
447
448 ret = pci_enable_device(pdev);
449 if (ret) {
450 dev_err(&pdev->dev, "can't enable device\n");
451 goto err;
452 }
453
454 /* XXX 32-bit addressing only */
284901a9 455 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 456 if (ret) {
457 dev_err(&pdev->dev, "32-bit DMA not available\n");
458 goto err_dis;
459 }
460
461 /*
462 * Cache line size is used to size and align various
463 * structures used to communicate with the hardware.
464 */
465 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
466 if (csz == 0) {
467 /*
468 * Linux 2.4.18 (at least) writes the cache line size
469 * register as a 16-bit wide register which is wrong.
470 * We must have this setup properly for rx buffer
471 * DMA to work so force a reasonable value here if it
472 * comes up zero.
473 */
474 csz = L1_CACHE_BYTES / sizeof(u32);
475 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
476 }
477 /*
478 * The default setting of latency timer yields poor results,
479 * set it to the value used by other systems. It may be worth
480 * tweaking this setting more.
481 */
482 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
483
484 /* Enable bus mastering */
485 pci_set_master(pdev);
486
487 /*
488 * Disable the RETRY_TIMEOUT register (0x41) to keep
489 * PCI Tx retries from interfering with C3 CPU state.
490 */
491 pci_write_config_byte(pdev, 0x41, 0);
492
493 ret = pci_request_region(pdev, 0, "ath5k");
494 if (ret) {
495 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
496 goto err_dis;
497 }
498
499 mem = pci_iomap(pdev, 0, 0);
500 if (!mem) {
501 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
502 ret = -EIO;
503 goto err_reg;
504 }
505
506 /*
507 * Allocate hw (mac80211 main struct)
508 * and hw->priv (driver private data)
509 */
510 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
511 if (hw == NULL) {
512 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
513 ret = -ENOMEM;
514 goto err_map;
515 }
516
517 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
518
519 /* Initialize driver private data */
520 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 521 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 522 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 523 IEEE80211_HW_SIGNAL_DBM |
524 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 525
526 hw->wiphy->interface_modes =
6f5f39c9 527 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 528 BIT(NL80211_IFTYPE_STATION) |
529 BIT(NL80211_IFTYPE_ADHOC) |
530 BIT(NL80211_IFTYPE_MESH_POINT);
531
fa1c114f
JS		 532 hw->extra_tx_headroom = 2;
533 hw->channel_change_time = 5000;
fa1c114f
JS		 534 sc = hw->priv;
535 sc->hw = hw;
536 sc->pdev = pdev;
537
538 ath5k_debug_init_device(sc);
539
540 /*
541 * Mark the device as detached to avoid processing
542 * interrupts until setup is complete.
543 */
544 __set_bit(ATH_STAT_INVALID, sc->status);
545
546 sc->iobase = mem; /* So we can unmap it on detach */
547 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 548 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 549 sc->bintval = 1000;
fa1c114f
JS		 550 mutex_init(&sc->lock);
551 spin_lock_init(&sc->rxbuflock);
552 spin_lock_init(&sc->txbuflock);
00482973 553 spin_lock_init(&sc->block);
fa1c114f
JS		 554
555 /* Set private data */
556 pci_set_drvdata(pdev, hw);
557
fa1c114f
JS		 558 /* Setup interrupt handler */
559 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
560 if (ret) {
561 ATH5K_ERR(sc, "request_irq failed\n");
562 goto err_free;
563 }
564
565 /* Initialize device */
566 sc->ah = ath5k_hw_attach(sc, id->driver_data);
567 if (IS_ERR(sc->ah)) {
568 ret = PTR_ERR(sc->ah);
569 goto err_irq;
570 }
571
2f7fe870
FF		 572 /* set up multi-rate retry capabilities */
573 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 574 hw->max_rates = 4;
575 hw->max_rate_tries = 11;
2f7fe870
FF		 576 }
577
fa1c114f
JS		 578 /* Finish private driver data initialization */
579 ret = ath5k_attach(pdev, hw);
580 if (ret)
581 goto err_ah;
582
583 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 584 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 585 sc->ah->ah_mac_srev,
586 sc->ah->ah_phy_revision);
587
400ec45a 588 if (!sc->ah->ah_single_chip) {
fa1c114f 589 /* Single chip radio (!RF5111) */
400ec45a
LR		 590 if (sc->ah->ah_radio_5ghz_revision &&
591 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 592 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 593 if (!test_bit(AR5K_MODE_11A,
594 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 595 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 596 ath5k_chip_name(AR5K_VERSION_RAD,
597 sc->ah->ah_radio_5ghz_revision),
598 sc->ah->ah_radio_5ghz_revision);
599 /* No 2GHz support (5110 and some
600 * 5Ghz only cards) -> report 5Ghz radio */
601 } else if (!test_bit(AR5K_MODE_11B,
602 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 603 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 604 ath5k_chip_name(AR5K_VERSION_RAD,
605 sc->ah->ah_radio_5ghz_revision),
606 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 607 /* Multiband radio */
608 } else {
609 ATH5K_INFO(sc, "RF%s multiband radio found"
610 " (0x%x)\n",
400ec45a
LR		 611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 614 }
615 }
400ec45a
LR		 616 /* Multi chip radio (RF5111 - RF2111) ->
617 * report both 2GHz/5GHz radios */
618 else if (sc->ah->ah_radio_5ghz_revision &&
619 sc->ah->ah_radio_2ghz_revision){
fa1c114f 620 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 621 ath5k_chip_name(AR5K_VERSION_RAD,
622 sc->ah->ah_radio_5ghz_revision),
623 sc->ah->ah_radio_5ghz_revision);
fa1c114f 624 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 625 ath5k_chip_name(AR5K_VERSION_RAD,
626 sc->ah->ah_radio_2ghz_revision),
627 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 628 }
629 }
630
631
632 /* ready to process interrupts */
633 __clear_bit(ATH_STAT_INVALID, sc->status);
634
635 return 0;
636err_ah:
637 ath5k_hw_detach(sc->ah);
638err_irq:
639 free_irq(pdev->irq, sc);
640err_free:
fa1c114f
JS		 641 ieee80211_free_hw(hw);
642err_map:
643 pci_iounmap(pdev, mem);
644err_reg:
645 pci_release_region(pdev, 0);
646err_dis:
647 pci_disable_device(pdev);
648err:
649 return ret;
650}
651
652static void __devexit
653ath5k_pci_remove(struct pci_dev *pdev)
654{
655 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
656 struct ath5k_softc *sc = hw->priv;
657
658 ath5k_debug_finish_device(sc);
659 ath5k_detach(pdev, hw);
660 ath5k_hw_detach(sc->ah);
661 free_irq(pdev->irq, sc);
fa1c114f
JS		 662 pci_iounmap(pdev, sc->iobase);
663 pci_release_region(pdev, 0);
664 pci_disable_device(pdev);
665 ieee80211_free_hw(hw);
666}
667
668#ifdef CONFIG_PM
669static int
670ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
671{
672 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
673 struct ath5k_softc *sc = hw->priv;
674
3a078876 675 ath5k_led_off(sc);
fa1c114f 676
fa1c114f
JS		 677 pci_save_state(pdev);
678 pci_disable_device(pdev);
679 pci_set_power_state(pdev, PCI_D3hot);
680
681 return 0;
682}
683
684static int
685ath5k_pci_resume(struct pci_dev *pdev)
686{
687 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
688 struct ath5k_softc *sc = hw->priv;
bc1b32d6 689 int err;
fa1c114f 690
3e4242b9 691 pci_restore_state(pdev);
fa1c114f
JS		 692
693 err = pci_enable_device(pdev);
694 if (err)
695 return err;
696
8451d22d
JM		 697 /*
698 * Suspend/Resume resets the PCI configuration space, so we have to
699 * re-disable the RETRY_TIMEOUT register (0x41) to keep
700 * PCI Tx retries from interfering with C3 CPU state
701 */
702 pci_write_config_byte(pdev, 0x41, 0);
703
3a078876 704 ath5k_led_enable(sc);
fa1c114f
JS		 705 return 0;
706}
707#endif /* CONFIG_PM */
708
709
fa1c114f
JS		 710/***********************\
711* Driver Initialization *
712\***********************/
713
f769c36b
BC		 714static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
715{
716 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
717 struct ath5k_softc *sc = hw->priv;
718 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
719
720 return ath_reg_notifier_apply(wiphy, request, reg);
721}
722
fa1c114f
JS		 723static int
724ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
725{
726 struct ath5k_softc *sc = hw->priv;
727 struct ath5k_hw *ah = sc->ah;
0e149cf5 728 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 729 int ret;
730
731 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
732
733 /*
734 * Check if the MAC has multi-rate retry support.
735 * We do this by trying to setup a fake extended
736 * descriptor. MAC's that don't have support will
737 * return false w/o doing anything. MAC's that do
738 * support it will return true w/o doing anything.
739 */
c6e387a2 740 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 741 if (ret < 0)
742 goto err;
743 if (ret > 0)
fa1c114f
JS		 744 __set_bit(ATH_STAT_MRRETRY, sc->status);
745
fa1c114f
JS		 746 /*
747 * Collect the channel list. The 802.11 layer
748 * is resposible for filtering this list based
749 * on settings like the phy mode and regulatory
750 * domain restrictions.
751 */
63266a65 752 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 753 if (ret) {
754 ATH5K_ERR(sc, "can't get channels\n");
755 goto err;
756 }
757
758 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 759 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
760 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 761 else
d8ee398d 762 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 763
764 /*
765 * Allocate tx+rx descriptors and populate the lists.
766 */
767 ret = ath5k_desc_alloc(sc, pdev);
768 if (ret) {
769 ATH5K_ERR(sc, "can't allocate descriptors\n");
770 goto err;
771 }
772
773 /*
774 * Allocate hardware transmit queues: one queue for
775 * beacon frames and one data queue for each QoS
776 * priority. Note that hw functions handle reseting
777 * these queues at the needed time.
778 */
779 ret = ath5k_beaconq_setup(ah);
780 if (ret < 0) {
781 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
782 goto err_desc;
783 }
784 sc->bhalq = ret;
cec8db23
BC		 785 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
786 if (IS_ERR(sc->cabq)) {
787 ATH5K_ERR(sc, "can't setup cab queue\n");
788 ret = PTR_ERR(sc->cabq);
789 goto err_bhal;
790 }
fa1c114f
JS		 791
792 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
793 if (IS_ERR(sc->txq)) {
794 ATH5K_ERR(sc, "can't setup xmit queue\n");
795 ret = PTR_ERR(sc->txq);
cec8db23 796 goto err_queues;
fa1c114f
JS		 797 }
798
799 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
800 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
801 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
acf3c1a5 802 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 803 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 804
0e149cf5
BC		 805 ret = ath5k_eeprom_read_mac(ah, mac);
806 if (ret) {
807 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
808 sc->pdev->device);
809 goto err_queues;
810 }
811
fa1c114f
JS		 812 SET_IEEE80211_PERM_ADDR(hw, mac);
813 /* All MAC address bits matter for ACKs */
814 memset(sc->bssidmask, 0xff, ETH_ALEN);
815 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
816
f769c36b
BC		 817 ah->ah_regulatory.current_rd =
818 ah->ah_capabilities.cap_eeprom.ee_regdomain;
819 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
820 if (ret) {
821 ATH5K_ERR(sc, "can't initialize regulatory system\n");
822 goto err_queues;
823 }
824
fa1c114f
JS		 825 ret = ieee80211_register_hw(hw);
826 if (ret) {
827 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
828 goto err_queues;
829 }
830
f769c36b
BC		 831 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
832 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
833
3a078876
BC		 834 ath5k_init_leds(sc);
835
fa1c114f
JS		 836 return 0;
837err_queues:
838 ath5k_txq_release(sc);
839err_bhal:
840 ath5k_hw_release_tx_queue(ah, sc->bhalq);
841err_desc:
842 ath5k_desc_free(sc, pdev);
843err:
844 return ret;
845}
846
847static void
848ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
849{
850 struct ath5k_softc *sc = hw->priv;
851
852 /*
853 * NB: the order of these is important:
854 * o call the 802.11 layer before detaching ath5k_hw to
855 * insure callbacks into the driver to delete global
856 * key cache entries can be handled
857 * o reclaim the tx queue data structures after calling
858 * the 802.11 layer as we'll get called back to reclaim
859 * node state and potentially want to use them
860 * o to cleanup the tx queues the hal is called, so detach
861 * it last
862 * XXX: ??? detach ath5k_hw ???
863 * Other than that, it's straightforward...
864 */
865 ieee80211_unregister_hw(hw);
866 ath5k_desc_free(sc, pdev);
867 ath5k_txq_release(sc);
868 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 869 ath5k_unregister_leds(sc);
fa1c114f
JS		 870
871 /*
872 * NB: can't reclaim these until after ieee80211_ifdetach
873 * returns because we'll get called back to reclaim node
874 * state and potentially want to use them.
875 */
876}
877
878
879
880
881/********************\
882* Channel/mode setup *
883\********************/
884
885/*
886 * Convert IEEE channel number to MHz frequency.
887 */
888static inline short
889ath5k_ieee2mhz(short chan)
890{
891 if (chan <= 14 || chan >= 27)
892 return ieee80211chan2mhz(chan);
893 else
894 return 2212 + chan * 20;
895}
896
42639fcd
BC		 897/*
898 * Returns true for the channel numbers used without all_channels modparam.
899 */
900static bool ath5k_is_standard_channel(short chan)
901{
902 return ((chan <= 14) ||
903 /* UNII 1,2 */
904 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
905 /* midband */
906 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
907 /* UNII-3 */
908 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
909}
910
fa1c114f
JS		 911static unsigned int
912ath5k_copy_channels(struct ath5k_hw *ah,
913 struct ieee80211_channel *channels,
914 unsigned int mode,
915 unsigned int max)
916{
d8ee398d 917 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 918
919 if (!test_bit(mode, ah->ah_modes))
920 return 0;
921
fa1c114f 922 switch (mode) {
d8ee398d
LR		 923 case AR5K_MODE_11A:
924 case AR5K_MODE_11A_TURBO:
fa1c114f 925 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 926 size = 220 ;
fa1c114f
JS		 927 chfreq = CHANNEL_5GHZ;
928 break;
d8ee398d
LR		 929 case AR5K_MODE_11B:
930 case AR5K_MODE_11G:
931 case AR5K_MODE_11G_TURBO:
932 size = 26;
fa1c114f
JS		 933 chfreq = CHANNEL_2GHZ;
934 break;
935 default:
936 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
937 return 0;
938 }
939
940 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 941 ch = i + 1 ;
942 freq = ath5k_ieee2mhz(ch);
fa1c114f 943
d8ee398d
LR		 944 /* Check if channel is supported by the chipset */
945 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 946 continue;
947
42639fcd
BC		 948 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
949 continue;
950
d8ee398d
LR		 951 /* Write channel info and increment counter */
952 channels[count].center_freq = freq;
a3f4b914
LR		 953 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
954 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 955 switch (mode) {
956 case AR5K_MODE_11A:
957 case AR5K_MODE_11G:
958 channels[count].hw_value = chfreq | CHANNEL_OFDM;
959 break;
960 case AR5K_MODE_11A_TURBO:
961 case AR5K_MODE_11G_TURBO:
962 channels[count].hw_value = chfreq |
963 CHANNEL_OFDM | CHANNEL_TURBO;
964 break;
965 case AR5K_MODE_11B:
d8ee398d
LR		 966 channels[count].hw_value = CHANNEL_B;
967 }
fa1c114f 968
fa1c114f
JS		 969 count++;
970 max--;
971 }
972
973 return count;
974}
975
63266a65
BR		 976static void
977ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
978{
979 u8 i;
980
981 for (i = 0; i < AR5K_MAX_RATES; i++)
982 sc->rate_idx[b->band][i] = -1;
983
984 for (i = 0; i < b->n_bitrates; i++) {
985 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
986 if (b->bitrates[i].hw_value_short)
987 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
988 }
989}
990
d8ee398d 991static int
63266a65 992ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 993{
994 struct ath5k_softc *sc = hw->priv;
d8ee398d 995 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 996 struct ieee80211_supported_band *sband;
997 int max_c, count_c = 0;
998 int i;
fa1c114f 999
d8ee398d 1000 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1001 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1002
1003 /* 2GHz band */
63266a65
BR		 1004 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1005 sband->band = IEEE80211_BAND_2GHZ;
1006 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1007
63266a65
BR		 1008 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1009 /* G mode */
1010 memcpy(sband->bitrates, &ath5k_rates[0],
1011 sizeof(struct ieee80211_rate) * 12);
1012 sband->n_bitrates = 12;
fa1c114f 1013
d8ee398d 1014 sband->channels = sc->channels;
d8ee398d 1015 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1016 AR5K_MODE_11G, max_c);
fa1c114f 1017
63266a65 1018 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1019 count_c = sband->n_channels;
63266a65
BR		 1020 max_c -= count_c;
1021 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1022 /* B mode */
1023 memcpy(sband->bitrates, &ath5k_rates[0],
1024 sizeof(struct ieee80211_rate) * 4);
1025 sband->n_bitrates = 4;
1026
1027 /* 5211 only supports B rates and uses 4bit rate codes
1028 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1029 * fix them up here:
1030 */
1031 if (ah->ah_version == AR5K_AR5211) {
1032 for (i = 0; i < 4; i++) {
1033 sband->bitrates[i].hw_value =
1034 sband->bitrates[i].hw_value & 0xF;
1035 sband->bitrates[i].hw_value_short =
1036 sband->bitrates[i].hw_value_short & 0xF;
1037 }
1038 }
fa1c114f 1039
63266a65
BR		 1040 sband->channels = sc->channels;
1041 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1042 AR5K_MODE_11B, max_c);
d8ee398d 1043
63266a65
BR		 1044 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1045 count_c = sband->n_channels;
d8ee398d 1046 max_c -= count_c;
fa1c114f 1047 }
63266a65 1048 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1049
63266a65 1050 /* 5GHz band, A mode */
400ec45a 1051 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1052 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1053 sband->band = IEEE80211_BAND_5GHZ;
1054 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1055
63266a65
BR		 1056 memcpy(sband->bitrates, &ath5k_rates[4],
1057 sizeof(struct ieee80211_rate) * 8);
1058 sband->n_bitrates = 8;
fa1c114f 1059
63266a65 1060 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1061 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1062 AR5K_MODE_11A, max_c);
1063
d8ee398d
LR		 1064 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1065 }
63266a65 1066 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1067
b446197c 1068 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1069
1070 return 0;
fa1c114f
JS		 1071}
1072
1073/*
1074 * Set/change channels. If the channel is really being changed,
1075 * it's done by reseting the chip. To accomplish this we must
1076 * first cleanup any pending DMA, then restart stuff after a la
1077 * ath5k_init.
be009370
BC		 1078 *
1079 * Called with sc->lock.
fa1c114f
JS		 1080 */
1081static int
1082ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1083{
d8ee398d
LR		 1084 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1085 sc->curchan->center_freq, chan->center_freq);
1086
1087 if (chan->center_freq != sc->curchan->center_freq ||
1088 chan->hw_value != sc->curchan->hw_value) {
1089
fa1c114f
JS		 1090 /*
1091 * To switch channels clear any pending DMA operations;
1092 * wait long enough for the RX fifo to drain, reset the
1093 * hardware at the new frequency, and then re-enable
1094 * the relevant bits of the h/w.
1095 */
209d889b 1096 return ath5k_reset(sc, chan);
fa1c114f
JS		 1097 }
1098
1099 return 0;
1100}
1101
1102static void
1103ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1104{
fa1c114f 1105 sc->curmode = mode;
d8ee398d 1106
400ec45a 1107 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1108 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1109 } else {
1110 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1111 }
fa1c114f
JS		 1112}
1113
1114static void
1115ath5k_mode_setup(struct ath5k_softc *sc)
1116{
1117 struct ath5k_hw *ah = sc->ah;
1118 u32 rfilt;
1119
1120 /* configure rx filter */
1121 rfilt = sc->filter_flags;
1122 ath5k_hw_set_rx_filter(ah, rfilt);
1123
1124 if (ath5k_hw_hasbssidmask(ah))
1125 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1126
1127 /* configure operational mode */
1128 ath5k_hw_set_opmode(ah);
1129
1130 ath5k_hw_set_mcast_filter(ah, 0, 0);
1131 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1132}
1133
d8ee398d 1134static inline int
63266a65
BR		 1135ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1136{
b7266047
BC		 1137 int rix;
1138
1139 /* return base rate on errors */
1140 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1141 "hw_rix out of bounds: %x\n", hw_rix))
1142 return 0;
1143
1144 rix = sc->rate_idx[sc->curband->band][hw_rix];
1145 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1146 rix = 0;
1147
1148 return rix;
d8ee398d
LR		 1149}
1150
fa1c114f
JS		 1151/***************\
1152* Buffers setup *
1153\***************/
1154
b6ea0356
BC		 1155static
1156struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1157{
1158 struct sk_buff *skb;
1159 unsigned int off;
1160
1161 /*
1162 * Allocate buffer with headroom_needed space for the
1163 * fake physical layer header at the start.
1164 */
1165 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1166
1167 if (!skb) {
1168 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1169 sc->rxbufsize + sc->cachelsz - 1);
1170 return NULL;
1171 }
1172 /*
1173 * Cache-line-align. This is important (for the
1174 * 5210 at least) as not doing so causes bogus data
1175 * in rx'd frames.
1176 */
1177 off = ((unsigned long)skb->data) % sc->cachelsz;
1178 if (off != 0)
1179 skb_reserve(skb, sc->cachelsz - off);
1180
1181 *skb_addr = pci_map_single(sc->pdev,
1182 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1183 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1184 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1185 dev_kfree_skb(skb);
1186 return NULL;
1187 }
1188 return skb;
1189}
1190
fa1c114f
JS		 1191static int
1192ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1193{
1194 struct ath5k_hw *ah = sc->ah;
1195 struct sk_buff *skb = bf->skb;
1196 struct ath5k_desc *ds;
1197
b6ea0356
BC		 1198 if (!skb) {
1199 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1200 if (!skb)
fa1c114f 1201 return -ENOMEM;
fa1c114f 1202 bf->skb = skb;
fa1c114f
JS		 1203 }
1204
1205 /*
1206 * Setup descriptors. For receive we always terminate
1207 * the descriptor list with a self-linked entry so we'll
1208 * not get overrun under high load (as can happen with a
1209 * 5212 when ANI processing enables PHY error frames).
1210 *
1211 * To insure the last descriptor is self-linked we create
1212 * each descriptor as self-linked and add it to the end. As
1213 * each additional descriptor is added the previous self-linked
1214 * entry is ``fixed'' naturally. This should be safe even
1215 * if DMA is happening. When processing RX interrupts we
1216 * never remove/process the last, self-linked, entry on the
1217 * descriptor list. This insures the hardware always has
1218 * someplace to write a new frame.
1219 */
1220 ds = bf->desc;
1221 ds->ds_link = bf->daddr; /* link to self */
1222 ds->ds_data = bf->skbaddr;
c6e387a2 1223 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1224 skb_tailroom(skb), /* buffer size */
1225 0);
1226
1227 if (sc->rxlink != NULL)
1228 *sc->rxlink = bf->daddr;
1229 sc->rxlink = &ds->ds_link;
1230 return 0;
1231}
1232
1233static int
cec8db23
BC		 1234ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1235 struct ath5k_txq *txq)
fa1c114f
JS		 1236{
1237 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1238 struct ath5k_desc *ds = bf->desc;
1239 struct sk_buff *skb = bf->skb;
a888d52d 1240 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1241 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1242 struct ieee80211_rate *rate;
1243 unsigned int mrr_rate[3], mrr_tries[3];
1244 int i, ret;
8902ff4e 1245 u16 hw_rate;
07c1e852
BC		 1246 u16 cts_rate = 0;
1247 u16 duration = 0;
8902ff4e 1248 u8 rc_flags;
fa1c114f
JS		 1249
1250 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1251
fa1c114f
JS		 1252 /* XXX endianness */
1253 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1254 PCI_DMA_TODEVICE);
1255
8902ff4e
BC		 1256 rate = ieee80211_get_tx_rate(sc->hw, info);
1257
e039fa4a 1258 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1259 flags |= AR5K_TXDESC_NOACK;
1260
8902ff4e
BC		 1261 rc_flags = info->control.rates[0].flags;
1262 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1263 rate->hw_value_short : rate->hw_value;
1264
281c56dd 1265 pktlen = skb->len;
fa1c114f 1266
8f655dde
NK		 1267 /* FIXME: If we are in g mode and rate is a CCK rate
1268 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1269 * from tx power (value is in dB units already) */
362695e1
BC		 1270 if (info->control.hw_key) {
1271 keyidx = info->control.hw_key->hw_key_idx;
1272 pktlen += info->control.hw_key->icv_len;
1273 }
07c1e852
BC		 1274 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1275 flags |= AR5K_TXDESC_RTSENA;
1276 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1277 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1278 sc->vif, pktlen, info));
1279 }
1280 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1281 flags |= AR5K_TXDESC_CTSENA;
1282 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1283 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1284 sc->vif, pktlen, info));
1285 }
fa1c114f
JS		 1286 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1287 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1288 (sc->power_level * 2),
8902ff4e 1289 hw_rate,
2bed03eb 1290 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1291 cts_rate, duration);
fa1c114f
JS		 1292 if (ret)
1293 goto err_unmap;
1294
2f7fe870
FF		 1295 memset(mrr_rate, 0, sizeof(mrr_rate));
1296 memset(mrr_tries, 0, sizeof(mrr_tries));
1297 for (i = 0; i < 3; i++) {
1298 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1299 if (!rate)
1300 break;
1301
1302 mrr_rate[i] = rate->hw_value;
e6a9854b 1303 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1304 }
1305
1306 ah->ah_setup_mrr_tx_desc(ah, ds,
1307 mrr_rate[0], mrr_tries[0],
1308 mrr_rate[1], mrr_tries[1],
1309 mrr_rate[2], mrr_tries[2]);
1310
fa1c114f
JS		 1311 ds->ds_link = 0;
1312 ds->ds_data = bf->skbaddr;
1313
1314 spin_lock_bh(&txq->lock);
1315 list_add_tail(&bf->list, &txq->q);
57ffc589 1316 sc->tx_stats[txq->qnum].len++;
fa1c114f 1317 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1318 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1319 else /* no, so only link it */
1320 *txq->link = bf->daddr;
1321
1322 txq->link = &ds->ds_link;
c6e387a2 1323 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1324 mmiowb();
fa1c114f
JS		 1325 spin_unlock_bh(&txq->lock);
1326
1327 return 0;
1328err_unmap:
1329 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1330 return ret;
1331}
1332
1333/*******************\
1334* Descriptors setup *
1335\*******************/
1336
1337static int
1338ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1339{
1340 struct ath5k_desc *ds;
1341 struct ath5k_buf *bf;
1342 dma_addr_t da;
1343 unsigned int i;
1344 int ret;
1345
1346 /* allocate descriptors */
1347 sc->desc_len = sizeof(struct ath5k_desc) *
1348 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1349 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1350 if (sc->desc == NULL) {
1351 ATH5K_ERR(sc, "can't allocate descriptors\n");
1352 ret = -ENOMEM;
1353 goto err;
1354 }
1355 ds = sc->desc;
1356 da = sc->desc_daddr;
1357 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1358 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1359
1360 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1361 sizeof(struct ath5k_buf), GFP_KERNEL);
1362 if (bf == NULL) {
1363 ATH5K_ERR(sc, "can't allocate bufptr\n");
1364 ret = -ENOMEM;
1365 goto err_free;
1366 }
1367 sc->bufptr = bf;
1368
1369 INIT_LIST_HEAD(&sc->rxbuf);
1370 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1371 bf->desc = ds;
1372 bf->daddr = da;
1373 list_add_tail(&bf->list, &sc->rxbuf);
1374 }
1375
1376 INIT_LIST_HEAD(&sc->txbuf);
1377 sc->txbuf_len = ATH_TXBUF;
1378 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1379 da += sizeof(*ds)) {
1380 bf->desc = ds;
1381 bf->daddr = da;
1382 list_add_tail(&bf->list, &sc->txbuf);
1383 }
1384
1385 /* beacon buffer */
1386 bf->desc = ds;
1387 bf->daddr = da;
1388 sc->bbuf = bf;
1389
1390 return 0;
1391err_free:
1392 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1393err:
1394 sc->desc = NULL;
1395 return ret;
1396}
1397
1398static void
1399ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1400{
1401 struct ath5k_buf *bf;
1402
1403 ath5k_txbuf_free(sc, sc->bbuf);
1404 list_for_each_entry(bf, &sc->txbuf, list)
1405 ath5k_txbuf_free(sc, bf);
1406 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1407 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1408
1409 /* Free memory associated with all descriptors */
1410 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1411
1412 kfree(sc->bufptr);
1413 sc->bufptr = NULL;
1414}
1415
1416
1417
1418
1419
1420/**************\
1421* Queues setup *
1422\**************/
1423
1424static struct ath5k_txq *
1425ath5k_txq_setup(struct ath5k_softc *sc,
1426 int qtype, int subtype)
1427{
1428 struct ath5k_hw *ah = sc->ah;
1429 struct ath5k_txq *txq;
1430 struct ath5k_txq_info qi = {
1431 .tqi_subtype = subtype,
1432 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1433 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1434 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1435 };
1436 int qnum;
1437
1438 /*
1439 * Enable interrupts only for EOL and DESC conditions.
1440 * We mark tx descriptors to receive a DESC interrupt
1441 * when a tx queue gets deep; otherwise waiting for the
1442 * EOL to reap descriptors. Note that this is done to
1443 * reduce interrupt load and this only defers reaping
1444 * descriptors, never transmitting frames. Aside from
1445 * reducing interrupts this also permits more concurrency.
1446 * The only potential downside is if the tx queue backs
1447 * up in which case the top half of the kernel may backup
1448 * due to a lack of tx descriptors.
1449 */
1450 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1451 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1452 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1453 if (qnum < 0) {
1454 /*
1455 * NB: don't print a message, this happens
1456 * normally on parts with too few tx queues
1457 */
1458 return ERR_PTR(qnum);
1459 }
1460 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1461 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1462 qnum, ARRAY_SIZE(sc->txqs));
1463 ath5k_hw_release_tx_queue(ah, qnum);
1464 return ERR_PTR(-EINVAL);
1465 }
1466 txq = &sc->txqs[qnum];
1467 if (!txq->setup) {
1468 txq->qnum = qnum;
1469 txq->link = NULL;
1470 INIT_LIST_HEAD(&txq->q);
1471 spin_lock_init(&txq->lock);
1472 txq->setup = true;
1473 }
1474 return &sc->txqs[qnum];
1475}
1476
1477static int
1478ath5k_beaconq_setup(struct ath5k_hw *ah)
1479{
1480 struct ath5k_txq_info qi = {
1481 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1482 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1483 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1484 /* NB: for dynamic turbo, don't enable any other interrupts */
1485 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1486 };
1487
1488 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1489}
1490
1491static int
1492ath5k_beaconq_config(struct ath5k_softc *sc)
1493{
1494 struct ath5k_hw *ah = sc->ah;
1495 struct ath5k_txq_info qi;
1496 int ret;
1497
1498 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1499 if (ret)
1500 return ret;
05c914fe
JB		 1501 if (sc->opmode == NL80211_IFTYPE_AP ||
1502 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1503 /*
1504 * Always burst out beacon and CAB traffic
1505 * (aifs = cwmin = cwmax = 0)
1506 */
1507 qi.tqi_aifs = 0;
1508 qi.tqi_cw_min = 0;
1509 qi.tqi_cw_max = 0;
05c914fe 1510 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1511 /*
1512 * Adhoc mode; backoff between 0 and (2 * cw_min).
1513 */
1514 qi.tqi_aifs = 0;
1515 qi.tqi_cw_min = 0;
1516 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1517 }
1518
6d91e1d8
BR		 1519 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1520 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1521 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1522
c6e387a2 1523 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1524 if (ret) {
1525 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1526 "hardware queue!\n", __func__);
1527 return ret;
1528 }
1529
1530 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1531}
1532
1533static void
1534ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1535{
1536 struct ath5k_buf *bf, *bf0;
1537
1538 /*
1539 * NB: this assumes output has been stopped and
1540 * we do not need to block ath5k_tx_tasklet
1541 */
1542 spin_lock_bh(&txq->lock);
1543 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1544 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1545
1546 ath5k_txbuf_free(sc, bf);
1547
1548 spin_lock_bh(&sc->txbuflock);
57ffc589 1549 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1550 list_move_tail(&bf->list, &sc->txbuf);
1551 sc->txbuf_len++;
1552 spin_unlock_bh(&sc->txbuflock);
1553 }
1554 txq->link = NULL;
1555 spin_unlock_bh(&txq->lock);
1556}
1557
1558/*
1559 * Drain the transmit queues and reclaim resources.
1560 */
1561static void
1562ath5k_txq_cleanup(struct ath5k_softc *sc)
1563{
1564 struct ath5k_hw *ah = sc->ah;
1565 unsigned int i;
1566
1567 /* XXX return value */
1568 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1569 /* don't touch the hardware if marked invalid */
1570 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1571 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1572 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1573 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1574 if (sc->txqs[i].setup) {
1575 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1576 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1577 "link %p\n",
1578 sc->txqs[i].qnum,
c6e387a2 1579 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1580 sc->txqs[i].qnum),
1581 sc->txqs[i].link);
1582 }
1583 }
36d6825b 1584 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1585
1586 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1587 if (sc->txqs[i].setup)
1588 ath5k_txq_drainq(sc, &sc->txqs[i]);
1589}
1590
1591static void
1592ath5k_txq_release(struct ath5k_softc *sc)
1593{
1594 struct ath5k_txq *txq = sc->txqs;
1595 unsigned int i;
1596
1597 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1598 if (txq->setup) {
1599 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1600 txq->setup = false;
1601 }
1602}
1603
1604
1605
1606
1607/*************\
1608* RX Handling *
1609\*************/
1610
1611/*
1612 * Enable the receive h/w following a reset.
1613 */
1614static int
1615ath5k_rx_start(struct ath5k_softc *sc)
1616{
1617 struct ath5k_hw *ah = sc->ah;
1618 struct ath5k_buf *bf;
1619 int ret;
1620
1621 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1622
1623 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1624 sc->cachelsz, sc->rxbufsize);
1625
fa1c114f 1626 spin_lock_bh(&sc->rxbuflock);
26925042 1627 sc->rxlink = NULL;
fa1c114f
JS		 1628 list_for_each_entry(bf, &sc->rxbuf, list) {
1629 ret = ath5k_rxbuf_setup(sc, bf);
1630 if (ret != 0) {
1631 spin_unlock_bh(&sc->rxbuflock);
1632 goto err;
1633 }
1634 }
1635 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1636 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1637 spin_unlock_bh(&sc->rxbuflock);
1638
c6e387a2 1639 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1640 ath5k_mode_setup(sc); /* set filters, etc. */
1641 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1642
1643 return 0;
1644err:
1645 return ret;
1646}
1647
1648/*
1649 * Disable the receive h/w in preparation for a reset.
1650 */
1651static void
1652ath5k_rx_stop(struct ath5k_softc *sc)
1653{
1654 struct ath5k_hw *ah = sc->ah;
1655
c6e387a2 1656 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1657 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1658 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1659
1660 ath5k_debug_printrxbuffs(sc, ah);
1661
1662 sc->rxlink = NULL; /* just in case */
1663}
1664
1665static unsigned int
1666ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1667 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1668{
1669 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1670 unsigned int keyix, hlen;
fa1c114f 1671
b47f407b
BR		 1672 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1673 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1674 return RX_FLAG_DECRYPTED;
1675
1676 /* Apparently when a default key is used to decrypt the packet
1677 the hw does not set the index used to decrypt. In such cases
1678 get the index from the packet. */
798ee985 1679 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1680 if (ieee80211_has_protected(hdr->frame_control) &&
1681 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1682 skb->len >= hlen + 4) {
fa1c114f
JS		 1683 keyix = skb->data[hlen + 3] >> 6;
1684
1685 if (test_bit(keyix, sc->keymap))
1686 return RX_FLAG_DECRYPTED;
1687 }
1688
1689 return 0;
1690}
1691
036cd1ec
BR		 1692
1693static void
6ba81c2c
BR		 1694ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1695 struct ieee80211_rx_status *rxs)
036cd1ec 1696{
6ba81c2c 1697 u64 tsf, bc_tstamp;
036cd1ec
BR		 1698 u32 hw_tu;
1699 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1700
24b56e70 1701 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1702 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1703 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1704 /*
6ba81c2c
BR		 1705 * Received an IBSS beacon with the same BSSID. Hardware *must*
1706 * have updated the local TSF. We have to work around various
1707 * hardware bugs, though...
036cd1ec 1708 */
6ba81c2c
BR		 1709 tsf = ath5k_hw_get_tsf64(sc->ah);
1710 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1711 hw_tu = TSF_TO_TU(tsf);
1712
1713 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1714 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1715 (unsigned long long)bc_tstamp,
1716 (unsigned long long)rxs->mactime,
1717 (unsigned long long)(rxs->mactime - bc_tstamp),
1718 (unsigned long long)tsf);
6ba81c2c
BR		 1719
1720 /*
1721 * Sometimes the HW will give us a wrong tstamp in the rx
1722 * status, causing the timestamp extension to go wrong.
1723 * (This seems to happen especially with beacon frames bigger
1724 * than 78 byte (incl. FCS))
1725 * But we know that the receive timestamp must be later than the
1726 * timestamp of the beacon since HW must have synced to that.
1727 *
1728 * NOTE: here we assume mactime to be after the frame was
1729 * received, not like mac80211 which defines it at the start.
1730 */
1731 if (bc_tstamp > rxs->mactime) {
036cd1ec 1732 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1733 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1734 (unsigned long long)rxs->mactime,
1735 (unsigned long long)tsf);
6ba81c2c 1736 rxs->mactime = tsf;
036cd1ec 1737 }
6ba81c2c
BR		 1738
1739 /*
1740 * Local TSF might have moved higher than our beacon timers,
1741 * in that case we have to update them to continue sending
1742 * beacons. This also takes care of synchronizing beacon sending
1743 * times with other stations.
1744 */
1745 if (hw_tu >= sc->nexttbtt)
1746 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1747 }
1748}
1749
fa1c114f
JS		 1750static void
1751ath5k_tasklet_rx(unsigned long data)
1752{
1753 struct ieee80211_rx_status rxs = {};
b47f407b 1754 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1755 struct sk_buff *skb, *next_skb;
1756 dma_addr_t next_skb_addr;
fa1c114f 1757 struct ath5k_softc *sc = (void *)data;
c57ca815 1758 struct ath5k_buf *bf;
fa1c114f 1759 struct ath5k_desc *ds;
fa1c114f
JS		 1760 int ret;
1761 int hdrlen;
0fe45b1d 1762 int padsize;
fa1c114f
JS		 1763
1764 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1765 if (list_empty(&sc->rxbuf)) {
1766 ATH5K_WARN(sc, "empty rx buf pool\n");
1767 goto unlock;
1768 }
fa1c114f 1769 do {
d6894b5b
BC		 1770 rxs.flag = 0;
1771
fa1c114f
JS		 1772 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1773 BUG_ON(bf->skb == NULL);
1774 skb = bf->skb;
1775 ds = bf->desc;
1776
c57ca815
BC		 1777 /* bail if HW is still using self-linked descriptor */
1778 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1779 break;
fa1c114f 1780
b47f407b 1781 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1782 if (unlikely(ret == -EINPROGRESS))
1783 break;
1784 else if (unlikely(ret)) {
1785 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1786 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1787 return;
1788 }
1789
b47f407b 1790 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1791 ATH5K_WARN(sc, "unsupported jumbo\n");
1792 goto next;
1793 }
1794
b47f407b
BR		 1795 if (unlikely(rs.rs_status)) {
1796 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1797 goto next;
b47f407b 1798 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1799 /*
1800 * Decrypt error. If the error occurred
1801 * because there was no hardware key, then
1802 * let the frame through so the upper layers
1803 * can process it. This is necessary for 5210
1804 * parts which have no way to setup a ``clear''
1805 * key cache entry.
1806 *
1807 * XXX do key cache faulting
1808 */
b47f407b
BR		 1809 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1810 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1811 goto accept;
1812 }
b47f407b 1813 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1814 rxs.flag |= RX_FLAG_MMIC_ERROR;
1815 goto accept;
1816 }
1817
1818 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1819 if ((rs.rs_status &
1820 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1821 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1822 goto next;
1823 }
1824accept:
b6ea0356
BC		 1825 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1826
1827 /*
1828 * If we can't replace bf->skb with a new skb under memory
1829 * pressure, just skip this packet
1830 */
1831 if (!next_skb)
1832 goto next;
1833
fa1c114f
JS		 1834 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1835 PCI_DMA_FROMDEVICE);
b47f407b 1836 skb_put(skb, rs.rs_datalen);
fa1c114f 1837
0fe45b1d
BP		 1838 /* The MAC header is padded to have 32-bit boundary if the
1839 * packet payload is non-zero. The general calculation for
1840 * padsize would take into account odd header lengths:
1841 * padsize = (4 - hdrlen % 4) % 4; However, since only
1842 * even-length headers are used, padding can only be 0 or 2
1843 * bytes and we can optimize this a bit. In addition, we must
1844 * not try to remove padding from short control frames that do
1845 * not have payload. */
fa1c114f 1846 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1847 padsize = ath5k_pad_size(hdrlen);
1848 if (padsize) {
0fe45b1d
BP		 1849 memmove(skb->data + padsize, skb->data, hdrlen);
1850 skb_pull(skb, padsize);
fa1c114f
JS		 1851 }
1852
c0e1899b
BR		 1853 /*
1854 * always extend the mac timestamp, since this information is
1855 * also needed for proper IBSS merging.
1856 *
1857 * XXX: it might be too late to do it here, since rs_tstamp is
1858 * 15bit only. that means TSF extension has to be done within
1859 * 32768usec (about 32ms). it might be necessary to move this to
1860 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1861 *
1862 * Unfortunately we don't know when the hardware takes the rx
1863 * timestamp (beginning of phy frame, data frame, end of rx?).
1864 * The only thing we know is that it is hardware specific...
1865 * On AR5213 it seems the rx timestamp is at the end of the
1866 * frame, but i'm not sure.
1867 *
1868 * NOTE: mac80211 defines mactime at the beginning of the first
1869 * data symbol. Since we don't have any time references it's
1870 * impossible to comply to that. This affects IBSS merge only
1871 * right now, so it's not too bad...
c0e1899b 1872 */
b47f407b 1873 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1874 rxs.flag |= RX_FLAG_TSFT;
1875
d8ee398d
LR		 1876 rxs.freq = sc->curchan->center_freq;
1877 rxs.band = sc->curband->band;
fa1c114f 1878
fa1c114f 1879 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1880 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1881
1882 /* An rssi of 35 indicates you should be able use
1883 * 54 Mbps reliably. A more elaborate scheme can be used
1884 * here but it requires a map of SNR/throughput for each
1885 * possible mode used */
1886 rxs.qual = rs.rs_rssi * 100 / 35;
1887
1888 /* rssi can be more than 35 though, anything above that
1889 * should be considered at 100% */
1890 if (rxs.qual > 100)
1891 rxs.qual = 100;
fa1c114f 1892
b47f407b
BR		 1893 rxs.antenna = rs.rs_antenna;
1894 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1895 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1896
06303352
BR		 1897 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1898 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1899 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1900
fa1c114f
JS		 1901 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1902
036cd1ec 1903 /* check beacons in IBSS mode */
05c914fe 1904 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1905 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1906
f1d58c25
JB		 1907 memcpy(IEEE80211_SKB_RXCB(skb), &rxs, sizeof(rxs));
1908 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 1909
1910 bf->skb = next_skb;
1911 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1912next:
1913 list_move_tail(&bf->list, &sc->rxbuf);
1914 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1915unlock:
fa1c114f
JS		 1916 spin_unlock(&sc->rxbuflock);
1917}
1918
1919
1920
1921
1922/*************\
1923* TX Handling *
1924\*************/
1925
1926static void
1927ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1928{
b47f407b 1929 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1930 struct ath5k_buf *bf, *bf0;
1931 struct ath5k_desc *ds;
1932 struct sk_buff *skb;
e039fa4a 1933 struct ieee80211_tx_info *info;
2f7fe870 1934 int i, ret;
fa1c114f
JS		 1935
1936 spin_lock(&txq->lock);
1937 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1938 ds = bf->desc;
1939
b47f407b 1940 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1941 if (unlikely(ret == -EINPROGRESS))
1942 break;
1943 else if (unlikely(ret)) {
1944 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1945 ret, txq->qnum);
1946 break;
1947 }
1948
1949 skb = bf->skb;
a888d52d 1950 info = IEEE80211_SKB_CB(skb);
fa1c114f 1951 bf->skb = NULL;
e039fa4a 1952
fa1c114f
JS		 1953 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1954 PCI_DMA_TODEVICE);
1955
e6a9854b 1956 ieee80211_tx_info_clear_status(info);
2f7fe870 1957 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1958 struct ieee80211_tx_rate *r =
1959 &info->status.rates[i];
2f7fe870
FF		 1960
1961 if (ts.ts_rate[i]) {
e6a9854b
JB		 1962 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1963 r->count = ts.ts_retry[i];
2f7fe870 1964 } else {
e6a9854b
JB		 1965 r->idx = -1;
1966 r->count = 0;
2f7fe870
FF		 1967 }
1968 }
1969
e6a9854b
JB		 1970 /* count the successful attempt as well */
1971 info->status.rates[ts.ts_final_idx].count++;
1972
b47f407b 1973 if (unlikely(ts.ts_status)) {
fa1c114f 1974 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1975 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1976 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1977 } else {
e039fa4a
JB		 1978 info->flags |= IEEE80211_TX_STAT_ACK;
1979 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1980 }
1981
e039fa4a 1982 ieee80211_tx_status(sc->hw, skb);
57ffc589 1983 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1984
1985 spin_lock(&sc->txbuflock);
57ffc589 1986 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1987 list_move_tail(&bf->list, &sc->txbuf);
1988 sc->txbuf_len++;
1989 spin_unlock(&sc->txbuflock);
1990 }
1991 if (likely(list_empty(&txq->q)))
1992 txq->link = NULL;
1993 spin_unlock(&txq->lock);
1994 if (sc->txbuf_len > ATH_TXBUF / 5)
1995 ieee80211_wake_queues(sc->hw);
1996}
1997
1998static void
1999ath5k_tasklet_tx(unsigned long data)
2000{
2001 struct ath5k_softc *sc = (void *)data;
2002
2003 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 2004}
2005
2006
fa1c114f
JS		 2007/*****************\
2008* Beacon handling *
2009\*****************/
2010
2011/*
2012 * Setup the beacon frame for transmit.
2013 */
2014static int
e039fa4a 2015ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2016{
2017 struct sk_buff *skb = bf->skb;
a888d52d 2018 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2019 struct ath5k_hw *ah = sc->ah;
2020 struct ath5k_desc *ds;
2bed03eb
NK		 2021 int ret = 0;
2022 u8 antenna;
fa1c114f
JS		 2023 u32 flags;
2024
2025 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2026 PCI_DMA_TODEVICE);
2027 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2028 "skbaddr %llx\n", skb, skb->data, skb->len,
2029 (unsigned long long)bf->skbaddr);
8d8bb39b 2030 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2031 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2032 return -EIO;
2033 }
2034
2035 ds = bf->desc;
2bed03eb 2036 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2037
2038 flags = AR5K_TXDESC_NOACK;
05c914fe 2039 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2040 ds->ds_link = bf->daddr; /* self-linked */
2041 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2042 } else
fa1c114f 2043 ds->ds_link = 0;
2bed03eb
NK		 2044
2045 /*
2046 * If we use multiple antennas on AP and use
2047 * the Sectored AP scenario, switch antenna every
2048 * 4 beacons to make sure everybody hears our AP.
2049 * When a client tries to associate, hw will keep
2050 * track of the tx antenna to be used for this client
2051 * automaticaly, based on ACKed packets.
2052 *
2053 * Note: AP still listens and transmits RTS on the
2054 * default antenna which is supposed to be an omni.
2055 *
2056 * Note2: On sectored scenarios it's possible to have
2057 * multiple antennas (1omni -the default- and 14 sectors)
2058 * so if we choose to actually support this mode we need
2059 * to allow user to set how many antennas we have and tweak
2060 * the code below to send beacons on all of them.
2061 */
2062 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2063 antenna = sc->bsent & 4 ? 2 : 1;
2064
fa1c114f 2065
8f655dde
NK		 2066 /* FIXME: If we are in g mode and rate is a CCK rate
2067 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2068 * from tx power (value is in dB units already) */
fa1c114f 2069 ds->ds_data = bf->skbaddr;
281c56dd 2070 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2071 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2072 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2073 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2074 1, AR5K_TXKEYIX_INVALID,
400ec45a 2075 antenna, flags, 0, 0);
fa1c114f
JS		 2076 if (ret)
2077 goto err_unmap;
2078
2079 return 0;
2080err_unmap:
2081 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2082 return ret;
2083}
2084
2085/*
2086 * Transmit a beacon frame at SWBA. Dynamic updates to the
2087 * frame contents are done as needed and the slot time is
2088 * also adjusted based on current state.
2089 *
acf3c1a5
BC		 2090 * This is called from software irq context (beacontq or restq
2091 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2092 */
2093static void
2094ath5k_beacon_send(struct ath5k_softc *sc)
2095{
2096 struct ath5k_buf *bf = sc->bbuf;
2097 struct ath5k_hw *ah = sc->ah;
cec8db23 2098 struct sk_buff *skb;
fa1c114f 2099
be9b7259 2100 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2101
05c914fe
JB		 2102 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2103 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2104 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2105 return;
2106 }
2107 /*
2108 * Check if the previous beacon has gone out. If
2109 * not don't don't try to post another, skip this
2110 * period and wait for the next. Missed beacons
2111 * indicate a problem and should not occur. If we
2112 * miss too many consecutive beacons reset the device.
2113 */
2114 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2115 sc->bmisscount++;
be9b7259 2116 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2117 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2118 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2119 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2120 "stuck beacon time (%u missed)\n",
2121 sc->bmisscount);
2122 tasklet_schedule(&sc->restq);
2123 }
2124 return;
2125 }
2126 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2127 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2128 "resume beacon xmit after %u misses\n",
2129 sc->bmisscount);
2130 sc->bmisscount = 0;
2131 }
2132
2133 /*
2134 * Stop any current dma and put the new frame on the queue.
2135 * This should never fail since we check above that no frames
2136 * are still pending on the queue.
2137 */
2138 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2139 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2140 /* NB: hw still stops DMA, so proceed */
2141 }
fa1c114f 2142
1071db86
BC		 2143 /* refresh the beacon for AP mode */
2144 if (sc->opmode == NL80211_IFTYPE_AP)
2145 ath5k_beacon_update(sc->hw, sc->vif);
2146
c6e387a2
NK		 2147 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2148 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2149 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2150 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2151
cec8db23
BC		 2152 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2153 while (skb) {
2154 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2155 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2156 }
2157
fa1c114f
JS		 2158 sc->bsent++;
2159}
2160
2161
9804b98d
BR		 2162/**
2163 * ath5k_beacon_update_timers - update beacon timers
2164 *
2165 * @sc: struct ath5k_softc pointer we are operating on
2166 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2167 * beacon timer update based on the current HW TSF.
2168 *
2169 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2170 * of a received beacon or the current local hardware TSF and write it to the
2171 * beacon timer registers.
2172 *
2173 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2174 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2175 * when we otherwise know we have to update the timers, but we keep it in this
2176 * function to have it all together in one place.
2177 */
fa1c114f 2178static void
9804b98d 2179ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2180{
2181 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2182 u32 nexttbtt, intval, hw_tu, bc_tu;
2183 u64 hw_tsf;
fa1c114f
JS		 2184
2185 intval = sc->bintval & AR5K_BEACON_PERIOD;
2186 if (WARN_ON(!intval))
2187 return;
2188
9804b98d
BR		 2189 /* beacon TSF converted to TU */
2190 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2191
9804b98d
BR		 2192 /* current TSF converted to TU */
2193 hw_tsf = ath5k_hw_get_tsf64(ah);
2194 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2195
9804b98d
BR		 2196#define FUDGE 3
2197 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2198 if (bc_tsf == -1) {
2199 /*
2200 * no beacons received, called internally.
2201 * just need to refresh timers based on HW TSF.
2202 */
2203 nexttbtt = roundup(hw_tu + FUDGE, intval);
2204 } else if (bc_tsf == 0) {
2205 /*
2206 * no beacon received, probably called by ath5k_reset_tsf().
2207 * reset TSF to start with 0.
2208 */
2209 nexttbtt = intval;
2210 intval |= AR5K_BEACON_RESET_TSF;
2211 } else if (bc_tsf > hw_tsf) {
2212 /*
2213 * beacon received, SW merge happend but HW TSF not yet updated.
2214 * not possible to reconfigure timers yet, but next time we
2215 * receive a beacon with the same BSSID, the hardware will
2216 * automatically update the TSF and then we need to reconfigure
2217 * the timers.
2218 */
2219 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2220 "need to wait for HW TSF sync\n");
2221 return;
2222 } else {
2223 /*
2224 * most important case for beacon synchronization between STA.
2225 *
2226 * beacon received and HW TSF has been already updated by HW.
2227 * update next TBTT based on the TSF of the beacon, but make
2228 * sure it is ahead of our local TSF timer.
2229 */
2230 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2231 }
2232#undef FUDGE
fa1c114f 2233
036cd1ec
BR		 2234 sc->nexttbtt = nexttbtt;
2235
fa1c114f 2236 intval |= AR5K_BEACON_ENA;
fa1c114f 2237 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2238
2239 /*
2240 * debugging output last in order to preserve the time critical aspect
2241 * of this function
2242 */
2243 if (bc_tsf == -1)
2244 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2245 "reconfigured timers based on HW TSF\n");
2246 else if (bc_tsf == 0)
2247 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2248 "reset HW TSF and timers\n");
2249 else
2250 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2251 "updated timers based on beacon TSF\n");
2252
2253 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2254 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2255 (unsigned long long) bc_tsf,
2256 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2257 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2258 intval & AR5K_BEACON_PERIOD,
2259 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2260 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2261}
2262
2263
036cd1ec
BR		 2264/**
2265 * ath5k_beacon_config - Configure the beacon queues and interrupts
2266 *
2267 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2268 *
036cd1ec 2269 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2270 * interrupts to detect TSF updates only.
fa1c114f
JS		 2271 */
2272static void
2273ath5k_beacon_config(struct ath5k_softc *sc)
2274{
2275 struct ath5k_hw *ah = sc->ah;
b5f03956 2276 unsigned long flags;
fa1c114f 2277
21800491 2278 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2279 sc->bmisscount = 0;
dc1968e7 2280 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2281
21800491 2282 if (sc->enable_beacon) {
fa1c114f 2283 /*
036cd1ec
BR		 2284 * In IBSS mode we use a self-linked tx descriptor and let the
2285 * hardware send the beacons automatically. We have to load it
fa1c114f 2286 * only once here.
036cd1ec 2287 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2288 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2289 */
2290 ath5k_beaconq_config(sc);
fa1c114f 2291
036cd1ec
BR		 2292 sc->imask |= AR5K_INT_SWBA;
2293
da966bca 2294 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2295 if (ath5k_hw_hasveol(ah))
da966bca 2296 ath5k_beacon_send(sc);
da966bca
JS		 2297 } else
2298 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2299 } else {
2300 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2301 }
fa1c114f 2302
c6e387a2 2303 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2304 mmiowb();
2305 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2306}
2307
428cbd4f
NK		 2308static void ath5k_tasklet_beacon(unsigned long data)
2309{
2310 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2311
2312 /*
2313 * Software beacon alert--time to send a beacon.
2314 *
2315 * In IBSS mode we use this interrupt just to
2316 * keep track of the next TBTT (target beacon
2317 * transmission time) in order to detect wether
2318 * automatic TSF updates happened.
2319 */
2320 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2321 /* XXX: only if VEOL suppported */
2322 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2323 sc->nexttbtt += sc->bintval;
2324 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2325 "SWBA nexttbtt: %x hw_tu: %x "
2326 "TSF: %llx\n",
2327 sc->nexttbtt,
2328 TSF_TO_TU(tsf),
2329 (unsigned long long) tsf);
2330 } else {
2331 spin_lock(&sc->block);
2332 ath5k_beacon_send(sc);
2333 spin_unlock(&sc->block);
2334 }
2335}
2336
fa1c114f
JS		 2337
2338/********************\
2339* Interrupt handling *
2340\********************/
2341
2342static int
bb2becac 2343ath5k_init(struct ath5k_softc *sc)
fa1c114f 2344{
bc1b32d6
EO		 2345 struct ath5k_hw *ah = sc->ah;
2346 int ret, i;
fa1c114f
JS		 2347
2348 mutex_lock(&sc->lock);
2349
2350 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2351
2352 /*
2353 * Stop anything previously setup. This is safe
2354 * no matter this is the first time through or not.
2355 */
2356 ath5k_stop_locked(sc);
2357
2358 /*
2359 * The basic interface to setting the hardware in a good
2360 * state is ``reset''. On return the hardware is known to
2361 * be powered up and with interrupts disabled. This must
2362 * be followed by initialization of the appropriate bits
2363 * and then setup of the interrupt mask.
2364 */
d8ee398d
LR		 2365 sc->curchan = sc->hw->conf.channel;
2366 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2367 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2368 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
9ca9fb8a 2369 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
209d889b 2370 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2371 if (ret)
2372 goto done;
fa1c114f 2373
e6a3b616
TD		 2374 ath5k_rfkill_hw_start(ah);
2375
bc1b32d6
EO		 2376 /*
2377 * Reset the key cache since some parts do not reset the
2378 * contents on initial power up or resume from suspend.
2379 */
2380 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2381 ath5k_hw_reset_key(ah, i);
2382
fa1c114f 2383 /* Set ack to be sent at low bit-rates */
bc1b32d6 2384 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2385
2386 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2387 msecs_to_jiffies(ath5k_calinterval * 1000)));
2388
2389 ret = 0;
2390done:
274c7c36 2391 mmiowb();
fa1c114f
JS		 2392 mutex_unlock(&sc->lock);
2393 return ret;
2394}
2395
2396static int
2397ath5k_stop_locked(struct ath5k_softc *sc)
2398{
2399 struct ath5k_hw *ah = sc->ah;
2400
2401 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2402 test_bit(ATH_STAT_INVALID, sc->status));
2403
2404 /*
2405 * Shutdown the hardware and driver:
2406 * stop output from above
2407 * disable interrupts
2408 * turn off timers
2409 * turn off the radio
2410 * clear transmit machinery
2411 * clear receive machinery
2412 * drain and release tx queues
2413 * reclaim beacon resources
2414 * power down hardware
2415 *
2416 * Note that some of this work is not possible if the
2417 * hardware is gone (invalid).
2418 */
2419 ieee80211_stop_queues(sc->hw);
2420
2421 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2422 ath5k_led_off(sc);
c6e387a2 2423 ath5k_hw_set_imr(ah, 0);
274c7c36 2424 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2425 }
2426 ath5k_txq_cleanup(sc);
2427 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2428 ath5k_rx_stop(sc);
2429 ath5k_hw_phy_disable(ah);
2430 } else
2431 sc->rxlink = NULL;
2432
2433 return 0;
2434}
2435
2436/*
2437 * Stop the device, grabbing the top-level lock to protect
2438 * against concurrent entry through ath5k_init (which can happen
2439 * if another thread does a system call and the thread doing the
2440 * stop is preempted).
2441 */
2442static int
bb2becac 2443ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2444{
2445 int ret;
2446
2447 mutex_lock(&sc->lock);
2448 ret = ath5k_stop_locked(sc);
2449 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2450 /*
2451 * Set the chip in full sleep mode. Note that we are
2452 * careful to do this only when bringing the interface
2453 * completely to a stop. When the chip is in this state
2454 * it must be carefully woken up or references to
2455 * registers in the PCI clock domain may freeze the bus
2456 * (and system). This varies by chip and is mostly an
2457 * issue with newer parts that go to sleep more quickly.
2458 */
2459 if (sc->ah->ah_mac_srev >= 0x78) {
2460 /*
2461 * XXX
2462 * don't put newer MAC revisions > 7.8 to sleep because
2463 * of the above mentioned problems
2464 */
2465 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2466 "not putting device to sleep\n");
2467 } else {
2468 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2469 "putting device to full sleep\n");
2470 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2471 }
2472 }
2473 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2474
274c7c36 2475 mmiowb();
fa1c114f
JS		 2476 mutex_unlock(&sc->lock);
2477
2478 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2479 tasklet_kill(&sc->rxtq);
2480 tasklet_kill(&sc->txtq);
2481 tasklet_kill(&sc->restq);
acf3c1a5 2482 tasklet_kill(&sc->beacontq);
fa1c114f 2483
e6a3b616
TD		 2484 ath5k_rfkill_hw_stop(sc->ah);
2485
fa1c114f
JS		 2486 return ret;
2487}
2488
2489static irqreturn_t
2490ath5k_intr(int irq, void *dev_id)
2491{
2492 struct ath5k_softc *sc = dev_id;
2493 struct ath5k_hw *ah = sc->ah;
2494 enum ath5k_int status;
2495 unsigned int counter = 1000;
2496
2497 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2498 !ath5k_hw_is_intr_pending(ah)))
2499 return IRQ_NONE;
2500
2501 do {
fa1c114f
JS		 2502 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2503 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2504 status, sc->imask);
fa1c114f
JS		 2505 if (unlikely(status & AR5K_INT_FATAL)) {
2506 /*
2507 * Fatal errors are unrecoverable.
2508 * Typically these are caused by DMA errors.
2509 */
2510 tasklet_schedule(&sc->restq);
2511 } else if (unlikely(status & AR5K_INT_RXORN)) {
2512 tasklet_schedule(&sc->restq);
2513 } else {
2514 if (status & AR5K_INT_SWBA) {
56d2ac76 2515 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2516 }
2517 if (status & AR5K_INT_RXEOL) {
2518 /*
2519 * NB: the hardware should re-read the link when
2520 * RXE bit is written, but it doesn't work at
2521 * least on older hardware revs.
2522 */
2523 sc->rxlink = NULL;
2524 }
2525 if (status & AR5K_INT_TXURN) {
2526 /* bump tx trigger level */
2527 ath5k_hw_update_tx_triglevel(ah, true);
2528 }
4c674c60 2529 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2530 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2531 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2532 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2533 tasklet_schedule(&sc->txtq);
2534 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2535 /* TODO */
fa1c114f
JS		 2536 }
2537 if (status & AR5K_INT_MIB) {
194828a2
NK		 2538 /*
2539 * These stats are also used for ANI i think
2540 * so how about updating them more often ?
2541 */
2542 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f 2543 }
e6a3b616 2544 if (status & AR5K_INT_GPIO)
e6a3b616 2545 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2546
fa1c114f 2547 }
2516baa6 2548 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2549
2550 if (unlikely(!counter))
2551 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2552
2553 return IRQ_HANDLED;
2554}
2555
2556static void
2557ath5k_tasklet_reset(unsigned long data)
2558{
2559 struct ath5k_softc *sc = (void *)data;
2560
d7dc1003 2561 ath5k_reset_wake(sc);
fa1c114f
JS		 2562}
2563
2564/*
2565 * Periodically recalibrate the PHY to account
2566 * for temperature/environment changes.
2567 */
2568static void
2569ath5k_calibrate(unsigned long data)
2570{
2571 struct ath5k_softc *sc = (void *)data;
2572 struct ath5k_hw *ah = sc->ah;
2573
2574 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2575 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2576 sc->curchan->hw_value);
fa1c114f 2577
6f3b414a 2578 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2579 /*
2580 * Rfgain is out of bounds, reset the chip
2581 * to load new gain values.
2582 */
2583 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2584 ath5k_reset_wake(sc);
fa1c114f
JS		 2585 }
2586 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2587 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2588 ieee80211_frequency_to_channel(
2589 sc->curchan->center_freq));
fa1c114f
JS		 2590
2591 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2592 msecs_to_jiffies(ath5k_calinterval * 1000)));
2593}
2594
2595
fa1c114f
JS		 2596/********************\
2597* Mac80211 functions *
2598\********************/
2599
2600static int
e039fa4a 2601ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2602{
2603 struct ath5k_softc *sc = hw->priv;
2604
2605 return ath5k_tx_queue(hw, skb, sc->txq);
2606}
2607
2608static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2609 struct ath5k_txq *txq)
fa1c114f
JS		 2610{
2611 struct ath5k_softc *sc = hw->priv;
2612 struct ath5k_buf *bf;
2613 unsigned long flags;
2614 int hdrlen;
0fe45b1d 2615 int padsize;
fa1c114f
JS		 2616
2617 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2618
05c914fe 2619 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2620 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2621
2622 /*
2623 * the hardware expects the header padded to 4 byte boundaries
2624 * if this is not the case we add the padding after the header
2625 */
2626 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2627 padsize = ath5k_pad_size(hdrlen);
2628 if (padsize) {
0fe45b1d
BP		 2629
2630 if (skb_headroom(skb) < padsize) {
fa1c114f 2631 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2632 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2633 goto drop_packet;
fa1c114f 2634 }
0fe45b1d
BP		 2635 skb_push(skb, padsize);
2636 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2637 }
2638
fa1c114f
JS		 2639 spin_lock_irqsave(&sc->txbuflock, flags);
2640 if (list_empty(&sc->txbuf)) {
2641 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2642 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2643 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2644 goto drop_packet;
fa1c114f
JS		 2645 }
2646 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2647 list_del(&bf->list);
2648 sc->txbuf_len--;
2649 if (list_empty(&sc->txbuf))
2650 ieee80211_stop_queues(hw);
2651 spin_unlock_irqrestore(&sc->txbuflock, flags);
2652
2653 bf->skb = skb;
2654
cec8db23 2655 if (ath5k_txbuf_setup(sc, bf, txq)) {
fa1c114f
JS		 2656 bf->skb = NULL;
2657 spin_lock_irqsave(&sc->txbuflock, flags);
2658 list_add_tail(&bf->list, &sc->txbuf);
2659 sc->txbuf_len++;
2660 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2661 goto drop_packet;
fa1c114f 2662 }
5a0fe8ac 2663 return NETDEV_TX_OK;
fa1c114f 2664
5a0fe8ac
BC		 2665drop_packet:
2666 dev_kfree_skb_any(skb);
71ef99c8 2667 return NETDEV_TX_OK;
fa1c114f
JS		 2668}
2669
209d889b
BC		 2670/*
2671 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2672 * and change to the given channel.
2673 */
fa1c114f 2674static int
209d889b 2675ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2676{
fa1c114f
JS		 2677 struct ath5k_hw *ah = sc->ah;
2678 int ret;
2679
2680 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2681
209d889b 2682 if (chan) {
c6e387a2 2683 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2684 ath5k_txq_cleanup(sc);
2685 ath5k_rx_stop(sc);
209d889b
BC		 2686
2687 sc->curchan = chan;
2688 sc->curband = &sc->sbands[chan->band];
d7dc1003 2689 }
3355443a 2690 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2691 if (ret) {
fa1c114f
JS		 2692 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2693 goto err;
2694 }
d7dc1003 2695
fa1c114f 2696 ret = ath5k_rx_start(sc);
d7dc1003 2697 if (ret) {
fa1c114f
JS		 2698 ATH5K_ERR(sc, "can't start recv logic\n");
2699 goto err;
2700 }
d7dc1003 2701
fa1c114f 2702 /*
d7dc1003
JS		 2703 * Change channels and update the h/w rate map if we're switching;
2704 * e.g. 11a to 11b/g.
2705 *
2706 * We may be doing a reset in response to an ioctl that changes the
2707 * channel so update any state that might change as a result.
fa1c114f
JS		 2708 *
2709 * XXX needed?
2710 */
2711/* ath5k_chan_change(sc, c); */
fa1c114f 2712
d7dc1003
JS		 2713 ath5k_beacon_config(sc);
2714 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2715
2716 return 0;
2717err:
2718 return ret;
2719}
2720
d7dc1003
JS		 2721static int
2722ath5k_reset_wake(struct ath5k_softc *sc)
2723{
2724 int ret;
2725
209d889b 2726 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2727 if (!ret)
2728 ieee80211_wake_queues(sc->hw);
2729
2730 return ret;
2731}
2732
fa1c114f
JS		 2733static int ath5k_start(struct ieee80211_hw *hw)
2734{
bb2becac 2735 return ath5k_init(hw->priv);
fa1c114f
JS		 2736}
2737
2738static void ath5k_stop(struct ieee80211_hw *hw)
2739{
bb2becac 2740 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2741}
2742
2743static int ath5k_add_interface(struct ieee80211_hw *hw,
2744 struct ieee80211_if_init_conf *conf)
2745{
2746 struct ath5k_softc *sc = hw->priv;
2747 int ret;
2748
2749 mutex_lock(&sc->lock);
32bfd35d 2750 if (sc->vif) {
fa1c114f
JS		 2751 ret = 0;
2752 goto end;
2753 }
2754
32bfd35d 2755 sc->vif = conf->vif;
fa1c114f
JS		 2756
2757 switch (conf->type) {
da966bca 2758 case NL80211_IFTYPE_AP:
05c914fe
JB		 2759 case NL80211_IFTYPE_STATION:
2760 case NL80211_IFTYPE_ADHOC:
b706e65b 2761 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2762 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2763 sc->opmode = conf->type;
2764 break;
2765 default:
2766 ret = -EOPNOTSUPP;
2767 goto end;
2768 }
67d2e2df 2769
0e149cf5 2770 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2771
fa1c114f
JS		 2772 ret = 0;
2773end:
2774 mutex_unlock(&sc->lock);
2775 return ret;
2776}
2777
2778static void
2779ath5k_remove_interface(struct ieee80211_hw *hw,
2780 struct ieee80211_if_init_conf *conf)
2781{
2782 struct ath5k_softc *sc = hw->priv;
0e149cf5 2783 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2784
2785 mutex_lock(&sc->lock);
32bfd35d 2786 if (sc->vif != conf->vif)
fa1c114f
JS		 2787 goto end;
2788
0e149cf5 2789 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2790 sc->vif = NULL;
fa1c114f
JS		 2791end:
2792 mutex_unlock(&sc->lock);
2793}
2794
d8ee398d
LR		 2795/*
2796 * TODO: Phy disable/diversity etc
2797 */
fa1c114f 2798static int
e8975581 2799ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2800{
2801 struct ath5k_softc *sc = hw->priv;
a0823810 2802 struct ath5k_hw *ah = sc->ah;
e8975581 2803 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 2804 int ret = 0;
be009370
BC		 2805
2806 mutex_lock(&sc->lock);
fa1c114f 2807
2bed03eb
NK		 2808 ret = ath5k_chan_set(sc, conf->channel);
2809 if (ret < 0)
55aa4e0f 2810 goto unlock;
2bed03eb 2811
a0823810
NK		 2812 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2813 (sc->power_level != conf->power_level)) {
2814 sc->power_level = conf->power_level;
2815
2816 /* Half dB steps */
2817 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2818 }
fa1c114f 2819
2bed03eb
NK		 2820 /* TODO:
2821 * 1) Move this on config_interface and handle each case
2822 * separately eg. when we have only one STA vif, use
2823 * AR5K_ANTMODE_SINGLE_AP
2824 *
2825 * 2) Allow the user to change antenna mode eg. when only
2826 * one antenna is present
2827 *
2828 * 3) Allow the user to set default/tx antenna when possible
2829 *
2830 * 4) Default mode should handle 90% of the cases, together
2831 * with fixed a/b and single AP modes we should be able to
2832 * handle 99%. Sectored modes are extreme cases and i still
2833 * haven't found a usage for them. If we decide to support them,
2834 * then we must allow the user to set how many tx antennas we
2835 * have available
2836 */
2837 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
be009370 2838
55aa4e0f 2839unlock:
be009370 2840 mutex_unlock(&sc->lock);
55aa4e0f 2841 return ret;
fa1c114f
JS		 2842}
2843
fa1c114f
JS		 2844#define SUPPORTED_FIF_FLAGS \
2845 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2846 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2847 FIF_BCN_PRBRESP_PROMISC
2848/*
2849 * o always accept unicast, broadcast, and multicast traffic
2850 * o multicast traffic for all BSSIDs will be enabled if mac80211
2851 * says it should be
2852 * o maintain current state of phy ofdm or phy cck error reception.
2853 * If the hardware detects any of these type of errors then
2854 * ath5k_hw_get_rx_filter() will pass to us the respective
2855 * hardware filters to be able to receive these type of frames.
2856 * o probe request frames are accepted only when operating in
2857 * hostap, adhoc, or monitor modes
2858 * o enable promiscuous mode according to the interface state
2859 * o accept beacons:
2860 * - when operating in adhoc mode so the 802.11 layer creates
2861 * node table entries for peers,
2862 * - when operating in station mode for collecting rssi data when
2863 * the station is otherwise quiet, or
2864 * - when scanning
2865 */
2866static void ath5k_configure_filter(struct ieee80211_hw *hw,
2867 unsigned int changed_flags,
2868 unsigned int *new_flags,
2869 int mc_count, struct dev_mc_list *mclist)
2870{
2871 struct ath5k_softc *sc = hw->priv;
2872 struct ath5k_hw *ah = sc->ah;
2873 u32 mfilt[2], val, rfilt;
2874 u8 pos;
2875 int i;
2876
2877 mfilt[0] = 0;
2878 mfilt[1] = 0;
2879
2880 /* Only deal with supported flags */
2881 changed_flags &= SUPPORTED_FIF_FLAGS;
2882 *new_flags &= SUPPORTED_FIF_FLAGS;
2883
2884 /* If HW detects any phy or radar errors, leave those filters on.
2885 * Also, always enable Unicast, Broadcasts and Multicast
2886 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2887 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2888 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2889 AR5K_RX_FILTER_MCAST);
2890
2891 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2892 if (*new_flags & FIF_PROMISC_IN_BSS) {
2893 rfilt |= AR5K_RX_FILTER_PROM;
2894 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2895 } else {
fa1c114f 2896 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2897 }
fa1c114f
JS		 2898 }
2899
2900 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2901 if (*new_flags & FIF_ALLMULTI) {
2902 mfilt[0] = ~0;
2903 mfilt[1] = ~0;
2904 } else {
2905 for (i = 0; i < mc_count; i++) {
2906 if (!mclist)
2907 break;
2908 /* calculate XOR of eight 6-bit values */
533dd1b0 2909 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2910 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2911 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2912 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2913 pos &= 0x3f;
2914 mfilt[pos / 32] |= (1 << (pos % 32));
2915 /* XXX: we might be able to just do this instead,
2916 * but not sure, needs testing, if we do use this we'd
2917 * neet to inform below to not reset the mcast */
2918 /* ath5k_hw_set_mcast_filterindex(ah,
2919 * mclist->dmi_addr[5]); */
2920 mclist = mclist->next;
2921 }
2922 }
2923
2924 /* This is the best we can do */
2925 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2926 rfilt |= AR5K_RX_FILTER_PHYERR;
2927
2928 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2929 * and probes for any BSSID, this needs testing */
2930 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2931 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2932
2933 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2934 * set we should only pass on control frames for this
2935 * station. This needs testing. I believe right now this
2936 * enables *all* control frames, which is OK.. but
2937 * but we should see if we can improve on granularity */
2938 if (*new_flags & FIF_CONTROL)
2939 rfilt |= AR5K_RX_FILTER_CONTROL;
2940
2941 /* Additional settings per mode -- this is per ath5k */
2942
2943 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2944
05c914fe 2945 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2946 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2947 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2948 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2949 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2950 if (sc->opmode != NL80211_IFTYPE_AP &&
2951 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2952 test_bit(ATH_STAT_PROMISC, sc->status))
2953 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2954 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2955 sc->opmode == NL80211_IFTYPE_ADHOC ||
2956 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2957 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2958 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2959 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2960 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2961
2962 /* Set filters */
0bbac08f 2963 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2964
2965 /* Set multicast bits */
2966 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2967 /* Set the cached hw filter flags, this will alter actually
2968 * be set in HW */
2969 sc->filter_flags = rfilt;
2970}
2971
2972static int
2973ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2974 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2975 struct ieee80211_key_conf *key)
fa1c114f
JS		 2976{
2977 struct ath5k_softc *sc = hw->priv;
2978 int ret = 0;
2979
9ad9a26e
BC		 2980 if (modparam_nohwcrypt)
2981 return -EOPNOTSUPP;
2982
0bbac08f 2983 switch (key->alg) {
fa1c114f 2984 case ALG_WEP:
fa1c114f 2985 case ALG_TKIP:
3f64b435 2986 break;
fa1c114f
JS		 2987 case ALG_CCMP:
2988 return -EOPNOTSUPP;
2989 default:
2990 WARN_ON(1);
2991 return -EINVAL;
2992 }
2993
2994 mutex_lock(&sc->lock);
2995
2996 switch (cmd) {
2997 case SET_KEY:
dc822b5d
JB		 2998 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2999 sta ? sta->addr : NULL);
fa1c114f
JS		 3000 if (ret) {
3001 ATH5K_ERR(sc, "can't set the key\n");
3002 goto unlock;
3003 }
3004 __set_bit(key->keyidx, sc->keymap);
3005 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3006 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3007 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3008 break;
3009 case DISABLE_KEY:
3010 ath5k_hw_reset_key(sc->ah, key->keyidx);
3011 __clear_bit(key->keyidx, sc->keymap);
3012 break;
3013 default:
3014 ret = -EINVAL;
3015 goto unlock;
3016 }
3017
3018unlock:
274c7c36 3019 mmiowb();
fa1c114f
JS		 3020 mutex_unlock(&sc->lock);
3021 return ret;
3022}
3023
3024static int
3025ath5k_get_stats(struct ieee80211_hw *hw,
3026 struct ieee80211_low_level_stats *stats)
3027{
3028 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3029 struct ath5k_hw *ah = sc->ah;
3030
3031 /* Force update */
3032 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3033
3034 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3035
3036 return 0;
3037}
3038
3039static int
3040ath5k_get_tx_stats(struct ieee80211_hw *hw,
3041 struct ieee80211_tx_queue_stats *stats)
3042{
3043 struct ath5k_softc *sc = hw->priv;
3044
3045 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3046
3047 return 0;
3048}
3049
3050static u64
3051ath5k_get_tsf(struct ieee80211_hw *hw)
3052{
3053 struct ath5k_softc *sc = hw->priv;
3054
3055 return ath5k_hw_get_tsf64(sc->ah);
3056}
3057
3b5d665b
AF		 3058static void
3059ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3060{
3061 struct ath5k_softc *sc = hw->priv;
3062
3063 ath5k_hw_set_tsf64(sc->ah, tsf);
3064}
3065
fa1c114f
JS		 3066static void
3067ath5k_reset_tsf(struct ieee80211_hw *hw)
3068{
3069 struct ath5k_softc *sc = hw->priv;
3070
9804b98d
BR		 3071 /*
3072 * in IBSS mode we need to update the beacon timers too.
3073 * this will also reset the TSF if we call it with 0
3074 */
05c914fe 3075 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3076 ath5k_beacon_update_timers(sc, 0);
3077 else
3078 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3079}
3080
1071db86
BC		 3081/*
3082 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3083 * this is called only once at config_bss time, for AP we do it every
3084 * SWBA interrupt so that the TIM will reflect buffered frames.
3085 *
3086 * Called with the beacon lock.
3087 */
fa1c114f 3088static int
1071db86 3089ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3090{
fa1c114f 3091 int ret;
1071db86 3092 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3093 struct sk_buff *skb;
3094
3095 if (WARN_ON(!vif)) {
3096 ret = -EINVAL;
3097 goto out;
3098 }
3099
3100 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3101
3102 if (!skb) {
3103 ret = -ENOMEM;
3104 goto out;
3105 }
fa1c114f
JS		 3106
3107 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3108
fa1c114f
JS		 3109 ath5k_txbuf_free(sc, sc->bbuf);
3110 sc->bbuf->skb = skb;
e039fa4a 3111 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3112 if (ret)
3113 sc->bbuf->skb = NULL;
1071db86
BC		 3114out:
3115 return ret;
3116}
3117
02969b38
MX		 3118static void
3119set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3120{
3121 struct ath5k_softc *sc = hw->priv;
3122 struct ath5k_hw *ah = sc->ah;
3123 u32 rfilt;
3124 rfilt = ath5k_hw_get_rx_filter(ah);
3125 if (enable)
3126 rfilt |= AR5K_RX_FILTER_BEACON;
3127 else
3128 rfilt &= ~AR5K_RX_FILTER_BEACON;
3129 ath5k_hw_set_rx_filter(ah, rfilt);
3130 sc->filter_flags = rfilt;
3131}
fa1c114f 3132
02969b38
MX		 3133static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3134 struct ieee80211_vif *vif,
3135 struct ieee80211_bss_conf *bss_conf,
3136 u32 changes)
3137{
3138 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3139 struct ath5k_hw *ah = sc->ah;
21800491 3140 unsigned long flags;
2d0ddec5
JB		 3141
3142 mutex_lock(&sc->lock);
3143 if (WARN_ON(sc->vif != vif))
3144 goto unlock;
3145
3146 if (changes & BSS_CHANGED_BSSID) {
3147 /* Cache for later use during resets */
3148 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3149 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3150 * a clean way of letting us retrieve this yet. */
3151 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3152 mmiowb();
3153 }
57c4d7b4
JB		 3154
3155 if (changes & BSS_CHANGED_BEACON_INT)
3156 sc->bintval = bss_conf->beacon_int;
3157
02969b38 3158 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3159 sc->assoc = bss_conf->assoc;
3160 if (sc->opmode == NL80211_IFTYPE_STATION)
3161 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3162 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3163 AR5K_LED_ASSOC : AR5K_LED_INIT);
02969b38 3164 }
2d0ddec5 3165
21800491
BC		 3166 if (changes & BSS_CHANGED_BEACON) {
3167 spin_lock_irqsave(&sc->block, flags);
3168 ath5k_beacon_update(hw, vif);
3169 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3170 }
3171
21800491
BC		 3172 if (changes & BSS_CHANGED_BEACON_ENABLED)
3173 sc->enable_beacon = bss_conf->enable_beacon;
3174
3175 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3176 BSS_CHANGED_BEACON_INT))
3177 ath5k_beacon_config(sc);
3178
2d0ddec5
JB		 3179 unlock:
3180 mutex_unlock(&sc->lock);
02969b38 3181}
f0f3d388
BC		 3182
3183static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3184{
3185 struct ath5k_softc *sc = hw->priv;
3186 if (!sc->assoc)
3187 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3188}
3189
3190static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3191{
3192 struct ath5k_softc *sc = hw->priv;
3193 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3194 AR5K_LED_ASSOC : AR5K_LED_INIT);
3195}
Clone of davem's net-next-2.6 tree