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ath5k: fix rx descriptor debugging
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
5a0e3ad6 53#include <linux/slab.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
9ad9a26e 64static int modparam_nohwcrypt;
46802a4f 65module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 66MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 67
42639fcd 68static int modparam_all_channels;
46802a4f 69module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 70MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
fa1c114f
JS		 72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 83MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 84
85
86/* Known PCI ids */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 106 { 0 }
107};
108MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
109
110/* Known SREVs */
2c91108c 111static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148};
149
2c91108c 150static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 /* XR missing */
190};
191
fa1c114f
JS		 192/*
193 * Prototypes - PCI stack related functions
194 */
195static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
196 const struct pci_device_id *id);
197static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
e307139d 198#ifdef CONFIG_PM_SLEEP
baee1f3c
RW		 199static int ath5k_pci_suspend(struct device *dev);
200static int ath5k_pci_resume(struct device *dev);
201
626ede6b 202static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
baee1f3c 203#define ATH5K_PM_OPS (&ath5k_pm_ops)
fa1c114f 204#else
baee1f3c 205#define ATH5K_PM_OPS NULL
e307139d 206#endif /* CONFIG_PM_SLEEP */
fa1c114f 207
04a9e451 208static struct pci_driver ath5k_pci_driver = {
9764f3f9 209 .name = KBUILD_MODNAME,
fa1c114f
JS		 210 .id_table = ath5k_pci_id_table,
211 .probe = ath5k_pci_probe,
212 .remove = __devexit_p(ath5k_pci_remove),
baee1f3c 213 .driver.pm = ATH5K_PM_OPS,
fa1c114f
JS		 214};
215
216
217
218/*
219 * Prototypes - MAC 802.11 stack related functions
220 */
e039fa4a 221static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 222static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
223 struct ath5k_txq *txq);
209d889b 224static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
fa1c114f
JS		 225static int ath5k_start(struct ieee80211_hw *hw);
226static void ath5k_stop(struct ieee80211_hw *hw);
227static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 228 struct ieee80211_vif *vif);
fa1c114f 229static void ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 230 struct ieee80211_vif *vif);
e8975581 231static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee 232static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 233 struct netdev_hw_addr_list *mc_list);
fa1c114f
JS		 234static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
3ac64bee 237 u64 multicast);
fa1c114f
JS		 238static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
dc822b5d 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 241 struct ieee80211_key_conf *key);
242static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
55ee82b5
HS		 244static int ath5k_get_survey(struct ieee80211_hw *hw,
245 int idx, struct survey_info *survey);
fa1c114f 246static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 247static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 248static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 249static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
02969b38
MX		 251static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
254 u32 changes);
f0f3d388
BC		 255static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
6e08d228
LT		 257static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
258 u8 coverage_class);
fa1c114f 259
2c91108c 260static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 261 .tx = ath5k_tx,
262 .start = ath5k_start,
263 .stop = ath5k_stop,
264 .add_interface = ath5k_add_interface,
265 .remove_interface = ath5k_remove_interface,
266 .config = ath5k_config,
3ac64bee 267 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 268 .configure_filter = ath5k_configure_filter,
269 .set_key = ath5k_set_key,
270 .get_stats = ath5k_get_stats,
55ee82b5 271 .get_survey = ath5k_get_survey,
fa1c114f 272 .conf_tx = NULL,
fa1c114f 273 .get_tsf = ath5k_get_tsf,
3b5d665b 274 .set_tsf = ath5k_set_tsf,
fa1c114f 275 .reset_tsf = ath5k_reset_tsf,
02969b38 276 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 277 .sw_scan_start = ath5k_sw_scan_start,
278 .sw_scan_complete = ath5k_sw_scan_complete,
6e08d228 279 .set_coverage_class = ath5k_set_coverage_class,
fa1c114f
JS		 280};
281
282/*
283 * Prototypes - Internal functions
284 */
285/* Attach detach */
286static int ath5k_attach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288static void ath5k_detach(struct pci_dev *pdev,
289 struct ieee80211_hw *hw);
290/* Channel/mode setup */
291static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 292static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
293 struct ieee80211_channel *channels,
294 unsigned int mode,
295 unsigned int max);
63266a65 296static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 297static int ath5k_chan_set(struct ath5k_softc *sc,
298 struct ieee80211_channel *chan);
299static void ath5k_setcurmode(struct ath5k_softc *sc,
300 unsigned int mode);
301static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 302
fa1c114f
JS		 303/* Descriptor setup */
304static int ath5k_desc_alloc(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
306static void ath5k_desc_free(struct ath5k_softc *sc,
307 struct pci_dev *pdev);
308/* Buffers setup */
309static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
310 struct ath5k_buf *bf);
311static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23 312 struct ath5k_buf *bf,
8127fbdc 313 struct ath5k_txq *txq, int padsize);
9e4e43f2
BR		 314
315static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 316 struct ath5k_buf *bf)
317{
318 BUG_ON(!bf);
319 if (!bf->skb)
320 return;
321 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
322 PCI_DMA_TODEVICE);
00482973 323 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 324 bf->skb = NULL;
325}
326
9e4e43f2 327static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 328 struct ath5k_buf *bf)
329{
cc861f74
LR		 330 struct ath5k_hw *ah = sc->ah;
331 struct ath_common *common = ath5k_hw_common(ah);
332
a6c8d375
FF		 333 BUG_ON(!bf);
334 if (!bf->skb)
335 return;
cc861f74 336 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 337 PCI_DMA_FROMDEVICE);
338 dev_kfree_skb_any(bf->skb);
339 bf->skb = NULL;
340}
341
342
fa1c114f
JS		 343/* Queues setup */
344static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
345 int qtype, int subtype);
346static int ath5k_beaconq_setup(struct ath5k_hw *ah);
347static int ath5k_beaconq_config(struct ath5k_softc *sc);
348static void ath5k_txq_drainq(struct ath5k_softc *sc,
349 struct ath5k_txq *txq);
350static void ath5k_txq_cleanup(struct ath5k_softc *sc);
351static void ath5k_txq_release(struct ath5k_softc *sc);
352/* Rx handling */
353static int ath5k_rx_start(struct ath5k_softc *sc);
354static void ath5k_rx_stop(struct ath5k_softc *sc);
355static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
356 struct ath5k_desc *ds,
b47f407b
BR		 357 struct sk_buff *skb,
358 struct ath5k_rx_status *rs);
fa1c114f
JS		 359static void ath5k_tasklet_rx(unsigned long data);
360/* Tx handling */
361static void ath5k_tx_processq(struct ath5k_softc *sc,
362 struct ath5k_txq *txq);
363static void ath5k_tasklet_tx(unsigned long data);
364/* Beacon handling */
365static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 366 struct ath5k_buf *bf);
fa1c114f
JS		 367static void ath5k_beacon_send(struct ath5k_softc *sc);
368static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 369static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 370static void ath5k_tasklet_beacon(unsigned long data);
2111ac0d 371static void ath5k_tasklet_ani(unsigned long data);
fa1c114f
JS		 372
373static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
374{
375 u64 tsf = ath5k_hw_get_tsf64(ah);
376
377 if ((tsf & 0x7fff) < rstamp)
378 tsf -= 0x8000;
379
380 return (tsf & ~0x7fff) | rstamp;
381}
382
383/* Interrupt handling */
bb2becac 384static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 385static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 386static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 387static irqreturn_t ath5k_intr(int irq, void *dev_id);
388static void ath5k_tasklet_reset(unsigned long data);
389
6e220662 390static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 391
392/*
393 * Module init/exit functions
394 */
395static int __init
396init_ath5k_pci(void)
397{
398 int ret;
399
400 ath5k_debug_init();
401
04a9e451 402 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 403 if (ret) {
404 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
405 return ret;
406 }
407
408 return 0;
409}
410
411static void __exit
412exit_ath5k_pci(void)
413{
04a9e451 414 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 415
416 ath5k_debug_finish();
417}
418
419module_init(init_ath5k_pci);
420module_exit(exit_ath5k_pci);
421
422
423/********************\
424* PCI Initialization *
425\********************/
426
427static const char *
428ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
429{
430 const char *name = "xxxxx";
431 unsigned int i;
432
433 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
434 if (srev_names[i].sr_type != type)
435 continue;
75d0edb8
NK		 436
437 if ((val & 0xf0) == srev_names[i].sr_val)
438 name = srev_names[i].sr_name;
439
440 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 441 name = srev_names[i].sr_name;
442 break;
443 }
444 }
445
446 return name;
447}
e5aa8474
LR		 448static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
449{
450 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
451 return ath5k_hw_reg_read(ah, reg_offset);
452}
453
454static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
455{
456 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
457 ath5k_hw_reg_write(ah, val, reg_offset);
458}
459
460static const struct ath_ops ath5k_common_ops = {
461 .read = ath5k_ioread32,
462 .write = ath5k_iowrite32,
463};
fa1c114f
JS		 464
465static int __devinit
466ath5k_pci_probe(struct pci_dev *pdev,
467 const struct pci_device_id *id)
468{
469 void __iomem *mem;
470 struct ath5k_softc *sc;
db719718 471 struct ath_common *common;
fa1c114f
JS		 472 struct ieee80211_hw *hw;
473 int ret;
474 u8 csz;
475
476 ret = pci_enable_device(pdev);
477 if (ret) {
478 dev_err(&pdev->dev, "can't enable device\n");
479 goto err;
480 }
481
482 /* XXX 32-bit addressing only */
284901a9 483 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 484 if (ret) {
485 dev_err(&pdev->dev, "32-bit DMA not available\n");
486 goto err_dis;
487 }
488
489 /*
490 * Cache line size is used to size and align various
491 * structures used to communicate with the hardware.
492 */
493 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
494 if (csz == 0) {
495 /*
496 * Linux 2.4.18 (at least) writes the cache line size
497 * register as a 16-bit wide register which is wrong.
498 * We must have this setup properly for rx buffer
499 * DMA to work so force a reasonable value here if it
500 * comes up zero.
501 */
13311b00 502 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 503 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
504 }
505 /*
506 * The default setting of latency timer yields poor results,
507 * set it to the value used by other systems. It may be worth
508 * tweaking this setting more.
509 */
510 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
511
512 /* Enable bus mastering */
513 pci_set_master(pdev);
514
515 /*
516 * Disable the RETRY_TIMEOUT register (0x41) to keep
517 * PCI Tx retries from interfering with C3 CPU state.
518 */
519 pci_write_config_byte(pdev, 0x41, 0);
520
521 ret = pci_request_region(pdev, 0, "ath5k");
522 if (ret) {
523 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
524 goto err_dis;
525 }
526
527 mem = pci_iomap(pdev, 0, 0);
528 if (!mem) {
529 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
530 ret = -EIO;
531 goto err_reg;
532 }
533
534 /*
535 * Allocate hw (mac80211 main struct)
536 * and hw->priv (driver private data)
537 */
538 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
539 if (hw == NULL) {
540 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
541 ret = -ENOMEM;
542 goto err_map;
543 }
544
545 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
546
547 /* Initialize driver private data */
548 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 549 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 550 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
f5c044e5 551 IEEE80211_HW_SIGNAL_DBM;
f59ac048
LR		 552
553 hw->wiphy->interface_modes =
6f5f39c9 554 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 555 BIT(NL80211_IFTYPE_STATION) |
556 BIT(NL80211_IFTYPE_ADHOC) |
557 BIT(NL80211_IFTYPE_MESH_POINT);
558
fa1c114f
JS		 559 hw->extra_tx_headroom = 2;
560 hw->channel_change_time = 5000;
fa1c114f
JS		 561 sc = hw->priv;
562 sc->hw = hw;
563 sc->pdev = pdev;
564
565 ath5k_debug_init_device(sc);
566
567 /*
568 * Mark the device as detached to avoid processing
569 * interrupts until setup is complete.
570 */
571 __set_bit(ATH_STAT_INVALID, sc->status);
572
573 sc->iobase = mem; /* So we can unmap it on detach */
05c914fe 574 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 575 sc->bintval = 1000;
fa1c114f
JS		 576 mutex_init(&sc->lock);
577 spin_lock_init(&sc->rxbuflock);
578 spin_lock_init(&sc->txbuflock);
00482973 579 spin_lock_init(&sc->block);
fa1c114f
JS		 580
581 /* Set private data */
6673e2e8 582 pci_set_drvdata(pdev, sc);
fa1c114f 583
fa1c114f
JS		 584 /* Setup interrupt handler */
585 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
586 if (ret) {
587 ATH5K_ERR(sc, "request_irq failed\n");
588 goto err_free;
589 }
590
9adca126
LR		 591 /*If we passed the test malloc a ath5k_hw struct*/
592 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
593 if (!sc->ah) {
594 ret = -ENOMEM;
595 ATH5K_ERR(sc, "out of memory\n");
fa1c114f
JS		 596 goto err_irq;
597 }
598
9adca126
LR		 599 sc->ah->ah_sc = sc;
600 sc->ah->ah_iobase = sc->iobase;
db719718 601 common = ath5k_hw_common(sc->ah);
e5aa8474 602 common->ops = &ath5k_common_ops;
13b81559 603 common->ah = sc->ah;
b002a4a9 604 common->hw = hw;
db719718
LR		 605 common->cachelsz = csz << 2; /* convert to bytes */
606
9adca126
LR		 607 /* Initialize device */
608 ret = ath5k_hw_attach(sc);
609 if (ret) {
610 goto err_free_ah;
611 }
612
2f7fe870
FF		 613 /* set up multi-rate retry capabilities */
614 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 615 hw->max_rates = 4;
616 hw->max_rate_tries = 11;
2f7fe870
FF		 617 }
618
fa1c114f
JS		 619 /* Finish private driver data initialization */
620 ret = ath5k_attach(pdev, hw);
621 if (ret)
622 goto err_ah;
623
624 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 625 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 626 sc->ah->ah_mac_srev,
627 sc->ah->ah_phy_revision);
628
400ec45a 629 if (!sc->ah->ah_single_chip) {
fa1c114f 630 /* Single chip radio (!RF5111) */
400ec45a
LR		 631 if (sc->ah->ah_radio_5ghz_revision &&
632 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 633 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 634 if (!test_bit(AR5K_MODE_11A,
635 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 636 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 637 ath5k_chip_name(AR5K_VERSION_RAD,
638 sc->ah->ah_radio_5ghz_revision),
639 sc->ah->ah_radio_5ghz_revision);
640 /* No 2GHz support (5110 and some
641 * 5Ghz only cards) -> report 5Ghz radio */
642 } else if (!test_bit(AR5K_MODE_11B,
643 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 644 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 645 ath5k_chip_name(AR5K_VERSION_RAD,
646 sc->ah->ah_radio_5ghz_revision),
647 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 648 /* Multiband radio */
649 } else {
650 ATH5K_INFO(sc, "RF%s multiband radio found"
651 " (0x%x)\n",
400ec45a
LR		 652 ath5k_chip_name(AR5K_VERSION_RAD,
653 sc->ah->ah_radio_5ghz_revision),
654 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 655 }
656 }
400ec45a
LR		 657 /* Multi chip radio (RF5111 - RF2111) ->
658 * report both 2GHz/5GHz radios */
659 else if (sc->ah->ah_radio_5ghz_revision &&
660 sc->ah->ah_radio_2ghz_revision){
fa1c114f 661 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 662 ath5k_chip_name(AR5K_VERSION_RAD,
663 sc->ah->ah_radio_5ghz_revision),
664 sc->ah->ah_radio_5ghz_revision);
fa1c114f 665 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 666 ath5k_chip_name(AR5K_VERSION_RAD,
667 sc->ah->ah_radio_2ghz_revision),
668 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 669 }
670 }
671
672
673 /* ready to process interrupts */
674 __clear_bit(ATH_STAT_INVALID, sc->status);
675
676 return 0;
677err_ah:
678 ath5k_hw_detach(sc->ah);
679err_irq:
680 free_irq(pdev->irq, sc);
9adca126
LR		 681err_free_ah:
682 kfree(sc->ah);
fa1c114f 683err_free:
fa1c114f
JS		 684 ieee80211_free_hw(hw);
685err_map:
686 pci_iounmap(pdev, mem);
687err_reg:
688 pci_release_region(pdev, 0);
689err_dis:
690 pci_disable_device(pdev);
691err:
692 return ret;
693}
694
695static void __devexit
696ath5k_pci_remove(struct pci_dev *pdev)
697{
6673e2e8 698 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f
JS		 699
700 ath5k_debug_finish_device(sc);
6673e2e8 701 ath5k_detach(pdev, sc->hw);
fa1c114f 702 ath5k_hw_detach(sc->ah);
9adca126 703 kfree(sc->ah);
fa1c114f 704 free_irq(pdev->irq, sc);
fa1c114f
JS		 705 pci_iounmap(pdev, sc->iobase);
706 pci_release_region(pdev, 0);
707 pci_disable_device(pdev);
6673e2e8 708 ieee80211_free_hw(sc->hw);
fa1c114f
JS		 709}
710
e307139d 711#ifdef CONFIG_PM_SLEEP
baee1f3c 712static int ath5k_pci_suspend(struct device *dev)
fa1c114f 713{
6673e2e8 714 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
fa1c114f 715
3a078876 716 ath5k_led_off(sc);
fa1c114f
JS		 717 return 0;
718}
719
baee1f3c 720static int ath5k_pci_resume(struct device *dev)
fa1c114f 721{
baee1f3c 722 struct pci_dev *pdev = to_pci_dev(dev);
6673e2e8 723 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 724
8451d22d
JM		 725 /*
726 * Suspend/Resume resets the PCI configuration space, so we have to
727 * re-disable the RETRY_TIMEOUT register (0x41) to keep
728 * PCI Tx retries from interfering with C3 CPU state
729 */
730 pci_write_config_byte(pdev, 0x41, 0);
731
3a078876 732 ath5k_led_enable(sc);
fa1c114f
JS		 733 return 0;
734}
e307139d 735#endif /* CONFIG_PM_SLEEP */
fa1c114f
JS		 736
737
fa1c114f
JS		 738/***********************\
739* Driver Initialization *
740\***********************/
741
f769c36b
BC		 742static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
743{
744 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
745 struct ath5k_softc *sc = hw->priv;
db719718 746 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
f769c36b 747
608b88cb 748 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 749}
750
fa1c114f
JS		 751static int
752ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
753{
754 struct ath5k_softc *sc = hw->priv;
755 struct ath5k_hw *ah = sc->ah;
db719718 756 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
0e149cf5 757 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 758 int ret;
759
760 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
761
762 /*
763 * Check if the MAC has multi-rate retry support.
764 * We do this by trying to setup a fake extended
765 * descriptor. MAC's that don't have support will
766 * return false w/o doing anything. MAC's that do
767 * support it will return true w/o doing anything.
768 */
c6e387a2 769 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 770 if (ret < 0)
771 goto err;
772 if (ret > 0)
fa1c114f
JS		 773 __set_bit(ATH_STAT_MRRETRY, sc->status);
774
fa1c114f
JS		 775 /*
776 * Collect the channel list. The 802.11 layer
777 * is resposible for filtering this list based
778 * on settings like the phy mode and regulatory
779 * domain restrictions.
780 */
63266a65 781 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 782 if (ret) {
783 ATH5K_ERR(sc, "can't get channels\n");
784 goto err;
785 }
786
787 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 788 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
789 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 790 else
d8ee398d 791 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 792
793 /*
794 * Allocate tx+rx descriptors and populate the lists.
795 */
796 ret = ath5k_desc_alloc(sc, pdev);
797 if (ret) {
798 ATH5K_ERR(sc, "can't allocate descriptors\n");
799 goto err;
800 }
801
802 /*
803 * Allocate hardware transmit queues: one queue for
804 * beacon frames and one data queue for each QoS
805 * priority. Note that hw functions handle reseting
806 * these queues at the needed time.
807 */
808 ret = ath5k_beaconq_setup(ah);
809 if (ret < 0) {
810 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
811 goto err_desc;
812 }
813 sc->bhalq = ret;
cec8db23
BC		 814 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
815 if (IS_ERR(sc->cabq)) {
816 ATH5K_ERR(sc, "can't setup cab queue\n");
817 ret = PTR_ERR(sc->cabq);
818 goto err_bhal;
819 }
fa1c114f
JS		 820
821 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
822 if (IS_ERR(sc->txq)) {
823 ATH5K_ERR(sc, "can't setup xmit queue\n");
824 ret = PTR_ERR(sc->txq);
cec8db23 825 goto err_queues;
fa1c114f
JS		 826 }
827
828 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
829 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
830 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
6e220662 831 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 832 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2111ac0d 833 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
fa1c114f 834
0e149cf5
BC		 835 ret = ath5k_eeprom_read_mac(ah, mac);
836 if (ret) {
837 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
838 sc->pdev->device);
839 goto err_queues;
840 }
841
fa1c114f
JS		 842 SET_IEEE80211_PERM_ADDR(hw, mac);
843 /* All MAC address bits matter for ACKs */
17753748 844 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 845 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
846
608b88cb
LR		 847 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
848 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 849 if (ret) {
850 ATH5K_ERR(sc, "can't initialize regulatory system\n");
851 goto err_queues;
852 }
853
fa1c114f
JS		 854 ret = ieee80211_register_hw(hw);
855 if (ret) {
856 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
857 goto err_queues;
858 }
859
608b88cb
LR		 860 if (!ath_is_world_regd(regulatory))
861 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 862
3a078876
BC		 863 ath5k_init_leds(sc);
864
40ca22ea
BR		 865 ath5k_sysfs_register(sc);
866
fa1c114f
JS		 867 return 0;
868err_queues:
869 ath5k_txq_release(sc);
870err_bhal:
871 ath5k_hw_release_tx_queue(ah, sc->bhalq);
872err_desc:
873 ath5k_desc_free(sc, pdev);
874err:
875 return ret;
876}
877
878static void
879ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
880{
881 struct ath5k_softc *sc = hw->priv;
882
883 /*
884 * NB: the order of these is important:
885 * o call the 802.11 layer before detaching ath5k_hw to
886 * insure callbacks into the driver to delete global
887 * key cache entries can be handled
888 * o reclaim the tx queue data structures after calling
889 * the 802.11 layer as we'll get called back to reclaim
890 * node state and potentially want to use them
891 * o to cleanup the tx queues the hal is called, so detach
892 * it last
893 * XXX: ??? detach ath5k_hw ???
894 * Other than that, it's straightforward...
895 */
896 ieee80211_unregister_hw(hw);
897 ath5k_desc_free(sc, pdev);
898 ath5k_txq_release(sc);
899 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 900 ath5k_unregister_leds(sc);
fa1c114f 901
40ca22ea 902 ath5k_sysfs_unregister(sc);
fa1c114f
JS		 903 /*
904 * NB: can't reclaim these until after ieee80211_ifdetach
905 * returns because we'll get called back to reclaim node
906 * state and potentially want to use them.
907 */
908}
909
910
911
912
913/********************\
914* Channel/mode setup *
915\********************/
916
917/*
918 * Convert IEEE channel number to MHz frequency.
919 */
920static inline short
921ath5k_ieee2mhz(short chan)
922{
923 if (chan <= 14 || chan >= 27)
924 return ieee80211chan2mhz(chan);
925 else
926 return 2212 + chan * 20;
927}
928
42639fcd
BC		 929/*
930 * Returns true for the channel numbers used without all_channels modparam.
931 */
932static bool ath5k_is_standard_channel(short chan)
933{
934 return ((chan <= 14) ||
935 /* UNII 1,2 */
936 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
937 /* midband */
938 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
939 /* UNII-3 */
940 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
941}
942
fa1c114f
JS		 943static unsigned int
944ath5k_copy_channels(struct ath5k_hw *ah,
945 struct ieee80211_channel *channels,
946 unsigned int mode,
947 unsigned int max)
948{
d8ee398d 949 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 950
951 if (!test_bit(mode, ah->ah_modes))
952 return 0;
953
fa1c114f 954 switch (mode) {
d8ee398d
LR		 955 case AR5K_MODE_11A:
956 case AR5K_MODE_11A_TURBO:
fa1c114f 957 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 958 size = 220 ;
fa1c114f
JS		 959 chfreq = CHANNEL_5GHZ;
960 break;
d8ee398d
LR		 961 case AR5K_MODE_11B:
962 case AR5K_MODE_11G:
963 case AR5K_MODE_11G_TURBO:
964 size = 26;
fa1c114f
JS		 965 chfreq = CHANNEL_2GHZ;
966 break;
967 default:
968 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
969 return 0;
970 }
971
972 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 973 ch = i + 1 ;
974 freq = ath5k_ieee2mhz(ch);
fa1c114f 975
d8ee398d
LR		 976 /* Check if channel is supported by the chipset */
977 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 978 continue;
979
42639fcd
BC		 980 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
981 continue;
982
d8ee398d
LR		 983 /* Write channel info and increment counter */
984 channels[count].center_freq = freq;
a3f4b914
LR		 985 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
986 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 987 switch (mode) {
988 case AR5K_MODE_11A:
989 case AR5K_MODE_11G:
990 channels[count].hw_value = chfreq | CHANNEL_OFDM;
991 break;
992 case AR5K_MODE_11A_TURBO:
993 case AR5K_MODE_11G_TURBO:
994 channels[count].hw_value = chfreq |
995 CHANNEL_OFDM | CHANNEL_TURBO;
996 break;
997 case AR5K_MODE_11B:
d8ee398d
LR		 998 channels[count].hw_value = CHANNEL_B;
999 }
fa1c114f 1000
fa1c114f
JS		 1001 count++;
1002 max--;
1003 }
1004
1005 return count;
1006}
1007
63266a65
BR		 1008static void
1009ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1010{
1011 u8 i;
1012
1013 for (i = 0; i < AR5K_MAX_RATES; i++)
1014 sc->rate_idx[b->band][i] = -1;
1015
1016 for (i = 0; i < b->n_bitrates; i++) {
1017 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1018 if (b->bitrates[i].hw_value_short)
1019 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1020 }
1021}
1022
d8ee398d 1023static int
63266a65 1024ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1025{
1026 struct ath5k_softc *sc = hw->priv;
d8ee398d 1027 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1028 struct ieee80211_supported_band *sband;
1029 int max_c, count_c = 0;
1030 int i;
fa1c114f 1031
d8ee398d 1032 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1033 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1034
1035 /* 2GHz band */
63266a65
BR		 1036 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1037 sband->band = IEEE80211_BAND_2GHZ;
1038 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1039
63266a65
BR		 1040 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1041 /* G mode */
1042 memcpy(sband->bitrates, &ath5k_rates[0],
1043 sizeof(struct ieee80211_rate) * 12);
1044 sband->n_bitrates = 12;
fa1c114f 1045
d8ee398d 1046 sband->channels = sc->channels;
d8ee398d 1047 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1048 AR5K_MODE_11G, max_c);
fa1c114f 1049
63266a65 1050 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1051 count_c = sband->n_channels;
63266a65
BR		 1052 max_c -= count_c;
1053 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1054 /* B mode */
1055 memcpy(sband->bitrates, &ath5k_rates[0],
1056 sizeof(struct ieee80211_rate) * 4);
1057 sband->n_bitrates = 4;
1058
1059 /* 5211 only supports B rates and uses 4bit rate codes
1060 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1061 * fix them up here:
1062 */
1063 if (ah->ah_version == AR5K_AR5211) {
1064 for (i = 0; i < 4; i++) {
1065 sband->bitrates[i].hw_value =
1066 sband->bitrates[i].hw_value & 0xF;
1067 sband->bitrates[i].hw_value_short =
1068 sband->bitrates[i].hw_value_short & 0xF;
1069 }
1070 }
fa1c114f 1071
63266a65
BR		 1072 sband->channels = sc->channels;
1073 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1074 AR5K_MODE_11B, max_c);
d8ee398d 1075
63266a65
BR		 1076 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1077 count_c = sband->n_channels;
d8ee398d 1078 max_c -= count_c;
fa1c114f 1079 }
63266a65 1080 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1081
63266a65 1082 /* 5GHz band, A mode */
400ec45a 1083 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1084 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1085 sband->band = IEEE80211_BAND_5GHZ;
1086 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1087
63266a65
BR		 1088 memcpy(sband->bitrates, &ath5k_rates[4],
1089 sizeof(struct ieee80211_rate) * 8);
1090 sband->n_bitrates = 8;
fa1c114f 1091
63266a65 1092 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1093 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1094 AR5K_MODE_11A, max_c);
1095
d8ee398d
LR		 1096 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1097 }
63266a65 1098 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1099
b446197c 1100 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1101
1102 return 0;
fa1c114f
JS		 1103}
1104
1105/*
e30eb4ab
JA		 1106 * Set/change channels. We always reset the chip.
1107 * To accomplish this we must first cleanup any pending DMA,
1108 * then restart stuff after a la ath5k_init.
be009370
BC		 1109 *
1110 * Called with sc->lock.
fa1c114f
JS		 1111 */
1112static int
1113ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1114{
8d67a031
BR		 1115 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1116 "channel set, resetting (%u -> %u MHz)\n",
1117 sc->curchan->center_freq, chan->center_freq);
d8ee398d 1118
e30eb4ab
JA		 1119 /*
1120 * To switch channels clear any pending DMA operations;
1121 * wait long enough for the RX fifo to drain, reset the
1122 * hardware at the new frequency, and then re-enable
1123 * the relevant bits of the h/w.
1124 */
1125 return ath5k_reset(sc, chan);
fa1c114f
JS		 1126}
1127
1128static void
1129ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1130{
fa1c114f 1131 sc->curmode = mode;
d8ee398d 1132
400ec45a 1133 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1134 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1135 } else {
1136 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1137 }
fa1c114f
JS		 1138}
1139
1140static void
1141ath5k_mode_setup(struct ath5k_softc *sc)
1142{
1143 struct ath5k_hw *ah = sc->ah;
1144 u32 rfilt;
1145
1146 /* configure rx filter */
1147 rfilt = sc->filter_flags;
1148 ath5k_hw_set_rx_filter(ah, rfilt);
1149
1150 if (ath5k_hw_hasbssidmask(ah))
1151 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1152
1153 /* configure operational mode */
ccfe5552 1154 ath5k_hw_set_opmode(ah, sc->opmode);
fa1c114f 1155
ccfe5552 1156 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
fa1c114f
JS		 1157 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1158}
1159
d8ee398d 1160static inline int
63266a65
BR		 1161ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1162{
b7266047
BC		 1163 int rix;
1164
1165 /* return base rate on errors */
1166 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1167 "hw_rix out of bounds: %x\n", hw_rix))
1168 return 0;
1169
1170 rix = sc->rate_idx[sc->curband->band][hw_rix];
1171 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1172 rix = 0;
1173
1174 return rix;
d8ee398d
LR		 1175}
1176
fa1c114f
JS		 1177/***************\
1178* Buffers setup *
1179\***************/
1180
b6ea0356
BC		 1181static
1182struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1183{
db719718 1184 struct ath_common *common = ath5k_hw_common(sc->ah);
b6ea0356 1185 struct sk_buff *skb;
b6ea0356
BC		 1186
1187 /*
1188 * Allocate buffer with headroom_needed space for the
1189 * fake physical layer header at the start.
1190 */
db719718 1191 skb = ath_rxbuf_alloc(common,
dd849782 1192 common->rx_bufsize,
aeb63cfd 1193 GFP_ATOMIC);
b6ea0356
BC		 1194
1195 if (!skb) {
1196 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
dd849782 1197 common->rx_bufsize);
b6ea0356
BC		 1198 return NULL;
1199 }
b6ea0356
BC		 1200
1201 *skb_addr = pci_map_single(sc->pdev,
cc861f74
LR		 1202 skb->data, common->rx_bufsize,
1203 PCI_DMA_FROMDEVICE);
b6ea0356
BC		 1204 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1205 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1206 dev_kfree_skb(skb);
1207 return NULL;
1208 }
1209 return skb;
1210}
1211
fa1c114f
JS		 1212static int
1213ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1214{
1215 struct ath5k_hw *ah = sc->ah;
1216 struct sk_buff *skb = bf->skb;
1217 struct ath5k_desc *ds;
b5eae9ff 1218 int ret;
fa1c114f 1219
b6ea0356
BC		 1220 if (!skb) {
1221 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1222 if (!skb)
fa1c114f 1223 return -ENOMEM;
fa1c114f 1224 bf->skb = skb;
fa1c114f
JS		 1225 }
1226
1227 /*
1228 * Setup descriptors. For receive we always terminate
1229 * the descriptor list with a self-linked entry so we'll
1230 * not get overrun under high load (as can happen with a
1231 * 5212 when ANI processing enables PHY error frames).
1232 *
beade636 1233 * To ensure the last descriptor is self-linked we create
fa1c114f
JS		 1234 * each descriptor as self-linked and add it to the end. As
1235 * each additional descriptor is added the previous self-linked
beade636 1236 * entry is "fixed" naturally. This should be safe even
fa1c114f
JS		 1237 * if DMA is happening. When processing RX interrupts we
1238 * never remove/process the last, self-linked, entry on the
beade636 1239 * descriptor list. This ensures the hardware always has
fa1c114f
JS		 1240 * someplace to write a new frame.
1241 */
1242 ds = bf->desc;
1243 ds->ds_link = bf->daddr; /* link to self */
1244 ds->ds_data = bf->skbaddr;
b5eae9ff
BR		 1245 ret = ah->ah_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
1246 if (ret)
1247 return ret;
fa1c114f
JS		 1248
1249 if (sc->rxlink != NULL)
1250 *sc->rxlink = bf->daddr;
1251 sc->rxlink = &ds->ds_link;
1252 return 0;
1253}
1254
2ac2927a
BC		 1255static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1256{
1257 struct ieee80211_hdr *hdr;
1258 enum ath5k_pkt_type htype;
1259 __le16 fc;
1260
1261 hdr = (struct ieee80211_hdr *)skb->data;
1262 fc = hdr->frame_control;
1263
1264 if (ieee80211_is_beacon(fc))
1265 htype = AR5K_PKT_TYPE_BEACON;
1266 else if (ieee80211_is_probe_resp(fc))
1267 htype = AR5K_PKT_TYPE_PROBE_RESP;
1268 else if (ieee80211_is_atim(fc))
1269 htype = AR5K_PKT_TYPE_ATIM;
1270 else if (ieee80211_is_pspoll(fc))
1271 htype = AR5K_PKT_TYPE_PSPOLL;
1272 else
1273 htype = AR5K_PKT_TYPE_NORMAL;
1274
1275 return htype;
1276}
1277
fa1c114f 1278static int
cec8db23 1279ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
8127fbdc 1280 struct ath5k_txq *txq, int padsize)
fa1c114f
JS		 1281{
1282 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1283 struct ath5k_desc *ds = bf->desc;
1284 struct sk_buff *skb = bf->skb;
a888d52d 1285 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1286 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1287 struct ieee80211_rate *rate;
1288 unsigned int mrr_rate[3], mrr_tries[3];
1289 int i, ret;
8902ff4e 1290 u16 hw_rate;
07c1e852
BC		 1291 u16 cts_rate = 0;
1292 u16 duration = 0;
8902ff4e 1293 u8 rc_flags;
fa1c114f
JS		 1294
1295 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1296
fa1c114f
JS		 1297 /* XXX endianness */
1298 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1299 PCI_DMA_TODEVICE);
1300
8902ff4e
BC		 1301 rate = ieee80211_get_tx_rate(sc->hw, info);
1302
e039fa4a 1303 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1304 flags |= AR5K_TXDESC_NOACK;
1305
8902ff4e
BC		 1306 rc_flags = info->control.rates[0].flags;
1307 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1308 rate->hw_value_short : rate->hw_value;
1309
281c56dd 1310 pktlen = skb->len;
fa1c114f 1311
8f655dde
NK		 1312 /* FIXME: If we are in g mode and rate is a CCK rate
1313 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1314 * from tx power (value is in dB units already) */
362695e1
BC		 1315 if (info->control.hw_key) {
1316 keyidx = info->control.hw_key->hw_key_idx;
1317 pktlen += info->control.hw_key->icv_len;
1318 }
07c1e852
BC		 1319 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1320 flags |= AR5K_TXDESC_RTSENA;
1321 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1322 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1323 sc->vif, pktlen, info));
1324 }
1325 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1326 flags |= AR5K_TXDESC_CTSENA;
1327 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1328 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1329 sc->vif, pktlen, info));
1330 }
fa1c114f 1331 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
8127fbdc 1332 ieee80211_get_hdrlen_from_skb(skb), padsize,
2ac2927a 1333 get_hw_packet_type(skb),
2e92e6f2 1334 (sc->power_level * 2),
8902ff4e 1335 hw_rate,
2bed03eb 1336 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1337 cts_rate, duration);
fa1c114f
JS		 1338 if (ret)
1339 goto err_unmap;
1340
2f7fe870
FF		 1341 memset(mrr_rate, 0, sizeof(mrr_rate));
1342 memset(mrr_tries, 0, sizeof(mrr_tries));
1343 for (i = 0; i < 3; i++) {
1344 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1345 if (!rate)
1346 break;
1347
1348 mrr_rate[i] = rate->hw_value;
e6a9854b 1349 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1350 }
1351
1352 ah->ah_setup_mrr_tx_desc(ah, ds,
1353 mrr_rate[0], mrr_tries[0],
1354 mrr_rate[1], mrr_tries[1],
1355 mrr_rate[2], mrr_tries[2]);
1356
fa1c114f
JS		 1357 ds->ds_link = 0;
1358 ds->ds_data = bf->skbaddr;
1359
1360 spin_lock_bh(&txq->lock);
1361 list_add_tail(&bf->list, &txq->q);
fa1c114f 1362 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1363 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1364 else /* no, so only link it */
1365 *txq->link = bf->daddr;
1366
1367 txq->link = &ds->ds_link;
c6e387a2 1368 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1369 mmiowb();
fa1c114f
JS		 1370 spin_unlock_bh(&txq->lock);
1371
1372 return 0;
1373err_unmap:
1374 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1375 return ret;
1376}
1377
1378/*******************\
1379* Descriptors setup *
1380\*******************/
1381
1382static int
1383ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1384{
1385 struct ath5k_desc *ds;
1386 struct ath5k_buf *bf;
1387 dma_addr_t da;
1388 unsigned int i;
1389 int ret;
1390
1391 /* allocate descriptors */
1392 sc->desc_len = sizeof(struct ath5k_desc) *
1393 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1394 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1395 if (sc->desc == NULL) {
1396 ATH5K_ERR(sc, "can't allocate descriptors\n");
1397 ret = -ENOMEM;
1398 goto err;
1399 }
1400 ds = sc->desc;
1401 da = sc->desc_daddr;
1402 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1403 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1404
1405 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1406 sizeof(struct ath5k_buf), GFP_KERNEL);
1407 if (bf == NULL) {
1408 ATH5K_ERR(sc, "can't allocate bufptr\n");
1409 ret = -ENOMEM;
1410 goto err_free;
1411 }
1412 sc->bufptr = bf;
1413
1414 INIT_LIST_HEAD(&sc->rxbuf);
1415 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1416 bf->desc = ds;
1417 bf->daddr = da;
1418 list_add_tail(&bf->list, &sc->rxbuf);
1419 }
1420
1421 INIT_LIST_HEAD(&sc->txbuf);
1422 sc->txbuf_len = ATH_TXBUF;
1423 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1424 da += sizeof(*ds)) {
1425 bf->desc = ds;
1426 bf->daddr = da;
1427 list_add_tail(&bf->list, &sc->txbuf);
1428 }
1429
1430 /* beacon buffer */
1431 bf->desc = ds;
1432 bf->daddr = da;
1433 sc->bbuf = bf;
1434
1435 return 0;
1436err_free:
1437 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1438err:
1439 sc->desc = NULL;
1440 return ret;
1441}
1442
1443static void
1444ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1445{
1446 struct ath5k_buf *bf;
1447
9e4e43f2 1448 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 1449 list_for_each_entry(bf, &sc->txbuf, list)
9e4e43f2 1450 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1451 list_for_each_entry(bf, &sc->rxbuf, list)
9e4e43f2 1452 ath5k_rxbuf_free_skb(sc, bf);
fa1c114f
JS		 1453
1454 /* Free memory associated with all descriptors */
1455 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1456
1457 kfree(sc->bufptr);
1458 sc->bufptr = NULL;
1459}
1460
1461
1462
1463
1464
1465/**************\
1466* Queues setup *
1467\**************/
1468
1469static struct ath5k_txq *
1470ath5k_txq_setup(struct ath5k_softc *sc,
1471 int qtype, int subtype)
1472{
1473 struct ath5k_hw *ah = sc->ah;
1474 struct ath5k_txq *txq;
1475 struct ath5k_txq_info qi = {
1476 .tqi_subtype = subtype,
1477 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1478 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1479 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1480 };
1481 int qnum;
1482
1483 /*
1484 * Enable interrupts only for EOL and DESC conditions.
1485 * We mark tx descriptors to receive a DESC interrupt
1486 * when a tx queue gets deep; otherwise waiting for the
1487 * EOL to reap descriptors. Note that this is done to
1488 * reduce interrupt load and this only defers reaping
1489 * descriptors, never transmitting frames. Aside from
1490 * reducing interrupts this also permits more concurrency.
1491 * The only potential downside is if the tx queue backs
1492 * up in which case the top half of the kernel may backup
1493 * due to a lack of tx descriptors.
1494 */
1495 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1496 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1497 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1498 if (qnum < 0) {
1499 /*
1500 * NB: don't print a message, this happens
1501 * normally on parts with too few tx queues
1502 */
1503 return ERR_PTR(qnum);
1504 }
1505 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1506 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1507 qnum, ARRAY_SIZE(sc->txqs));
1508 ath5k_hw_release_tx_queue(ah, qnum);
1509 return ERR_PTR(-EINVAL);
1510 }
1511 txq = &sc->txqs[qnum];
1512 if (!txq->setup) {
1513 txq->qnum = qnum;
1514 txq->link = NULL;
1515 INIT_LIST_HEAD(&txq->q);
1516 spin_lock_init(&txq->lock);
1517 txq->setup = true;
1518 }
1519 return &sc->txqs[qnum];
1520}
1521
1522static int
1523ath5k_beaconq_setup(struct ath5k_hw *ah)
1524{
1525 struct ath5k_txq_info qi = {
1526 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1527 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1528 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1529 /* NB: for dynamic turbo, don't enable any other interrupts */
1530 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1531 };
1532
1533 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1534}
1535
1536static int
1537ath5k_beaconq_config(struct ath5k_softc *sc)
1538{
1539 struct ath5k_hw *ah = sc->ah;
1540 struct ath5k_txq_info qi;
1541 int ret;
1542
1543 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1544 if (ret)
a951ae21
BC		 1545 goto err;
1546
05c914fe
JB		 1547 if (sc->opmode == NL80211_IFTYPE_AP ||
1548 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1549 /*
1550 * Always burst out beacon and CAB traffic
1551 * (aifs = cwmin = cwmax = 0)
1552 */
1553 qi.tqi_aifs = 0;
1554 qi.tqi_cw_min = 0;
1555 qi.tqi_cw_max = 0;
05c914fe 1556 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1557 /*
1558 * Adhoc mode; backoff between 0 and (2 * cw_min).
1559 */
1560 qi.tqi_aifs = 0;
1561 qi.tqi_cw_min = 0;
1562 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1563 }
1564
6d91e1d8
BR		 1565 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1566 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1567 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1568
c6e387a2 1569 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1570 if (ret) {
1571 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1572 "hardware queue!\n", __func__);
a951ae21 1573 goto err;
fa1c114f 1574 }
a951ae21
BC		 1575 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1576 if (ret)
1577 goto err;
fa1c114f 1578
a951ae21
BC		 1579 /* reconfigure cabq with ready time to 80% of beacon_interval */
1580 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1581 if (ret)
1582 goto err;
1583
1584 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1585 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1586 if (ret)
1587 goto err;
1588
1589 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1590err:
1591 return ret;
fa1c114f
JS		 1592}
1593
1594static void
1595ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1596{
1597 struct ath5k_buf *bf, *bf0;
1598
1599 /*
1600 * NB: this assumes output has been stopped and
1601 * we do not need to block ath5k_tx_tasklet
1602 */
1603 spin_lock_bh(&txq->lock);
1604 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1605 ath5k_debug_printtxbuf(sc, bf);
fa1c114f 1606
9e4e43f2 1607 ath5k_txbuf_free_skb(sc, bf);
fa1c114f
JS		 1608
1609 spin_lock_bh(&sc->txbuflock);
fa1c114f
JS		 1610 list_move_tail(&bf->list, &sc->txbuf);
1611 sc->txbuf_len++;
1612 spin_unlock_bh(&sc->txbuflock);
1613 }
1614 txq->link = NULL;
1615 spin_unlock_bh(&txq->lock);
1616}
1617
1618/*
1619 * Drain the transmit queues and reclaim resources.
1620 */
1621static void
1622ath5k_txq_cleanup(struct ath5k_softc *sc)
1623{
1624 struct ath5k_hw *ah = sc->ah;
1625 unsigned int i;
1626
1627 /* XXX return value */
1628 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1629 /* don't touch the hardware if marked invalid */
1630 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1631 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1632 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1633 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1634 if (sc->txqs[i].setup) {
1635 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1636 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1637 "link %p\n",
1638 sc->txqs[i].qnum,
c6e387a2 1639 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1640 sc->txqs[i].qnum),
1641 sc->txqs[i].link);
1642 }
1643 }
fa1c114f
JS		 1644
1645 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1646 if (sc->txqs[i].setup)
1647 ath5k_txq_drainq(sc, &sc->txqs[i]);
1648}
1649
1650static void
1651ath5k_txq_release(struct ath5k_softc *sc)
1652{
1653 struct ath5k_txq *txq = sc->txqs;
1654 unsigned int i;
1655
1656 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1657 if (txq->setup) {
1658 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1659 txq->setup = false;
1660 }
1661}
1662
1663
1664
1665
1666/*************\
1667* RX Handling *
1668\*************/
1669
1670/*
1671 * Enable the receive h/w following a reset.
1672 */
1673static int
1674ath5k_rx_start(struct ath5k_softc *sc)
1675{
1676 struct ath5k_hw *ah = sc->ah;
db719718 1677 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 1678 struct ath5k_buf *bf;
1679 int ret;
1680
cc861f74 1681 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
fa1c114f 1682
cc861f74
LR		 1683 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1684 common->cachelsz, common->rx_bufsize);
fa1c114f 1685
fa1c114f 1686 spin_lock_bh(&sc->rxbuflock);
26925042 1687 sc->rxlink = NULL;
fa1c114f
JS		 1688 list_for_each_entry(bf, &sc->rxbuf, list) {
1689 ret = ath5k_rxbuf_setup(sc, bf);
1690 if (ret != 0) {
1691 spin_unlock_bh(&sc->rxbuflock);
1692 goto err;
1693 }
1694 }
1695 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1696 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1697 spin_unlock_bh(&sc->rxbuflock);
1698
c6e387a2 1699 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1700 ath5k_mode_setup(sc); /* set filters, etc. */
1701 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1702
1703 return 0;
1704err:
1705 return ret;
1706}
1707
1708/*
1709 * Disable the receive h/w in preparation for a reset.
1710 */
1711static void
1712ath5k_rx_stop(struct ath5k_softc *sc)
1713{
1714 struct ath5k_hw *ah = sc->ah;
1715
c6e387a2 1716 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1717 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1718 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1719
1720 ath5k_debug_printrxbuffs(sc, ah);
1721
1722 sc->rxlink = NULL; /* just in case */
1723}
1724
1725static unsigned int
1726ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1727 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f 1728{
dc1e001b
LR		 1729 struct ath5k_hw *ah = sc->ah;
1730 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1731 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1732 unsigned int keyix, hlen;
fa1c114f 1733
b47f407b
BR		 1734 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1735 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1736 return RX_FLAG_DECRYPTED;
1737
1738 /* Apparently when a default key is used to decrypt the packet
1739 the hw does not set the index used to decrypt. In such cases
1740 get the index from the packet. */
798ee985 1741 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1742 if (ieee80211_has_protected(hdr->frame_control) &&
1743 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1744 skb->len >= hlen + 4) {
fa1c114f
JS		 1745 keyix = skb->data[hlen + 3] >> 6;
1746
dc1e001b 1747 if (test_bit(keyix, common->keymap))
fa1c114f
JS		 1748 return RX_FLAG_DECRYPTED;
1749 }
1750
1751 return 0;
1752}
1753
036cd1ec
BR		 1754
1755static void
6ba81c2c
BR		 1756ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1757 struct ieee80211_rx_status *rxs)
036cd1ec 1758{
954fecea 1759 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1760 u64 tsf, bc_tstamp;
036cd1ec
BR		 1761 u32 hw_tu;
1762 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1763
24b56e70 1764 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1765 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1766 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1767 /*
6ba81c2c
BR		 1768 * Received an IBSS beacon with the same BSSID. Hardware *must*
1769 * have updated the local TSF. We have to work around various
1770 * hardware bugs, though...
036cd1ec 1771 */
6ba81c2c
BR		 1772 tsf = ath5k_hw_get_tsf64(sc->ah);
1773 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1774 hw_tu = TSF_TO_TU(tsf);
1775
1776 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1777 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1778 (unsigned long long)bc_tstamp,
1779 (unsigned long long)rxs->mactime,
1780 (unsigned long long)(rxs->mactime - bc_tstamp),
1781 (unsigned long long)tsf);
6ba81c2c
BR		 1782
1783 /*
1784 * Sometimes the HW will give us a wrong tstamp in the rx
1785 * status, causing the timestamp extension to go wrong.
1786 * (This seems to happen especially with beacon frames bigger
1787 * than 78 byte (incl. FCS))
1788 * But we know that the receive timestamp must be later than the
1789 * timestamp of the beacon since HW must have synced to that.
1790 *
1791 * NOTE: here we assume mactime to be after the frame was
1792 * received, not like mac80211 which defines it at the start.
1793 */
1794 if (bc_tstamp > rxs->mactime) {
036cd1ec 1795 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1796 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1797 (unsigned long long)rxs->mactime,
1798 (unsigned long long)tsf);
6ba81c2c 1799 rxs->mactime = tsf;
036cd1ec 1800 }
6ba81c2c
BR		 1801
1802 /*
1803 * Local TSF might have moved higher than our beacon timers,
1804 * in that case we have to update them to continue sending
1805 * beacons. This also takes care of synchronizing beacon sending
1806 * times with other stations.
1807 */
1808 if (hw_tu >= sc->nexttbtt)
1809 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1810 }
1811}
1812
b4ea449d
BR		 1813static void
1814ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1815{
1816 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1817 struct ath5k_hw *ah = sc->ah;
1818 struct ath_common *common = ath5k_hw_common(ah);
1819
1820 /* only beacons from our BSSID */
1821 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1822 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1823 return;
1824
1825 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1826 rssi);
1827
1828 /* in IBSS mode we should keep RSSI statistics per neighbour */
1829 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1830}
1831
8127fbdc
BP		 1832/*
1833 * Compute padding position. skb must contains an IEEE 802.11 frame
1834 */
1835static int ath5k_common_padpos(struct sk_buff *skb)
1836{
1837 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1838 __le16 frame_control = hdr->frame_control;
1839 int padpos = 24;
1840
1841 if (ieee80211_has_a4(frame_control)) {
1842 padpos += ETH_ALEN;
1843 }
1844 if (ieee80211_is_data_qos(frame_control)) {
1845 padpos += IEEE80211_QOS_CTL_LEN;
1846 }
1847
1848 return padpos;
1849}
1850
1851/*
1852 * This function expects a 802.11 frame and returns the number of
1853 * bytes added, or -1 if we don't have enought header room.
1854 */
1855
1856static int ath5k_add_padding(struct sk_buff *skb)
1857{
1858 int padpos = ath5k_common_padpos(skb);
1859 int padsize = padpos & 3;
1860
1861 if (padsize && skb->len>padpos) {
1862
1863 if (skb_headroom(skb) < padsize)
1864 return -1;
1865
1866 skb_push(skb, padsize);
1867 memmove(skb->data, skb->data+padsize, padpos);
1868 return padsize;
1869 }
1870
1871 return 0;
1872}
1873
1874/*
1875 * This function expects a 802.11 frame and returns the number of
1876 * bytes removed
1877 */
1878
1879static int ath5k_remove_padding(struct sk_buff *skb)
1880{
1881 int padpos = ath5k_common_padpos(skb);
1882 int padsize = padpos & 3;
1883
1884 if (padsize && skb->len>=padpos+padsize) {
1885 memmove(skb->data + padsize, skb->data, padpos);
1886 skb_pull(skb, padsize);
1887 return padsize;
1888 }
1889
1890 return 0;
1891}
1892
fa1c114f
JS		 1893static void
1894ath5k_tasklet_rx(unsigned long data)
1895{
1c5256bb 1896 struct ieee80211_rx_status *rxs;
b47f407b 1897 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1898 struct sk_buff *skb, *next_skb;
1899 dma_addr_t next_skb_addr;
fa1c114f 1900 struct ath5k_softc *sc = (void *)data;
cc861f74
LR		 1901 struct ath5k_hw *ah = sc->ah;
1902 struct ath_common *common = ath5k_hw_common(ah);
c57ca815 1903 struct ath5k_buf *bf;
fa1c114f 1904 struct ath5k_desc *ds;
fa1c114f 1905 int ret;
1c5256bb 1906 int rx_flag;
fa1c114f
JS		 1907
1908 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1909 if (list_empty(&sc->rxbuf)) {
1910 ATH5K_WARN(sc, "empty rx buf pool\n");
1911 goto unlock;
1912 }
fa1c114f 1913 do {
1c5256bb 1914 rx_flag = 0;
d6894b5b 1915
fa1c114f
JS		 1916 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1917 BUG_ON(bf->skb == NULL);
1918 skb = bf->skb;
1919 ds = bf->desc;
1920
c57ca815
BC		 1921 /* bail if HW is still using self-linked descriptor */
1922 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1923 break;
fa1c114f 1924
b47f407b 1925 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1926 if (unlikely(ret == -EINPROGRESS))
1927 break;
1928 else if (unlikely(ret)) {
1929 ATH5K_ERR(sc, "error in processing rx descriptor\n");
7644395f 1930 sc->stats.rxerr_proc++;
65872e6b 1931 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1932 return;
1933 }
1934
7644395f
BR		 1935 sc->stats.rx_all_count++;
1936
b47f407b 1937 if (unlikely(rs.rs_status)) {
7644395f
BR		 1938 if (rs.rs_status & AR5K_RXERR_CRC)
1939 sc->stats.rxerr_crc++;
1940 if (rs.rs_status & AR5K_RXERR_FIFO)
1941 sc->stats.rxerr_fifo++;
1942 if (rs.rs_status & AR5K_RXERR_PHY) {
1943 sc->stats.rxerr_phy++;
da35111a
BR		 1944 if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
1945 sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
fa1c114f 1946 goto next;
7644395f 1947 }
b47f407b 1948 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1949 /*
1950 * Decrypt error. If the error occurred
1951 * because there was no hardware key, then
1952 * let the frame through so the upper layers
1953 * can process it. This is necessary for 5210
1954 * parts which have no way to setup a ``clear''
1955 * key cache entry.
1956 *
1957 * XXX do key cache faulting
1958 */
7644395f 1959 sc->stats.rxerr_decrypt++;
b47f407b
BR		 1960 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1961 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1962 goto accept;
1963 }
b47f407b 1964 if (rs.rs_status & AR5K_RXERR_MIC) {
1c5256bb 1965 rx_flag |= RX_FLAG_MMIC_ERROR;
7644395f 1966 sc->stats.rxerr_mic++;
fa1c114f
JS		 1967 goto accept;
1968 }
1969
1970 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1971 if ((rs.rs_status &
1972 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1973 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1974 goto next;
1975 }
9637e516
LR		 1976
1977 if (unlikely(rs.rs_more)) {
1978 sc->stats.rxerr_jumbo++;
1979 goto next;
1980
1981 }
fa1c114f 1982accept:
b6ea0356
BC		 1983 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1984
1985 /*
1986 * If we can't replace bf->skb with a new skb under memory
1987 * pressure, just skip this packet
1988 */
1989 if (!next_skb)
1990 goto next;
1991
cc861f74 1992 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
fa1c114f 1993 PCI_DMA_FROMDEVICE);
b47f407b 1994 skb_put(skb, rs.rs_datalen);
fa1c114f 1995
0fe45b1d
BP		 1996 /* The MAC header is padded to have 32-bit boundary if the
1997 * packet payload is non-zero. The general calculation for
1998 * padsize would take into account odd header lengths:
1999 * padsize = (4 - hdrlen % 4) % 4; However, since only
2000 * even-length headers are used, padding can only be 0 or 2
2001 * bytes and we can optimize this a bit. In addition, we must
2002 * not try to remove padding from short control frames that do
2003 * not have payload. */
8127fbdc
BP		 2004 ath5k_remove_padding(skb);
2005
1c5256bb 2006 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 2007
c0e1899b
BR		 2008 /*
2009 * always extend the mac timestamp, since this information is
2010 * also needed for proper IBSS merging.
2011 *
2012 * XXX: it might be too late to do it here, since rs_tstamp is
2013 * 15bit only. that means TSF extension has to be done within
2014 * 32768usec (about 32ms). it might be necessary to move this to
2015 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 2016 *
2017 * Unfortunately we don't know when the hardware takes the rx
2018 * timestamp (beginning of phy frame, data frame, end of rx?).
2019 * The only thing we know is that it is hardware specific...
2020 * On AR5213 it seems the rx timestamp is at the end of the
2021 * frame, but i'm not sure.
2022 *
2023 * NOTE: mac80211 defines mactime at the beginning of the first
2024 * data symbol. Since we don't have any time references it's
2025 * impossible to comply to that. This affects IBSS merge only
2026 * right now, so it's not too bad...
c0e1899b 2027 */
1c5256bb
BC		 2028 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2029 rxs->flag = rx_flag | RX_FLAG_TSFT;
c0e1899b 2030
1c5256bb
BC		 2031 rxs->freq = sc->curchan->center_freq;
2032 rxs->band = sc->curband->band;
fa1c114f 2033
54c7c91e 2034 rxs->signal = sc->ah->ah_noise_floor + rs.rs_rssi;
6e0e0bf8 2035
1c5256bb 2036 rxs->antenna = rs.rs_antenna;
604eeadd
BR		 2037
2038 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2039 sc->stats.antenna_rx[rs.rs_antenna]++;
2040 else
2041 sc->stats.antenna_rx[0]++; /* invalid */
2042
1c5256bb
BC		 2043 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2044 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 2045
1c5256bb
BC		 2046 if (rxs->rate_idx >= 0 && rs.rs_rate ==
2047 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2048 rxs->flag |= RX_FLAG_SHORTPRE;
06303352 2049
fa1c114f
JS		 2050 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
2051
b4ea449d
BR		 2052 ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi);
2053
036cd1ec 2054 /* check beacons in IBSS mode */
05c914fe 2055 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1c5256bb 2056 ath5k_check_ibss_tsf(sc, skb, rxs);
036cd1ec 2057
f1d58c25 2058 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 2059
2060 bf->skb = next_skb;
2061 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 2062next:
2063 list_move_tail(&bf->list, &sc->rxbuf);
2064 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 2065unlock:
fa1c114f
JS		 2066 spin_unlock(&sc->rxbuflock);
2067}
2068
2069
2070
2071
2072/*************\
2073* TX Handling *
2074\*************/
2075
2076static void
2077ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2078{
b47f407b 2079 struct ath5k_tx_status ts = {};
fa1c114f
JS		 2080 struct ath5k_buf *bf, *bf0;
2081 struct ath5k_desc *ds;
2082 struct sk_buff *skb;
e039fa4a 2083 struct ieee80211_tx_info *info;
2f7fe870 2084 int i, ret;
fa1c114f
JS		 2085
2086 spin_lock(&txq->lock);
2087 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2088 ds = bf->desc;
2089
a05988bb
BC		 2090 /*
2091 * It's possible that the hardware can say the buffer is
2092 * completed when it hasn't yet loaded the ds_link from
2093 * host memory and moved on. If there are more TX
2094 * descriptors in the queue, wait for TXDP to change
2095 * before processing this one.
2096 */
2097 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2098 !list_is_last(&bf->list, &txq->q))
2099 break;
2100
b47f407b 2101 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 2102 if (unlikely(ret == -EINPROGRESS))
2103 break;
2104 else if (unlikely(ret)) {
2105 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2106 ret, txq->qnum);
2107 break;
2108 }
2109
7644395f 2110 sc->stats.tx_all_count++;
fa1c114f 2111 skb = bf->skb;
a888d52d 2112 info = IEEE80211_SKB_CB(skb);
fa1c114f 2113 bf->skb = NULL;
e039fa4a 2114
fa1c114f
JS		 2115 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2116 PCI_DMA_TODEVICE);
2117
e6a9854b 2118 ieee80211_tx_info_clear_status(info);
2f7fe870 2119 for (i = 0; i < 4; i++) {
e6a9854b
JB		 2120 struct ieee80211_tx_rate *r =
2121 &info->status.rates[i];
2f7fe870
FF		 2122
2123 if (ts.ts_rate[i]) {
e6a9854b
JB		 2124 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2125 r->count = ts.ts_retry[i];
2f7fe870 2126 } else {
e6a9854b
JB		 2127 r->idx = -1;
2128 r->count = 0;
2f7fe870
FF		 2129 }
2130 }
2131
e6a9854b
JB		 2132 /* count the successful attempt as well */
2133 info->status.rates[ts.ts_final_idx].count++;
2134
b47f407b 2135 if (unlikely(ts.ts_status)) {
495391d7 2136 sc->stats.ack_fail++;
7644395f 2137 if (ts.ts_status & AR5K_TXERR_FILT) {
e039fa4a 2138 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
7644395f
BR		 2139 sc->stats.txerr_filt++;
2140 }
2141 if (ts.ts_status & AR5K_TXERR_XRETRY)
2142 sc->stats.txerr_retry++;
2143 if (ts.ts_status & AR5K_TXERR_FIFO)
2144 sc->stats.txerr_fifo++;
fa1c114f 2145 } else {
e039fa4a
JB		 2146 info->flags |= IEEE80211_TX_STAT_ACK;
2147 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2148 }
2149
8127fbdc
BP		 2150 /*
2151 * Remove MAC header padding before giving the frame
2152 * back to mac80211.
2153 */
2154 ath5k_remove_padding(skb);
2155
604eeadd
BR		 2156 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2157 sc->stats.antenna_tx[ts.ts_antenna]++;
2158 else
2159 sc->stats.antenna_tx[0]++; /* invalid */
2160
e039fa4a 2161 ieee80211_tx_status(sc->hw, skb);
fa1c114f
JS		 2162
2163 spin_lock(&sc->txbuflock);
fa1c114f
JS		 2164 list_move_tail(&bf->list, &sc->txbuf);
2165 sc->txbuf_len++;
2166 spin_unlock(&sc->txbuflock);
2167 }
2168 if (likely(list_empty(&txq->q)))
2169 txq->link = NULL;
2170 spin_unlock(&txq->lock);
2171 if (sc->txbuf_len > ATH_TXBUF / 5)
2172 ieee80211_wake_queues(sc->hw);
2173}
2174
2175static void
2176ath5k_tasklet_tx(unsigned long data)
2177{
8784d2ee 2178 int i;
fa1c114f
JS		 2179 struct ath5k_softc *sc = (void *)data;
2180
8784d2ee
BC		 2181 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2182 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2183 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2184}
2185
2186
fa1c114f
JS		 2187/*****************\
2188* Beacon handling *
2189\*****************/
2190
2191/*
2192 * Setup the beacon frame for transmit.
2193 */
2194static int
e039fa4a 2195ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2196{
2197 struct sk_buff *skb = bf->skb;
a888d52d 2198 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2199 struct ath5k_hw *ah = sc->ah;
2200 struct ath5k_desc *ds;
2bed03eb
NK		 2201 int ret = 0;
2202 u8 antenna;
fa1c114f 2203 u32 flags;
8127fbdc 2204 const int padsize = 0;
fa1c114f
JS		 2205
2206 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2207 PCI_DMA_TODEVICE);
2208 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2209 "skbaddr %llx\n", skb, skb->data, skb->len,
2210 (unsigned long long)bf->skbaddr);
8d8bb39b 2211 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2212 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2213 return -EIO;
2214 }
2215
2216 ds = bf->desc;
2bed03eb 2217 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2218
2219 flags = AR5K_TXDESC_NOACK;
05c914fe 2220 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2221 ds->ds_link = bf->daddr; /* self-linked */
2222 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2223 } else
fa1c114f 2224 ds->ds_link = 0;
2bed03eb
NK		 2225
2226 /*
2227 * If we use multiple antennas on AP and use
2228 * the Sectored AP scenario, switch antenna every
2229 * 4 beacons to make sure everybody hears our AP.
2230 * When a client tries to associate, hw will keep
2231 * track of the tx antenna to be used for this client
2232 * automaticaly, based on ACKed packets.
2233 *
2234 * Note: AP still listens and transmits RTS on the
2235 * default antenna which is supposed to be an omni.
2236 *
2237 * Note2: On sectored scenarios it's possible to have
2238 * multiple antennas (1omni -the default- and 14 sectors)
2239 * so if we choose to actually support this mode we need
2240 * to allow user to set how many antennas we have and tweak
2241 * the code below to send beacons on all of them.
2242 */
2243 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2244 antenna = sc->bsent & 4 ? 2 : 1;
2245
fa1c114f 2246
8f655dde
NK		 2247 /* FIXME: If we are in g mode and rate is a CCK rate
2248 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2249 * from tx power (value is in dB units already) */
fa1c114f 2250 ds->ds_data = bf->skbaddr;
281c56dd 2251 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 2252 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 2253 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2254 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2255 1, AR5K_TXKEYIX_INVALID,
400ec45a 2256 antenna, flags, 0, 0);
fa1c114f
JS		 2257 if (ret)
2258 goto err_unmap;
2259
2260 return 0;
2261err_unmap:
2262 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2263 return ret;
2264}
2265
2266/*
2267 * Transmit a beacon frame at SWBA. Dynamic updates to the
2268 * frame contents are done as needed and the slot time is
2269 * also adjusted based on current state.
2270 *
acf3c1a5
BC		 2271 * This is called from software irq context (beacontq or restq
2272 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2273 */
2274static void
2275ath5k_beacon_send(struct ath5k_softc *sc)
2276{
2277 struct ath5k_buf *bf = sc->bbuf;
2278 struct ath5k_hw *ah = sc->ah;
cec8db23 2279 struct sk_buff *skb;
fa1c114f 2280
be9b7259 2281 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2282
05c914fe
JB		 2283 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2284 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2285 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2286 return;
2287 }
2288 /*
2289 * Check if the previous beacon has gone out. If
2290 * not don't don't try to post another, skip this
2291 * period and wait for the next. Missed beacons
2292 * indicate a problem and should not occur. If we
2293 * miss too many consecutive beacons reset the device.
2294 */
2295 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2296 sc->bmisscount++;
be9b7259 2297 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2298 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2299 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2300 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2301 "stuck beacon time (%u missed)\n",
2302 sc->bmisscount);
8d67a031
BR		 2303 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2304 "stuck beacon, resetting\n");
fa1c114f
JS		 2305 tasklet_schedule(&sc->restq);
2306 }
2307 return;
2308 }
2309 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2310 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2311 "resume beacon xmit after %u misses\n",
2312 sc->bmisscount);
2313 sc->bmisscount = 0;
2314 }
2315
2316 /*
2317 * Stop any current dma and put the new frame on the queue.
2318 * This should never fail since we check above that no frames
2319 * are still pending on the queue.
2320 */
2321 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2322 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2323 /* NB: hw still stops DMA, so proceed */
2324 }
fa1c114f 2325
1071db86
BC		 2326 /* refresh the beacon for AP mode */
2327 if (sc->opmode == NL80211_IFTYPE_AP)
2328 ath5k_beacon_update(sc->hw, sc->vif);
2329
c6e387a2
NK		 2330 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2331 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2332 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2333 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2334
cec8db23
BC		 2335 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2336 while (skb) {
2337 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2338 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2339 }
2340
fa1c114f
JS		 2341 sc->bsent++;
2342}
2343
2344
9804b98d
BR		 2345/**
2346 * ath5k_beacon_update_timers - update beacon timers
2347 *
2348 * @sc: struct ath5k_softc pointer we are operating on
2349 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2350 * beacon timer update based on the current HW TSF.
2351 *
2352 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2353 * of a received beacon or the current local hardware TSF and write it to the
2354 * beacon timer registers.
2355 *
2356 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2357 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2358 * when we otherwise know we have to update the timers, but we keep it in this
2359 * function to have it all together in one place.
2360 */
fa1c114f 2361static void
9804b98d 2362ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2363{
2364 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2365 u32 nexttbtt, intval, hw_tu, bc_tu;
2366 u64 hw_tsf;
fa1c114f
JS		 2367
2368 intval = sc->bintval & AR5K_BEACON_PERIOD;
2369 if (WARN_ON(!intval))
2370 return;
2371
9804b98d
BR		 2372 /* beacon TSF converted to TU */
2373 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2374
9804b98d
BR		 2375 /* current TSF converted to TU */
2376 hw_tsf = ath5k_hw_get_tsf64(ah);
2377 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2378
9804b98d
BR		 2379#define FUDGE 3
2380 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2381 if (bc_tsf == -1) {
2382 /*
2383 * no beacons received, called internally.
2384 * just need to refresh timers based on HW TSF.
2385 */
2386 nexttbtt = roundup(hw_tu + FUDGE, intval);
2387 } else if (bc_tsf == 0) {
2388 /*
2389 * no beacon received, probably called by ath5k_reset_tsf().
2390 * reset TSF to start with 0.
2391 */
2392 nexttbtt = intval;
2393 intval |= AR5K_BEACON_RESET_TSF;
2394 } else if (bc_tsf > hw_tsf) {
2395 /*
2396 * beacon received, SW merge happend but HW TSF not yet updated.
2397 * not possible to reconfigure timers yet, but next time we
2398 * receive a beacon with the same BSSID, the hardware will
2399 * automatically update the TSF and then we need to reconfigure
2400 * the timers.
2401 */
2402 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2403 "need to wait for HW TSF sync\n");
2404 return;
2405 } else {
2406 /*
2407 * most important case for beacon synchronization between STA.
2408 *
2409 * beacon received and HW TSF has been already updated by HW.
2410 * update next TBTT based on the TSF of the beacon, but make
2411 * sure it is ahead of our local TSF timer.
2412 */
2413 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2414 }
2415#undef FUDGE
fa1c114f 2416
036cd1ec
BR		 2417 sc->nexttbtt = nexttbtt;
2418
fa1c114f 2419 intval |= AR5K_BEACON_ENA;
fa1c114f 2420 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2421
2422 /*
2423 * debugging output last in order to preserve the time critical aspect
2424 * of this function
2425 */
2426 if (bc_tsf == -1)
2427 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2428 "reconfigured timers based on HW TSF\n");
2429 else if (bc_tsf == 0)
2430 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2431 "reset HW TSF and timers\n");
2432 else
2433 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2434 "updated timers based on beacon TSF\n");
2435
2436 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2437 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2438 (unsigned long long) bc_tsf,
2439 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2440 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2441 intval & AR5K_BEACON_PERIOD,
2442 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2443 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2444}
2445
2446
036cd1ec
BR		 2447/**
2448 * ath5k_beacon_config - Configure the beacon queues and interrupts
2449 *
2450 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2451 *
036cd1ec 2452 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2453 * interrupts to detect TSF updates only.
fa1c114f
JS		 2454 */
2455static void
2456ath5k_beacon_config(struct ath5k_softc *sc)
2457{
2458 struct ath5k_hw *ah = sc->ah;
b5f03956 2459 unsigned long flags;
fa1c114f 2460
21800491 2461 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2462 sc->bmisscount = 0;
dc1968e7 2463 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2464
21800491 2465 if (sc->enable_beacon) {
fa1c114f 2466 /*
036cd1ec
BR		 2467 * In IBSS mode we use a self-linked tx descriptor and let the
2468 * hardware send the beacons automatically. We have to load it
fa1c114f 2469 * only once here.
036cd1ec 2470 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2471 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2472 */
2473 ath5k_beaconq_config(sc);
fa1c114f 2474
036cd1ec
BR		 2475 sc->imask |= AR5K_INT_SWBA;
2476
da966bca 2477 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2478 if (ath5k_hw_hasveol(ah))
da966bca 2479 ath5k_beacon_send(sc);
da966bca
JS		 2480 } else
2481 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2482 } else {
2483 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2484 }
fa1c114f 2485
c6e387a2 2486 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2487 mmiowb();
2488 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2489}
2490
428cbd4f
NK		 2491static void ath5k_tasklet_beacon(unsigned long data)
2492{
2493 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2494
2495 /*
2496 * Software beacon alert--time to send a beacon.
2497 *
2498 * In IBSS mode we use this interrupt just to
2499 * keep track of the next TBTT (target beacon
2500 * transmission time) in order to detect wether
2501 * automatic TSF updates happened.
2502 */
2503 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2504 /* XXX: only if VEOL suppported */
2505 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2506 sc->nexttbtt += sc->bintval;
2507 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2508 "SWBA nexttbtt: %x hw_tu: %x "
2509 "TSF: %llx\n",
2510 sc->nexttbtt,
2511 TSF_TO_TU(tsf),
2512 (unsigned long long) tsf);
2513 } else {
2514 spin_lock(&sc->block);
2515 ath5k_beacon_send(sc);
2516 spin_unlock(&sc->block);
2517 }
2518}
2519
fa1c114f
JS		 2520
2521/********************\
2522* Interrupt handling *
2523\********************/
2524
2525static int
bb2becac 2526ath5k_init(struct ath5k_softc *sc)
fa1c114f 2527{
bc1b32d6
EO		 2528 struct ath5k_hw *ah = sc->ah;
2529 int ret, i;
fa1c114f
JS		 2530
2531 mutex_lock(&sc->lock);
2532
2533 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2534
2535 /*
2536 * Stop anything previously setup. This is safe
2537 * no matter this is the first time through or not.
2538 */
2539 ath5k_stop_locked(sc);
2540
2541 /*
2542 * The basic interface to setting the hardware in a good
2543 * state is ``reset''. On return the hardware is known to
2544 * be powered up and with interrupts disabled. This must
2545 * be followed by initialization of the appropriate bits
2546 * and then setup of the interrupt mask.
2547 */
d8ee398d
LR		 2548 sc->curchan = sc->hw->conf.channel;
2549 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2550 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2551 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2111ac0d
BR		 2552 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2553
209d889b 2554 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2555 if (ret)
2556 goto done;
fa1c114f 2557
e6a3b616
TD		 2558 ath5k_rfkill_hw_start(ah);
2559
bc1b32d6
EO		 2560 /*
2561 * Reset the key cache since some parts do not reset the
2562 * contents on initial power up or resume from suspend.
2563 */
2564 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2565 ath5k_hw_reset_key(ah, i);
2566
0edc9a67 2567 ath5k_hw_set_ack_bitrate_high(ah, true);
fa1c114f
JS		 2568 ret = 0;
2569done:
274c7c36 2570 mmiowb();
fa1c114f
JS		 2571 mutex_unlock(&sc->lock);
2572 return ret;
2573}
2574
2575static int
2576ath5k_stop_locked(struct ath5k_softc *sc)
2577{
2578 struct ath5k_hw *ah = sc->ah;
2579
2580 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2581 test_bit(ATH_STAT_INVALID, sc->status));
2582
2583 /*
2584 * Shutdown the hardware and driver:
2585 * stop output from above
2586 * disable interrupts
2587 * turn off timers
2588 * turn off the radio
2589 * clear transmit machinery
2590 * clear receive machinery
2591 * drain and release tx queues
2592 * reclaim beacon resources
2593 * power down hardware
2594 *
2595 * Note that some of this work is not possible if the
2596 * hardware is gone (invalid).
2597 */
2598 ieee80211_stop_queues(sc->hw);
2599
2600 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2601 ath5k_led_off(sc);
c6e387a2 2602 ath5k_hw_set_imr(ah, 0);
274c7c36 2603 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2604 }
2605 ath5k_txq_cleanup(sc);
2606 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2607 ath5k_rx_stop(sc);
2608 ath5k_hw_phy_disable(ah);
2609 } else
2610 sc->rxlink = NULL;
2611
2612 return 0;
2613}
2614
2615/*
2616 * Stop the device, grabbing the top-level lock to protect
2617 * against concurrent entry through ath5k_init (which can happen
2618 * if another thread does a system call and the thread doing the
2619 * stop is preempted).
2620 */
2621static int
bb2becac 2622ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2623{
2624 int ret;
2625
2626 mutex_lock(&sc->lock);
2627 ret = ath5k_stop_locked(sc);
2628 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2629 /*
edd7fc70
NK		 2630 * Don't set the card in full sleep mode!
2631 *
2632 * a) When the device is in this state it must be carefully
2633 * woken up or references to registers in the PCI clock
2634 * domain may freeze the bus (and system). This varies
2635 * by chip and is mostly an issue with newer parts
2636 * (madwifi sources mentioned srev >= 0x78) that go to
2637 * sleep more quickly.
2638 *
2639 * b) On older chips full sleep results a weird behaviour
2640 * during wakeup. I tested various cards with srev < 0x78
2641 * and they don't wake up after module reload, a second
2642 * module reload is needed to bring the card up again.
2643 *
2644 * Until we figure out what's going on don't enable
2645 * full chip reset on any chip (this is what Legacy HAL
2646 * and Sam's HAL do anyway). Instead Perform a full reset
2647 * on the device (same as initial state after attach) and
2648 * leave it idle (keep MAC/BB on warm reset) */
2649 ret = ath5k_hw_on_hold(sc->ah);
2650
2651 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2652 "putting device to sleep\n");
fa1c114f 2653 }
9e4e43f2 2654 ath5k_txbuf_free_skb(sc, sc->bbuf);
8bdd5b9c 2655
274c7c36 2656 mmiowb();
fa1c114f
JS		 2657 mutex_unlock(&sc->lock);
2658
10488f8a
JS		 2659 tasklet_kill(&sc->rxtq);
2660 tasklet_kill(&sc->txtq);
2661 tasklet_kill(&sc->restq);
6e220662 2662 tasklet_kill(&sc->calib);
acf3c1a5 2663 tasklet_kill(&sc->beacontq);
2111ac0d 2664 tasklet_kill(&sc->ani_tasklet);
fa1c114f 2665
e6a3b616
TD		 2666 ath5k_rfkill_hw_stop(sc->ah);
2667
fa1c114f
JS		 2668 return ret;
2669}
2670
6a8a3f6b
BR		 2671static void
2672ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2673{
2111ac0d
BR		 2674 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2675 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2676 /* run ANI only when full calibration is not active */
2677 ah->ah_cal_next_ani = jiffies +
2678 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2679 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2680
2681 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2682 ah->ah_cal_next_full = jiffies +
2683 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2684 tasklet_schedule(&ah->ah_sc->calib);
2685 }
2686 /* we could use SWI to generate enough interrupts to meet our
2687 * calibration interval requirements, if necessary:
2688 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2689}
2690
fa1c114f
JS		 2691static irqreturn_t
2692ath5k_intr(int irq, void *dev_id)
2693{
2694 struct ath5k_softc *sc = dev_id;
2695 struct ath5k_hw *ah = sc->ah;
2696 enum ath5k_int status;
2697 unsigned int counter = 1000;
2698
2699 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2700 !ath5k_hw_is_intr_pending(ah)))
2701 return IRQ_NONE;
2702
2703 do {
fa1c114f
JS		 2704 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2705 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2706 status, sc->imask);
fa1c114f
JS		 2707 if (unlikely(status & AR5K_INT_FATAL)) {
2708 /*
2709 * Fatal errors are unrecoverable.
2710 * Typically these are caused by DMA errors.
2711 */
8d67a031
BR		 2712 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2713 "fatal int, resetting\n");
fa1c114f
JS		 2714 tasklet_schedule(&sc->restq);
2715 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2716 /*
2717 * Receive buffers are full. Either the bus is busy or
2718 * the CPU is not fast enough to process all received
2719 * frames.
2720 * Older chipsets need a reset to come out of this
2721 * condition, but we treat it as RX for newer chips.
2722 * We don't know exactly which versions need a reset -
2723 * this guess is copied from the HAL.
2724 */
2725 sc->stats.rxorn_intr++;
8d67a031
BR		 2726 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2727 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2728 "rx overrun, resetting\n");
87d77c4e 2729 tasklet_schedule(&sc->restq);
8d67a031 2730 }
87d77c4e
BR		 2731 else
2732 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2733 } else {
2734 if (status & AR5K_INT_SWBA) {
56d2ac76 2735 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2736 }
2737 if (status & AR5K_INT_RXEOL) {
2738 /*
2739 * NB: the hardware should re-read the link when
2740 * RXE bit is written, but it doesn't work at
2741 * least on older hardware revs.
2742 */
2743 sc->rxlink = NULL;
2744 }
2745 if (status & AR5K_INT_TXURN) {
2746 /* bump tx trigger level */
2747 ath5k_hw_update_tx_triglevel(ah, true);
2748 }
4c674c60 2749 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2750 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2751 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2752 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2753 tasklet_schedule(&sc->txtq);
2754 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2755 /* TODO */
fa1c114f
JS		 2756 }
2757 if (status & AR5K_INT_MIB) {
2111ac0d 2758 sc->stats.mib_intr++;
495391d7 2759 ath5k_hw_update_mib_counters(ah);
2111ac0d 2760 ath5k_ani_mib_intr(ah);
fa1c114f 2761 }
e6a3b616 2762 if (status & AR5K_INT_GPIO)
e6a3b616 2763 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2764
fa1c114f 2765 }
2516baa6 2766 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2767
2768 if (unlikely(!counter))
2769 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2770
6a8a3f6b 2771 ath5k_intr_calibration_poll(ah);
6e220662 2772
fa1c114f
JS		 2773 return IRQ_HANDLED;
2774}
2775
2776static void
2777ath5k_tasklet_reset(unsigned long data)
2778{
2779 struct ath5k_softc *sc = (void *)data;
2780
397f385b 2781 ath5k_reset(sc, sc->curchan);
fa1c114f
JS		 2782}
2783
2784/*
2785 * Periodically recalibrate the PHY to account
2786 * for temperature/environment changes.
2787 */
2788static void
6e220662 2789ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2790{
2791 struct ath5k_softc *sc = (void *)data;
2792 struct ath5k_hw *ah = sc->ah;
2793
6e220662 2794 /* Only full calibration for now */
e65e1d77 2795 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2796
fa1c114f 2797 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2798 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2799 sc->curchan->hw_value);
fa1c114f 2800
6f3b414a 2801 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2802 /*
2803 * Rfgain is out of bounds, reset the chip
2804 * to load new gain values.
2805 */
2806 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
6b5d117e 2807 ath5k_reset(sc, sc->curchan);
fa1c114f
JS		 2808 }
2809 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2810 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2811 ieee80211_frequency_to_channel(
2812 sc->curchan->center_freq));
fa1c114f 2813
0e8e02dd 2814 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
afe86286
BR		 2815 * doesn't. We stop the queues so that calibration doesn't interfere
2816 * with TX and don't run it as often */
2817 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2818 ah->ah_cal_next_nf = jiffies +
2819 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2820 ieee80211_stop_queues(sc->hw);
2821 ath5k_hw_update_noise_floor(ah);
2822 ieee80211_wake_queues(sc->hw);
2823 }
6e220662 2824
e65e1d77 2825 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2826}
2827
2828
2111ac0d
BR		 2829static void
2830ath5k_tasklet_ani(unsigned long data)
2831{
2832 struct ath5k_softc *sc = (void *)data;
2833 struct ath5k_hw *ah = sc->ah;
2834
2835 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2836 ath5k_ani_calibration(ah);
2837 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2838}
2839
2840
fa1c114f
JS		 2841/********************\
2842* Mac80211 functions *
2843\********************/
2844
2845static int
e039fa4a 2846ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2847{
2848 struct ath5k_softc *sc = hw->priv;
2849
2850 return ath5k_tx_queue(hw, skb, sc->txq);
2851}
2852
2853static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2854 struct ath5k_txq *txq)
fa1c114f
JS		 2855{
2856 struct ath5k_softc *sc = hw->priv;
2857 struct ath5k_buf *bf;
2858 unsigned long flags;
0fe45b1d 2859 int padsize;
fa1c114f
JS		 2860
2861 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2862
05c914fe 2863 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2864 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2865
2866 /*
2867 * the hardware expects the header padded to 4 byte boundaries
2868 * if this is not the case we add the padding after the header
2869 */
8127fbdc
BP		 2870 padsize = ath5k_add_padding(skb);
2871 if (padsize < 0) {
2872 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2873 " headroom to pad");
2874 goto drop_packet;
fa1c114f
JS		 2875 }
2876
fa1c114f
JS		 2877 spin_lock_irqsave(&sc->txbuflock, flags);
2878 if (list_empty(&sc->txbuf)) {
2879 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2880 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2881 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2882 goto drop_packet;
fa1c114f
JS		 2883 }
2884 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2885 list_del(&bf->list);
2886 sc->txbuf_len--;
2887 if (list_empty(&sc->txbuf))
2888 ieee80211_stop_queues(hw);
2889 spin_unlock_irqrestore(&sc->txbuflock, flags);
2890
2891 bf->skb = skb;
2892
8127fbdc 2893 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
fa1c114f
JS		 2894 bf->skb = NULL;
2895 spin_lock_irqsave(&sc->txbuflock, flags);
2896 list_add_tail(&bf->list, &sc->txbuf);
2897 sc->txbuf_len++;
2898 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2899 goto drop_packet;
fa1c114f 2900 }
5a0fe8ac 2901 return NETDEV_TX_OK;
fa1c114f 2902
5a0fe8ac
BC		 2903drop_packet:
2904 dev_kfree_skb_any(skb);
71ef99c8 2905 return NETDEV_TX_OK;
fa1c114f
JS		 2906}
2907
209d889b
BC		 2908/*
2909 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2910 * and change to the given channel.
2911 */
fa1c114f 2912static int
209d889b 2913ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2914{
fa1c114f
JS		 2915 struct ath5k_hw *ah = sc->ah;
2916 int ret;
2917
2918 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2919
209d889b 2920 if (chan) {
c6e387a2 2921 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2922 ath5k_txq_cleanup(sc);
2923 ath5k_rx_stop(sc);
209d889b
BC		 2924
2925 sc->curchan = chan;
2926 sc->curband = &sc->sbands[chan->band];
d7dc1003 2927 }
3355443a 2928 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2929 if (ret) {
fa1c114f
JS		 2930 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2931 goto err;
2932 }
d7dc1003 2933
fa1c114f 2934 ret = ath5k_rx_start(sc);
d7dc1003 2935 if (ret) {
fa1c114f
JS		 2936 ATH5K_ERR(sc, "can't start recv logic\n");
2937 goto err;
2938 }
d7dc1003 2939
2111ac0d
BR		 2940 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2941
ac559526
BR		 2942 ah->ah_cal_next_full = jiffies;
2943 ah->ah_cal_next_ani = jiffies;
afe86286
BR		 2944 ah->ah_cal_next_nf = jiffies;
2945
fa1c114f 2946 /*
d7dc1003
JS		 2947 * Change channels and update the h/w rate map if we're switching;
2948 * e.g. 11a to 11b/g.
2949 *
2950 * We may be doing a reset in response to an ioctl that changes the
2951 * channel so update any state that might change as a result.
fa1c114f
JS		 2952 *
2953 * XXX needed?
2954 */
2955/* ath5k_chan_change(sc, c); */
fa1c114f 2956
d7dc1003
JS		 2957 ath5k_beacon_config(sc);
2958 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2959
397f385b
BR		 2960 ieee80211_wake_queues(sc->hw);
2961
fa1c114f
JS		 2962 return 0;
2963err:
2964 return ret;
2965}
2966
2967static int ath5k_start(struct ieee80211_hw *hw)
2968{
bb2becac 2969 return ath5k_init(hw->priv);
fa1c114f
JS		 2970}
2971
2972static void ath5k_stop(struct ieee80211_hw *hw)
2973{
bb2becac 2974 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2975}
2976
2977static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2978 struct ieee80211_vif *vif)
fa1c114f
JS		 2979{
2980 struct ath5k_softc *sc = hw->priv;
2981 int ret;
2982
2983 mutex_lock(&sc->lock);
32bfd35d 2984 if (sc->vif) {
fa1c114f
JS		 2985 ret = 0;
2986 goto end;
2987 }
2988
1ed32e4f 2989 sc->vif = vif;
fa1c114f 2990
1ed32e4f 2991 switch (vif->type) {
da966bca 2992 case NL80211_IFTYPE_AP:
05c914fe
JB		 2993 case NL80211_IFTYPE_STATION:
2994 case NL80211_IFTYPE_ADHOC:
b706e65b 2995 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2996 case NL80211_IFTYPE_MONITOR:
1ed32e4f 2997 sc->opmode = vif->type;
fa1c114f
JS		 2998 break;
2999 default:
3000 ret = -EOPNOTSUPP;
3001 goto end;
3002 }
67d2e2df 3003
ccfe5552
BR		 3004 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
3005
1ed32e4f 3006 ath5k_hw_set_lladdr(sc->ah, vif->addr);
ae6f53f2 3007 ath5k_mode_setup(sc);
67d2e2df 3008
fa1c114f
JS		 3009 ret = 0;
3010end:
3011 mutex_unlock(&sc->lock);
3012 return ret;
3013}
3014
3015static void
3016ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3017 struct ieee80211_vif *vif)
fa1c114f
JS		 3018{
3019 struct ath5k_softc *sc = hw->priv;
0e149cf5 3020 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 3021
3022 mutex_lock(&sc->lock);
1ed32e4f 3023 if (sc->vif != vif)
fa1c114f
JS		 3024 goto end;
3025
0e149cf5 3026 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 3027 sc->vif = NULL;
fa1c114f
JS		 3028end:
3029 mutex_unlock(&sc->lock);
3030}
3031
d8ee398d
LR		 3032/*
3033 * TODO: Phy disable/diversity etc
3034 */
fa1c114f 3035static int
e8975581 3036ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 3037{
3038 struct ath5k_softc *sc = hw->priv;
a0823810 3039 struct ath5k_hw *ah = sc->ah;
e8975581 3040 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 3041 int ret = 0;
be009370
BC		 3042
3043 mutex_lock(&sc->lock);
fa1c114f 3044
e30eb4ab
JA		 3045 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3046 ret = ath5k_chan_set(sc, conf->channel);
3047 if (ret < 0)
3048 goto unlock;
3049 }
2bed03eb 3050
a0823810
NK		 3051 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3052 (sc->power_level != conf->power_level)) {
3053 sc->power_level = conf->power_level;
3054
3055 /* Half dB steps */
3056 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3057 }
fa1c114f 3058
2bed03eb
NK		 3059 /* TODO:
3060 * 1) Move this on config_interface and handle each case
3061 * separately eg. when we have only one STA vif, use
3062 * AR5K_ANTMODE_SINGLE_AP
3063 *
3064 * 2) Allow the user to change antenna mode eg. when only
3065 * one antenna is present
3066 *
3067 * 3) Allow the user to set default/tx antenna when possible
3068 *
3069 * 4) Default mode should handle 90% of the cases, together
3070 * with fixed a/b and single AP modes we should be able to
3071 * handle 99%. Sectored modes are extreme cases and i still
3072 * haven't found a usage for them. If we decide to support them,
3073 * then we must allow the user to set how many tx antennas we
3074 * have available
3075 */
caec9112 3076 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 3077
55aa4e0f 3078unlock:
be009370 3079 mutex_unlock(&sc->lock);
55aa4e0f 3080 return ret;
fa1c114f
JS		 3081}
3082
3ac64bee 3083static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 3084 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 3085{
3086 u32 mfilt[2], val;
3ac64bee 3087 u8 pos;
22bedad3 3088 struct netdev_hw_addr *ha;
3ac64bee
JB		 3089
3090 mfilt[0] = 0;
3091 mfilt[1] = 1;
3092
22bedad3 3093 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 3094 /* calculate XOR of eight 6-bit values */
22bedad3 3095 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 3096 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 3097 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 3098 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3099 pos &= 0x3f;
3100 mfilt[pos / 32] |= (1 << (pos % 32));
3101 /* XXX: we might be able to just do this instead,
3102 * but not sure, needs testing, if we do use this we'd
3103 * neet to inform below to not reset the mcast */
3104 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 3105 * ha->addr[5]); */
3ac64bee
JB		 3106 }
3107
3108 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3109}
3110
fa1c114f
JS		 3111#define SUPPORTED_FIF_FLAGS \
3112 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3113 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3114 FIF_BCN_PRBRESP_PROMISC
3115/*
3116 * o always accept unicast, broadcast, and multicast traffic
3117 * o multicast traffic for all BSSIDs will be enabled if mac80211
3118 * says it should be
3119 * o maintain current state of phy ofdm or phy cck error reception.
3120 * If the hardware detects any of these type of errors then
3121 * ath5k_hw_get_rx_filter() will pass to us the respective
3122 * hardware filters to be able to receive these type of frames.
3123 * o probe request frames are accepted only when operating in
3124 * hostap, adhoc, or monitor modes
3125 * o enable promiscuous mode according to the interface state
3126 * o accept beacons:
3127 * - when operating in adhoc mode so the 802.11 layer creates
3128 * node table entries for peers,
3129 * - when operating in station mode for collecting rssi data when
3130 * the station is otherwise quiet, or
3131 * - when scanning
3132 */
3133static void ath5k_configure_filter(struct ieee80211_hw *hw,
3134 unsigned int changed_flags,
3135 unsigned int *new_flags,
3ac64bee 3136 u64 multicast)
fa1c114f
JS		 3137{
3138 struct ath5k_softc *sc = hw->priv;
3139 struct ath5k_hw *ah = sc->ah;
3ac64bee 3140 u32 mfilt[2], rfilt;
fa1c114f 3141
56d1de0a
BC		 3142 mutex_lock(&sc->lock);
3143
3ac64bee
JB		 3144 mfilt[0] = multicast;
3145 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3146
3147 /* Only deal with supported flags */
3148 changed_flags &= SUPPORTED_FIF_FLAGS;
3149 *new_flags &= SUPPORTED_FIF_FLAGS;
3150
3151 /* If HW detects any phy or radar errors, leave those filters on.
3152 * Also, always enable Unicast, Broadcasts and Multicast
3153 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3154 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3155 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3156 AR5K_RX_FILTER_MCAST);
3157
3158 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3159 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 3160 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3161 } else {
fa1c114f 3162 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3163 }
fa1c114f
JS		 3164 }
3165
6b5dcccb
BC		 3166 if (test_bit(ATH_STAT_PROMISC, sc->status))
3167 rfilt |= AR5K_RX_FILTER_PROM;
3168
fa1c114f
JS		 3169 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3170 if (*new_flags & FIF_ALLMULTI) {
3171 mfilt[0] = ~0;
3172 mfilt[1] = ~0;
fa1c114f
JS		 3173 }
3174
3175 /* This is the best we can do */
3176 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3177 rfilt |= AR5K_RX_FILTER_PHYERR;
3178
3179 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3180 * and probes for any BSSID, this needs testing */
3181 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3182 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3183
3184 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3185 * set we should only pass on control frames for this
3186 * station. This needs testing. I believe right now this
3187 * enables *all* control frames, which is OK.. but
3188 * but we should see if we can improve on granularity */
3189 if (*new_flags & FIF_CONTROL)
3190 rfilt |= AR5K_RX_FILTER_CONTROL;
3191
3192 /* Additional settings per mode -- this is per ath5k */
3193
3194 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3195
56d1de0a
BC		 3196 switch (sc->opmode) {
3197 case NL80211_IFTYPE_MESH_POINT:
3198 case NL80211_IFTYPE_MONITOR:
3199 rfilt |= AR5K_RX_FILTER_CONTROL |
3200 AR5K_RX_FILTER_BEACON |
3201 AR5K_RX_FILTER_PROBEREQ |
3202 AR5K_RX_FILTER_PROM;
3203 break;
3204 case NL80211_IFTYPE_AP:
3205 case NL80211_IFTYPE_ADHOC:
3206 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3207 AR5K_RX_FILTER_BEACON;
3208 break;
3209 case NL80211_IFTYPE_STATION:
3210 if (sc->assoc)
3211 rfilt |= AR5K_RX_FILTER_BEACON;
3212 default:
3213 break;
3214 }
fa1c114f
JS		 3215
3216 /* Set filters */
0bbac08f 3217 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3218
3219 /* Set multicast bits */
3220 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3221 /* Set the cached hw filter flags, this will alter actually
3222 * be set in HW */
3223 sc->filter_flags = rfilt;
56d1de0a
BC		 3224
3225 mutex_unlock(&sc->lock);
fa1c114f
JS		 3226}
3227
3228static int
3229ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3230 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3231 struct ieee80211_key_conf *key)
fa1c114f
JS		 3232{
3233 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3234 struct ath5k_hw *ah = sc->ah;
3235 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3236 int ret = 0;
3237
9ad9a26e
BC		 3238 if (modparam_nohwcrypt)
3239 return -EOPNOTSUPP;
3240
65b5a698
BC		 3241 if (sc->opmode == NL80211_IFTYPE_AP)
3242 return -EOPNOTSUPP;
3243
0bbac08f 3244 switch (key->alg) {
fa1c114f 3245 case ALG_WEP:
fa1c114f 3246 case ALG_TKIP:
3f64b435 3247 break;
fa1c114f 3248 case ALG_CCMP:
1c818740
BC		 3249 if (sc->ah->ah_aes_support)
3250 break;
3251
fa1c114f
JS		 3252 return -EOPNOTSUPP;
3253 default:
3254 WARN_ON(1);
3255 return -EINVAL;
3256 }
3257
3258 mutex_lock(&sc->lock);
3259
3260 switch (cmd) {
3261 case SET_KEY:
dc822b5d
JB		 3262 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3263 sta ? sta->addr : NULL);
fa1c114f
JS		 3264 if (ret) {
3265 ATH5K_ERR(sc, "can't set the key\n");
3266 goto unlock;
3267 }
dc1e001b 3268 __set_bit(key->keyidx, common->keymap);
fa1c114f 3269 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3270 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3271 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3272 break;
3273 case DISABLE_KEY:
3274 ath5k_hw_reset_key(sc->ah, key->keyidx);
dc1e001b 3275 __clear_bit(key->keyidx, common->keymap);
fa1c114f
JS		 3276 break;
3277 default:
3278 ret = -EINVAL;
3279 goto unlock;
3280 }
3281
3282unlock:
274c7c36 3283 mmiowb();
fa1c114f
JS		 3284 mutex_unlock(&sc->lock);
3285 return ret;
3286}
3287
3288static int
3289ath5k_get_stats(struct ieee80211_hw *hw,
3290 struct ieee80211_low_level_stats *stats)
3291{
3292 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3293
3294 /* Force update */
495391d7 3295 ath5k_hw_update_mib_counters(sc->ah);
fa1c114f 3296
495391d7
BR		 3297 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3298 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3299 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3300 stats->dot11FCSErrorCount = sc->stats.fcs_error;
fa1c114f
JS		 3301
3302 return 0;
3303}
3304
55ee82b5
HS		 3305static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3306 struct survey_info *survey)
3307{
3308 struct ath5k_softc *sc = hw->priv;
3309 struct ieee80211_conf *conf = &hw->conf;
3310
3311 if (idx != 0)
3312 return -ENOENT;
3313
3314 survey->channel = conf->channel;
3315 survey->filled = SURVEY_INFO_NOISE_DBM;
3316 survey->noise = sc->ah->ah_noise_floor;
3317
3318 return 0;
3319}
3320
fa1c114f
JS		 3321static u64
3322ath5k_get_tsf(struct ieee80211_hw *hw)
3323{
3324 struct ath5k_softc *sc = hw->priv;
3325
3326 return ath5k_hw_get_tsf64(sc->ah);
3327}
3328
3b5d665b
AF		 3329static void
3330ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3331{
3332 struct ath5k_softc *sc = hw->priv;
3333
3334 ath5k_hw_set_tsf64(sc->ah, tsf);
3335}
3336
fa1c114f
JS		 3337static void
3338ath5k_reset_tsf(struct ieee80211_hw *hw)
3339{
3340 struct ath5k_softc *sc = hw->priv;
3341
9804b98d
BR		 3342 /*
3343 * in IBSS mode we need to update the beacon timers too.
3344 * this will also reset the TSF if we call it with 0
3345 */
05c914fe 3346 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3347 ath5k_beacon_update_timers(sc, 0);
3348 else
3349 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3350}
3351
1071db86
BC		 3352/*
3353 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3354 * this is called only once at config_bss time, for AP we do it every
3355 * SWBA interrupt so that the TIM will reflect buffered frames.
3356 *
3357 * Called with the beacon lock.
3358 */
fa1c114f 3359static int
1071db86 3360ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3361{
fa1c114f 3362 int ret;
1071db86 3363 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3364 struct sk_buff *skb;
3365
3366 if (WARN_ON(!vif)) {
3367 ret = -EINVAL;
3368 goto out;
3369 }
3370
3371 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3372
3373 if (!skb) {
3374 ret = -ENOMEM;
3375 goto out;
3376 }
fa1c114f
JS		 3377
3378 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3379
9e4e43f2 3380 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 3381 sc->bbuf->skb = skb;
e039fa4a 3382 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3383 if (ret)
3384 sc->bbuf->skb = NULL;
1071db86
BC		 3385out:
3386 return ret;
3387}
3388
02969b38
MX		 3389static void
3390set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3391{
3392 struct ath5k_softc *sc = hw->priv;
3393 struct ath5k_hw *ah = sc->ah;
3394 u32 rfilt;
3395 rfilt = ath5k_hw_get_rx_filter(ah);
3396 if (enable)
3397 rfilt |= AR5K_RX_FILTER_BEACON;
3398 else
3399 rfilt &= ~AR5K_RX_FILTER_BEACON;
3400 ath5k_hw_set_rx_filter(ah, rfilt);
3401 sc->filter_flags = rfilt;
3402}
fa1c114f 3403
02969b38
MX		 3404static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3405 struct ieee80211_vif *vif,
3406 struct ieee80211_bss_conf *bss_conf,
3407 u32 changes)
3408{
3409 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3410 struct ath5k_hw *ah = sc->ah;
954fecea 3411 struct ath_common *common = ath5k_hw_common(ah);
21800491 3412 unsigned long flags;
2d0ddec5
JB		 3413
3414 mutex_lock(&sc->lock);
3415 if (WARN_ON(sc->vif != vif))
3416 goto unlock;
3417
3418 if (changes & BSS_CHANGED_BSSID) {
3419 /* Cache for later use during resets */
954fecea 3420 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
8ce54c5a 3421 common->curaid = 0;
be5d6b75 3422 ath5k_hw_set_associd(ah);
2d0ddec5
JB		 3423 mmiowb();
3424 }
57c4d7b4
JB		 3425
3426 if (changes & BSS_CHANGED_BEACON_INT)
3427 sc->bintval = bss_conf->beacon_int;
3428
02969b38 3429 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3430 sc->assoc = bss_conf->assoc;
3431 if (sc->opmode == NL80211_IFTYPE_STATION)
3432 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3433 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3434 AR5K_LED_ASSOC : AR5K_LED_INIT);
8ce54c5a
LR		 3435 if (bss_conf->assoc) {
3436 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3437 "Bss Info ASSOC %d, bssid: %pM\n",
3438 bss_conf->aid, common->curbssid);
3439 common->curaid = bss_conf->aid;
3440 ath5k_hw_set_associd(ah);
3441 /* Once ANI is available you would start it here */
3442 }
02969b38 3443 }
2d0ddec5 3444
21800491
BC		 3445 if (changes & BSS_CHANGED_BEACON) {
3446 spin_lock_irqsave(&sc->block, flags);
3447 ath5k_beacon_update(hw, vif);
3448 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3449 }
3450
21800491
BC		 3451 if (changes & BSS_CHANGED_BEACON_ENABLED)
3452 sc->enable_beacon = bss_conf->enable_beacon;
3453
3454 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3455 BSS_CHANGED_BEACON_INT))
3456 ath5k_beacon_config(sc);
3457
2d0ddec5
JB		 3458 unlock:
3459 mutex_unlock(&sc->lock);
02969b38 3460}
f0f3d388
BC		 3461
3462static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3463{
3464 struct ath5k_softc *sc = hw->priv;
3465 if (!sc->assoc)
3466 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3467}
3468
3469static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3470{
3471 struct ath5k_softc *sc = hw->priv;
3472 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3473 AR5K_LED_ASSOC : AR5K_LED_INIT);
3474}
6e08d228
LT		 3475
3476/**
3477 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3478 *
3479 * @hw: struct ieee80211_hw pointer
3480 * @coverage_class: IEEE 802.11 coverage class number
3481 *
3482 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3483 * coverage class. The values are persistent, they are restored after device
3484 * reset.
3485 */
3486static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3487{
3488 struct ath5k_softc *sc = hw->priv;
3489
3490 mutex_lock(&sc->lock);
3491 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3492 mutex_unlock(&sc->lock);
3493}
Clone of davem's net-next-2.6 tree