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ath5k: Move tx frame completion into separate function
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
6ccf15a1 51#include <linux/pci-aspm.h>
fa1c114f
JS		 52#include <linux/ethtool.h>
53#include <linux/uaccess.h>
5a0e3ad6 54#include <linux/slab.h>
fa1c114f
JS		 55
56#include <net/ieee80211_radiotap.h>
57
58#include <asm/unaligned.h>
59
60#include "base.h"
61#include "reg.h"
62#include "debug.h"
2111ac0d 63#include "ani.h"
fa1c114f 64
9ad9a26e 65static int modparam_nohwcrypt;
46802a4f 66module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 67MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 68
42639fcd 69static int modparam_all_channels;
46802a4f 70module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 71MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
72
fa1c114f
JS		 73/* Module info */
74MODULE_AUTHOR("Jiri Slaby");
75MODULE_AUTHOR("Nick Kossifidis");
76MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 79MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f 80
8a63facc
BC		 81static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
82static int ath5k_beacon_update(struct ieee80211_hw *hw,
83 struct ieee80211_vif *vif);
84static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 85
86/* Known PCI ids */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 106 { 0 }
107};
108MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
109
110/* Known SREVs */
2c91108c 111static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148};
149
2c91108c 150static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 /* XR missing */
190};
191
9e4e43f2 192static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 193 struct ath5k_buf *bf)
194{
195 BUG_ON(!bf);
196 if (!bf->skb)
197 return;
198 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
199 PCI_DMA_TODEVICE);
00482973 200 dev_kfree_skb_any(bf->skb);
fa1c114f 201 bf->skb = NULL;
39d63f2a
BR		 202 bf->skbaddr = 0;
203 bf->desc->ds_data = 0;
fa1c114f
JS		 204}
205
9e4e43f2 206static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 207 struct ath5k_buf *bf)
208{
cc861f74
LR		 209 struct ath5k_hw *ah = sc->ah;
210 struct ath_common *common = ath5k_hw_common(ah);
211
a6c8d375
FF		 212 BUG_ON(!bf);
213 if (!bf->skb)
214 return;
cc861f74 215 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 216 PCI_DMA_FROMDEVICE);
217 dev_kfree_skb_any(bf->skb);
218 bf->skb = NULL;
39d63f2a
BR		 219 bf->skbaddr = 0;
220 bf->desc->ds_data = 0;
a6c8d375
FF		 221}
222
223
fa1c114f
JS		 224static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
225{
226 u64 tsf = ath5k_hw_get_tsf64(ah);
227
228 if ((tsf & 0x7fff) < rstamp)
229 tsf -= 0x8000;
230
231 return (tsf & ~0x7fff) | rstamp;
232}
233
fa1c114f
JS		 234static const char *
235ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
236{
237 const char *name = "xxxxx";
238 unsigned int i;
239
240 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
241 if (srev_names[i].sr_type != type)
242 continue;
75d0edb8
NK		 243
244 if ((val & 0xf0) == srev_names[i].sr_val)
245 name = srev_names[i].sr_name;
246
247 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 248 name = srev_names[i].sr_name;
249 break;
250 }
251 }
252
253 return name;
254}
e5aa8474
LR		 255static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
256{
257 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
258 return ath5k_hw_reg_read(ah, reg_offset);
259}
260
261static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
262{
263 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
264 ath5k_hw_reg_write(ah, val, reg_offset);
265}
266
267static const struct ath_ops ath5k_common_ops = {
268 .read = ath5k_ioread32,
269 .write = ath5k_iowrite32,
270};
fa1c114f 271
8a63facc
BC		 272/***********************\
273* Driver Initialization *
274\***********************/
275
276static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 277{
8a63facc
BC		 278 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
279 struct ath5k_softc *sc = hw->priv;
280 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 281
8a63facc
BC		 282 return ath_reg_notifier_apply(wiphy, request, regulatory);
283}
6ccf15a1 284
8a63facc
BC		 285/********************\
286* Channel/mode setup *
287\********************/
fa1c114f 288
8a63facc
BC		 289/*
290 * Convert IEEE channel number to MHz frequency.
291 */
292static inline short
293ath5k_ieee2mhz(short chan)
294{
295 if (chan <= 14 || chan >= 27)
296 return ieee80211chan2mhz(chan);
297 else
298 return 2212 + chan * 20;
299}
fa1c114f 300
8a63facc
BC		 301/*
302 * Returns true for the channel numbers used without all_channels modparam.
303 */
304static bool ath5k_is_standard_channel(short chan)
305{
306 return ((chan <= 14) ||
307 /* UNII 1,2 */
308 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
309 /* midband */
310 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
311 /* UNII-3 */
312 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
313}
fa1c114f 314
8a63facc
BC		 315static unsigned int
316ath5k_copy_channels(struct ath5k_hw *ah,
317 struct ieee80211_channel *channels,
318 unsigned int mode,
319 unsigned int max)
320{
321 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f 322
8a63facc
BC		 323 if (!test_bit(mode, ah->ah_modes))
324 return 0;
fa1c114f 325
8a63facc
BC		 326 switch (mode) {
327 case AR5K_MODE_11A:
328 case AR5K_MODE_11A_TURBO:
329 /* 1..220, but 2GHz frequencies are filtered by check_channel */
330 size = 220 ;
331 chfreq = CHANNEL_5GHZ;
332 break;
333 case AR5K_MODE_11B:
334 case AR5K_MODE_11G:
335 case AR5K_MODE_11G_TURBO:
336 size = 26;
337 chfreq = CHANNEL_2GHZ;
338 break;
339 default:
340 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
341 return 0;
fa1c114f
JS		 342 }
343
8a63facc
BC		 344 for (i = 0, count = 0; i < size && max > 0; i++) {
345 ch = i + 1 ;
346 freq = ath5k_ieee2mhz(ch);
fa1c114f 347
8a63facc
BC		 348 /* Check if channel is supported by the chipset */
349 if (!ath5k_channel_ok(ah, freq, chfreq))
350 continue;
f59ac048 351
8a63facc
BC		 352 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
353 continue;
f59ac048 354
8a63facc
BC		 355 /* Write channel info and increment counter */
356 channels[count].center_freq = freq;
357 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
358 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
359 switch (mode) {
360 case AR5K_MODE_11A:
361 case AR5K_MODE_11G:
362 channels[count].hw_value = chfreq | CHANNEL_OFDM;
363 break;
364 case AR5K_MODE_11A_TURBO:
365 case AR5K_MODE_11G_TURBO:
366 channels[count].hw_value = chfreq |
367 CHANNEL_OFDM | CHANNEL_TURBO;
368 break;
369 case AR5K_MODE_11B:
370 channels[count].hw_value = CHANNEL_B;
371 }
fa1c114f 372
8a63facc
BC		 373 count++;
374 max--;
375 }
fa1c114f 376
8a63facc
BC		 377 return count;
378}
fa1c114f 379
8a63facc
BC		 380static void
381ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
382{
383 u8 i;
fa1c114f 384
8a63facc
BC		 385 for (i = 0; i < AR5K_MAX_RATES; i++)
386 sc->rate_idx[b->band][i] = -1;
fa1c114f 387
8a63facc
BC		 388 for (i = 0; i < b->n_bitrates; i++) {
389 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
390 if (b->bitrates[i].hw_value_short)
391 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 392 }
8a63facc 393}
fa1c114f 394
8a63facc
BC		 395static int
396ath5k_setup_bands(struct ieee80211_hw *hw)
397{
398 struct ath5k_softc *sc = hw->priv;
399 struct ath5k_hw *ah = sc->ah;
400 struct ieee80211_supported_band *sband;
401 int max_c, count_c = 0;
402 int i;
fa1c114f 403
8a63facc
BC		 404 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
405 max_c = ARRAY_SIZE(sc->channels);
db719718 406
8a63facc
BC		 407 /* 2GHz band */
408 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
409 sband->band = IEEE80211_BAND_2GHZ;
410 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 411
8a63facc
BC		 412 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
413 /* G mode */
414 memcpy(sband->bitrates, &ath5k_rates[0],
415 sizeof(struct ieee80211_rate) * 12);
416 sband->n_bitrates = 12;
2f7fe870 417
8a63facc
BC		 418 sband->channels = sc->channels;
419 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
420 AR5K_MODE_11G, max_c);
fa1c114f 421
8a63facc
BC		 422 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
423 count_c = sband->n_channels;
424 max_c -= count_c;
425 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
426 /* B mode */
427 memcpy(sband->bitrates, &ath5k_rates[0],
428 sizeof(struct ieee80211_rate) * 4);
429 sband->n_bitrates = 4;
fa1c114f 430
8a63facc
BC		 431 /* 5211 only supports B rates and uses 4bit rate codes
432 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
433 * fix them up here:
434 */
435 if (ah->ah_version == AR5K_AR5211) {
436 for (i = 0; i < 4; i++) {
437 sband->bitrates[i].hw_value =
438 sband->bitrates[i].hw_value & 0xF;
439 sband->bitrates[i].hw_value_short =
440 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 441 }
442 }
fa1c114f 443
8a63facc
BC		 444 sband->channels = sc->channels;
445 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
446 AR5K_MODE_11B, max_c);
fa1c114f 447
8a63facc
BC		 448 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
449 count_c = sband->n_channels;
450 max_c -= count_c;
451 }
452 ath5k_setup_rate_idx(sc, sband);
fa1c114f 453
8a63facc
BC		 454 /* 5GHz band, A mode */
455 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
456 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
457 sband->band = IEEE80211_BAND_5GHZ;
458 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 459
8a63facc
BC		 460 memcpy(sband->bitrates, &ath5k_rates[4],
461 sizeof(struct ieee80211_rate) * 8);
462 sband->n_bitrates = 8;
fa1c114f 463
8a63facc
BC		 464 sband->channels = &sc->channels[count_c];
465 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
466 AR5K_MODE_11A, max_c);
fa1c114f 467
8a63facc
BC		 468 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
469 }
470 ath5k_setup_rate_idx(sc, sband);
471
472 ath5k_debug_dump_bands(sc);
fa1c114f 473
fa1c114f
JS		 474 return 0;
475}
476
8a63facc
BC		 477/*
478 * Set/change channels. We always reset the chip.
479 * To accomplish this we must first cleanup any pending DMA,
480 * then restart stuff after a la ath5k_init.
481 *
482 * Called with sc->lock.
483 */
484static int
485ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
486{
487 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
488 "channel set, resetting (%u -> %u MHz)\n",
489 sc->curchan->center_freq, chan->center_freq);
490
8451d22d 491 /*
8a63facc
BC		 492 * To switch channels clear any pending DMA operations;
493 * wait long enough for the RX fifo to drain, reset the
494 * hardware at the new frequency, and then re-enable
495 * the relevant bits of the h/w.
8451d22d 496 */
8a63facc 497 return ath5k_reset(sc, chan);
fa1c114f 498}
fa1c114f 499
8a63facc
BC		 500static void
501ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 502{
8a63facc 503 sc->curmode = mode;
f769c36b 504
8a63facc
BC		 505 if (mode == AR5K_MODE_11A) {
506 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
507 } else {
508 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
509 }
f769c36b
BC		 510}
511
8a63facc
BC		 512static void
513ath5k_mode_setup(struct ath5k_softc *sc)
fa1c114f 514{
fa1c114f 515 struct ath5k_hw *ah = sc->ah;
8a63facc 516 u32 rfilt;
fa1c114f 517
8a63facc
BC		 518 /* configure rx filter */
519 rfilt = sc->filter_flags;
520 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f 521
8a63facc
BC		 522 if (ath5k_hw_hasbssidmask(ah))
523 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
a6668193 524
8a63facc
BC		 525 /* configure operational mode */
526 ath5k_hw_set_opmode(ah, sc->opmode);
fa1c114f 527
8a63facc
BC		 528 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
529 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
530}
fa1c114f 531
8a63facc
BC		 532static inline int
533ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
534{
535 int rix;
fa1c114f 536
8a63facc
BC		 537 /* return base rate on errors */
538 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
539 "hw_rix out of bounds: %x\n", hw_rix))
540 return 0;
541
542 rix = sc->rate_idx[sc->curband->band][hw_rix];
543 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
544 rix = 0;
545
546 return rix;
547}
548
549/***************\
550* Buffers setup *
551\***************/
552
553static
554struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
555{
556 struct ath_common *common = ath5k_hw_common(sc->ah);
557 struct sk_buff *skb;
fa1c114f
JS		 558
559 /*
8a63facc
BC		 560 * Allocate buffer with headroom_needed space for the
561 * fake physical layer header at the start.
fa1c114f 562 */
8a63facc
BC		 563 skb = ath_rxbuf_alloc(common,
564 common->rx_bufsize,
565 GFP_ATOMIC);
fa1c114f 566
8a63facc
BC		 567 if (!skb) {
568 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
569 common->rx_bufsize);
570 return NULL;
fa1c114f
JS		 571 }
572
8a63facc
BC		 573 *skb_addr = pci_map_single(sc->pdev,
574 skb->data, common->rx_bufsize,
575 PCI_DMA_FROMDEVICE);
576 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
577 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
578 dev_kfree_skb(skb);
579 return NULL;
0e149cf5 580 }
8a63facc
BC		 581 return skb;
582}
0e149cf5 583
8a63facc
BC		 584static int
585ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
586{
587 struct ath5k_hw *ah = sc->ah;
588 struct sk_buff *skb = bf->skb;
589 struct ath5k_desc *ds;
590 int ret;
fa1c114f 591
8a63facc
BC		 592 if (!skb) {
593 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
594 if (!skb)
595 return -ENOMEM;
596 bf->skb = skb;
f769c36b
BC		 597 }
598
8a63facc
BC		 599 /*
600 * Setup descriptors. For receive we always terminate
601 * the descriptor list with a self-linked entry so we'll
602 * not get overrun under high load (as can happen with a
603 * 5212 when ANI processing enables PHY error frames).
604 *
605 * To ensure the last descriptor is self-linked we create
606 * each descriptor as self-linked and add it to the end. As
607 * each additional descriptor is added the previous self-linked
608 * entry is "fixed" naturally. This should be safe even
609 * if DMA is happening. When processing RX interrupts we
610 * never remove/process the last, self-linked, entry on the
611 * descriptor list. This ensures the hardware always has
612 * someplace to write a new frame.
613 */
614 ds = bf->desc;
615 ds->ds_link = bf->daddr; /* link to self */
616 ds->ds_data = bf->skbaddr;
617 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 618 if (ret) {
8a63facc
BC		 619 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
620 return ret;
fa1c114f
JS		 621 }
622
8a63facc
BC		 623 if (sc->rxlink != NULL)
624 *sc->rxlink = bf->daddr;
625 sc->rxlink = &ds->ds_link;
fa1c114f 626 return 0;
fa1c114f
JS		 627}
628
8a63facc 629static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 630{
8a63facc
BC		 631 struct ieee80211_hdr *hdr;
632 enum ath5k_pkt_type htype;
633 __le16 fc;
fa1c114f 634
8a63facc
BC		 635 hdr = (struct ieee80211_hdr *)skb->data;
636 fc = hdr->frame_control;
fa1c114f 637
8a63facc
BC		 638 if (ieee80211_is_beacon(fc))
639 htype = AR5K_PKT_TYPE_BEACON;
640 else if (ieee80211_is_probe_resp(fc))
641 htype = AR5K_PKT_TYPE_PROBE_RESP;
642 else if (ieee80211_is_atim(fc))
643 htype = AR5K_PKT_TYPE_ATIM;
644 else if (ieee80211_is_pspoll(fc))
645 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 646 else
8a63facc 647 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 648
8a63facc 649 return htype;
42639fcd
BC		 650}
651
8a63facc
BC		 652static int
653ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
654 struct ath5k_txq *txq, int padsize)
fa1c114f 655{
8a63facc
BC		 656 struct ath5k_hw *ah = sc->ah;
657 struct ath5k_desc *ds = bf->desc;
658 struct sk_buff *skb = bf->skb;
659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
660 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
661 struct ieee80211_rate *rate;
662 unsigned int mrr_rate[3], mrr_tries[3];
663 int i, ret;
664 u16 hw_rate;
665 u16 cts_rate = 0;
666 u16 duration = 0;
667 u8 rc_flags;
fa1c114f 668
8a63facc 669 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 670
8a63facc
BC		 671 /* XXX endianness */
672 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
673 PCI_DMA_TODEVICE);
fa1c114f 674
8a63facc 675 rate = ieee80211_get_tx_rate(sc->hw, info);
fa1c114f 676
8a63facc
BC		 677 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
678 flags |= AR5K_TXDESC_NOACK;
fa1c114f 679
8a63facc
BC		 680 rc_flags = info->control.rates[0].flags;
681 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
682 rate->hw_value_short : rate->hw_value;
42639fcd 683
8a63facc
BC		 684 pktlen = skb->len;
685
686 /* FIXME: If we are in g mode and rate is a CCK rate
687 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
688 * from tx power (value is in dB units already) */
689 if (info->control.hw_key) {
690 keyidx = info->control.hw_key->hw_key_idx;
691 pktlen += info->control.hw_key->icv_len;
692 }
693 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
694 flags |= AR5K_TXDESC_RTSENA;
695 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
696 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
697 sc->vif, pktlen, info));
698 }
699 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
700 flags |= AR5K_TXDESC_CTSENA;
701 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
702 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
703 sc->vif, pktlen, info));
704 }
705 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
706 ieee80211_get_hdrlen_from_skb(skb), padsize,
707 get_hw_packet_type(skb),
708 (sc->power_level * 2),
709 hw_rate,
710 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
711 cts_rate, duration);
712 if (ret)
713 goto err_unmap;
714
715 memset(mrr_rate, 0, sizeof(mrr_rate));
716 memset(mrr_tries, 0, sizeof(mrr_tries));
717 for (i = 0; i < 3; i++) {
718 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
719 if (!rate)
400ec45a 720 break;
fa1c114f 721
8a63facc
BC		 722 mrr_rate[i] = rate->hw_value;
723 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 724 }
725
8a63facc
BC		 726 ath5k_hw_setup_mrr_tx_desc(ah, ds,
727 mrr_rate[0], mrr_tries[0],
728 mrr_rate[1], mrr_tries[1],
729 mrr_rate[2], mrr_tries[2]);
fa1c114f 730
8a63facc
BC		 731 ds->ds_link = 0;
732 ds->ds_data = bf->skbaddr;
63266a65 733
8a63facc
BC		 734 spin_lock_bh(&txq->lock);
735 list_add_tail(&bf->list, &txq->q);
925e0b06 736 txq->txq_len++;
8a63facc
BC		 737 if (txq->link == NULL) /* is this first packet? */
738 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
739 else /* no, so only link it */
740 *txq->link = bf->daddr;
63266a65 741
8a63facc
BC		 742 txq->link = &ds->ds_link;
743 ath5k_hw_start_tx_dma(ah, txq->qnum);
744 mmiowb();
745 spin_unlock_bh(&txq->lock);
746
747 return 0;
748err_unmap:
749 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
750 return ret;
63266a65
BR		 751}
752
8a63facc
BC		 753/*******************\
754* Descriptors setup *
755\*******************/
756
d8ee398d 757static int
8a63facc 758ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
fa1c114f 759{
8a63facc
BC		 760 struct ath5k_desc *ds;
761 struct ath5k_buf *bf;
762 dma_addr_t da;
763 unsigned int i;
764 int ret;
d8ee398d 765
8a63facc
BC		 766 /* allocate descriptors */
767 sc->desc_len = sizeof(struct ath5k_desc) *
768 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
769 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
770 if (sc->desc == NULL) {
771 ATH5K_ERR(sc, "can't allocate descriptors\n");
772 ret = -ENOMEM;
773 goto err;
774 }
775 ds = sc->desc;
776 da = sc->desc_daddr;
777 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
778 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 779
8a63facc
BC		 780 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
781 sizeof(struct ath5k_buf), GFP_KERNEL);
782 if (bf == NULL) {
783 ATH5K_ERR(sc, "can't allocate bufptr\n");
784 ret = -ENOMEM;
785 goto err_free;
786 }
787 sc->bufptr = bf;
fa1c114f 788
8a63facc
BC		 789 INIT_LIST_HEAD(&sc->rxbuf);
790 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
791 bf->desc = ds;
792 bf->daddr = da;
793 list_add_tail(&bf->list, &sc->rxbuf);
794 }
d8ee398d 795
8a63facc
BC		 796 INIT_LIST_HEAD(&sc->txbuf);
797 sc->txbuf_len = ATH_TXBUF;
798 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
799 da += sizeof(*ds)) {
800 bf->desc = ds;
801 bf->daddr = da;
802 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 803 }
804
8a63facc
BC		 805 /* beacon buffer */
806 bf->desc = ds;
807 bf->daddr = da;
808 sc->bbuf = bf;
fa1c114f 809
8a63facc
BC		 810 return 0;
811err_free:
812 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
813err:
814 sc->desc = NULL;
815 return ret;
816}
fa1c114f 817
8a63facc
BC		 818static void
819ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
820{
821 struct ath5k_buf *bf;
d8ee398d 822
8a63facc
BC		 823 ath5k_txbuf_free_skb(sc, sc->bbuf);
824 list_for_each_entry(bf, &sc->txbuf, list)
825 ath5k_txbuf_free_skb(sc, bf);
826 list_for_each_entry(bf, &sc->rxbuf, list)
827 ath5k_rxbuf_free_skb(sc, bf);
d8ee398d 828
8a63facc
BC		 829 /* Free memory associated with all descriptors */
830 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
831 sc->desc = NULL;
832 sc->desc_daddr = 0;
d8ee398d 833
8a63facc
BC		 834 kfree(sc->bufptr);
835 sc->bufptr = NULL;
836 sc->bbuf = NULL;
fa1c114f
JS		 837}
838
8a63facc
BC		 839
840/**************\
841* Queues setup *
842\**************/
843
844static struct ath5k_txq *
845ath5k_txq_setup(struct ath5k_softc *sc,
846 int qtype, int subtype)
fa1c114f 847{
8a63facc
BC		 848 struct ath5k_hw *ah = sc->ah;
849 struct ath5k_txq *txq;
850 struct ath5k_txq_info qi = {
851 .tqi_subtype = subtype,
852 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
853 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
854 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
855 };
856 int qnum;
d8ee398d 857
e30eb4ab 858 /*
8a63facc
BC		 859 * Enable interrupts only for EOL and DESC conditions.
860 * We mark tx descriptors to receive a DESC interrupt
861 * when a tx queue gets deep; otherwise we wait for the
862 * EOL to reap descriptors. Note that this is done to
863 * reduce interrupt load and this only defers reaping
864 * descriptors, never transmitting frames. Aside from
865 * reducing interrupts this also permits more concurrency.
866 * The only potential downside is if the tx queue backs
867 * up in which case the top half of the kernel may backup
868 * due to a lack of tx descriptors.
e30eb4ab 869 */
8a63facc
BC		 870 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
871 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
872 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
873 if (qnum < 0) {
874 /*
875 * NB: don't print a message, this happens
876 * normally on parts with too few tx queues
877 */
878 return ERR_PTR(qnum);
879 }
880 if (qnum >= ARRAY_SIZE(sc->txqs)) {
881 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
882 qnum, ARRAY_SIZE(sc->txqs));
883 ath5k_hw_release_tx_queue(ah, qnum);
884 return ERR_PTR(-EINVAL);
885 }
886 txq = &sc->txqs[qnum];
887 if (!txq->setup) {
888 txq->qnum = qnum;
889 txq->link = NULL;
890 INIT_LIST_HEAD(&txq->q);
891 spin_lock_init(&txq->lock);
892 txq->setup = true;
925e0b06 893 txq->txq_len = 0;
8a63facc
BC		 894 }
895 return &sc->txqs[qnum];
fa1c114f
JS		 896}
897
8a63facc
BC		 898static int
899ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 900{
8a63facc
BC		 901 struct ath5k_txq_info qi = {
902 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
903 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
904 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
905 /* NB: for dynamic turbo, don't enable any other interrupts */
906 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
907 };
d8ee398d 908
8a63facc 909 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 910}
911
8a63facc
BC		 912static int
913ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 914{
915 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 916 struct ath5k_txq_info qi;
917 int ret;
fa1c114f 918
8a63facc
BC		 919 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
920 if (ret)
921 goto err;
fa1c114f 922
8a63facc
BC		 923 if (sc->opmode == NL80211_IFTYPE_AP ||
924 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
925 /*
926 * Always burst out beacon and CAB traffic
927 * (aifs = cwmin = cwmax = 0)
928 */
929 qi.tqi_aifs = 0;
930 qi.tqi_cw_min = 0;
931 qi.tqi_cw_max = 0;
932 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
933 /*
934 * Adhoc mode; backoff between 0 and (2 * cw_min).
935 */
936 qi.tqi_aifs = 0;
937 qi.tqi_cw_min = 0;
938 qi.tqi_cw_max = 2 * ah->ah_cw_min;
939 }
fa1c114f 940
8a63facc
BC		 941 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
942 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
943 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 944
8a63facc
BC		 945 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
946 if (ret) {
947 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
948 "hardware queue!\n", __func__);
949 goto err;
950 }
951 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
952 if (ret)
953 goto err;
b7266047 954
8a63facc
BC		 955 /* reconfigure cabq with ready time to 80% of beacon_interval */
956 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
957 if (ret)
958 goto err;
b7266047 959
8a63facc
BC		 960 qi.tqi_ready_time = (sc->bintval * 80) / 100;
961 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
962 if (ret)
963 goto err;
b7266047 964
8a63facc
BC		 965 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
966err:
967 return ret;
d8ee398d
LR		 968}
969
8a63facc
BC		 970static void
971ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
972{
973 struct ath5k_buf *bf, *bf0;
b6ea0356
BC		 974
975 /*
8a63facc
BC		 976 * NB: this assumes output has been stopped and
977 * we do not need to block ath5k_tx_tasklet
b6ea0356 978 */
8a63facc
BC		 979 spin_lock_bh(&txq->lock);
980 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
981 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 982
8a63facc 983 ath5k_txbuf_free_skb(sc, bf);
b6ea0356 984
8a63facc
BC		 985 spin_lock_bh(&sc->txbuflock);
986 list_move_tail(&bf->list, &sc->txbuf);
987 sc->txbuf_len++;
925e0b06 988 txq->txq_len--;
8a63facc 989 spin_unlock_bh(&sc->txbuflock);
b6ea0356 990 }
8a63facc
BC		 991 txq->link = NULL;
992 spin_unlock_bh(&txq->lock);
b6ea0356
BC		 993}
994
8a63facc
BC		 995/*
996 * Drain the transmit queues and reclaim resources.
997 */
998static void
999ath5k_txq_cleanup(struct ath5k_softc *sc)
fa1c114f
JS		 1000{
1001 struct ath5k_hw *ah = sc->ah;
8a63facc 1002 unsigned int i;
fa1c114f 1003
8a63facc
BC		 1004 /* XXX return value */
1005 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1006 /* don't touch the hardware if marked invalid */
1007 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1008 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1009 ath5k_hw_get_txdp(ah, sc->bhalq));
1010 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1011 if (sc->txqs[i].setup) {
1012 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1013 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1014 "link %p\n",
1015 sc->txqs[i].qnum,
1016 ath5k_hw_get_txdp(ah,
1017 sc->txqs[i].qnum),
1018 sc->txqs[i].link);
1019 }
0452d4a5 1020 }
fa1c114f 1021
8a63facc
BC		 1022 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1023 if (sc->txqs[i].setup)
1024 ath5k_txq_drainq(sc, &sc->txqs[i]);
fa1c114f
JS		 1025}
1026
8a63facc
BC		 1027static void
1028ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1029{
8a63facc
BC		 1030 struct ath5k_txq *txq = sc->txqs;
1031 unsigned int i;
2ac2927a 1032
8a63facc
BC		 1033 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1034 if (txq->setup) {
1035 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1036 txq->setup = false;
1037 }
1038}
2ac2927a 1039
2ac2927a 1040
8a63facc
BC		 1041/*************\
1042* RX Handling *
1043\*************/
2ac2927a 1044
8a63facc
BC		 1045/*
1046 * Enable the receive h/w following a reset.
1047 */
fa1c114f 1048static int
8a63facc 1049ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1050{
1051 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1052 struct ath_common *common = ath5k_hw_common(ah);
1053 struct ath5k_buf *bf;
1054 int ret;
fa1c114f 1055
8a63facc 1056 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1057
8a63facc
BC		 1058 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1059 common->cachelsz, common->rx_bufsize);
2f7fe870 1060
8a63facc
BC		 1061 spin_lock_bh(&sc->rxbuflock);
1062 sc->rxlink = NULL;
1063 list_for_each_entry(bf, &sc->rxbuf, list) {
1064 ret = ath5k_rxbuf_setup(sc, bf);
1065 if (ret != 0) {
1066 spin_unlock_bh(&sc->rxbuflock);
1067 goto err;
1068 }
2f7fe870 1069 }
8a63facc
BC		 1070 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1071 ath5k_hw_set_rxdp(ah, bf->daddr);
1072 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1073
8a63facc
BC		 1074 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1075 ath5k_mode_setup(sc); /* set filters, etc. */
1076 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1077
1078 return 0;
8a63facc 1079err:
fa1c114f
JS		 1080 return ret;
1081}
1082
8a63facc
BC		 1083/*
1084 * Disable the receive h/w in preparation for a reset.
1085 */
1086static void
1087ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1088{
8a63facc 1089 struct ath5k_hw *ah = sc->ah;
fa1c114f 1090
8a63facc
BC		 1091 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1092 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1093 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f 1094
8a63facc
BC		 1095 ath5k_debug_printrxbuffs(sc, ah);
1096}
fa1c114f 1097
8a63facc
BC		 1098static unsigned int
1099ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1100 struct ath5k_rx_status *rs)
1101{
1102 struct ath5k_hw *ah = sc->ah;
1103 struct ath_common *common = ath5k_hw_common(ah);
1104 struct ieee80211_hdr *hdr = (void *)skb->data;
1105 unsigned int keyix, hlen;
fa1c114f 1106
8a63facc
BC		 1107 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1108 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1109 return RX_FLAG_DECRYPTED;
fa1c114f 1110
8a63facc
BC		 1111 /* Apparently when a default key is used to decrypt the packet
1112 the hw does not set the index used to decrypt. In such cases
1113 get the index from the packet. */
1114 hlen = ieee80211_hdrlen(hdr->frame_control);
1115 if (ieee80211_has_protected(hdr->frame_control) &&
1116 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1117 skb->len >= hlen + 4) {
1118 keyix = skb->data[hlen + 3] >> 6;
1119
1120 if (test_bit(keyix, common->keymap))
1121 return RX_FLAG_DECRYPTED;
1122 }
fa1c114f
JS		 1123
1124 return 0;
fa1c114f
JS		 1125}
1126
8a63facc 1127
fa1c114f 1128static void
8a63facc
BC		 1129ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1130 struct ieee80211_rx_status *rxs)
fa1c114f 1131{
8a63facc
BC		 1132 struct ath_common *common = ath5k_hw_common(sc->ah);
1133 u64 tsf, bc_tstamp;
1134 u32 hw_tu;
1135 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1136
8a63facc
BC		 1137 if (ieee80211_is_beacon(mgmt->frame_control) &&
1138 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1139 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1140 /*
1141 * Received an IBSS beacon with the same BSSID. Hardware *must*
1142 * have updated the local TSF. We have to work around various
1143 * hardware bugs, though...
1144 */
1145 tsf = ath5k_hw_get_tsf64(sc->ah);
1146 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1147 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1148
8a63facc
BC		 1149 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1150 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1151 (unsigned long long)bc_tstamp,
1152 (unsigned long long)rxs->mactime,
1153 (unsigned long long)(rxs->mactime - bc_tstamp),
1154 (unsigned long long)tsf);
fa1c114f 1155
8a63facc
BC		 1156 /*
1157 * Sometimes the HW will give us a wrong tstamp in the rx
1158 * status, causing the timestamp extension to go wrong.
1159 * (This seems to happen especially with beacon frames bigger
1160 * than 78 byte (incl. FCS))
1161 * But we know that the receive timestamp must be later than the
1162 * timestamp of the beacon since HW must have synced to that.
1163 *
1164 * NOTE: here we assume mactime to be after the frame was
1165 * received, not like mac80211 which defines it at the start.
1166 */
1167 if (bc_tstamp > rxs->mactime) {
1168 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1169 "fixing mactime from %llx to %llx\n",
1170 (unsigned long long)rxs->mactime,
1171 (unsigned long long)tsf);
1172 rxs->mactime = tsf;
1173 }
fa1c114f 1174
8a63facc
BC		 1175 /*
1176 * Local TSF might have moved higher than our beacon timers,
1177 * in that case we have to update them to continue sending
1178 * beacons. This also takes care of synchronizing beacon sending
1179 * times with other stations.
1180 */
1181 if (hw_tu >= sc->nexttbtt)
1182 ath5k_beacon_update_timers(sc, bc_tstamp);
1183 }
1184}
fa1c114f 1185
8a63facc
BC		 1186static void
1187ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1188{
1189 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1190 struct ath5k_hw *ah = sc->ah;
1191 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1192
8a63facc
BC		 1193 /* only beacons from our BSSID */
1194 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1195 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1196 return;
fa1c114f 1197
8a63facc
BC		 1198 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1199 rssi);
fa1c114f 1200
8a63facc
BC		 1201 /* in IBSS mode we should keep RSSI statistics per neighbour */
1202 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1203}
fa1c114f 1204
8a63facc
BC		 1205/*
1206 * Compute padding position. skb must contain an IEEE 802.11 frame
1207 */
1208static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1209{
8a63facc
BC		 1210 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1211 __le16 frame_control = hdr->frame_control;
1212 int padpos = 24;
fa1c114f 1213
8a63facc
BC		 1214 if (ieee80211_has_a4(frame_control)) {
1215 padpos += ETH_ALEN;
fa1c114f 1216 }
8a63facc
BC		 1217 if (ieee80211_is_data_qos(frame_control)) {
1218 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1219 }
8a63facc
BC		 1220
1221 return padpos;
fa1c114f
JS		 1222}
1223
8a63facc
BC		 1224/*
1225 * This function expects an 802.11 frame and returns the number of
1226 * bytes added, or -1 if we don't have enough header room.
1227 */
1228static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1229{
8a63facc
BC		 1230 int padpos = ath5k_common_padpos(skb);
1231 int padsize = padpos & 3;
fa1c114f 1232
8a63facc 1233 if (padsize && skb->len>padpos) {
fa1c114f 1234
8a63facc
BC		 1235 if (skb_headroom(skb) < padsize)
1236 return -1;
fa1c114f 1237
8a63facc
BC		 1238 skb_push(skb, padsize);
1239 memmove(skb->data, skb->data+padsize, padpos);
1240 return padsize;
1241 }
a951ae21 1242
8a63facc
BC		 1243 return 0;
1244}
fa1c114f 1245
8a63facc
BC		 1246/*
1247 * The MAC header is padded to have 32-bit boundary if the
1248 * packet payload is non-zero. The general calculation for
1249 * padsize would take into account odd header lengths:
1250 * padsize = 4 - (hdrlen & 3); however, since only
1251 * even-length headers are used, padding can only be 0 or 2
1252 * bytes and we can optimize this a bit. We must not try to
1253 * remove padding from short control frames that do not have a
1254 * payload.
1255 *
1256 * This function expects an 802.11 frame and returns the number of
1257 * bytes removed.
1258 */
1259static int ath5k_remove_padding(struct sk_buff *skb)
1260{
1261 int padpos = ath5k_common_padpos(skb);
1262 int padsize = padpos & 3;
6d91e1d8 1263
8a63facc
BC		 1264 if (padsize && skb->len>=padpos+padsize) {
1265 memmove(skb->data + padsize, skb->data, padpos);
1266 skb_pull(skb, padsize);
1267 return padsize;
fa1c114f 1268 }
a951ae21 1269
8a63facc 1270 return 0;
fa1c114f
JS		 1271}
1272
1273static void
8a63facc
BC		 1274ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1275 struct ath5k_rx_status *rs)
fa1c114f 1276{
8a63facc
BC		 1277 struct ieee80211_rx_status *rxs;
1278
1279 ath5k_remove_padding(skb);
1280
1281 rxs = IEEE80211_SKB_RXCB(skb);
1282
1283 rxs->flag = 0;
1284 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1285 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1286
1287 /*
8a63facc
BC		 1288 * always extend the mac timestamp, since this information is
1289 * also needed for proper IBSS merging.
1290 *
1291 * XXX: it might be too late to do it here, since rs_tstamp is
1292 * 15bit only. that means TSF extension has to be done within
1293 * 32768usec (about 32ms). it might be necessary to move this to
1294 * the interrupt handler, like it is done in madwifi.
1295 *
1296 * Unfortunately we don't know when the hardware takes the rx
1297 * timestamp (beginning of phy frame, data frame, end of rx?).
1298 * The only thing we know is that it is hardware specific...
1299 * On AR5213 it seems the rx timestamp is at the end of the
1300 * frame, but i'm not sure.
1301 *
1302 * NOTE: mac80211 defines mactime at the beginning of the first
1303 * data symbol. Since we don't have any time references it's
1304 * impossible to comply to that. This affects IBSS merge only
1305 * right now, so it's not too bad...
fa1c114f 1306 */
8a63facc
BC		 1307 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1308 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1309
8a63facc
BC		 1310 rxs->freq = sc->curchan->center_freq;
1311 rxs->band = sc->curband->band;
fa1c114f 1312
8a63facc 1313 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1314
8a63facc 1315 rxs->antenna = rs->rs_antenna;
fa1c114f 1316
8a63facc
BC		 1317 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1318 sc->stats.antenna_rx[rs->rs_antenna]++;
1319 else
1320 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1321
8a63facc
BC		 1322 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1323 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1324
8a63facc
BC		 1325 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1326 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1327 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1328
8a63facc 1329 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1330
8a63facc 1331 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1332
8a63facc
BC		 1333 /* check beacons in IBSS mode */
1334 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1335 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1336
8a63facc
BC		 1337 ieee80211_rx(sc->hw, skb);
1338}
fa1c114f 1339
8a63facc
BC		 1340/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1341 *
1342 * Check if we want to further process this frame or not. Also update
1343 * statistics. Return true if we want this frame, false if not.
fa1c114f 1344 */
8a63facc
BC		 1345static bool
1346ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1347{
8a63facc 1348 sc->stats.rx_all_count++;
fa1c114f 1349
8a63facc
BC		 1350 if (unlikely(rs->rs_status)) {
1351 if (rs->rs_status & AR5K_RXERR_CRC)
1352 sc->stats.rxerr_crc++;
1353 if (rs->rs_status & AR5K_RXERR_FIFO)
1354 sc->stats.rxerr_fifo++;
1355 if (rs->rs_status & AR5K_RXERR_PHY) {
1356 sc->stats.rxerr_phy++;
1357 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1358 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1359 return false;
1360 }
1361 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1362 /*
1363 * Decrypt error. If the error occurred
1364 * because there was no hardware key, then
1365 * let the frame through so the upper layers
1366 * can process it. This is necessary for 5210
1367 * parts which have no way to setup a ``clear''
1368 * key cache entry.
1369 *
1370 * XXX do key cache faulting
1371 */
1372 sc->stats.rxerr_decrypt++;
1373 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1374 !(rs->rs_status & AR5K_RXERR_CRC))
1375 return true;
1376 }
1377 if (rs->rs_status & AR5K_RXERR_MIC) {
1378 sc->stats.rxerr_mic++;
1379 return true;
fa1c114f 1380 }
fa1c114f 1381
8a63facc
BC		 1382 /* reject any frames with non-crypto errors */
1383 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1384 return false;
1385 }
fa1c114f 1386
8a63facc
BC		 1387 if (unlikely(rs->rs_more)) {
1388 sc->stats.rxerr_jumbo++;
1389 return false;
1390 }
1391 return true;
fa1c114f
JS		 1392}
1393
fa1c114f 1394static void
8a63facc 1395ath5k_tasklet_rx(unsigned long data)
fa1c114f 1396{
8a63facc
BC		 1397 struct ath5k_rx_status rs = {};
1398 struct sk_buff *skb, *next_skb;
1399 dma_addr_t next_skb_addr;
1400 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1401 struct ath5k_hw *ah = sc->ah;
1402 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1403 struct ath5k_buf *bf;
1404 struct ath5k_desc *ds;
1405 int ret;
fa1c114f 1406
8a63facc
BC		 1407 spin_lock(&sc->rxbuflock);
1408 if (list_empty(&sc->rxbuf)) {
1409 ATH5K_WARN(sc, "empty rx buf pool\n");
1410 goto unlock;
1411 }
1412 do {
1413 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1414 BUG_ON(bf->skb == NULL);
1415 skb = bf->skb;
1416 ds = bf->desc;
fa1c114f 1417
8a63facc
BC		 1418 /* bail if HW is still using self-linked descriptor */
1419 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1420 break;
fa1c114f 1421
8a63facc
BC		 1422 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1423 if (unlikely(ret == -EINPROGRESS))
1424 break;
1425 else if (unlikely(ret)) {
1426 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1427 sc->stats.rxerr_proc++;
1428 break;
1429 }
fa1c114f 1430
8a63facc
BC		 1431 if (ath5k_receive_frame_ok(sc, &rs)) {
1432 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1433
8a63facc
BC		 1434 /*
1435 * If we can't replace bf->skb with a new skb under
1436 * memory pressure, just skip this packet
1437 */
1438 if (!next_skb)
1439 goto next;
036cd1ec 1440
8a63facc
BC		 1441 pci_unmap_single(sc->pdev, bf->skbaddr,
1442 common->rx_bufsize,
1443 PCI_DMA_FROMDEVICE);
036cd1ec 1444
8a63facc 1445 skb_put(skb, rs.rs_datalen);
6ba81c2c 1446
8a63facc 1447 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1448
8a63facc
BC		 1449 bf->skb = next_skb;
1450 bf->skbaddr = next_skb_addr;
036cd1ec 1451 }
8a63facc
BC		 1452next:
1453 list_move_tail(&bf->list, &sc->rxbuf);
1454 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1455unlock:
1456 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1457}
1458
b4ea449d 1459
8a63facc
BC		 1460/*************\
1461* TX Handling *
1462\*************/
b4ea449d 1463
8a63facc
BC		 1464static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1465 struct ath5k_txq *txq)
1466{
1467 struct ath5k_softc *sc = hw->priv;
1468 struct ath5k_buf *bf;
1469 unsigned long flags;
1470 int padsize;
b4ea449d 1471
8a63facc 1472 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
b4ea449d 1473
8a63facc
BC		 1474 /*
1475 * The hardware expects the header padded to 4 byte boundaries.
1476 * If this is not the case, we add the padding after the header.
1477 */
1478 padsize = ath5k_add_padding(skb);
1479 if (padsize < 0) {
1480 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1481 " headroom to pad");
1482 goto drop_packet;
1483 }
8127fbdc 1484
925e0b06
BR		 1485 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1486 ieee80211_stop_queue(hw, txq->qnum);
1487
8a63facc
BC		 1488 spin_lock_irqsave(&sc->txbuflock, flags);
1489 if (list_empty(&sc->txbuf)) {
1490 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1491 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1492 ieee80211_stop_queues(hw);
8a63facc 1493 goto drop_packet;
8127fbdc 1494 }
8a63facc
BC		 1495 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1496 list_del(&bf->list);
1497 sc->txbuf_len--;
1498 if (list_empty(&sc->txbuf))
1499 ieee80211_stop_queues(hw);
1500 spin_unlock_irqrestore(&sc->txbuflock, flags);
1501
1502 bf->skb = skb;
1503
1504 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1505 bf->skb = NULL;
1506 spin_lock_irqsave(&sc->txbuflock, flags);
1507 list_add_tail(&bf->list, &sc->txbuf);
1508 sc->txbuf_len++;
1509 spin_unlock_irqrestore(&sc->txbuflock, flags);
1510 goto drop_packet;
8127fbdc 1511 }
8a63facc 1512 return NETDEV_TX_OK;
8127fbdc 1513
8a63facc
BC		 1514drop_packet:
1515 dev_kfree_skb_any(skb);
1516 return NETDEV_TX_OK;
8127fbdc
BP		 1517}
1518
1440401e
BR		 1519static void
1520ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1521 struct ath5k_tx_status *ts)
1522{
1523 struct ieee80211_tx_info *info;
1524 int i;
1525
1526 sc->stats.tx_all_count++;
1527 info = IEEE80211_SKB_CB(skb);
1528
1529 ieee80211_tx_info_clear_status(info);
1530 for (i = 0; i < 4; i++) {
1531 struct ieee80211_tx_rate *r =
1532 &info->status.rates[i];
1533
1534 if (ts->ts_rate[i]) {
1535 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1536 r->count = ts->ts_retry[i];
1537 } else {
1538 r->idx = -1;
1539 r->count = 0;
1540 }
1541 }
1542
1543 /* count the successful attempt as well */
1544 info->status.rates[ts->ts_final_idx].count++;
1545
1546 if (unlikely(ts->ts_status)) {
1547 sc->stats.ack_fail++;
1548 if (ts->ts_status & AR5K_TXERR_FILT) {
1549 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1550 sc->stats.txerr_filt++;
1551 }
1552 if (ts->ts_status & AR5K_TXERR_XRETRY)
1553 sc->stats.txerr_retry++;
1554 if (ts->ts_status & AR5K_TXERR_FIFO)
1555 sc->stats.txerr_fifo++;
1556 } else {
1557 info->flags |= IEEE80211_TX_STAT_ACK;
1558 info->status.ack_signal = ts->ts_rssi;
1559 }
1560
1561 /*
1562 * Remove MAC header padding before giving the frame
1563 * back to mac80211.
1564 */
1565 ath5k_remove_padding(skb);
1566
1567 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1568 sc->stats.antenna_tx[ts->ts_antenna]++;
1569 else
1570 sc->stats.antenna_tx[0]++; /* invalid */
1571
1572 ieee80211_tx_status(sc->hw, skb);
1573}
8a63facc
BC		 1574
1575static void
1576ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1577{
8a63facc
BC		 1578 struct ath5k_tx_status ts = {};
1579 struct ath5k_buf *bf, *bf0;
1580 struct ath5k_desc *ds;
1581 struct sk_buff *skb;
1440401e 1582 int ret;
8127fbdc 1583
8a63facc
BC		 1584 spin_lock(&txq->lock);
1585 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1586 ds = bf->desc;
8127fbdc 1587
8a63facc
BC		 1588 /*
1589 * It's possible that the hardware can say the buffer is
1590 * completed when it hasn't yet loaded the ds_link from
1591 * host memory and moved on. If there are more TX
1592 * descriptors in the queue, wait for TXDP to change
1593 * before processing this one.
1594 */
1595 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
1596 !list_is_last(&bf->list, &txq->q))
1597 break;
8a63facc
BC		 1598 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1599 if (unlikely(ret == -EINPROGRESS))
1600 break;
1601 else if (unlikely(ret)) {
1602 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1603 ret, txq->qnum);
1604 break;
1605 }
8127fbdc 1606
8a63facc 1607 skb = bf->skb;
8a63facc 1608 bf->skb = NULL;
fa1c114f
JS		 1609 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1610 PCI_DMA_TODEVICE);
1611
1440401e 1612 ath5k_tx_frame_completed(sc, skb, &ts);
fa1c114f
JS		 1613
1614 spin_lock(&sc->txbuflock);
fa1c114f
JS		 1615 list_move_tail(&bf->list, &sc->txbuf);
1616 sc->txbuf_len++;
925e0b06 1617 txq->txq_len--;
fa1c114f
JS		 1618 spin_unlock(&sc->txbuflock);
1619 }
1620 if (likely(list_empty(&txq->q)))
1621 txq->link = NULL;
1622 spin_unlock(&txq->lock);
925e0b06
BR		 1623 if (txq->txq_len < ATH5K_TXQ_LEN_LOW)
1624 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1625}
1626
1627static void
1628ath5k_tasklet_tx(unsigned long data)
1629{
8784d2ee 1630 int i;
fa1c114f
JS		 1631 struct ath5k_softc *sc = (void *)data;
1632
8784d2ee
BC		 1633 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1634 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1635 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1636}
1637
1638
fa1c114f
JS		 1639/*****************\
1640* Beacon handling *
1641\*****************/
1642
1643/*
1644 * Setup the beacon frame for transmit.
1645 */
1646static int
e039fa4a 1647ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1648{
1649 struct sk_buff *skb = bf->skb;
a888d52d 1650 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1651 struct ath5k_hw *ah = sc->ah;
1652 struct ath5k_desc *ds;
2bed03eb
NK		 1653 int ret = 0;
1654 u8 antenna;
fa1c114f 1655 u32 flags;
8127fbdc 1656 const int padsize = 0;
fa1c114f
JS		 1657
1658 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1659 PCI_DMA_TODEVICE);
1660 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1661 "skbaddr %llx\n", skb, skb->data, skb->len,
1662 (unsigned long long)bf->skbaddr);
8d8bb39b 1663 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1664 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1665 return -EIO;
1666 }
1667
1668 ds = bf->desc;
2bed03eb 1669 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1670
1671 flags = AR5K_TXDESC_NOACK;
05c914fe 1672 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1673 ds->ds_link = bf->daddr; /* self-linked */
1674 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1675 } else
fa1c114f 1676 ds->ds_link = 0;
2bed03eb
NK		 1677
1678 /*
1679 * If we use multiple antennas on AP and use
1680 * the Sectored AP scenario, switch antenna every
1681 * 4 beacons to make sure everybody hears our AP.
1682 * When a client tries to associate, hw will keep
1683 * track of the tx antenna to be used for this client
1684 * automaticaly, based on ACKed packets.
1685 *
1686 * Note: AP still listens and transmits RTS on the
1687 * default antenna which is supposed to be an omni.
1688 *
1689 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1690 * multiple antennas (1 omni -- the default -- and 14
1691 * sectors), so if we choose to actually support this
1692 * mode, we need to allow the user to set how many antennas
1693 * we have and tweak the code below to send beacons
1694 * on all of them.
2bed03eb
NK		 1695 */
1696 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1697 antenna = sc->bsent & 4 ? 2 : 1;
1698
fa1c114f 1699
8f655dde
NK		 1700 /* FIXME: If we are in g mode and rate is a CCK rate
1701 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1702 * from tx power (value is in dB units already) */
fa1c114f 1703 ds->ds_data = bf->skbaddr;
281c56dd 1704 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1705 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1706 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1707 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1708 1, AR5K_TXKEYIX_INVALID,
400ec45a 1709 antenna, flags, 0, 0);
fa1c114f
JS		 1710 if (ret)
1711 goto err_unmap;
1712
1713 return 0;
1714err_unmap:
1715 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1716 return ret;
1717}
1718
8a63facc
BC		 1719/*
1720 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1721 * this is called only once at config_bss time, for AP we do it every
1722 * SWBA interrupt so that the TIM will reflect buffered frames.
1723 *
1724 * Called with the beacon lock.
1725 */
1726static int
1727ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1728{
1729 int ret;
1730 struct ath5k_softc *sc = hw->priv;
1731 struct sk_buff *skb;
1732
1733 if (WARN_ON(!vif)) {
1734 ret = -EINVAL;
1735 goto out;
1736 }
1737
1738 skb = ieee80211_beacon_get(hw, vif);
1739
1740 if (!skb) {
1741 ret = -ENOMEM;
1742 goto out;
1743 }
1744
1745 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1746
1747 ath5k_txbuf_free_skb(sc, sc->bbuf);
1748 sc->bbuf->skb = skb;
1749 ret = ath5k_beacon_setup(sc, sc->bbuf);
1750 if (ret)
1751 sc->bbuf->skb = NULL;
1752out:
1753 return ret;
1754}
1755
fa1c114f
JS		 1756/*
1757 * Transmit a beacon frame at SWBA. Dynamic updates to the
1758 * frame contents are done as needed and the slot time is
1759 * also adjusted based on current state.
1760 *
5faaff74
BC		 1761 * This is called from software irq context (beacontq tasklets)
1762 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1763 */
1764static void
1765ath5k_beacon_send(struct ath5k_softc *sc)
1766{
1767 struct ath5k_buf *bf = sc->bbuf;
1768 struct ath5k_hw *ah = sc->ah;
cec8db23 1769 struct sk_buff *skb;
fa1c114f 1770
be9b7259 1771 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1772
4afd89d9 1773 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION)) {
fa1c114f
JS		 1774 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1775 return;
1776 }
1777 /*
1778 * Check if the previous beacon has gone out. If
a180a130 1779 * not, don't don't try to post another: skip this
fa1c114f
JS		 1780 * period and wait for the next. Missed beacons
1781 * indicate a problem and should not occur. If we
1782 * miss too many consecutive beacons reset the device.
1783 */
1784 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1785 sc->bmisscount++;
be9b7259 1786 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1787 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1788 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1789 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1790 "stuck beacon time (%u missed)\n",
1791 sc->bmisscount);
8d67a031
BR		 1792 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1793 "stuck beacon, resetting\n");
5faaff74 1794 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1795 }
1796 return;
1797 }
1798 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1799 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1800 "resume beacon xmit after %u misses\n",
1801 sc->bmisscount);
1802 sc->bmisscount = 0;
1803 }
1804
1805 /*
1806 * Stop any current dma and put the new frame on the queue.
1807 * This should never fail since we check above that no frames
1808 * are still pending on the queue.
1809 */
1810 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 1811 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1812 /* NB: hw still stops DMA, so proceed */
1813 }
fa1c114f 1814
1071db86
BC		 1815 /* refresh the beacon for AP mode */
1816 if (sc->opmode == NL80211_IFTYPE_AP)
1817 ath5k_beacon_update(sc->hw, sc->vif);
1818
c6e387a2
NK		 1819 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1820 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1821 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1822 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1823
cec8db23
BC		 1824 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
1825 while (skb) {
1826 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1827 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
1828 }
1829
fa1c114f
JS		 1830 sc->bsent++;
1831}
1832
9804b98d
BR		 1833/**
1834 * ath5k_beacon_update_timers - update beacon timers
1835 *
1836 * @sc: struct ath5k_softc pointer we are operating on
1837 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1838 * beacon timer update based on the current HW TSF.
1839 *
1840 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1841 * of a received beacon or the current local hardware TSF and write it to the
1842 * beacon timer registers.
1843 *
1844 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1845 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1846 * when we otherwise know we have to update the timers, but we keep it in this
1847 * function to have it all together in one place.
1848 */
fa1c114f 1849static void
9804b98d 1850ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1851{
1852 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1853 u32 nexttbtt, intval, hw_tu, bc_tu;
1854 u64 hw_tsf;
fa1c114f
JS		 1855
1856 intval = sc->bintval & AR5K_BEACON_PERIOD;
1857 if (WARN_ON(!intval))
1858 return;
1859
9804b98d
BR		 1860 /* beacon TSF converted to TU */
1861 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1862
9804b98d
BR		 1863 /* current TSF converted to TU */
1864 hw_tsf = ath5k_hw_get_tsf64(ah);
1865 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1866
9804b98d
BR		 1867#define FUDGE 3
1868 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
1869 if (bc_tsf == -1) {
1870 /*
1871 * no beacons received, called internally.
1872 * just need to refresh timers based on HW TSF.
1873 */
1874 nexttbtt = roundup(hw_tu + FUDGE, intval);
1875 } else if (bc_tsf == 0) {
1876 /*
1877 * no beacon received, probably called by ath5k_reset_tsf().
1878 * reset TSF to start with 0.
1879 */
1880 nexttbtt = intval;
1881 intval |= AR5K_BEACON_RESET_TSF;
1882 } else if (bc_tsf > hw_tsf) {
1883 /*
1884 * beacon received, SW merge happend but HW TSF not yet updated.
1885 * not possible to reconfigure timers yet, but next time we
1886 * receive a beacon with the same BSSID, the hardware will
1887 * automatically update the TSF and then we need to reconfigure
1888 * the timers.
1889 */
1890 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1891 "need to wait for HW TSF sync\n");
1892 return;
1893 } else {
1894 /*
1895 * most important case for beacon synchronization between STA.
1896 *
1897 * beacon received and HW TSF has been already updated by HW.
1898 * update next TBTT based on the TSF of the beacon, but make
1899 * sure it is ahead of our local TSF timer.
1900 */
1901 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
1902 }
1903#undef FUDGE
fa1c114f 1904
036cd1ec
BR		 1905 sc->nexttbtt = nexttbtt;
1906
fa1c114f 1907 intval |= AR5K_BEACON_ENA;
fa1c114f 1908 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 1909
1910 /*
1911 * debugging output last in order to preserve the time critical aspect
1912 * of this function
1913 */
1914 if (bc_tsf == -1)
1915 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1916 "reconfigured timers based on HW TSF\n");
1917 else if (bc_tsf == 0)
1918 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1919 "reset HW TSF and timers\n");
1920 else
1921 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1922 "updated timers based on beacon TSF\n");
1923
1924 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 1925 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
1926 (unsigned long long) bc_tsf,
1927 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 1928 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
1929 intval & AR5K_BEACON_PERIOD,
1930 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
1931 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 1932}
1933
036cd1ec
BR		 1934/**
1935 * ath5k_beacon_config - Configure the beacon queues and interrupts
1936 *
1937 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 1938 *
036cd1ec 1939 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 1940 * interrupts to detect TSF updates only.
fa1c114f
JS		 1941 */
1942static void
1943ath5k_beacon_config(struct ath5k_softc *sc)
1944{
1945 struct ath5k_hw *ah = sc->ah;
b5f03956 1946 unsigned long flags;
fa1c114f 1947
21800491 1948 spin_lock_irqsave(&sc->block, flags);
fa1c114f 1949 sc->bmisscount = 0;
dc1968e7 1950 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 1951
21800491 1952 if (sc->enable_beacon) {
fa1c114f 1953 /*
036cd1ec
BR		 1954 * In IBSS mode we use a self-linked tx descriptor and let the
1955 * hardware send the beacons automatically. We have to load it
fa1c114f 1956 * only once here.
036cd1ec 1957 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 1958 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 1959 */
1960 ath5k_beaconq_config(sc);
fa1c114f 1961
036cd1ec
BR		 1962 sc->imask |= AR5K_INT_SWBA;
1963
da966bca 1964 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 1965 if (ath5k_hw_hasveol(ah))
da966bca 1966 ath5k_beacon_send(sc);
da966bca
JS		 1967 } else
1968 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 1969 } else {
1970 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 1971 }
fa1c114f 1972
c6e387a2 1973 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 1974 mmiowb();
1975 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 1976}
1977
428cbd4f
NK		 1978static void ath5k_tasklet_beacon(unsigned long data)
1979{
1980 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1981
1982 /*
1983 * Software beacon alert--time to send a beacon.
1984 *
1985 * In IBSS mode we use this interrupt just to
1986 * keep track of the next TBTT (target beacon
1987 * transmission time) in order to detect wether
1988 * automatic TSF updates happened.
1989 */
1990 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1991 /* XXX: only if VEOL suppported */
1992 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1993 sc->nexttbtt += sc->bintval;
1994 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1995 "SWBA nexttbtt: %x hw_tu: %x "
1996 "TSF: %llx\n",
1997 sc->nexttbtt,
1998 TSF_TO_TU(tsf),
1999 (unsigned long long) tsf);
2000 } else {
2001 spin_lock(&sc->block);
2002 ath5k_beacon_send(sc);
2003 spin_unlock(&sc->block);
2004 }
2005}
2006
fa1c114f
JS		 2007
2008/********************\
2009* Interrupt handling *
2010\********************/
2011
6a8a3f6b
BR		 2012static void
2013ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2014{
2111ac0d
BR		 2015 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2016 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2017 /* run ANI only when full calibration is not active */
2018 ah->ah_cal_next_ani = jiffies +
2019 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2020 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2021
2022 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2023 ah->ah_cal_next_full = jiffies +
2024 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2025 tasklet_schedule(&ah->ah_sc->calib);
2026 }
2027 /* we could use SWI to generate enough interrupts to meet our
2028 * calibration interval requirements, if necessary:
2029 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2030}
2031
fa1c114f
JS		 2032static irqreturn_t
2033ath5k_intr(int irq, void *dev_id)
2034{
2035 struct ath5k_softc *sc = dev_id;
2036 struct ath5k_hw *ah = sc->ah;
2037 enum ath5k_int status;
2038 unsigned int counter = 1000;
2039
2040 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2041 !ath5k_hw_is_intr_pending(ah)))
2042 return IRQ_NONE;
2043
2044 do {
fa1c114f
JS		 2045 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2046 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2047 status, sc->imask);
fa1c114f
JS		 2048 if (unlikely(status & AR5K_INT_FATAL)) {
2049 /*
2050 * Fatal errors are unrecoverable.
2051 * Typically these are caused by DMA errors.
2052 */
8d67a031
BR		 2053 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2054 "fatal int, resetting\n");
5faaff74 2055 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2056 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2057 /*
2058 * Receive buffers are full. Either the bus is busy or
2059 * the CPU is not fast enough to process all received
2060 * frames.
2061 * Older chipsets need a reset to come out of this
2062 * condition, but we treat it as RX for newer chips.
2063 * We don't know exactly which versions need a reset -
2064 * this guess is copied from the HAL.
2065 */
2066 sc->stats.rxorn_intr++;
8d67a031
BR		 2067 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2068 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2069 "rx overrun, resetting\n");
5faaff74 2070 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2071 }
87d77c4e
BR		 2072 else
2073 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2074 } else {
2075 if (status & AR5K_INT_SWBA) {
56d2ac76 2076 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2077 }
2078 if (status & AR5K_INT_RXEOL) {
2079 /*
2080 * NB: the hardware should re-read the link when
2081 * RXE bit is written, but it doesn't work at
2082 * least on older hardware revs.
2083 */
b3f194e5 2084 sc->stats.rxeol_intr++;
fa1c114f
JS		 2085 }
2086 if (status & AR5K_INT_TXURN) {
2087 /* bump tx trigger level */
2088 ath5k_hw_update_tx_triglevel(ah, true);
2089 }
4c674c60 2090 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2091 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2092 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2093 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2094 tasklet_schedule(&sc->txtq);
2095 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2096 /* TODO */
fa1c114f
JS		 2097 }
2098 if (status & AR5K_INT_MIB) {
2111ac0d 2099 sc->stats.mib_intr++;
495391d7 2100 ath5k_hw_update_mib_counters(ah);
2111ac0d 2101 ath5k_ani_mib_intr(ah);
fa1c114f 2102 }
e6a3b616 2103 if (status & AR5K_INT_GPIO)
e6a3b616 2104 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2105
fa1c114f 2106 }
2516baa6 2107 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2108
2109 if (unlikely(!counter))
2110 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2111
6a8a3f6b 2112 ath5k_intr_calibration_poll(ah);
6e220662 2113
fa1c114f
JS		 2114 return IRQ_HANDLED;
2115}
2116
fa1c114f
JS		 2117/*
2118 * Periodically recalibrate the PHY to account
2119 * for temperature/environment changes.
2120 */
2121static void
6e220662 2122ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2123{
2124 struct ath5k_softc *sc = (void *)data;
2125 struct ath5k_hw *ah = sc->ah;
2126
6e220662 2127 /* Only full calibration for now */
e65e1d77 2128 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2129
fa1c114f 2130 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2131 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2132 sc->curchan->hw_value);
fa1c114f 2133
6f3b414a 2134 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2135 /*
2136 * Rfgain is out of bounds, reset the chip
2137 * to load new gain values.
2138 */
2139 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2140 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2141 }
2142 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2143 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2144 ieee80211_frequency_to_channel(
2145 sc->curchan->center_freq));
fa1c114f 2146
0e8e02dd 2147 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2148 * doesn't.
2149 * TODO: We should stop TX here, so that it doesn't interfere.
2150 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2151 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2152 ah->ah_cal_next_nf = jiffies +
2153 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2154 ath5k_hw_update_noise_floor(ah);
afe86286 2155 }
6e220662 2156
e65e1d77 2157 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2158}
2159
2160
2111ac0d
BR		 2161static void
2162ath5k_tasklet_ani(unsigned long data)
2163{
2164 struct ath5k_softc *sc = (void *)data;
2165 struct ath5k_hw *ah = sc->ah;
2166
2167 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2168 ath5k_ani_calibration(ah);
2169 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2170}
2171
2172
8a63facc
BC		 2173/*************************\
2174* Initialization routines *
2175\*************************/
fa1c114f
JS		 2176
2177static int
8a63facc 2178ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2179{
8a63facc 2180 struct ath5k_hw *ah = sc->ah;
cec8db23 2181
8a63facc
BC		 2182 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2183 test_bit(ATH_STAT_INVALID, sc->status));
2184
2185 /*
2186 * Shutdown the hardware and driver:
2187 * stop output from above
2188 * disable interrupts
2189 * turn off timers
2190 * turn off the radio
2191 * clear transmit machinery
2192 * clear receive machinery
2193 * drain and release tx queues
2194 * reclaim beacon resources
2195 * power down hardware
2196 *
2197 * Note that some of this work is not possible if the
2198 * hardware is gone (invalid).
2199 */
2200 ieee80211_stop_queues(sc->hw);
2201
2202 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2203 ath5k_led_off(sc);
2204 ath5k_hw_set_imr(ah, 0);
2205 synchronize_irq(sc->pdev->irq);
2206 }
2207 ath5k_txq_cleanup(sc);
2208 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2209 ath5k_rx_stop(sc);
2210 ath5k_hw_phy_disable(ah);
2211 }
2212
2213 return 0;
cec8db23
BC		 2214}
2215
8a63facc
BC		 2216static int
2217ath5k_init(struct ath5k_softc *sc)
fa1c114f 2218{
8a63facc
BC		 2219 struct ath5k_hw *ah = sc->ah;
2220 struct ath_common *common = ath5k_hw_common(ah);
2221 int ret, i;
fa1c114f 2222
8a63facc
BC		 2223 mutex_lock(&sc->lock);
2224
2225 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2226
fa1c114f 2227 /*
8a63facc
BC		 2228 * Stop anything previously setup. This is safe
2229 * no matter this is the first time through or not.
fa1c114f 2230 */
8a63facc 2231 ath5k_stop_locked(sc);
fa1c114f 2232
8a63facc
BC		 2233 /*
2234 * The basic interface to setting the hardware in a good
2235 * state is ``reset''. On return the hardware is known to
2236 * be powered up and with interrupts disabled. This must
2237 * be followed by initialization of the appropriate bits
2238 * and then setup of the interrupt mask.
2239 */
2240 sc->curchan = sc->hw->conf.channel;
2241 sc->curband = &sc->sbands[sc->curchan->band];
2242 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2243 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2244 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2245
8a63facc
BC		 2246 ret = ath5k_reset(sc, NULL);
2247 if (ret)
2248 goto done;
fa1c114f 2249
8a63facc
BC		 2250 ath5k_rfkill_hw_start(ah);
2251
2252 /*
2253 * Reset the key cache since some parts do not reset the
2254 * contents on initial power up or resume from suspend.
2255 */
2256 for (i = 0; i < common->keymax; i++)
2257 ath_hw_keyreset(common, (u16) i);
2258
2259 ath5k_hw_set_ack_bitrate_high(ah, true);
2260 ret = 0;
2261done:
2262 mmiowb();
2263 mutex_unlock(&sc->lock);
2264 return ret;
2265}
2266
2267static void stop_tasklets(struct ath5k_softc *sc)
2268{
2269 tasklet_kill(&sc->rxtq);
2270 tasklet_kill(&sc->txtq);
2271 tasklet_kill(&sc->calib);
2272 tasklet_kill(&sc->beacontq);
2273 tasklet_kill(&sc->ani_tasklet);
2274}
2275
2276/*
2277 * Stop the device, grabbing the top-level lock to protect
2278 * against concurrent entry through ath5k_init (which can happen
2279 * if another thread does a system call and the thread doing the
2280 * stop is preempted).
2281 */
2282static int
2283ath5k_stop_hw(struct ath5k_softc *sc)
2284{
2285 int ret;
2286
2287 mutex_lock(&sc->lock);
2288 ret = ath5k_stop_locked(sc);
2289 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2290 /*
2291 * Don't set the card in full sleep mode!
2292 *
2293 * a) When the device is in this state it must be carefully
2294 * woken up or references to registers in the PCI clock
2295 * domain may freeze the bus (and system). This varies
2296 * by chip and is mostly an issue with newer parts
2297 * (madwifi sources mentioned srev >= 0x78) that go to
2298 * sleep more quickly.
2299 *
2300 * b) On older chips full sleep results a weird behaviour
2301 * during wakeup. I tested various cards with srev < 0x78
2302 * and they don't wake up after module reload, a second
2303 * module reload is needed to bring the card up again.
2304 *
2305 * Until we figure out what's going on don't enable
2306 * full chip reset on any chip (this is what Legacy HAL
2307 * and Sam's HAL do anyway). Instead Perform a full reset
2308 * on the device (same as initial state after attach) and
2309 * leave it idle (keep MAC/BB on warm reset) */
2310 ret = ath5k_hw_on_hold(sc->ah);
2311
2312 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2313 "putting device to sleep\n");
fa1c114f 2314 }
8a63facc 2315 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 2316
8a63facc
BC		 2317 mmiowb();
2318 mutex_unlock(&sc->lock);
2319
2320 stop_tasklets(sc);
2321
2322 ath5k_rfkill_hw_stop(sc->ah);
2323
2324 return ret;
fa1c114f
JS		 2325}
2326
209d889b
BC		 2327/*
2328 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2329 * and change to the given channel.
5faaff74
BC		 2330 *
2331 * This should be called with sc->lock.
209d889b 2332 */
fa1c114f 2333static int
209d889b 2334ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2335{
fa1c114f
JS		 2336 struct ath5k_hw *ah = sc->ah;
2337 int ret;
2338
2339 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2340
450464de
BC		 2341 ath5k_hw_set_imr(ah, 0);
2342 synchronize_irq(sc->pdev->irq);
2343 stop_tasklets(sc);
2344
209d889b 2345 if (chan) {
d7dc1003
JS		 2346 ath5k_txq_cleanup(sc);
2347 ath5k_rx_stop(sc);
209d889b
BC		 2348
2349 sc->curchan = chan;
2350 sc->curband = &sc->sbands[chan->band];
d7dc1003 2351 }
3355443a 2352 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2353 if (ret) {
fa1c114f
JS		 2354 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2355 goto err;
2356 }
d7dc1003 2357
fa1c114f 2358 ret = ath5k_rx_start(sc);
d7dc1003 2359 if (ret) {
fa1c114f
JS		 2360 ATH5K_ERR(sc, "can't start recv logic\n");
2361 goto err;
2362 }
d7dc1003 2363
2111ac0d
BR		 2364 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2365
ac559526
BR		 2366 ah->ah_cal_next_full = jiffies;
2367 ah->ah_cal_next_ani = jiffies;
afe86286
BR		 2368 ah->ah_cal_next_nf = jiffies;
2369
fa1c114f 2370 /*
d7dc1003
JS		 2371 * Change channels and update the h/w rate map if we're switching;
2372 * e.g. 11a to 11b/g.
2373 *
2374 * We may be doing a reset in response to an ioctl that changes the
2375 * channel so update any state that might change as a result.
fa1c114f
JS		 2376 *
2377 * XXX needed?
2378 */
2379/* ath5k_chan_change(sc, c); */
fa1c114f 2380
d7dc1003
JS		 2381 ath5k_beacon_config(sc);
2382 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2383
397f385b
BR		 2384 ieee80211_wake_queues(sc->hw);
2385
fa1c114f
JS		 2386 return 0;
2387err:
2388 return ret;
2389}
2390
5faaff74
BC		 2391static void ath5k_reset_work(struct work_struct *work)
2392{
2393 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2394 reset_work);
2395
2396 mutex_lock(&sc->lock);
2397 ath5k_reset(sc, sc->curchan);
2398 mutex_unlock(&sc->lock);
2399}
2400
8a63facc
BC		 2401static int
2402ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
fa1c114f
JS		 2403{
2404 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2405 struct ath5k_hw *ah = sc->ah;
2406 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2407 struct ath5k_txq *txq;
8a63facc 2408 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2409 int ret;
2410
8a63facc 2411 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
fa1c114f 2412
8a63facc
BC		 2413 /*
2414 * Check if the MAC has multi-rate retry support.
2415 * We do this by trying to setup a fake extended
2416 * descriptor. MACs that don't have support will
2417 * return false w/o doing anything. MACs that do
2418 * support it will return true w/o doing anything.
2419 */
2420 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2421
8a63facc
BC		 2422 if (ret < 0)
2423 goto err;
2424 if (ret > 0)
2425 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2426
8a63facc
BC		 2427 /*
2428 * Collect the channel list. The 802.11 layer
2429 * is resposible for filtering this list based
2430 * on settings like the phy mode and regulatory
2431 * domain restrictions.
2432 */
2433 ret = ath5k_setup_bands(hw);
2434 if (ret) {
2435 ATH5K_ERR(sc, "can't get channels\n");
2436 goto err;
2437 }
67d2e2df 2438
8a63facc
BC		 2439 /* NB: setup here so ath5k_rate_update is happy */
2440 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2441 ath5k_setcurmode(sc, AR5K_MODE_11A);
2442 else
2443 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2444
8a63facc
BC		 2445 /*
2446 * Allocate tx+rx descriptors and populate the lists.
2447 */
2448 ret = ath5k_desc_alloc(sc, pdev);
2449 if (ret) {
2450 ATH5K_ERR(sc, "can't allocate descriptors\n");
2451 goto err;
2452 }
fa1c114f 2453
8a63facc
BC		 2454 /*
2455 * Allocate hardware transmit queues: one queue for
2456 * beacon frames and one data queue for each QoS
2457 * priority. Note that hw functions handle resetting
2458 * these queues at the needed time.
2459 */
2460 ret = ath5k_beaconq_setup(ah);
2461 if (ret < 0) {
2462 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2463 goto err_desc;
2464 }
2465 sc->bhalq = ret;
2466 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2467 if (IS_ERR(sc->cabq)) {
2468 ATH5K_ERR(sc, "can't setup cab queue\n");
2469 ret = PTR_ERR(sc->cabq);
2470 goto err_bhal;
2471 }
fa1c114f 2472
925e0b06
BR		 2473 /* This order matches mac80211's queue priority, so we can
2474 * directly use the mac80211 queue number without any mapping */
2475 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2476 if (IS_ERR(txq)) {
2477 ATH5K_ERR(sc, "can't setup xmit queue\n");
2478 ret = PTR_ERR(txq);
2479 goto err_queues;
2480 }
2481 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2482 if (IS_ERR(txq)) {
8a63facc 2483 ATH5K_ERR(sc, "can't setup xmit queue\n");
925e0b06 2484 ret = PTR_ERR(txq);
8a63facc
BC		 2485 goto err_queues;
2486 }
925e0b06
BR		 2487 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2488 if (IS_ERR(txq)) {
2489 ATH5K_ERR(sc, "can't setup xmit queue\n");
2490 ret = PTR_ERR(txq);
2491 goto err_queues;
2492 }
2493 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2494 if (IS_ERR(txq)) {
2495 ATH5K_ERR(sc, "can't setup xmit queue\n");
2496 ret = PTR_ERR(txq);
2497 goto err_queues;
2498 }
2499 hw->queues = 4;
fa1c114f 2500
8a63facc
BC		 2501 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2502 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2503 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2504 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2505 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2506
8a63facc 2507 INIT_WORK(&sc->reset_work, ath5k_reset_work);
fa1c114f 2508
8a63facc
BC		 2509 ret = ath5k_eeprom_read_mac(ah, mac);
2510 if (ret) {
2511 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
2512 sc->pdev->device);
2513 goto err_queues;
e30eb4ab 2514 }
2bed03eb 2515
8a63facc
BC		 2516 SET_IEEE80211_PERM_ADDR(hw, mac);
2517 /* All MAC address bits matter for ACKs */
2518 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
2519 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
2520
2521 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2522 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2523 if (ret) {
2524 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2525 goto err_queues;
2526 }
2527
2528 ret = ieee80211_register_hw(hw);
2529 if (ret) {
2530 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2531 goto err_queues;
2532 }
2533
2534 if (!ath_is_world_regd(regulatory))
2535 regulatory_hint(hw->wiphy, regulatory->alpha2);
2536
2537 ath5k_init_leds(sc);
2538
2539 ath5k_sysfs_register(sc);
2540
2541 return 0;
2542err_queues:
2543 ath5k_txq_release(sc);
2544err_bhal:
2545 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2546err_desc:
2547 ath5k_desc_free(sc, pdev);
2548err:
2549 return ret;
2550}
2551
2552static void
2553ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2554{
2555 struct ath5k_softc *sc = hw->priv;
2556
2557 /*
2558 * NB: the order of these is important:
2559 * o call the 802.11 layer before detaching ath5k_hw to
2560 * ensure callbacks into the driver to delete global
2561 * key cache entries can be handled
2562 * o reclaim the tx queue data structures after calling
2563 * the 802.11 layer as we'll get called back to reclaim
2564 * node state and potentially want to use them
2565 * o to cleanup the tx queues the hal is called, so detach
2566 * it last
2567 * XXX: ??? detach ath5k_hw ???
2568 * Other than that, it's straightforward...
2569 */
2570 ieee80211_unregister_hw(hw);
2571 ath5k_desc_free(sc, pdev);
2572 ath5k_txq_release(sc);
2573 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2574 ath5k_unregister_leds(sc);
2575
2576 ath5k_sysfs_unregister(sc);
2577 /*
2578 * NB: can't reclaim these until after ieee80211_ifdetach
2579 * returns because we'll get called back to reclaim node
2580 * state and potentially want to use them.
2581 */
2582}
2583
2584/********************\
2585* Mac80211 functions *
2586\********************/
2587
2588static int
2589ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2590{
2591 struct ath5k_softc *sc = hw->priv;
925e0b06
BR		 2592 u16 qnum = skb_get_queue_mapping(skb);
2593
2594 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2595 dev_kfree_skb_any(skb);
2596 return 0;
2597 }
8a63facc 2598
925e0b06 2599 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
8a63facc
BC		 2600}
2601
2602static int ath5k_start(struct ieee80211_hw *hw)
2603{
2604 return ath5k_init(hw->priv);
2605}
2606
2607static void ath5k_stop(struct ieee80211_hw *hw)
2608{
2609 ath5k_stop_hw(hw->priv);
2610}
2611
2612static int ath5k_add_interface(struct ieee80211_hw *hw,
2613 struct ieee80211_vif *vif)
2614{
2615 struct ath5k_softc *sc = hw->priv;
2616 int ret;
2617
2618 mutex_lock(&sc->lock);
2619 if (sc->vif) {
2620 ret = 0;
2621 goto end;
2622 }
2623
2624 sc->vif = vif;
2625
2626 switch (vif->type) {
2627 case NL80211_IFTYPE_AP:
2628 case NL80211_IFTYPE_STATION:
2629 case NL80211_IFTYPE_ADHOC:
2630 case NL80211_IFTYPE_MESH_POINT:
2631 sc->opmode = vif->type;
2632 break;
2633 default:
2634 ret = -EOPNOTSUPP;
2635 goto end;
2636 }
2637
2638 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2639
2640 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2641 ath5k_mode_setup(sc);
2642
2643 ret = 0;
2644end:
2645 mutex_unlock(&sc->lock);
2646 return ret;
2647}
2648
2649static void
2650ath5k_remove_interface(struct ieee80211_hw *hw,
2651 struct ieee80211_vif *vif)
2652{
2653 struct ath5k_softc *sc = hw->priv;
2654 u8 mac[ETH_ALEN] = {};
2655
2656 mutex_lock(&sc->lock);
2657 if (sc->vif != vif)
2658 goto end;
2659
2660 ath5k_hw_set_lladdr(sc->ah, mac);
2661 sc->vif = NULL;
2662end:
2663 mutex_unlock(&sc->lock);
2664}
2665
2666/*
2667 * TODO: Phy disable/diversity etc
2668 */
2669static int
2670ath5k_config(struct ieee80211_hw *hw, u32 changed)
2671{
2672 struct ath5k_softc *sc = hw->priv;
2673 struct ath5k_hw *ah = sc->ah;
2674 struct ieee80211_conf *conf = &hw->conf;
2675 int ret = 0;
2676
2677 mutex_lock(&sc->lock);
2678
2679 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2680 ret = ath5k_chan_set(sc, conf->channel);
2681 if (ret < 0)
2682 goto unlock;
2683 }
2684
2685 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2686 (sc->power_level != conf->power_level)) {
a0823810
NK		 2687 sc->power_level = conf->power_level;
2688
2689 /* Half dB steps */
2690 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2691 }
fa1c114f 2692
2bed03eb
NK		 2693 /* TODO:
2694 * 1) Move this on config_interface and handle each case
2695 * separately eg. when we have only one STA vif, use
2696 * AR5K_ANTMODE_SINGLE_AP
2697 *
2698 * 2) Allow the user to change antenna mode eg. when only
2699 * one antenna is present
2700 *
2701 * 3) Allow the user to set default/tx antenna when possible
2702 *
2703 * 4) Default mode should handle 90% of the cases, together
2704 * with fixed a/b and single AP modes we should be able to
2705 * handle 99%. Sectored modes are extreme cases and i still
2706 * haven't found a usage for them. If we decide to support them,
2707 * then we must allow the user to set how many tx antennas we
2708 * have available
2709 */
caec9112 2710 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 2711
55aa4e0f 2712unlock:
be009370 2713 mutex_unlock(&sc->lock);
55aa4e0f 2714 return ret;
fa1c114f
JS		 2715}
2716
3ac64bee 2717static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 2718 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 2719{
2720 u32 mfilt[2], val;
3ac64bee 2721 u8 pos;
22bedad3 2722 struct netdev_hw_addr *ha;
3ac64bee
JB		 2723
2724 mfilt[0] = 0;
2725 mfilt[1] = 1;
2726
22bedad3 2727 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 2728 /* calculate XOR of eight 6-bit values */
22bedad3 2729 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 2730 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 2731 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 2732 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2733 pos &= 0x3f;
2734 mfilt[pos / 32] |= (1 << (pos % 32));
2735 /* XXX: we might be able to just do this instead,
2736 * but not sure, needs testing, if we do use this we'd
2737 * neet to inform below to not reset the mcast */
2738 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 2739 * ha->addr[5]); */
3ac64bee
JB		 2740 }
2741
2742 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2743}
2744
fa1c114f
JS		 2745#define SUPPORTED_FIF_FLAGS \
2746 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2747 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2748 FIF_BCN_PRBRESP_PROMISC
2749/*
2750 * o always accept unicast, broadcast, and multicast traffic
2751 * o multicast traffic for all BSSIDs will be enabled if mac80211
2752 * says it should be
2753 * o maintain current state of phy ofdm or phy cck error reception.
2754 * If the hardware detects any of these type of errors then
2755 * ath5k_hw_get_rx_filter() will pass to us the respective
2756 * hardware filters to be able to receive these type of frames.
2757 * o probe request frames are accepted only when operating in
2758 * hostap, adhoc, or monitor modes
2759 * o enable promiscuous mode according to the interface state
2760 * o accept beacons:
2761 * - when operating in adhoc mode so the 802.11 layer creates
2762 * node table entries for peers,
2763 * - when operating in station mode for collecting rssi data when
2764 * the station is otherwise quiet, or
2765 * - when scanning
2766 */
2767static void ath5k_configure_filter(struct ieee80211_hw *hw,
2768 unsigned int changed_flags,
2769 unsigned int *new_flags,
3ac64bee 2770 u64 multicast)
fa1c114f
JS		 2771{
2772 struct ath5k_softc *sc = hw->priv;
2773 struct ath5k_hw *ah = sc->ah;
3ac64bee 2774 u32 mfilt[2], rfilt;
fa1c114f 2775
56d1de0a
BC		 2776 mutex_lock(&sc->lock);
2777
3ac64bee
JB		 2778 mfilt[0] = multicast;
2779 mfilt[1] = multicast >> 32;
fa1c114f
JS		 2780
2781 /* Only deal with supported flags */
2782 changed_flags &= SUPPORTED_FIF_FLAGS;
2783 *new_flags &= SUPPORTED_FIF_FLAGS;
2784
2785 /* If HW detects any phy or radar errors, leave those filters on.
2786 * Also, always enable Unicast, Broadcasts and Multicast
2787 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2788 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2789 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2790 AR5K_RX_FILTER_MCAST);
2791
2792 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2793 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 2794 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2795 } else {
fa1c114f 2796 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2797 }
fa1c114f
JS		 2798 }
2799
6b5dcccb
BC		 2800 if (test_bit(ATH_STAT_PROMISC, sc->status))
2801 rfilt |= AR5K_RX_FILTER_PROM;
2802
fa1c114f
JS		 2803 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2804 if (*new_flags & FIF_ALLMULTI) {
2805 mfilt[0] = ~0;
2806 mfilt[1] = ~0;
fa1c114f
JS		 2807 }
2808
2809 /* This is the best we can do */
2810 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2811 rfilt |= AR5K_RX_FILTER_PHYERR;
2812
2813 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
30bf4169 2814 * and probes for any BSSID */
fa1c114f 2815 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
30bf4169 2816 rfilt |= AR5K_RX_FILTER_BEACON;
fa1c114f
JS		 2817
2818 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2819 * set we should only pass on control frames for this
2820 * station. This needs testing. I believe right now this
2821 * enables *all* control frames, which is OK.. but
2822 * but we should see if we can improve on granularity */
2823 if (*new_flags & FIF_CONTROL)
2824 rfilt |= AR5K_RX_FILTER_CONTROL;
2825
2826 /* Additional settings per mode -- this is per ath5k */
2827
2828 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2829
56d1de0a
BC		 2830 switch (sc->opmode) {
2831 case NL80211_IFTYPE_MESH_POINT:
56d1de0a
BC		 2832 rfilt |= AR5K_RX_FILTER_CONTROL |
2833 AR5K_RX_FILTER_BEACON |
2834 AR5K_RX_FILTER_PROBEREQ |
2835 AR5K_RX_FILTER_PROM;
2836 break;
2837 case NL80211_IFTYPE_AP:
2838 case NL80211_IFTYPE_ADHOC:
2839 rfilt |= AR5K_RX_FILTER_PROBEREQ |
2840 AR5K_RX_FILTER_BEACON;
2841 break;
2842 case NL80211_IFTYPE_STATION:
2843 if (sc->assoc)
2844 rfilt |= AR5K_RX_FILTER_BEACON;
2845 default:
2846 break;
2847 }
fa1c114f
JS		 2848
2849 /* Set filters */
0bbac08f 2850 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2851
2852 /* Set multicast bits */
2853 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
a180a130 2854 /* Set the cached hw filter flags, this will later actually
fa1c114f
JS		 2855 * be set in HW */
2856 sc->filter_flags = rfilt;
56d1de0a
BC		 2857
2858 mutex_unlock(&sc->lock);
fa1c114f
JS		 2859}
2860
2861static int
2862ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2863 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2864 struct ieee80211_key_conf *key)
fa1c114f
JS		 2865{
2866 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 2867 struct ath5k_hw *ah = sc->ah;
2868 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 2869 int ret = 0;
2870
9ad9a26e
BC		 2871 if (modparam_nohwcrypt)
2872 return -EOPNOTSUPP;
2873
97359d12
JB		 2874 switch (key->cipher) {
2875 case WLAN_CIPHER_SUITE_WEP40:
2876 case WLAN_CIPHER_SUITE_WEP104:
2877 case WLAN_CIPHER_SUITE_TKIP:
3f64b435 2878 break;
97359d12 2879 case WLAN_CIPHER_SUITE_CCMP:
781f3136 2880 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
1c818740 2881 break;
fa1c114f
JS		 2882 return -EOPNOTSUPP;
2883 default:
2884 WARN_ON(1);
2885 return -EINVAL;
2886 }
2887
2888 mutex_lock(&sc->lock);
2889
2890 switch (cmd) {
2891 case SET_KEY:
e0f8c2a9
BR		 2892 ret = ath_key_config(common, vif, sta, key);
2893 if (ret >= 0) {
2894 key->hw_key_idx = ret;
2895 /* push IV and Michael MIC generation to stack */
2896 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2897 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
2898 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2899 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
2900 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2901 ret = 0;
fa1c114f 2902 }
fa1c114f
JS		 2903 break;
2904 case DISABLE_KEY:
e0f8c2a9 2905 ath_key_delete(common, key);
fa1c114f
JS		 2906 break;
2907 default:
2908 ret = -EINVAL;
fa1c114f
JS		 2909 }
2910
8a63facc
BC		 2911 mmiowb();
2912 mutex_unlock(&sc->lock);
2913 return ret;
2914}
2915
2916static int
2917ath5k_get_stats(struct ieee80211_hw *hw,
2918 struct ieee80211_low_level_stats *stats)
2919{
2920 struct ath5k_softc *sc = hw->priv;
2921
2922 /* Force update */
2923 ath5k_hw_update_mib_counters(sc->ah);
2924
2925 stats->dot11ACKFailureCount = sc->stats.ack_fail;
2926 stats->dot11RTSFailureCount = sc->stats.rts_fail;
2927 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
2928 stats->dot11FCSErrorCount = sc->stats.fcs_error;
2929
2930 return 0;
2931}
2932
2933static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
2934 struct survey_info *survey)
2935{
2936 struct ath5k_softc *sc = hw->priv;
2937 struct ieee80211_conf *conf = &hw->conf;
2938
2939 if (idx != 0)
2940 return -ENOENT;
2941
2942 survey->channel = conf->channel;
2943 survey->filled = SURVEY_INFO_NOISE_DBM;
2944 survey->noise = sc->ah->ah_noise_floor;
2945
2946 return 0;
2947}
2948
2949static u64
2950ath5k_get_tsf(struct ieee80211_hw *hw)
2951{
2952 struct ath5k_softc *sc = hw->priv;
2953
2954 return ath5k_hw_get_tsf64(sc->ah);
2955}
2956
2957static void
2958ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2959{
2960 struct ath5k_softc *sc = hw->priv;
2961
2962 ath5k_hw_set_tsf64(sc->ah, tsf);
2963}
2964
2965static void
2966ath5k_reset_tsf(struct ieee80211_hw *hw)
2967{
2968 struct ath5k_softc *sc = hw->priv;
2969
2970 /*
2971 * in IBSS mode we need to update the beacon timers too.
2972 * this will also reset the TSF if we call it with 0
2973 */
2974 if (sc->opmode == NL80211_IFTYPE_ADHOC)
2975 ath5k_beacon_update_timers(sc, 0);
2976 else
2977 ath5k_hw_reset_tsf(sc->ah);
2978}
2979
2980static void
2981set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2982{
2983 struct ath5k_softc *sc = hw->priv;
2984 struct ath5k_hw *ah = sc->ah;
2985 u32 rfilt;
2986 rfilt = ath5k_hw_get_rx_filter(ah);
2987 if (enable)
2988 rfilt |= AR5K_RX_FILTER_BEACON;
2989 else
2990 rfilt &= ~AR5K_RX_FILTER_BEACON;
2991 ath5k_hw_set_rx_filter(ah, rfilt);
2992 sc->filter_flags = rfilt;
2993}
2994
2995static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
2996 struct ieee80211_vif *vif,
2997 struct ieee80211_bss_conf *bss_conf,
2998 u32 changes)
2999{
3000 struct ath5k_softc *sc = hw->priv;
3001 struct ath5k_hw *ah = sc->ah;
3002 struct ath_common *common = ath5k_hw_common(ah);
3003 unsigned long flags;
3004
3005 mutex_lock(&sc->lock);
3006 if (WARN_ON(sc->vif != vif))
3007 goto unlock;
3008
3009 if (changes & BSS_CHANGED_BSSID) {
3010 /* Cache for later use during resets */
3011 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3012 common->curaid = 0;
3013 ath5k_hw_set_bssid(ah);
3014 mmiowb();
3015 }
3016
3017 if (changes & BSS_CHANGED_BEACON_INT)
3018 sc->bintval = bss_conf->beacon_int;
3019
3020 if (changes & BSS_CHANGED_ASSOC) {
3021 sc->assoc = bss_conf->assoc;
3022 if (sc->opmode == NL80211_IFTYPE_STATION)
3023 set_beacon_filter(hw, sc->assoc);
3024 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3025 AR5K_LED_ASSOC : AR5K_LED_INIT);
3026 if (bss_conf->assoc) {
3027 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3028 "Bss Info ASSOC %d, bssid: %pM\n",
3029 bss_conf->aid, common->curbssid);
3030 common->curaid = bss_conf->aid;
3031 ath5k_hw_set_bssid(ah);
3032 /* Once ANI is available you would start it here */
3033 }
3034 }
3035
3036 if (changes & BSS_CHANGED_BEACON) {
3037 spin_lock_irqsave(&sc->block, flags);
3038 ath5k_beacon_update(hw, vif);
3039 spin_unlock_irqrestore(&sc->block, flags);
3040 }
3041
3042 if (changes & BSS_CHANGED_BEACON_ENABLED)
3043 sc->enable_beacon = bss_conf->enable_beacon;
3044
3045 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3046 BSS_CHANGED_BEACON_INT))
3047 ath5k_beacon_config(sc);
3048
3049 unlock:
3050 mutex_unlock(&sc->lock);
3051}
3052
3053static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3054{
3055 struct ath5k_softc *sc = hw->priv;
3056 if (!sc->assoc)
3057 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3058}
3059
3060static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3061{
3062 struct ath5k_softc *sc = hw->priv;
3063 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3064 AR5K_LED_ASSOC : AR5K_LED_INIT);
3065}
3066
3067/**
3068 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3069 *
3070 * @hw: struct ieee80211_hw pointer
3071 * @coverage_class: IEEE 802.11 coverage class number
3072 *
3073 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3074 * coverage class. The values are persistent, they are restored after device
3075 * reset.
3076 */
3077static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3078{
3079 struct ath5k_softc *sc = hw->priv;
3080
3081 mutex_lock(&sc->lock);
3082 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3083 mutex_unlock(&sc->lock);
3084}
3085
3086static const struct ieee80211_ops ath5k_hw_ops = {
3087 .tx = ath5k_tx,
3088 .start = ath5k_start,
3089 .stop = ath5k_stop,
3090 .add_interface = ath5k_add_interface,
3091 .remove_interface = ath5k_remove_interface,
3092 .config = ath5k_config,
3093 .prepare_multicast = ath5k_prepare_multicast,
3094 .configure_filter = ath5k_configure_filter,
3095 .set_key = ath5k_set_key,
3096 .get_stats = ath5k_get_stats,
3097 .get_survey = ath5k_get_survey,
3098 .conf_tx = NULL,
3099 .get_tsf = ath5k_get_tsf,
3100 .set_tsf = ath5k_set_tsf,
3101 .reset_tsf = ath5k_reset_tsf,
3102 .bss_info_changed = ath5k_bss_info_changed,
3103 .sw_scan_start = ath5k_sw_scan_start,
3104 .sw_scan_complete = ath5k_sw_scan_complete,
3105 .set_coverage_class = ath5k_set_coverage_class,
3106};
3107
3108/********************\
3109* PCI Initialization *
3110\********************/
3111
3112static int __devinit
3113ath5k_pci_probe(struct pci_dev *pdev,
3114 const struct pci_device_id *id)
3115{
3116 void __iomem *mem;
3117 struct ath5k_softc *sc;
3118 struct ath_common *common;
3119 struct ieee80211_hw *hw;
3120 int ret;
3121 u8 csz;
3122
3123 /*
3124 * L0s needs to be disabled on all ath5k cards.
3125 *
3126 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3127 * by default in the future in 2.6.36) this will also mean both L1 and
3128 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3129 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3130 * though but cannot currently undue the effect of a blacklist, for
3131 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3132 * the device link capability.
3133 *
3134 * It may be possible in the future to implement some PCI API to allow
3135 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3136 * best to accept that both L0s and L1 will be disabled completely for
3137 * distributions shipping with CONFIG_PCIEASPM rather than having this
3138 * issue present. Motivation for adding this new API will be to help
3139 * with power consumption for some of these devices.
3140 */
3141 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
3142
3143 ret = pci_enable_device(pdev);
3144 if (ret) {
3145 dev_err(&pdev->dev, "can't enable device\n");
3146 goto err;
3147 }
3148
3149 /* XXX 32-bit addressing only */
3150 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3151 if (ret) {
3152 dev_err(&pdev->dev, "32-bit DMA not available\n");
3153 goto err_dis;
3154 }
3155
3156 /*
3157 * Cache line size is used to size and align various
3158 * structures used to communicate with the hardware.
3159 */
3160 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
3161 if (csz == 0) {
3162 /*
3163 * Linux 2.4.18 (at least) writes the cache line size
3164 * register as a 16-bit wide register which is wrong.
3165 * We must have this setup properly for rx buffer
3166 * DMA to work so force a reasonable value here if it
3167 * comes up zero.
3168 */
3169 csz = L1_CACHE_BYTES >> 2;
3170 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
3171 }
3172 /*
3173 * The default setting of latency timer yields poor results,
3174 * set it to the value used by other systems. It may be worth
3175 * tweaking this setting more.
3176 */
3177 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
3178
3179 /* Enable bus mastering */
3180 pci_set_master(pdev);
3181
3182 /*
3183 * Disable the RETRY_TIMEOUT register (0x41) to keep
3184 * PCI Tx retries from interfering with C3 CPU state.
3185 */
3186 pci_write_config_byte(pdev, 0x41, 0);
3187
3188 ret = pci_request_region(pdev, 0, "ath5k");
3189 if (ret) {
3190 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
3191 goto err_dis;
3192 }
3193
3194 mem = pci_iomap(pdev, 0, 0);
3195 if (!mem) {
3196 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
3197 ret = -EIO;
3198 goto err_reg;
3199 }
3200
3201 /*
3202 * Allocate hw (mac80211 main struct)
3203 * and hw->priv (driver private data)
3204 */
3205 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
3206 if (hw == NULL) {
3207 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
3208 ret = -ENOMEM;
3209 goto err_map;
3210 }
3211
3212 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
3213
3214 /* Initialize driver private data */
3215 SET_IEEE80211_DEV(hw, &pdev->dev);
3216 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3217 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3218 IEEE80211_HW_SIGNAL_DBM;
3219
3220 hw->wiphy->interface_modes =
3221 BIT(NL80211_IFTYPE_AP) |
3222 BIT(NL80211_IFTYPE_STATION) |
3223 BIT(NL80211_IFTYPE_ADHOC) |
3224 BIT(NL80211_IFTYPE_MESH_POINT);
3225
3226 hw->extra_tx_headroom = 2;
3227 hw->channel_change_time = 5000;
3228 sc = hw->priv;
3229 sc->hw = hw;
3230 sc->pdev = pdev;
3231
3232 ath5k_debug_init_device(sc);
3233
3234 /*
3235 * Mark the device as detached to avoid processing
3236 * interrupts until setup is complete.
3237 */
3238 __set_bit(ATH_STAT_INVALID, sc->status);
3239
3240 sc->iobase = mem; /* So we can unmap it on detach */
3241 sc->opmode = NL80211_IFTYPE_STATION;
3242 sc->bintval = 1000;
3243 mutex_init(&sc->lock);
3244 spin_lock_init(&sc->rxbuflock);
3245 spin_lock_init(&sc->txbuflock);
3246 spin_lock_init(&sc->block);
3247
3248 /* Set private data */
3249 pci_set_drvdata(pdev, sc);
3250
3251 /* Setup interrupt handler */
3252 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
3253 if (ret) {
3254 ATH5K_ERR(sc, "request_irq failed\n");
3255 goto err_free;
3256 }
3257
3258 /* If we passed the test, malloc an ath5k_hw struct */
3259 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
3260 if (!sc->ah) {
3261 ret = -ENOMEM;
3262 ATH5K_ERR(sc, "out of memory\n");
3263 goto err_irq;
3264 }
3265
3266 sc->ah->ah_sc = sc;
3267 sc->ah->ah_iobase = sc->iobase;
3268 common = ath5k_hw_common(sc->ah);
3269 common->ops = &ath5k_common_ops;
3270 common->ah = sc->ah;
3271 common->hw = hw;
3272 common->cachelsz = csz << 2; /* convert to bytes */
3273
3274 /* Initialize device */
3275 ret = ath5k_hw_attach(sc);
3276 if (ret) {
3277 goto err_free_ah;
3278 }
3279
3280 /* set up multi-rate retry capabilities */
3281 if (sc->ah->ah_version == AR5K_AR5212) {
3282 hw->max_rates = 4;
3283 hw->max_rate_tries = 11;
3284 }
3285
3286 /* Finish private driver data initialization */
3287 ret = ath5k_attach(pdev, hw);
3288 if (ret)
3289 goto err_ah;
3290
3291 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3292 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
3293 sc->ah->ah_mac_srev,
3294 sc->ah->ah_phy_revision);
3295
3296 if (!sc->ah->ah_single_chip) {
3297 /* Single chip radio (!RF5111) */
3298 if (sc->ah->ah_radio_5ghz_revision &&
3299 !sc->ah->ah_radio_2ghz_revision) {
3300 /* No 5GHz support -> report 2GHz radio */
3301 if (!test_bit(AR5K_MODE_11A,
3302 sc->ah->ah_capabilities.cap_mode)) {
3303 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3304 ath5k_chip_name(AR5K_VERSION_RAD,
3305 sc->ah->ah_radio_5ghz_revision),
3306 sc->ah->ah_radio_5ghz_revision);
3307 /* No 2GHz support (5110 and some
3308 * 5Ghz only cards) -> report 5Ghz radio */
3309 } else if (!test_bit(AR5K_MODE_11B,
3310 sc->ah->ah_capabilities.cap_mode)) {
3311 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3312 ath5k_chip_name(AR5K_VERSION_RAD,
3313 sc->ah->ah_radio_5ghz_revision),
3314 sc->ah->ah_radio_5ghz_revision);
3315 /* Multiband radio */
3316 } else {
3317 ATH5K_INFO(sc, "RF%s multiband radio found"
3318 " (0x%x)\n",
3319 ath5k_chip_name(AR5K_VERSION_RAD,
3320 sc->ah->ah_radio_5ghz_revision),
3321 sc->ah->ah_radio_5ghz_revision);
3322 }
3323 }
3324 /* Multi chip radio (RF5111 - RF2111) ->
3325 * report both 2GHz/5GHz radios */
3326 else if (sc->ah->ah_radio_5ghz_revision &&
3327 sc->ah->ah_radio_2ghz_revision){
3328 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3329 ath5k_chip_name(AR5K_VERSION_RAD,
3330 sc->ah->ah_radio_5ghz_revision),
3331 sc->ah->ah_radio_5ghz_revision);
3332 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3333 ath5k_chip_name(AR5K_VERSION_RAD,
3334 sc->ah->ah_radio_2ghz_revision),
3335 sc->ah->ah_radio_2ghz_revision);
3336 }
3337 }
3338
55ee82b5 3339
8a63facc
BC		 3340 /* ready to process interrupts */
3341 __clear_bit(ATH_STAT_INVALID, sc->status);
55ee82b5
HS		 3342
3343 return 0;
8a63facc
BC		 3344err_ah:
3345 ath5k_hw_detach(sc->ah);
3346err_free_ah:
3347 kfree(sc->ah);
3348err_irq:
3349 free_irq(pdev->irq, sc);
3350err_free:
3351 ieee80211_free_hw(hw);
3352err_map:
3353 pci_iounmap(pdev, mem);
3354err_reg:
3355 pci_release_region(pdev, 0);
3356err_dis:
3357 pci_disable_device(pdev);
3358err:
3359 return ret;
55ee82b5
HS		 3360}
3361
8a63facc
BC		 3362static void __devexit
3363ath5k_pci_remove(struct pci_dev *pdev)
fa1c114f 3364{
8a63facc 3365 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3366
8a63facc
BC		 3367 ath5k_debug_finish_device(sc);
3368 ath5k_detach(pdev, sc->hw);
3369 ath5k_hw_detach(sc->ah);
3370 kfree(sc->ah);
3371 free_irq(pdev->irq, sc);
3372 pci_iounmap(pdev, sc->iobase);
3373 pci_release_region(pdev, 0);
3374 pci_disable_device(pdev);
3375 ieee80211_free_hw(sc->hw);
fa1c114f
JS		 3376}
3377
8a63facc
BC		 3378#ifdef CONFIG_PM_SLEEP
3379static int ath5k_pci_suspend(struct device *dev)
3b5d665b 3380{
8a63facc 3381 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
3b5d665b 3382
8a63facc
BC		 3383 ath5k_led_off(sc);
3384 return 0;
3b5d665b
AF		 3385}
3386
8a63facc 3387static int ath5k_pci_resume(struct device *dev)
fa1c114f 3388{
8a63facc
BC		 3389 struct pci_dev *pdev = to_pci_dev(dev);
3390 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3391
9804b98d 3392 /*
8a63facc
BC		 3393 * Suspend/Resume resets the PCI configuration space, so we have to
3394 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3395 * PCI Tx retries from interfering with C3 CPU state
9804b98d 3396 */
8a63facc
BC		 3397 pci_write_config_byte(pdev, 0x41, 0);
3398
3399 ath5k_led_enable(sc);
3400 return 0;
fa1c114f
JS		 3401}
3402
8a63facc
BC		 3403static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
3404#define ATH5K_PM_OPS (&ath5k_pm_ops)
3405#else
3406#define ATH5K_PM_OPS NULL
3407#endif /* CONFIG_PM_SLEEP */
3408
3409static struct pci_driver ath5k_pci_driver = {
3410 .name = KBUILD_MODNAME,
3411 .id_table = ath5k_pci_id_table,
3412 .probe = ath5k_pci_probe,
3413 .remove = __devexit_p(ath5k_pci_remove),
3414 .driver.pm = ATH5K_PM_OPS,
3415};
3416
1071db86 3417/*
8a63facc 3418 * Module init/exit functions
1071db86 3419 */
8a63facc
BC		 3420static int __init
3421init_ath5k_pci(void)
fa1c114f 3422{
fa1c114f 3423 int ret;
57c4d7b4 3424
8a63facc 3425 ath5k_debug_init();
2d0ddec5 3426
8a63facc
BC		 3427 ret = pci_register_driver(&ath5k_pci_driver);
3428 if (ret) {
3429 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
3430 return ret;
2d0ddec5
JB		 3431 }
3432
8a63facc 3433 return 0;
02969b38 3434}
f0f3d388 3435
8a63facc
BC		 3436static void __exit
3437exit_ath5k_pci(void)
f0f3d388 3438{
8a63facc 3439 pci_unregister_driver(&ath5k_pci_driver);
f0f3d388 3440
8a63facc 3441 ath5k_debug_finish();
f0f3d388 3442}
6e08d228 3443
8a63facc
BC		 3444module_init(init_ath5k_pci);
3445module_exit(exit_ath5k_pci);
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