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ath5k: remove static calibration interval variable
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
9ad9a26e 62static int modparam_nohwcrypt;
46802a4f 63module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 64MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 65
42639fcd 66static int modparam_all_channels;
46802a4f 67module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 68MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
69
fa1c114f
JS		 70
71/******************\
72* Internal defines *
73\******************/
74
75/* Module info */
76MODULE_AUTHOR("Jiri Slaby");
77MODULE_AUTHOR("Nick Kossifidis");
78MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 81MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 82
83
84/* Known PCI ids */
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 86 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
87 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
88 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
89 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
90 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
91 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
92 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
93 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
101 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
102 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
103 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 104 { 0 }
105};
106MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
107
108/* Known SREVs */
2c91108c 109static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 110 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
111 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
112 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
113 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
114 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
115 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
116 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
117 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
118 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
119 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
120 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
121 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
122 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
123 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
124 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
125 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
126 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
127 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
128 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 129 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
130 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 131 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 132 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
133 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
134 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 135 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 136 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
137 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 138 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
139 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
140 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
141 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
142 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
143 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 144 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
145 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
146};
147
2c91108c 148static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 149 { .bitrate = 10,
150 .hw_value = ATH5K_RATE_CODE_1M, },
151 { .bitrate = 20,
152 .hw_value = ATH5K_RATE_CODE_2M,
153 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
155 { .bitrate = 55,
156 .hw_value = ATH5K_RATE_CODE_5_5M,
157 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
158 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
159 { .bitrate = 110,
160 .hw_value = ATH5K_RATE_CODE_11M,
161 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
162 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
163 { .bitrate = 60,
164 .hw_value = ATH5K_RATE_CODE_6M,
165 .flags = 0 },
166 { .bitrate = 90,
167 .hw_value = ATH5K_RATE_CODE_9M,
168 .flags = 0 },
169 { .bitrate = 120,
170 .hw_value = ATH5K_RATE_CODE_12M,
171 .flags = 0 },
172 { .bitrate = 180,
173 .hw_value = ATH5K_RATE_CODE_18M,
174 .flags = 0 },
175 { .bitrate = 240,
176 .hw_value = ATH5K_RATE_CODE_24M,
177 .flags = 0 },
178 { .bitrate = 360,
179 .hw_value = ATH5K_RATE_CODE_36M,
180 .flags = 0 },
181 { .bitrate = 480,
182 .hw_value = ATH5K_RATE_CODE_48M,
183 .flags = 0 },
184 { .bitrate = 540,
185 .hw_value = ATH5K_RATE_CODE_54M,
186 .flags = 0 },
187 /* XR missing */
188};
189
fa1c114f
JS		 190/*
191 * Prototypes - PCI stack related functions
192 */
193static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
194 const struct pci_device_id *id);
195static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
196#ifdef CONFIG_PM
baee1f3c
RW		 197static int ath5k_pci_suspend(struct device *dev);
198static int ath5k_pci_resume(struct device *dev);
199
626ede6b 200static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
baee1f3c 201#define ATH5K_PM_OPS (&ath5k_pm_ops)
fa1c114f 202#else
baee1f3c 203#define ATH5K_PM_OPS NULL
fa1c114f
JS		 204#endif /* CONFIG_PM */
205
04a9e451 206static struct pci_driver ath5k_pci_driver = {
9764f3f9 207 .name = KBUILD_MODNAME,
fa1c114f
JS		 208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
baee1f3c 211 .driver.pm = ATH5K_PM_OPS,
fa1c114f
JS		 212};
213
214
215
216/*
217 * Prototypes - MAC 802.11 stack related functions
218 */
e039fa4a 219static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 220static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
221 struct ath5k_txq *txq);
209d889b 222static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 223static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 224static int ath5k_start(struct ieee80211_hw *hw);
225static void ath5k_stop(struct ieee80211_hw *hw);
226static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 227 struct ieee80211_vif *vif);
fa1c114f 228static void ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 229 struct ieee80211_vif *vif);
e8975581 230static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee
JB		 231static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
232 int mc_count, struct dev_addr_list *mc_list);
fa1c114f
JS		 233static void ath5k_configure_filter(struct ieee80211_hw *hw,
234 unsigned int changed_flags,
235 unsigned int *new_flags,
3ac64bee 236 u64 multicast);
fa1c114f
JS		 237static int ath5k_set_key(struct ieee80211_hw *hw,
238 enum set_key_cmd cmd,
dc822b5d 239 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 240 struct ieee80211_key_conf *key);
241static int ath5k_get_stats(struct ieee80211_hw *hw,
242 struct ieee80211_low_level_stats *stats);
fa1c114f 243static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 244static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 245static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 246static int ath5k_beacon_update(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif);
02969b38
MX		 248static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
249 struct ieee80211_vif *vif,
250 struct ieee80211_bss_conf *bss_conf,
251 u32 changes);
f0f3d388
BC		 252static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
253static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
6e08d228
LT		 254static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
255 u8 coverage_class);
fa1c114f 256
2c91108c 257static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 258 .tx = ath5k_tx,
259 .start = ath5k_start,
260 .stop = ath5k_stop,
261 .add_interface = ath5k_add_interface,
262 .remove_interface = ath5k_remove_interface,
263 .config = ath5k_config,
3ac64bee 264 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 265 .configure_filter = ath5k_configure_filter,
266 .set_key = ath5k_set_key,
267 .get_stats = ath5k_get_stats,
268 .conf_tx = NULL,
fa1c114f 269 .get_tsf = ath5k_get_tsf,
3b5d665b 270 .set_tsf = ath5k_set_tsf,
fa1c114f 271 .reset_tsf = ath5k_reset_tsf,
02969b38 272 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 273 .sw_scan_start = ath5k_sw_scan_start,
274 .sw_scan_complete = ath5k_sw_scan_complete,
6e08d228 275 .set_coverage_class = ath5k_set_coverage_class,
fa1c114f
JS		 276};
277
278/*
279 * Prototypes - Internal functions
280 */
281/* Attach detach */
282static int ath5k_attach(struct pci_dev *pdev,
283 struct ieee80211_hw *hw);
284static void ath5k_detach(struct pci_dev *pdev,
285 struct ieee80211_hw *hw);
286/* Channel/mode setup */
287static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 288static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
289 struct ieee80211_channel *channels,
290 unsigned int mode,
291 unsigned int max);
63266a65 292static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 293static int ath5k_chan_set(struct ath5k_softc *sc,
294 struct ieee80211_channel *chan);
295static void ath5k_setcurmode(struct ath5k_softc *sc,
296 unsigned int mode);
297static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 298
fa1c114f
JS		 299/* Descriptor setup */
300static int ath5k_desc_alloc(struct ath5k_softc *sc,
301 struct pci_dev *pdev);
302static void ath5k_desc_free(struct ath5k_softc *sc,
303 struct pci_dev *pdev);
304/* Buffers setup */
305static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
306 struct ath5k_buf *bf);
307static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23 308 struct ath5k_buf *bf,
8127fbdc 309 struct ath5k_txq *txq, int padsize);
fa1c114f
JS		 310static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
311 struct ath5k_buf *bf)
312{
313 BUG_ON(!bf);
314 if (!bf->skb)
315 return;
316 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
317 PCI_DMA_TODEVICE);
00482973 318 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 319 bf->skb = NULL;
320}
321
a6c8d375
FF		 322static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
323 struct ath5k_buf *bf)
324{
cc861f74
LR		 325 struct ath5k_hw *ah = sc->ah;
326 struct ath_common *common = ath5k_hw_common(ah);
327
a6c8d375
FF		 328 BUG_ON(!bf);
329 if (!bf->skb)
330 return;
cc861f74 331 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 332 PCI_DMA_FROMDEVICE);
333 dev_kfree_skb_any(bf->skb);
334 bf->skb = NULL;
335}
336
337
fa1c114f
JS		 338/* Queues setup */
339static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
340 int qtype, int subtype);
341static int ath5k_beaconq_setup(struct ath5k_hw *ah);
342static int ath5k_beaconq_config(struct ath5k_softc *sc);
343static void ath5k_txq_drainq(struct ath5k_softc *sc,
344 struct ath5k_txq *txq);
345static void ath5k_txq_cleanup(struct ath5k_softc *sc);
346static void ath5k_txq_release(struct ath5k_softc *sc);
347/* Rx handling */
348static int ath5k_rx_start(struct ath5k_softc *sc);
349static void ath5k_rx_stop(struct ath5k_softc *sc);
350static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
351 struct ath5k_desc *ds,
b47f407b
BR		 352 struct sk_buff *skb,
353 struct ath5k_rx_status *rs);
fa1c114f
JS		 354static void ath5k_tasklet_rx(unsigned long data);
355/* Tx handling */
356static void ath5k_tx_processq(struct ath5k_softc *sc,
357 struct ath5k_txq *txq);
358static void ath5k_tasklet_tx(unsigned long data);
359/* Beacon handling */
360static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 361 struct ath5k_buf *bf);
fa1c114f
JS		 362static void ath5k_beacon_send(struct ath5k_softc *sc);
363static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 364static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 365static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 366
367static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
368{
369 u64 tsf = ath5k_hw_get_tsf64(ah);
370
371 if ((tsf & 0x7fff) < rstamp)
372 tsf -= 0x8000;
373
374 return (tsf & ~0x7fff) | rstamp;
375}
376
377/* Interrupt handling */
bb2becac 378static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 379static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 380static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 381static irqreturn_t ath5k_intr(int irq, void *dev_id);
382static void ath5k_tasklet_reset(unsigned long data);
383
6e220662 384static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 385
386/*
387 * Module init/exit functions
388 */
389static int __init
390init_ath5k_pci(void)
391{
392 int ret;
393
394 ath5k_debug_init();
395
04a9e451 396 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 397 if (ret) {
398 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
399 return ret;
400 }
401
402 return 0;
403}
404
405static void __exit
406exit_ath5k_pci(void)
407{
04a9e451 408 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 409
410 ath5k_debug_finish();
411}
412
413module_init(init_ath5k_pci);
414module_exit(exit_ath5k_pci);
415
416
417/********************\
418* PCI Initialization *
419\********************/
420
421static const char *
422ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
423{
424 const char *name = "xxxxx";
425 unsigned int i;
426
427 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
428 if (srev_names[i].sr_type != type)
429 continue;
75d0edb8
NK		 430
431 if ((val & 0xf0) == srev_names[i].sr_val)
432 name = srev_names[i].sr_name;
433
434 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 435 name = srev_names[i].sr_name;
436 break;
437 }
438 }
439
440 return name;
441}
e5aa8474
LR		 442static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
443{
444 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
445 return ath5k_hw_reg_read(ah, reg_offset);
446}
447
448static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
449{
450 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
451 ath5k_hw_reg_write(ah, val, reg_offset);
452}
453
454static const struct ath_ops ath5k_common_ops = {
455 .read = ath5k_ioread32,
456 .write = ath5k_iowrite32,
457};
fa1c114f
JS		 458
459static int __devinit
460ath5k_pci_probe(struct pci_dev *pdev,
461 const struct pci_device_id *id)
462{
463 void __iomem *mem;
464 struct ath5k_softc *sc;
db719718 465 struct ath_common *common;
fa1c114f
JS		 466 struct ieee80211_hw *hw;
467 int ret;
468 u8 csz;
469
470 ret = pci_enable_device(pdev);
471 if (ret) {
472 dev_err(&pdev->dev, "can't enable device\n");
473 goto err;
474 }
475
476 /* XXX 32-bit addressing only */
284901a9 477 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 478 if (ret) {
479 dev_err(&pdev->dev, "32-bit DMA not available\n");
480 goto err_dis;
481 }
482
483 /*
484 * Cache line size is used to size and align various
485 * structures used to communicate with the hardware.
486 */
487 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
488 if (csz == 0) {
489 /*
490 * Linux 2.4.18 (at least) writes the cache line size
491 * register as a 16-bit wide register which is wrong.
492 * We must have this setup properly for rx buffer
493 * DMA to work so force a reasonable value here if it
494 * comes up zero.
495 */
13311b00 496 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 497 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
498 }
499 /*
500 * The default setting of latency timer yields poor results,
501 * set it to the value used by other systems. It may be worth
502 * tweaking this setting more.
503 */
504 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
505
506 /* Enable bus mastering */
507 pci_set_master(pdev);
508
509 /*
510 * Disable the RETRY_TIMEOUT register (0x41) to keep
511 * PCI Tx retries from interfering with C3 CPU state.
512 */
513 pci_write_config_byte(pdev, 0x41, 0);
514
515 ret = pci_request_region(pdev, 0, "ath5k");
516 if (ret) {
517 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
518 goto err_dis;
519 }
520
521 mem = pci_iomap(pdev, 0, 0);
522 if (!mem) {
523 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
524 ret = -EIO;
525 goto err_reg;
526 }
527
528 /*
529 * Allocate hw (mac80211 main struct)
530 * and hw->priv (driver private data)
531 */
532 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
533 if (hw == NULL) {
534 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
535 ret = -ENOMEM;
536 goto err_map;
537 }
538
539 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
540
541 /* Initialize driver private data */
542 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 543 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 544 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
566bfe5a
BR		 545 IEEE80211_HW_SIGNAL_DBM |
546 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 547
548 hw->wiphy->interface_modes =
6f5f39c9 549 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 550 BIT(NL80211_IFTYPE_STATION) |
551 BIT(NL80211_IFTYPE_ADHOC) |
552 BIT(NL80211_IFTYPE_MESH_POINT);
553
fa1c114f
JS		 554 hw->extra_tx_headroom = 2;
555 hw->channel_change_time = 5000;
fa1c114f
JS		 556 sc = hw->priv;
557 sc->hw = hw;
558 sc->pdev = pdev;
559
560 ath5k_debug_init_device(sc);
561
562 /*
563 * Mark the device as detached to avoid processing
564 * interrupts until setup is complete.
565 */
566 __set_bit(ATH_STAT_INVALID, sc->status);
567
568 sc->iobase = mem; /* So we can unmap it on detach */
05c914fe 569 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 570 sc->bintval = 1000;
fa1c114f
JS		 571 mutex_init(&sc->lock);
572 spin_lock_init(&sc->rxbuflock);
573 spin_lock_init(&sc->txbuflock);
00482973 574 spin_lock_init(&sc->block);
fa1c114f
JS		 575
576 /* Set private data */
577 pci_set_drvdata(pdev, hw);
578
fa1c114f
JS		 579 /* Setup interrupt handler */
580 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
581 if (ret) {
582 ATH5K_ERR(sc, "request_irq failed\n");
583 goto err_free;
584 }
585
9adca126
LR		 586 /*If we passed the test malloc a ath5k_hw struct*/
587 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
588 if (!sc->ah) {
589 ret = -ENOMEM;
590 ATH5K_ERR(sc, "out of memory\n");
fa1c114f
JS		 591 goto err_irq;
592 }
593
9adca126
LR		 594 sc->ah->ah_sc = sc;
595 sc->ah->ah_iobase = sc->iobase;
db719718 596 common = ath5k_hw_common(sc->ah);
e5aa8474 597 common->ops = &ath5k_common_ops;
13b81559 598 common->ah = sc->ah;
b002a4a9 599 common->hw = hw;
db719718
LR		 600 common->cachelsz = csz << 2; /* convert to bytes */
601
9adca126
LR		 602 /* Initialize device */
603 ret = ath5k_hw_attach(sc);
604 if (ret) {
605 goto err_free_ah;
606 }
607
2f7fe870
FF		 608 /* set up multi-rate retry capabilities */
609 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 610 hw->max_rates = 4;
611 hw->max_rate_tries = 11;
2f7fe870
FF		 612 }
613
fa1c114f
JS		 614 /* Finish private driver data initialization */
615 ret = ath5k_attach(pdev, hw);
616 if (ret)
617 goto err_ah;
618
619 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 620 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 621 sc->ah->ah_mac_srev,
622 sc->ah->ah_phy_revision);
623
400ec45a 624 if (!sc->ah->ah_single_chip) {
fa1c114f 625 /* Single chip radio (!RF5111) */
400ec45a
LR		 626 if (sc->ah->ah_radio_5ghz_revision &&
627 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 628 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 629 if (!test_bit(AR5K_MODE_11A,
630 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 631 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 632 ath5k_chip_name(AR5K_VERSION_RAD,
633 sc->ah->ah_radio_5ghz_revision),
634 sc->ah->ah_radio_5ghz_revision);
635 /* No 2GHz support (5110 and some
636 * 5Ghz only cards) -> report 5Ghz radio */
637 } else if (!test_bit(AR5K_MODE_11B,
638 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 639 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 640 ath5k_chip_name(AR5K_VERSION_RAD,
641 sc->ah->ah_radio_5ghz_revision),
642 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 643 /* Multiband radio */
644 } else {
645 ATH5K_INFO(sc, "RF%s multiband radio found"
646 " (0x%x)\n",
400ec45a
LR		 647 ath5k_chip_name(AR5K_VERSION_RAD,
648 sc->ah->ah_radio_5ghz_revision),
649 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 650 }
651 }
400ec45a
LR		 652 /* Multi chip radio (RF5111 - RF2111) ->
653 * report both 2GHz/5GHz radios */
654 else if (sc->ah->ah_radio_5ghz_revision &&
655 sc->ah->ah_radio_2ghz_revision){
fa1c114f 656 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 657 ath5k_chip_name(AR5K_VERSION_RAD,
658 sc->ah->ah_radio_5ghz_revision),
659 sc->ah->ah_radio_5ghz_revision);
fa1c114f 660 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 661 ath5k_chip_name(AR5K_VERSION_RAD,
662 sc->ah->ah_radio_2ghz_revision),
663 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 664 }
665 }
666
667
668 /* ready to process interrupts */
669 __clear_bit(ATH_STAT_INVALID, sc->status);
670
671 return 0;
672err_ah:
673 ath5k_hw_detach(sc->ah);
674err_irq:
675 free_irq(pdev->irq, sc);
9adca126
LR		 676err_free_ah:
677 kfree(sc->ah);
fa1c114f 678err_free:
fa1c114f
JS		 679 ieee80211_free_hw(hw);
680err_map:
681 pci_iounmap(pdev, mem);
682err_reg:
683 pci_release_region(pdev, 0);
684err_dis:
685 pci_disable_device(pdev);
686err:
687 return ret;
688}
689
690static void __devexit
691ath5k_pci_remove(struct pci_dev *pdev)
692{
693 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
694 struct ath5k_softc *sc = hw->priv;
695
696 ath5k_debug_finish_device(sc);
697 ath5k_detach(pdev, hw);
698 ath5k_hw_detach(sc->ah);
9adca126 699 kfree(sc->ah);
fa1c114f 700 free_irq(pdev->irq, sc);
fa1c114f
JS		 701 pci_iounmap(pdev, sc->iobase);
702 pci_release_region(pdev, 0);
703 pci_disable_device(pdev);
704 ieee80211_free_hw(hw);
705}
706
707#ifdef CONFIG_PM
baee1f3c 708static int ath5k_pci_suspend(struct device *dev)
fa1c114f 709{
baee1f3c 710 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
fa1c114f
JS		 711 struct ath5k_softc *sc = hw->priv;
712
3a078876 713 ath5k_led_off(sc);
fa1c114f
JS		 714 return 0;
715}
716
baee1f3c 717static int ath5k_pci_resume(struct device *dev)
fa1c114f 718{
baee1f3c 719 struct pci_dev *pdev = to_pci_dev(dev);
fa1c114f
JS		 720 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
721 struct ath5k_softc *sc = hw->priv;
fa1c114f 722
8451d22d
JM		 723 /*
724 * Suspend/Resume resets the PCI configuration space, so we have to
725 * re-disable the RETRY_TIMEOUT register (0x41) to keep
726 * PCI Tx retries from interfering with C3 CPU state
727 */
728 pci_write_config_byte(pdev, 0x41, 0);
729
3a078876 730 ath5k_led_enable(sc);
fa1c114f
JS		 731 return 0;
732}
733#endif /* CONFIG_PM */
734
735
fa1c114f
JS		 736/***********************\
737* Driver Initialization *
738\***********************/
739
f769c36b
BC		 740static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
741{
742 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
743 struct ath5k_softc *sc = hw->priv;
db719718 744 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
f769c36b 745
608b88cb 746 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 747}
748
fa1c114f
JS		 749static int
750ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
751{
752 struct ath5k_softc *sc = hw->priv;
753 struct ath5k_hw *ah = sc->ah;
db719718 754 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
0e149cf5 755 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 756 int ret;
757
758 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
759
760 /*
761 * Check if the MAC has multi-rate retry support.
762 * We do this by trying to setup a fake extended
763 * descriptor. MAC's that don't have support will
764 * return false w/o doing anything. MAC's that do
765 * support it will return true w/o doing anything.
766 */
c6e387a2 767 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 768 if (ret < 0)
769 goto err;
770 if (ret > 0)
fa1c114f
JS		 771 __set_bit(ATH_STAT_MRRETRY, sc->status);
772
fa1c114f
JS		 773 /*
774 * Collect the channel list. The 802.11 layer
775 * is resposible for filtering this list based
776 * on settings like the phy mode and regulatory
777 * domain restrictions.
778 */
63266a65 779 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 780 if (ret) {
781 ATH5K_ERR(sc, "can't get channels\n");
782 goto err;
783 }
784
785 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 786 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
787 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 788 else
d8ee398d 789 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 790
791 /*
792 * Allocate tx+rx descriptors and populate the lists.
793 */
794 ret = ath5k_desc_alloc(sc, pdev);
795 if (ret) {
796 ATH5K_ERR(sc, "can't allocate descriptors\n");
797 goto err;
798 }
799
800 /*
801 * Allocate hardware transmit queues: one queue for
802 * beacon frames and one data queue for each QoS
803 * priority. Note that hw functions handle reseting
804 * these queues at the needed time.
805 */
806 ret = ath5k_beaconq_setup(ah);
807 if (ret < 0) {
808 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
809 goto err_desc;
810 }
811 sc->bhalq = ret;
cec8db23
BC		 812 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
813 if (IS_ERR(sc->cabq)) {
814 ATH5K_ERR(sc, "can't setup cab queue\n");
815 ret = PTR_ERR(sc->cabq);
816 goto err_bhal;
817 }
fa1c114f
JS		 818
819 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
820 if (IS_ERR(sc->txq)) {
821 ATH5K_ERR(sc, "can't setup xmit queue\n");
822 ret = PTR_ERR(sc->txq);
cec8db23 823 goto err_queues;
fa1c114f
JS		 824 }
825
826 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
827 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
828 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
6e220662 829 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 830 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 831
0e149cf5
BC		 832 ret = ath5k_eeprom_read_mac(ah, mac);
833 if (ret) {
834 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
835 sc->pdev->device);
836 goto err_queues;
837 }
838
fa1c114f
JS		 839 SET_IEEE80211_PERM_ADDR(hw, mac);
840 /* All MAC address bits matter for ACKs */
17753748 841 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 842 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
843
608b88cb
LR		 844 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
845 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 846 if (ret) {
847 ATH5K_ERR(sc, "can't initialize regulatory system\n");
848 goto err_queues;
849 }
850
fa1c114f
JS		 851 ret = ieee80211_register_hw(hw);
852 if (ret) {
853 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
854 goto err_queues;
855 }
856
608b88cb
LR		 857 if (!ath_is_world_regd(regulatory))
858 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 859
3a078876
BC		 860 ath5k_init_leds(sc);
861
fa1c114f
JS		 862 return 0;
863err_queues:
864 ath5k_txq_release(sc);
865err_bhal:
866 ath5k_hw_release_tx_queue(ah, sc->bhalq);
867err_desc:
868 ath5k_desc_free(sc, pdev);
869err:
870 return ret;
871}
872
873static void
874ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
875{
876 struct ath5k_softc *sc = hw->priv;
877
878 /*
879 * NB: the order of these is important:
880 * o call the 802.11 layer before detaching ath5k_hw to
881 * insure callbacks into the driver to delete global
882 * key cache entries can be handled
883 * o reclaim the tx queue data structures after calling
884 * the 802.11 layer as we'll get called back to reclaim
885 * node state and potentially want to use them
886 * o to cleanup the tx queues the hal is called, so detach
887 * it last
888 * XXX: ??? detach ath5k_hw ???
889 * Other than that, it's straightforward...
890 */
891 ieee80211_unregister_hw(hw);
892 ath5k_desc_free(sc, pdev);
893 ath5k_txq_release(sc);
894 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 895 ath5k_unregister_leds(sc);
fa1c114f
JS		 896
897 /*
898 * NB: can't reclaim these until after ieee80211_ifdetach
899 * returns because we'll get called back to reclaim node
900 * state and potentially want to use them.
901 */
902}
903
904
905
906
907/********************\
908* Channel/mode setup *
909\********************/
910
911/*
912 * Convert IEEE channel number to MHz frequency.
913 */
914static inline short
915ath5k_ieee2mhz(short chan)
916{
917 if (chan <= 14 || chan >= 27)
918 return ieee80211chan2mhz(chan);
919 else
920 return 2212 + chan * 20;
921}
922
42639fcd
BC		 923/*
924 * Returns true for the channel numbers used without all_channels modparam.
925 */
926static bool ath5k_is_standard_channel(short chan)
927{
928 return ((chan <= 14) ||
929 /* UNII 1,2 */
930 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
931 /* midband */
932 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
933 /* UNII-3 */
934 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
935}
936
fa1c114f
JS		 937static unsigned int
938ath5k_copy_channels(struct ath5k_hw *ah,
939 struct ieee80211_channel *channels,
940 unsigned int mode,
941 unsigned int max)
942{
d8ee398d 943 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 944
945 if (!test_bit(mode, ah->ah_modes))
946 return 0;
947
fa1c114f 948 switch (mode) {
d8ee398d
LR		 949 case AR5K_MODE_11A:
950 case AR5K_MODE_11A_TURBO:
fa1c114f 951 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 952 size = 220 ;
fa1c114f
JS		 953 chfreq = CHANNEL_5GHZ;
954 break;
d8ee398d
LR		 955 case AR5K_MODE_11B:
956 case AR5K_MODE_11G:
957 case AR5K_MODE_11G_TURBO:
958 size = 26;
fa1c114f
JS		 959 chfreq = CHANNEL_2GHZ;
960 break;
961 default:
962 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
963 return 0;
964 }
965
966 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 967 ch = i + 1 ;
968 freq = ath5k_ieee2mhz(ch);
fa1c114f 969
d8ee398d
LR		 970 /* Check if channel is supported by the chipset */
971 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 972 continue;
973
42639fcd
BC		 974 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
975 continue;
976
d8ee398d
LR		 977 /* Write channel info and increment counter */
978 channels[count].center_freq = freq;
a3f4b914
LR		 979 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
980 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 981 switch (mode) {
982 case AR5K_MODE_11A:
983 case AR5K_MODE_11G:
984 channels[count].hw_value = chfreq | CHANNEL_OFDM;
985 break;
986 case AR5K_MODE_11A_TURBO:
987 case AR5K_MODE_11G_TURBO:
988 channels[count].hw_value = chfreq |
989 CHANNEL_OFDM | CHANNEL_TURBO;
990 break;
991 case AR5K_MODE_11B:
d8ee398d
LR		 992 channels[count].hw_value = CHANNEL_B;
993 }
fa1c114f 994
fa1c114f
JS		 995 count++;
996 max--;
997 }
998
999 return count;
1000}
1001
63266a65
BR		 1002static void
1003ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1004{
1005 u8 i;
1006
1007 for (i = 0; i < AR5K_MAX_RATES; i++)
1008 sc->rate_idx[b->band][i] = -1;
1009
1010 for (i = 0; i < b->n_bitrates; i++) {
1011 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1012 if (b->bitrates[i].hw_value_short)
1013 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1014 }
1015}
1016
d8ee398d 1017static int
63266a65 1018ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1019{
1020 struct ath5k_softc *sc = hw->priv;
d8ee398d 1021 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1022 struct ieee80211_supported_band *sband;
1023 int max_c, count_c = 0;
1024 int i;
fa1c114f 1025
d8ee398d 1026 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1027 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1028
1029 /* 2GHz band */
63266a65
BR		 1030 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1031 sband->band = IEEE80211_BAND_2GHZ;
1032 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1033
63266a65
BR		 1034 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1035 /* G mode */
1036 memcpy(sband->bitrates, &ath5k_rates[0],
1037 sizeof(struct ieee80211_rate) * 12);
1038 sband->n_bitrates = 12;
fa1c114f 1039
d8ee398d 1040 sband->channels = sc->channels;
d8ee398d 1041 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1042 AR5K_MODE_11G, max_c);
fa1c114f 1043
63266a65 1044 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1045 count_c = sband->n_channels;
63266a65
BR		 1046 max_c -= count_c;
1047 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1048 /* B mode */
1049 memcpy(sband->bitrates, &ath5k_rates[0],
1050 sizeof(struct ieee80211_rate) * 4);
1051 sband->n_bitrates = 4;
1052
1053 /* 5211 only supports B rates and uses 4bit rate codes
1054 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1055 * fix them up here:
1056 */
1057 if (ah->ah_version == AR5K_AR5211) {
1058 for (i = 0; i < 4; i++) {
1059 sband->bitrates[i].hw_value =
1060 sband->bitrates[i].hw_value & 0xF;
1061 sband->bitrates[i].hw_value_short =
1062 sband->bitrates[i].hw_value_short & 0xF;
1063 }
1064 }
fa1c114f 1065
63266a65
BR		 1066 sband->channels = sc->channels;
1067 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1068 AR5K_MODE_11B, max_c);
d8ee398d 1069
63266a65
BR		 1070 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1071 count_c = sband->n_channels;
d8ee398d 1072 max_c -= count_c;
fa1c114f 1073 }
63266a65 1074 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1075
63266a65 1076 /* 5GHz band, A mode */
400ec45a 1077 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1078 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1079 sband->band = IEEE80211_BAND_5GHZ;
1080 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1081
63266a65
BR		 1082 memcpy(sband->bitrates, &ath5k_rates[4],
1083 sizeof(struct ieee80211_rate) * 8);
1084 sband->n_bitrates = 8;
fa1c114f 1085
63266a65 1086 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1087 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1088 AR5K_MODE_11A, max_c);
1089
d8ee398d
LR		 1090 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1091 }
63266a65 1092 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1093
b446197c 1094 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1095
1096 return 0;
fa1c114f
JS		 1097}
1098
1099/*
e30eb4ab
JA		 1100 * Set/change channels. We always reset the chip.
1101 * To accomplish this we must first cleanup any pending DMA,
1102 * then restart stuff after a la ath5k_init.
be009370
BC		 1103 *
1104 * Called with sc->lock.
fa1c114f
JS		 1105 */
1106static int
1107ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1108{
d8ee398d
LR		 1109 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1110 sc->curchan->center_freq, chan->center_freq);
1111
e30eb4ab
JA		 1112 /*
1113 * To switch channels clear any pending DMA operations;
1114 * wait long enough for the RX fifo to drain, reset the
1115 * hardware at the new frequency, and then re-enable
1116 * the relevant bits of the h/w.
1117 */
1118 return ath5k_reset(sc, chan);
fa1c114f
JS		 1119}
1120
1121static void
1122ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1123{
fa1c114f 1124 sc->curmode = mode;
d8ee398d 1125
400ec45a 1126 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1127 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1128 } else {
1129 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1130 }
fa1c114f
JS		 1131}
1132
1133static void
1134ath5k_mode_setup(struct ath5k_softc *sc)
1135{
1136 struct ath5k_hw *ah = sc->ah;
1137 u32 rfilt;
1138
1139 /* configure rx filter */
1140 rfilt = sc->filter_flags;
1141 ath5k_hw_set_rx_filter(ah, rfilt);
1142
1143 if (ath5k_hw_hasbssidmask(ah))
1144 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1145
1146 /* configure operational mode */
ccfe5552 1147 ath5k_hw_set_opmode(ah, sc->opmode);
fa1c114f 1148
ccfe5552 1149 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
fa1c114f
JS		 1150 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1151}
1152
d8ee398d 1153static inline int
63266a65
BR		 1154ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1155{
b7266047
BC		 1156 int rix;
1157
1158 /* return base rate on errors */
1159 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1160 "hw_rix out of bounds: %x\n", hw_rix))
1161 return 0;
1162
1163 rix = sc->rate_idx[sc->curband->band][hw_rix];
1164 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1165 rix = 0;
1166
1167 return rix;
d8ee398d
LR		 1168}
1169
fa1c114f
JS		 1170/***************\
1171* Buffers setup *
1172\***************/
1173
b6ea0356
BC		 1174static
1175struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1176{
db719718 1177 struct ath_common *common = ath5k_hw_common(sc->ah);
b6ea0356 1178 struct sk_buff *skb;
b6ea0356
BC		 1179
1180 /*
1181 * Allocate buffer with headroom_needed space for the
1182 * fake physical layer header at the start.
1183 */
db719718 1184 skb = ath_rxbuf_alloc(common,
dd849782 1185 common->rx_bufsize,
aeb63cfd 1186 GFP_ATOMIC);
b6ea0356
BC		 1187
1188 if (!skb) {
1189 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
dd849782 1190 common->rx_bufsize);
b6ea0356
BC		 1191 return NULL;
1192 }
b6ea0356
BC		 1193
1194 *skb_addr = pci_map_single(sc->pdev,
cc861f74
LR		 1195 skb->data, common->rx_bufsize,
1196 PCI_DMA_FROMDEVICE);
b6ea0356
BC		 1197 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1198 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1199 dev_kfree_skb(skb);
1200 return NULL;
1201 }
1202 return skb;
1203}
1204
fa1c114f
JS		 1205static int
1206ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1207{
1208 struct ath5k_hw *ah = sc->ah;
1209 struct sk_buff *skb = bf->skb;
1210 struct ath5k_desc *ds;
1211
b6ea0356
BC		 1212 if (!skb) {
1213 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1214 if (!skb)
fa1c114f 1215 return -ENOMEM;
fa1c114f 1216 bf->skb = skb;
fa1c114f
JS		 1217 }
1218
1219 /*
1220 * Setup descriptors. For receive we always terminate
1221 * the descriptor list with a self-linked entry so we'll
1222 * not get overrun under high load (as can happen with a
1223 * 5212 when ANI processing enables PHY error frames).
1224 *
1225 * To insure the last descriptor is self-linked we create
1226 * each descriptor as self-linked and add it to the end. As
1227 * each additional descriptor is added the previous self-linked
1228 * entry is ``fixed'' naturally. This should be safe even
1229 * if DMA is happening. When processing RX interrupts we
1230 * never remove/process the last, self-linked, entry on the
1231 * descriptor list. This insures the hardware always has
1232 * someplace to write a new frame.
1233 */
1234 ds = bf->desc;
1235 ds->ds_link = bf->daddr; /* link to self */
1236 ds->ds_data = bf->skbaddr;
c6e387a2 1237 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1238 skb_tailroom(skb), /* buffer size */
1239 0);
1240
1241 if (sc->rxlink != NULL)
1242 *sc->rxlink = bf->daddr;
1243 sc->rxlink = &ds->ds_link;
1244 return 0;
1245}
1246
2ac2927a
BC		 1247static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1248{
1249 struct ieee80211_hdr *hdr;
1250 enum ath5k_pkt_type htype;
1251 __le16 fc;
1252
1253 hdr = (struct ieee80211_hdr *)skb->data;
1254 fc = hdr->frame_control;
1255
1256 if (ieee80211_is_beacon(fc))
1257 htype = AR5K_PKT_TYPE_BEACON;
1258 else if (ieee80211_is_probe_resp(fc))
1259 htype = AR5K_PKT_TYPE_PROBE_RESP;
1260 else if (ieee80211_is_atim(fc))
1261 htype = AR5K_PKT_TYPE_ATIM;
1262 else if (ieee80211_is_pspoll(fc))
1263 htype = AR5K_PKT_TYPE_PSPOLL;
1264 else
1265 htype = AR5K_PKT_TYPE_NORMAL;
1266
1267 return htype;
1268}
1269
fa1c114f 1270static int
cec8db23 1271ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
8127fbdc 1272 struct ath5k_txq *txq, int padsize)
fa1c114f
JS		 1273{
1274 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1275 struct ath5k_desc *ds = bf->desc;
1276 struct sk_buff *skb = bf->skb;
a888d52d 1277 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1278 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1279 struct ieee80211_rate *rate;
1280 unsigned int mrr_rate[3], mrr_tries[3];
1281 int i, ret;
8902ff4e 1282 u16 hw_rate;
07c1e852
BC		 1283 u16 cts_rate = 0;
1284 u16 duration = 0;
8902ff4e 1285 u8 rc_flags;
fa1c114f
JS		 1286
1287 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1288
fa1c114f
JS		 1289 /* XXX endianness */
1290 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1291 PCI_DMA_TODEVICE);
1292
8902ff4e
BC		 1293 rate = ieee80211_get_tx_rate(sc->hw, info);
1294
e039fa4a 1295 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1296 flags |= AR5K_TXDESC_NOACK;
1297
8902ff4e
BC		 1298 rc_flags = info->control.rates[0].flags;
1299 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1300 rate->hw_value_short : rate->hw_value;
1301
281c56dd 1302 pktlen = skb->len;
fa1c114f 1303
8f655dde
NK		 1304 /* FIXME: If we are in g mode and rate is a CCK rate
1305 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1306 * from tx power (value is in dB units already) */
362695e1
BC		 1307 if (info->control.hw_key) {
1308 keyidx = info->control.hw_key->hw_key_idx;
1309 pktlen += info->control.hw_key->icv_len;
1310 }
07c1e852
BC		 1311 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1312 flags |= AR5K_TXDESC_RTSENA;
1313 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1314 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1315 sc->vif, pktlen, info));
1316 }
1317 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1318 flags |= AR5K_TXDESC_CTSENA;
1319 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1320 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1321 sc->vif, pktlen, info));
1322 }
fa1c114f 1323 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
8127fbdc 1324 ieee80211_get_hdrlen_from_skb(skb), padsize,
2ac2927a 1325 get_hw_packet_type(skb),
2e92e6f2 1326 (sc->power_level * 2),
8902ff4e 1327 hw_rate,
2bed03eb 1328 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1329 cts_rate, duration);
fa1c114f
JS		 1330 if (ret)
1331 goto err_unmap;
1332
2f7fe870
FF		 1333 memset(mrr_rate, 0, sizeof(mrr_rate));
1334 memset(mrr_tries, 0, sizeof(mrr_tries));
1335 for (i = 0; i < 3; i++) {
1336 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1337 if (!rate)
1338 break;
1339
1340 mrr_rate[i] = rate->hw_value;
e6a9854b 1341 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1342 }
1343
1344 ah->ah_setup_mrr_tx_desc(ah, ds,
1345 mrr_rate[0], mrr_tries[0],
1346 mrr_rate[1], mrr_tries[1],
1347 mrr_rate[2], mrr_tries[2]);
1348
fa1c114f
JS		 1349 ds->ds_link = 0;
1350 ds->ds_data = bf->skbaddr;
1351
1352 spin_lock_bh(&txq->lock);
1353 list_add_tail(&bf->list, &txq->q);
fa1c114f 1354 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1355 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1356 else /* no, so only link it */
1357 *txq->link = bf->daddr;
1358
1359 txq->link = &ds->ds_link;
c6e387a2 1360 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1361 mmiowb();
fa1c114f
JS		 1362 spin_unlock_bh(&txq->lock);
1363
1364 return 0;
1365err_unmap:
1366 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1367 return ret;
1368}
1369
1370/*******************\
1371* Descriptors setup *
1372\*******************/
1373
1374static int
1375ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1376{
1377 struct ath5k_desc *ds;
1378 struct ath5k_buf *bf;
1379 dma_addr_t da;
1380 unsigned int i;
1381 int ret;
1382
1383 /* allocate descriptors */
1384 sc->desc_len = sizeof(struct ath5k_desc) *
1385 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1386 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1387 if (sc->desc == NULL) {
1388 ATH5K_ERR(sc, "can't allocate descriptors\n");
1389 ret = -ENOMEM;
1390 goto err;
1391 }
1392 ds = sc->desc;
1393 da = sc->desc_daddr;
1394 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1395 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1396
1397 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1398 sizeof(struct ath5k_buf), GFP_KERNEL);
1399 if (bf == NULL) {
1400 ATH5K_ERR(sc, "can't allocate bufptr\n");
1401 ret = -ENOMEM;
1402 goto err_free;
1403 }
1404 sc->bufptr = bf;
1405
1406 INIT_LIST_HEAD(&sc->rxbuf);
1407 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1408 bf->desc = ds;
1409 bf->daddr = da;
1410 list_add_tail(&bf->list, &sc->rxbuf);
1411 }
1412
1413 INIT_LIST_HEAD(&sc->txbuf);
1414 sc->txbuf_len = ATH_TXBUF;
1415 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1416 da += sizeof(*ds)) {
1417 bf->desc = ds;
1418 bf->daddr = da;
1419 list_add_tail(&bf->list, &sc->txbuf);
1420 }
1421
1422 /* beacon buffer */
1423 bf->desc = ds;
1424 bf->daddr = da;
1425 sc->bbuf = bf;
1426
1427 return 0;
1428err_free:
1429 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1430err:
1431 sc->desc = NULL;
1432 return ret;
1433}
1434
1435static void
1436ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1437{
1438 struct ath5k_buf *bf;
1439
1440 ath5k_txbuf_free(sc, sc->bbuf);
1441 list_for_each_entry(bf, &sc->txbuf, list)
1442 ath5k_txbuf_free(sc, bf);
1443 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1444 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1445
1446 /* Free memory associated with all descriptors */
1447 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1448
1449 kfree(sc->bufptr);
1450 sc->bufptr = NULL;
1451}
1452
1453
1454
1455
1456
1457/**************\
1458* Queues setup *
1459\**************/
1460
1461static struct ath5k_txq *
1462ath5k_txq_setup(struct ath5k_softc *sc,
1463 int qtype, int subtype)
1464{
1465 struct ath5k_hw *ah = sc->ah;
1466 struct ath5k_txq *txq;
1467 struct ath5k_txq_info qi = {
1468 .tqi_subtype = subtype,
1469 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1470 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1471 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1472 };
1473 int qnum;
1474
1475 /*
1476 * Enable interrupts only for EOL and DESC conditions.
1477 * We mark tx descriptors to receive a DESC interrupt
1478 * when a tx queue gets deep; otherwise waiting for the
1479 * EOL to reap descriptors. Note that this is done to
1480 * reduce interrupt load and this only defers reaping
1481 * descriptors, never transmitting frames. Aside from
1482 * reducing interrupts this also permits more concurrency.
1483 * The only potential downside is if the tx queue backs
1484 * up in which case the top half of the kernel may backup
1485 * due to a lack of tx descriptors.
1486 */
1487 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1488 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1489 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1490 if (qnum < 0) {
1491 /*
1492 * NB: don't print a message, this happens
1493 * normally on parts with too few tx queues
1494 */
1495 return ERR_PTR(qnum);
1496 }
1497 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1498 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1499 qnum, ARRAY_SIZE(sc->txqs));
1500 ath5k_hw_release_tx_queue(ah, qnum);
1501 return ERR_PTR(-EINVAL);
1502 }
1503 txq = &sc->txqs[qnum];
1504 if (!txq->setup) {
1505 txq->qnum = qnum;
1506 txq->link = NULL;
1507 INIT_LIST_HEAD(&txq->q);
1508 spin_lock_init(&txq->lock);
1509 txq->setup = true;
1510 }
1511 return &sc->txqs[qnum];
1512}
1513
1514static int
1515ath5k_beaconq_setup(struct ath5k_hw *ah)
1516{
1517 struct ath5k_txq_info qi = {
1518 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1519 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1520 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1521 /* NB: for dynamic turbo, don't enable any other interrupts */
1522 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1523 };
1524
1525 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1526}
1527
1528static int
1529ath5k_beaconq_config(struct ath5k_softc *sc)
1530{
1531 struct ath5k_hw *ah = sc->ah;
1532 struct ath5k_txq_info qi;
1533 int ret;
1534
1535 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1536 if (ret)
a951ae21
BC		 1537 goto err;
1538
05c914fe
JB		 1539 if (sc->opmode == NL80211_IFTYPE_AP ||
1540 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1541 /*
1542 * Always burst out beacon and CAB traffic
1543 * (aifs = cwmin = cwmax = 0)
1544 */
1545 qi.tqi_aifs = 0;
1546 qi.tqi_cw_min = 0;
1547 qi.tqi_cw_max = 0;
05c914fe 1548 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1549 /*
1550 * Adhoc mode; backoff between 0 and (2 * cw_min).
1551 */
1552 qi.tqi_aifs = 0;
1553 qi.tqi_cw_min = 0;
1554 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1555 }
1556
6d91e1d8
BR		 1557 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1558 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1559 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1560
c6e387a2 1561 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1562 if (ret) {
1563 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1564 "hardware queue!\n", __func__);
a951ae21 1565 goto err;
fa1c114f 1566 }
a951ae21
BC		 1567 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1568 if (ret)
1569 goto err;
fa1c114f 1570
a951ae21
BC		 1571 /* reconfigure cabq with ready time to 80% of beacon_interval */
1572 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1573 if (ret)
1574 goto err;
1575
1576 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1577 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1578 if (ret)
1579 goto err;
1580
1581 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1582err:
1583 return ret;
fa1c114f
JS		 1584}
1585
1586static void
1587ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1588{
1589 struct ath5k_buf *bf, *bf0;
1590
1591 /*
1592 * NB: this assumes output has been stopped and
1593 * we do not need to block ath5k_tx_tasklet
1594 */
1595 spin_lock_bh(&txq->lock);
1596 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1597 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1598
1599 ath5k_txbuf_free(sc, bf);
1600
1601 spin_lock_bh(&sc->txbuflock);
fa1c114f
JS		 1602 list_move_tail(&bf->list, &sc->txbuf);
1603 sc->txbuf_len++;
1604 spin_unlock_bh(&sc->txbuflock);
1605 }
1606 txq->link = NULL;
1607 spin_unlock_bh(&txq->lock);
1608}
1609
1610/*
1611 * Drain the transmit queues and reclaim resources.
1612 */
1613static void
1614ath5k_txq_cleanup(struct ath5k_softc *sc)
1615{
1616 struct ath5k_hw *ah = sc->ah;
1617 unsigned int i;
1618
1619 /* XXX return value */
1620 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1621 /* don't touch the hardware if marked invalid */
1622 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1623 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1624 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1625 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1626 if (sc->txqs[i].setup) {
1627 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1628 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1629 "link %p\n",
1630 sc->txqs[i].qnum,
c6e387a2 1631 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1632 sc->txqs[i].qnum),
1633 sc->txqs[i].link);
1634 }
1635 }
36d6825b 1636 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1637
1638 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1639 if (sc->txqs[i].setup)
1640 ath5k_txq_drainq(sc, &sc->txqs[i]);
1641}
1642
1643static void
1644ath5k_txq_release(struct ath5k_softc *sc)
1645{
1646 struct ath5k_txq *txq = sc->txqs;
1647 unsigned int i;
1648
1649 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1650 if (txq->setup) {
1651 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1652 txq->setup = false;
1653 }
1654}
1655
1656
1657
1658
1659/*************\
1660* RX Handling *
1661\*************/
1662
1663/*
1664 * Enable the receive h/w following a reset.
1665 */
1666static int
1667ath5k_rx_start(struct ath5k_softc *sc)
1668{
1669 struct ath5k_hw *ah = sc->ah;
db719718 1670 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 1671 struct ath5k_buf *bf;
1672 int ret;
1673
cc861f74 1674 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
fa1c114f 1675
cc861f74
LR		 1676 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1677 common->cachelsz, common->rx_bufsize);
fa1c114f 1678
fa1c114f 1679 spin_lock_bh(&sc->rxbuflock);
26925042 1680 sc->rxlink = NULL;
fa1c114f
JS		 1681 list_for_each_entry(bf, &sc->rxbuf, list) {
1682 ret = ath5k_rxbuf_setup(sc, bf);
1683 if (ret != 0) {
1684 spin_unlock_bh(&sc->rxbuflock);
1685 goto err;
1686 }
1687 }
1688 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1689 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1690 spin_unlock_bh(&sc->rxbuflock);
1691
c6e387a2 1692 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1693 ath5k_mode_setup(sc); /* set filters, etc. */
1694 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1695
1696 return 0;
1697err:
1698 return ret;
1699}
1700
1701/*
1702 * Disable the receive h/w in preparation for a reset.
1703 */
1704static void
1705ath5k_rx_stop(struct ath5k_softc *sc)
1706{
1707 struct ath5k_hw *ah = sc->ah;
1708
c6e387a2 1709 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1710 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1711 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1712
1713 ath5k_debug_printrxbuffs(sc, ah);
1714
1715 sc->rxlink = NULL; /* just in case */
1716}
1717
1718static unsigned int
1719ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1720 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f 1721{
dc1e001b
LR		 1722 struct ath5k_hw *ah = sc->ah;
1723 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1724 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1725 unsigned int keyix, hlen;
fa1c114f 1726
b47f407b
BR		 1727 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1728 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1729 return RX_FLAG_DECRYPTED;
1730
1731 /* Apparently when a default key is used to decrypt the packet
1732 the hw does not set the index used to decrypt. In such cases
1733 get the index from the packet. */
798ee985 1734 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1735 if (ieee80211_has_protected(hdr->frame_control) &&
1736 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1737 skb->len >= hlen + 4) {
fa1c114f
JS		 1738 keyix = skb->data[hlen + 3] >> 6;
1739
dc1e001b 1740 if (test_bit(keyix, common->keymap))
fa1c114f
JS		 1741 return RX_FLAG_DECRYPTED;
1742 }
1743
1744 return 0;
1745}
1746
036cd1ec
BR		 1747
1748static void
6ba81c2c
BR		 1749ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1750 struct ieee80211_rx_status *rxs)
036cd1ec 1751{
954fecea 1752 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1753 u64 tsf, bc_tstamp;
036cd1ec
BR		 1754 u32 hw_tu;
1755 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1756
24b56e70 1757 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1758 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1759 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1760 /*
6ba81c2c
BR		 1761 * Received an IBSS beacon with the same BSSID. Hardware *must*
1762 * have updated the local TSF. We have to work around various
1763 * hardware bugs, though...
036cd1ec 1764 */
6ba81c2c
BR		 1765 tsf = ath5k_hw_get_tsf64(sc->ah);
1766 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1767 hw_tu = TSF_TO_TU(tsf);
1768
1769 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1770 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1771 (unsigned long long)bc_tstamp,
1772 (unsigned long long)rxs->mactime,
1773 (unsigned long long)(rxs->mactime - bc_tstamp),
1774 (unsigned long long)tsf);
6ba81c2c
BR		 1775
1776 /*
1777 * Sometimes the HW will give us a wrong tstamp in the rx
1778 * status, causing the timestamp extension to go wrong.
1779 * (This seems to happen especially with beacon frames bigger
1780 * than 78 byte (incl. FCS))
1781 * But we know that the receive timestamp must be later than the
1782 * timestamp of the beacon since HW must have synced to that.
1783 *
1784 * NOTE: here we assume mactime to be after the frame was
1785 * received, not like mac80211 which defines it at the start.
1786 */
1787 if (bc_tstamp > rxs->mactime) {
036cd1ec 1788 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1789 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1790 (unsigned long long)rxs->mactime,
1791 (unsigned long long)tsf);
6ba81c2c 1792 rxs->mactime = tsf;
036cd1ec 1793 }
6ba81c2c
BR		 1794
1795 /*
1796 * Local TSF might have moved higher than our beacon timers,
1797 * in that case we have to update them to continue sending
1798 * beacons. This also takes care of synchronizing beacon sending
1799 * times with other stations.
1800 */
1801 if (hw_tu >= sc->nexttbtt)
1802 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1803 }
1804}
1805
8127fbdc
BP		 1806/*
1807 * Compute padding position. skb must contains an IEEE 802.11 frame
1808 */
1809static int ath5k_common_padpos(struct sk_buff *skb)
1810{
1811 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1812 __le16 frame_control = hdr->frame_control;
1813 int padpos = 24;
1814
1815 if (ieee80211_has_a4(frame_control)) {
1816 padpos += ETH_ALEN;
1817 }
1818 if (ieee80211_is_data_qos(frame_control)) {
1819 padpos += IEEE80211_QOS_CTL_LEN;
1820 }
1821
1822 return padpos;
1823}
1824
1825/*
1826 * This function expects a 802.11 frame and returns the number of
1827 * bytes added, or -1 if we don't have enought header room.
1828 */
1829
1830static int ath5k_add_padding(struct sk_buff *skb)
1831{
1832 int padpos = ath5k_common_padpos(skb);
1833 int padsize = padpos & 3;
1834
1835 if (padsize && skb->len>padpos) {
1836
1837 if (skb_headroom(skb) < padsize)
1838 return -1;
1839
1840 skb_push(skb, padsize);
1841 memmove(skb->data, skb->data+padsize, padpos);
1842 return padsize;
1843 }
1844
1845 return 0;
1846}
1847
1848/*
1849 * This function expects a 802.11 frame and returns the number of
1850 * bytes removed
1851 */
1852
1853static int ath5k_remove_padding(struct sk_buff *skb)
1854{
1855 int padpos = ath5k_common_padpos(skb);
1856 int padsize = padpos & 3;
1857
1858 if (padsize && skb->len>=padpos+padsize) {
1859 memmove(skb->data + padsize, skb->data, padpos);
1860 skb_pull(skb, padsize);
1861 return padsize;
1862 }
1863
1864 return 0;
1865}
1866
fa1c114f
JS		 1867static void
1868ath5k_tasklet_rx(unsigned long data)
1869{
1c5256bb 1870 struct ieee80211_rx_status *rxs;
b47f407b 1871 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1872 struct sk_buff *skb, *next_skb;
1873 dma_addr_t next_skb_addr;
fa1c114f 1874 struct ath5k_softc *sc = (void *)data;
cc861f74
LR		 1875 struct ath5k_hw *ah = sc->ah;
1876 struct ath_common *common = ath5k_hw_common(ah);
c57ca815 1877 struct ath5k_buf *bf;
fa1c114f 1878 struct ath5k_desc *ds;
fa1c114f 1879 int ret;
1c5256bb 1880 int rx_flag;
fa1c114f
JS		 1881
1882 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1883 if (list_empty(&sc->rxbuf)) {
1884 ATH5K_WARN(sc, "empty rx buf pool\n");
1885 goto unlock;
1886 }
fa1c114f 1887 do {
1c5256bb 1888 rx_flag = 0;
d6894b5b 1889
fa1c114f
JS		 1890 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1891 BUG_ON(bf->skb == NULL);
1892 skb = bf->skb;
1893 ds = bf->desc;
1894
c57ca815
BC		 1895 /* bail if HW is still using self-linked descriptor */
1896 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1897 break;
fa1c114f 1898
b47f407b 1899 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1900 if (unlikely(ret == -EINPROGRESS))
1901 break;
1902 else if (unlikely(ret)) {
1903 ATH5K_ERR(sc, "error in processing rx descriptor\n");
7644395f 1904 sc->stats.rxerr_proc++;
65872e6b 1905 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1906 return;
1907 }
1908
7644395f
BR		 1909 sc->stats.rx_all_count++;
1910
b47f407b 1911 if (unlikely(rs.rs_more)) {
fa1c114f 1912 ATH5K_WARN(sc, "unsupported jumbo\n");
7644395f 1913 sc->stats.rxerr_jumbo++;
fa1c114f
JS		 1914 goto next;
1915 }
1916
b47f407b 1917 if (unlikely(rs.rs_status)) {
7644395f
BR		 1918 if (rs.rs_status & AR5K_RXERR_CRC)
1919 sc->stats.rxerr_crc++;
1920 if (rs.rs_status & AR5K_RXERR_FIFO)
1921 sc->stats.rxerr_fifo++;
1922 if (rs.rs_status & AR5K_RXERR_PHY) {
1923 sc->stats.rxerr_phy++;
fa1c114f 1924 goto next;
7644395f 1925 }
b47f407b 1926 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1927 /*
1928 * Decrypt error. If the error occurred
1929 * because there was no hardware key, then
1930 * let the frame through so the upper layers
1931 * can process it. This is necessary for 5210
1932 * parts which have no way to setup a ``clear''
1933 * key cache entry.
1934 *
1935 * XXX do key cache faulting
1936 */
7644395f 1937 sc->stats.rxerr_decrypt++;
b47f407b
BR		 1938 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1939 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1940 goto accept;
1941 }
b47f407b 1942 if (rs.rs_status & AR5K_RXERR_MIC) {
1c5256bb 1943 rx_flag |= RX_FLAG_MMIC_ERROR;
7644395f 1944 sc->stats.rxerr_mic++;
fa1c114f
JS		 1945 goto accept;
1946 }
1947
1948 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1949 if ((rs.rs_status &
1950 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1951 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1952 goto next;
1953 }
1954accept:
b6ea0356
BC		 1955 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1956
1957 /*
1958 * If we can't replace bf->skb with a new skb under memory
1959 * pressure, just skip this packet
1960 */
1961 if (!next_skb)
1962 goto next;
1963
cc861f74 1964 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
fa1c114f 1965 PCI_DMA_FROMDEVICE);
b47f407b 1966 skb_put(skb, rs.rs_datalen);
fa1c114f 1967
0fe45b1d
BP		 1968 /* The MAC header is padded to have 32-bit boundary if the
1969 * packet payload is non-zero. The general calculation for
1970 * padsize would take into account odd header lengths:
1971 * padsize = (4 - hdrlen % 4) % 4; However, since only
1972 * even-length headers are used, padding can only be 0 or 2
1973 * bytes and we can optimize this a bit. In addition, we must
1974 * not try to remove padding from short control frames that do
1975 * not have payload. */
8127fbdc
BP		 1976 ath5k_remove_padding(skb);
1977
1c5256bb 1978 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 1979
c0e1899b
BR		 1980 /*
1981 * always extend the mac timestamp, since this information is
1982 * also needed for proper IBSS merging.
1983 *
1984 * XXX: it might be too late to do it here, since rs_tstamp is
1985 * 15bit only. that means TSF extension has to be done within
1986 * 32768usec (about 32ms). it might be necessary to move this to
1987 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1988 *
1989 * Unfortunately we don't know when the hardware takes the rx
1990 * timestamp (beginning of phy frame, data frame, end of rx?).
1991 * The only thing we know is that it is hardware specific...
1992 * On AR5213 it seems the rx timestamp is at the end of the
1993 * frame, but i'm not sure.
1994 *
1995 * NOTE: mac80211 defines mactime at the beginning of the first
1996 * data symbol. Since we don't have any time references it's
1997 * impossible to comply to that. This affects IBSS merge only
1998 * right now, so it's not too bad...
c0e1899b 1999 */
1c5256bb
BC		 2000 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2001 rxs->flag = rx_flag | RX_FLAG_TSFT;
c0e1899b 2002
1c5256bb
BC		 2003 rxs->freq = sc->curchan->center_freq;
2004 rxs->band = sc->curband->band;
fa1c114f 2005
1c5256bb
BC		 2006 rxs->noise = sc->ah->ah_noise_floor;
2007 rxs->signal = rxs->noise + rs.rs_rssi;
6e0e0bf8 2008
1c5256bb 2009 rxs->antenna = rs.rs_antenna;
604eeadd
BR		 2010
2011 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2012 sc->stats.antenna_rx[rs.rs_antenna]++;
2013 else
2014 sc->stats.antenna_rx[0]++; /* invalid */
2015
1c5256bb
BC		 2016 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2017 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 2018
1c5256bb
BC		 2019 if (rxs->rate_idx >= 0 && rs.rs_rate ==
2020 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2021 rxs->flag |= RX_FLAG_SHORTPRE;
06303352 2022
fa1c114f
JS		 2023 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
2024
036cd1ec 2025 /* check beacons in IBSS mode */
05c914fe 2026 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1c5256bb 2027 ath5k_check_ibss_tsf(sc, skb, rxs);
036cd1ec 2028
f1d58c25 2029 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 2030
2031 bf->skb = next_skb;
2032 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 2033next:
2034 list_move_tail(&bf->list, &sc->rxbuf);
2035 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 2036unlock:
fa1c114f
JS		 2037 spin_unlock(&sc->rxbuflock);
2038}
2039
2040
2041
2042
2043/*************\
2044* TX Handling *
2045\*************/
2046
2047static void
2048ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2049{
b47f407b 2050 struct ath5k_tx_status ts = {};
fa1c114f
JS		 2051 struct ath5k_buf *bf, *bf0;
2052 struct ath5k_desc *ds;
2053 struct sk_buff *skb;
e039fa4a 2054 struct ieee80211_tx_info *info;
2f7fe870 2055 int i, ret;
fa1c114f
JS		 2056
2057 spin_lock(&txq->lock);
2058 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2059 ds = bf->desc;
2060
b47f407b 2061 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 2062 if (unlikely(ret == -EINPROGRESS))
2063 break;
2064 else if (unlikely(ret)) {
2065 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2066 ret, txq->qnum);
2067 break;
2068 }
2069
7644395f 2070 sc->stats.tx_all_count++;
fa1c114f 2071 skb = bf->skb;
a888d52d 2072 info = IEEE80211_SKB_CB(skb);
fa1c114f 2073 bf->skb = NULL;
e039fa4a 2074
fa1c114f
JS		 2075 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2076 PCI_DMA_TODEVICE);
2077
e6a9854b 2078 ieee80211_tx_info_clear_status(info);
2f7fe870 2079 for (i = 0; i < 4; i++) {
e6a9854b
JB		 2080 struct ieee80211_tx_rate *r =
2081 &info->status.rates[i];
2f7fe870
FF		 2082
2083 if (ts.ts_rate[i]) {
e6a9854b
JB		 2084 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2085 r->count = ts.ts_retry[i];
2f7fe870 2086 } else {
e6a9854b
JB		 2087 r->idx = -1;
2088 r->count = 0;
2f7fe870
FF		 2089 }
2090 }
2091
e6a9854b
JB		 2092 /* count the successful attempt as well */
2093 info->status.rates[ts.ts_final_idx].count++;
2094
b47f407b 2095 if (unlikely(ts.ts_status)) {
fa1c114f 2096 sc->ll_stats.dot11ACKFailureCount++;
7644395f 2097 if (ts.ts_status & AR5K_TXERR_FILT) {
e039fa4a 2098 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
7644395f
BR		 2099 sc->stats.txerr_filt++;
2100 }
2101 if (ts.ts_status & AR5K_TXERR_XRETRY)
2102 sc->stats.txerr_retry++;
2103 if (ts.ts_status & AR5K_TXERR_FIFO)
2104 sc->stats.txerr_fifo++;
fa1c114f 2105 } else {
e039fa4a
JB		 2106 info->flags |= IEEE80211_TX_STAT_ACK;
2107 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2108 }
2109
8127fbdc
BP		 2110 /*
2111 * Remove MAC header padding before giving the frame
2112 * back to mac80211.
2113 */
2114 ath5k_remove_padding(skb);
2115
604eeadd
BR		 2116 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2117 sc->stats.antenna_tx[ts.ts_antenna]++;
2118 else
2119 sc->stats.antenna_tx[0]++; /* invalid */
2120
e039fa4a 2121 ieee80211_tx_status(sc->hw, skb);
fa1c114f
JS		 2122
2123 spin_lock(&sc->txbuflock);
fa1c114f
JS		 2124 list_move_tail(&bf->list, &sc->txbuf);
2125 sc->txbuf_len++;
2126 spin_unlock(&sc->txbuflock);
2127 }
2128 if (likely(list_empty(&txq->q)))
2129 txq->link = NULL;
2130 spin_unlock(&txq->lock);
2131 if (sc->txbuf_len > ATH_TXBUF / 5)
2132 ieee80211_wake_queues(sc->hw);
2133}
2134
2135static void
2136ath5k_tasklet_tx(unsigned long data)
2137{
8784d2ee 2138 int i;
fa1c114f
JS		 2139 struct ath5k_softc *sc = (void *)data;
2140
8784d2ee
BC		 2141 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2142 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2143 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2144}
2145
2146
fa1c114f
JS		 2147/*****************\
2148* Beacon handling *
2149\*****************/
2150
2151/*
2152 * Setup the beacon frame for transmit.
2153 */
2154static int
e039fa4a 2155ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2156{
2157 struct sk_buff *skb = bf->skb;
a888d52d 2158 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2159 struct ath5k_hw *ah = sc->ah;
2160 struct ath5k_desc *ds;
2bed03eb
NK		 2161 int ret = 0;
2162 u8 antenna;
fa1c114f 2163 u32 flags;
8127fbdc 2164 const int padsize = 0;
fa1c114f
JS		 2165
2166 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2167 PCI_DMA_TODEVICE);
2168 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2169 "skbaddr %llx\n", skb, skb->data, skb->len,
2170 (unsigned long long)bf->skbaddr);
8d8bb39b 2171 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2172 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2173 return -EIO;
2174 }
2175
2176 ds = bf->desc;
2bed03eb 2177 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2178
2179 flags = AR5K_TXDESC_NOACK;
05c914fe 2180 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2181 ds->ds_link = bf->daddr; /* self-linked */
2182 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2183 } else
fa1c114f 2184 ds->ds_link = 0;
2bed03eb
NK		 2185
2186 /*
2187 * If we use multiple antennas on AP and use
2188 * the Sectored AP scenario, switch antenna every
2189 * 4 beacons to make sure everybody hears our AP.
2190 * When a client tries to associate, hw will keep
2191 * track of the tx antenna to be used for this client
2192 * automaticaly, based on ACKed packets.
2193 *
2194 * Note: AP still listens and transmits RTS on the
2195 * default antenna which is supposed to be an omni.
2196 *
2197 * Note2: On sectored scenarios it's possible to have
2198 * multiple antennas (1omni -the default- and 14 sectors)
2199 * so if we choose to actually support this mode we need
2200 * to allow user to set how many antennas we have and tweak
2201 * the code below to send beacons on all of them.
2202 */
2203 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2204 antenna = sc->bsent & 4 ? 2 : 1;
2205
fa1c114f 2206
8f655dde
NK		 2207 /* FIXME: If we are in g mode and rate is a CCK rate
2208 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2209 * from tx power (value is in dB units already) */
fa1c114f 2210 ds->ds_data = bf->skbaddr;
281c56dd 2211 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 2212 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 2213 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2214 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2215 1, AR5K_TXKEYIX_INVALID,
400ec45a 2216 antenna, flags, 0, 0);
fa1c114f
JS		 2217 if (ret)
2218 goto err_unmap;
2219
2220 return 0;
2221err_unmap:
2222 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2223 return ret;
2224}
2225
2226/*
2227 * Transmit a beacon frame at SWBA. Dynamic updates to the
2228 * frame contents are done as needed and the slot time is
2229 * also adjusted based on current state.
2230 *
acf3c1a5
BC		 2231 * This is called from software irq context (beacontq or restq
2232 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2233 */
2234static void
2235ath5k_beacon_send(struct ath5k_softc *sc)
2236{
2237 struct ath5k_buf *bf = sc->bbuf;
2238 struct ath5k_hw *ah = sc->ah;
cec8db23 2239 struct sk_buff *skb;
fa1c114f 2240
be9b7259 2241 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2242
05c914fe
JB		 2243 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2244 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2245 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2246 return;
2247 }
2248 /*
2249 * Check if the previous beacon has gone out. If
2250 * not don't don't try to post another, skip this
2251 * period and wait for the next. Missed beacons
2252 * indicate a problem and should not occur. If we
2253 * miss too many consecutive beacons reset the device.
2254 */
2255 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2256 sc->bmisscount++;
be9b7259 2257 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2258 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2259 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2260 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2261 "stuck beacon time (%u missed)\n",
2262 sc->bmisscount);
2263 tasklet_schedule(&sc->restq);
2264 }
2265 return;
2266 }
2267 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2268 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2269 "resume beacon xmit after %u misses\n",
2270 sc->bmisscount);
2271 sc->bmisscount = 0;
2272 }
2273
2274 /*
2275 * Stop any current dma and put the new frame on the queue.
2276 * This should never fail since we check above that no frames
2277 * are still pending on the queue.
2278 */
2279 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2280 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2281 /* NB: hw still stops DMA, so proceed */
2282 }
fa1c114f 2283
1071db86
BC		 2284 /* refresh the beacon for AP mode */
2285 if (sc->opmode == NL80211_IFTYPE_AP)
2286 ath5k_beacon_update(sc->hw, sc->vif);
2287
c6e387a2
NK		 2288 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2289 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2290 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2291 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2292
cec8db23
BC		 2293 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2294 while (skb) {
2295 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2296 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2297 }
2298
fa1c114f
JS		 2299 sc->bsent++;
2300}
2301
2302
9804b98d
BR		 2303/**
2304 * ath5k_beacon_update_timers - update beacon timers
2305 *
2306 * @sc: struct ath5k_softc pointer we are operating on
2307 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2308 * beacon timer update based on the current HW TSF.
2309 *
2310 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2311 * of a received beacon or the current local hardware TSF and write it to the
2312 * beacon timer registers.
2313 *
2314 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2315 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2316 * when we otherwise know we have to update the timers, but we keep it in this
2317 * function to have it all together in one place.
2318 */
fa1c114f 2319static void
9804b98d 2320ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2321{
2322 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2323 u32 nexttbtt, intval, hw_tu, bc_tu;
2324 u64 hw_tsf;
fa1c114f
JS		 2325
2326 intval = sc->bintval & AR5K_BEACON_PERIOD;
2327 if (WARN_ON(!intval))
2328 return;
2329
9804b98d
BR		 2330 /* beacon TSF converted to TU */
2331 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2332
9804b98d
BR		 2333 /* current TSF converted to TU */
2334 hw_tsf = ath5k_hw_get_tsf64(ah);
2335 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2336
9804b98d
BR		 2337#define FUDGE 3
2338 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2339 if (bc_tsf == -1) {
2340 /*
2341 * no beacons received, called internally.
2342 * just need to refresh timers based on HW TSF.
2343 */
2344 nexttbtt = roundup(hw_tu + FUDGE, intval);
2345 } else if (bc_tsf == 0) {
2346 /*
2347 * no beacon received, probably called by ath5k_reset_tsf().
2348 * reset TSF to start with 0.
2349 */
2350 nexttbtt = intval;
2351 intval |= AR5K_BEACON_RESET_TSF;
2352 } else if (bc_tsf > hw_tsf) {
2353 /*
2354 * beacon received, SW merge happend but HW TSF not yet updated.
2355 * not possible to reconfigure timers yet, but next time we
2356 * receive a beacon with the same BSSID, the hardware will
2357 * automatically update the TSF and then we need to reconfigure
2358 * the timers.
2359 */
2360 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2361 "need to wait for HW TSF sync\n");
2362 return;
2363 } else {
2364 /*
2365 * most important case for beacon synchronization between STA.
2366 *
2367 * beacon received and HW TSF has been already updated by HW.
2368 * update next TBTT based on the TSF of the beacon, but make
2369 * sure it is ahead of our local TSF timer.
2370 */
2371 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2372 }
2373#undef FUDGE
fa1c114f 2374
036cd1ec
BR		 2375 sc->nexttbtt = nexttbtt;
2376
fa1c114f 2377 intval |= AR5K_BEACON_ENA;
fa1c114f 2378 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2379
2380 /*
2381 * debugging output last in order to preserve the time critical aspect
2382 * of this function
2383 */
2384 if (bc_tsf == -1)
2385 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2386 "reconfigured timers based on HW TSF\n");
2387 else if (bc_tsf == 0)
2388 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2389 "reset HW TSF and timers\n");
2390 else
2391 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2392 "updated timers based on beacon TSF\n");
2393
2394 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2395 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2396 (unsigned long long) bc_tsf,
2397 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2398 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2399 intval & AR5K_BEACON_PERIOD,
2400 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2401 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2402}
2403
2404
036cd1ec
BR		 2405/**
2406 * ath5k_beacon_config - Configure the beacon queues and interrupts
2407 *
2408 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2409 *
036cd1ec 2410 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2411 * interrupts to detect TSF updates only.
fa1c114f
JS		 2412 */
2413static void
2414ath5k_beacon_config(struct ath5k_softc *sc)
2415{
2416 struct ath5k_hw *ah = sc->ah;
b5f03956 2417 unsigned long flags;
fa1c114f 2418
21800491 2419 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2420 sc->bmisscount = 0;
dc1968e7 2421 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2422
21800491 2423 if (sc->enable_beacon) {
fa1c114f 2424 /*
036cd1ec
BR		 2425 * In IBSS mode we use a self-linked tx descriptor and let the
2426 * hardware send the beacons automatically. We have to load it
fa1c114f 2427 * only once here.
036cd1ec 2428 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2429 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2430 */
2431 ath5k_beaconq_config(sc);
fa1c114f 2432
036cd1ec
BR		 2433 sc->imask |= AR5K_INT_SWBA;
2434
da966bca 2435 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2436 if (ath5k_hw_hasveol(ah))
da966bca 2437 ath5k_beacon_send(sc);
da966bca
JS		 2438 } else
2439 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2440 } else {
2441 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2442 }
fa1c114f 2443
c6e387a2 2444 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2445 mmiowb();
2446 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2447}
2448
428cbd4f
NK		 2449static void ath5k_tasklet_beacon(unsigned long data)
2450{
2451 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2452
2453 /*
2454 * Software beacon alert--time to send a beacon.
2455 *
2456 * In IBSS mode we use this interrupt just to
2457 * keep track of the next TBTT (target beacon
2458 * transmission time) in order to detect wether
2459 * automatic TSF updates happened.
2460 */
2461 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2462 /* XXX: only if VEOL suppported */
2463 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2464 sc->nexttbtt += sc->bintval;
2465 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2466 "SWBA nexttbtt: %x hw_tu: %x "
2467 "TSF: %llx\n",
2468 sc->nexttbtt,
2469 TSF_TO_TU(tsf),
2470 (unsigned long long) tsf);
2471 } else {
2472 spin_lock(&sc->block);
2473 ath5k_beacon_send(sc);
2474 spin_unlock(&sc->block);
2475 }
2476}
2477
fa1c114f
JS		 2478
2479/********************\
2480* Interrupt handling *
2481\********************/
2482
2483static int
bb2becac 2484ath5k_init(struct ath5k_softc *sc)
fa1c114f 2485{
bc1b32d6
EO		 2486 struct ath5k_hw *ah = sc->ah;
2487 int ret, i;
fa1c114f
JS		 2488
2489 mutex_lock(&sc->lock);
2490
2491 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2492
2493 /*
2494 * Stop anything previously setup. This is safe
2495 * no matter this is the first time through or not.
2496 */
2497 ath5k_stop_locked(sc);
2498
2499 /*
2500 * The basic interface to setting the hardware in a good
2501 * state is ``reset''. On return the hardware is known to
2502 * be powered up and with interrupts disabled. This must
2503 * be followed by initialization of the appropriate bits
2504 * and then setup of the interrupt mask.
2505 */
d8ee398d
LR		 2506 sc->curchan = sc->hw->conf.channel;
2507 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2508 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2509 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
6e220662 2510 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
209d889b 2511 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2512 if (ret)
2513 goto done;
fa1c114f 2514
e6a3b616
TD		 2515 ath5k_rfkill_hw_start(ah);
2516
bc1b32d6
EO		 2517 /*
2518 * Reset the key cache since some parts do not reset the
2519 * contents on initial power up or resume from suspend.
2520 */
2521 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2522 ath5k_hw_reset_key(ah, i);
2523
fa1c114f 2524 /* Set ack to be sent at low bit-rates */
bc1b32d6 2525 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2526 ret = 0;
2527done:
274c7c36 2528 mmiowb();
fa1c114f
JS		 2529 mutex_unlock(&sc->lock);
2530 return ret;
2531}
2532
2533static int
2534ath5k_stop_locked(struct ath5k_softc *sc)
2535{
2536 struct ath5k_hw *ah = sc->ah;
2537
2538 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2539 test_bit(ATH_STAT_INVALID, sc->status));
2540
2541 /*
2542 * Shutdown the hardware and driver:
2543 * stop output from above
2544 * disable interrupts
2545 * turn off timers
2546 * turn off the radio
2547 * clear transmit machinery
2548 * clear receive machinery
2549 * drain and release tx queues
2550 * reclaim beacon resources
2551 * power down hardware
2552 *
2553 * Note that some of this work is not possible if the
2554 * hardware is gone (invalid).
2555 */
2556 ieee80211_stop_queues(sc->hw);
2557
2558 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2559 ath5k_led_off(sc);
c6e387a2 2560 ath5k_hw_set_imr(ah, 0);
274c7c36 2561 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2562 }
2563 ath5k_txq_cleanup(sc);
2564 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2565 ath5k_rx_stop(sc);
2566 ath5k_hw_phy_disable(ah);
2567 } else
2568 sc->rxlink = NULL;
2569
2570 return 0;
2571}
2572
2573/*
2574 * Stop the device, grabbing the top-level lock to protect
2575 * against concurrent entry through ath5k_init (which can happen
2576 * if another thread does a system call and the thread doing the
2577 * stop is preempted).
2578 */
2579static int
bb2becac 2580ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2581{
2582 int ret;
2583
2584 mutex_lock(&sc->lock);
2585 ret = ath5k_stop_locked(sc);
2586 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2587 /*
edd7fc70
NK		 2588 * Don't set the card in full sleep mode!
2589 *
2590 * a) When the device is in this state it must be carefully
2591 * woken up or references to registers in the PCI clock
2592 * domain may freeze the bus (and system). This varies
2593 * by chip and is mostly an issue with newer parts
2594 * (madwifi sources mentioned srev >= 0x78) that go to
2595 * sleep more quickly.
2596 *
2597 * b) On older chips full sleep results a weird behaviour
2598 * during wakeup. I tested various cards with srev < 0x78
2599 * and they don't wake up after module reload, a second
2600 * module reload is needed to bring the card up again.
2601 *
2602 * Until we figure out what's going on don't enable
2603 * full chip reset on any chip (this is what Legacy HAL
2604 * and Sam's HAL do anyway). Instead Perform a full reset
2605 * on the device (same as initial state after attach) and
2606 * leave it idle (keep MAC/BB on warm reset) */
2607 ret = ath5k_hw_on_hold(sc->ah);
2608
2609 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2610 "putting device to sleep\n");
fa1c114f
JS		 2611 }
2612 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2613
274c7c36 2614 mmiowb();
fa1c114f
JS		 2615 mutex_unlock(&sc->lock);
2616
10488f8a
JS		 2617 tasklet_kill(&sc->rxtq);
2618 tasklet_kill(&sc->txtq);
2619 tasklet_kill(&sc->restq);
6e220662 2620 tasklet_kill(&sc->calib);
acf3c1a5 2621 tasklet_kill(&sc->beacontq);
fa1c114f 2622
e6a3b616
TD		 2623 ath5k_rfkill_hw_stop(sc->ah);
2624
fa1c114f
JS		 2625 return ret;
2626}
2627
2628static irqreturn_t
2629ath5k_intr(int irq, void *dev_id)
2630{
2631 struct ath5k_softc *sc = dev_id;
2632 struct ath5k_hw *ah = sc->ah;
2633 enum ath5k_int status;
2634 unsigned int counter = 1000;
2635
2636 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2637 !ath5k_hw_is_intr_pending(ah)))
2638 return IRQ_NONE;
2639
2640 do {
fa1c114f
JS		 2641 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2642 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2643 status, sc->imask);
fa1c114f
JS		 2644 if (unlikely(status & AR5K_INT_FATAL)) {
2645 /*
2646 * Fatal errors are unrecoverable.
2647 * Typically these are caused by DMA errors.
2648 */
2649 tasklet_schedule(&sc->restq);
2650 } else if (unlikely(status & AR5K_INT_RXORN)) {
2651 tasklet_schedule(&sc->restq);
2652 } else {
2653 if (status & AR5K_INT_SWBA) {
56d2ac76 2654 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2655 }
2656 if (status & AR5K_INT_RXEOL) {
2657 /*
2658 * NB: the hardware should re-read the link when
2659 * RXE bit is written, but it doesn't work at
2660 * least on older hardware revs.
2661 */
2662 sc->rxlink = NULL;
2663 }
2664 if (status & AR5K_INT_TXURN) {
2665 /* bump tx trigger level */
2666 ath5k_hw_update_tx_triglevel(ah, true);
2667 }
4c674c60 2668 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2669 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2670 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2671 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2672 tasklet_schedule(&sc->txtq);
2673 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2674 /* TODO */
fa1c114f 2675 }
6e220662
NK		 2676 if (status & AR5K_INT_SWI) {
2677 tasklet_schedule(&sc->calib);
2678 }
fa1c114f 2679 if (status & AR5K_INT_MIB) {
194828a2
NK		 2680 /*
2681 * These stats are also used for ANI i think
2682 * so how about updating them more often ?
2683 */
2684 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f 2685 }
e6a3b616 2686 if (status & AR5K_INT_GPIO)
e6a3b616 2687 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2688
fa1c114f 2689 }
2516baa6 2690 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2691
2692 if (unlikely(!counter))
2693 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2694
6e220662
NK		 2695 ath5k_hw_calibration_poll(ah);
2696
fa1c114f
JS		 2697 return IRQ_HANDLED;
2698}
2699
2700static void
2701ath5k_tasklet_reset(unsigned long data)
2702{
2703 struct ath5k_softc *sc = (void *)data;
2704
d7dc1003 2705 ath5k_reset_wake(sc);
fa1c114f
JS		 2706}
2707
2708/*
2709 * Periodically recalibrate the PHY to account
2710 * for temperature/environment changes.
2711 */
2712static void
6e220662 2713ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2714{
2715 struct ath5k_softc *sc = (void *)data;
2716 struct ath5k_hw *ah = sc->ah;
2717
6e220662
NK		 2718 /* Only full calibration for now */
2719 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2720 return;
2721
2722 /* Stop queues so that calibration
2723 * doesn't interfere with tx */
2724 ieee80211_stop_queues(sc->hw);
2725
fa1c114f 2726 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2727 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2728 sc->curchan->hw_value);
fa1c114f 2729
6f3b414a 2730 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2731 /*
2732 * Rfgain is out of bounds, reset the chip
2733 * to load new gain values.
2734 */
2735 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2736 ath5k_reset_wake(sc);
fa1c114f
JS		 2737 }
2738 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2739 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2740 ieee80211_frequency_to_channel(
2741 sc->curchan->center_freq));
fa1c114f 2742
6e220662
NK		 2743 ah->ah_swi_mask = 0;
2744
2745 /* Wake queues */
2746 ieee80211_wake_queues(sc->hw);
2747
fa1c114f
JS		 2748}
2749
2750
fa1c114f
JS		 2751/********************\
2752* Mac80211 functions *
2753\********************/
2754
2755static int
e039fa4a 2756ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2757{
2758 struct ath5k_softc *sc = hw->priv;
2759
2760 return ath5k_tx_queue(hw, skb, sc->txq);
2761}
2762
2763static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2764 struct ath5k_txq *txq)
fa1c114f
JS		 2765{
2766 struct ath5k_softc *sc = hw->priv;
2767 struct ath5k_buf *bf;
2768 unsigned long flags;
0fe45b1d 2769 int padsize;
fa1c114f
JS		 2770
2771 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2772
05c914fe 2773 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2774 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2775
2776 /*
2777 * the hardware expects the header padded to 4 byte boundaries
2778 * if this is not the case we add the padding after the header
2779 */
8127fbdc
BP		 2780 padsize = ath5k_add_padding(skb);
2781 if (padsize < 0) {
2782 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2783 " headroom to pad");
2784 goto drop_packet;
fa1c114f
JS		 2785 }
2786
fa1c114f
JS		 2787 spin_lock_irqsave(&sc->txbuflock, flags);
2788 if (list_empty(&sc->txbuf)) {
2789 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2790 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2791 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2792 goto drop_packet;
fa1c114f
JS		 2793 }
2794 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2795 list_del(&bf->list);
2796 sc->txbuf_len--;
2797 if (list_empty(&sc->txbuf))
2798 ieee80211_stop_queues(hw);
2799 spin_unlock_irqrestore(&sc->txbuflock, flags);
2800
2801 bf->skb = skb;
2802
8127fbdc 2803 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
fa1c114f
JS		 2804 bf->skb = NULL;
2805 spin_lock_irqsave(&sc->txbuflock, flags);
2806 list_add_tail(&bf->list, &sc->txbuf);
2807 sc->txbuf_len++;
2808 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2809 goto drop_packet;
fa1c114f 2810 }
5a0fe8ac 2811 return NETDEV_TX_OK;
fa1c114f 2812
5a0fe8ac
BC		 2813drop_packet:
2814 dev_kfree_skb_any(skb);
71ef99c8 2815 return NETDEV_TX_OK;
fa1c114f
JS		 2816}
2817
209d889b
BC		 2818/*
2819 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2820 * and change to the given channel.
2821 */
fa1c114f 2822static int
209d889b 2823ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2824{
fa1c114f
JS		 2825 struct ath5k_hw *ah = sc->ah;
2826 int ret;
2827
2828 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2829
209d889b 2830 if (chan) {
c6e387a2 2831 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2832 ath5k_txq_cleanup(sc);
2833 ath5k_rx_stop(sc);
209d889b
BC		 2834
2835 sc->curchan = chan;
2836 sc->curband = &sc->sbands[chan->band];
d7dc1003 2837 }
3355443a 2838 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2839 if (ret) {
fa1c114f
JS		 2840 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2841 goto err;
2842 }
d7dc1003 2843
fa1c114f 2844 ret = ath5k_rx_start(sc);
d7dc1003 2845 if (ret) {
fa1c114f
JS		 2846 ATH5K_ERR(sc, "can't start recv logic\n");
2847 goto err;
2848 }
d7dc1003 2849
fa1c114f 2850 /*
d7dc1003
JS		 2851 * Change channels and update the h/w rate map if we're switching;
2852 * e.g. 11a to 11b/g.
2853 *
2854 * We may be doing a reset in response to an ioctl that changes the
2855 * channel so update any state that might change as a result.
fa1c114f
JS		 2856 *
2857 * XXX needed?
2858 */
2859/* ath5k_chan_change(sc, c); */
fa1c114f 2860
d7dc1003
JS		 2861 ath5k_beacon_config(sc);
2862 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2863
2864 return 0;
2865err:
2866 return ret;
2867}
2868
d7dc1003
JS		 2869static int
2870ath5k_reset_wake(struct ath5k_softc *sc)
2871{
2872 int ret;
2873
209d889b 2874 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2875 if (!ret)
2876 ieee80211_wake_queues(sc->hw);
2877
2878 return ret;
2879}
2880
fa1c114f
JS		 2881static int ath5k_start(struct ieee80211_hw *hw)
2882{
bb2becac 2883 return ath5k_init(hw->priv);
fa1c114f
JS		 2884}
2885
2886static void ath5k_stop(struct ieee80211_hw *hw)
2887{
bb2becac 2888 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2889}
2890
2891static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2892 struct ieee80211_vif *vif)
fa1c114f
JS		 2893{
2894 struct ath5k_softc *sc = hw->priv;
2895 int ret;
2896
2897 mutex_lock(&sc->lock);
32bfd35d 2898 if (sc->vif) {
fa1c114f
JS		 2899 ret = 0;
2900 goto end;
2901 }
2902
1ed32e4f 2903 sc->vif = vif;
fa1c114f 2904
1ed32e4f 2905 switch (vif->type) {
da966bca 2906 case NL80211_IFTYPE_AP:
05c914fe
JB		 2907 case NL80211_IFTYPE_STATION:
2908 case NL80211_IFTYPE_ADHOC:
b706e65b 2909 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2910 case NL80211_IFTYPE_MONITOR:
1ed32e4f 2911 sc->opmode = vif->type;
fa1c114f
JS		 2912 break;
2913 default:
2914 ret = -EOPNOTSUPP;
2915 goto end;
2916 }
67d2e2df 2917
ccfe5552
BR		 2918 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2919
1ed32e4f 2920 ath5k_hw_set_lladdr(sc->ah, vif->addr);
ae6f53f2 2921 ath5k_mode_setup(sc);
67d2e2df 2922
fa1c114f
JS		 2923 ret = 0;
2924end:
2925 mutex_unlock(&sc->lock);
2926 return ret;
2927}
2928
2929static void
2930ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 2931 struct ieee80211_vif *vif)
fa1c114f
JS		 2932{
2933 struct ath5k_softc *sc = hw->priv;
0e149cf5 2934 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2935
2936 mutex_lock(&sc->lock);
1ed32e4f 2937 if (sc->vif != vif)
fa1c114f
JS		 2938 goto end;
2939
0e149cf5 2940 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2941 sc->vif = NULL;
fa1c114f
JS		 2942end:
2943 mutex_unlock(&sc->lock);
2944}
2945
d8ee398d
LR		 2946/*
2947 * TODO: Phy disable/diversity etc
2948 */
fa1c114f 2949static int
e8975581 2950ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2951{
2952 struct ath5k_softc *sc = hw->priv;
a0823810 2953 struct ath5k_hw *ah = sc->ah;
e8975581 2954 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 2955 int ret = 0;
be009370
BC		 2956
2957 mutex_lock(&sc->lock);
fa1c114f 2958
e30eb4ab
JA		 2959 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2960 ret = ath5k_chan_set(sc, conf->channel);
2961 if (ret < 0)
2962 goto unlock;
2963 }
2bed03eb 2964
a0823810
NK		 2965 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2966 (sc->power_level != conf->power_level)) {
2967 sc->power_level = conf->power_level;
2968
2969 /* Half dB steps */
2970 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2971 }
fa1c114f 2972
2bed03eb
NK		 2973 /* TODO:
2974 * 1) Move this on config_interface and handle each case
2975 * separately eg. when we have only one STA vif, use
2976 * AR5K_ANTMODE_SINGLE_AP
2977 *
2978 * 2) Allow the user to change antenna mode eg. when only
2979 * one antenna is present
2980 *
2981 * 3) Allow the user to set default/tx antenna when possible
2982 *
2983 * 4) Default mode should handle 90% of the cases, together
2984 * with fixed a/b and single AP modes we should be able to
2985 * handle 99%. Sectored modes are extreme cases and i still
2986 * haven't found a usage for them. If we decide to support them,
2987 * then we must allow the user to set how many tx antennas we
2988 * have available
2989 */
caec9112 2990 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 2991
55aa4e0f 2992unlock:
be009370 2993 mutex_unlock(&sc->lock);
55aa4e0f 2994 return ret;
fa1c114f
JS		 2995}
2996
3ac64bee
JB		 2997static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2998 int mc_count, struct dev_addr_list *mclist)
2999{
3000 u32 mfilt[2], val;
3001 int i;
3002 u8 pos;
3003
3004 mfilt[0] = 0;
3005 mfilt[1] = 1;
3006
3007 for (i = 0; i < mc_count; i++) {
3008 if (!mclist)
3009 break;
3010 /* calculate XOR of eight 6-bit values */
3011 val = get_unaligned_le32(mclist->dmi_addr + 0);
3012 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3013 val = get_unaligned_le32(mclist->dmi_addr + 3);
3014 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3015 pos &= 0x3f;
3016 mfilt[pos / 32] |= (1 << (pos % 32));
3017 /* XXX: we might be able to just do this instead,
3018 * but not sure, needs testing, if we do use this we'd
3019 * neet to inform below to not reset the mcast */
3020 /* ath5k_hw_set_mcast_filterindex(ah,
3021 * mclist->dmi_addr[5]); */
3022 mclist = mclist->next;
3023 }
3024
3025 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3026}
3027
fa1c114f
JS		 3028#define SUPPORTED_FIF_FLAGS \
3029 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3030 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3031 FIF_BCN_PRBRESP_PROMISC
3032/*
3033 * o always accept unicast, broadcast, and multicast traffic
3034 * o multicast traffic for all BSSIDs will be enabled if mac80211
3035 * says it should be
3036 * o maintain current state of phy ofdm or phy cck error reception.
3037 * If the hardware detects any of these type of errors then
3038 * ath5k_hw_get_rx_filter() will pass to us the respective
3039 * hardware filters to be able to receive these type of frames.
3040 * o probe request frames are accepted only when operating in
3041 * hostap, adhoc, or monitor modes
3042 * o enable promiscuous mode according to the interface state
3043 * o accept beacons:
3044 * - when operating in adhoc mode so the 802.11 layer creates
3045 * node table entries for peers,
3046 * - when operating in station mode for collecting rssi data when
3047 * the station is otherwise quiet, or
3048 * - when scanning
3049 */
3050static void ath5k_configure_filter(struct ieee80211_hw *hw,
3051 unsigned int changed_flags,
3052 unsigned int *new_flags,
3ac64bee 3053 u64 multicast)
fa1c114f
JS		 3054{
3055 struct ath5k_softc *sc = hw->priv;
3056 struct ath5k_hw *ah = sc->ah;
3ac64bee 3057 u32 mfilt[2], rfilt;
fa1c114f 3058
56d1de0a
BC		 3059 mutex_lock(&sc->lock);
3060
3ac64bee
JB		 3061 mfilt[0] = multicast;
3062 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3063
3064 /* Only deal with supported flags */
3065 changed_flags &= SUPPORTED_FIF_FLAGS;
3066 *new_flags &= SUPPORTED_FIF_FLAGS;
3067
3068 /* If HW detects any phy or radar errors, leave those filters on.
3069 * Also, always enable Unicast, Broadcasts and Multicast
3070 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3071 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3072 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3073 AR5K_RX_FILTER_MCAST);
3074
3075 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3076 if (*new_flags & FIF_PROMISC_IN_BSS) {
3077 rfilt |= AR5K_RX_FILTER_PROM;
3078 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3079 } else {
fa1c114f 3080 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3081 }
fa1c114f
JS		 3082 }
3083
3084 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3085 if (*new_flags & FIF_ALLMULTI) {
3086 mfilt[0] = ~0;
3087 mfilt[1] = ~0;
fa1c114f
JS		 3088 }
3089
3090 /* This is the best we can do */
3091 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3092 rfilt |= AR5K_RX_FILTER_PHYERR;
3093
3094 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3095 * and probes for any BSSID, this needs testing */
3096 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3097 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3098
3099 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3100 * set we should only pass on control frames for this
3101 * station. This needs testing. I believe right now this
3102 * enables *all* control frames, which is OK.. but
3103 * but we should see if we can improve on granularity */
3104 if (*new_flags & FIF_CONTROL)
3105 rfilt |= AR5K_RX_FILTER_CONTROL;
3106
3107 /* Additional settings per mode -- this is per ath5k */
3108
3109 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3110
56d1de0a
BC		 3111 switch (sc->opmode) {
3112 case NL80211_IFTYPE_MESH_POINT:
3113 case NL80211_IFTYPE_MONITOR:
3114 rfilt |= AR5K_RX_FILTER_CONTROL |
3115 AR5K_RX_FILTER_BEACON |
3116 AR5K_RX_FILTER_PROBEREQ |
3117 AR5K_RX_FILTER_PROM;
3118 break;
3119 case NL80211_IFTYPE_AP:
3120 case NL80211_IFTYPE_ADHOC:
3121 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3122 AR5K_RX_FILTER_BEACON;
3123 break;
3124 case NL80211_IFTYPE_STATION:
3125 if (sc->assoc)
3126 rfilt |= AR5K_RX_FILTER_BEACON;
3127 default:
3128 break;
3129 }
fa1c114f
JS		 3130
3131 /* Set filters */
0bbac08f 3132 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3133
3134 /* Set multicast bits */
3135 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3136 /* Set the cached hw filter flags, this will alter actually
3137 * be set in HW */
3138 sc->filter_flags = rfilt;
56d1de0a
BC		 3139
3140 mutex_unlock(&sc->lock);
fa1c114f
JS		 3141}
3142
3143static int
3144ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3145 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3146 struct ieee80211_key_conf *key)
fa1c114f
JS		 3147{
3148 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3149 struct ath5k_hw *ah = sc->ah;
3150 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3151 int ret = 0;
3152
9ad9a26e
BC		 3153 if (modparam_nohwcrypt)
3154 return -EOPNOTSUPP;
3155
65b5a698
BC		 3156 if (sc->opmode == NL80211_IFTYPE_AP)
3157 return -EOPNOTSUPP;
3158
0bbac08f 3159 switch (key->alg) {
fa1c114f 3160 case ALG_WEP:
fa1c114f 3161 case ALG_TKIP:
3f64b435 3162 break;
fa1c114f 3163 case ALG_CCMP:
1c818740
BC		 3164 if (sc->ah->ah_aes_support)
3165 break;
3166
fa1c114f
JS		 3167 return -EOPNOTSUPP;
3168 default:
3169 WARN_ON(1);
3170 return -EINVAL;
3171 }
3172
3173 mutex_lock(&sc->lock);
3174
3175 switch (cmd) {
3176 case SET_KEY:
dc822b5d
JB		 3177 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3178 sta ? sta->addr : NULL);
fa1c114f
JS		 3179 if (ret) {
3180 ATH5K_ERR(sc, "can't set the key\n");
3181 goto unlock;
3182 }
dc1e001b 3183 __set_bit(key->keyidx, common->keymap);
fa1c114f 3184 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3185 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3186 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3187 break;
3188 case DISABLE_KEY:
3189 ath5k_hw_reset_key(sc->ah, key->keyidx);
dc1e001b 3190 __clear_bit(key->keyidx, common->keymap);
fa1c114f
JS		 3191 break;
3192 default:
3193 ret = -EINVAL;
3194 goto unlock;
3195 }
3196
3197unlock:
274c7c36 3198 mmiowb();
fa1c114f
JS		 3199 mutex_unlock(&sc->lock);
3200 return ret;
3201}
3202
3203static int
3204ath5k_get_stats(struct ieee80211_hw *hw,
3205 struct ieee80211_low_level_stats *stats)
3206{
3207 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3208 struct ath5k_hw *ah = sc->ah;
3209
3210 /* Force update */
3211 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3212
3213 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3214
3215 return 0;
3216}
3217
fa1c114f
JS		 3218static u64
3219ath5k_get_tsf(struct ieee80211_hw *hw)
3220{
3221 struct ath5k_softc *sc = hw->priv;
3222
3223 return ath5k_hw_get_tsf64(sc->ah);
3224}
3225
3b5d665b
AF		 3226static void
3227ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3228{
3229 struct ath5k_softc *sc = hw->priv;
3230
3231 ath5k_hw_set_tsf64(sc->ah, tsf);
3232}
3233
fa1c114f
JS		 3234static void
3235ath5k_reset_tsf(struct ieee80211_hw *hw)
3236{
3237 struct ath5k_softc *sc = hw->priv;
3238
9804b98d
BR		 3239 /*
3240 * in IBSS mode we need to update the beacon timers too.
3241 * this will also reset the TSF if we call it with 0
3242 */
05c914fe 3243 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3244 ath5k_beacon_update_timers(sc, 0);
3245 else
3246 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3247}
3248
1071db86
BC		 3249/*
3250 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3251 * this is called only once at config_bss time, for AP we do it every
3252 * SWBA interrupt so that the TIM will reflect buffered frames.
3253 *
3254 * Called with the beacon lock.
3255 */
fa1c114f 3256static int
1071db86 3257ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3258{
fa1c114f 3259 int ret;
1071db86 3260 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3261 struct sk_buff *skb;
3262
3263 if (WARN_ON(!vif)) {
3264 ret = -EINVAL;
3265 goto out;
3266 }
3267
3268 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3269
3270 if (!skb) {
3271 ret = -ENOMEM;
3272 goto out;
3273 }
fa1c114f
JS		 3274
3275 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3276
fa1c114f
JS		 3277 ath5k_txbuf_free(sc, sc->bbuf);
3278 sc->bbuf->skb = skb;
e039fa4a 3279 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3280 if (ret)
3281 sc->bbuf->skb = NULL;
1071db86
BC		 3282out:
3283 return ret;
3284}
3285
02969b38
MX		 3286static void
3287set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3288{
3289 struct ath5k_softc *sc = hw->priv;
3290 struct ath5k_hw *ah = sc->ah;
3291 u32 rfilt;
3292 rfilt = ath5k_hw_get_rx_filter(ah);
3293 if (enable)
3294 rfilt |= AR5K_RX_FILTER_BEACON;
3295 else
3296 rfilt &= ~AR5K_RX_FILTER_BEACON;
3297 ath5k_hw_set_rx_filter(ah, rfilt);
3298 sc->filter_flags = rfilt;
3299}
fa1c114f 3300
02969b38
MX		 3301static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3302 struct ieee80211_vif *vif,
3303 struct ieee80211_bss_conf *bss_conf,
3304 u32 changes)
3305{
3306 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3307 struct ath5k_hw *ah = sc->ah;
954fecea 3308 struct ath_common *common = ath5k_hw_common(ah);
21800491 3309 unsigned long flags;
2d0ddec5
JB		 3310
3311 mutex_lock(&sc->lock);
3312 if (WARN_ON(sc->vif != vif))
3313 goto unlock;
3314
3315 if (changes & BSS_CHANGED_BSSID) {
3316 /* Cache for later use during resets */
954fecea 3317 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
8ce54c5a 3318 common->curaid = 0;
be5d6b75 3319 ath5k_hw_set_associd(ah);
2d0ddec5
JB		 3320 mmiowb();
3321 }
57c4d7b4
JB		 3322
3323 if (changes & BSS_CHANGED_BEACON_INT)
3324 sc->bintval = bss_conf->beacon_int;
3325
02969b38 3326 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3327 sc->assoc = bss_conf->assoc;
3328 if (sc->opmode == NL80211_IFTYPE_STATION)
3329 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3330 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3331 AR5K_LED_ASSOC : AR5K_LED_INIT);
8ce54c5a
LR		 3332 if (bss_conf->assoc) {
3333 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3334 "Bss Info ASSOC %d, bssid: %pM\n",
3335 bss_conf->aid, common->curbssid);
3336 common->curaid = bss_conf->aid;
3337 ath5k_hw_set_associd(ah);
3338 /* Once ANI is available you would start it here */
3339 }
02969b38 3340 }
2d0ddec5 3341
21800491
BC		 3342 if (changes & BSS_CHANGED_BEACON) {
3343 spin_lock_irqsave(&sc->block, flags);
3344 ath5k_beacon_update(hw, vif);
3345 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3346 }
3347
21800491
BC		 3348 if (changes & BSS_CHANGED_BEACON_ENABLED)
3349 sc->enable_beacon = bss_conf->enable_beacon;
3350
3351 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3352 BSS_CHANGED_BEACON_INT))
3353 ath5k_beacon_config(sc);
3354
2d0ddec5
JB		 3355 unlock:
3356 mutex_unlock(&sc->lock);
02969b38 3357}
f0f3d388
BC		 3358
3359static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3360{
3361 struct ath5k_softc *sc = hw->priv;
3362 if (!sc->assoc)
3363 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3364}
3365
3366static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3367{
3368 struct ath5k_softc *sc = hw->priv;
3369 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3370 AR5K_LED_ASSOC : AR5K_LED_INIT);
3371}
6e08d228
LT		 3372
3373/**
3374 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3375 *
3376 * @hw: struct ieee80211_hw pointer
3377 * @coverage_class: IEEE 802.11 coverage class number
3378 *
3379 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3380 * coverage class. The values are persistent, they are restored after device
3381 * reset.
3382 */
3383static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3384{
3385 struct ath5k_softc *sc = hw->priv;
3386
3387 mutex_lock(&sc->lock);
3388 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3389 mutex_unlock(&sc->lock);
3390}
Clone of davem's net-next-2.6 tree