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ath5k: print more errors when decriptor setup fails
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
5a0e3ad6 53#include <linux/slab.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
9ad9a26e 64static int modparam_nohwcrypt;
46802a4f 65module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 66MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 67
42639fcd 68static int modparam_all_channels;
46802a4f 69module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 70MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
71
fa1c114f
JS		 72
73/******************\
74* Internal defines *
75\******************/
76
77/* Module info */
78MODULE_AUTHOR("Jiri Slaby");
79MODULE_AUTHOR("Nick Kossifidis");
80MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
81MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
82MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 83MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 84
85
86/* Known PCI ids */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 106 { 0 }
107};
108MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
109
110/* Known SREVs */
2c91108c 111static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148};
149
2c91108c 150static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 /* XR missing */
190};
191
fa1c114f
JS		 192/*
193 * Prototypes - PCI stack related functions
194 */
195static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
196 const struct pci_device_id *id);
197static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
e307139d 198#ifdef CONFIG_PM_SLEEP
baee1f3c
RW		 199static int ath5k_pci_suspend(struct device *dev);
200static int ath5k_pci_resume(struct device *dev);
201
626ede6b 202static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
baee1f3c 203#define ATH5K_PM_OPS (&ath5k_pm_ops)
fa1c114f 204#else
baee1f3c 205#define ATH5K_PM_OPS NULL
e307139d 206#endif /* CONFIG_PM_SLEEP */
fa1c114f 207
04a9e451 208static struct pci_driver ath5k_pci_driver = {
9764f3f9 209 .name = KBUILD_MODNAME,
fa1c114f
JS		 210 .id_table = ath5k_pci_id_table,
211 .probe = ath5k_pci_probe,
212 .remove = __devexit_p(ath5k_pci_remove),
baee1f3c 213 .driver.pm = ATH5K_PM_OPS,
fa1c114f
JS		 214};
215
216
217
218/*
219 * Prototypes - MAC 802.11 stack related functions
220 */
e039fa4a 221static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
cec8db23
BC		 222static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
223 struct ath5k_txq *txq);
209d889b 224static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
fa1c114f
JS		 225static int ath5k_start(struct ieee80211_hw *hw);
226static void ath5k_stop(struct ieee80211_hw *hw);
227static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 228 struct ieee80211_vif *vif);
fa1c114f 229static void ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 230 struct ieee80211_vif *vif);
e8975581 231static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
3ac64bee 232static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 233 struct netdev_hw_addr_list *mc_list);
fa1c114f
JS		 234static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
3ac64bee 237 u64 multicast);
fa1c114f
JS		 238static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
dc822b5d 240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 241 struct ieee80211_key_conf *key);
242static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
55ee82b5
HS		 244static int ath5k_get_survey(struct ieee80211_hw *hw,
245 int idx, struct survey_info *survey);
fa1c114f 246static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 247static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 248static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 249static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
02969b38
MX		 251static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
254 u32 changes);
f0f3d388
BC		 255static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
6e08d228
LT		 257static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
258 u8 coverage_class);
fa1c114f 259
2c91108c 260static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 261 .tx = ath5k_tx,
262 .start = ath5k_start,
263 .stop = ath5k_stop,
264 .add_interface = ath5k_add_interface,
265 .remove_interface = ath5k_remove_interface,
266 .config = ath5k_config,
3ac64bee 267 .prepare_multicast = ath5k_prepare_multicast,
fa1c114f
JS		 268 .configure_filter = ath5k_configure_filter,
269 .set_key = ath5k_set_key,
270 .get_stats = ath5k_get_stats,
55ee82b5 271 .get_survey = ath5k_get_survey,
fa1c114f 272 .conf_tx = NULL,
fa1c114f 273 .get_tsf = ath5k_get_tsf,
3b5d665b 274 .set_tsf = ath5k_set_tsf,
fa1c114f 275 .reset_tsf = ath5k_reset_tsf,
02969b38 276 .bss_info_changed = ath5k_bss_info_changed,
f0f3d388
BC		 277 .sw_scan_start = ath5k_sw_scan_start,
278 .sw_scan_complete = ath5k_sw_scan_complete,
6e08d228 279 .set_coverage_class = ath5k_set_coverage_class,
fa1c114f
JS		 280};
281
282/*
283 * Prototypes - Internal functions
284 */
285/* Attach detach */
286static int ath5k_attach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288static void ath5k_detach(struct pci_dev *pdev,
289 struct ieee80211_hw *hw);
290/* Channel/mode setup */
291static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 292static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
293 struct ieee80211_channel *channels,
294 unsigned int mode,
295 unsigned int max);
63266a65 296static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 297static int ath5k_chan_set(struct ath5k_softc *sc,
298 struct ieee80211_channel *chan);
299static void ath5k_setcurmode(struct ath5k_softc *sc,
300 unsigned int mode);
301static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 302
fa1c114f
JS		 303/* Descriptor setup */
304static int ath5k_desc_alloc(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
306static void ath5k_desc_free(struct ath5k_softc *sc,
307 struct pci_dev *pdev);
308/* Buffers setup */
309static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
310 struct ath5k_buf *bf);
311static int ath5k_txbuf_setup(struct ath5k_softc *sc,
cec8db23 312 struct ath5k_buf *bf,
8127fbdc 313 struct ath5k_txq *txq, int padsize);
9e4e43f2
BR		 314
315static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 316 struct ath5k_buf *bf)
317{
318 BUG_ON(!bf);
319 if (!bf->skb)
320 return;
321 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
322 PCI_DMA_TODEVICE);
00482973 323 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 324 bf->skb = NULL;
325}
326
9e4e43f2 327static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 328 struct ath5k_buf *bf)
329{
cc861f74
LR		 330 struct ath5k_hw *ah = sc->ah;
331 struct ath_common *common = ath5k_hw_common(ah);
332
a6c8d375
FF		 333 BUG_ON(!bf);
334 if (!bf->skb)
335 return;
cc861f74 336 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 337 PCI_DMA_FROMDEVICE);
338 dev_kfree_skb_any(bf->skb);
339 bf->skb = NULL;
340}
341
342
fa1c114f
JS		 343/* Queues setup */
344static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
345 int qtype, int subtype);
346static int ath5k_beaconq_setup(struct ath5k_hw *ah);
347static int ath5k_beaconq_config(struct ath5k_softc *sc);
348static void ath5k_txq_drainq(struct ath5k_softc *sc,
349 struct ath5k_txq *txq);
350static void ath5k_txq_cleanup(struct ath5k_softc *sc);
351static void ath5k_txq_release(struct ath5k_softc *sc);
352/* Rx handling */
353static int ath5k_rx_start(struct ath5k_softc *sc);
354static void ath5k_rx_stop(struct ath5k_softc *sc);
355static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
356 struct ath5k_desc *ds,
b47f407b
BR		 357 struct sk_buff *skb,
358 struct ath5k_rx_status *rs);
fa1c114f
JS		 359static void ath5k_tasklet_rx(unsigned long data);
360/* Tx handling */
361static void ath5k_tx_processq(struct ath5k_softc *sc,
362 struct ath5k_txq *txq);
363static void ath5k_tasklet_tx(unsigned long data);
364/* Beacon handling */
365static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 366 struct ath5k_buf *bf);
fa1c114f
JS		 367static void ath5k_beacon_send(struct ath5k_softc *sc);
368static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 369static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 370static void ath5k_tasklet_beacon(unsigned long data);
2111ac0d 371static void ath5k_tasklet_ani(unsigned long data);
fa1c114f
JS		 372
373static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
374{
375 u64 tsf = ath5k_hw_get_tsf64(ah);
376
377 if ((tsf & 0x7fff) < rstamp)
378 tsf -= 0x8000;
379
380 return (tsf & ~0x7fff) | rstamp;
381}
382
383/* Interrupt handling */
bb2becac 384static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 385static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 386static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 387static irqreturn_t ath5k_intr(int irq, void *dev_id);
388static void ath5k_tasklet_reset(unsigned long data);
389
6e220662 390static void ath5k_tasklet_calibrate(unsigned long data);
fa1c114f
JS		 391
392/*
393 * Module init/exit functions
394 */
395static int __init
396init_ath5k_pci(void)
397{
398 int ret;
399
400 ath5k_debug_init();
401
04a9e451 402 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 403 if (ret) {
404 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
405 return ret;
406 }
407
408 return 0;
409}
410
411static void __exit
412exit_ath5k_pci(void)
413{
04a9e451 414 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 415
416 ath5k_debug_finish();
417}
418
419module_init(init_ath5k_pci);
420module_exit(exit_ath5k_pci);
421
422
423/********************\
424* PCI Initialization *
425\********************/
426
427static const char *
428ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
429{
430 const char *name = "xxxxx";
431 unsigned int i;
432
433 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
434 if (srev_names[i].sr_type != type)
435 continue;
75d0edb8
NK		 436
437 if ((val & 0xf0) == srev_names[i].sr_val)
438 name = srev_names[i].sr_name;
439
440 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 441 name = srev_names[i].sr_name;
442 break;
443 }
444 }
445
446 return name;
447}
e5aa8474
LR		 448static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
449{
450 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
451 return ath5k_hw_reg_read(ah, reg_offset);
452}
453
454static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
455{
456 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
457 ath5k_hw_reg_write(ah, val, reg_offset);
458}
459
460static const struct ath_ops ath5k_common_ops = {
461 .read = ath5k_ioread32,
462 .write = ath5k_iowrite32,
463};
fa1c114f
JS		 464
465static int __devinit
466ath5k_pci_probe(struct pci_dev *pdev,
467 const struct pci_device_id *id)
468{
469 void __iomem *mem;
470 struct ath5k_softc *sc;
db719718 471 struct ath_common *common;
fa1c114f
JS		 472 struct ieee80211_hw *hw;
473 int ret;
474 u8 csz;
475
476 ret = pci_enable_device(pdev);
477 if (ret) {
478 dev_err(&pdev->dev, "can't enable device\n");
479 goto err;
480 }
481
482 /* XXX 32-bit addressing only */
284901a9 483 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 484 if (ret) {
485 dev_err(&pdev->dev, "32-bit DMA not available\n");
486 goto err_dis;
487 }
488
489 /*
490 * Cache line size is used to size and align various
491 * structures used to communicate with the hardware.
492 */
493 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
494 if (csz == 0) {
495 /*
496 * Linux 2.4.18 (at least) writes the cache line size
497 * register as a 16-bit wide register which is wrong.
498 * We must have this setup properly for rx buffer
499 * DMA to work so force a reasonable value here if it
500 * comes up zero.
501 */
13311b00 502 csz = L1_CACHE_BYTES >> 2;
fa1c114f
JS		 503 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
504 }
505 /*
506 * The default setting of latency timer yields poor results,
507 * set it to the value used by other systems. It may be worth
508 * tweaking this setting more.
509 */
510 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
511
512 /* Enable bus mastering */
513 pci_set_master(pdev);
514
515 /*
516 * Disable the RETRY_TIMEOUT register (0x41) to keep
517 * PCI Tx retries from interfering with C3 CPU state.
518 */
519 pci_write_config_byte(pdev, 0x41, 0);
520
521 ret = pci_request_region(pdev, 0, "ath5k");
522 if (ret) {
523 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
524 goto err_dis;
525 }
526
527 mem = pci_iomap(pdev, 0, 0);
528 if (!mem) {
529 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
530 ret = -EIO;
531 goto err_reg;
532 }
533
534 /*
535 * Allocate hw (mac80211 main struct)
536 * and hw->priv (driver private data)
537 */
538 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
539 if (hw == NULL) {
540 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
541 ret = -ENOMEM;
542 goto err_map;
543 }
544
545 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
546
547 /* Initialize driver private data */
548 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a 549 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
cec8db23 550 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
f5c044e5 551 IEEE80211_HW_SIGNAL_DBM;
f59ac048
LR		 552
553 hw->wiphy->interface_modes =
6f5f39c9 554 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 555 BIT(NL80211_IFTYPE_STATION) |
556 BIT(NL80211_IFTYPE_ADHOC) |
557 BIT(NL80211_IFTYPE_MESH_POINT);
558
fa1c114f
JS		 559 hw->extra_tx_headroom = 2;
560 hw->channel_change_time = 5000;
fa1c114f
JS		 561 sc = hw->priv;
562 sc->hw = hw;
563 sc->pdev = pdev;
564
565 ath5k_debug_init_device(sc);
566
567 /*
568 * Mark the device as detached to avoid processing
569 * interrupts until setup is complete.
570 */
571 __set_bit(ATH_STAT_INVALID, sc->status);
572
573 sc->iobase = mem; /* So we can unmap it on detach */
05c914fe 574 sc->opmode = NL80211_IFTYPE_STATION;
eab0cd49 575 sc->bintval = 1000;
fa1c114f
JS		 576 mutex_init(&sc->lock);
577 spin_lock_init(&sc->rxbuflock);
578 spin_lock_init(&sc->txbuflock);
00482973 579 spin_lock_init(&sc->block);
fa1c114f
JS		 580
581 /* Set private data */
6673e2e8 582 pci_set_drvdata(pdev, sc);
fa1c114f 583
fa1c114f
JS		 584 /* Setup interrupt handler */
585 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
586 if (ret) {
587 ATH5K_ERR(sc, "request_irq failed\n");
588 goto err_free;
589 }
590
9adca126
LR		 591 /*If we passed the test malloc a ath5k_hw struct*/
592 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
593 if (!sc->ah) {
594 ret = -ENOMEM;
595 ATH5K_ERR(sc, "out of memory\n");
fa1c114f
JS		 596 goto err_irq;
597 }
598
9adca126
LR		 599 sc->ah->ah_sc = sc;
600 sc->ah->ah_iobase = sc->iobase;
db719718 601 common = ath5k_hw_common(sc->ah);
e5aa8474 602 common->ops = &ath5k_common_ops;
13b81559 603 common->ah = sc->ah;
b002a4a9 604 common->hw = hw;
db719718
LR		 605 common->cachelsz = csz << 2; /* convert to bytes */
606
9adca126
LR		 607 /* Initialize device */
608 ret = ath5k_hw_attach(sc);
609 if (ret) {
610 goto err_free_ah;
611 }
612
2f7fe870
FF		 613 /* set up multi-rate retry capabilities */
614 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 615 hw->max_rates = 4;
616 hw->max_rate_tries = 11;
2f7fe870
FF		 617 }
618
fa1c114f
JS		 619 /* Finish private driver data initialization */
620 ret = ath5k_attach(pdev, hw);
621 if (ret)
622 goto err_ah;
623
624 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 625 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 626 sc->ah->ah_mac_srev,
627 sc->ah->ah_phy_revision);
628
400ec45a 629 if (!sc->ah->ah_single_chip) {
fa1c114f 630 /* Single chip radio (!RF5111) */
400ec45a
LR		 631 if (sc->ah->ah_radio_5ghz_revision &&
632 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 633 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 634 if (!test_bit(AR5K_MODE_11A,
635 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 636 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 637 ath5k_chip_name(AR5K_VERSION_RAD,
638 sc->ah->ah_radio_5ghz_revision),
639 sc->ah->ah_radio_5ghz_revision);
640 /* No 2GHz support (5110 and some
641 * 5Ghz only cards) -> report 5Ghz radio */
642 } else if (!test_bit(AR5K_MODE_11B,
643 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 644 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 645 ath5k_chip_name(AR5K_VERSION_RAD,
646 sc->ah->ah_radio_5ghz_revision),
647 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 648 /* Multiband radio */
649 } else {
650 ATH5K_INFO(sc, "RF%s multiband radio found"
651 " (0x%x)\n",
400ec45a
LR		 652 ath5k_chip_name(AR5K_VERSION_RAD,
653 sc->ah->ah_radio_5ghz_revision),
654 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 655 }
656 }
400ec45a
LR		 657 /* Multi chip radio (RF5111 - RF2111) ->
658 * report both 2GHz/5GHz radios */
659 else if (sc->ah->ah_radio_5ghz_revision &&
660 sc->ah->ah_radio_2ghz_revision){
fa1c114f 661 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 662 ath5k_chip_name(AR5K_VERSION_RAD,
663 sc->ah->ah_radio_5ghz_revision),
664 sc->ah->ah_radio_5ghz_revision);
fa1c114f 665 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 666 ath5k_chip_name(AR5K_VERSION_RAD,
667 sc->ah->ah_radio_2ghz_revision),
668 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 669 }
670 }
671
672
673 /* ready to process interrupts */
674 __clear_bit(ATH_STAT_INVALID, sc->status);
675
676 return 0;
677err_ah:
678 ath5k_hw_detach(sc->ah);
679err_irq:
680 free_irq(pdev->irq, sc);
9adca126
LR		 681err_free_ah:
682 kfree(sc->ah);
fa1c114f 683err_free:
fa1c114f
JS		 684 ieee80211_free_hw(hw);
685err_map:
686 pci_iounmap(pdev, mem);
687err_reg:
688 pci_release_region(pdev, 0);
689err_dis:
690 pci_disable_device(pdev);
691err:
692 return ret;
693}
694
695static void __devexit
696ath5k_pci_remove(struct pci_dev *pdev)
697{
6673e2e8 698 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f
JS		 699
700 ath5k_debug_finish_device(sc);
6673e2e8 701 ath5k_detach(pdev, sc->hw);
fa1c114f 702 ath5k_hw_detach(sc->ah);
9adca126 703 kfree(sc->ah);
fa1c114f 704 free_irq(pdev->irq, sc);
fa1c114f
JS		 705 pci_iounmap(pdev, sc->iobase);
706 pci_release_region(pdev, 0);
707 pci_disable_device(pdev);
6673e2e8 708 ieee80211_free_hw(sc->hw);
fa1c114f
JS		 709}
710
e307139d 711#ifdef CONFIG_PM_SLEEP
baee1f3c 712static int ath5k_pci_suspend(struct device *dev)
fa1c114f 713{
6673e2e8 714 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
fa1c114f 715
3a078876 716 ath5k_led_off(sc);
fa1c114f
JS		 717 return 0;
718}
719
baee1f3c 720static int ath5k_pci_resume(struct device *dev)
fa1c114f 721{
baee1f3c 722 struct pci_dev *pdev = to_pci_dev(dev);
6673e2e8 723 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 724
8451d22d
JM		 725 /*
726 * Suspend/Resume resets the PCI configuration space, so we have to
727 * re-disable the RETRY_TIMEOUT register (0x41) to keep
728 * PCI Tx retries from interfering with C3 CPU state
729 */
730 pci_write_config_byte(pdev, 0x41, 0);
731
3a078876 732 ath5k_led_enable(sc);
fa1c114f
JS		 733 return 0;
734}
e307139d 735#endif /* CONFIG_PM_SLEEP */
fa1c114f
JS		 736
737
fa1c114f
JS		 738/***********************\
739* Driver Initialization *
740\***********************/
741
f769c36b
BC		 742static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
743{
744 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
745 struct ath5k_softc *sc = hw->priv;
db719718 746 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
f769c36b 747
608b88cb 748 return ath_reg_notifier_apply(wiphy, request, regulatory);
f769c36b
BC		 749}
750
fa1c114f
JS		 751static int
752ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
753{
754 struct ath5k_softc *sc = hw->priv;
755 struct ath5k_hw *ah = sc->ah;
db719718 756 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
0e149cf5 757 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 758 int ret;
759
760 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
761
762 /*
763 * Check if the MAC has multi-rate retry support.
764 * We do this by trying to setup a fake extended
765 * descriptor. MAC's that don't have support will
766 * return false w/o doing anything. MAC's that do
767 * support it will return true w/o doing anything.
768 */
c6e387a2 769 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 770 if (ret < 0)
771 goto err;
772 if (ret > 0)
fa1c114f
JS		 773 __set_bit(ATH_STAT_MRRETRY, sc->status);
774
fa1c114f
JS		 775 /*
776 * Collect the channel list. The 802.11 layer
777 * is resposible for filtering this list based
778 * on settings like the phy mode and regulatory
779 * domain restrictions.
780 */
63266a65 781 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 782 if (ret) {
783 ATH5K_ERR(sc, "can't get channels\n");
784 goto err;
785 }
786
787 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 788 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
789 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 790 else
d8ee398d 791 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 792
793 /*
794 * Allocate tx+rx descriptors and populate the lists.
795 */
796 ret = ath5k_desc_alloc(sc, pdev);
797 if (ret) {
798 ATH5K_ERR(sc, "can't allocate descriptors\n");
799 goto err;
800 }
801
802 /*
803 * Allocate hardware transmit queues: one queue for
804 * beacon frames and one data queue for each QoS
805 * priority. Note that hw functions handle reseting
806 * these queues at the needed time.
807 */
808 ret = ath5k_beaconq_setup(ah);
809 if (ret < 0) {
810 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
811 goto err_desc;
812 }
813 sc->bhalq = ret;
cec8db23
BC		 814 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
815 if (IS_ERR(sc->cabq)) {
816 ATH5K_ERR(sc, "can't setup cab queue\n");
817 ret = PTR_ERR(sc->cabq);
818 goto err_bhal;
819 }
fa1c114f
JS		 820
821 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
822 if (IS_ERR(sc->txq)) {
823 ATH5K_ERR(sc, "can't setup xmit queue\n");
824 ret = PTR_ERR(sc->txq);
cec8db23 825 goto err_queues;
fa1c114f
JS		 826 }
827
828 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
829 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
830 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
6e220662 831 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
acf3c1a5 832 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2111ac0d 833 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
fa1c114f 834
0e149cf5
BC		 835 ret = ath5k_eeprom_read_mac(ah, mac);
836 if (ret) {
837 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
838 sc->pdev->device);
839 goto err_queues;
840 }
841
fa1c114f
JS		 842 SET_IEEE80211_PERM_ADDR(hw, mac);
843 /* All MAC address bits matter for ACKs */
17753748 844 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
fa1c114f
JS		 845 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
846
608b88cb
LR		 847 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
848 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
f769c36b
BC		 849 if (ret) {
850 ATH5K_ERR(sc, "can't initialize regulatory system\n");
851 goto err_queues;
852 }
853
fa1c114f
JS		 854 ret = ieee80211_register_hw(hw);
855 if (ret) {
856 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
857 goto err_queues;
858 }
859
608b88cb
LR		 860 if (!ath_is_world_regd(regulatory))
861 regulatory_hint(hw->wiphy, regulatory->alpha2);
f769c36b 862
3a078876
BC		 863 ath5k_init_leds(sc);
864
40ca22ea
BR		 865 ath5k_sysfs_register(sc);
866
fa1c114f
JS		 867 return 0;
868err_queues:
869 ath5k_txq_release(sc);
870err_bhal:
871 ath5k_hw_release_tx_queue(ah, sc->bhalq);
872err_desc:
873 ath5k_desc_free(sc, pdev);
874err:
875 return ret;
876}
877
878static void
879ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
880{
881 struct ath5k_softc *sc = hw->priv;
882
883 /*
884 * NB: the order of these is important:
885 * o call the 802.11 layer before detaching ath5k_hw to
886 * insure callbacks into the driver to delete global
887 * key cache entries can be handled
888 * o reclaim the tx queue data structures after calling
889 * the 802.11 layer as we'll get called back to reclaim
890 * node state and potentially want to use them
891 * o to cleanup the tx queues the hal is called, so detach
892 * it last
893 * XXX: ??? detach ath5k_hw ???
894 * Other than that, it's straightforward...
895 */
896 ieee80211_unregister_hw(hw);
897 ath5k_desc_free(sc, pdev);
898 ath5k_txq_release(sc);
899 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 900 ath5k_unregister_leds(sc);
fa1c114f 901
40ca22ea 902 ath5k_sysfs_unregister(sc);
fa1c114f
JS		 903 /*
904 * NB: can't reclaim these until after ieee80211_ifdetach
905 * returns because we'll get called back to reclaim node
906 * state and potentially want to use them.
907 */
908}
909
910
911
912
913/********************\
914* Channel/mode setup *
915\********************/
916
917/*
918 * Convert IEEE channel number to MHz frequency.
919 */
920static inline short
921ath5k_ieee2mhz(short chan)
922{
923 if (chan <= 14 || chan >= 27)
924 return ieee80211chan2mhz(chan);
925 else
926 return 2212 + chan * 20;
927}
928
42639fcd
BC		 929/*
930 * Returns true for the channel numbers used without all_channels modparam.
931 */
932static bool ath5k_is_standard_channel(short chan)
933{
934 return ((chan <= 14) ||
935 /* UNII 1,2 */
936 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
937 /* midband */
938 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
939 /* UNII-3 */
940 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
941}
942
fa1c114f
JS		 943static unsigned int
944ath5k_copy_channels(struct ath5k_hw *ah,
945 struct ieee80211_channel *channels,
946 unsigned int mode,
947 unsigned int max)
948{
d8ee398d 949 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 950
951 if (!test_bit(mode, ah->ah_modes))
952 return 0;
953
fa1c114f 954 switch (mode) {
d8ee398d
LR		 955 case AR5K_MODE_11A:
956 case AR5K_MODE_11A_TURBO:
fa1c114f 957 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 958 size = 220 ;
fa1c114f
JS		 959 chfreq = CHANNEL_5GHZ;
960 break;
d8ee398d
LR		 961 case AR5K_MODE_11B:
962 case AR5K_MODE_11G:
963 case AR5K_MODE_11G_TURBO:
964 size = 26;
fa1c114f
JS		 965 chfreq = CHANNEL_2GHZ;
966 break;
967 default:
968 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
969 return 0;
970 }
971
972 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 973 ch = i + 1 ;
974 freq = ath5k_ieee2mhz(ch);
fa1c114f 975
d8ee398d
LR		 976 /* Check if channel is supported by the chipset */
977 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 978 continue;
979
42639fcd
BC		 980 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
981 continue;
982
d8ee398d
LR		 983 /* Write channel info and increment counter */
984 channels[count].center_freq = freq;
a3f4b914
LR		 985 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
986 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 987 switch (mode) {
988 case AR5K_MODE_11A:
989 case AR5K_MODE_11G:
990 channels[count].hw_value = chfreq | CHANNEL_OFDM;
991 break;
992 case AR5K_MODE_11A_TURBO:
993 case AR5K_MODE_11G_TURBO:
994 channels[count].hw_value = chfreq |
995 CHANNEL_OFDM | CHANNEL_TURBO;
996 break;
997 case AR5K_MODE_11B:
d8ee398d
LR		 998 channels[count].hw_value = CHANNEL_B;
999 }
fa1c114f 1000
fa1c114f
JS		 1001 count++;
1002 max--;
1003 }
1004
1005 return count;
1006}
1007
63266a65
BR		 1008static void
1009ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1010{
1011 u8 i;
1012
1013 for (i = 0; i < AR5K_MAX_RATES; i++)
1014 sc->rate_idx[b->band][i] = -1;
1015
1016 for (i = 0; i < b->n_bitrates; i++) {
1017 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1018 if (b->bitrates[i].hw_value_short)
1019 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1020 }
1021}
1022
d8ee398d 1023static int
63266a65 1024ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 1025{
1026 struct ath5k_softc *sc = hw->priv;
d8ee398d 1027 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 1028 struct ieee80211_supported_band *sband;
1029 int max_c, count_c = 0;
1030 int i;
fa1c114f 1031
d8ee398d 1032 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 1033 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 1034
1035 /* 2GHz band */
63266a65
BR		 1036 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1037 sband->band = IEEE80211_BAND_2GHZ;
1038 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 1039
63266a65
BR		 1040 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1041 /* G mode */
1042 memcpy(sband->bitrates, &ath5k_rates[0],
1043 sizeof(struct ieee80211_rate) * 12);
1044 sband->n_bitrates = 12;
fa1c114f 1045
d8ee398d 1046 sband->channels = sc->channels;
d8ee398d 1047 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1048 AR5K_MODE_11G, max_c);
fa1c114f 1049
63266a65 1050 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1051 count_c = sband->n_channels;
63266a65
BR		 1052 max_c -= count_c;
1053 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1054 /* B mode */
1055 memcpy(sband->bitrates, &ath5k_rates[0],
1056 sizeof(struct ieee80211_rate) * 4);
1057 sband->n_bitrates = 4;
1058
1059 /* 5211 only supports B rates and uses 4bit rate codes
1060 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1061 * fix them up here:
1062 */
1063 if (ah->ah_version == AR5K_AR5211) {
1064 for (i = 0; i < 4; i++) {
1065 sband->bitrates[i].hw_value =
1066 sband->bitrates[i].hw_value & 0xF;
1067 sband->bitrates[i].hw_value_short =
1068 sband->bitrates[i].hw_value_short & 0xF;
1069 }
1070 }
fa1c114f 1071
63266a65
BR		 1072 sband->channels = sc->channels;
1073 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1074 AR5K_MODE_11B, max_c);
d8ee398d 1075
63266a65
BR		 1076 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1077 count_c = sband->n_channels;
d8ee398d 1078 max_c -= count_c;
fa1c114f 1079 }
63266a65 1080 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1081
63266a65 1082 /* 5GHz band, A mode */
400ec45a 1083 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1084 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1085 sband->band = IEEE80211_BAND_5GHZ;
1086 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1087
63266a65
BR		 1088 memcpy(sband->bitrates, &ath5k_rates[4],
1089 sizeof(struct ieee80211_rate) * 8);
1090 sband->n_bitrates = 8;
fa1c114f 1091
63266a65 1092 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1093 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1094 AR5K_MODE_11A, max_c);
1095
d8ee398d
LR		 1096 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1097 }
63266a65 1098 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1099
b446197c 1100 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1101
1102 return 0;
fa1c114f
JS		 1103}
1104
1105/*
e30eb4ab
JA		 1106 * Set/change channels. We always reset the chip.
1107 * To accomplish this we must first cleanup any pending DMA,
1108 * then restart stuff after a la ath5k_init.
be009370
BC		 1109 *
1110 * Called with sc->lock.
fa1c114f
JS		 1111 */
1112static int
1113ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1114{
8d67a031
BR		 1115 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1116 "channel set, resetting (%u -> %u MHz)\n",
1117 sc->curchan->center_freq, chan->center_freq);
d8ee398d 1118
e30eb4ab
JA		 1119 /*
1120 * To switch channels clear any pending DMA operations;
1121 * wait long enough for the RX fifo to drain, reset the
1122 * hardware at the new frequency, and then re-enable
1123 * the relevant bits of the h/w.
1124 */
1125 return ath5k_reset(sc, chan);
fa1c114f
JS		 1126}
1127
1128static void
1129ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1130{
fa1c114f 1131 sc->curmode = mode;
d8ee398d 1132
400ec45a 1133 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1134 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1135 } else {
1136 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1137 }
fa1c114f
JS		 1138}
1139
1140static void
1141ath5k_mode_setup(struct ath5k_softc *sc)
1142{
1143 struct ath5k_hw *ah = sc->ah;
1144 u32 rfilt;
1145
1146 /* configure rx filter */
1147 rfilt = sc->filter_flags;
1148 ath5k_hw_set_rx_filter(ah, rfilt);
1149
1150 if (ath5k_hw_hasbssidmask(ah))
1151 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1152
1153 /* configure operational mode */
ccfe5552 1154 ath5k_hw_set_opmode(ah, sc->opmode);
fa1c114f 1155
ccfe5552 1156 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
fa1c114f
JS		 1157 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1158}
1159
d8ee398d 1160static inline int
63266a65
BR		 1161ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1162{
b7266047
BC		 1163 int rix;
1164
1165 /* return base rate on errors */
1166 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1167 "hw_rix out of bounds: %x\n", hw_rix))
1168 return 0;
1169
1170 rix = sc->rate_idx[sc->curband->band][hw_rix];
1171 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1172 rix = 0;
1173
1174 return rix;
d8ee398d
LR		 1175}
1176
fa1c114f
JS		 1177/***************\
1178* Buffers setup *
1179\***************/
1180
b6ea0356
BC		 1181static
1182struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1183{
db719718 1184 struct ath_common *common = ath5k_hw_common(sc->ah);
b6ea0356 1185 struct sk_buff *skb;
b6ea0356
BC		 1186
1187 /*
1188 * Allocate buffer with headroom_needed space for the
1189 * fake physical layer header at the start.
1190 */
db719718 1191 skb = ath_rxbuf_alloc(common,
dd849782 1192 common->rx_bufsize,
aeb63cfd 1193 GFP_ATOMIC);
b6ea0356
BC		 1194
1195 if (!skb) {
1196 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
dd849782 1197 common->rx_bufsize);
b6ea0356
BC		 1198 return NULL;
1199 }
b6ea0356
BC		 1200
1201 *skb_addr = pci_map_single(sc->pdev,
cc861f74
LR		 1202 skb->data, common->rx_bufsize,
1203 PCI_DMA_FROMDEVICE);
b6ea0356
BC		 1204 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1205 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1206 dev_kfree_skb(skb);
1207 return NULL;
1208 }
1209 return skb;
1210}
1211
fa1c114f
JS		 1212static int
1213ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1214{
1215 struct ath5k_hw *ah = sc->ah;
1216 struct sk_buff *skb = bf->skb;
1217 struct ath5k_desc *ds;
b5eae9ff 1218 int ret;
fa1c114f 1219
b6ea0356
BC		 1220 if (!skb) {
1221 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1222 if (!skb)
fa1c114f 1223 return -ENOMEM;
fa1c114f 1224 bf->skb = skb;
fa1c114f
JS		 1225 }
1226
1227 /*
1228 * Setup descriptors. For receive we always terminate
1229 * the descriptor list with a self-linked entry so we'll
1230 * not get overrun under high load (as can happen with a
1231 * 5212 when ANI processing enables PHY error frames).
1232 *
beade636 1233 * To ensure the last descriptor is self-linked we create
fa1c114f
JS		 1234 * each descriptor as self-linked and add it to the end. As
1235 * each additional descriptor is added the previous self-linked
beade636 1236 * entry is "fixed" naturally. This should be safe even
fa1c114f
JS		 1237 * if DMA is happening. When processing RX interrupts we
1238 * never remove/process the last, self-linked, entry on the
beade636 1239 * descriptor list. This ensures the hardware always has
fa1c114f
JS		 1240 * someplace to write a new frame.
1241 */
1242 ds = bf->desc;
1243 ds->ds_link = bf->daddr; /* link to self */
1244 ds->ds_data = bf->skbaddr;
b5eae9ff 1245 ret = ah->ah_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
0452d4a5
BR		 1246 if (ret) {
1247 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
b5eae9ff 1248 return ret;
0452d4a5 1249 }
fa1c114f
JS		 1250
1251 if (sc->rxlink != NULL)
1252 *sc->rxlink = bf->daddr;
1253 sc->rxlink = &ds->ds_link;
1254 return 0;
1255}
1256
2ac2927a
BC		 1257static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1258{
1259 struct ieee80211_hdr *hdr;
1260 enum ath5k_pkt_type htype;
1261 __le16 fc;
1262
1263 hdr = (struct ieee80211_hdr *)skb->data;
1264 fc = hdr->frame_control;
1265
1266 if (ieee80211_is_beacon(fc))
1267 htype = AR5K_PKT_TYPE_BEACON;
1268 else if (ieee80211_is_probe_resp(fc))
1269 htype = AR5K_PKT_TYPE_PROBE_RESP;
1270 else if (ieee80211_is_atim(fc))
1271 htype = AR5K_PKT_TYPE_ATIM;
1272 else if (ieee80211_is_pspoll(fc))
1273 htype = AR5K_PKT_TYPE_PSPOLL;
1274 else
1275 htype = AR5K_PKT_TYPE_NORMAL;
1276
1277 return htype;
1278}
1279
fa1c114f 1280static int
cec8db23 1281ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
8127fbdc 1282 struct ath5k_txq *txq, int padsize)
fa1c114f
JS		 1283{
1284 struct ath5k_hw *ah = sc->ah;
fa1c114f
JS		 1285 struct ath5k_desc *ds = bf->desc;
1286 struct sk_buff *skb = bf->skb;
a888d52d 1287 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1288 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1289 struct ieee80211_rate *rate;
1290 unsigned int mrr_rate[3], mrr_tries[3];
1291 int i, ret;
8902ff4e 1292 u16 hw_rate;
07c1e852
BC		 1293 u16 cts_rate = 0;
1294 u16 duration = 0;
8902ff4e 1295 u8 rc_flags;
fa1c114f
JS		 1296
1297 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1298
fa1c114f
JS		 1299 /* XXX endianness */
1300 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1301 PCI_DMA_TODEVICE);
1302
8902ff4e
BC		 1303 rate = ieee80211_get_tx_rate(sc->hw, info);
1304
e039fa4a 1305 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1306 flags |= AR5K_TXDESC_NOACK;
1307
8902ff4e
BC		 1308 rc_flags = info->control.rates[0].flags;
1309 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1310 rate->hw_value_short : rate->hw_value;
1311
281c56dd 1312 pktlen = skb->len;
fa1c114f 1313
8f655dde
NK		 1314 /* FIXME: If we are in g mode and rate is a CCK rate
1315 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1316 * from tx power (value is in dB units already) */
362695e1
BC		 1317 if (info->control.hw_key) {
1318 keyidx = info->control.hw_key->hw_key_idx;
1319 pktlen += info->control.hw_key->icv_len;
1320 }
07c1e852
BC		 1321 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1322 flags |= AR5K_TXDESC_RTSENA;
1323 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1324 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1325 sc->vif, pktlen, info));
1326 }
1327 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1328 flags |= AR5K_TXDESC_CTSENA;
1329 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1330 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1331 sc->vif, pktlen, info));
1332 }
fa1c114f 1333 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
8127fbdc 1334 ieee80211_get_hdrlen_from_skb(skb), padsize,
2ac2927a 1335 get_hw_packet_type(skb),
2e92e6f2 1336 (sc->power_level * 2),
8902ff4e 1337 hw_rate,
2bed03eb 1338 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1339 cts_rate, duration);
fa1c114f
JS		 1340 if (ret)
1341 goto err_unmap;
1342
2f7fe870
FF		 1343 memset(mrr_rate, 0, sizeof(mrr_rate));
1344 memset(mrr_tries, 0, sizeof(mrr_tries));
1345 for (i = 0; i < 3; i++) {
1346 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1347 if (!rate)
1348 break;
1349
1350 mrr_rate[i] = rate->hw_value;
e6a9854b 1351 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1352 }
1353
1354 ah->ah_setup_mrr_tx_desc(ah, ds,
1355 mrr_rate[0], mrr_tries[0],
1356 mrr_rate[1], mrr_tries[1],
1357 mrr_rate[2], mrr_tries[2]);
1358
fa1c114f
JS		 1359 ds->ds_link = 0;
1360 ds->ds_data = bf->skbaddr;
1361
1362 spin_lock_bh(&txq->lock);
1363 list_add_tail(&bf->list, &txq->q);
fa1c114f 1364 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1365 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1366 else /* no, so only link it */
1367 *txq->link = bf->daddr;
1368
1369 txq->link = &ds->ds_link;
c6e387a2 1370 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1371 mmiowb();
fa1c114f
JS		 1372 spin_unlock_bh(&txq->lock);
1373
1374 return 0;
1375err_unmap:
1376 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1377 return ret;
1378}
1379
1380/*******************\
1381* Descriptors setup *
1382\*******************/
1383
1384static int
1385ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1386{
1387 struct ath5k_desc *ds;
1388 struct ath5k_buf *bf;
1389 dma_addr_t da;
1390 unsigned int i;
1391 int ret;
1392
1393 /* allocate descriptors */
1394 sc->desc_len = sizeof(struct ath5k_desc) *
1395 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1396 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1397 if (sc->desc == NULL) {
1398 ATH5K_ERR(sc, "can't allocate descriptors\n");
1399 ret = -ENOMEM;
1400 goto err;
1401 }
1402 ds = sc->desc;
1403 da = sc->desc_daddr;
1404 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1405 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1406
1407 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1408 sizeof(struct ath5k_buf), GFP_KERNEL);
1409 if (bf == NULL) {
1410 ATH5K_ERR(sc, "can't allocate bufptr\n");
1411 ret = -ENOMEM;
1412 goto err_free;
1413 }
1414 sc->bufptr = bf;
1415
1416 INIT_LIST_HEAD(&sc->rxbuf);
1417 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1418 bf->desc = ds;
1419 bf->daddr = da;
1420 list_add_tail(&bf->list, &sc->rxbuf);
1421 }
1422
1423 INIT_LIST_HEAD(&sc->txbuf);
1424 sc->txbuf_len = ATH_TXBUF;
1425 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1426 da += sizeof(*ds)) {
1427 bf->desc = ds;
1428 bf->daddr = da;
1429 list_add_tail(&bf->list, &sc->txbuf);
1430 }
1431
1432 /* beacon buffer */
1433 bf->desc = ds;
1434 bf->daddr = da;
1435 sc->bbuf = bf;
1436
1437 return 0;
1438err_free:
1439 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1440err:
1441 sc->desc = NULL;
1442 return ret;
1443}
1444
1445static void
1446ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1447{
1448 struct ath5k_buf *bf;
1449
9e4e43f2 1450 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 1451 list_for_each_entry(bf, &sc->txbuf, list)
9e4e43f2 1452 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1453 list_for_each_entry(bf, &sc->rxbuf, list)
9e4e43f2 1454 ath5k_rxbuf_free_skb(sc, bf);
fa1c114f
JS		 1455
1456 /* Free memory associated with all descriptors */
1457 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1458
1459 kfree(sc->bufptr);
1460 sc->bufptr = NULL;
1461}
1462
1463
1464
1465
1466
1467/**************\
1468* Queues setup *
1469\**************/
1470
1471static struct ath5k_txq *
1472ath5k_txq_setup(struct ath5k_softc *sc,
1473 int qtype, int subtype)
1474{
1475 struct ath5k_hw *ah = sc->ah;
1476 struct ath5k_txq *txq;
1477 struct ath5k_txq_info qi = {
1478 .tqi_subtype = subtype,
1479 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1480 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1481 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1482 };
1483 int qnum;
1484
1485 /*
1486 * Enable interrupts only for EOL and DESC conditions.
1487 * We mark tx descriptors to receive a DESC interrupt
1488 * when a tx queue gets deep; otherwise waiting for the
1489 * EOL to reap descriptors. Note that this is done to
1490 * reduce interrupt load and this only defers reaping
1491 * descriptors, never transmitting frames. Aside from
1492 * reducing interrupts this also permits more concurrency.
1493 * The only potential downside is if the tx queue backs
1494 * up in which case the top half of the kernel may backup
1495 * due to a lack of tx descriptors.
1496 */
1497 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1498 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1499 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1500 if (qnum < 0) {
1501 /*
1502 * NB: don't print a message, this happens
1503 * normally on parts with too few tx queues
1504 */
1505 return ERR_PTR(qnum);
1506 }
1507 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1508 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1509 qnum, ARRAY_SIZE(sc->txqs));
1510 ath5k_hw_release_tx_queue(ah, qnum);
1511 return ERR_PTR(-EINVAL);
1512 }
1513 txq = &sc->txqs[qnum];
1514 if (!txq->setup) {
1515 txq->qnum = qnum;
1516 txq->link = NULL;
1517 INIT_LIST_HEAD(&txq->q);
1518 spin_lock_init(&txq->lock);
1519 txq->setup = true;
1520 }
1521 return &sc->txqs[qnum];
1522}
1523
1524static int
1525ath5k_beaconq_setup(struct ath5k_hw *ah)
1526{
1527 struct ath5k_txq_info qi = {
1528 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1529 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1530 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1531 /* NB: for dynamic turbo, don't enable any other interrupts */
1532 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1533 };
1534
1535 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1536}
1537
1538static int
1539ath5k_beaconq_config(struct ath5k_softc *sc)
1540{
1541 struct ath5k_hw *ah = sc->ah;
1542 struct ath5k_txq_info qi;
1543 int ret;
1544
1545 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1546 if (ret)
a951ae21
BC		 1547 goto err;
1548
05c914fe
JB		 1549 if (sc->opmode == NL80211_IFTYPE_AP ||
1550 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1551 /*
1552 * Always burst out beacon and CAB traffic
1553 * (aifs = cwmin = cwmax = 0)
1554 */
1555 qi.tqi_aifs = 0;
1556 qi.tqi_cw_min = 0;
1557 qi.tqi_cw_max = 0;
05c914fe 1558 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1559 /*
1560 * Adhoc mode; backoff between 0 and (2 * cw_min).
1561 */
1562 qi.tqi_aifs = 0;
1563 qi.tqi_cw_min = 0;
1564 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1565 }
1566
6d91e1d8
BR		 1567 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1568 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1569 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1570
c6e387a2 1571 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1572 if (ret) {
1573 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1574 "hardware queue!\n", __func__);
a951ae21 1575 goto err;
fa1c114f 1576 }
a951ae21
BC		 1577 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1578 if (ret)
1579 goto err;
fa1c114f 1580
a951ae21
BC		 1581 /* reconfigure cabq with ready time to 80% of beacon_interval */
1582 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1583 if (ret)
1584 goto err;
1585
1586 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1587 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1588 if (ret)
1589 goto err;
1590
1591 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1592err:
1593 return ret;
fa1c114f
JS		 1594}
1595
1596static void
1597ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1598{
1599 struct ath5k_buf *bf, *bf0;
1600
1601 /*
1602 * NB: this assumes output has been stopped and
1603 * we do not need to block ath5k_tx_tasklet
1604 */
1605 spin_lock_bh(&txq->lock);
1606 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1607 ath5k_debug_printtxbuf(sc, bf);
fa1c114f 1608
9e4e43f2 1609 ath5k_txbuf_free_skb(sc, bf);
fa1c114f
JS		 1610
1611 spin_lock_bh(&sc->txbuflock);
fa1c114f
JS		 1612 list_move_tail(&bf->list, &sc->txbuf);
1613 sc->txbuf_len++;
1614 spin_unlock_bh(&sc->txbuflock);
1615 }
1616 txq->link = NULL;
1617 spin_unlock_bh(&txq->lock);
1618}
1619
1620/*
1621 * Drain the transmit queues and reclaim resources.
1622 */
1623static void
1624ath5k_txq_cleanup(struct ath5k_softc *sc)
1625{
1626 struct ath5k_hw *ah = sc->ah;
1627 unsigned int i;
1628
1629 /* XXX return value */
1630 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1631 /* don't touch the hardware if marked invalid */
1632 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1633 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1634 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1635 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1636 if (sc->txqs[i].setup) {
1637 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1638 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1639 "link %p\n",
1640 sc->txqs[i].qnum,
c6e387a2 1641 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1642 sc->txqs[i].qnum),
1643 sc->txqs[i].link);
1644 }
1645 }
fa1c114f
JS		 1646
1647 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1648 if (sc->txqs[i].setup)
1649 ath5k_txq_drainq(sc, &sc->txqs[i]);
1650}
1651
1652static void
1653ath5k_txq_release(struct ath5k_softc *sc)
1654{
1655 struct ath5k_txq *txq = sc->txqs;
1656 unsigned int i;
1657
1658 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1659 if (txq->setup) {
1660 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1661 txq->setup = false;
1662 }
1663}
1664
1665
1666
1667
1668/*************\
1669* RX Handling *
1670\*************/
1671
1672/*
1673 * Enable the receive h/w following a reset.
1674 */
1675static int
1676ath5k_rx_start(struct ath5k_softc *sc)
1677{
1678 struct ath5k_hw *ah = sc->ah;
db719718 1679 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 1680 struct ath5k_buf *bf;
1681 int ret;
1682
cc861f74 1683 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
fa1c114f 1684
cc861f74
LR		 1685 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1686 common->cachelsz, common->rx_bufsize);
fa1c114f 1687
fa1c114f 1688 spin_lock_bh(&sc->rxbuflock);
26925042 1689 sc->rxlink = NULL;
fa1c114f
JS		 1690 list_for_each_entry(bf, &sc->rxbuf, list) {
1691 ret = ath5k_rxbuf_setup(sc, bf);
1692 if (ret != 0) {
1693 spin_unlock_bh(&sc->rxbuflock);
1694 goto err;
1695 }
1696 }
1697 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1698 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1699 spin_unlock_bh(&sc->rxbuflock);
1700
c6e387a2 1701 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1702 ath5k_mode_setup(sc); /* set filters, etc. */
1703 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1704
1705 return 0;
1706err:
1707 return ret;
1708}
1709
1710/*
1711 * Disable the receive h/w in preparation for a reset.
1712 */
1713static void
1714ath5k_rx_stop(struct ath5k_softc *sc)
1715{
1716 struct ath5k_hw *ah = sc->ah;
1717
c6e387a2 1718 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1719 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1720 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1721
1722 ath5k_debug_printrxbuffs(sc, ah);
1723
1724 sc->rxlink = NULL; /* just in case */
1725}
1726
1727static unsigned int
1728ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1729 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f 1730{
dc1e001b
LR		 1731 struct ath5k_hw *ah = sc->ah;
1732 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1733 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1734 unsigned int keyix, hlen;
fa1c114f 1735
b47f407b
BR		 1736 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1737 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1738 return RX_FLAG_DECRYPTED;
1739
1740 /* Apparently when a default key is used to decrypt the packet
1741 the hw does not set the index used to decrypt. In such cases
1742 get the index from the packet. */
798ee985 1743 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1744 if (ieee80211_has_protected(hdr->frame_control) &&
1745 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1746 skb->len >= hlen + 4) {
fa1c114f
JS		 1747 keyix = skb->data[hlen + 3] >> 6;
1748
dc1e001b 1749 if (test_bit(keyix, common->keymap))
fa1c114f
JS		 1750 return RX_FLAG_DECRYPTED;
1751 }
1752
1753 return 0;
1754}
1755
036cd1ec
BR		 1756
1757static void
6ba81c2c
BR		 1758ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1759 struct ieee80211_rx_status *rxs)
036cd1ec 1760{
954fecea 1761 struct ath_common *common = ath5k_hw_common(sc->ah);
6ba81c2c 1762 u64 tsf, bc_tstamp;
036cd1ec
BR		 1763 u32 hw_tu;
1764 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1765
24b56e70 1766 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1767 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
954fecea 1768 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
036cd1ec 1769 /*
6ba81c2c
BR		 1770 * Received an IBSS beacon with the same BSSID. Hardware *must*
1771 * have updated the local TSF. We have to work around various
1772 * hardware bugs, though...
036cd1ec 1773 */
6ba81c2c
BR		 1774 tsf = ath5k_hw_get_tsf64(sc->ah);
1775 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1776 hw_tu = TSF_TO_TU(tsf);
1777
1778 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1779 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1780 (unsigned long long)bc_tstamp,
1781 (unsigned long long)rxs->mactime,
1782 (unsigned long long)(rxs->mactime - bc_tstamp),
1783 (unsigned long long)tsf);
6ba81c2c
BR		 1784
1785 /*
1786 * Sometimes the HW will give us a wrong tstamp in the rx
1787 * status, causing the timestamp extension to go wrong.
1788 * (This seems to happen especially with beacon frames bigger
1789 * than 78 byte (incl. FCS))
1790 * But we know that the receive timestamp must be later than the
1791 * timestamp of the beacon since HW must have synced to that.
1792 *
1793 * NOTE: here we assume mactime to be after the frame was
1794 * received, not like mac80211 which defines it at the start.
1795 */
1796 if (bc_tstamp > rxs->mactime) {
036cd1ec 1797 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1798 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1799 (unsigned long long)rxs->mactime,
1800 (unsigned long long)tsf);
6ba81c2c 1801 rxs->mactime = tsf;
036cd1ec 1802 }
6ba81c2c
BR		 1803
1804 /*
1805 * Local TSF might have moved higher than our beacon timers,
1806 * in that case we have to update them to continue sending
1807 * beacons. This also takes care of synchronizing beacon sending
1808 * times with other stations.
1809 */
1810 if (hw_tu >= sc->nexttbtt)
1811 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1812 }
1813}
1814
b4ea449d
BR		 1815static void
1816ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1817{
1818 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1819 struct ath5k_hw *ah = sc->ah;
1820 struct ath_common *common = ath5k_hw_common(ah);
1821
1822 /* only beacons from our BSSID */
1823 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1824 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1825 return;
1826
1827 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1828 rssi);
1829
1830 /* in IBSS mode we should keep RSSI statistics per neighbour */
1831 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1832}
1833
8127fbdc
BP		 1834/*
1835 * Compute padding position. skb must contains an IEEE 802.11 frame
1836 */
1837static int ath5k_common_padpos(struct sk_buff *skb)
1838{
1839 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1840 __le16 frame_control = hdr->frame_control;
1841 int padpos = 24;
1842
1843 if (ieee80211_has_a4(frame_control)) {
1844 padpos += ETH_ALEN;
1845 }
1846 if (ieee80211_is_data_qos(frame_control)) {
1847 padpos += IEEE80211_QOS_CTL_LEN;
1848 }
1849
1850 return padpos;
1851}
1852
1853/*
1854 * This function expects a 802.11 frame and returns the number of
1855 * bytes added, or -1 if we don't have enought header room.
1856 */
1857
1858static int ath5k_add_padding(struct sk_buff *skb)
1859{
1860 int padpos = ath5k_common_padpos(skb);
1861 int padsize = padpos & 3;
1862
1863 if (padsize && skb->len>padpos) {
1864
1865 if (skb_headroom(skb) < padsize)
1866 return -1;
1867
1868 skb_push(skb, padsize);
1869 memmove(skb->data, skb->data+padsize, padpos);
1870 return padsize;
1871 }
1872
1873 return 0;
1874}
1875
1876/*
1877 * This function expects a 802.11 frame and returns the number of
1878 * bytes removed
1879 */
1880
1881static int ath5k_remove_padding(struct sk_buff *skb)
1882{
1883 int padpos = ath5k_common_padpos(skb);
1884 int padsize = padpos & 3;
1885
1886 if (padsize && skb->len>=padpos+padsize) {
1887 memmove(skb->data + padsize, skb->data, padpos);
1888 skb_pull(skb, padsize);
1889 return padsize;
1890 }
1891
1892 return 0;
1893}
1894
fa1c114f
JS		 1895static void
1896ath5k_tasklet_rx(unsigned long data)
1897{
1c5256bb 1898 struct ieee80211_rx_status *rxs;
b47f407b 1899 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1900 struct sk_buff *skb, *next_skb;
1901 dma_addr_t next_skb_addr;
fa1c114f 1902 struct ath5k_softc *sc = (void *)data;
cc861f74
LR		 1903 struct ath5k_hw *ah = sc->ah;
1904 struct ath_common *common = ath5k_hw_common(ah);
c57ca815 1905 struct ath5k_buf *bf;
fa1c114f 1906 struct ath5k_desc *ds;
fa1c114f 1907 int ret;
1c5256bb 1908 int rx_flag;
fa1c114f
JS		 1909
1910 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1911 if (list_empty(&sc->rxbuf)) {
1912 ATH5K_WARN(sc, "empty rx buf pool\n");
1913 goto unlock;
1914 }
fa1c114f 1915 do {
1c5256bb 1916 rx_flag = 0;
d6894b5b 1917
fa1c114f
JS		 1918 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1919 BUG_ON(bf->skb == NULL);
1920 skb = bf->skb;
1921 ds = bf->desc;
1922
c57ca815
BC		 1923 /* bail if HW is still using self-linked descriptor */
1924 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1925 break;
fa1c114f 1926
b47f407b 1927 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1928 if (unlikely(ret == -EINPROGRESS))
1929 break;
1930 else if (unlikely(ret)) {
1931 ATH5K_ERR(sc, "error in processing rx descriptor\n");
7644395f 1932 sc->stats.rxerr_proc++;
65872e6b 1933 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1934 return;
1935 }
1936
7644395f
BR		 1937 sc->stats.rx_all_count++;
1938
b47f407b 1939 if (unlikely(rs.rs_status)) {
7644395f
BR		 1940 if (rs.rs_status & AR5K_RXERR_CRC)
1941 sc->stats.rxerr_crc++;
1942 if (rs.rs_status & AR5K_RXERR_FIFO)
1943 sc->stats.rxerr_fifo++;
1944 if (rs.rs_status & AR5K_RXERR_PHY) {
1945 sc->stats.rxerr_phy++;
da35111a
BR		 1946 if (rs.rs_phyerr > 0 && rs.rs_phyerr < 32)
1947 sc->stats.rxerr_phy_code[rs.rs_phyerr]++;
fa1c114f 1948 goto next;
7644395f 1949 }
b47f407b 1950 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1951 /*
1952 * Decrypt error. If the error occurred
1953 * because there was no hardware key, then
1954 * let the frame through so the upper layers
1955 * can process it. This is necessary for 5210
1956 * parts which have no way to setup a ``clear''
1957 * key cache entry.
1958 *
1959 * XXX do key cache faulting
1960 */
7644395f 1961 sc->stats.rxerr_decrypt++;
b47f407b
BR		 1962 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1963 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1964 goto accept;
1965 }
b47f407b 1966 if (rs.rs_status & AR5K_RXERR_MIC) {
1c5256bb 1967 rx_flag |= RX_FLAG_MMIC_ERROR;
7644395f 1968 sc->stats.rxerr_mic++;
fa1c114f
JS		 1969 goto accept;
1970 }
1971
1972 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1973 if ((rs.rs_status &
1974 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1975 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1976 goto next;
1977 }
9637e516
LR		 1978
1979 if (unlikely(rs.rs_more)) {
1980 sc->stats.rxerr_jumbo++;
1981 goto next;
1982
1983 }
fa1c114f 1984accept:
b6ea0356
BC		 1985 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1986
1987 /*
1988 * If we can't replace bf->skb with a new skb under memory
1989 * pressure, just skip this packet
1990 */
1991 if (!next_skb)
1992 goto next;
1993
cc861f74 1994 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
fa1c114f 1995 PCI_DMA_FROMDEVICE);
b47f407b 1996 skb_put(skb, rs.rs_datalen);
fa1c114f 1997
0fe45b1d
BP		 1998 /* The MAC header is padded to have 32-bit boundary if the
1999 * packet payload is non-zero. The general calculation for
2000 * padsize would take into account odd header lengths:
2001 * padsize = (4 - hdrlen % 4) % 4; However, since only
2002 * even-length headers are used, padding can only be 0 or 2
2003 * bytes and we can optimize this a bit. In addition, we must
2004 * not try to remove padding from short control frames that do
2005 * not have payload. */
8127fbdc
BP		 2006 ath5k_remove_padding(skb);
2007
1c5256bb 2008 rxs = IEEE80211_SKB_RXCB(skb);
fa1c114f 2009
c0e1899b
BR		 2010 /*
2011 * always extend the mac timestamp, since this information is
2012 * also needed for proper IBSS merging.
2013 *
2014 * XXX: it might be too late to do it here, since rs_tstamp is
2015 * 15bit only. that means TSF extension has to be done within
2016 * 32768usec (about 32ms). it might be necessary to move this to
2017 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 2018 *
2019 * Unfortunately we don't know when the hardware takes the rx
2020 * timestamp (beginning of phy frame, data frame, end of rx?).
2021 * The only thing we know is that it is hardware specific...
2022 * On AR5213 it seems the rx timestamp is at the end of the
2023 * frame, but i'm not sure.
2024 *
2025 * NOTE: mac80211 defines mactime at the beginning of the first
2026 * data symbol. Since we don't have any time references it's
2027 * impossible to comply to that. This affects IBSS merge only
2028 * right now, so it's not too bad...
c0e1899b 2029 */
1c5256bb
BC		 2030 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
2031 rxs->flag = rx_flag | RX_FLAG_TSFT;
c0e1899b 2032
1c5256bb
BC		 2033 rxs->freq = sc->curchan->center_freq;
2034 rxs->band = sc->curband->band;
fa1c114f 2035
54c7c91e 2036 rxs->signal = sc->ah->ah_noise_floor + rs.rs_rssi;
6e0e0bf8 2037
1c5256bb 2038 rxs->antenna = rs.rs_antenna;
604eeadd
BR		 2039
2040 if (rs.rs_antenna > 0 && rs.rs_antenna < 5)
2041 sc->stats.antenna_rx[rs.rs_antenna]++;
2042 else
2043 sc->stats.antenna_rx[0]++; /* invalid */
2044
1c5256bb
BC		 2045 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
2046 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 2047
1c5256bb
BC		 2048 if (rxs->rate_idx >= 0 && rs.rs_rate ==
2049 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
2050 rxs->flag |= RX_FLAG_SHORTPRE;
06303352 2051
fa1c114f
JS		 2052 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
2053
b4ea449d
BR		 2054 ath5k_update_beacon_rssi(sc, skb, rs.rs_rssi);
2055
036cd1ec 2056 /* check beacons in IBSS mode */
05c914fe 2057 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1c5256bb 2058 ath5k_check_ibss_tsf(sc, skb, rxs);
036cd1ec 2059
f1d58c25 2060 ieee80211_rx(sc->hw, skb);
b6ea0356
BC		 2061
2062 bf->skb = next_skb;
2063 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 2064next:
2065 list_move_tail(&bf->list, &sc->rxbuf);
2066 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 2067unlock:
fa1c114f
JS		 2068 spin_unlock(&sc->rxbuflock);
2069}
2070
2071
2072
2073
2074/*************\
2075* TX Handling *
2076\*************/
2077
2078static void
2079ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
2080{
b47f407b 2081 struct ath5k_tx_status ts = {};
fa1c114f
JS		 2082 struct ath5k_buf *bf, *bf0;
2083 struct ath5k_desc *ds;
2084 struct sk_buff *skb;
e039fa4a 2085 struct ieee80211_tx_info *info;
2f7fe870 2086 int i, ret;
fa1c114f
JS		 2087
2088 spin_lock(&txq->lock);
2089 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
2090 ds = bf->desc;
2091
a05988bb
BC		 2092 /*
2093 * It's possible that the hardware can say the buffer is
2094 * completed when it hasn't yet loaded the ds_link from
2095 * host memory and moved on. If there are more TX
2096 * descriptors in the queue, wait for TXDP to change
2097 * before processing this one.
2098 */
2099 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
2100 !list_is_last(&bf->list, &txq->q))
2101 break;
2102
b47f407b 2103 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 2104 if (unlikely(ret == -EINPROGRESS))
2105 break;
2106 else if (unlikely(ret)) {
2107 ATH5K_ERR(sc, "error %d while processing queue %u\n",
2108 ret, txq->qnum);
2109 break;
2110 }
2111
7644395f 2112 sc->stats.tx_all_count++;
fa1c114f 2113 skb = bf->skb;
a888d52d 2114 info = IEEE80211_SKB_CB(skb);
fa1c114f 2115 bf->skb = NULL;
e039fa4a 2116
fa1c114f
JS		 2117 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
2118 PCI_DMA_TODEVICE);
2119
e6a9854b 2120 ieee80211_tx_info_clear_status(info);
2f7fe870 2121 for (i = 0; i < 4; i++) {
e6a9854b
JB		 2122 struct ieee80211_tx_rate *r =
2123 &info->status.rates[i];
2f7fe870
FF		 2124
2125 if (ts.ts_rate[i]) {
e6a9854b
JB		 2126 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
2127 r->count = ts.ts_retry[i];
2f7fe870 2128 } else {
e6a9854b
JB		 2129 r->idx = -1;
2130 r->count = 0;
2f7fe870
FF		 2131 }
2132 }
2133
e6a9854b
JB		 2134 /* count the successful attempt as well */
2135 info->status.rates[ts.ts_final_idx].count++;
2136
b47f407b 2137 if (unlikely(ts.ts_status)) {
495391d7 2138 sc->stats.ack_fail++;
7644395f 2139 if (ts.ts_status & AR5K_TXERR_FILT) {
e039fa4a 2140 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
7644395f
BR		 2141 sc->stats.txerr_filt++;
2142 }
2143 if (ts.ts_status & AR5K_TXERR_XRETRY)
2144 sc->stats.txerr_retry++;
2145 if (ts.ts_status & AR5K_TXERR_FIFO)
2146 sc->stats.txerr_fifo++;
fa1c114f 2147 } else {
e039fa4a
JB		 2148 info->flags |= IEEE80211_TX_STAT_ACK;
2149 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2150 }
2151
8127fbdc
BP		 2152 /*
2153 * Remove MAC header padding before giving the frame
2154 * back to mac80211.
2155 */
2156 ath5k_remove_padding(skb);
2157
604eeadd
BR		 2158 if (ts.ts_antenna > 0 && ts.ts_antenna < 5)
2159 sc->stats.antenna_tx[ts.ts_antenna]++;
2160 else
2161 sc->stats.antenna_tx[0]++; /* invalid */
2162
e039fa4a 2163 ieee80211_tx_status(sc->hw, skb);
fa1c114f
JS		 2164
2165 spin_lock(&sc->txbuflock);
fa1c114f
JS		 2166 list_move_tail(&bf->list, &sc->txbuf);
2167 sc->txbuf_len++;
2168 spin_unlock(&sc->txbuflock);
2169 }
2170 if (likely(list_empty(&txq->q)))
2171 txq->link = NULL;
2172 spin_unlock(&txq->lock);
2173 if (sc->txbuf_len > ATH_TXBUF / 5)
2174 ieee80211_wake_queues(sc->hw);
2175}
2176
2177static void
2178ath5k_tasklet_tx(unsigned long data)
2179{
8784d2ee 2180 int i;
fa1c114f
JS		 2181 struct ath5k_softc *sc = (void *)data;
2182
8784d2ee
BC		 2183 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2184 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2185 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 2186}
2187
2188
fa1c114f
JS		 2189/*****************\
2190* Beacon handling *
2191\*****************/
2192
2193/*
2194 * Setup the beacon frame for transmit.
2195 */
2196static int
e039fa4a 2197ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2198{
2199 struct sk_buff *skb = bf->skb;
a888d52d 2200 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2201 struct ath5k_hw *ah = sc->ah;
2202 struct ath5k_desc *ds;
2bed03eb
NK		 2203 int ret = 0;
2204 u8 antenna;
fa1c114f 2205 u32 flags;
8127fbdc 2206 const int padsize = 0;
fa1c114f
JS		 2207
2208 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2209 PCI_DMA_TODEVICE);
2210 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2211 "skbaddr %llx\n", skb, skb->data, skb->len,
2212 (unsigned long long)bf->skbaddr);
8d8bb39b 2213 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2214 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2215 return -EIO;
2216 }
2217
2218 ds = bf->desc;
2bed03eb 2219 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2220
2221 flags = AR5K_TXDESC_NOACK;
05c914fe 2222 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2223 ds->ds_link = bf->daddr; /* self-linked */
2224 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2225 } else
fa1c114f 2226 ds->ds_link = 0;
2bed03eb
NK		 2227
2228 /*
2229 * If we use multiple antennas on AP and use
2230 * the Sectored AP scenario, switch antenna every
2231 * 4 beacons to make sure everybody hears our AP.
2232 * When a client tries to associate, hw will keep
2233 * track of the tx antenna to be used for this client
2234 * automaticaly, based on ACKed packets.
2235 *
2236 * Note: AP still listens and transmits RTS on the
2237 * default antenna which is supposed to be an omni.
2238 *
2239 * Note2: On sectored scenarios it's possible to have
2240 * multiple antennas (1omni -the default- and 14 sectors)
2241 * so if we choose to actually support this mode we need
2242 * to allow user to set how many antennas we have and tweak
2243 * the code below to send beacons on all of them.
2244 */
2245 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2246 antenna = sc->bsent & 4 ? 2 : 1;
2247
fa1c114f 2248
8f655dde
NK		 2249 /* FIXME: If we are in g mode and rate is a CCK rate
2250 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2251 * from tx power (value is in dB units already) */
fa1c114f 2252 ds->ds_data = bf->skbaddr;
281c56dd 2253 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 2254 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 2255 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2256 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2257 1, AR5K_TXKEYIX_INVALID,
400ec45a 2258 antenna, flags, 0, 0);
fa1c114f
JS		 2259 if (ret)
2260 goto err_unmap;
2261
2262 return 0;
2263err_unmap:
2264 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2265 return ret;
2266}
2267
2268/*
2269 * Transmit a beacon frame at SWBA. Dynamic updates to the
2270 * frame contents are done as needed and the slot time is
2271 * also adjusted based on current state.
2272 *
acf3c1a5
BC		 2273 * This is called from software irq context (beacontq or restq
2274 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2275 */
2276static void
2277ath5k_beacon_send(struct ath5k_softc *sc)
2278{
2279 struct ath5k_buf *bf = sc->bbuf;
2280 struct ath5k_hw *ah = sc->ah;
cec8db23 2281 struct sk_buff *skb;
fa1c114f 2282
be9b7259 2283 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2284
05c914fe
JB		 2285 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2286 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2287 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2288 return;
2289 }
2290 /*
2291 * Check if the previous beacon has gone out. If
2292 * not don't don't try to post another, skip this
2293 * period and wait for the next. Missed beacons
2294 * indicate a problem and should not occur. If we
2295 * miss too many consecutive beacons reset the device.
2296 */
2297 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2298 sc->bmisscount++;
be9b7259 2299 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2300 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2301 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2302 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2303 "stuck beacon time (%u missed)\n",
2304 sc->bmisscount);
8d67a031
BR		 2305 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2306 "stuck beacon, resetting\n");
fa1c114f
JS		 2307 tasklet_schedule(&sc->restq);
2308 }
2309 return;
2310 }
2311 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2312 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2313 "resume beacon xmit after %u misses\n",
2314 sc->bmisscount);
2315 sc->bmisscount = 0;
2316 }
2317
2318 /*
2319 * Stop any current dma and put the new frame on the queue.
2320 * This should never fail since we check above that no frames
2321 * are still pending on the queue.
2322 */
2323 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2324 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2325 /* NB: hw still stops DMA, so proceed */
2326 }
fa1c114f 2327
1071db86
BC		 2328 /* refresh the beacon for AP mode */
2329 if (sc->opmode == NL80211_IFTYPE_AP)
2330 ath5k_beacon_update(sc->hw, sc->vif);
2331
c6e387a2
NK		 2332 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2333 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2334 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2335 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2336
cec8db23
BC		 2337 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2338 while (skb) {
2339 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2340 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2341 }
2342
fa1c114f
JS		 2343 sc->bsent++;
2344}
2345
2346
9804b98d
BR		 2347/**
2348 * ath5k_beacon_update_timers - update beacon timers
2349 *
2350 * @sc: struct ath5k_softc pointer we are operating on
2351 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2352 * beacon timer update based on the current HW TSF.
2353 *
2354 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2355 * of a received beacon or the current local hardware TSF and write it to the
2356 * beacon timer registers.
2357 *
2358 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2359 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2360 * when we otherwise know we have to update the timers, but we keep it in this
2361 * function to have it all together in one place.
2362 */
fa1c114f 2363static void
9804b98d 2364ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2365{
2366 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2367 u32 nexttbtt, intval, hw_tu, bc_tu;
2368 u64 hw_tsf;
fa1c114f
JS		 2369
2370 intval = sc->bintval & AR5K_BEACON_PERIOD;
2371 if (WARN_ON(!intval))
2372 return;
2373
9804b98d
BR		 2374 /* beacon TSF converted to TU */
2375 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2376
9804b98d
BR		 2377 /* current TSF converted to TU */
2378 hw_tsf = ath5k_hw_get_tsf64(ah);
2379 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2380
9804b98d
BR		 2381#define FUDGE 3
2382 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2383 if (bc_tsf == -1) {
2384 /*
2385 * no beacons received, called internally.
2386 * just need to refresh timers based on HW TSF.
2387 */
2388 nexttbtt = roundup(hw_tu + FUDGE, intval);
2389 } else if (bc_tsf == 0) {
2390 /*
2391 * no beacon received, probably called by ath5k_reset_tsf().
2392 * reset TSF to start with 0.
2393 */
2394 nexttbtt = intval;
2395 intval |= AR5K_BEACON_RESET_TSF;
2396 } else if (bc_tsf > hw_tsf) {
2397 /*
2398 * beacon received, SW merge happend but HW TSF not yet updated.
2399 * not possible to reconfigure timers yet, but next time we
2400 * receive a beacon with the same BSSID, the hardware will
2401 * automatically update the TSF and then we need to reconfigure
2402 * the timers.
2403 */
2404 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2405 "need to wait for HW TSF sync\n");
2406 return;
2407 } else {
2408 /*
2409 * most important case for beacon synchronization between STA.
2410 *
2411 * beacon received and HW TSF has been already updated by HW.
2412 * update next TBTT based on the TSF of the beacon, but make
2413 * sure it is ahead of our local TSF timer.
2414 */
2415 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2416 }
2417#undef FUDGE
fa1c114f 2418
036cd1ec
BR		 2419 sc->nexttbtt = nexttbtt;
2420
fa1c114f 2421 intval |= AR5K_BEACON_ENA;
fa1c114f 2422 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2423
2424 /*
2425 * debugging output last in order to preserve the time critical aspect
2426 * of this function
2427 */
2428 if (bc_tsf == -1)
2429 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2430 "reconfigured timers based on HW TSF\n");
2431 else if (bc_tsf == 0)
2432 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2433 "reset HW TSF and timers\n");
2434 else
2435 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2436 "updated timers based on beacon TSF\n");
2437
2438 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2439 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2440 (unsigned long long) bc_tsf,
2441 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2442 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2443 intval & AR5K_BEACON_PERIOD,
2444 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2445 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2446}
2447
2448
036cd1ec
BR		 2449/**
2450 * ath5k_beacon_config - Configure the beacon queues and interrupts
2451 *
2452 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2453 *
036cd1ec 2454 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2455 * interrupts to detect TSF updates only.
fa1c114f
JS		 2456 */
2457static void
2458ath5k_beacon_config(struct ath5k_softc *sc)
2459{
2460 struct ath5k_hw *ah = sc->ah;
b5f03956 2461 unsigned long flags;
fa1c114f 2462
21800491 2463 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2464 sc->bmisscount = 0;
dc1968e7 2465 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2466
21800491 2467 if (sc->enable_beacon) {
fa1c114f 2468 /*
036cd1ec
BR		 2469 * In IBSS mode we use a self-linked tx descriptor and let the
2470 * hardware send the beacons automatically. We have to load it
fa1c114f 2471 * only once here.
036cd1ec 2472 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2473 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2474 */
2475 ath5k_beaconq_config(sc);
fa1c114f 2476
036cd1ec
BR		 2477 sc->imask |= AR5K_INT_SWBA;
2478
da966bca 2479 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2480 if (ath5k_hw_hasveol(ah))
da966bca 2481 ath5k_beacon_send(sc);
da966bca
JS		 2482 } else
2483 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 2484 } else {
2485 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 2486 }
fa1c114f 2487
c6e387a2 2488 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2489 mmiowb();
2490 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2491}
2492
428cbd4f
NK		 2493static void ath5k_tasklet_beacon(unsigned long data)
2494{
2495 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2496
2497 /*
2498 * Software beacon alert--time to send a beacon.
2499 *
2500 * In IBSS mode we use this interrupt just to
2501 * keep track of the next TBTT (target beacon
2502 * transmission time) in order to detect wether
2503 * automatic TSF updates happened.
2504 */
2505 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2506 /* XXX: only if VEOL suppported */
2507 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2508 sc->nexttbtt += sc->bintval;
2509 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2510 "SWBA nexttbtt: %x hw_tu: %x "
2511 "TSF: %llx\n",
2512 sc->nexttbtt,
2513 TSF_TO_TU(tsf),
2514 (unsigned long long) tsf);
2515 } else {
2516 spin_lock(&sc->block);
2517 ath5k_beacon_send(sc);
2518 spin_unlock(&sc->block);
2519 }
2520}
2521
fa1c114f
JS		 2522
2523/********************\
2524* Interrupt handling *
2525\********************/
2526
2527static int
bb2becac 2528ath5k_init(struct ath5k_softc *sc)
fa1c114f 2529{
bc1b32d6
EO		 2530 struct ath5k_hw *ah = sc->ah;
2531 int ret, i;
fa1c114f
JS		 2532
2533 mutex_lock(&sc->lock);
2534
2535 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2536
2537 /*
2538 * Stop anything previously setup. This is safe
2539 * no matter this is the first time through or not.
2540 */
2541 ath5k_stop_locked(sc);
2542
2543 /*
2544 * The basic interface to setting the hardware in a good
2545 * state is ``reset''. On return the hardware is known to
2546 * be powered up and with interrupts disabled. This must
2547 * be followed by initialization of the appropriate bits
2548 * and then setup of the interrupt mask.
2549 */
d8ee398d
LR		 2550 sc->curchan = sc->hw->conf.channel;
2551 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2552 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2553 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2111ac0d
BR		 2554 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2555
209d889b 2556 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2557 if (ret)
2558 goto done;
fa1c114f 2559
e6a3b616
TD		 2560 ath5k_rfkill_hw_start(ah);
2561
bc1b32d6
EO		 2562 /*
2563 * Reset the key cache since some parts do not reset the
2564 * contents on initial power up or resume from suspend.
2565 */
2566 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2567 ath5k_hw_reset_key(ah, i);
2568
0edc9a67 2569 ath5k_hw_set_ack_bitrate_high(ah, true);
fa1c114f
JS		 2570 ret = 0;
2571done:
274c7c36 2572 mmiowb();
fa1c114f
JS		 2573 mutex_unlock(&sc->lock);
2574 return ret;
2575}
2576
2577static int
2578ath5k_stop_locked(struct ath5k_softc *sc)
2579{
2580 struct ath5k_hw *ah = sc->ah;
2581
2582 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2583 test_bit(ATH_STAT_INVALID, sc->status));
2584
2585 /*
2586 * Shutdown the hardware and driver:
2587 * stop output from above
2588 * disable interrupts
2589 * turn off timers
2590 * turn off the radio
2591 * clear transmit machinery
2592 * clear receive machinery
2593 * drain and release tx queues
2594 * reclaim beacon resources
2595 * power down hardware
2596 *
2597 * Note that some of this work is not possible if the
2598 * hardware is gone (invalid).
2599 */
2600 ieee80211_stop_queues(sc->hw);
2601
2602 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2603 ath5k_led_off(sc);
c6e387a2 2604 ath5k_hw_set_imr(ah, 0);
274c7c36 2605 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2606 }
2607 ath5k_txq_cleanup(sc);
2608 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2609 ath5k_rx_stop(sc);
2610 ath5k_hw_phy_disable(ah);
2611 } else
2612 sc->rxlink = NULL;
2613
2614 return 0;
2615}
2616
2617/*
2618 * Stop the device, grabbing the top-level lock to protect
2619 * against concurrent entry through ath5k_init (which can happen
2620 * if another thread does a system call and the thread doing the
2621 * stop is preempted).
2622 */
2623static int
bb2becac 2624ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2625{
2626 int ret;
2627
2628 mutex_lock(&sc->lock);
2629 ret = ath5k_stop_locked(sc);
2630 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2631 /*
edd7fc70
NK		 2632 * Don't set the card in full sleep mode!
2633 *
2634 * a) When the device is in this state it must be carefully
2635 * woken up or references to registers in the PCI clock
2636 * domain may freeze the bus (and system). This varies
2637 * by chip and is mostly an issue with newer parts
2638 * (madwifi sources mentioned srev >= 0x78) that go to
2639 * sleep more quickly.
2640 *
2641 * b) On older chips full sleep results a weird behaviour
2642 * during wakeup. I tested various cards with srev < 0x78
2643 * and they don't wake up after module reload, a second
2644 * module reload is needed to bring the card up again.
2645 *
2646 * Until we figure out what's going on don't enable
2647 * full chip reset on any chip (this is what Legacy HAL
2648 * and Sam's HAL do anyway). Instead Perform a full reset
2649 * on the device (same as initial state after attach) and
2650 * leave it idle (keep MAC/BB on warm reset) */
2651 ret = ath5k_hw_on_hold(sc->ah);
2652
2653 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2654 "putting device to sleep\n");
fa1c114f 2655 }
9e4e43f2 2656 ath5k_txbuf_free_skb(sc, sc->bbuf);
8bdd5b9c 2657
274c7c36 2658 mmiowb();
fa1c114f
JS		 2659 mutex_unlock(&sc->lock);
2660
10488f8a
JS		 2661 tasklet_kill(&sc->rxtq);
2662 tasklet_kill(&sc->txtq);
2663 tasklet_kill(&sc->restq);
6e220662 2664 tasklet_kill(&sc->calib);
acf3c1a5 2665 tasklet_kill(&sc->beacontq);
2111ac0d 2666 tasklet_kill(&sc->ani_tasklet);
fa1c114f 2667
e6a3b616
TD		 2668 ath5k_rfkill_hw_stop(sc->ah);
2669
fa1c114f
JS		 2670 return ret;
2671}
2672
6a8a3f6b
BR		 2673static void
2674ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2675{
2111ac0d
BR		 2676 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2677 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2678 /* run ANI only when full calibration is not active */
2679 ah->ah_cal_next_ani = jiffies +
2680 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2681 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2682
2683 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2684 ah->ah_cal_next_full = jiffies +
2685 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2686 tasklet_schedule(&ah->ah_sc->calib);
2687 }
2688 /* we could use SWI to generate enough interrupts to meet our
2689 * calibration interval requirements, if necessary:
2690 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2691}
2692
fa1c114f
JS		 2693static irqreturn_t
2694ath5k_intr(int irq, void *dev_id)
2695{
2696 struct ath5k_softc *sc = dev_id;
2697 struct ath5k_hw *ah = sc->ah;
2698 enum ath5k_int status;
2699 unsigned int counter = 1000;
2700
2701 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2702 !ath5k_hw_is_intr_pending(ah)))
2703 return IRQ_NONE;
2704
2705 do {
fa1c114f
JS		 2706 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2707 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2708 status, sc->imask);
fa1c114f
JS		 2709 if (unlikely(status & AR5K_INT_FATAL)) {
2710 /*
2711 * Fatal errors are unrecoverable.
2712 * Typically these are caused by DMA errors.
2713 */
8d67a031
BR		 2714 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2715 "fatal int, resetting\n");
fa1c114f
JS		 2716 tasklet_schedule(&sc->restq);
2717 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2718 /*
2719 * Receive buffers are full. Either the bus is busy or
2720 * the CPU is not fast enough to process all received
2721 * frames.
2722 * Older chipsets need a reset to come out of this
2723 * condition, but we treat it as RX for newer chips.
2724 * We don't know exactly which versions need a reset -
2725 * this guess is copied from the HAL.
2726 */
2727 sc->stats.rxorn_intr++;
8d67a031
BR		 2728 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2729 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2730 "rx overrun, resetting\n");
87d77c4e 2731 tasklet_schedule(&sc->restq);
8d67a031 2732 }
87d77c4e
BR		 2733 else
2734 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2735 } else {
2736 if (status & AR5K_INT_SWBA) {
56d2ac76 2737 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2738 }
2739 if (status & AR5K_INT_RXEOL) {
2740 /*
2741 * NB: the hardware should re-read the link when
2742 * RXE bit is written, but it doesn't work at
2743 * least on older hardware revs.
2744 */
2745 sc->rxlink = NULL;
2746 }
2747 if (status & AR5K_INT_TXURN) {
2748 /* bump tx trigger level */
2749 ath5k_hw_update_tx_triglevel(ah, true);
2750 }
4c674c60 2751 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2752 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2753 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2754 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2755 tasklet_schedule(&sc->txtq);
2756 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2757 /* TODO */
fa1c114f
JS		 2758 }
2759 if (status & AR5K_INT_MIB) {
2111ac0d 2760 sc->stats.mib_intr++;
495391d7 2761 ath5k_hw_update_mib_counters(ah);
2111ac0d 2762 ath5k_ani_mib_intr(ah);
fa1c114f 2763 }
e6a3b616 2764 if (status & AR5K_INT_GPIO)
e6a3b616 2765 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2766
fa1c114f 2767 }
2516baa6 2768 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2769
2770 if (unlikely(!counter))
2771 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2772
6a8a3f6b 2773 ath5k_intr_calibration_poll(ah);
6e220662 2774
fa1c114f
JS		 2775 return IRQ_HANDLED;
2776}
2777
2778static void
2779ath5k_tasklet_reset(unsigned long data)
2780{
2781 struct ath5k_softc *sc = (void *)data;
2782
397f385b 2783 ath5k_reset(sc, sc->curchan);
fa1c114f
JS		 2784}
2785
2786/*
2787 * Periodically recalibrate the PHY to account
2788 * for temperature/environment changes.
2789 */
2790static void
6e220662 2791ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2792{
2793 struct ath5k_softc *sc = (void *)data;
2794 struct ath5k_hw *ah = sc->ah;
2795
6e220662 2796 /* Only full calibration for now */
e65e1d77 2797 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2798
fa1c114f 2799 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2800 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2801 sc->curchan->hw_value);
fa1c114f 2802
6f3b414a 2803 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2804 /*
2805 * Rfgain is out of bounds, reset the chip
2806 * to load new gain values.
2807 */
2808 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
6b5d117e 2809 ath5k_reset(sc, sc->curchan);
fa1c114f
JS		 2810 }
2811 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2812 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2813 ieee80211_frequency_to_channel(
2814 sc->curchan->center_freq));
fa1c114f 2815
0e8e02dd 2816 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
afe86286
BR		 2817 * doesn't. We stop the queues so that calibration doesn't interfere
2818 * with TX and don't run it as often */
2819 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2820 ah->ah_cal_next_nf = jiffies +
2821 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
2822 ieee80211_stop_queues(sc->hw);
2823 ath5k_hw_update_noise_floor(ah);
2824 ieee80211_wake_queues(sc->hw);
2825 }
6e220662 2826
e65e1d77 2827 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2828}
2829
2830
2111ac0d
BR		 2831static void
2832ath5k_tasklet_ani(unsigned long data)
2833{
2834 struct ath5k_softc *sc = (void *)data;
2835 struct ath5k_hw *ah = sc->ah;
2836
2837 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2838 ath5k_ani_calibration(ah);
2839 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2840}
2841
2842
fa1c114f
JS		 2843/********************\
2844* Mac80211 functions *
2845\********************/
2846
2847static int
e039fa4a 2848ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
cec8db23
BC		 2849{
2850 struct ath5k_softc *sc = hw->priv;
2851
2852 return ath5k_tx_queue(hw, skb, sc->txq);
2853}
2854
2855static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2856 struct ath5k_txq *txq)
fa1c114f
JS		 2857{
2858 struct ath5k_softc *sc = hw->priv;
2859 struct ath5k_buf *bf;
2860 unsigned long flags;
0fe45b1d 2861 int padsize;
fa1c114f
JS		 2862
2863 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2864
05c914fe 2865 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2866 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2867
2868 /*
2869 * the hardware expects the header padded to 4 byte boundaries
2870 * if this is not the case we add the padding after the header
2871 */
8127fbdc
BP		 2872 padsize = ath5k_add_padding(skb);
2873 if (padsize < 0) {
2874 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
2875 " headroom to pad");
2876 goto drop_packet;
fa1c114f
JS		 2877 }
2878
fa1c114f
JS		 2879 spin_lock_irqsave(&sc->txbuflock, flags);
2880 if (list_empty(&sc->txbuf)) {
2881 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2882 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2883 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2884 goto drop_packet;
fa1c114f
JS		 2885 }
2886 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2887 list_del(&bf->list);
2888 sc->txbuf_len--;
2889 if (list_empty(&sc->txbuf))
2890 ieee80211_stop_queues(hw);
2891 spin_unlock_irqrestore(&sc->txbuflock, flags);
2892
2893 bf->skb = skb;
2894
8127fbdc 2895 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
fa1c114f
JS		 2896 bf->skb = NULL;
2897 spin_lock_irqsave(&sc->txbuflock, flags);
2898 list_add_tail(&bf->list, &sc->txbuf);
2899 sc->txbuf_len++;
2900 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2901 goto drop_packet;
fa1c114f 2902 }
5a0fe8ac 2903 return NETDEV_TX_OK;
fa1c114f 2904
5a0fe8ac
BC		 2905drop_packet:
2906 dev_kfree_skb_any(skb);
71ef99c8 2907 return NETDEV_TX_OK;
fa1c114f
JS		 2908}
2909
209d889b
BC		 2910/*
2911 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2912 * and change to the given channel.
2913 */
fa1c114f 2914static int
209d889b 2915ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2916{
fa1c114f
JS		 2917 struct ath5k_hw *ah = sc->ah;
2918 int ret;
2919
2920 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2921
209d889b 2922 if (chan) {
c6e387a2 2923 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2924 ath5k_txq_cleanup(sc);
2925 ath5k_rx_stop(sc);
209d889b
BC		 2926
2927 sc->curchan = chan;
2928 sc->curband = &sc->sbands[chan->band];
d7dc1003 2929 }
3355443a 2930 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2931 if (ret) {
fa1c114f
JS		 2932 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2933 goto err;
2934 }
d7dc1003 2935
fa1c114f 2936 ret = ath5k_rx_start(sc);
d7dc1003 2937 if (ret) {
fa1c114f
JS		 2938 ATH5K_ERR(sc, "can't start recv logic\n");
2939 goto err;
2940 }
d7dc1003 2941
2111ac0d
BR		 2942 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2943
ac559526
BR		 2944 ah->ah_cal_next_full = jiffies;
2945 ah->ah_cal_next_ani = jiffies;
afe86286
BR		 2946 ah->ah_cal_next_nf = jiffies;
2947
fa1c114f 2948 /*
d7dc1003
JS		 2949 * Change channels and update the h/w rate map if we're switching;
2950 * e.g. 11a to 11b/g.
2951 *
2952 * We may be doing a reset in response to an ioctl that changes the
2953 * channel so update any state that might change as a result.
fa1c114f
JS		 2954 *
2955 * XXX needed?
2956 */
2957/* ath5k_chan_change(sc, c); */
fa1c114f 2958
d7dc1003
JS		 2959 ath5k_beacon_config(sc);
2960 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2961
397f385b
BR		 2962 ieee80211_wake_queues(sc->hw);
2963
fa1c114f
JS		 2964 return 0;
2965err:
2966 return ret;
2967}
2968
2969static int ath5k_start(struct ieee80211_hw *hw)
2970{
bb2becac 2971 return ath5k_init(hw->priv);
fa1c114f
JS		 2972}
2973
2974static void ath5k_stop(struct ieee80211_hw *hw)
2975{
bb2becac 2976 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2977}
2978
2979static int ath5k_add_interface(struct ieee80211_hw *hw,
1ed32e4f 2980 struct ieee80211_vif *vif)
fa1c114f
JS		 2981{
2982 struct ath5k_softc *sc = hw->priv;
2983 int ret;
2984
2985 mutex_lock(&sc->lock);
32bfd35d 2986 if (sc->vif) {
fa1c114f
JS		 2987 ret = 0;
2988 goto end;
2989 }
2990
1ed32e4f 2991 sc->vif = vif;
fa1c114f 2992
1ed32e4f 2993 switch (vif->type) {
da966bca 2994 case NL80211_IFTYPE_AP:
05c914fe
JB		 2995 case NL80211_IFTYPE_STATION:
2996 case NL80211_IFTYPE_ADHOC:
b706e65b 2997 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2998 case NL80211_IFTYPE_MONITOR:
1ed32e4f 2999 sc->opmode = vif->type;
fa1c114f
JS		 3000 break;
3001 default:
3002 ret = -EOPNOTSUPP;
3003 goto end;
3004 }
67d2e2df 3005
ccfe5552
BR		 3006 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
3007
1ed32e4f 3008 ath5k_hw_set_lladdr(sc->ah, vif->addr);
ae6f53f2 3009 ath5k_mode_setup(sc);
67d2e2df 3010
fa1c114f
JS		 3011 ret = 0;
3012end:
3013 mutex_unlock(&sc->lock);
3014 return ret;
3015}
3016
3017static void
3018ath5k_remove_interface(struct ieee80211_hw *hw,
1ed32e4f 3019 struct ieee80211_vif *vif)
fa1c114f
JS		 3020{
3021 struct ath5k_softc *sc = hw->priv;
0e149cf5 3022 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 3023
3024 mutex_lock(&sc->lock);
1ed32e4f 3025 if (sc->vif != vif)
fa1c114f
JS		 3026 goto end;
3027
0e149cf5 3028 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 3029 sc->vif = NULL;
fa1c114f
JS		 3030end:
3031 mutex_unlock(&sc->lock);
3032}
3033
d8ee398d
LR		 3034/*
3035 * TODO: Phy disable/diversity etc
3036 */
fa1c114f 3037static int
e8975581 3038ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 3039{
3040 struct ath5k_softc *sc = hw->priv;
a0823810 3041 struct ath5k_hw *ah = sc->ah;
e8975581 3042 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 3043 int ret = 0;
be009370
BC		 3044
3045 mutex_lock(&sc->lock);
fa1c114f 3046
e30eb4ab
JA		 3047 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3048 ret = ath5k_chan_set(sc, conf->channel);
3049 if (ret < 0)
3050 goto unlock;
3051 }
2bed03eb 3052
a0823810
NK		 3053 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
3054 (sc->power_level != conf->power_level)) {
3055 sc->power_level = conf->power_level;
3056
3057 /* Half dB steps */
3058 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
3059 }
fa1c114f 3060
2bed03eb
NK		 3061 /* TODO:
3062 * 1) Move this on config_interface and handle each case
3063 * separately eg. when we have only one STA vif, use
3064 * AR5K_ANTMODE_SINGLE_AP
3065 *
3066 * 2) Allow the user to change antenna mode eg. when only
3067 * one antenna is present
3068 *
3069 * 3) Allow the user to set default/tx antenna when possible
3070 *
3071 * 4) Default mode should handle 90% of the cases, together
3072 * with fixed a/b and single AP modes we should be able to
3073 * handle 99%. Sectored modes are extreme cases and i still
3074 * haven't found a usage for them. If we decide to support them,
3075 * then we must allow the user to set how many tx antennas we
3076 * have available
3077 */
caec9112 3078 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 3079
55aa4e0f 3080unlock:
be009370 3081 mutex_unlock(&sc->lock);
55aa4e0f 3082 return ret;
fa1c114f
JS		 3083}
3084
3ac64bee 3085static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 3086 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 3087{
3088 u32 mfilt[2], val;
3ac64bee 3089 u8 pos;
22bedad3 3090 struct netdev_hw_addr *ha;
3ac64bee
JB		 3091
3092 mfilt[0] = 0;
3093 mfilt[1] = 1;
3094
22bedad3 3095 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 3096 /* calculate XOR of eight 6-bit values */
22bedad3 3097 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 3098 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 3099 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 3100 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3101 pos &= 0x3f;
3102 mfilt[pos / 32] |= (1 << (pos % 32));
3103 /* XXX: we might be able to just do this instead,
3104 * but not sure, needs testing, if we do use this we'd
3105 * neet to inform below to not reset the mcast */
3106 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 3107 * ha->addr[5]); */
3ac64bee
JB		 3108 }
3109
3110 return ((u64)(mfilt[1]) << 32) | mfilt[0];
3111}
3112
fa1c114f
JS		 3113#define SUPPORTED_FIF_FLAGS \
3114 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3115 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3116 FIF_BCN_PRBRESP_PROMISC
3117/*
3118 * o always accept unicast, broadcast, and multicast traffic
3119 * o multicast traffic for all BSSIDs will be enabled if mac80211
3120 * says it should be
3121 * o maintain current state of phy ofdm or phy cck error reception.
3122 * If the hardware detects any of these type of errors then
3123 * ath5k_hw_get_rx_filter() will pass to us the respective
3124 * hardware filters to be able to receive these type of frames.
3125 * o probe request frames are accepted only when operating in
3126 * hostap, adhoc, or monitor modes
3127 * o enable promiscuous mode according to the interface state
3128 * o accept beacons:
3129 * - when operating in adhoc mode so the 802.11 layer creates
3130 * node table entries for peers,
3131 * - when operating in station mode for collecting rssi data when
3132 * the station is otherwise quiet, or
3133 * - when scanning
3134 */
3135static void ath5k_configure_filter(struct ieee80211_hw *hw,
3136 unsigned int changed_flags,
3137 unsigned int *new_flags,
3ac64bee 3138 u64 multicast)
fa1c114f
JS		 3139{
3140 struct ath5k_softc *sc = hw->priv;
3141 struct ath5k_hw *ah = sc->ah;
3ac64bee 3142 u32 mfilt[2], rfilt;
fa1c114f 3143
56d1de0a
BC		 3144 mutex_lock(&sc->lock);
3145
3ac64bee
JB		 3146 mfilt[0] = multicast;
3147 mfilt[1] = multicast >> 32;
fa1c114f
JS		 3148
3149 /* Only deal with supported flags */
3150 changed_flags &= SUPPORTED_FIF_FLAGS;
3151 *new_flags &= SUPPORTED_FIF_FLAGS;
3152
3153 /* If HW detects any phy or radar errors, leave those filters on.
3154 * Also, always enable Unicast, Broadcasts and Multicast
3155 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3156 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
3157 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
3158 AR5K_RX_FILTER_MCAST);
3159
3160 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
3161 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 3162 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3163 } else {
fa1c114f 3164 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 3165 }
fa1c114f
JS		 3166 }
3167
6b5dcccb
BC		 3168 if (test_bit(ATH_STAT_PROMISC, sc->status))
3169 rfilt |= AR5K_RX_FILTER_PROM;
3170
fa1c114f
JS		 3171 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3172 if (*new_flags & FIF_ALLMULTI) {
3173 mfilt[0] = ~0;
3174 mfilt[1] = ~0;
fa1c114f
JS		 3175 }
3176
3177 /* This is the best we can do */
3178 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
3179 rfilt |= AR5K_RX_FILTER_PHYERR;
3180
3181 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3182 * and probes for any BSSID, this needs testing */
3183 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3184 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3185
3186 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3187 * set we should only pass on control frames for this
3188 * station. This needs testing. I believe right now this
3189 * enables *all* control frames, which is OK.. but
3190 * but we should see if we can improve on granularity */
3191 if (*new_flags & FIF_CONTROL)
3192 rfilt |= AR5K_RX_FILTER_CONTROL;
3193
3194 /* Additional settings per mode -- this is per ath5k */
3195
3196 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3197
56d1de0a
BC		 3198 switch (sc->opmode) {
3199 case NL80211_IFTYPE_MESH_POINT:
3200 case NL80211_IFTYPE_MONITOR:
3201 rfilt |= AR5K_RX_FILTER_CONTROL |
3202 AR5K_RX_FILTER_BEACON |
3203 AR5K_RX_FILTER_PROBEREQ |
3204 AR5K_RX_FILTER_PROM;
3205 break;
3206 case NL80211_IFTYPE_AP:
3207 case NL80211_IFTYPE_ADHOC:
3208 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3209 AR5K_RX_FILTER_BEACON;
3210 break;
3211 case NL80211_IFTYPE_STATION:
3212 if (sc->assoc)
3213 rfilt |= AR5K_RX_FILTER_BEACON;
3214 default:
3215 break;
3216 }
fa1c114f
JS		 3217
3218 /* Set filters */
0bbac08f 3219 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 3220
3221 /* Set multicast bits */
3222 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3223 /* Set the cached hw filter flags, this will alter actually
3224 * be set in HW */
3225 sc->filter_flags = rfilt;
56d1de0a
BC		 3226
3227 mutex_unlock(&sc->lock);
fa1c114f
JS		 3228}
3229
3230static int
3231ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 3232 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3233 struct ieee80211_key_conf *key)
fa1c114f
JS		 3234{
3235 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 3236 struct ath5k_hw *ah = sc->ah;
3237 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 3238 int ret = 0;
3239
9ad9a26e
BC		 3240 if (modparam_nohwcrypt)
3241 return -EOPNOTSUPP;
3242
65b5a698
BC		 3243 if (sc->opmode == NL80211_IFTYPE_AP)
3244 return -EOPNOTSUPP;
3245
0bbac08f 3246 switch (key->alg) {
fa1c114f 3247 case ALG_WEP:
fa1c114f 3248 case ALG_TKIP:
3f64b435 3249 break;
fa1c114f 3250 case ALG_CCMP:
1c818740
BC		 3251 if (sc->ah->ah_aes_support)
3252 break;
3253
fa1c114f
JS		 3254 return -EOPNOTSUPP;
3255 default:
3256 WARN_ON(1);
3257 return -EINVAL;
3258 }
3259
3260 mutex_lock(&sc->lock);
3261
3262 switch (cmd) {
3263 case SET_KEY:
dc822b5d
JB		 3264 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3265 sta ? sta->addr : NULL);
fa1c114f
JS		 3266 if (ret) {
3267 ATH5K_ERR(sc, "can't set the key\n");
3268 goto unlock;
3269 }
dc1e001b 3270 __set_bit(key->keyidx, common->keymap);
fa1c114f 3271 key->hw_key_idx = key->keyidx;
3f64b435
BC		 3272 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3273 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 3274 break;
3275 case DISABLE_KEY:
3276 ath5k_hw_reset_key(sc->ah, key->keyidx);
dc1e001b 3277 __clear_bit(key->keyidx, common->keymap);
fa1c114f
JS		 3278 break;
3279 default:
3280 ret = -EINVAL;
3281 goto unlock;
3282 }
3283
3284unlock:
274c7c36 3285 mmiowb();
fa1c114f
JS		 3286 mutex_unlock(&sc->lock);
3287 return ret;
3288}
3289
3290static int
3291ath5k_get_stats(struct ieee80211_hw *hw,
3292 struct ieee80211_low_level_stats *stats)
3293{
3294 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3295
3296 /* Force update */
495391d7 3297 ath5k_hw_update_mib_counters(sc->ah);
fa1c114f 3298
495391d7
BR		 3299 stats->dot11ACKFailureCount = sc->stats.ack_fail;
3300 stats->dot11RTSFailureCount = sc->stats.rts_fail;
3301 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
3302 stats->dot11FCSErrorCount = sc->stats.fcs_error;
fa1c114f
JS		 3303
3304 return 0;
3305}
3306
55ee82b5
HS		 3307static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
3308 struct survey_info *survey)
3309{
3310 struct ath5k_softc *sc = hw->priv;
3311 struct ieee80211_conf *conf = &hw->conf;
3312
3313 if (idx != 0)
3314 return -ENOENT;
3315
3316 survey->channel = conf->channel;
3317 survey->filled = SURVEY_INFO_NOISE_DBM;
3318 survey->noise = sc->ah->ah_noise_floor;
3319
3320 return 0;
3321}
3322
fa1c114f
JS		 3323static u64
3324ath5k_get_tsf(struct ieee80211_hw *hw)
3325{
3326 struct ath5k_softc *sc = hw->priv;
3327
3328 return ath5k_hw_get_tsf64(sc->ah);
3329}
3330
3b5d665b
AF		 3331static void
3332ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3333{
3334 struct ath5k_softc *sc = hw->priv;
3335
3336 ath5k_hw_set_tsf64(sc->ah, tsf);
3337}
3338
fa1c114f
JS		 3339static void
3340ath5k_reset_tsf(struct ieee80211_hw *hw)
3341{
3342 struct ath5k_softc *sc = hw->priv;
3343
9804b98d
BR		 3344 /*
3345 * in IBSS mode we need to update the beacon timers too.
3346 * this will also reset the TSF if we call it with 0
3347 */
05c914fe 3348 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3349 ath5k_beacon_update_timers(sc, 0);
3350 else
3351 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3352}
3353
1071db86
BC		 3354/*
3355 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3356 * this is called only once at config_bss time, for AP we do it every
3357 * SWBA interrupt so that the TIM will reflect buffered frames.
3358 *
3359 * Called with the beacon lock.
3360 */
fa1c114f 3361static int
1071db86 3362ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3363{
fa1c114f 3364 int ret;
1071db86 3365 struct ath5k_softc *sc = hw->priv;
72828b1b
BC		 3366 struct sk_buff *skb;
3367
3368 if (WARN_ON(!vif)) {
3369 ret = -EINVAL;
3370 goto out;
3371 }
3372
3373 skb = ieee80211_beacon_get(hw, vif);
1071db86
BC		 3374
3375 if (!skb) {
3376 ret = -ENOMEM;
3377 goto out;
3378 }
fa1c114f
JS		 3379
3380 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3381
9e4e43f2 3382 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 3383 sc->bbuf->skb = skb;
e039fa4a 3384 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3385 if (ret)
3386 sc->bbuf->skb = NULL;
1071db86
BC		 3387out:
3388 return ret;
3389}
3390
02969b38
MX		 3391static void
3392set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3393{
3394 struct ath5k_softc *sc = hw->priv;
3395 struct ath5k_hw *ah = sc->ah;
3396 u32 rfilt;
3397 rfilt = ath5k_hw_get_rx_filter(ah);
3398 if (enable)
3399 rfilt |= AR5K_RX_FILTER_BEACON;
3400 else
3401 rfilt &= ~AR5K_RX_FILTER_BEACON;
3402 ath5k_hw_set_rx_filter(ah, rfilt);
3403 sc->filter_flags = rfilt;
3404}
fa1c114f 3405
02969b38
MX		 3406static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3407 struct ieee80211_vif *vif,
3408 struct ieee80211_bss_conf *bss_conf,
3409 u32 changes)
3410{
3411 struct ath5k_softc *sc = hw->priv;
2d0ddec5 3412 struct ath5k_hw *ah = sc->ah;
954fecea 3413 struct ath_common *common = ath5k_hw_common(ah);
21800491 3414 unsigned long flags;
2d0ddec5
JB		 3415
3416 mutex_lock(&sc->lock);
3417 if (WARN_ON(sc->vif != vif))
3418 goto unlock;
3419
3420 if (changes & BSS_CHANGED_BSSID) {
3421 /* Cache for later use during resets */
954fecea 3422 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
8ce54c5a 3423 common->curaid = 0;
be5d6b75 3424 ath5k_hw_set_associd(ah);
2d0ddec5
JB		 3425 mmiowb();
3426 }
57c4d7b4
JB		 3427
3428 if (changes & BSS_CHANGED_BEACON_INT)
3429 sc->bintval = bss_conf->beacon_int;
3430
02969b38 3431 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3432 sc->assoc = bss_conf->assoc;
3433 if (sc->opmode == NL80211_IFTYPE_STATION)
3434 set_beacon_filter(hw, sc->assoc);
f0f3d388
BC		 3435 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3436 AR5K_LED_ASSOC : AR5K_LED_INIT);
8ce54c5a
LR		 3437 if (bss_conf->assoc) {
3438 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3439 "Bss Info ASSOC %d, bssid: %pM\n",
3440 bss_conf->aid, common->curbssid);
3441 common->curaid = bss_conf->aid;
3442 ath5k_hw_set_associd(ah);
3443 /* Once ANI is available you would start it here */
3444 }
02969b38 3445 }
2d0ddec5 3446
21800491
BC		 3447 if (changes & BSS_CHANGED_BEACON) {
3448 spin_lock_irqsave(&sc->block, flags);
3449 ath5k_beacon_update(hw, vif);
3450 spin_unlock_irqrestore(&sc->block, flags);
2d0ddec5
JB		 3451 }
3452
21800491
BC		 3453 if (changes & BSS_CHANGED_BEACON_ENABLED)
3454 sc->enable_beacon = bss_conf->enable_beacon;
3455
3456 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3457 BSS_CHANGED_BEACON_INT))
3458 ath5k_beacon_config(sc);
3459
2d0ddec5
JB		 3460 unlock:
3461 mutex_unlock(&sc->lock);
02969b38 3462}
f0f3d388
BC		 3463
3464static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3465{
3466 struct ath5k_softc *sc = hw->priv;
3467 if (!sc->assoc)
3468 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3469}
3470
3471static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3472{
3473 struct ath5k_softc *sc = hw->priv;
3474 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3475 AR5K_LED_ASSOC : AR5K_LED_INIT);
3476}
6e08d228
LT		 3477
3478/**
3479 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3480 *
3481 * @hw: struct ieee80211_hw pointer
3482 * @coverage_class: IEEE 802.11 coverage class number
3483 *
3484 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3485 * coverage class. The values are persistent, they are restored after device
3486 * reset.
3487 */
3488static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3489{
3490 struct ath5k_softc *sc = hw->priv;
3491
3492 mutex_lock(&sc->lock);
3493 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3494 mutex_unlock(&sc->lock);
3495}
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