[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / attach.c

/*
 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
 *
 * Permission to use, copy, modify, and distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

/*************************************\
* Attach/Detach Functions and helpers *
\*************************************/

#include <linux/pci.h>
#include "ath5k.h"
#include "reg.h"
#include "debug.h"
#include "base.h"

/**
 * ath5k_hw_post - Power On Self Test helper function
 *
 * @ah: The &struct ath5k_hw
 */
static int ath5k_hw_post(struct ath5k_hw *ah)
{

	static const u32 static_pattern[4] = {
		0x55555555,	0xaaaaaaaa,
		0x66666666,	0x99999999
	};
	static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
	int i, c;
	u16 cur_reg;
	u32 var_pattern;
	u32 init_val;
	u32 cur_val;

	for (c = 0; c < 2; c++) {

		cur_reg = regs[c];

		/* Save previous value */
		init_val = ath5k_hw_reg_read(ah, cur_reg);

		for (i = 0; i < 256; i++) {
			var_pattern = i << 16 | i;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
			cur_val = ath5k_hw_reg_read(ah, cur_reg);

			if (cur_val != var_pattern) {
				ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
				return -EAGAIN;
			}

			/* Found on ndiswrapper dumps */
			var_pattern = 0x0039080f;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
		}

		for (i = 0; i < 4; i++) {
			var_pattern = static_pattern[i];
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
			cur_val = ath5k_hw_reg_read(ah, cur_reg);

			if (cur_val != var_pattern) {
				ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
				return -EAGAIN;
			}

			/* Found on ndiswrapper dumps */
			var_pattern = 0x003b080f;
			ath5k_hw_reg_write(ah, var_pattern, cur_reg);
		}

		/* Restore previous value */
		ath5k_hw_reg_write(ah, init_val, cur_reg);

	}

	return 0;

}

/**
 * ath5k_hw_attach - Check if hw is supported and init the needed structs
 *
 * @sc: The &struct ath5k_softc we got from the driver's attach function
 *
 * Check if the device is supported, perform a POST and initialize the needed
 * structs. Returns -ENOMEM if we don't have memory for the needed structs,
 * -ENODEV if the device is not supported or prints an error msg if something
 * else went wrong.
 */
int ath5k_hw_attach(struct ath5k_softc *sc)
{
	struct ath5k_hw *ah = sc->ah;
	struct ath_common *common = ath5k_hw_common(ah);
	struct pci_dev *pdev = sc->pdev;
	struct ath5k_eeprom_info *ee;
	int ret;
	u32 srev;

	/*
	 * HW information
	 */
	ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
	ah->ah_turbo = false;
	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
	ah->ah_imr = 0;
	ah->ah_atim_window = 0;
	ah->ah_aifs = AR5K_TUNE_AIFS;
	ah->ah_cw_min = AR5K_TUNE_CWMIN;
	ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
	ah->ah_software_retry = false;
	ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
	ah->ah_noise_floor = -95;	/* until first NF calibration is run */

	/*
	 * Find the mac version
	 */
	srev = ath5k_hw_reg_read(ah, AR5K_SREV);
	if (srev < AR5K_SREV_AR5311)
		ah->ah_version = AR5K_AR5210;
	else if (srev < AR5K_SREV_AR5212)
		ah->ah_version = AR5K_AR5211;
	else
		ah->ah_version = AR5K_AR5212;

	/*Fill the ath5k_hw struct with the needed functions*/
	ret = ath5k_hw_init_desc_functions(ah);
	if (ret)
		goto err_free;

	/* Bring device out of sleep and reset it's units */
	ret = ath5k_hw_nic_wakeup(ah, 0, true);
	if (ret)
		goto err_free;

	/* Get MAC, PHY and RADIO revisions */
	ah->ah_mac_srev = srev;
	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
			0xffffffff;
	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
			CHANNEL_5GHZ);
	ah->ah_phy = AR5K_PHY(0);

	/* Try to identify radio chip based on it's srev */
	switch (ah->ah_radio_5ghz_revision & 0xf0) {
	case AR5K_SREV_RAD_5111:
		ah->ah_radio = AR5K_RF5111;
		ah->ah_single_chip = false;
		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							CHANNEL_2GHZ);
		break;
	case AR5K_SREV_RAD_5112:
	case AR5K_SREV_RAD_2112:
		ah->ah_radio = AR5K_RF5112;
		ah->ah_single_chip = false;
		ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
							CHANNEL_2GHZ);
		break;
	case AR5K_SREV_RAD_2413:
		ah->ah_radio = AR5K_RF2413;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_5413:
		ah->ah_radio = AR5K_RF5413;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_2316:
		ah->ah_radio = AR5K_RF2316;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_2317:
		ah->ah_radio = AR5K_RF2317;
		ah->ah_single_chip = true;
		break;
	case AR5K_SREV_RAD_5424:
		if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
		ah->ah_mac_version == AR5K_SREV_AR2417){
			ah->ah_radio = AR5K_RF2425;
			ah->ah_single_chip = true;
		} else {
			ah->ah_radio = AR5K_RF5413;
			ah->ah_single_chip = true;
		}
		break;
	default:
		/* Identify radio based on mac/phy srev */
		if (ah->ah_version == AR5K_AR5210) {
			ah->ah_radio = AR5K_RF5110;
			ah->ah_single_chip = false;
		} else if (ah->ah_version == AR5K_AR5211) {
			ah->ah_radio = AR5K_RF5111;
			ah->ah_single_chip = false;
			ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
								CHANNEL_2GHZ);
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
		ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
		ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
			ah->ah_radio = AR5K_RF2425;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
		} else if (srev == AR5K_SREV_AR5213A &&
		ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
			ah->ah_radio = AR5K_RF5112;
			ah->ah_single_chip = false;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
			ah->ah_radio = AR5K_RF2316;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
		ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
			ah->ah_radio = AR5K_RF5413;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
		} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
		ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
			ah->ah_radio = AR5K_RF2413;
			ah->ah_single_chip = true;
			ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
		} else {
			ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
			ret = -ENODEV;
			goto err_free;
		}
	}


	/* Return on unsuported chips (unsupported eeprom etc) */
	if ((srev >= AR5K_SREV_AR5416) &&
	(srev < AR5K_SREV_AR2425)) {
		ATH5K_ERR(sc, "Device not yet supported.\n");
		ret = -ENODEV;
		goto err_free;
	}

	/*
	 * POST
	 */
	ret = ath5k_hw_post(ah);
	if (ret)
		goto err_free;

	/* Enable pci core retry fix on Hainan (5213A) and later chips */
	if (srev >= AR5K_SREV_AR5213A)
		AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);

	/*
	 * Get card capabilities, calibration values etc
	 * TODO: EEPROM work
	 */
	ret = ath5k_eeprom_init(ah);
	if (ret) {
		ATH5K_ERR(sc, "unable to init EEPROM\n");
		goto err_free;
	}

	ee = &ah->ah_capabilities.cap_eeprom;

	/*
	 * Write PCI-E power save settings
	 */
	if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
		ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);

		/* Shut off RX when elecidle is asserted */
		ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);

		/* If serdes programing is enabled, increase PCI-E
		 * tx power for systems with long trace from host
		 * to minicard connector. */
		if (ee->ee_serdes)
			ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
		else
			ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);

		/* Shut off PLL and CLKREQ active in L1 */
		ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);

		/* Preserve other settings */
		ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
		ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);

		/* Reset SERDES to load new settings */
		ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
		mdelay(1);
	}

	/* Get misc capabilities */
	ret = ath5k_hw_set_capabilities(ah);
	if (ret) {
		ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
			sc->pdev->device);
		goto err_free;
	}

	/* Crypto settings */
	ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 &&
		(ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
		 !AR5K_EEPROM_AES_DIS(ee->ee_misc5));

	if (srev >= AR5K_SREV_AR2414) {
		ah->ah_combined_mic = true;
		AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
			AR5K_MISC_MODE_COMBINED_MIC);
	}

	/* MAC address is cleared until add_interface */
	ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});

	/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
	memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
	ath5k_hw_set_associd(ah);
	ath5k_hw_set_opmode(ah, sc->opmode);

	ath5k_hw_rfgain_opt_init(ah);

	ath5k_hw_init_nfcal_hist(ah);

	/* turn on HW LEDs */
	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);

	return 0;
err_free:
	kfree(ah);
	return ret;
}

/**
 * ath5k_hw_detach - Free the ath5k_hw struct
 *
 * @ah: The &struct ath5k_hw
 */
void ath5k_hw_detach(struct ath5k_hw *ah)
{
	ATH5K_TRACE(ah->ah_sc);

	__set_bit(ATH_STAT_INVALID, ah->ah_sc->status);

	if (ah->ah_rf_banks != NULL)
		kfree(ah->ah_rf_banks);

	ath5k_eeprom_detach(ah);

	/* assume interrupts are down */
}
Commit	Line	Data
c6e387a2 NK	1	/*
	2	* Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
	3	* Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
	4	*
	5	* Permission to use, copy, modify, and distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*
	17	*/
	18
	19	/*************************************\
	20	* Attach/Detach Functions and helpers *
	21	\*************************************/
	22
	23	#include <linux/pci.h>
	24	#include "ath5k.h"
	25	#include "reg.h"
	26	#include "debug.h"
	27	#include "base.h"
	28
	29	/**
	30	* ath5k_hw_post - Power On Self Test helper function
	31	*
	32	* @ah: The &struct ath5k_hw
	33	*/
	34	static int ath5k_hw_post(struct ath5k_hw *ah)
	35	{
	36
2c91108c	37	static const u32 static_pattern[4] = {
c6e387a2 NK	38	0x55555555, 0xaaaaaaaa,
	39	0x66666666, 0x99999999
	40	};
2c91108c JS	41	static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
	42	int i, c;
	43	u16 cur_reg;
	44	u32 var_pattern;
c6e387a2 NK	45	u32 init_val;
	46	u32 cur_val;
	47
	48	for (c = 0; c < 2; c++) {
	49
	50	cur_reg = regs[c];
	51
	52	/* Save previous value */
	53	init_val = ath5k_hw_reg_read(ah, cur_reg);
	54
	55	for (i = 0; i < 256; i++) {
	56	var_pattern = i << 16 \| i;
	57	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	58	cur_val = ath5k_hw_reg_read(ah, cur_reg);
	59
	60	if (cur_val != var_pattern) {
	61	ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
	62	return -EAGAIN;
	63	}
	64
	65	/* Found on ndiswrapper dumps */
	66	var_pattern = 0x0039080f;
	67	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	68	}
	69
	70	for (i = 0; i < 4; i++) {
	71	var_pattern = static_pattern[i];
	72	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	73	cur_val = ath5k_hw_reg_read(ah, cur_reg);
	74
	75	if (cur_val != var_pattern) {
	76	ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
	77	return -EAGAIN;
	78	}
	79
	80	/* Found on ndiswrapper dumps */
	81	var_pattern = 0x003b080f;
	82	ath5k_hw_reg_write(ah, var_pattern, cur_reg);
	83	}
	84
	85	/* Restore previous value */
	86	ath5k_hw_reg_write(ah, init_val, cur_reg);
	87
	88	}
	89
	90	return 0;
	91
	92	}
	93
	94	/**
	95	* ath5k_hw_attach - Check if hw is supported and init the needed structs
	96	*
	97	* @sc: The &struct ath5k_softc we got from the driver's attach function
c6e387a2 NK	98	*
	99	* Check if the device is supported, perform a POST and initialize the needed
	100	* structs. Returns -ENOMEM if we don't have memory for the needed structs,
	101	* -ENODEV if the device is not supported or prints an error msg if something
	102	* else went wrong.
	103	*/
9adca126	104	int ath5k_hw_attach(struct ath5k_softc *sc)
c6e387a2	105	{
9adca126	106	struct ath5k_hw *ah = sc->ah;
13b81559	107	struct ath_common *common = ath5k_hw_common(ah);
c6e387a2	108	struct pci_dev *pdev = sc->pdev;
1c818740	109	struct ath5k_eeprom_info *ee;
c6e387a2 NK	110	int ret;
	111	u32 srev;
	112
c6e387a2 NK	113	/*
	114	* HW information
	115	*/
c6e387a2 NK	116	ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
	117	ah->ah_turbo = false;
	118	ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
	119	ah->ah_imr = 0;
	120	ah->ah_atim_window = 0;
	121	ah->ah_aifs = AR5K_TUNE_AIFS;
	122	ah->ah_cw_min = AR5K_TUNE_CWMIN;
	123	ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
	124	ah->ah_software_retry = false;
caec9112	125	ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
9d332c82	126	ah->ah_noise_floor = -95; /* until first NF calibration is run */
c6e387a2 NK	127
c6e387a2 NK	128	/*
97a81f5c	129	* Find the mac version
c6e387a2	130	*/
97a81f5c PR	131	srev = ath5k_hw_reg_read(ah, AR5K_SREV);
	132	if (srev < AR5K_SREV_AR5311)
	133	ah->ah_version = AR5K_AR5210;
	134	else if (srev < AR5K_SREV_AR5212)
	135	ah->ah_version = AR5K_AR5211;
	136	else
	137	ah->ah_version = AR5K_AR5212;
c6e387a2 NK	138
	139	/Fill the ath5k_hw struct with the needed functions/
	140	ret = ath5k_hw_init_desc_functions(ah);
	141	if (ret)
	142	goto err_free;
	143
	144	/* Bring device out of sleep and reset it's units */
edd7fc70	145	ret = ath5k_hw_nic_wakeup(ah, 0, true);
c6e387a2 NK	146	if (ret)
	147	goto err_free;
	148
	149	/* Get MAC, PHY and RADIO revisions */
c6e387a2 NK	150	ah->ah_mac_srev = srev;
c6e387a2 NK	151	ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
c6e387a2 NK	152	ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
	153	0xffffffff;
	154	ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
	155	CHANNEL_5GHZ);
ee81c554	156	ah->ah_phy = AR5K_PHY(0);
c6e387a2	157
ee81c554 NK	158	/* Try to identify radio chip based on it's srev */
	159	switch (ah->ah_radio_5ghz_revision & 0xf0) {
	160	case AR5K_SREV_RAD_5111:
c6e387a2	161	ah->ah_radio = AR5K_RF5111;
ee81c554 NK	162	ah->ah_single_chip = false;
	163	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	164	CHANNEL_2GHZ);
ee81c554 NK	165	break;
	166	case AR5K_SREV_RAD_5112:
	167	case AR5K_SREV_RAD_2112:
c6e387a2	168	ah->ah_radio = AR5K_RF5112;
ee81c554 NK	169	ah->ah_single_chip = false;
	170	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	171	CHANNEL_2GHZ);
ee81c554 NK	172	break;
ee81c554 NK	173	case AR5K_SREV_RAD_2413:
c6e387a2	174	ah->ah_radio = AR5K_RF2413;
ee81c554	175	ah->ah_single_chip = true;
ee81c554 NK	176	break;
ee81c554 NK	177	case AR5K_SREV_RAD_5413:
c6e387a2	178	ah->ah_radio = AR5K_RF5413;
ee81c554	179	ah->ah_single_chip = true;
ee81c554 NK	180	break;
	181	case AR5K_SREV_RAD_2316:
	182	ah->ah_radio = AR5K_RF2316;
	183	ah->ah_single_chip = true;
ee81c554 NK	184	break;
	185	case AR5K_SREV_RAD_2317:
	186	ah->ah_radio = AR5K_RF2317;
	187	ah->ah_single_chip = true;
ee81c554 NK	188	break;
	189	case AR5K_SREV_RAD_5424:
	190	if (ah->ah_mac_version == AR5K_SREV_AR2425 \|\|
	191	ah->ah_mac_version == AR5K_SREV_AR2417){
	192	ah->ah_radio = AR5K_RF2425;
	193	ah->ah_single_chip = true;
ee81c554	194	} else {
c6e387a2	195	ah->ah_radio = AR5K_RF5413;
ee81c554	196	ah->ah_single_chip = true;
ee81c554 NK	197	}
	198	break;
	199	default:
	200	/* Identify radio based on mac/phy srev */
	201	if (ah->ah_version == AR5K_AR5210) {
	202	ah->ah_radio = AR5K_RF5110;
	203	ah->ah_single_chip = false;
	204	} else if (ah->ah_version == AR5K_AR5211) {
	205	ah->ah_radio = AR5K_RF5111;
	206	ah->ah_single_chip = false;
	207	ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
	208	CHANNEL_2GHZ);
	209	} else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) \|\|
	210	ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) \|\|
	211	ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
	212	ah->ah_radio = AR5K_RF2425;
	213	ah->ah_single_chip = true;
	214	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
ee81c554	215	} else if (srev == AR5K_SREV_AR5213A &&
e8f055f0	216	ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
ee81c554 NK	217	ah->ah_radio = AR5K_RF5112;
ee81c554 NK	218	ah->ah_single_chip = false;
e8f055f0	219	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
ee81c554 NK	220	} else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
	221	ah->ah_radio = AR5K_RF2316;
	222	ah->ah_single_chip = true;
	223	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
ee81c554 NK	224	} else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) \|\|
	225	ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
	226	ah->ah_radio = AR5K_RF5413;
	227	ah->ah_single_chip = true;
	228	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
ee81c554 NK	229	} else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) \|\|
	230	ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
	231	ah->ah_radio = AR5K_RF2413;
	232	ah->ah_single_chip = true;
	233	ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
ee81c554 NK	234	} else {
	235	ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
	236	ret = -ENODEV;
	237	goto err_free;
c6e387a2 NK	238	}
c6e387a2 NK	239	}
ee81c554 NK	240
	241
	242	/* Return on unsuported chips (unsupported eeprom etc) */
	243	if ((srev >= AR5K_SREV_AR5416) &&
	244	(srev < AR5K_SREV_AR2425)) {
	245	ATH5K_ERR(sc, "Device not yet supported.\n");
	246	ret = -ENODEV;
	247	goto err_free;
	248	}
c6e387a2	249
c6e387a2 NK	250	/*
	251	* POST
	252	*/
	253	ret = ath5k_hw_post(ah);
	254	if (ret)
	255	goto err_free;
	256
ee81c554 NK	257	/* Enable pci core retry fix on Hainan (5213A) and later chips */
ee81c554 NK	258	if (srev >= AR5K_SREV_AR5213A)
b55a5de1	259	AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
c6e387a2 NK	260
c6e387a2 NK	261	/*
ee81c554 NK	262	* Get card capabilities, calibration values etc
ee81c554 NK	263	* TODO: EEPROM work
c6e387a2 NK	264	*/
	265	ret = ath5k_eeprom_init(ah);
	266	if (ret) {
	267	ATH5K_ERR(sc, "unable to init EEPROM\n");
	268	goto err_free;
	269	}
	270
394317fc LR	271	ee = &ah->ah_capabilities.cap_eeprom;
394317fc LR	272
c38e7a93 NK	273	/*
	274	* Write PCI-E power save settings
	275	*/
	276	if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
c38e7a93 NK	277	ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
	278	ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
	279
	280	/* Shut off RX when elecidle is asserted */
	281	ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
	282	ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
	283
	284	/* If serdes programing is enabled, increase PCI-E
	285	* tx power for systems with long trace from host
	286	* to minicard connector. */
	287	if (ee->ee_serdes)
	288	ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
	289	else
	290	ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
	291
	292	/* Shut off PLL and CLKREQ active in L1 */
	293	ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
	294
	295	/* Preserve other settings */
	296	ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
	297	ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
	298	ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
	299
	300	/* Reset SERDES to load new settings */
	301	ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
	302	mdelay(1);
	303	}
	304
c6e387a2 NK	305	/* Get misc capabilities */
	306	ret = ath5k_hw_set_capabilities(ah);
	307	if (ret) {
	308	ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
	309	sc->pdev->device);
	310	goto err_free;
	311	}
	312
1c818740	313	/* Crypto settings */
ca5efbe2	314	ah->ah_aes_support = srev >= AR5K_SREV_AR5212_V4 &&
1c818740	315	(ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
ca5efbe2	316	!AR5K_EEPROM_AES_DIS(ee->ee_misc5));
1c818740	317
f650470a BC	318	if (srev >= AR5K_SREV_AR2414) {
	319	ah->ah_combined_mic = true;
	320	AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
	321	AR5K_MISC_MODE_COMBINED_MIC);
	322	}
	323
0e149cf5	324	/* MAC address is cleared until add_interface */
2c91108c	325	ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
0e149cf5	326
c6e387a2	327	/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
954fecea	328	memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
be5d6b75	329	ath5k_hw_set_associd(ah);
ccfe5552	330	ath5k_hw_set_opmode(ah, sc->opmode);
c6e387a2	331
6f3b414a	332	ath5k_hw_rfgain_opt_init(ah);
c6e387a2	333
e5e2647f BC	334	ath5k_hw_init_nfcal_hist(ah);
e5e2647f BC	335
f0f3d388 BC	336	/* turn on HW LEDs */
	337	ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
	338
9adca126	339	return 0;
c6e387a2 NK	340	err_free:
c6e387a2 NK	341	kfree(ah);
9adca126	342	return ret;
c6e387a2 NK	343	}
	344
	345	/**
	346	* ath5k_hw_detach - Free the ath5k_hw struct
	347	*
	348	* @ah: The &struct ath5k_hw
	349	*/
	350	void ath5k_hw_detach(struct ath5k_hw *ah)
	351	{
	352	ATH5K_TRACE(ah->ah_sc);
	353
	354	__set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
	355
	356	if (ah->ah_rf_banks != NULL)
	357	kfree(ah->ah_rf_banks);
	358
8f655dde NK	359	ath5k_eeprom_detach(ah);
8f655dde NK	360
c6e387a2	361	/* assume interrupts are down */
c6e387a2	362	}