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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / ath5k.h
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fa1c114f
JS		 1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _ATH5K_H
19#define _ATH5K_H
20
c6e387a2
NK		 21/* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
fa1c114f
JS		 24#define CHAN_DEBUG 0
25
26#include <linux/io.h>
27#include <linux/types.h>
28#include <net/mac80211.h>
29
c6e387a2
NK		 30/* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
32#include "desc.h"
33
34/* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
37#include "eeprom.h"
db719718 38#include "../ath.h"
fa1c114f
JS		 39
40/* PCI IDs */
41#define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
42#define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
43#define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
44#define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
45#define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
46#define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
47#define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
48#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
49#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
50#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
51#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
52#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
53#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
54#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
55#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
56#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
57#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
58#define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
59#define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
60#define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
61#define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
62#define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
63#define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
64#define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
65#define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
66#define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
67#define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
68#define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
69
70/****************************\
71 GENERIC DRIVER DEFINITIONS
72\****************************/
73
74#define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
75
76#define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
77 printk(_level "ath5k %s: " _fmt, \
78 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
79 ##__VA_ARGS__)
80
81#define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
82 if (net_ratelimit()) \
83 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
84 } while (0)
85
86#define ATH5K_INFO(_sc, _fmt, ...) \
87 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
88
89#define ATH5K_WARN(_sc, _fmt, ...) \
90 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
91
92#define ATH5K_ERR(_sc, _fmt, ...) \
93 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
94
c6e387a2
NK		 95/*
96 * AR5K REGISTER ACCESS
97 */
98
99/* Some macros to read/write fields */
100
101/* First shift, then mask */
102#define AR5K_REG_SM(_val, _flags) \
103 (((_val) << _flags##_S) & (_flags))
104
105/* First mask, then shift */
106#define AR5K_REG_MS(_val, _flags) \
107 (((_val) & (_flags)) >> _flags##_S)
108
109/* Some registers can hold multiple values of interest. For this
110 * reason when we want to write to these registers we must first
111 * retrieve the values which we do not want to clear (lets call this
112 * old_data) and then set the register with this and our new_value:
113 * ( old_data | new_value) */
114#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
115 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
116 (((_val) << _flags##_S) & (_flags)), _reg)
117
118#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
119 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
120 (_mask)) | (_flags), _reg)
121
122#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
123 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
124
125#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
126 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
127
128/* Access to PHY registers */
129#define AR5K_PHY_READ(ah, _reg) \
130 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
131
132#define AR5K_PHY_WRITE(ah, _reg, _val) \
133 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
134
135/* Access QCU registers per queue */
136#define AR5K_REG_READ_Q(ah, _reg, _queue) \
137 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
138
139#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
140 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
141
142#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
143 _reg |= 1 << _queue; \
144} while (0)
145
146#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
147 _reg &= ~(1 << _queue); \
148} while (0)
149
150/* Used while writing initvals */
151#define AR5K_REG_WAIT(_i) do { \
152 if (_i % 64) \
153 udelay(1); \
154} while (0)
155
156/* Register dumps are done per operation mode */
157#define AR5K_INI_RFGAIN_5GHZ 0
158#define AR5K_INI_RFGAIN_2GHZ 1
159
160/* TODO: Clean this up */
161#define AR5K_INI_VAL_11A 0
162#define AR5K_INI_VAL_11A_TURBO 1
163#define AR5K_INI_VAL_11B 2
164#define AR5K_INI_VAL_11G 3
165#define AR5K_INI_VAL_11G_TURBO 4
166#define AR5K_INI_VAL_XR 0
167#define AR5K_INI_VAL_MAX 5
168
fa1c114f
JS		 169/*
170 * Some tuneable values (these should be changeable by the user)
c6e387a2 171 * TODO: Make use of them and add more options OR use debug/configfs
fa1c114f
JS		 172 */
173#define AR5K_TUNE_DMA_BEACON_RESP 2
174#define AR5K_TUNE_SW_BEACON_RESP 10
175#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
176#define AR5K_TUNE_RADAR_ALERT false
177#define AR5K_TUNE_MIN_TX_FIFO_THRES 1
b6127980 178#define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
fa1c114f
JS		 179#define AR5K_TUNE_REGISTER_TIMEOUT 20000
180/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
181 * be the max value. */
c6e387a2 182#define AR5K_TUNE_RSSI_THRES 129
fa1c114f
JS		 183/* This must be set when setting the RSSI threshold otherwise it can
184 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
185 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
186 * track of it. Max value depends on harware. For AR5210 this is just 7.
187 * For AR5211+ this seems to be up to 255. */
c6e387a2 188#define AR5K_TUNE_BMISS_THRES 7
fa1c114f
JS		 189#define AR5K_TUNE_REGISTER_DWELL_TIME 20000
190#define AR5K_TUNE_BEACON_INTERVAL 100
191#define AR5K_TUNE_AIFS 2
192#define AR5K_TUNE_AIFS_11B 2
193#define AR5K_TUNE_AIFS_XR 0
194#define AR5K_TUNE_CWMIN 15
195#define AR5K_TUNE_CWMIN_11B 31
196#define AR5K_TUNE_CWMIN_XR 3
197#define AR5K_TUNE_CWMAX 1023
198#define AR5K_TUNE_CWMAX_11B 1023
199#define AR5K_TUNE_CWMAX_XR 7
200#define AR5K_TUNE_NOISE_FLOOR -72
e5e2647f 201#define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
8f655dde
NK		 202#define AR5K_TUNE_MAX_TXPOWER 63
203#define AR5K_TUNE_DEFAULT_TXPOWER 25
204#define AR5K_TUNE_TPC_TXPOWER false
1063b176 205#define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */
2111ac0d 206#define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
afe86286 207#define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */
fa1c114f 208
4edd761f
BR		 209#define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
210
c6e387a2
NK		 211#define AR5K_INIT_CARR_SENSE_EN 1
212
213/*Swap RX/TX Descriptor for big endian archs*/
214#if defined(__BIG_ENDIAN)
215#define AR5K_INIT_CFG ( \
216 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
217)
218#else
219#define AR5K_INIT_CFG 0x00000000
220#endif
221
222/* Initial values */
e8f055f0 223#define AR5K_INIT_CYCRSSI_THR1 2
c6e387a2
NK		 224#define AR5K_INIT_TX_LATENCY 502
225#define AR5K_INIT_USEC 39
226#define AR5K_INIT_USEC_TURBO 79
227#define AR5K_INIT_USEC_32 31
228#define AR5K_INIT_SLOT_TIME 396
229#define AR5K_INIT_SLOT_TIME_TURBO 480
230#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
231#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
232#define AR5K_INIT_PROG_IFS 920
233#define AR5K_INIT_PROG_IFS_TURBO 960
234#define AR5K_INIT_EIFS 3440
235#define AR5K_INIT_EIFS_TURBO 6880
236#define AR5K_INIT_SIFS 560
237#define AR5K_INIT_SIFS_TURBO 480
238#define AR5K_INIT_SH_RETRY 10
239#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
240#define AR5K_INIT_SSH_RETRY 32
241#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
242#define AR5K_INIT_TX_RETRY 10
243
244#define AR5K_INIT_TRANSMIT_LATENCY ( \
245 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
246 (AR5K_INIT_USEC) \
247)
248#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
249 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
250 (AR5K_INIT_USEC_TURBO) \
251)
252#define AR5K_INIT_PROTO_TIME_CNTRL ( \
253 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
254 (AR5K_INIT_PROG_IFS) \
255)
256#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
257 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
258 (AR5K_INIT_PROG_IFS_TURBO) \
259)
260
fa1c114f
JS		 261
262/* GENERIC CHIPSET DEFINITIONS */
263
264/* MAC Chips */
265enum ath5k_version {
266 AR5K_AR5210 = 0,
267 AR5K_AR5211 = 1,
268 AR5K_AR5212 = 2,
269};
270
271/* PHY Chips */
272enum ath5k_radio {
273 AR5K_RF5110 = 0,
274 AR5K_RF5111 = 1,
275 AR5K_RF5112 = 2,
8daeef97
NK		 276 AR5K_RF2413 = 3,
277 AR5K_RF5413 = 4,
1bef016a
NK		 278 AR5K_RF2316 = 5,
279 AR5K_RF2317 = 6,
280 AR5K_RF2425 = 7,
fa1c114f
JS		 281};
282
283/*
284 * Common silicon revision/version values
285 */
286
287enum ath5k_srev_type {
1bef016a 288 AR5K_VERSION_MAC,
fa1c114f
JS		 289 AR5K_VERSION_RAD,
290};
291
292struct ath5k_srev_name {
293 const char *sr_name;
294 enum ath5k_srev_type sr_type;
295 u_int sr_val;
296};
297
298#define AR5K_SREV_UNKNOWN 0xffff
299
1bef016a
NK		 300#define AR5K_SREV_AR5210 0x00 /* Crete */
301#define AR5K_SREV_AR5311 0x10 /* Maui 1 */
302#define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
303#define AR5K_SREV_AR5311B 0x30 /* Spirit */
304#define AR5K_SREV_AR5211 0x40 /* Oahu */
305#define AR5K_SREV_AR5212 0x50 /* Venice */
ca5efbe2 306#define AR5K_SREV_AR5212_V4 0x54 /* ??? */
1bef016a
NK		 307#define AR5K_SREV_AR5213 0x55 /* ??? */
308#define AR5K_SREV_AR5213A 0x59 /* Hainan */
309#define AR5K_SREV_AR2413 0x78 /* Griffin lite */
310#define AR5K_SREV_AR2414 0x70 /* Griffin */
311#define AR5K_SREV_AR5424 0x90 /* Condor */
312#define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
313#define AR5K_SREV_AR5414 0xa0 /* Eagle */
e8f055f0 314#define AR5K_SREV_AR2415 0xb0 /* Talon */
1bef016a
NK		 315#define AR5K_SREV_AR5416 0xc0 /* PCI-E */
316#define AR5K_SREV_AR5418 0xca /* PCI-E */
317#define AR5K_SREV_AR2425 0xe0 /* Swan */
318#define AR5K_SREV_AR2417 0xf0 /* Nala */
fa1c114f
JS		 319
320#define AR5K_SREV_RAD_5110 0x00
321#define AR5K_SREV_RAD_5111 0x10
322#define AR5K_SREV_RAD_5111A 0x15
323#define AR5K_SREV_RAD_2111 0x20
324#define AR5K_SREV_RAD_5112 0x30
325#define AR5K_SREV_RAD_5112A 0x35
e5a4ad0d 326#define AR5K_SREV_RAD_5112B 0x36
fa1c114f
JS		 327#define AR5K_SREV_RAD_2112 0x40
328#define AR5K_SREV_RAD_2112A 0x45
e5a4ad0d 329#define AR5K_SREV_RAD_2112B 0x46
1bef016a
NK		 330#define AR5K_SREV_RAD_2413 0x50
331#define AR5K_SREV_RAD_5413 0x60
e8f055f0 332#define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
1bef016a
NK		 333#define AR5K_SREV_RAD_2317 0x80
334#define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
335#define AR5K_SREV_RAD_2425 0xa2
336#define AR5K_SREV_RAD_5133 0xc0
337
338#define AR5K_SREV_PHY_5211 0x30
339#define AR5K_SREV_PHY_5212 0x41
8892e4ec 340#define AR5K_SREV_PHY_5212A 0x42
e8f055f0 341#define AR5K_SREV_PHY_5212B 0x43
1bef016a
NK		 342#define AR5K_SREV_PHY_2413 0x45
343#define AR5K_SREV_PHY_5413 0x61
344#define AR5K_SREV_PHY_2425 0x70
fa1c114f 345
fa1c114f
JS		 346/* TODO add support to mac80211 for vendor-specific rates and modes */
347
348/*
349 * Some of this information is based on Documentation from:
350 *
351 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
352 *
353 * Modulation for Atheros' eXtended Range - range enhancing extension that is
354 * supposed to double the distance an Atheros client device can keep a
355 * connection with an Atheros access point. This is achieved by increasing
356 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
357 * the 802.11 specifications demand. In addition, new (proprietary) data rates
358 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
359 *
360 * Please note that can you either use XR or TURBO but you cannot use both,
361 * they are exclusive.
362 *
363 */
364#define MODULATION_XR 0x00000200
365/*
366 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
367 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
368 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
369 * channels. To use this feature your Access Point must also suport it.
370 * There is also a distinction between "static" and "dynamic" turbo modes:
371 *
372 * - Static: is the dumb version: devices set to this mode stick to it until
373 * the mode is turned off.
374 * - Dynamic: is the intelligent version, the network decides itself if it
375 * is ok to use turbo. As soon as traffic is detected on adjacent channels
376 * (which would get used in turbo mode), or when a non-turbo station joins
377 * the network, turbo mode won't be used until the situation changes again.
378 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
379 * monitors the used radio band in order to decide whether turbo mode may
380 * be used or not.
381 *
382 * This article claims Super G sticks to bonding of channels 5 and 6 for
383 * USA:
384 *
385 * http://www.pcworld.com/article/id,113428-page,1/article.html
386 *
387 * The channel bonding seems to be driver specific though. In addition to
388 * deciding what channels will be used, these "Turbo" modes are accomplished
389 * by also enabling the following features:
390 *
391 * - Bursting: allows multiple frames to be sent at once, rather than pausing
392 * after each frame. Bursting is a standards-compliant feature that can be
393 * used with any Access Point.
394 * - Fast frames: increases the amount of information that can be sent per
395 * frame, also resulting in a reduction of transmission overhead. It is a
396 * proprietary feature that needs to be supported by the Access Point.
397 * - Compression: data frames are compressed in real time using a Lempel Ziv
398 * algorithm. This is done transparently. Once this feature is enabled,
399 * compression and decompression takes place inside the chipset, without
400 * putting additional load on the host CPU.
401 *
402 */
403#define MODULATION_TURBO 0x00000080
404
d8ee398d
LR		 405enum ath5k_driver_mode {
406 AR5K_MODE_11A = 0,
407 AR5K_MODE_11A_TURBO = 1,
408 AR5K_MODE_11B = 2,
409 AR5K_MODE_11G = 3,
410 AR5K_MODE_11G_TURBO = 4,
411 AR5K_MODE_XR = 0,
412 AR5K_MODE_MAX = 5
fa1c114f
JS		 413};
414
2bed03eb
NK		 415enum ath5k_ant_mode {
416 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */
417 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */
418 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */
419 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */
420 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */
421 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */
422 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */
423 AR5K_ANTMODE_MAX,
424};
425
19fd6e55 426
fa1c114f
JS		 427/****************\
428 TX DEFINITIONS
429\****************/
430
431/*
c6e387a2 432 * TX Status descriptor
fa1c114f
JS		 433 */
434struct ath5k_tx_status {
435 u16 ts_seqnum;
436 u16 ts_tstamp;
437 u8 ts_status;
2f7fe870
FF		 438 u8 ts_rate[4];
439 u8 ts_retry[4];
440 u8 ts_final_idx;
fa1c114f
JS		 441 s8 ts_rssi;
442 u8 ts_shortretry;
443 u8 ts_longretry;
444 u8 ts_virtcol;
445 u8 ts_antenna;
446};
447
448#define AR5K_TXSTAT_ALTRATE 0x80
449#define AR5K_TXERR_XRETRY 0x01
450#define AR5K_TXERR_FILT 0x02
451#define AR5K_TXERR_FIFO 0x04
452
453/**
454 * enum ath5k_tx_queue - Queue types used to classify tx queues.
455 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
456 * @AR5K_TX_QUEUE_DATA: A normal data queue
457 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
458 * @AR5K_TX_QUEUE_BEACON: The beacon queue
459 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
460 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
461 */
462enum ath5k_tx_queue {
463 AR5K_TX_QUEUE_INACTIVE = 0,
464 AR5K_TX_QUEUE_DATA,
465 AR5K_TX_QUEUE_XR_DATA,
466 AR5K_TX_QUEUE_BEACON,
467 AR5K_TX_QUEUE_CAB,
468 AR5K_TX_QUEUE_UAPSD,
469};
470
471#define AR5K_NUM_TX_QUEUES 10
472#define AR5K_NUM_TX_QUEUES_NOQCU 2
473
474/*
475 * Queue syb-types to classify normal data queues.
476 * These are the 4 Access Categories as defined in
477 * WME spec. 0 is the lowest priority and 4 is the
478 * highest. Normal data that hasn't been classified
479 * goes to the Best Effort AC.
480 */
481enum ath5k_tx_queue_subtype {
482 AR5K_WME_AC_BK = 0, /*Background traffic*/
483 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
484 AR5K_WME_AC_VI, /*Video traffic*/
485 AR5K_WME_AC_VO, /*Voice traffic*/
486};
487
488/*
489 * Queue ID numbers as returned by the hw functions, each number
490 * represents a hw queue. If hw does not support hw queues
491 * (eg 5210) all data goes in one queue. These match
492 * d80211 definitions (net80211/MadWiFi don't use them).
493 */
494enum ath5k_tx_queue_id {
495 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
496 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
497 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
498 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
499 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
500 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
501 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
502 AR5K_TX_QUEUE_ID_UAPSD = 8,
503 AR5K_TX_QUEUE_ID_XR_DATA = 9,
504};
505
fa1c114f
JS		 506/*
507 * Flags to set hw queue's parameters...
508 */
509#define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
510#define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
511#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
512#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
513#define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
4c674c60
NK		 514#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
515#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
516#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
517#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
518#define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
519#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
520#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
521#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
522#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
fa1c114f
JS		 523
524/*
525 * A struct to hold tx queue's parameters
526 */
527struct ath5k_txq_info {
528 enum ath5k_tx_queue tqi_type;
529 enum ath5k_tx_queue_subtype tqi_subtype;
530 u16 tqi_flags; /* Tx queue flags (see above) */
de8af455
BR		 531 u8 tqi_aifs; /* Arbitrated Interframe Space */
532 u16 tqi_cw_min; /* Minimum Contention Window */
533 u16 tqi_cw_max; /* Maximum Contention Window */
fa1c114f
JS		 534 u32 tqi_cbr_period; /* Constant bit rate period */
535 u32 tqi_cbr_overflow_limit;
536 u32 tqi_burst_time;
a951ae21 537 u32 tqi_ready_time; /* Time queue waits after an event */
fa1c114f
JS		 538};
539
540/*
541 * Transmit packet types.
c6e387a2 542 * used on tx control descriptor
fa1c114f
JS		 543 */
544enum ath5k_pkt_type {
545 AR5K_PKT_TYPE_NORMAL = 0,
546 AR5K_PKT_TYPE_ATIM = 1,
547 AR5K_PKT_TYPE_PSPOLL = 2,
548 AR5K_PKT_TYPE_BEACON = 3,
549 AR5K_PKT_TYPE_PROBE_RESP = 4,
550 AR5K_PKT_TYPE_PIFS = 5,
551};
552
553/*
554 * TX power and TPC settings
555 */
556#define AR5K_TXPOWER_OFDM(_r, _v) ( \
557 ((0 & 1) << ((_v) + 6)) | \
8f655dde 558 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
fa1c114f
JS		 559)
560
561#define AR5K_TXPOWER_CCK(_r, _v) ( \
8f655dde 562 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
fa1c114f
JS		 563)
564
565/*
beade636 566 * DMA size definitions (2^(n+2))
fa1c114f
JS		 567 */
568enum ath5k_dmasize {
569 AR5K_DMASIZE_4B = 0,
570 AR5K_DMASIZE_8B,
571 AR5K_DMASIZE_16B,
572 AR5K_DMASIZE_32B,
573 AR5K_DMASIZE_64B,
574 AR5K_DMASIZE_128B,
575 AR5K_DMASIZE_256B,
576 AR5K_DMASIZE_512B
577};
578
579
580/****************\
581 RX DEFINITIONS
582\****************/
583
584/*
c6e387a2 585 * RX Status descriptor
fa1c114f
JS		 586 */
587struct ath5k_rx_status {
588 u16 rs_datalen;
589 u16 rs_tstamp;
590 u8 rs_status;
591 u8 rs_phyerr;
592 s8 rs_rssi;
593 u8 rs_keyix;
594 u8 rs_rate;
595 u8 rs_antenna;
596 u8 rs_more;
597};
598
599#define AR5K_RXERR_CRC 0x01
600#define AR5K_RXERR_PHY 0x02
601#define AR5K_RXERR_FIFO 0x04
602#define AR5K_RXERR_DECRYPT 0x08
603#define AR5K_RXERR_MIC 0x10
604#define AR5K_RXKEYIX_INVALID ((u8) - 1)
605#define AR5K_TXKEYIX_INVALID ((u32) - 1)
606
fa1c114f 607
fa1c114f
JS		 608/**************************\
609 BEACON TIMERS DEFINITIONS
610\**************************/
611
612#define AR5K_BEACON_PERIOD 0x0000ffff
613#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
614#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
615
fa1c114f
JS		 616
617/*
618 * TSF to TU conversion:
619 *
620 * TSF is a 64bit value in usec (microseconds).
e535c1ac
BR		 621 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
622 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
fa1c114f
JS		 623 */
624#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
625
626
c6e387a2
NK		 627/*******************************\
628 GAIN OPTIMIZATION DEFINITIONS
629\*******************************/
630
631enum ath5k_rfgain {
632 AR5K_RFGAIN_INACTIVE = 0,
6f3b414a 633 AR5K_RFGAIN_ACTIVE,
c6e387a2
NK		 634 AR5K_RFGAIN_READ_REQUESTED,
635 AR5K_RFGAIN_NEED_CHANGE,
636};
637
c6e387a2 638struct ath5k_gain {
6f3b414a
NK		 639 u8 g_step_idx;
640 u8 g_current;
641 u8 g_target;
642 u8 g_low;
643 u8 g_high;
644 u8 g_f_corr;
645 u8 g_state;
c6e387a2
NK		 646};
647
fa1c114f
JS		 648/********************\
649 COMMON DEFINITIONS
650\********************/
651
fa1c114f
JS		 652#define AR5K_SLOT_TIME_9 396
653#define AR5K_SLOT_TIME_20 880
654#define AR5K_SLOT_TIME_MAX 0xffff
655
656/* channel_flags */
657#define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
658#define CHANNEL_TURBO 0x0010 /* Turbo Channel */
659#define CHANNEL_CCK 0x0020 /* CCK channel */
660#define CHANNEL_OFDM 0x0040 /* OFDM channel */
661#define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
662#define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
663#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
664#define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
665#define CHANNEL_XR 0x0800 /* XR channel */
666
667#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
668#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
669#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
670#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
671#define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
672#define CHANNEL_108A CHANNEL_T
673#define CHANNEL_108G CHANNEL_TG
674#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
675
676#define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
677 CHANNEL_TURBO)
678
679#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
680#define CHANNEL_MODES CHANNEL_ALL
681
682/*
c6e387a2
NK		 683 * Used internaly for reset_tx_queue).
684 * Also see struct struct ieee80211_channel.
fa1c114f 685 */
46026e8f
BC		 686#define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
687#define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
fa1c114f
JS		 688
689/*
c6e387a2 690 * The following structure is used to map 2GHz channels to
fa1c114f 691 * 5GHz Atheros channels.
c6e387a2 692 * TODO: Clean up
fa1c114f
JS		 693 */
694struct ath5k_athchan_2ghz {
695 u32 a2_flags;
696 u16 a2_athchan;
697};
698
63266a65 699
c6e387a2
NK		 700/******************\
701 RATE DEFINITIONS
702\******************/
fa1c114f 703
fa1c114f 704/**
63266a65 705 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
fa1c114f 706 *
63266a65 707 * The rate code is used to get the RX rate or set the TX rate on the
fa1c114f
JS		 708 * hardware descriptors. It is also used for internal modulation control
709 * and settings.
710 *
63266a65 711 * This is the hardware rate map we are aware of:
fa1c114f 712 *
63266a65 713 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
fa1c114f
JS		 714 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
715 *
63266a65 716 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
fa1c114f
JS		 717 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
718 *
719 * rate_code 17 18 19 20 21 22 23 24
720 * rate_kbps ? ? ? ? ? ? ? 11000
721 *
722 * rate_code 25 26 27 28 29 30 31 32
63266a65
BR		 723 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
724 *
725 * "S" indicates CCK rates with short preamble.
fa1c114f 726 *
63266a65
BR		 727 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
728 * lowest 4 bits, so they are the same as below with a 0xF mask.
729 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
730 * We handle this in ath5k_setup_bands().
fa1c114f 731 */
63266a65 732#define AR5K_MAX_RATES 32
fa1c114f 733
63266a65
BR		 734/* B */
735#define ATH5K_RATE_CODE_1M 0x1B
736#define ATH5K_RATE_CODE_2M 0x1A
737#define ATH5K_RATE_CODE_5_5M 0x19
738#define ATH5K_RATE_CODE_11M 0x18
739/* A and G */
740#define ATH5K_RATE_CODE_6M 0x0B
741#define ATH5K_RATE_CODE_9M 0x0F
742#define ATH5K_RATE_CODE_12M 0x0A
743#define ATH5K_RATE_CODE_18M 0x0E
744#define ATH5K_RATE_CODE_24M 0x09
745#define ATH5K_RATE_CODE_36M 0x0D
746#define ATH5K_RATE_CODE_48M 0x08
747#define ATH5K_RATE_CODE_54M 0x0C
748/* XR */
749#define ATH5K_RATE_CODE_XR_500K 0x07
750#define ATH5K_RATE_CODE_XR_1M 0x02
751#define ATH5K_RATE_CODE_XR_2M 0x06
752#define ATH5K_RATE_CODE_XR_3M 0x01
fa1c114f 753
c6e387a2
NK		 754/* adding this flag to rate_code enables short preamble */
755#define AR5K_SET_SHORT_PREAMBLE 0x04
fa1c114f
JS		 756
757/*
758 * Crypto definitions
759 */
760
761#define AR5K_KEYCACHE_SIZE 8
762
763/***********************\
764 HW RELATED DEFINITIONS
765\***********************/
766
767/*
768 * Misc definitions
769 */
770#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
771
772#define AR5K_ASSERT_ENTRY(_e, _s) do { \
773 if (_e >= _s) \
774 return (false); \
775} while (0)
776
fa1c114f
JS		 777/*
778 * Hardware interrupt abstraction
779 */
780
781/**
782 * enum ath5k_int - Hardware interrupt masks helpers
783 *
784 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
785 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
786 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
787 * @AR5K_INT_RXNOFRM: No frame received (?)
788 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
789 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
790 * LinkPtr is NULL. For more details, refer to:
791 * http://www.freepatentsonline.com/20030225739.html
792 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
793 * Note that Rx overrun is not always fatal, on some chips we can continue
794 * operation without reseting the card, that's why int_fatal is not
795 * common for all chips.
796 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
797 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
798 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
799 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
800 * We currently do increments on interrupt by
801 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
2111ac0d
BR		 802 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
803 * one of the PHY error counters reached the maximum value and should be
804 * read and cleared.
fa1c114f 805 * @AR5K_INT_RXPHY: RX PHY Error
4c674c60 806 * @AR5K_INT_RXKCM: RX Key cache miss
fa1c114f
JS		 807 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
808 * beacon that must be handled in software. The alternative is if you
809 * have VEOL support, in that case you let the hardware deal with things.
810 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
811 * beacons from the AP have associated with, we should probably try to
812 * reassociate. When in IBSS mode this might mean we have not received
813 * any beacons from any local stations. Note that every station in an
814 * IBSS schedules to send beacons at the Target Beacon Transmission Time
815 * (TBTT) with a random backoff.
816 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
817 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
818 * until properly handled
819 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
820 * errors. These types of errors we can enable seem to be of type
821 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
4c674c60 822 * @AR5K_INT_GLOBAL: Used to clear and set the IER
fa1c114f
JS		 823 * @AR5K_INT_NOCARD: signals the card has been removed
824 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
825 * bit value
826 *
827 * These are mapped to take advantage of some common bits
828 * between the MACs, to be able to set intr properties
829 * easier. Some of them are not used yet inside hw.c. Most map
830 * to the respective hw interrupt value as they are common amogst different
831 * MACs.
832 */
833enum ath5k_int {
4c674c60 834 AR5K_INT_RXOK = 0x00000001,
fa1c114f 835 AR5K_INT_RXDESC = 0x00000002,
4c674c60 836 AR5K_INT_RXERR = 0x00000004,
fa1c114f
JS		 837 AR5K_INT_RXNOFRM = 0x00000008,
838 AR5K_INT_RXEOL = 0x00000010,
839 AR5K_INT_RXORN = 0x00000020,
4c674c60 840 AR5K_INT_TXOK = 0x00000040,
fa1c114f 841 AR5K_INT_TXDESC = 0x00000080,
4c674c60
NK		 842 AR5K_INT_TXERR = 0x00000100,
843 AR5K_INT_TXNOFRM = 0x00000200,
844 AR5K_INT_TXEOL = 0x00000400,
fa1c114f
JS		 845 AR5K_INT_TXURN = 0x00000800,
846 AR5K_INT_MIB = 0x00001000,
4c674c60 847 AR5K_INT_SWI = 0x00002000,
fa1c114f
JS		 848 AR5K_INT_RXPHY = 0x00004000,
849 AR5K_INT_RXKCM = 0x00008000,
850 AR5K_INT_SWBA = 0x00010000,
4c674c60 851 AR5K_INT_BRSSI = 0x00020000,
fa1c114f 852 AR5K_INT_BMISS = 0x00040000,
4c674c60
NK		 853 AR5K_INT_FATAL = 0x00080000, /* Non common */
854 AR5K_INT_BNR = 0x00100000, /* Non common */
855 AR5K_INT_TIM = 0x00200000, /* Non common */
856 AR5K_INT_DTIM = 0x00400000, /* Non common */
857 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
858 AR5K_INT_GPIO = 0x01000000,
859 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
860 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
861 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
862 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
863 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
864 AR5K_INT_QTRIG = 0x40000000, /* Non common */
865 AR5K_INT_GLOBAL = 0x80000000,
866
867 AR5K_INT_COMMON = AR5K_INT_RXOK
868 | AR5K_INT_RXDESC
869 | AR5K_INT_RXERR
870 | AR5K_INT_RXNOFRM
871 | AR5K_INT_RXEOL
872 | AR5K_INT_RXORN
873 | AR5K_INT_TXOK
874 | AR5K_INT_TXDESC
875 | AR5K_INT_TXERR
876 | AR5K_INT_TXNOFRM
877 | AR5K_INT_TXEOL
878 | AR5K_INT_TXURN
879 | AR5K_INT_MIB
880 | AR5K_INT_SWI
881 | AR5K_INT_RXPHY
882 | AR5K_INT_RXKCM
883 | AR5K_INT_SWBA
884 | AR5K_INT_BRSSI
885 | AR5K_INT_BMISS
886 | AR5K_INT_GPIO
887 | AR5K_INT_GLOBAL,
888
fa1c114f
JS		 889 AR5K_INT_NOCARD = 0xffffffff
890};
891
e65e1d77
BR		 892/* mask which calibration is active at the moment */
893enum ath5k_calibration_mask {
894 AR5K_CALIBRATION_FULL = 0x01,
895 AR5K_CALIBRATION_SHORT = 0x02,
2111ac0d 896 AR5K_CALIBRATION_ANI = 0x04,
6e220662
NK		 897};
898
fa1c114f
JS		 899/*
900 * Power management
901 */
902enum ath5k_power_mode {
903 AR5K_PM_UNDEFINED = 0,
904 AR5K_PM_AUTO,
905 AR5K_PM_AWAKE,
906 AR5K_PM_FULL_SLEEP,
907 AR5K_PM_NETWORK_SLEEP,
908};
909
910/*
911 * These match net80211 definitions (not used in
c6e387a2
NK		 912 * mac80211).
913 * TODO: Clean this up
fa1c114f
JS		 914 */
915#define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
916#define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
917#define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
918#define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
919#define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
920
921/* GPIO-controlled software LED */
922#define AR5K_SOFTLED_PIN 0
923#define AR5K_SOFTLED_ON 0
924#define AR5K_SOFTLED_OFF 1
925
926/*
927 * Chipset capabilities -see ath5k_hw_get_capability-
928 * get_capability function is not yet fully implemented
c6e387a2
NK		 929 * in ath5k so most of these don't work yet...
930 * TODO: Implement these & merge with _TUNE_ stuff above
fa1c114f
JS		 931 */
932enum ath5k_capability_type {
933 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
934 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
935 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
936 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
937 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
938 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
939 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
940 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
941 AR5K_CAP_BURST = 9, /* Supports packet bursting */
942 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
943 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
944 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
945 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
946 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
947 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
948 AR5K_CAP_XR = 16, /* Supports XR mode */
949 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
950 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
951 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
952 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
953};
954
400ec45a
LR		 955
956/* XXX: we *may* move cap_range stuff to struct wiphy */
fa1c114f
JS		 957struct ath5k_capabilities {
958 /*
959 * Supported PHY modes
960 * (ie. CHANNEL_A, CHANNEL_B, ...)
961 */
d8ee398d 962 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
fa1c114f
JS		 963
964 /*
965 * Frequency range (without regulation restrictions)
966 */
967 struct {
968 u16 range_2ghz_min;
969 u16 range_2ghz_max;
970 u16 range_5ghz_min;
971 u16 range_5ghz_max;
972 } cap_range;
973
fa1c114f
JS		 974 /*
975 * Values stored in the EEPROM (some of them...)
976 */
977 struct ath5k_eeprom_info cap_eeprom;
978
979 /*
980 * Queue information
981 */
982 struct {
983 u8 q_tx_num;
984 } cap_queues;
a8c944f8
BR		 985
986 bool cap_has_phyerr_counters;
fa1c114f
JS		 987};
988
e5e2647f
BC		 989/* size of noise floor history (keep it a power of two) */
990#define ATH5K_NF_CAL_HIST_MAX 8
991struct ath5k_nfcal_hist
992{
993 s16 index; /* current index into nfval */
994 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
995};
996
b4ea449d
BR		 997/**
998 * struct avg_val - Helper structure for average calculation
999 * @avg: contains the actual average value
1000 * @avg_weight: is used internally during calculation to prevent rounding errors
1001 */
1002struct ath5k_avg_val {
1003 int avg;
1004 int avg_weight;
1005};
fa1c114f
JS		 1006
1007/***************************************\
1008 HARDWARE ABSTRACTION LAYER STRUCTURE
1009\***************************************/
1010
1011/*
1012 * Misc defines
1013 */
1014
1015#define AR5K_MAX_GPIO 10
1016#define AR5K_MAX_RF_BANKS 8
1017
c6e387a2 1018/* TODO: Clean up and merge with ath5k_softc */
fa1c114f 1019struct ath5k_hw {
db719718 1020 struct ath_common common;
fa1c114f
JS		 1021
1022 struct ath5k_softc *ah_sc;
1023 void __iomem *ah_iobase;
1024
1025 enum ath5k_int ah_imr;
1026
46026e8f 1027 struct ieee80211_channel *ah_current_channel;
fa1c114f
JS		 1028 bool ah_turbo;
1029 bool ah_calibration;
fa1c114f 1030 bool ah_single_chip;
fa1c114f 1031
46026e8f
BC		 1032 enum ath5k_version ah_version;
1033 enum ath5k_radio ah_radio;
1034 u32 ah_phy;
fa1c114f
JS		 1035 u32 ah_mac_srev;
1036 u16 ah_mac_version;
fa1c114f
JS		 1037 u16 ah_phy_revision;
1038 u16 ah_radio_5ghz_revision;
1039 u16 ah_radio_2ghz_revision;
1040
fa1c114f
JS		 1041#define ah_modes ah_capabilities.cap_mode
1042#define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1043
1044 u32 ah_atim_window;
fa1c114f 1045 u32 ah_limit_tx_retries;
6e08d228 1046 u8 ah_coverage_class;
fa1c114f 1047
2bed03eb
NK		 1048 /* Antenna Control */
1049 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1050 u8 ah_ant_mode;
1051 u8 ah_tx_ant;
1052 u8 ah_def_ant;
46026e8f 1053 bool ah_software_retry;
fa1c114f 1054
fa1c114f
JS		 1055 struct ath5k_capabilities ah_capabilities;
1056
1057 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1058 u32 ah_txq_status;
1059 u32 ah_txq_imr_txok;
1060 u32 ah_txq_imr_txerr;
1061 u32 ah_txq_imr_txurn;
1062 u32 ah_txq_imr_txdesc;
1063 u32 ah_txq_imr_txeol;
4c674c60
NK		 1064 u32 ah_txq_imr_cbrorn;
1065 u32 ah_txq_imr_cbrurn;
1066 u32 ah_txq_imr_qtrig;
1067 u32 ah_txq_imr_nofrm;
1068 u32 ah_txq_isr;
fa1c114f
JS		 1069 u32 *ah_rf_banks;
1070 size_t ah_rf_banks_size;
8892e4ec 1071 size_t ah_rf_regs_count;
fa1c114f 1072 struct ath5k_gain ah_gain;
8892e4ec 1073 u8 ah_offset[AR5K_MAX_RF_BANKS];
fa1c114f 1074
8f655dde 1075
fa1c114f 1076 struct {
8f655dde
NK		 1077 /* Temporary tables used for interpolation */
1078 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1079 [AR5K_EEPROM_POWER_TABLE_SIZE];
1080 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1081 [AR5K_EEPROM_POWER_TABLE_SIZE];
1082 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1083 u16 txp_rates_power_table[AR5K_MAX_RATES];
1084 u8 txp_min_idx;
fa1c114f 1085 bool txp_tpc;
8f655dde
NK		 1086 /* Values in 0.25dB units */
1087 s16 txp_min_pwr;
1088 s16 txp_max_pwr;
a0823810 1089 /* Values in 0.5dB units */
8f655dde 1090 s16 txp_offset;
fa1c114f 1091 s16 txp_ofdm;
8f655dde 1092 s16 txp_cck_ofdm_gainf_delta;
a0823810
NK		 1093 /* Value in dB units */
1094 s16 txp_cck_ofdm_pwr_delta;
fa1c114f
JS		 1095 } ah_txpower;
1096
1097 struct {
1098 bool r_enabled;
1099 int r_last_alert;
1100 struct ieee80211_channel r_last_channel;
1101 } ah_radar;
1102
e5e2647f
BC		 1103 struct ath5k_nfcal_hist ah_nfcal_hist;
1104
b4ea449d
BR		 1105 /* average beacon RSSI in our BSS (used by ANI) */
1106 struct ath5k_avg_val ah_beacon_rssi_avg;
1107
fa1c114f
JS		 1108 /* noise floor from last periodic calibration */
1109 s32 ah_noise_floor;
1110
6e220662 1111 /* Calibration timestamp */
a9167f96 1112 unsigned long ah_cal_next_full;
2111ac0d 1113 unsigned long ah_cal_next_ani;
afe86286 1114 unsigned long ah_cal_next_nf;
6e220662 1115
e65e1d77
BR		 1116 /* Calibration mask */
1117 u8 ah_cal_mask;
6e220662 1118
fa1c114f
JS		 1119 /*
1120 * Function pointers
1121 */
1122 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
8127fbdc 1123 unsigned int, unsigned int, int, enum ath5k_pkt_type,
fa1c114f 1124 unsigned int, unsigned int, unsigned int, unsigned int,
8127fbdc 1125 unsigned int, unsigned int, unsigned int, unsigned int);
b47f407b
BR		 1126 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1127 struct ath5k_tx_status *);
1128 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1129 struct ath5k_rx_status *);
fa1c114f
JS		 1130};
1131
1132/*
1133 * Prototypes
1134 */
1135
fa1c114f 1136/* Attach/Detach Functions */
a25d1e4c
PR		 1137int ath5k_hw_attach(struct ath5k_softc *sc);
1138void ath5k_hw_detach(struct ath5k_hw *ah);
c6e387a2 1139
40ca22ea
BR		 1140int ath5k_sysfs_register(struct ath5k_softc *sc);
1141void ath5k_sysfs_unregister(struct ath5k_softc *sc);
1142
0ed4548f 1143/* LED functions */
a25d1e4c
PR		 1144int ath5k_init_leds(struct ath5k_softc *sc);
1145void ath5k_led_enable(struct ath5k_softc *sc);
1146void ath5k_led_off(struct ath5k_softc *sc);
1147void ath5k_unregister_leds(struct ath5k_softc *sc);
0ed4548f 1148
fa1c114f 1149/* Reset Functions */
a25d1e4c
PR		 1150int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1151int ath5k_hw_on_hold(struct ath5k_hw *ah);
1152int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1153 struct ieee80211_channel *channel, bool change_channel);
ec182d97
PR		 1154int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1155 bool is_set);
fa1c114f 1156/* Power management functions */
c6e387a2 1157
fa1c114f 1158/* DMA Related Functions */
a25d1e4c
PR		 1159void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1160int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1161u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1162void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1163int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1164int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1165u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1166int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
c6e387a2 1167 u32 phys_addr);
a25d1e4c 1168int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
fa1c114f 1169/* Interrupt handling */
a25d1e4c
PR		 1170bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1171int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1172enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
495391d7 1173void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
c6e387a2 1174
fa1c114f 1175/* EEPROM access functions */
a25d1e4c
PR		 1176int ath5k_eeprom_init(struct ath5k_hw *ah);
1177void ath5k_eeprom_detach(struct ath5k_hw *ah);
1178int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
c6e387a2 1179
fa1c114f 1180/* Protocol Control Unit Functions */
ccfe5552 1181extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
a25d1e4c 1182void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
fa1c114f 1183/* BSSID Functions */
a25d1e4c 1184int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
418de6d9 1185void ath5k_hw_set_bssid(struct ath5k_hw *ah);
a25d1e4c 1186void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
fa1c114f 1187/* Receive start/stop functions */
a25d1e4c
PR		 1188void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1189void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
fa1c114f 1190/* RX Filter functions */
a25d1e4c
PR		 1191void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1192u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1193void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
c6e387a2 1194/* Beacon control functions */
a25d1e4c
PR		 1195u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1196void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1197void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1198void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
fa1c114f
JS		 1199/* ACK bit rate */
1200void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
3578e6eb
LT		 1201/* Clock rate related functions */
1202unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1203unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1204unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah);
c6e387a2 1205
fa1c114f 1206/* Queue Control Unit, DFS Control Unit Functions */
a25d1e4c
PR		 1207int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1208 struct ath5k_txq_info *queue_info);
1209int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1210 const struct ath5k_txq_info *queue_info);
1211int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1212 enum ath5k_tx_queue queue_type,
1213 struct ath5k_txq_info *queue_info);
1214u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1215void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1216int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1217int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
c6e387a2 1218
fa1c114f 1219/* Hardware Descriptor Functions */
a25d1e4c 1220int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
a6668193
BR		 1221int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1222 u32 size, unsigned int flags);
1223int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1224 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1225 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
c6e387a2 1226
fa1c114f 1227/* GPIO Functions */
a25d1e4c
PR		 1228void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1229int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1230int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1231u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1232int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1233void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1234 u32 interrupt_level);
c6e387a2 1235
e6a3b616 1236/* rfkill Functions */
a25d1e4c
PR		 1237void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1238void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
e6a3b616 1239
fa1c114f 1240/* Misc functions */
c6e387a2 1241int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
a25d1e4c
PR		 1242int ath5k_hw_get_capability(struct ath5k_hw *ah,
1243 enum ath5k_capability_type cap_type, u32 capability,
1244 u32 *result);
1245int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1246int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
fa1c114f
JS		 1247
1248/* Initial register settings functions */
a25d1e4c 1249int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
c6e387a2 1250
fa1c114f 1251/* Initialize RF */
a25d1e4c
PR		 1252int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1253 struct ieee80211_channel *channel,
1254 unsigned int mode);
1255int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1256enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1257int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
fa1c114f 1258/* PHY/RF channel functions */
a25d1e4c
PR		 1259bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1260int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
fa1c114f 1261/* PHY calibration */
e5e2647f 1262void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
a25d1e4c
PR		 1263int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1264 struct ieee80211_channel *channel);
9e04a7eb 1265void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
57e6c56d
NK		 1266/* Spur mitigation */
1267bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
a25d1e4c 1268 struct ieee80211_channel *channel);
57e6c56d 1269void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
a25d1e4c 1270 struct ieee80211_channel *channel);
fa1c114f 1271/* Misc PHY functions */
a25d1e4c
PR		 1272u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1273int ath5k_hw_phy_disable(struct ath5k_hw *ah);
2bed03eb 1274/* Antenna control */
a25d1e4c 1275void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
0ca74027 1276void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
fa1c114f 1277/* TX power setup */
a25d1e4c
PR		 1278int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1279 u8 ee_mode, u8 txpower);
1280int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
fa1c114f 1281
c6e387a2
NK		 1282/*
1283 * Functions used internaly
1284 */
1285
e5aa8474
LR		 1286static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1287{
1288 return &ah->common;
1289}
1290
1291static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1292{
1293 return &(ath5k_hw_common(ah)->regulatory);
1294}
1295
fa1c114f
JS		 1296static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1297{
1298 return ioread32(ah->ah_iobase + reg);
1299}
1300
1301static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1302{
1303 iowrite32(val, ah->ah_iobase + reg);
1304}
1305
c6e387a2
NK		 1306static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1307{
1308 u32 retval = 0, bit, i;
1309
1310 for (i = 0; i < bits; i++) {
1311 bit = (val >> i) & 1;
1312 retval = (retval << 1) | bit;
1313 }
1314
1315 return retval;
1316}
1317
b4ea449d
BR		 1318#define AVG_SAMPLES 8
1319#define AVG_FACTOR 1000
1320
1321/**
1322 * ath5k_moving_average - Exponentially weighted moving average
1323 * @avg: average structure
1324 * @val: current value
1325 *
1326 * This implementation make use of a struct ath5k_avg_val to prevent rounding
1327 * errors.
1328 */
1329static inline struct ath5k_avg_val
1330ath5k_moving_average(const struct ath5k_avg_val avg, const int val)
1331{
1332 struct ath5k_avg_val new;
1333 new.avg_weight = avg.avg_weight ?
1334 (((avg.avg_weight * ((AVG_SAMPLES) - 1)) +
1335 (val * (AVG_FACTOR))) / (AVG_SAMPLES)) :
1336 (val * (AVG_FACTOR));
1337 new.avg = new.avg_weight / (AVG_FACTOR);
1338 return new;
1339}
1340
fa1c114f 1341#endif
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