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1 | /* |
2 | * Copyright (C) 2010 Bruno Randolf <br1@einfach.org> | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "ath5k.h" | |
18 | #include "base.h" | |
19 | #include "reg.h" | |
20 | #include "debug.h" | |
21 | #include "ani.h" | |
22 | ||
23 | /** | |
24 | * DOC: Basic ANI Operation | |
25 | * | |
26 | * Adaptive Noise Immunity (ANI) controls five noise immunity parameters | |
27 | * depending on the amount of interference in the environment, increasing | |
28 | * or reducing sensitivity as necessary. | |
29 | * | |
30 | * The parameters are: | |
31 | * - "noise immunity" | |
32 | * - "spur immunity" | |
33 | * - "firstep level" | |
34 | * - "OFDM weak signal detection" | |
35 | * - "CCK weak signal detection" | |
36 | * | |
37 | * Basically we look at the amount of ODFM and CCK timing errors we get and then | |
38 | * raise or lower immunity accordingly by setting one or more of these | |
39 | * parameters. | |
40 | * Newer chipsets have PHY error counters in hardware which will generate a MIB | |
41 | * interrupt when they overflow. Older hardware has too enable PHY error frames | |
42 | * by setting a RX flag and then count every single PHY error. When a specified | |
43 | * threshold of errors has been reached we will raise immunity. | |
44 | * Also we regularly check the amount of errors and lower or raise immunity as | |
45 | * necessary. | |
46 | */ | |
47 | ||
48 | ||
49 | /*** ANI parameter control ***/ | |
50 | ||
51 | /** | |
52 | * ath5k_ani_set_noise_immunity_level() - Set noise immunity level | |
53 | * | |
54 | * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL | |
55 | */ | |
56 | void | |
57 | ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) | |
58 | { | |
59 | /* TODO: | |
60 | * ANI documents suggest the following five levels to use, but the HAL | |
61 | * and ath9k use only use the last two levels, making this | |
62 | * essentially an on/off option. There *may* be a reason for this (???), | |
63 | * so i stick with the HAL version for now... | |
64 | */ | |
65 | #if 0 | |
66 | const s8 hi[] = { -18, -18, -16, -14, -12 }; | |
67 | const s8 lo[] = { -52, -56, -60, -64, -70 }; | |
68 | const s8 sz[] = { -34, -41, -48, -55, -62 }; | |
69 | const s8 fr[] = { -70, -72, -75, -78, -80 }; | |
70 | #else | |
71 | const s8 sz[] = { -55, -62 }; | |
72 | const s8 lo[] = { -64, -70 }; | |
73 | const s8 hi[] = { -14, -12 }; | |
74 | const s8 fr[] = { -78, -80 }; | |
75 | #endif | |
05e8594d | 76 | if (level < 0 || level >= ARRAY_SIZE(sz)) { |
4f424867 BR |
77 | ATH5K_ERR(ah->ah_sc, "noise immuniy level %d out of range", |
78 | level); | |
2111ac0d BR |
79 | return; |
80 | } | |
81 | ||
82 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, | |
83 | AR5K_PHY_DESIRED_SIZE_TOT, sz[level]); | |
84 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, | |
85 | AR5K_PHY_AGCCOARSE_LO, lo[level]); | |
86 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, | |
87 | AR5K_PHY_AGCCOARSE_HI, hi[level]); | |
88 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, | |
89 | AR5K_PHY_SIG_FIRPWR, fr[level]); | |
90 | ||
91 | ah->ah_sc->ani_state.noise_imm_level = level; | |
92 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); | |
93 | } | |
94 | ||
95 | ||
96 | /** | |
97 | * ath5k_ani_set_spur_immunity_level() - Set spur immunity level | |
98 | * | |
99 | * @level: level between 0 and @max_spur_level (the maximum level is dependent | |
100 | * on the chip revision). | |
101 | */ | |
102 | void | |
103 | ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level) | |
104 | { | |
105 | const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; | |
106 | ||
05e8594d | 107 | if (level < 0 || level >= ARRAY_SIZE(val) || |
2111ac0d | 108 | level > ah->ah_sc->ani_state.max_spur_level) { |
4f424867 BR |
109 | ATH5K_ERR(ah->ah_sc, "spur immunity level %d out of range", |
110 | level); | |
2111ac0d BR |
111 | return; |
112 | } | |
113 | ||
114 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, | |
115 | AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]); | |
116 | ||
117 | ah->ah_sc->ani_state.spur_level = level; | |
118 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); | |
119 | } | |
120 | ||
121 | ||
122 | /** | |
123 | * ath5k_ani_set_firstep_level() - Set "firstep" level | |
124 | * | |
125 | * @level: level between 0 and @ATH5K_ANI_MAX_FIRSTEP_LVL | |
126 | */ | |
127 | void | |
128 | ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level) | |
129 | { | |
130 | const int val[] = { 0, 4, 8 }; | |
131 | ||
05e8594d | 132 | if (level < 0 || level >= ARRAY_SIZE(val)) { |
4f424867 | 133 | ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level); |
2111ac0d BR |
134 | return; |
135 | } | |
136 | ||
137 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, | |
138 | AR5K_PHY_SIG_FIRSTEP, val[level]); | |
139 | ||
140 | ah->ah_sc->ani_state.firstep_level = level; | |
141 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); | |
142 | } | |
143 | ||
144 | ||
145 | /** | |
146 | * ath5k_ani_set_ofdm_weak_signal_detection() - Control OFDM weak signal | |
147 | * detection | |
148 | * | |
149 | * @on: turn on or off | |
150 | */ | |
151 | void | |
152 | ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on) | |
153 | { | |
154 | const int m1l[] = { 127, 50 }; | |
155 | const int m2l[] = { 127, 40 }; | |
156 | const int m1[] = { 127, 0x4d }; | |
157 | const int m2[] = { 127, 0x40 }; | |
158 | const int m2cnt[] = { 31, 16 }; | |
159 | const int m2lcnt[] = { 63, 48 }; | |
160 | ||
161 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, | |
162 | AR5K_PHY_WEAK_OFDM_LOW_THR_M1, m1l[on]); | |
163 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, | |
164 | AR5K_PHY_WEAK_OFDM_LOW_THR_M2, m2l[on]); | |
165 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, | |
166 | AR5K_PHY_WEAK_OFDM_HIGH_THR_M1, m1[on]); | |
167 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, | |
168 | AR5K_PHY_WEAK_OFDM_HIGH_THR_M2, m2[on]); | |
169 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, | |
170 | AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT, m2cnt[on]); | |
171 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, | |
172 | AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT, m2lcnt[on]); | |
173 | ||
174 | if (on) | |
175 | AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, | |
176 | AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN); | |
177 | else | |
178 | AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, | |
179 | AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN); | |
180 | ||
181 | ah->ah_sc->ani_state.ofdm_weak_sig = on; | |
182 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s", | |
183 | on ? "on" : "off"); | |
184 | } | |
185 | ||
186 | ||
187 | /** | |
188 | * ath5k_ani_set_cck_weak_signal_detection() - control CCK weak signal detection | |
189 | * | |
190 | * @on: turn on or off | |
191 | */ | |
192 | void | |
193 | ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on) | |
194 | { | |
195 | const int val[] = { 8, 6 }; | |
196 | AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR, | |
197 | AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]); | |
198 | ah->ah_sc->ani_state.cck_weak_sig = on; | |
199 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s", | |
200 | on ? "on" : "off"); | |
201 | } | |
202 | ||
203 | ||
204 | /*** ANI algorithm ***/ | |
205 | ||
206 | /** | |
207 | * ath5k_ani_raise_immunity() - Increase noise immunity | |
208 | * | |
209 | * @ofdm_trigger: If this is true we are called because of too many OFDM errors, | |
210 | * the algorithm will tune more parameters then. | |
211 | * | |
212 | * Try to raise noise immunity (=decrease sensitivity) in several steps | |
213 | * depending on the average RSSI of the beacons we received. | |
214 | */ | |
215 | static void | |
216 | ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as, | |
217 | bool ofdm_trigger) | |
218 | { | |
219 | int rssi = ah->ah_beacon_rssi_avg.avg; | |
220 | ||
221 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)", | |
222 | ofdm_trigger ? "ODFM" : "CCK"); | |
223 | ||
224 | /* first: raise noise immunity */ | |
225 | if (as->noise_imm_level < ATH5K_ANI_MAX_NOISE_IMM_LVL) { | |
226 | ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level + 1); | |
227 | return; | |
228 | } | |
229 | ||
230 | /* only OFDM: raise spur immunity level */ | |
231 | if (ofdm_trigger && | |
232 | as->spur_level < ah->ah_sc->ani_state.max_spur_level) { | |
233 | ath5k_ani_set_spur_immunity_level(ah, as->spur_level + 1); | |
234 | return; | |
235 | } | |
236 | ||
237 | /* AP mode */ | |
238 | if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) { | |
239 | if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) | |
240 | ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); | |
241 | return; | |
242 | } | |
243 | ||
244 | /* STA and IBSS mode */ | |
245 | ||
246 | /* TODO: for IBSS mode it would be better to keep a beacon RSSI average | |
247 | * per each neighbour node and use the minimum of these, to make sure we | |
248 | * don't shut out a remote node by raising immunity too high. */ | |
249 | ||
250 | if (rssi > ATH5K_ANI_RSSI_THR_HIGH) { | |
251 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, | |
252 | "beacon RSSI high"); | |
253 | /* only OFDM: beacon RSSI is high, we can disable ODFM weak | |
254 | * signal detection */ | |
255 | if (ofdm_trigger && as->ofdm_weak_sig == true) { | |
256 | ath5k_ani_set_ofdm_weak_signal_detection(ah, false); | |
257 | ath5k_ani_set_spur_immunity_level(ah, 0); | |
258 | return; | |
259 | } | |
260 | /* as a last resort or CCK: raise firstep level */ | |
261 | if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) { | |
262 | ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); | |
263 | return; | |
264 | } | |
265 | } else if (rssi > ATH5K_ANI_RSSI_THR_LOW) { | |
266 | /* beacon RSSI in mid range, we need OFDM weak signal detect, | |
267 | * but can raise firstep level */ | |
268 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, | |
269 | "beacon RSSI mid"); | |
270 | if (ofdm_trigger && as->ofdm_weak_sig == false) | |
271 | ath5k_ani_set_ofdm_weak_signal_detection(ah, true); | |
272 | if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) | |
273 | ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); | |
274 | return; | |
275 | } else if (ah->ah_current_channel->band == IEEE80211_BAND_2GHZ) { | |
276 | /* beacon RSSI is low. in B/G mode turn of OFDM weak signal | |
277 | * detect and zero firstep level to maximize CCK sensitivity */ | |
278 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, | |
279 | "beacon RSSI low, 2GHz"); | |
280 | if (ofdm_trigger && as->ofdm_weak_sig == true) | |
281 | ath5k_ani_set_ofdm_weak_signal_detection(ah, false); | |
282 | if (as->firstep_level > 0) | |
283 | ath5k_ani_set_firstep_level(ah, 0); | |
284 | return; | |
285 | } | |
286 | ||
287 | /* TODO: why not?: | |
288 | if (as->cck_weak_sig == true) { | |
289 | ath5k_ani_set_cck_weak_signal_detection(ah, false); | |
290 | } | |
291 | */ | |
292 | } | |
293 | ||
294 | ||
295 | /** | |
296 | * ath5k_ani_lower_immunity() - Decrease noise immunity | |
297 | * | |
298 | * Try to lower noise immunity (=increase sensitivity) in several steps | |
299 | * depending on the average RSSI of the beacons we received. | |
300 | */ | |
301 | static void | |
302 | ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as) | |
303 | { | |
304 | int rssi = ah->ah_beacon_rssi_avg.avg; | |
305 | ||
306 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity"); | |
307 | ||
308 | if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) { | |
309 | /* AP mode */ | |
310 | if (as->firstep_level > 0) { | |
311 | ath5k_ani_set_firstep_level(ah, as->firstep_level - 1); | |
312 | return; | |
313 | } | |
314 | } else { | |
315 | /* STA and IBSS mode (see TODO above) */ | |
316 | if (rssi > ATH5K_ANI_RSSI_THR_HIGH) { | |
317 | /* beacon signal is high, leave OFDM weak signal | |
318 | * detection off or it may oscillate | |
319 | * TODO: who said it's off??? */ | |
320 | } else if (rssi > ATH5K_ANI_RSSI_THR_LOW) { | |
321 | /* beacon RSSI is mid-range: turn on ODFM weak signal | |
322 | * detection and next, lower firstep level */ | |
323 | if (as->ofdm_weak_sig == false) { | |
324 | ath5k_ani_set_ofdm_weak_signal_detection(ah, | |
325 | true); | |
326 | return; | |
327 | } | |
328 | if (as->firstep_level > 0) { | |
329 | ath5k_ani_set_firstep_level(ah, | |
330 | as->firstep_level - 1); | |
331 | return; | |
332 | } | |
333 | } else { | |
334 | /* beacon signal is low: only reduce firstep level */ | |
335 | if (as->firstep_level > 0) { | |
336 | ath5k_ani_set_firstep_level(ah, | |
337 | as->firstep_level - 1); | |
338 | return; | |
339 | } | |
340 | } | |
341 | } | |
342 | ||
343 | /* all modes */ | |
344 | if (as->spur_level > 0) { | |
345 | ath5k_ani_set_spur_immunity_level(ah, as->spur_level - 1); | |
346 | return; | |
347 | } | |
348 | ||
349 | /* finally, reduce noise immunity */ | |
350 | if (as->noise_imm_level > 0) { | |
351 | ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level - 1); | |
352 | return; | |
353 | } | |
354 | } | |
355 | ||
356 | ||
357 | /** | |
358 | * ath5k_hw_ani_get_listen_time() - Calculate time spent listening | |
359 | * | |
360 | * Return an approximation of the time spent "listening" in milliseconds (ms) | |
361 | * since the last call of this function by deducting the cycles spent | |
362 | * transmitting and receiving from the total cycle count. | |
363 | * Save profile count values for debugging/statistics and because we might want | |
364 | * to use them later. | |
365 | * | |
366 | * We assume no one else clears these registers! | |
367 | */ | |
368 | static int | |
369 | ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as) | |
370 | { | |
371 | int listen; | |
372 | ||
373 | /* freeze */ | |
374 | ath5k_hw_reg_write(ah, AR5K_MIBC_FMC, AR5K_MIBC); | |
375 | /* read */ | |
376 | as->pfc_cycles = ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE); | |
377 | as->pfc_busy = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR); | |
378 | as->pfc_tx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX); | |
379 | as->pfc_rx = ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX); | |
380 | /* clear */ | |
381 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX); | |
382 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX); | |
383 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR); | |
384 | ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE); | |
385 | /* un-freeze */ | |
386 | ath5k_hw_reg_write(ah, 0, AR5K_MIBC); | |
387 | ||
388 | /* TODO: where does 44000 come from? (11g clock rate?) */ | |
389 | listen = (as->pfc_cycles - as->pfc_rx - as->pfc_tx) / 44000; | |
390 | ||
391 | if (as->pfc_cycles == 0 || listen < 0) | |
392 | return 0; | |
393 | return listen; | |
394 | } | |
395 | ||
396 | ||
397 | /** | |
398 | * ath5k_ani_save_and_clear_phy_errors() - Clear and save PHY error counters | |
399 | * | |
400 | * Clear the PHY error counters as soon as possible, since this might be called | |
401 | * from a MIB interrupt and we want to make sure we don't get interrupted again. | |
402 | * Add the count of CCK and OFDM errors to our internal state, so it can be used | |
403 | * by the algorithm later. | |
404 | * | |
405 | * Will be called from interrupt and tasklet context. | |
406 | * Returns 0 if both counters are zero. | |
407 | */ | |
408 | static int | |
409 | ath5k_ani_save_and_clear_phy_errors(struct ath5k_hw *ah, | |
410 | struct ath5k_ani_state *as) | |
411 | { | |
412 | unsigned int ofdm_err, cck_err; | |
413 | ||
414 | if (!ah->ah_capabilities.cap_has_phyerr_counters) | |
415 | return 0; | |
416 | ||
417 | ofdm_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1); | |
418 | cck_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2); | |
419 | ||
420 | /* reset counters first, we might be in a hurry (interrupt) */ | |
421 | ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH, | |
422 | AR5K_PHYERR_CNT1); | |
423 | ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH, | |
424 | AR5K_PHYERR_CNT2); | |
425 | ||
426 | ofdm_err = ATH5K_ANI_OFDM_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX - ofdm_err); | |
427 | cck_err = ATH5K_ANI_CCK_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX - cck_err); | |
428 | ||
429 | /* sometimes both can be zero, especially when there is a superfluous | |
430 | * second interrupt. detect that here and return an error. */ | |
431 | if (ofdm_err <= 0 && cck_err <= 0) | |
432 | return 0; | |
433 | ||
434 | /* avoid negative values should one of the registers overflow */ | |
435 | if (ofdm_err > 0) { | |
436 | as->ofdm_errors += ofdm_err; | |
437 | as->sum_ofdm_errors += ofdm_err; | |
438 | } | |
439 | if (cck_err > 0) { | |
440 | as->cck_errors += cck_err; | |
441 | as->sum_cck_errors += cck_err; | |
442 | } | |
443 | return 1; | |
444 | } | |
445 | ||
446 | ||
447 | /** | |
448 | * ath5k_ani_period_restart() - Restart ANI period | |
449 | * | |
450 | * Just reset counters, so they are clear for the next "ani period". | |
451 | */ | |
452 | static void | |
453 | ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as) | |
454 | { | |
455 | /* keep last values for debugging */ | |
456 | as->last_ofdm_errors = as->ofdm_errors; | |
457 | as->last_cck_errors = as->cck_errors; | |
458 | as->last_listen = as->listen_time; | |
459 | ||
460 | as->ofdm_errors = 0; | |
461 | as->cck_errors = 0; | |
462 | as->listen_time = 0; | |
463 | } | |
464 | ||
465 | ||
466 | /** | |
467 | * ath5k_ani_calibration() - The main ANI calibration function | |
468 | * | |
469 | * We count OFDM and CCK errors relative to the time where we did not send or | |
470 | * receive ("listen" time) and raise or lower immunity accordingly. | |
471 | * This is called regularly (every second) from the calibration timer, but also | |
472 | * when an error threshold has been reached. | |
473 | * | |
474 | * In order to synchronize access from different contexts, this should be | |
475 | * called only indirectly by scheduling the ANI tasklet! | |
476 | */ | |
477 | void | |
478 | ath5k_ani_calibration(struct ath5k_hw *ah) | |
479 | { | |
480 | struct ath5k_ani_state *as = &ah->ah_sc->ani_state; | |
481 | int listen, ofdm_high, ofdm_low, cck_high, cck_low; | |
482 | ||
2111ac0d | 483 | /* get listen time since last call and add it to the counter because we |
9537a162 BR |
484 | * might not have restarted the "ani period" last time. |
485 | * always do this to calculate the busy time also in manual mode */ | |
2111ac0d BR |
486 | listen = ath5k_hw_ani_get_listen_time(ah, as); |
487 | as->listen_time += listen; | |
488 | ||
9537a162 BR |
489 | if (as->ani_mode != ATH5K_ANI_MODE_AUTO) |
490 | return; | |
491 | ||
2111ac0d BR |
492 | ath5k_ani_save_and_clear_phy_errors(ah, as); |
493 | ||
494 | ofdm_high = as->listen_time * ATH5K_ANI_OFDM_TRIG_HIGH / 1000; | |
495 | cck_high = as->listen_time * ATH5K_ANI_CCK_TRIG_HIGH / 1000; | |
496 | ofdm_low = as->listen_time * ATH5K_ANI_OFDM_TRIG_LOW / 1000; | |
497 | cck_low = as->listen_time * ATH5K_ANI_CCK_TRIG_LOW / 1000; | |
498 | ||
499 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, | |
500 | "listen %d (now %d)", as->listen_time, listen); | |
501 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, | |
502 | "check high ofdm %d/%d cck %d/%d", | |
503 | as->ofdm_errors, ofdm_high, as->cck_errors, cck_high); | |
504 | ||
505 | if (as->ofdm_errors > ofdm_high || as->cck_errors > cck_high) { | |
506 | /* too many PHY errors - we have to raise immunity */ | |
507 | bool ofdm_flag = as->ofdm_errors > ofdm_high ? true : false; | |
508 | ath5k_ani_raise_immunity(ah, as, ofdm_flag); | |
509 | ath5k_ani_period_restart(ah, as); | |
510 | ||
511 | } else if (as->listen_time > 5 * ATH5K_ANI_LISTEN_PERIOD) { | |
512 | /* If more than 5 (TODO: why 5?) periods have passed and we got | |
513 | * relatively little errors we can try to lower immunity */ | |
514 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, | |
515 | "check low ofdm %d/%d cck %d/%d", | |
516 | as->ofdm_errors, ofdm_low, as->cck_errors, cck_low); | |
517 | ||
518 | if (as->ofdm_errors <= ofdm_low && as->cck_errors <= cck_low) | |
519 | ath5k_ani_lower_immunity(ah, as); | |
520 | ||
521 | ath5k_ani_period_restart(ah, as); | |
522 | } | |
523 | } | |
524 | ||
525 | ||
526 | /*** INTERRUPT HANDLER ***/ | |
527 | ||
528 | /** | |
529 | * ath5k_ani_mib_intr() - Interrupt handler for ANI MIB counters | |
530 | * | |
531 | * Just read & reset the registers quickly, so they don't generate more | |
532 | * interrupts, save the counters and schedule the tasklet to decide whether | |
533 | * to raise immunity or not. | |
534 | * | |
535 | * We just need to handle PHY error counters, ath5k_hw_update_mib_counters() | |
536 | * should take care of all "normal" MIB interrupts. | |
537 | */ | |
538 | void | |
539 | ath5k_ani_mib_intr(struct ath5k_hw *ah) | |
540 | { | |
541 | struct ath5k_ani_state *as = &ah->ah_sc->ani_state; | |
542 | ||
543 | /* nothing to do here if HW does not have PHY error counters - they | |
544 | * can't be the reason for the MIB interrupt then */ | |
545 | if (!ah->ah_capabilities.cap_has_phyerr_counters) | |
546 | return; | |
547 | ||
548 | /* not in use but clear anyways */ | |
549 | ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); | |
550 | ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); | |
551 | ||
552 | if (ah->ah_sc->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO) | |
553 | return; | |
554 | ||
555 | /* if one of the errors triggered, we can get a superfluous second | |
556 | * interrupt, even though we have already reset the register. the | |
557 | * function detects that so we can return early */ | |
558 | if (ath5k_ani_save_and_clear_phy_errors(ah, as) == 0) | |
559 | return; | |
560 | ||
561 | if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH || | |
562 | as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH) | |
563 | tasklet_schedule(&ah->ah_sc->ani_tasklet); | |
564 | } | |
565 | ||
566 | ||
567 | /** | |
568 | * ath5k_ani_phy_error_report() - Used by older HW to report PHY errors | |
569 | * | |
570 | * This is used by hardware without PHY error counters to report PHY errors | |
571 | * on a frame-by-frame basis, instead of the interrupt. | |
572 | */ | |
573 | void | |
574 | ath5k_ani_phy_error_report(struct ath5k_hw *ah, | |
575 | enum ath5k_phy_error_code phyerr) | |
576 | { | |
577 | struct ath5k_ani_state *as = &ah->ah_sc->ani_state; | |
578 | ||
579 | if (phyerr == AR5K_RX_PHY_ERROR_OFDM_TIMING) { | |
580 | as->ofdm_errors++; | |
581 | if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH) | |
582 | tasklet_schedule(&ah->ah_sc->ani_tasklet); | |
583 | } else if (phyerr == AR5K_RX_PHY_ERROR_CCK_TIMING) { | |
584 | as->cck_errors++; | |
585 | if (as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH) | |
586 | tasklet_schedule(&ah->ah_sc->ani_tasklet); | |
587 | } | |
588 | } | |
589 | ||
590 | ||
591 | /*** INIT ***/ | |
592 | ||
593 | /** | |
594 | * ath5k_enable_phy_err_counters() - Enable PHY error counters | |
595 | * | |
596 | * Enable PHY error counters for OFDM and CCK timing errors. | |
597 | */ | |
598 | static void | |
599 | ath5k_enable_phy_err_counters(struct ath5k_hw *ah) | |
600 | { | |
601 | ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH, | |
602 | AR5K_PHYERR_CNT1); | |
603 | ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH, | |
604 | AR5K_PHYERR_CNT2); | |
605 | ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHYERR_CNT1_MASK); | |
606 | ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_CCK, AR5K_PHYERR_CNT2_MASK); | |
607 | ||
608 | /* not in use */ | |
609 | ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); | |
610 | ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); | |
611 | } | |
612 | ||
613 | ||
614 | /** | |
615 | * ath5k_disable_phy_err_counters() - Disable PHY error counters | |
616 | * | |
617 | * Disable PHY error counters for OFDM and CCK timing errors. | |
618 | */ | |
619 | static void | |
620 | ath5k_disable_phy_err_counters(struct ath5k_hw *ah) | |
621 | { | |
622 | ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1); | |
623 | ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2); | |
624 | ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1_MASK); | |
625 | ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2_MASK); | |
626 | ||
627 | /* not in use */ | |
628 | ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); | |
629 | ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); | |
630 | } | |
631 | ||
632 | ||
633 | /** | |
634 | * ath5k_ani_init() - Initialize ANI | |
635 | * @mode: Which mode to use (auto, manual high, manual low, off) | |
636 | * | |
637 | * Initialize ANI according to mode. | |
638 | */ | |
639 | void | |
640 | ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode) | |
641 | { | |
642 | /* ANI is only possible on 5212 and newer */ | |
643 | if (ah->ah_version < AR5K_AR5212) | |
644 | return; | |
645 | ||
646 | /* clear old state information */ | |
647 | memset(&ah->ah_sc->ani_state, 0, sizeof(ah->ah_sc->ani_state)); | |
648 | ||
649 | /* older hardware has more spur levels than newer */ | |
650 | if (ah->ah_mac_srev < AR5K_SREV_AR2414) | |
651 | ah->ah_sc->ani_state.max_spur_level = 7; | |
652 | else | |
653 | ah->ah_sc->ani_state.max_spur_level = 2; | |
654 | ||
655 | /* initial values for our ani parameters */ | |
656 | if (mode == ATH5K_ANI_MODE_OFF) { | |
657 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI off\n"); | |
658 | } else if (mode == ATH5K_ANI_MODE_MANUAL_LOW) { | |
659 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, | |
660 | "ANI manual low -> high sensitivity\n"); | |
661 | ath5k_ani_set_noise_immunity_level(ah, 0); | |
662 | ath5k_ani_set_spur_immunity_level(ah, 0); | |
663 | ath5k_ani_set_firstep_level(ah, 0); | |
664 | ath5k_ani_set_ofdm_weak_signal_detection(ah, true); | |
665 | ath5k_ani_set_cck_weak_signal_detection(ah, true); | |
666 | } else if (mode == ATH5K_ANI_MODE_MANUAL_HIGH) { | |
667 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, | |
668 | "ANI manual high -> low sensitivity\n"); | |
669 | ath5k_ani_set_noise_immunity_level(ah, | |
670 | ATH5K_ANI_MAX_NOISE_IMM_LVL); | |
671 | ath5k_ani_set_spur_immunity_level(ah, | |
672 | ah->ah_sc->ani_state.max_spur_level); | |
673 | ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL); | |
674 | ath5k_ani_set_ofdm_weak_signal_detection(ah, false); | |
675 | ath5k_ani_set_cck_weak_signal_detection(ah, false); | |
676 | } else if (mode == ATH5K_ANI_MODE_AUTO) { | |
677 | ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI auto\n"); | |
678 | ath5k_ani_set_noise_immunity_level(ah, 0); | |
679 | ath5k_ani_set_spur_immunity_level(ah, 0); | |
680 | ath5k_ani_set_firstep_level(ah, 0); | |
681 | ath5k_ani_set_ofdm_weak_signal_detection(ah, true); | |
682 | ath5k_ani_set_cck_weak_signal_detection(ah, false); | |
683 | } | |
684 | ||
685 | /* newer hardware has PHY error counter registers which we can use to | |
686 | * get OFDM and CCK error counts. older hardware has to set rxfilter and | |
687 | * report every single PHY error by calling ath5k_ani_phy_error_report() | |
688 | */ | |
689 | if (mode == ATH5K_ANI_MODE_AUTO) { | |
690 | if (ah->ah_capabilities.cap_has_phyerr_counters) | |
691 | ath5k_enable_phy_err_counters(ah); | |
692 | else | |
693 | ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) | | |
694 | AR5K_RX_FILTER_PHYERR); | |
695 | } else { | |
696 | if (ah->ah_capabilities.cap_has_phyerr_counters) | |
697 | ath5k_disable_phy_err_counters(ah); | |
698 | else | |
699 | ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) & | |
700 | ~AR5K_RX_FILTER_PHYERR); | |
701 | } | |
702 | ||
703 | ah->ah_sc->ani_state.ani_mode = mode; | |
704 | } | |
705 | ||
706 | ||
707 | /*** DEBUG ***/ | |
708 | ||
709 | #ifdef CONFIG_ATH5K_DEBUG | |
710 | ||
711 | void | |
712 | ath5k_ani_print_counters(struct ath5k_hw *ah) | |
713 | { | |
714 | /* clears too */ | |
715 | printk(KERN_NOTICE "ACK fail\t%d\n", | |
716 | ath5k_hw_reg_read(ah, AR5K_ACK_FAIL)); | |
717 | printk(KERN_NOTICE "RTS fail\t%d\n", | |
718 | ath5k_hw_reg_read(ah, AR5K_RTS_FAIL)); | |
719 | printk(KERN_NOTICE "RTS success\t%d\n", | |
720 | ath5k_hw_reg_read(ah, AR5K_RTS_OK)); | |
721 | printk(KERN_NOTICE "FCS error\t%d\n", | |
722 | ath5k_hw_reg_read(ah, AR5K_FCS_FAIL)); | |
723 | ||
724 | /* no clear */ | |
725 | printk(KERN_NOTICE "tx\t%d\n", | |
726 | ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX)); | |
727 | printk(KERN_NOTICE "rx\t%d\n", | |
728 | ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX)); | |
729 | printk(KERN_NOTICE "busy\t%d\n", | |
730 | ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR)); | |
731 | printk(KERN_NOTICE "cycles\t%d\n", | |
732 | ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE)); | |
733 | ||
734 | printk(KERN_NOTICE "AR5K_PHYERR_CNT1\t%d\n", | |
735 | ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1)); | |
736 | printk(KERN_NOTICE "AR5K_PHYERR_CNT2\t%d\n", | |
737 | ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2)); | |
738 | printk(KERN_NOTICE "AR5K_OFDM_FIL_CNT\t%d\n", | |
739 | ath5k_hw_reg_read(ah, AR5K_OFDM_FIL_CNT)); | |
740 | printk(KERN_NOTICE "AR5K_CCK_FIL_CNT\t%d\n", | |
741 | ath5k_hw_reg_read(ah, AR5K_CCK_FIL_CNT)); | |
742 | } | |
743 | ||
744 | #endif |