[net-next-2.6.git] / drivers / net / wireless / ath / ath.h

/*
 * Copyright (c) 2008-2009 Atheros Communications Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef ATH_H
#define ATH_H

#include <linux/skbuff.h>
#include <linux/if_ether.h>
#include <linux/spinlock.h>
#include <net/mac80211.h>

/*
 * The key cache is used for h/w cipher state and also for
 * tracking station state such as the current tx antenna.
 * We also setup a mapping table between key cache slot indices
 * and station state to short-circuit node lookups on rx.
 * Different parts have different size key caches.  We handle
 * up to ATH_KEYMAX entries (could dynamically allocate state).
 */
#define	ATH_KEYMAX	        128     /* max key cache size we handle */

static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};

struct ath_ani {
	bool caldone;
	unsigned int longcal_timer;
	unsigned int shortcal_timer;
	unsigned int resetcal_timer;
	unsigned int checkani_timer;
	struct timer_list timer;
};

struct ath_cycle_counters {
	u32 cycles;
	u32 rx_busy;
	u32 rx_frame;
	u32 tx_frame;
};

enum ath_device_state {
	ATH_HW_UNAVAILABLE,
	ATH_HW_INITIALIZED,
};

enum ath_bus_type {
	ATH_PCI,
	ATH_AHB,
	ATH_USB,
};

struct reg_dmn_pair_mapping {
	u16 regDmnEnum;
	u16 reg_5ghz_ctl;
	u16 reg_2ghz_ctl;
};

struct ath_regulatory {
	char alpha2[2];
	u16 country_code;
	u16 max_power_level;
	u32 tp_scale;
	u16 current_rd;
	u16 current_rd_ext;
	int16_t power_limit;
	struct reg_dmn_pair_mapping *regpair;
};

enum ath_crypt_caps {
	ATH_CRYPT_CAP_CIPHER_AESCCM		= BIT(0),
	ATH_CRYPT_CAP_MIC_COMBINED		= BIT(1),
};

struct ath_keyval {
	u8 kv_type;
	u8 kv_pad;
	u16 kv_len;
	u8 kv_val[16]; /* TK */
	u8 kv_mic[8]; /* Michael MIC key */
	u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
			 * supports both MIC keys in the same key cache entry;
			 * in that case, kv_mic is the RX key) */
};

enum ath_cipher {
	ATH_CIPHER_WEP = 0,
	ATH_CIPHER_AES_OCB = 1,
	ATH_CIPHER_AES_CCM = 2,
	ATH_CIPHER_CKIP = 3,
	ATH_CIPHER_TKIP = 4,
	ATH_CIPHER_CLR = 5,
	ATH_CIPHER_MIC = 127
};

/**
 * struct ath_ops - Register read/write operations
 *
 * @read: Register read
 * @write: Register write
 * @enable_write_buffer: Enable multiple register writes
 * @write_flush: flush buffered register writes and disable buffering
 */
struct ath_ops {
	unsigned int (*read)(void *, u32 reg_offset);
	void (*write)(void *, u32 val, u32 reg_offset);
	void (*enable_write_buffer)(void *);
	void (*write_flush) (void *);
};

struct ath_common;

struct ath_bus_ops {
	enum ath_bus_type ath_bus_type;
	void (*read_cachesize)(struct ath_common *common, int *csz);
	bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
	void (*bt_coex_prep)(struct ath_common *common);
};

struct ath_common {
	void *ah;
	void *priv;
	struct ieee80211_hw *hw;
	int debug_mask;
	enum ath_device_state state;

	struct ath_ani ani;

	u16 cachelsz;
	u16 curaid;
	u8 macaddr[ETH_ALEN];
	u8 curbssid[ETH_ALEN];
	u8 bssidmask[ETH_ALEN];

	u8 tx_chainmask;
	u8 rx_chainmask;

	u32 rx_bufsize;

	u32 keymax;
	DECLARE_BITMAP(keymap, ATH_KEYMAX);
	DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
	enum ath_crypt_caps crypt_caps;

	unsigned int clockrate;

	spinlock_t cc_lock;
	struct ath_cycle_counters cc_ani;
	struct ath_cycle_counters cc_survey;

	struct ath_regulatory regulatory;
	const struct ath_ops *ops;
	const struct ath_bus_ops *bus_ops;
};

struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
				u32 len,
				gfp_t gfp_mask);

void ath_hw_setbssidmask(struct ath_common *common);
void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
int ath_key_config(struct ath_common *common,
			  struct ieee80211_vif *vif,
			  struct ieee80211_sta *sta,
			  struct ieee80211_key_conf *key);
bool ath_hw_keyreset(struct ath_common *common, u16 entry);
void ath_hw_cycle_counters_update(struct ath_common *common);
int32_t ath_hw_get_listen_time(struct ath_common *common);

#endif /* ATH_H */
Commit	Line	Data
d15dd3e5 LR	1	/*
	2	* Copyright (c) 2008-2009 Atheros Communications Inc.
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	11	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	13	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	14	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef ATH_H
	18	#define ATH_H
	19
	20	#include <linux/skbuff.h>
bcd8f54a	21	#include <linux/if_ether.h>
b5bfc568	22	#include <linux/spinlock.h>
b002a4a9	23	#include <net/mac80211.h>
d15dd3e5	24
7e86c104 LR	25	/*
	26	* The key cache is used for h/w cipher state and also for
	27	* tracking station state such as the current tx antenna.
	28	* We also setup a mapping table between key cache slot indices
	29	* and station state to short-circuit node lookups on rx.
	30	* Different parts have different size key caches. We handle
	31	* up to ATH_KEYMAX entries (could dynamically allocate state).
	32	*/
	33	#define ATH_KEYMAX 128 /* max key cache size we handle */
	34
17753748 LR	35	static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
17753748 LR	36
3d536acf LR	37	struct ath_ani {
3d536acf LR	38	bool caldone;
3d536acf LR	39	unsigned int longcal_timer;
	40	unsigned int shortcal_timer;
	41	unsigned int resetcal_timer;
	42	unsigned int checkani_timer;
	43	struct timer_list timer;
	44	};
	45
b5bfc568 FF	46	struct ath_cycle_counters {
	47	u32 cycles;
	48	u32 rx_busy;
	49	u32 rx_frame;
	50	u32 tx_frame;
	51	};
	52
211f5859 LR	53	enum ath_device_state {
	54	ATH_HW_UNAVAILABLE,
	55	ATH_HW_INITIALIZED,
	56	};
	57
497ad9ad S	58	enum ath_bus_type {
	59	ATH_PCI,
	60	ATH_AHB,
	61	ATH_USB,
	62	};
	63
608b88cb LR	64	struct reg_dmn_pair_mapping {
	65	u16 regDmnEnum;
	66	u16 reg_5ghz_ctl;
	67	u16 reg_2ghz_ctl;
	68	};
	69
	70	struct ath_regulatory {
	71	char alpha2[2];
	72	u16 country_code;
	73	u16 max_power_level;
	74	u32 tp_scale;
	75	u16 current_rd;
	76	u16 current_rd_ext;
	77	int16_t power_limit;
	78	struct reg_dmn_pair_mapping *regpair;
	79	};
	80
34a13051	81	enum ath_crypt_caps {
ce2220d1 BR	82	ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
ce2220d1 BR	83	ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
34a13051 BR	84	};
34a13051 BR	85
1bba5b73 BR	86	struct ath_keyval {
	87	u8 kv_type;
	88	u8 kv_pad;
	89	u16 kv_len;
	90	u8 kv_val[16]; /* TK */
	91	u8 kv_mic[8]; /* Michael MIC key */
	92	u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
	93	* supports both MIC keys in the same key cache entry;
	94	* in that case, kv_mic is the RX key) */
	95	};
	96
	97	enum ath_cipher {
	98	ATH_CIPHER_WEP = 0,
	99	ATH_CIPHER_AES_OCB = 1,
	100	ATH_CIPHER_AES_CCM = 2,
	101	ATH_CIPHER_CKIP = 3,
	102	ATH_CIPHER_TKIP = 4,
	103	ATH_CIPHER_CLR = 5,
	104	ATH_CIPHER_MIC = 127
	105	};
	106
50f56316 S	107	/**
	108	* struct ath_ops - Register read/write operations
	109	*
	110	* @read: Register read
	111	* @write: Register write
	112	* @enable_write_buffer: Enable multiple register writes
435c1610	113	* @write_flush: flush buffered register writes and disable buffering
50f56316	114	*/
9e4bffd2 LR	115	struct ath_ops {
9e4bffd2 LR	116	unsigned int (read)(void , u32 reg_offset);
50f56316 S	117	void (write)(void , u32 val, u32 reg_offset);
50f56316 S	118	void (enable_write_buffer)(void );
50f56316	119	void (write_flush) (void );
9e4bffd2 LR	120	};
9e4bffd2 LR	121
5bb12791 LR	122	struct ath_common;
	123
	124	struct ath_bus_ops {
497ad9ad S	125	enum ath_bus_type ath_bus_type;
	126	void (read_cachesize)(struct ath_common common, int *csz);
	127	bool (eeprom_read)(struct ath_common common, u32 off, u16 *data);
	128	void (bt_coex_prep)(struct ath_common common);
5bb12791 LR	129	};
5bb12791 LR	130
d15dd3e5	131	struct ath_common {
13b81559	132	void *ah;
bc974f4a	133	void *priv;
b002a4a9	134	struct ieee80211_hw *hw;
c46917bb	135	int debug_mask;
211f5859	136	enum ath_device_state state;
c46917bb	137
3d536acf LR	138	struct ath_ani ani;
3d536acf LR	139
d15dd3e5	140	u16 cachelsz;
1510718d LR	141	u16 curaid;
	142	u8 macaddr[ETH_ALEN];
	143	u8 curbssid[ETH_ALEN];
	144	u8 bssidmask[ETH_ALEN];
c46917bb	145
43c27613 LR	146	u8 tx_chainmask;
	147	u8 rx_chainmask;
	148
cc861f74 LR	149	u32 rx_bufsize;
cc861f74 LR	150
7e86c104 LR	151	u32 keymax;
7e86c104 LR	152	DECLARE_BITMAP(keymap, ATH_KEYMAX);
56363dde	153	DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
34a13051	154	enum ath_crypt_caps crypt_caps;
7e86c104	155
dfdac8ac FF	156	unsigned int clockrate;
dfdac8ac FF	157
b5bfc568 FF	158	spinlock_t cc_lock;
	159	struct ath_cycle_counters cc_ani;
	160	struct ath_cycle_counters cc_survey;
	161
608b88cb	162	struct ath_regulatory regulatory;
9adca126	163	const struct ath_ops *ops;
5bb12791	164	const struct ath_bus_ops *bus_ops;
d15dd3e5 LR	165	};
	166
	167	struct sk_buff ath_rxbuf_alloc(struct ath_common common,
	168	u32 len,
	169	gfp_t gfp_mask);
	170
13b81559	171	void ath_hw_setbssidmask(struct ath_common *common);
1bba5b73 BR	172	void ath_key_delete(struct ath_common common, struct ieee80211_key_conf key);
	173	int ath_key_config(struct ath_common *common,
	174	struct ieee80211_vif *vif,
	175	struct ieee80211_sta *sta,
	176	struct ieee80211_key_conf *key);
	177	bool ath_hw_keyreset(struct ath_common *common, u16 entry);
b5bfc568 FF	178	void ath_hw_cycle_counters_update(struct ath_common *common);
b5bfc568 FF	179	int32_t ath_hw_get_listen_time(struct ath_common *common);
13b81559	180
d15dd3e5	181	#endif /* ATH_H */