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Merge branch 'for-linus' of git://android.git.kernel.org/kernel/tegra
[net-next-2.6.git] / drivers / net / wireless / adm8211.c
CommitLineData
cc0b88cf
MW		 1
2/*
3 * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
4 *
5 * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
6 * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
7 * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
8 * and used with permission.
9 *
10 * Much thanks to Infineon-ADMtek for their support of this driver.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. See README and COPYING for
15 * more details.
16 */
17
18#include <linux/init.h>
19#include <linux/if.h>
20#include <linux/skbuff.h>
5a0e3ad6 21#include <linux/slab.h>
cc0b88cf
MW		 22#include <linux/etherdevice.h>
23#include <linux/pci.h>
24#include <linux/delay.h>
25#include <linux/crc32.h>
26#include <linux/eeprom_93cx6.h>
27#include <net/mac80211.h>
28
29#include "adm8211.h"
30
31MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
32MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
33MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
34MODULE_SUPPORTED_DEVICE("ADM8211");
35MODULE_LICENSE("GPL");
36
37static unsigned int tx_ring_size __read_mostly = 16;
38static unsigned int rx_ring_size __read_mostly = 16;
39
40module_param(tx_ring_size, uint, 0);
41module_param(rx_ring_size, uint, 0);
42
a3aa1884 43static DEFINE_PCI_DEVICE_TABLE(adm8211_pci_id_table) = {
cc0b88cf
MW		 44 /* ADMtek ADM8211 */
45 { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
46 { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
47 { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
48 { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
49 { 0 }
50};
51
8318d78a
JB		 52static struct ieee80211_rate adm8211_rates[] = {
53 { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
54 { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
55 { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
56 { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
57 { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
58};
59
60static const struct ieee80211_channel adm8211_channels[] = {
61 { .center_freq = 2412},
62 { .center_freq = 2417},
63 { .center_freq = 2422},
64 { .center_freq = 2427},
65 { .center_freq = 2432},
66 { .center_freq = 2437},
67 { .center_freq = 2442},
68 { .center_freq = 2447},
69 { .center_freq = 2452},
70 { .center_freq = 2457},
71 { .center_freq = 2462},
72 { .center_freq = 2467},
73 { .center_freq = 2472},
74 { .center_freq = 2484},
75};
76
77
cc0b88cf
MW		 78static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
79{
80 struct adm8211_priv *priv = eeprom->data;
81 u32 reg = ADM8211_CSR_READ(SPR);
82
83 eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
84 eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
85 eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
86 eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
87}
88
89static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
90{
91 struct adm8211_priv *priv = eeprom->data;
92 u32 reg = 0x4000 | ADM8211_SPR_SRS;
93
94 if (eeprom->reg_data_in)
95 reg |= ADM8211_SPR_SDI;
96 if (eeprom->reg_data_out)
97 reg |= ADM8211_SPR_SDO;
98 if (eeprom->reg_data_clock)
99 reg |= ADM8211_SPR_SCLK;
100 if (eeprom->reg_chip_select)
101 reg |= ADM8211_SPR_SCS;
102
103 ADM8211_CSR_WRITE(SPR, reg);
104 ADM8211_CSR_READ(SPR); /* eeprom_delay */
105}
106
107static int adm8211_read_eeprom(struct ieee80211_hw *dev)
108{
109 struct adm8211_priv *priv = dev->priv;
110 unsigned int words, i;
111 struct ieee80211_chan_range chan_range;
112 u16 cr49;
113 struct eeprom_93cx6 eeprom = {
114 .data = priv,
115 .register_read = adm8211_eeprom_register_read,
116 .register_write = adm8211_eeprom_register_write
117 };
118
119 if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
120 /* 256 * 16-bit = 512 bytes */
121 eeprom.width = PCI_EEPROM_WIDTH_93C66;
122 words = 256;
123 } else {
124 /* 64 * 16-bit = 128 bytes */
125 eeprom.width = PCI_EEPROM_WIDTH_93C46;
126 words = 64;
127 }
128
129 priv->eeprom_len = words * 2;
130 priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
131 if (!priv->eeprom)
132 return -ENOMEM;
133
0e5ce1f3 134 eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
cc0b88cf
MW		 135
136 cr49 = le16_to_cpu(priv->eeprom->cr49);
137 priv->rf_type = (cr49 >> 3) & 0x7;
138 switch (priv->rf_type) {
139 case ADM8211_TYPE_INTERSIL:
140 case ADM8211_TYPE_RFMD:
141 case ADM8211_TYPE_MARVEL:
142 case ADM8211_TYPE_AIROHA:
143 case ADM8211_TYPE_ADMTEK:
144 break;
145
146 default:
f6ac0adf 147 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 148 priv->rf_type = ADM8211_TYPE_RFMD;
149 else
150 priv->rf_type = ADM8211_TYPE_AIROHA;
151
152 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
153 pci_name(priv->pdev), (cr49 >> 3) & 0x7);
154 }
155
156 priv->bbp_type = cr49 & 0x7;
157 switch (priv->bbp_type) {
158 case ADM8211_TYPE_INTERSIL:
159 case ADM8211_TYPE_RFMD:
160 case ADM8211_TYPE_MARVEL:
161 case ADM8211_TYPE_AIROHA:
162 case ADM8211_TYPE_ADMTEK:
163 break;
164 default:
f6ac0adf 165 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 166 priv->bbp_type = ADM8211_TYPE_RFMD;
167 else
168 priv->bbp_type = ADM8211_TYPE_ADMTEK;
169
170 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
171 pci_name(priv->pdev), cr49 >> 3);
172 }
173
174 if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
175 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
176 pci_name(priv->pdev), priv->eeprom->country_code);
177
178 chan_range = cranges[2];
179 } else
180 chan_range = cranges[priv->eeprom->country_code];
181
182 printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
183 pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
184
8318d78a 185 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
cc0b88cf 186
8318d78a
JB		 187 memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
188 priv->band.channels = priv->channels;
189 priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
190 priv->band.bitrates = adm8211_rates;
191 priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
cc0b88cf
MW		 192
193 for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
8318d78a
JB		 194 if (i < chan_range.min || i > chan_range.max)
195 priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
cc0b88cf
MW		 196
197 switch (priv->eeprom->specific_bbptype) {
198 case ADM8211_BBP_RFMD3000:
199 case ADM8211_BBP_RFMD3002:
200 case ADM8211_BBP_ADM8011:
201 priv->specific_bbptype = priv->eeprom->specific_bbptype;
202 break;
203
204 default:
f6ac0adf 205 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 206 priv->specific_bbptype = ADM8211_BBP_RFMD3000;
207 else
208 priv->specific_bbptype = ADM8211_BBP_ADM8011;
209
210 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
211 pci_name(priv->pdev), priv->eeprom->specific_bbptype);
212 }
213
214 switch (priv->eeprom->specific_rftype) {
215 case ADM8211_RFMD2948:
216 case ADM8211_RFMD2958:
217 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
218 case ADM8211_MAX2820:
219 case ADM8211_AL2210L:
220 priv->transceiver_type = priv->eeprom->specific_rftype;
221 break;
222
223 default:
f6ac0adf 224 if (priv->pdev->revision == ADM8211_REV_BA)
cc0b88cf 225 priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
f6ac0adf 226 else if (priv->pdev->revision == ADM8211_REV_CA)
cc0b88cf 227 priv->transceiver_type = ADM8211_AL2210L;
f6ac0adf 228 else if (priv->pdev->revision == ADM8211_REV_AB)
cc0b88cf
MW		 229 priv->transceiver_type = ADM8211_RFMD2948;
230
231 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
232 pci_name(priv->pdev), priv->eeprom->specific_rftype);
233
234 break;
235 }
236
237 printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
238 "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
239 priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
240
241 return 0;
242}
243
244static inline void adm8211_write_sram(struct ieee80211_hw *dev,
245 u32 addr, u32 data)
246{
247 struct adm8211_priv *priv = dev->priv;
248
249 ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
f6ac0adf 250 (priv->pdev->revision < ADM8211_REV_BA ?
cc0b88cf
MW		 251 0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
252 ADM8211_CSR_READ(WEPCTL);
253 msleep(1);
254
255 ADM8211_CSR_WRITE(WESK, data);
256 ADM8211_CSR_READ(WESK);
257 msleep(1);
258}
259
260static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
261 unsigned int addr, u8 *buf,
262 unsigned int len)
263{
264 struct adm8211_priv *priv = dev->priv;
265 u32 reg = ADM8211_CSR_READ(WEPCTL);
266 unsigned int i;
267
f6ac0adf 268 if (priv->pdev->revision < ADM8211_REV_BA) {
cc0b88cf
MW		 269 for (i = 0; i < len; i += 2) {
270 u16 val = buf[i] | (buf[i + 1] << 8);
271 adm8211_write_sram(dev, addr + i / 2, val);
272 }
273 } else {
274 for (i = 0; i < len; i += 4) {
275 u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
276 (buf[i + 2] << 16) | (buf[i + 3] << 24);
277 adm8211_write_sram(dev, addr + i / 4, val);
278 }
279 }
280
281 ADM8211_CSR_WRITE(WEPCTL, reg);
282}
283
284static void adm8211_clear_sram(struct ieee80211_hw *dev)
285{
286 struct adm8211_priv *priv = dev->priv;
287 u32 reg = ADM8211_CSR_READ(WEPCTL);
288 unsigned int addr;
289
290 for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
291 adm8211_write_sram(dev, addr, 0);
292
293 ADM8211_CSR_WRITE(WEPCTL, reg);
294}
295
296static int adm8211_get_stats(struct ieee80211_hw *dev,
297 struct ieee80211_low_level_stats *stats)
298{
299 struct adm8211_priv *priv = dev->priv;
300
301 memcpy(stats, &priv->stats, sizeof(*stats));
302
303 return 0;
304}
305
cc0b88cf
MW		 306static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
307{
308 struct adm8211_priv *priv = dev->priv;
309 unsigned int dirty_tx;
310
311 spin_lock(&priv->lock);
312
313 for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
314 unsigned int entry = dirty_tx % priv->tx_ring_size;
315 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
e039fa4a 316 struct ieee80211_tx_info *txi;
cc0b88cf
MW		 317 struct adm8211_tx_ring_info *info;
318 struct sk_buff *skb;
319
320 if (status & TDES0_CONTROL_OWN ||
321 !(status & TDES0_CONTROL_DONE))
322 break;
323
324 info = &priv->tx_buffers[entry];
325 skb = info->skb;
e039fa4a 326 txi = IEEE80211_SKB_CB(skb);
cc0b88cf
MW		 327
328 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
329
330 pci_unmap_single(priv->pdev, info->mapping,
331 info->skb->len, PCI_DMA_TODEVICE);
332
e6a9854b
JB		 333 ieee80211_tx_info_clear_status(txi);
334
d703e29a
MW		 335 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
336 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
e6a9854b
JB		 337 if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
338 !(status & TDES0_STATUS_ES))
339 txi->flags |= IEEE80211_TX_STAT_ACK;
340
e039fa4a 341 ieee80211_tx_status_irqsafe(dev, skb);
d703e29a 342
cc0b88cf
MW		 343 info->skb = NULL;
344 }
345
346 if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
347 ieee80211_wake_queue(dev, 0);
348
349 priv->dirty_tx = dirty_tx;
350 spin_unlock(&priv->lock);
351}
352
353
354static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
355{
356 struct adm8211_priv *priv = dev->priv;
357 unsigned int entry = priv->cur_rx % priv->rx_ring_size;
358 u32 status;
359 unsigned int pktlen;
360 struct sk_buff *skb, *newskb;
361 unsigned int limit = priv->rx_ring_size;
cc0b88cf
MW		 362 u8 rssi, rate;
363
364 while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
365 if (!limit--)
366 break;
367
368 status = le32_to_cpu(priv->rx_ring[entry].status);
369 rate = (status & RDES0_STATUS_RXDR) >> 12;
370 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
371 RDES1_STATUS_RSSI;
372
373 pktlen = status & RDES0_STATUS_FL;
374 if (pktlen > RX_PKT_SIZE) {
375 if (net_ratelimit())
c96c31e4
JP		 376 wiphy_debug(dev->wiphy, "frame too long (%d)\n",
377 pktlen);
cc0b88cf
MW		 378 pktlen = RX_PKT_SIZE;
379 }
380
381 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
382 skb = NULL; /* old buffer will be reused */
383 /* TODO: update RX error stats */
384 /* TODO: check RDES0_STATUS_CRC*E */
385 } else if (pktlen < RX_COPY_BREAK) {
386 skb = dev_alloc_skb(pktlen);
387 if (skb) {
388 pci_dma_sync_single_for_cpu(
389 priv->pdev,
390 priv->rx_buffers[entry].mapping,
391 pktlen, PCI_DMA_FROMDEVICE);
392 memcpy(skb_put(skb, pktlen),
393 skb_tail_pointer(priv->rx_buffers[entry].skb),
394 pktlen);
395 pci_dma_sync_single_for_device(
396 priv->pdev,
397 priv->rx_buffers[entry].mapping,
398 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
399 }
400 } else {
401 newskb = dev_alloc_skb(RX_PKT_SIZE);
402 if (newskb) {
403 skb = priv->rx_buffers[entry].skb;
404 skb_put(skb, pktlen);
405 pci_unmap_single(
406 priv->pdev,
407 priv->rx_buffers[entry].mapping,
408 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
409 priv->rx_buffers[entry].skb = newskb;
410 priv->rx_buffers[entry].mapping =
411 pci_map_single(priv->pdev,
412 skb_tail_pointer(newskb),
413 RX_PKT_SIZE,
414 PCI_DMA_FROMDEVICE);
415 } else {
416 skb = NULL;
417 /* TODO: update rx dropped stats */
418 }
419
420 priv->rx_ring[entry].buffer1 =
421 cpu_to_le32(priv->rx_buffers[entry].mapping);
422 }
423
424 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
425 RDES0_STATUS_SQL);
426 priv->rx_ring[entry].length =
427 cpu_to_le32(RX_PKT_SIZE |
428 (entry == priv->rx_ring_size - 1 ?
429 RDES1_CONTROL_RER : 0));
430
431 if (skb) {
432 struct ieee80211_rx_status rx_status = {0};
433
f6ac0adf 434 if (priv->pdev->revision < ADM8211_REV_CA)
566bfe5a 435 rx_status.signal = rssi;
cc0b88cf 436 else
566bfe5a 437 rx_status.signal = 100 - rssi;
cc0b88cf 438
8318d78a 439 rx_status.rate_idx = rate;
cc0b88cf 440
8318d78a
JB		 441 rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
442 rx_status.band = IEEE80211_BAND_2GHZ;
cc0b88cf 443
f1d58c25
JB		 444 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
445 ieee80211_rx_irqsafe(dev, skb);
cc0b88cf
MW		 446 }
447
448 entry = (++priv->cur_rx) % priv->rx_ring_size;
449 }
450
451 /* TODO: check LPC and update stats? */
452}
453
454
455static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
456{
c96c31e4
JP		 457#define ADM8211_INT(x) \
458do { \
459 if (unlikely(stsr & ADM8211_STSR_ ## x)) \
460 wiphy_debug(dev->wiphy, "%s\n", #x); \
cc0b88cf
MW		 461} while (0)
462
463 struct ieee80211_hw *dev = dev_id;
464 struct adm8211_priv *priv = dev->priv;
2e08ac7e
MW		 465 u32 stsr = ADM8211_CSR_READ(STSR);
466 ADM8211_CSR_WRITE(STSR, stsr);
467 if (stsr == 0xffffffff)
468 return IRQ_HANDLED;
469
470 if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
471 return IRQ_HANDLED;
472
473 if (stsr & ADM8211_STSR_RCI)
474 adm8211_interrupt_rci(dev);
475 if (stsr & ADM8211_STSR_TCI)
476 adm8211_interrupt_tci(dev);
477
2e08ac7e
MW		 478 ADM8211_INT(PCF);
479 ADM8211_INT(BCNTC);
480 ADM8211_INT(GPINT);
481 ADM8211_INT(ATIMTC);
482 ADM8211_INT(TSFTF);
483 ADM8211_INT(TSCZ);
484 ADM8211_INT(SQL);
485 ADM8211_INT(WEPTD);
486 ADM8211_INT(ATIME);
2e08ac7e
MW		 487 ADM8211_INT(TEIS);
488 ADM8211_INT(FBE);
489 ADM8211_INT(REIS);
490 ADM8211_INT(GPTT);
491 ADM8211_INT(RPS);
492 ADM8211_INT(RDU);
493 ADM8211_INT(TUF);
2e08ac7e
MW		 494 ADM8211_INT(TPS);
495
496 return IRQ_HANDLED;
cc0b88cf
MW		 497
498#undef ADM8211_INT
499}
500
501#define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
502static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev, \
503 u16 addr, u32 value) { \
504 struct adm8211_priv *priv = dev->priv; \
505 unsigned int i; \
506 u32 reg, bitbuf; \
507 \
508 value &= v_mask; \
509 addr &= a_mask; \
510 bitbuf = (value << v_shift) | (addr << a_shift); \
511 \
512 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1); \
513 ADM8211_CSR_READ(SYNRF); \
514 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0); \
515 ADM8211_CSR_READ(SYNRF); \
516 \
517 if (prewrite) { \
518 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0); \
519 ADM8211_CSR_READ(SYNRF); \
520 } \
521 \
522 for (i = 0; i <= bits; i++) { \
523 if (bitbuf & (1 << (bits - i))) \
524 reg = ADM8211_SYNRF_WRITE_SYNDATA_1; \
525 else \
526 reg = ADM8211_SYNRF_WRITE_SYNDATA_0; \
527 \
528 ADM8211_CSR_WRITE(SYNRF, reg); \
529 ADM8211_CSR_READ(SYNRF); \
530 \
531 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
532 ADM8211_CSR_READ(SYNRF); \
533 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
534 ADM8211_CSR_READ(SYNRF); \
535 } \
536 \
537 if (postwrite == 1) { \
538 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0); \
539 ADM8211_CSR_READ(SYNRF); \
540 } \
541 if (postwrite == 2) { \
542 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1); \
543 ADM8211_CSR_READ(SYNRF); \
544 } \
545 \
546 ADM8211_CSR_WRITE(SYNRF, 0); \
547 ADM8211_CSR_READ(SYNRF); \
548}
549
550WRITE_SYN(max2820, 0x00FFF, 0, 0x0F, 12, 15, 1, 1)
551WRITE_SYN(al2210l, 0xFFFFF, 4, 0x0F, 0, 23, 1, 1)
552WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
553WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F, 0, 21, 0, 2)
554
555#undef WRITE_SYN
556
557static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
558{
559 struct adm8211_priv *priv = dev->priv;
560 unsigned int timeout;
561 u32 reg;
562
563 timeout = 10;
564 while (timeout > 0) {
565 reg = ADM8211_CSR_READ(BBPCTL);
566 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
567 break;
568 timeout--;
569 msleep(2);
570 }
571
572 if (timeout == 0) {
c96c31e4
JP		 573 wiphy_debug(dev->wiphy,
574 "adm8211_write_bbp(%d,%d) failed prewrite (reg=0x%08x)\n",
575 addr, data, reg);
cc0b88cf
MW		 576 return -ETIMEDOUT;
577 }
578
579 switch (priv->bbp_type) {
580 case ADM8211_TYPE_INTERSIL:
581 reg = ADM8211_BBPCTL_MMISEL; /* three wire interface */
582 break;
583 case ADM8211_TYPE_RFMD:
584 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
585 (0x01 << 18);
586 break;
587 case ADM8211_TYPE_ADMTEK:
588 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
589 (0x05 << 18);
590 break;
591 }
592 reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
593
594 ADM8211_CSR_WRITE(BBPCTL, reg);
595
596 timeout = 10;
597 while (timeout > 0) {
598 reg = ADM8211_CSR_READ(BBPCTL);
599 if (!(reg & ADM8211_BBPCTL_WR))
600 break;
601 timeout--;
602 msleep(2);
603 }
604
605 if (timeout == 0) {
606 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
607 ~ADM8211_BBPCTL_WR);
c96c31e4
JP		 608 wiphy_debug(dev->wiphy,
609 "adm8211_write_bbp(%d,%d) failed postwrite (reg=0x%08x)\n",
610 addr, data, reg);
cc0b88cf
MW		 611 return -ETIMEDOUT;
612 }
613
614 return 0;
615}
616
617static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
618{
619 static const u32 adm8211_rfmd2958_reg5[] =
620 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
621 0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
622 static const u32 adm8211_rfmd2958_reg6[] =
623 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
624 0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
625
626 struct adm8211_priv *priv = dev->priv;
627 u8 ant_power = priv->ant_power > 0x3F ?
628 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
629 u8 tx_power = priv->tx_power > 0x3F ?
630 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
631 u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
632 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
633 u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
634 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
635 u32 reg;
636
637 ADM8211_IDLE();
638
639 /* Program synthesizer to new channel */
640 switch (priv->transceiver_type) {
641 case ADM8211_RFMD2958:
642 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
643 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
644 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
645
646 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
647 adm8211_rfmd2958_reg5[chan - 1]);
648 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
649 adm8211_rfmd2958_reg6[chan - 1]);
650 break;
651
652 case ADM8211_RFMD2948:
653 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
654 SI4126_MAIN_XINDIV2);
655 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
656 SI4126_POWERDOWN_PDIB |
657 SI4126_POWERDOWN_PDRB);
658 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
659 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
660 (chan == 14 ?
661 2110 : (2033 + (chan * 5))));
662 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
663 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
664 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
665 break;
666
667 case ADM8211_MAX2820:
668 adm8211_rf_write_syn_max2820(dev, 0x3,
669 (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
670 break;
671
672 case ADM8211_AL2210L:
673 adm8211_rf_write_syn_al2210l(dev, 0x0,
674 (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
675 break;
676
677 default:
c96c31e4
JP		 678 wiphy_debug(dev->wiphy, "unsupported transceiver type %d\n",
679 priv->transceiver_type);
cc0b88cf
MW		 680 break;
681 }
682
683 /* write BBP regs */
684 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
685
686 /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
687 /* TODO: remove if SMC 2635W doesn't need this */
688 if (priv->transceiver_type == ADM8211_RFMD2948) {
689 reg = ADM8211_CSR_READ(GPIO);
690 reg &= 0xfffc0000;
691 reg |= ADM8211_CSR_GPIO_EN0;
692 if (chan != 14)
693 reg |= ADM8211_CSR_GPIO_O0;
694 ADM8211_CSR_WRITE(GPIO, reg);
695 }
696
697 if (priv->transceiver_type == ADM8211_RFMD2958) {
698 /* set PCNT2 */
699 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
700 /* set PCNT1 P_DESIRED/MID_BIAS */
701 reg = le16_to_cpu(priv->eeprom->cr49);
702 reg >>= 13;
703 reg <<= 15;
704 reg |= ant_power << 9;
705 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
706 /* set TXRX TX_GAIN */
707 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
f6ac0adf 708 (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
cc0b88cf
MW		 709 } else {
710 reg = ADM8211_CSR_READ(PLCPHD);
711 reg &= 0xff00ffff;
712 reg |= tx_power << 18;
713 ADM8211_CSR_WRITE(PLCPHD, reg);
714 }
715
716 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
717 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
718 ADM8211_CSR_READ(SYNRF);
719 msleep(30);
720
721 /* RF3000 BBP */
722 if (priv->transceiver_type != ADM8211_RFMD2958)
723 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
724 tx_power<<2);
725 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
726 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
f6ac0adf 727 adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
cc0b88cf
MW		 728 priv->eeprom->cr28 : 0);
729 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
730
731 ADM8211_CSR_WRITE(SYNRF, 0);
732
733 /* Nothing to do for ADMtek BBP */
734 } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
5db55844 735 wiphy_debug(dev->wiphy, "unsupported BBP type %d\n",
c96c31e4 736 priv->bbp_type);
cc0b88cf
MW		 737
738 ADM8211_RESTORE();
739
740 /* update current channel for adhoc (and maybe AP mode) */
741 reg = ADM8211_CSR_READ(CAP0);
742 reg &= ~0xF;
743 reg |= chan;
744 ADM8211_CSR_WRITE(CAP0, reg);
745
746 return 0;
747}
748
749static void adm8211_update_mode(struct ieee80211_hw *dev)
750{
751 struct adm8211_priv *priv = dev->priv;
752
753 ADM8211_IDLE();
754
755 priv->soft_rx_crc = 0;
756 switch (priv->mode) {
05c914fe 757 case NL80211_IFTYPE_STATION:
cc0b88cf
MW		 758 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
759 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
760 break;
05c914fe 761 case NL80211_IFTYPE_ADHOC:
cc0b88cf
MW		 762 priv->nar &= ~ADM8211_NAR_PR;
763 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
764
765 /* don't trust the error bits on rev 0x20 and up in adhoc */
f6ac0adf 766 if (priv->pdev->revision >= ADM8211_REV_BA)
cc0b88cf
MW		 767 priv->soft_rx_crc = 1;
768 break;
05c914fe 769 case NL80211_IFTYPE_MONITOR:
cc0b88cf
MW		 770 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
771 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
772 break;
773 }
774
775 ADM8211_RESTORE();
776}
777
778static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
779{
780 struct adm8211_priv *priv = dev->priv;
781
782 switch (priv->transceiver_type) {
783 case ADM8211_RFMD2958:
784 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
785 /* comments taken from ADMtek vendor driver */
786
787 /* Reset RF2958 after power on */
788 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
789 /* Initialize RF VCO Core Bias to maximum */
790 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
791 /* Initialize IF PLL */
792 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
793 /* Initialize IF PLL Coarse Tuning */
794 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
795 /* Initialize RF PLL */
796 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
797 /* Initialize RF PLL Coarse Tuning */
798 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
799 /* Initialize TX gain and filter BW (R9) */
800 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
801 (priv->transceiver_type == ADM8211_RFMD2958 ?
802 0x10050 : 0x00050));
803 /* Initialize CAL register */
804 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
805 break;
806
807 case ADM8211_MAX2820:
808 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
809 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
810 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
811 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
812 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
813 break;
814
815 case ADM8211_AL2210L:
816 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
817 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
818 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
819 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
820 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
821 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
822 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
823 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
824 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
825 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
826 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
827 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
828 break;
829
830 case ADM8211_RFMD2948:
831 default:
832 break;
833 }
834}
835
836static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
837{
838 struct adm8211_priv *priv = dev->priv;
839 u32 reg;
840
841 /* write addresses */
842 if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
843 ADM8211_CSR_WRITE(MMIWA, 0x100E0C0A);
844 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
845 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
846 } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
847 priv->bbp_type == ADM8211_TYPE_ADMTEK) {
848 /* check specific BBP type */
849 switch (priv->specific_bbptype) {
850 case ADM8211_BBP_RFMD3000:
851 case ADM8211_BBP_RFMD3002:
852 ADM8211_CSR_WRITE(MMIWA, 0x00009101);
853 ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
854 break;
855
856 case ADM8211_BBP_ADM8011:
857 ADM8211_CSR_WRITE(MMIWA, 0x00008903);
858 ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
859
860 reg = ADM8211_CSR_READ(BBPCTL);
861 reg &= ~ADM8211_BBPCTL_TYPE;
862 reg |= 0x5 << 18;
863 ADM8211_CSR_WRITE(BBPCTL, reg);
864 break;
865 }
866
f6ac0adf 867 switch (priv->pdev->revision) {
cc0b88cf
MW		 868 case ADM8211_REV_CA:
869 if (priv->transceiver_type == ADM8211_RFMD2958 ||
870 priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
871 priv->transceiver_type == ADM8211_RFMD2948)
872 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
873 else if (priv->transceiver_type == ADM8211_MAX2820 ||
874 priv->transceiver_type == ADM8211_AL2210L)
875 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
876 break;
877
878 case ADM8211_REV_BA:
879 reg = ADM8211_CSR_READ(MMIRD1);
880 reg &= 0x0000FFFF;
881 reg |= 0x7e100000;
882 ADM8211_CSR_WRITE(MMIRD1, reg);
883 break;
884
885 case ADM8211_REV_AB:
886 case ADM8211_REV_AF:
887 default:
888 ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
889 break;
890 }
891
892 /* For RFMD */
893 ADM8211_CSR_WRITE(MACTEST, 0x800);
894 }
895
896 adm8211_hw_init_syn(dev);
897
898 /* Set RF Power control IF pin to PE1+PHYRST# */
899 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
900 ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
901 ADM8211_CSR_READ(SYNRF);
902 msleep(20);
903
904 /* write BBP regs */
905 if (priv->bbp_type == ADM8211_TYPE_RFMD) {
906 /* RF3000 BBP */
907 /* another set:
908 * 11: c8
909 * 14: 14
910 * 15: 50 (chan 1..13; chan 14: d0)
911 * 1c: 00
912 * 1d: 84
913 */
914 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
915 /* antenna selection: diversity */
916 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
917 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
918 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
919 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
920
921 if (priv->eeprom->major_version < 2) {
922 adm8211_write_bbp(dev, 0x1c, 0x00);
923 adm8211_write_bbp(dev, 0x1d, 0x80);
924 } else {
f6ac0adf 925 if (priv->pdev->revision == ADM8211_REV_BA)
cc0b88cf
MW		 926 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
927 else
928 adm8211_write_bbp(dev, 0x1c, 0x00);
929
930 adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
931 }
932 } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
933 /* reset baseband */
934 adm8211_write_bbp(dev, 0x00, 0xFF);
935 /* antenna selection: diversity */
936 adm8211_write_bbp(dev, 0x07, 0x0A);
937
938 /* TODO: find documentation for this */
939 switch (priv->transceiver_type) {
940 case ADM8211_RFMD2958:
941 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
942 adm8211_write_bbp(dev, 0x00, 0x00);
943 adm8211_write_bbp(dev, 0x01, 0x00);
944 adm8211_write_bbp(dev, 0x02, 0x00);
945 adm8211_write_bbp(dev, 0x03, 0x00);
946 adm8211_write_bbp(dev, 0x06, 0x0f);
947 adm8211_write_bbp(dev, 0x09, 0x00);
948 adm8211_write_bbp(dev, 0x0a, 0x00);
949 adm8211_write_bbp(dev, 0x0b, 0x00);
950 adm8211_write_bbp(dev, 0x0c, 0x00);
951 adm8211_write_bbp(dev, 0x0f, 0xAA);
952 adm8211_write_bbp(dev, 0x10, 0x8c);
953 adm8211_write_bbp(dev, 0x11, 0x43);
954 adm8211_write_bbp(dev, 0x18, 0x40);
955 adm8211_write_bbp(dev, 0x20, 0x23);
956 adm8211_write_bbp(dev, 0x21, 0x02);
957 adm8211_write_bbp(dev, 0x22, 0x28);
958 adm8211_write_bbp(dev, 0x23, 0x30);
959 adm8211_write_bbp(dev, 0x24, 0x2d);
960 adm8211_write_bbp(dev, 0x28, 0x35);
961 adm8211_write_bbp(dev, 0x2a, 0x8c);
962 adm8211_write_bbp(dev, 0x2b, 0x81);
963 adm8211_write_bbp(dev, 0x2c, 0x44);
964 adm8211_write_bbp(dev, 0x2d, 0x0A);
965 adm8211_write_bbp(dev, 0x29, 0x40);
966 adm8211_write_bbp(dev, 0x60, 0x08);
967 adm8211_write_bbp(dev, 0x64, 0x01);
968 break;
969
970 case ADM8211_MAX2820:
971 adm8211_write_bbp(dev, 0x00, 0x00);
972 adm8211_write_bbp(dev, 0x01, 0x00);
973 adm8211_write_bbp(dev, 0x02, 0x00);
974 adm8211_write_bbp(dev, 0x03, 0x00);
975 adm8211_write_bbp(dev, 0x06, 0x0f);
976 adm8211_write_bbp(dev, 0x09, 0x05);
977 adm8211_write_bbp(dev, 0x0a, 0x02);
978 adm8211_write_bbp(dev, 0x0b, 0x00);
979 adm8211_write_bbp(dev, 0x0c, 0x0f);
980 adm8211_write_bbp(dev, 0x0f, 0x55);
981 adm8211_write_bbp(dev, 0x10, 0x8d);
982 adm8211_write_bbp(dev, 0x11, 0x43);
983 adm8211_write_bbp(dev, 0x18, 0x4a);
984 adm8211_write_bbp(dev, 0x20, 0x20);
985 adm8211_write_bbp(dev, 0x21, 0x02);
986 adm8211_write_bbp(dev, 0x22, 0x23);
987 adm8211_write_bbp(dev, 0x23, 0x30);
988 adm8211_write_bbp(dev, 0x24, 0x2d);
989 adm8211_write_bbp(dev, 0x2a, 0x8c);
990 adm8211_write_bbp(dev, 0x2b, 0x81);
991 adm8211_write_bbp(dev, 0x2c, 0x44);
992 adm8211_write_bbp(dev, 0x29, 0x4a);
993 adm8211_write_bbp(dev, 0x60, 0x2b);
994 adm8211_write_bbp(dev, 0x64, 0x01);
995 break;
996
997 case ADM8211_AL2210L:
998 adm8211_write_bbp(dev, 0x00, 0x00);
999 adm8211_write_bbp(dev, 0x01, 0x00);
1000 adm8211_write_bbp(dev, 0x02, 0x00);
1001 adm8211_write_bbp(dev, 0x03, 0x00);
1002 adm8211_write_bbp(dev, 0x06, 0x0f);
1003 adm8211_write_bbp(dev, 0x07, 0x05);
1004 adm8211_write_bbp(dev, 0x08, 0x03);
1005 adm8211_write_bbp(dev, 0x09, 0x00);
1006 adm8211_write_bbp(dev, 0x0a, 0x00);
1007 adm8211_write_bbp(dev, 0x0b, 0x00);
1008 adm8211_write_bbp(dev, 0x0c, 0x10);
1009 adm8211_write_bbp(dev, 0x0f, 0x55);
1010 adm8211_write_bbp(dev, 0x10, 0x8d);
1011 adm8211_write_bbp(dev, 0x11, 0x43);
1012 adm8211_write_bbp(dev, 0x18, 0x4a);
1013 adm8211_write_bbp(dev, 0x20, 0x20);
1014 adm8211_write_bbp(dev, 0x21, 0x02);
1015 adm8211_write_bbp(dev, 0x22, 0x23);
1016 adm8211_write_bbp(dev, 0x23, 0x30);
1017 adm8211_write_bbp(dev, 0x24, 0x2d);
1018 adm8211_write_bbp(dev, 0x2a, 0xaa);
1019 adm8211_write_bbp(dev, 0x2b, 0x81);
1020 adm8211_write_bbp(dev, 0x2c, 0x44);
1021 adm8211_write_bbp(dev, 0x29, 0xfa);
1022 adm8211_write_bbp(dev, 0x60, 0x2d);
1023 adm8211_write_bbp(dev, 0x64, 0x01);
1024 break;
1025
1026 case ADM8211_RFMD2948:
1027 break;
1028
1029 default:
c96c31e4
JP		 1030 wiphy_debug(dev->wiphy, "unsupported transceiver %d\n",
1031 priv->transceiver_type);
cc0b88cf
MW		 1032 break;
1033 }
1034 } else
5db55844 1035 wiphy_debug(dev->wiphy, "unsupported BBP %d\n", priv->bbp_type);
cc0b88cf
MW		 1036
1037 ADM8211_CSR_WRITE(SYNRF, 0);
1038
1039 /* Set RF CAL control source to MAC control */
1040 reg = ADM8211_CSR_READ(SYNCTL);
1041 reg |= ADM8211_SYNCTL_SELCAL;
1042 ADM8211_CSR_WRITE(SYNCTL, reg);
1043
1044 return 0;
1045}
1046
1047/* configures hw beacons/probe responses */
1048static int adm8211_set_rate(struct ieee80211_hw *dev)
1049{
1050 struct adm8211_priv *priv = dev->priv;
1051 u32 reg;
1052 int i = 0;
1053 u8 rate_buf[12] = {0};
1054
1055 /* write supported rates */
f6ac0adf 1056 if (priv->pdev->revision != ADM8211_REV_BA) {
cc0b88cf
MW		 1057 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1058 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
8318d78a 1059 rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
cc0b88cf
MW		 1060 } else {
1061 /* workaround for rev BA specific bug */
1062 rate_buf[0] = 0x04;
1063 rate_buf[1] = 0x82;
1064 rate_buf[2] = 0x04;
1065 rate_buf[3] = 0x0b;
1066 rate_buf[4] = 0x16;
1067 }
1068
1069 adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1070 ARRAY_SIZE(adm8211_rates) + 1);
1071
1072 reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1073 reg |= 1 << 15; /* short preamble */
1074 reg |= 110 << 24;
1075 ADM8211_CSR_WRITE(PLCPHD, reg);
1076
1077 /* MTMLT = 512 TU (max TX MSDU lifetime)
1078 * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1079 * SRTYLIM = 224 (short retry limit, TX header value is default) */
1080 ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1081
1082 return 0;
1083}
1084
1085static void adm8211_hw_init(struct ieee80211_hw *dev)
1086{
1087 struct adm8211_priv *priv = dev->priv;
1088 u32 reg;
1089 u8 cline;
1090
e63e3fa7 1091 reg = ADM8211_CSR_READ(PAR);
cc0b88cf
MW		 1092 reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1093 reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1094
1095 if (!pci_set_mwi(priv->pdev)) {
1096 reg |= 0x1 << 24;
1097 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1098
1099 switch (cline) {
1100 case 0x8: reg |= (0x1 << 14);
1101 break;
1102 case 0x16: reg |= (0x2 << 14);
1103 break;
1104 case 0x32: reg |= (0x3 << 14);
1105 break;
1106 default: reg |= (0x0 << 14);
1107 break;
1108 }
1109 }
1110
1111 ADM8211_CSR_WRITE(PAR, reg);
1112
1113 reg = ADM8211_CSR_READ(CSR_TEST1);
1114 reg &= ~(0xF << 28);
1115 reg |= (1 << 28) | (1 << 31);
1116 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1117
1118 /* lose link after 4 lost beacons */
1119 reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1120 ADM8211_CSR_WRITE(WCSR, reg);
1121
1122 /* Disable APM, enable receive FIFO threshold, and set drain receive
1123 * threshold to store-and-forward */
1124 reg = ADM8211_CSR_READ(CMDR);
1125 reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1126 reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1127 ADM8211_CSR_WRITE(CMDR, reg);
1128
1129 adm8211_set_rate(dev);
1130
1131 /* 4-bit values:
1132 * PWR1UP = 8 * 2 ms
1133 * PWR0PAPE = 8 us or 5 us
1134 * PWR1PAPE = 1 us or 3 us
1135 * PWR0TRSW = 5 us
1136 * PWR1TRSW = 12 us
1137 * PWR0PE2 = 13 us
1138 * PWR1PE2 = 1 us
1139 * PWR0TXPE = 8 or 6 */
f6ac0adf 1140 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 1141 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1142 else
1143 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1144
1145 /* Enable store and forward for transmit */
1146 priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1147 ADM8211_CSR_WRITE(NAR, priv->nar);
1148
1149 /* Reset RF */
1150 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1151 ADM8211_CSR_READ(SYNRF);
1152 msleep(10);
1153 ADM8211_CSR_WRITE(SYNRF, 0);
1154 ADM8211_CSR_READ(SYNRF);
1155 msleep(5);
1156
1157 /* Set CFP Max Duration to 0x10 TU */
1158 reg = ADM8211_CSR_READ(CFPP);
1159 reg &= ~(0xffff << 8);
1160 reg |= 0x0010 << 8;
1161 ADM8211_CSR_WRITE(CFPP, reg);
1162
1163 /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1164 * TUCNT = 0x3ff - Tu counter 1024 us */
1165 ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1166
1167 /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1168 * DIFS=50 us, EIFS=100 us */
f6ac0adf 1169 if (priv->pdev->revision < ADM8211_REV_CA)
cc0b88cf
MW		 1170 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1171 (50 << 9) | 100);
1172 else
1173 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1174 (50 << 9) | 100);
1175
1176 /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1177 * RMRD = 2346 * 8 + 1 us (max RX duration) */
1178 ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1179
1180 /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1181 ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1182
1183 /* Initialize BBP (and SYN) */
1184 adm8211_hw_init_bbp(dev);
1185
1186 /* make sure interrupts are off */
1187 ADM8211_CSR_WRITE(IER, 0);
1188
1189 /* ACK interrupts */
1190 ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1191
1192 /* Setup WEP (turns it off for now) */
1193 reg = ADM8211_CSR_READ(MACTEST);
1194 reg &= ~(7 << 20);
1195 ADM8211_CSR_WRITE(MACTEST, reg);
1196
1197 reg = ADM8211_CSR_READ(WEPCTL);
1198 reg &= ~ADM8211_WEPCTL_WEPENABLE;
1199 reg |= ADM8211_WEPCTL_WEPRXBYP;
1200 ADM8211_CSR_WRITE(WEPCTL, reg);
1201
1202 /* Clear the missed-packet counter. */
1203 ADM8211_CSR_READ(LPC);
cc0b88cf
MW		 1204}
1205
1206static int adm8211_hw_reset(struct ieee80211_hw *dev)
1207{
1208 struct adm8211_priv *priv = dev->priv;
1209 u32 reg, tmp;
1210 int timeout = 100;
1211
1212 /* Power-on issue */
1213 /* TODO: check if this is necessary */
1214 ADM8211_CSR_WRITE(FRCTL, 0);
1215
1216 /* Reset the chip */
1217 tmp = ADM8211_CSR_READ(PAR);
1218 ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1219
1220 while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1221 msleep(50);
1222
1223 if (timeout <= 0)
1224 return -ETIMEDOUT;
1225
1226 ADM8211_CSR_WRITE(PAR, tmp);
1227
f6ac0adf 1228 if (priv->pdev->revision == ADM8211_REV_BA &&
cc0b88cf
MW		 1229 (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1230 priv->transceiver_type == ADM8211_RFMD2958)) {
1231 reg = ADM8211_CSR_READ(CSR_TEST1);
1232 reg |= (1 << 4) | (1 << 5);
1233 ADM8211_CSR_WRITE(CSR_TEST1, reg);
f6ac0adf 1234 } else if (priv->pdev->revision == ADM8211_REV_CA) {
cc0b88cf
MW		 1235 reg = ADM8211_CSR_READ(CSR_TEST1);
1236 reg &= ~((1 << 4) | (1 << 5));
1237 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1238 }
1239
1240 ADM8211_CSR_WRITE(FRCTL, 0);
1241
1242 reg = ADM8211_CSR_READ(CSR_TEST0);
1243 reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1244 ADM8211_CSR_WRITE(CSR_TEST0, reg);
1245
1246 adm8211_clear_sram(dev);
1247
1248 return 0;
1249}
1250
1251static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1252{
1253 struct adm8211_priv *priv = dev->priv;
1254 u32 tsftl;
1255 u64 tsft;
1256
1257 tsftl = ADM8211_CSR_READ(TSFTL);
1258 tsft = ADM8211_CSR_READ(TSFTH);
1259 tsft <<= 32;
1260 tsft |= tsftl;
1261
1262 return tsft;
1263}
1264
1265static void adm8211_set_interval(struct ieee80211_hw *dev,
1266 unsigned short bi, unsigned short li)
1267{
1268 struct adm8211_priv *priv = dev->priv;
1269 u32 reg;
1270
1271 /* BP (beacon interval) = data->beacon_interval
1272 * LI (listen interval) = data->listen_interval (in beacon intervals) */
1273 reg = (bi << 16) | li;
1274 ADM8211_CSR_WRITE(BPLI, reg);
1275}
1276
4150c572 1277static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
cc0b88cf
MW		 1278{
1279 struct adm8211_priv *priv = dev->priv;
1280 u32 reg;
1281
fb9bc28f 1282 ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
cc0b88cf
MW		 1283 reg = ADM8211_CSR_READ(ABDA1);
1284 reg &= 0x0000ffff;
1285 reg |= (bssid[4] << 16) | (bssid[5] << 24);
1286 ADM8211_CSR_WRITE(ABDA1, reg);
1287}
1288
e8975581 1289static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
cc0b88cf
MW		 1290{
1291 struct adm8211_priv *priv = dev->priv;
e8975581 1292 struct ieee80211_conf *conf = &dev->conf;
8318d78a 1293 int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
cc0b88cf 1294
8318d78a
JB		 1295 if (channel != priv->channel) {
1296 priv->channel = channel;
cc0b88cf
MW		 1297 adm8211_rf_set_channel(dev, priv->channel);
1298 }
1299
1300 return 0;
1301}
1302
2d0ddec5
JB		 1303static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1304 struct ieee80211_vif *vif,
1305 struct ieee80211_bss_conf *conf,
1306 u32 changes)
cc0b88cf
MW		 1307{
1308 struct adm8211_priv *priv = dev->priv;
1309
2d0ddec5
JB		 1310 if (!(changes & BSS_CHANGED_BSSID))
1311 return;
1312
cc0b88cf
MW		 1313 if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1314 adm8211_set_bssid(dev, conf->bssid);
1315 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1316 }
cc0b88cf
MW		 1317}
1318
3ac64bee 1319static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 1320 struct netdev_hw_addr_list *mc_list)
3ac64bee 1321{
22bedad3 1322 unsigned int bit_nr;
3ac64bee 1323 u32 mc_filter[2];
22bedad3 1324 struct netdev_hw_addr *ha;
3ac64bee
JB		 1325
1326 mc_filter[1] = mc_filter[0] = 0;
1327
22bedad3
JP		 1328 netdev_hw_addr_list_for_each(ha, mc_list) {
1329 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
3ac64bee
JB		 1330
1331 bit_nr &= 0x3F;
1332 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3ac64bee
JB		 1333 }
1334
1335 return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1336}
1337
4150c572
JB		 1338static void adm8211_configure_filter(struct ieee80211_hw *dev,
1339 unsigned int changed_flags,
1340 unsigned int *total_flags,
3ac64bee 1341 u64 multicast)
4150c572
JB		 1342{
1343 static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1344 struct adm8211_priv *priv = dev->priv;
3ac64bee 1345 unsigned int new_flags;
4150c572 1346 u32 mc_filter[2];
3ac64bee
JB		 1347
1348 mc_filter[0] = multicast;
1349 mc_filter[1] = multicast >> 32;
4150c572
JB		 1350
1351 new_flags = 0;
1352
1353 if (*total_flags & FIF_PROMISC_IN_BSS) {
1354 new_flags |= FIF_PROMISC_IN_BSS;
1355 priv->nar |= ADM8211_NAR_PR;
1356 priv->nar &= ~ADM8211_NAR_MM;
1357 mc_filter[1] = mc_filter[0] = ~0;
3ac64bee 1358 } else if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
4150c572
JB		 1359 new_flags |= FIF_ALLMULTI;
1360 priv->nar &= ~ADM8211_NAR_PR;
1361 priv->nar |= ADM8211_NAR_MM;
1362 mc_filter[1] = mc_filter[0] = ~0;
1363 } else {
1364 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
4150c572
JB		 1365 }
1366
1367 ADM8211_IDLE_RX();
1368
1369 ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1370 ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1371 ADM8211_CSR_READ(NAR);
1372
1373 if (priv->nar & ADM8211_NAR_PR)
1374 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1375 else
1376 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1377
1378 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1379 adm8211_set_bssid(dev, bcast);
1380 else
1381 adm8211_set_bssid(dev, priv->bssid);
1382
1383 ADM8211_RESTORE();
1384
1385 *total_flags = new_flags;
1386}
1387
cc0b88cf 1388static int adm8211_add_interface(struct ieee80211_hw *dev,
1ed32e4f 1389 struct ieee80211_vif *vif)
cc0b88cf
MW		 1390{
1391 struct adm8211_priv *priv = dev->priv;
05c914fe 1392 if (priv->mode != NL80211_IFTYPE_MONITOR)
4150c572 1393 return -EOPNOTSUPP;
cc0b88cf 1394
1ed32e4f 1395 switch (vif->type) {
05c914fe 1396 case NL80211_IFTYPE_STATION:
1ed32e4f 1397 priv->mode = vif->type;
cc0b88cf
MW		 1398 break;
1399 default:
1400 return -EOPNOTSUPP;
1401 }
1402
4150c572
JB		 1403 ADM8211_IDLE();
1404
1ed32e4f
JB		 1405 ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1406 ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
4150c572
JB		 1407
1408 adm8211_update_mode(dev);
1409
1410 ADM8211_RESTORE();
cc0b88cf
MW		 1411
1412 return 0;
1413}
1414
1415static void adm8211_remove_interface(struct ieee80211_hw *dev,
1ed32e4f 1416 struct ieee80211_vif *vif)
cc0b88cf
MW		 1417{
1418 struct adm8211_priv *priv = dev->priv;
05c914fe 1419 priv->mode = NL80211_IFTYPE_MONITOR;
cc0b88cf
MW		 1420}
1421
1422static int adm8211_init_rings(struct ieee80211_hw *dev)
1423{
1424 struct adm8211_priv *priv = dev->priv;
1425 struct adm8211_desc *desc = NULL;
1426 struct adm8211_rx_ring_info *rx_info;
1427 struct adm8211_tx_ring_info *tx_info;
1428 unsigned int i;
1429
1430 for (i = 0; i < priv->rx_ring_size; i++) {
1431 desc = &priv->rx_ring[i];
1432 desc->status = 0;
1433 desc->length = cpu_to_le32(RX_PKT_SIZE);
1434 priv->rx_buffers[i].skb = NULL;
1435 }
1436 /* Mark the end of RX ring; hw returns to base address after this
1437 * descriptor */
1438 desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1439
1440 for (i = 0; i < priv->rx_ring_size; i++) {
1441 desc = &priv->rx_ring[i];
1442 rx_info = &priv->rx_buffers[i];
1443
1444 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1445 if (rx_info->skb == NULL)
1446 break;
1447 rx_info->mapping = pci_map_single(priv->pdev,
1448 skb_tail_pointer(rx_info->skb),
1449 RX_PKT_SIZE,
1450 PCI_DMA_FROMDEVICE);
1451 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1452 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1453 }
1454
1455 /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1456 for (i = 0; i < priv->tx_ring_size; i++) {
1457 desc = &priv->tx_ring[i];
1458 tx_info = &priv->tx_buffers[i];
1459
1460 tx_info->skb = NULL;
1461 tx_info->mapping = 0;
1462 desc->status = 0;
1463 }
1464 desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1465
1466 priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1467 ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1468 ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1469
1470 return 0;
1471}
1472
1473static void adm8211_free_rings(struct ieee80211_hw *dev)
1474{
1475 struct adm8211_priv *priv = dev->priv;
1476 unsigned int i;
1477
1478 for (i = 0; i < priv->rx_ring_size; i++) {
1479 if (!priv->rx_buffers[i].skb)
1480 continue;
1481
1482 pci_unmap_single(
1483 priv->pdev,
1484 priv->rx_buffers[i].mapping,
1485 RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1486
1487 dev_kfree_skb(priv->rx_buffers[i].skb);
1488 }
1489
1490 for (i = 0; i < priv->tx_ring_size; i++) {
1491 if (!priv->tx_buffers[i].skb)
1492 continue;
1493
1494 pci_unmap_single(priv->pdev,
1495 priv->tx_buffers[i].mapping,
1496 priv->tx_buffers[i].skb->len,
1497 PCI_DMA_TODEVICE);
1498
1499 dev_kfree_skb(priv->tx_buffers[i].skb);
1500 }
1501}
1502
4150c572 1503static int adm8211_start(struct ieee80211_hw *dev)
cc0b88cf
MW		 1504{
1505 struct adm8211_priv *priv = dev->priv;
1506 int retval;
1507
1508 /* Power up MAC and RF chips */
1509 retval = adm8211_hw_reset(dev);
1510 if (retval) {
c96c31e4 1511 wiphy_err(dev->wiphy, "hardware reset failed\n");
cc0b88cf
MW		 1512 goto fail;
1513 }
1514
1515 retval = adm8211_init_rings(dev);
1516 if (retval) {
c96c31e4 1517 wiphy_err(dev->wiphy, "failed to initialize rings\n");
cc0b88cf
MW		 1518 goto fail;
1519 }
1520
1521 /* Init hardware */
1522 adm8211_hw_init(dev);
1523 adm8211_rf_set_channel(dev, priv->channel);
1524
fe4eb548 1525 retval = request_irq(priv->pdev->irq, adm8211_interrupt,
cc0b88cf
MW		 1526 IRQF_SHARED, "adm8211", dev);
1527 if (retval) {
5db55844 1528 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
cc0b88cf
MW		 1529 goto fail;
1530 }
1531
1532 ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1533 ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1534 ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
05c914fe 1535 priv->mode = NL80211_IFTYPE_MONITOR;
cc0b88cf
MW		 1536 adm8211_update_mode(dev);
1537 ADM8211_CSR_WRITE(RDR, 0);
1538
1539 adm8211_set_interval(dev, 100, 10);
1540 return 0;
1541
1542fail:
1543 return retval;
1544}
1545
4150c572 1546static void adm8211_stop(struct ieee80211_hw *dev)
cc0b88cf
MW		 1547{
1548 struct adm8211_priv *priv = dev->priv;
1549
05c914fe 1550 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
cc0b88cf
MW		 1551 priv->nar = 0;
1552 ADM8211_CSR_WRITE(NAR, 0);
1553 ADM8211_CSR_WRITE(IER, 0);
1554 ADM8211_CSR_READ(NAR);
1555
1556 free_irq(priv->pdev->irq, dev);
1557
1558 adm8211_free_rings(dev);
cc0b88cf
MW		 1559}
1560
1561static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1562 int plcp_signal, int short_preamble)
1563{
1564 /* Alternative calculation from NetBSD: */
1565
1566/* IEEE 802.11b durations for DSSS PHY in microseconds */
1567#define IEEE80211_DUR_DS_LONG_PREAMBLE 144
1568#define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1569#define IEEE80211_DUR_DS_FAST_PLCPHDR 24
1570#define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
1571#define IEEE80211_DUR_DS_SLOW_ACK 112
1572#define IEEE80211_DUR_DS_FAST_ACK 56
1573#define IEEE80211_DUR_DS_SLOW_CTS 112
1574#define IEEE80211_DUR_DS_FAST_CTS 56
1575#define IEEE80211_DUR_DS_SLOT 20
1576#define IEEE80211_DUR_DS_SIFS 10
1577
1578 int remainder;
1579
1580 *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1581 / plcp_signal;
1582
1583 if (plcp_signal <= PLCP_SIGNAL_2M)
1584 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1585 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1586 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1587 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1588 IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1589 else
1590 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1591 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1592 IEEE80211_DUR_DS_SHORT_PREAMBLE +
1593 IEEE80211_DUR_DS_FAST_PLCPHDR) +
1594 IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1595
1596 /* lengthen duration if long preamble */
1597 if (!short_preamble)
1598 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1599 IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1600 3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1601 IEEE80211_DUR_DS_FAST_PLCPHDR);
1602
1603
1604 *plcp = (80 * len) / plcp_signal;
1605 remainder = (80 * len) % plcp_signal;
1606 if (plcp_signal == PLCP_SIGNAL_11M &&
1607 remainder <= 30 && remainder > 0)
1608 *plcp = (*plcp | 0x8000) + 1;
1609 else if (remainder)
1610 (*plcp)++;
1611}
1612
1613/* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1614static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1615 u16 plcp_signal,
cc0b88cf
MW		 1616 size_t hdrlen)
1617{
1618 struct adm8211_priv *priv = dev->priv;
1619 unsigned long flags;
1620 dma_addr_t mapping;
1621 unsigned int entry;
1622 u32 flag;
1623
1624 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1625 PCI_DMA_TODEVICE);
1626
1627 spin_lock_irqsave(&priv->lock, flags);
1628
1629 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1630 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1631 else
1632 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1633
1634 if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1635 ieee80211_stop_queue(dev, 0);
1636
1637 entry = priv->cur_tx % priv->tx_ring_size;
1638
1639 priv->tx_buffers[entry].skb = skb;
1640 priv->tx_buffers[entry].mapping = mapping;
cc0b88cf
MW		 1641 priv->tx_buffers[entry].hdrlen = hdrlen;
1642 priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1643
1644 if (entry == priv->tx_ring_size - 1)
1645 flag |= TDES1_CONTROL_TER;
1646 priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1647
1648 /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1649 flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1650 priv->tx_ring[entry].status = cpu_to_le32(flag);
1651
1652 priv->cur_tx++;
1653
1654 spin_unlock_irqrestore(&priv->lock, flags);
1655
1656 /* Trigger transmit poll */
1657 ADM8211_CSR_WRITE(TDR, 0);
1658}
1659
1660/* Put adm8211_tx_hdr on skb and transmit */
e039fa4a 1661static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
cc0b88cf
MW		 1662{
1663 struct adm8211_tx_hdr *txhdr;
cc0b88cf
MW		 1664 size_t payload_len, hdrlen;
1665 int plcp, dur, len, plcp_signal, short_preamble;
1666 struct ieee80211_hdr *hdr;
e039fa4a
JB		 1667 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1668 struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
e6a9854b 1669 u8 rc_flags;
cc0b88cf 1670
e6a9854b
JB		 1671 rc_flags = info->control.rates[0].flags;
1672 short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
2e92e6f2 1673 plcp_signal = txrate->bitrate;
cc0b88cf
MW		 1674
1675 hdr = (struct ieee80211_hdr *)skb->data;
316af76f 1676 hdrlen = ieee80211_hdrlen(hdr->frame_control);
cc0b88cf
MW		 1677 memcpy(skb->cb, skb->data, hdrlen);
1678 hdr = (struct ieee80211_hdr *)skb->cb;
1679 skb_pull(skb, hdrlen);
1680 payload_len = skb->len;
1681
1682 txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1683 memset(txhdr, 0, sizeof(*txhdr));
1684 memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1685 txhdr->signal = plcp_signal;
1686 txhdr->frame_body_size = cpu_to_le16(payload_len);
1687 txhdr->frame_control = hdr->frame_control;
1688
1689 len = hdrlen + payload_len + FCS_LEN;
cc0b88cf
MW		 1690
1691 txhdr->frag = cpu_to_le16(0x0FFF);
1692 adm8211_calc_durations(&dur, &plcp, payload_len,
1693 len, plcp_signal, short_preamble);
1694 txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1695 txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1696 txhdr->dur_frag_head = cpu_to_le16(dur);
1697 txhdr->dur_frag_tail = cpu_to_le16(dur);
1698
1699 txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1700
1701 if (short_preamble)
1702 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1703
e6a9854b 1704 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
cc0b88cf
MW		 1705 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1706
e6a9854b 1707 txhdr->retry_limit = info->control.rates[0].count;
cc0b88cf 1708
e039fa4a 1709 adm8211_tx_raw(dev, skb, plcp_signal, hdrlen);
cc0b88cf
MW		 1710
1711 return NETDEV_TX_OK;
1712}
1713
1714static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1715{
1716 struct adm8211_priv *priv = dev->priv;
1717 unsigned int ring_size;
1718
1719 priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1720 sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1721 if (!priv->rx_buffers)
1722 return -ENOMEM;
1723
1724 priv->tx_buffers = (void *)priv->rx_buffers +
1725 sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1726
1727 /* Allocate TX/RX descriptors */
1728 ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1729 sizeof(struct adm8211_desc) * priv->tx_ring_size;
1730 priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1731 &priv->rx_ring_dma);
1732
1733 if (!priv->rx_ring) {
1734 kfree(priv->rx_buffers);
1735 priv->rx_buffers = NULL;
1736 priv->tx_buffers = NULL;
1737 return -ENOMEM;
1738 }
1739
1740 priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1741 priv->rx_ring_size);
1742 priv->tx_ring_dma = priv->rx_ring_dma +
1743 sizeof(struct adm8211_desc) * priv->rx_ring_size;
1744
1745 return 0;
1746}
1747
1748static const struct ieee80211_ops adm8211_ops = {
1749 .tx = adm8211_tx,
4150c572 1750 .start = adm8211_start,
cc0b88cf
MW		 1751 .stop = adm8211_stop,
1752 .add_interface = adm8211_add_interface,
1753 .remove_interface = adm8211_remove_interface,
1754 .config = adm8211_config,
2d0ddec5 1755 .bss_info_changed = adm8211_bss_info_changed,
3ac64bee 1756 .prepare_multicast = adm8211_prepare_multicast,
4150c572 1757 .configure_filter = adm8211_configure_filter,
cc0b88cf 1758 .get_stats = adm8211_get_stats,
cc0b88cf
MW		 1759 .get_tsf = adm8211_get_tsft
1760};
1761
1762static int __devinit adm8211_probe(struct pci_dev *pdev,
1763 const struct pci_device_id *id)
1764{
1765 struct ieee80211_hw *dev;
1766 struct adm8211_priv *priv;
1767 unsigned long mem_addr, mem_len;
1768 unsigned int io_addr, io_len;
1769 int err;
1770 u32 reg;
1771 u8 perm_addr[ETH_ALEN];
1772
cc0b88cf
MW		 1773 err = pci_enable_device(pdev);
1774 if (err) {
1775 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1776 pci_name(pdev));
1777 return err;
1778 }
1779
1780 io_addr = pci_resource_start(pdev, 0);
1781 io_len = pci_resource_len(pdev, 0);
1782 mem_addr = pci_resource_start(pdev, 1);
1783 mem_len = pci_resource_len(pdev, 1);
1784 if (io_len < 256 || mem_len < 1024) {
1785 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1786 pci_name(pdev));
1787 goto err_disable_pdev;
1788 }
1789
1790
1791 /* check signature */
1792 pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1793 if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1794 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1795 pci_name(pdev), reg);
1796 goto err_disable_pdev;
1797 }
1798
1799 err = pci_request_regions(pdev, "adm8211");
1800 if (err) {
1801 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1802 pci_name(pdev));
1803 return err; /* someone else grabbed it? don't disable it */
1804 }
1805
284901a9
YH		 1806 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
1807 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
cc0b88cf
MW		 1808 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1809 pci_name(pdev));
1810 goto err_free_reg;
1811 }
1812
1813 pci_set_master(pdev);
1814
1815 dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1816 if (!dev) {
1817 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1818 pci_name(pdev));
1819 err = -ENOMEM;
1820 goto err_free_reg;
1821 }
1822 priv = dev->priv;
1823 priv->pdev = pdev;
1824
1825 spin_lock_init(&priv->lock);
1826
1827 SET_IEEE80211_DEV(dev, &pdev->dev);
1828
1829 pci_set_drvdata(pdev, dev);
1830
1831 priv->map = pci_iomap(pdev, 1, mem_len);
1832 if (!priv->map)
1833 priv->map = pci_iomap(pdev, 0, io_len);
1834
1835 if (!priv->map) {
1836 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1837 pci_name(pdev));
1838 goto err_free_dev;
1839 }
1840
1841 priv->rx_ring_size = rx_ring_size;
1842 priv->tx_ring_size = tx_ring_size;
1843
1844 if (adm8211_alloc_rings(dev)) {
1845 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1846 pci_name(pdev));
1847 goto err_iounmap;
1848 }
1849
0e5ce1f3
AV		 1850 *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1851 *(__le16 *)&perm_addr[4] =
1852 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
cc0b88cf
MW		 1853
1854 if (!is_valid_ether_addr(perm_addr)) {
1855 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1856 pci_name(pdev));
1857 random_ether_addr(perm_addr);
1858 }
1859 SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1860
1861 dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
8318d78a 1862 /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
566bfe5a 1863 dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
f59ac048 1864 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
cc0b88cf
MW		 1865
1866 dev->channel_change_time = 1000;
566bfe5a 1867 dev->max_signal = 100; /* FIXME: find better value */
cc0b88cf 1868
cc0b88cf
MW		 1869 dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1870
1871 priv->retry_limit = 3;
1872 priv->ant_power = 0x40;
1873 priv->tx_power = 0x40;
1874 priv->lpf_cutoff = 0xFF;
1875 priv->lnags_threshold = 0xFF;
05c914fe 1876 priv->mode = NL80211_IFTYPE_UNSPECIFIED;
cc0b88cf
MW		 1877
1878 /* Power-on issue. EEPROM won't read correctly without */
f6ac0adf 1879 if (pdev->revision >= ADM8211_REV_BA) {
cc0b88cf
MW		 1880 ADM8211_CSR_WRITE(FRCTL, 0);
1881 ADM8211_CSR_READ(FRCTL);
1882 ADM8211_CSR_WRITE(FRCTL, 1);
1883 ADM8211_CSR_READ(FRCTL);
1884 msleep(100);
1885 }
1886
1887 err = adm8211_read_eeprom(dev);
1888 if (err) {
1889 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1890 pci_name(pdev));
1891 goto err_free_desc;
1892 }
1893
8318d78a 1894 priv->channel = 1;
cc0b88cf 1895
9a89c839
JB		 1896 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1897
cc0b88cf
MW		 1898 err = ieee80211_register_hw(dev);
1899 if (err) {
1900 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1901 pci_name(pdev));
b85aeb51 1902 goto err_free_eeprom;
cc0b88cf
MW		 1903 }
1904
5db55844 1905 wiphy_info(dev->wiphy, "hwaddr %pM, Rev 0x%02x\n",
c96c31e4 1906 dev->wiphy->perm_addr, pdev->revision);
cc0b88cf
MW		 1907
1908 return 0;
1909
b85aeb51
KV		 1910 err_free_eeprom:
1911 kfree(priv->eeprom);
1912
cc0b88cf
MW		 1913 err_free_desc:
1914 pci_free_consistent(pdev,
1915 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1916 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1917 priv->rx_ring, priv->rx_ring_dma);
1918 kfree(priv->rx_buffers);
1919
1920 err_iounmap:
1921 pci_iounmap(pdev, priv->map);
1922
1923 err_free_dev:
1924 pci_set_drvdata(pdev, NULL);
1925 ieee80211_free_hw(dev);
1926
1927 err_free_reg:
1928 pci_release_regions(pdev);
1929
1930 err_disable_pdev:
1931 pci_disable_device(pdev);
1932 return err;
1933}
1934
1935
1936static void __devexit adm8211_remove(struct pci_dev *pdev)
1937{
1938 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1939 struct adm8211_priv *priv;
1940
1941 if (!dev)
1942 return;
1943
1944 ieee80211_unregister_hw(dev);
1945
1946 priv = dev->priv;
1947
1948 pci_free_consistent(pdev,
1949 sizeof(struct adm8211_desc) * priv->rx_ring_size +
1950 sizeof(struct adm8211_desc) * priv->tx_ring_size,
1951 priv->rx_ring, priv->rx_ring_dma);
1952
1953 kfree(priv->rx_buffers);
1954 kfree(priv->eeprom);
1955 pci_iounmap(pdev, priv->map);
1956 pci_release_regions(pdev);
1957 pci_disable_device(pdev);
1958 ieee80211_free_hw(dev);
1959}
1960
1961
1962#ifdef CONFIG_PM
1963static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1964{
cc0b88cf
MW		 1965 pci_save_state(pdev);
1966 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1967 return 0;
1968}
1969
1970static int adm8211_resume(struct pci_dev *pdev)
1971{
cc0b88cf
MW		 1972 pci_set_power_state(pdev, PCI_D0);
1973 pci_restore_state(pdev);
cc0b88cf
MW		 1974 return 0;
1975}
1976#endif /* CONFIG_PM */
1977
1978
1979MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
1980
1981/* TODO: implement enable_wake */
1982static struct pci_driver adm8211_driver = {
1983 .name = "adm8211",
1984 .id_table = adm8211_pci_id_table,
1985 .probe = adm8211_probe,
1986 .remove = __devexit_p(adm8211_remove),
1987#ifdef CONFIG_PM
1988 .suspend = adm8211_suspend,
1989 .resume = adm8211_resume,
1990#endif /* CONFIG_PM */
1991};
1992
1993
1994
1995static int __init adm8211_init(void)
1996{
cc0b88cf
MW		 1997 return pci_register_driver(&adm8211_driver);
1998}
1999
2000
2001static void __exit adm8211_exit(void)
2002{
2003 pci_unregister_driver(&adm8211_driver);
2004}
2005
2006
2007module_init(adm8211_init);
2008module_exit(adm8211_exit);
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