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Merge branch 'master' of git://dev.medozas.de/linux
[net-next-2.6.git] / drivers / net / wan / wanxl.c
CommitLineData
1da177e4
LT		 1/*
2 * wanXL serial card driver for Linux
3 * host part
4 *
5 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
10 *
11 * Status:
12 * - Only DTE (external clock) support with NRZ and NRZI encodings
13 * - wanXL100 will require minor driver modifications, no access to hw
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/sched.h>
20#include <linux/types.h>
21#include <linux/fcntl.h>
22#include <linux/string.h>
23#include <linux/errno.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/netdevice.h>
27#include <linux/hdlc.h>
28#include <linux/pci.h>
1e7f0bd8 29#include <linux/dma-mapping.h>
164006da 30#include <linux/delay.h>
1da177e4 31#include <asm/io.h>
1da177e4
LT		 32
33#include "wanxl.h"
34
35static const char* version = "wanXL serial card driver version: 0.48";
36
37#define PLX_CTL_RESET 0x40000000 /* adapter reset */
38
39#undef DEBUG_PKT
40#undef DEBUG_PCI
41
42/* MAILBOX #1 - PUTS COMMANDS */
43#define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
44#ifdef __LITTLE_ENDIAN
45#define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
46#else
47#define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
48#endif
49
50/* MAILBOX #2 - DRAM SIZE */
51#define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
52
53
54typedef struct {
55 struct net_device *dev;
56 struct card_t *card;
57 spinlock_t lock; /* for wanxl_xmit */
58 int node; /* physical port #0 - 3 */
59 unsigned int clock_type;
60 int tx_in, tx_out;
61 struct sk_buff *tx_skbs[TX_BUFFERS];
62}port_t;
63
64
65typedef struct {
66 desc_t rx_descs[RX_QUEUE_LENGTH];
67 port_status_t port_status[4];
68}card_status_t;
69
70
71typedef struct card_t {
72 int n_ports; /* 1, 2 or 4 ports */
73 u8 irq;
74
75 u8 __iomem *plx; /* PLX PCI9060 virtual base address */
76 struct pci_dev *pdev; /* for pci_name(pdev) */
77 int rx_in;
78 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
79 card_status_t *status; /* shared between host and card */
80 dma_addr_t status_address;
81 port_t ports[0]; /* 1 - 4 port_t structures follow */
82}card_t;
83
84
85
86static inline port_t* dev_to_port(struct net_device *dev)
87{
88 return (port_t *)dev_to_hdlc(dev)->priv;
89}
90
91
92static inline port_status_t* get_status(port_t *port)
93{
94 return &port->card->status->port_status[port->node];
95}
96
97
98#ifdef DEBUG_PCI
99static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr,
100 size_t size, int direction)
101{
102 dma_addr_t addr = pci_map_single(pdev, ptr, size, direction);
103 if (addr + size > 0x100000000LL)
104 printk(KERN_CRIT "wanXL %s: pci_map_single() returned memory"
105 " at 0x%LX!\n", pci_name(pdev),
106 (unsigned long long)addr);
107 return addr;
108}
109
110#undef pci_map_single
111#define pci_map_single pci_map_single_debug
112#endif
113
114
115/* Cable and/or personality module change interrupt service */
116static inline void wanxl_cable_intr(port_t *port)
117{
118 u32 value = get_status(port)->cable;
119 int valid = 1;
120 const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
121
122 switch(value & 0x7) {
123 case STATUS_CABLE_V35: cable = "V.35"; break;
124 case STATUS_CABLE_X21: cable = "X.21"; break;
125 case STATUS_CABLE_V24: cable = "V.24"; break;
126 case STATUS_CABLE_EIA530: cable = "EIA530"; break;
127 case STATUS_CABLE_NONE: cable = "no"; break;
128 default: cable = "invalid";
129 }
130
131 switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
132 case STATUS_CABLE_V35: pm = "V.35"; break;
133 case STATUS_CABLE_X21: pm = "X.21"; break;
134 case STATUS_CABLE_V24: pm = "V.24"; break;
135 case STATUS_CABLE_EIA530: pm = "EIA530"; break;
136 case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break;
137 default: pm = "invalid personality"; valid = 0;
138 }
139
140 if (valid) {
141 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
142 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
143 ", DSR off";
144 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
145 ", carrier off";
146 }
147 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
148 }
149 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n",
150 port->dev->name, pm, dte, cable, dsr, dcd);
151
c2ce9204
KH		 152 if (value & STATUS_CABLE_DCD)
153 netif_carrier_on(port->dev);
154 else
155 netif_carrier_off(port->dev);
1da177e4
LT		 156}
157
158
159
160/* Transmit complete interrupt service */
161static inline void wanxl_tx_intr(port_t *port)
162{
163 struct net_device *dev = port->dev;
1da177e4
LT		 164 while (1) {
165 desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
166 struct sk_buff *skb = port->tx_skbs[port->tx_in];
167
168 switch (desc->stat) {
169 case PACKET_FULL:
170 case PACKET_EMPTY:
171 netif_wake_queue(dev);
172 return;
173
174 case PACKET_UNDERRUN:
198191c4
KH		 175 dev->stats.tx_errors++;
176 dev->stats.tx_fifo_errors++;
1da177e4
LT		 177 break;
178
179 default:
198191c4
KH		 180 dev->stats.tx_packets++;
181 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 182 }
183 desc->stat = PACKET_EMPTY; /* Free descriptor */
184 pci_unmap_single(port->card->pdev, desc->address, skb->len,
185 PCI_DMA_TODEVICE);
186 dev_kfree_skb_irq(skb);
187 port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
188 }
189}
190
191
192
193/* Receive complete interrupt service */
194static inline void wanxl_rx_intr(card_t *card)
195{
196 desc_t *desc;
197 while (desc = &card->status->rx_descs[card->rx_in],
198 desc->stat != PACKET_EMPTY) {
199 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports)
200 printk(KERN_CRIT "wanXL %s: received packet for"
201 " nonexistent port\n", pci_name(card->pdev));
202 else {
203 struct sk_buff *skb = card->rx_skbs[card->rx_in];
204 port_t *port = &card->ports[desc->stat &
205 PACKET_PORT_MASK];
206 struct net_device *dev = port->dev;
1da177e4
LT		 207
208 if (!skb)
198191c4 209 dev->stats.rx_dropped++;
1da177e4
LT		 210 else {
211 pci_unmap_single(card->pdev, desc->address,
212 BUFFER_LENGTH,
213 PCI_DMA_FROMDEVICE);
214 skb_put(skb, desc->length);
215
216#ifdef DEBUG_PKT
217 printk(KERN_DEBUG "%s RX(%i):", dev->name,
218 skb->len);
219 debug_frame(skb);
220#endif
198191c4
KH		 221 dev->stats.rx_packets++;
222 dev->stats.rx_bytes += skb->len;
1da177e4
LT		 223 skb->protocol = hdlc_type_trans(skb, dev);
224 netif_rx(skb);
225 skb = NULL;
226 }
227
228 if (!skb) {
229 skb = dev_alloc_skb(BUFFER_LENGTH);
230 desc->address = skb ?
231 pci_map_single(card->pdev, skb->data,
232 BUFFER_LENGTH,
233 PCI_DMA_FROMDEVICE) : 0;
234 card->rx_skbs[card->rx_in] = skb;
235 }
236 }
237 desc->stat = PACKET_EMPTY; /* Free descriptor */
238 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
239 }
240}
241
242
243
7d12e780 244static irqreturn_t wanxl_intr(int irq, void* dev_id)
1da177e4
LT		 245{
246 card_t *card = dev_id;
247 int i;
248 u32 stat;
249 int handled = 0;
250
251
252 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
253 handled = 1;
254 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
255
256 for (i = 0; i < card->n_ports; i++) {
257 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
258 wanxl_tx_intr(&card->ports[i]);
259 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
260 wanxl_cable_intr(&card->ports[i]);
261 }
262 if (stat & (1 << DOORBELL_FROM_CARD_RX))
263 wanxl_rx_intr(card);
264 }
265
266 return IRQ_RETVAL(handled);
267}
268
269
270
d71a6749 271static netdev_tx_t wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 272{
273 port_t *port = dev_to_port(dev);
274 desc_t *desc;
275
276 spin_lock(&port->lock);
277
278 desc = &get_status(port)->tx_descs[port->tx_out];
279 if (desc->stat != PACKET_EMPTY) {
280 /* should never happen - previous xmit should stop queue */
281#ifdef DEBUG_PKT
282 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
283#endif
284 netif_stop_queue(dev);
285 spin_unlock_irq(&port->lock);
5b548140 286 return NETDEV_TX_BUSY; /* request packet to be queued */
1da177e4
LT		 287 }
288
289#ifdef DEBUG_PKT
290 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
291 debug_frame(skb);
292#endif
293
294 port->tx_skbs[port->tx_out] = skb;
295 desc->address = pci_map_single(port->card->pdev, skb->data, skb->len,
296 PCI_DMA_TODEVICE);
297 desc->length = skb->len;
298 desc->stat = PACKET_FULL;
299 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
300 port->card->plx + PLX_DOORBELL_TO_CARD);
1da177e4
LT		 301
302 port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
303
304 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
305 netif_stop_queue(dev);
306#ifdef DEBUG_PKT
307 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
308#endif
309 }
310
311 spin_unlock(&port->lock);
ec634fe3 312 return NETDEV_TX_OK;
1da177e4
LT		 313}
314
315
316
317static int wanxl_attach(struct net_device *dev, unsigned short encoding,
318 unsigned short parity)
319{
320 port_t *port = dev_to_port(dev);
321
322 if (encoding != ENCODING_NRZ &&
323 encoding != ENCODING_NRZI)
324 return -EINVAL;
325
326 if (parity != PARITY_NONE &&
327 parity != PARITY_CRC32_PR1_CCITT &&
328 parity != PARITY_CRC16_PR1_CCITT &&
329 parity != PARITY_CRC32_PR0_CCITT &&
330 parity != PARITY_CRC16_PR0_CCITT)
331 return -EINVAL;
332
333 get_status(port)->encoding = encoding;
334 get_status(port)->parity = parity;
335 return 0;
336}
337
338
339
340static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
341{
342 const size_t size = sizeof(sync_serial_settings);
343 sync_serial_settings line;
344 port_t *port = dev_to_port(dev);
345
346 if (cmd != SIOCWANDEV)
347 return hdlc_ioctl(dev, ifr, cmd);
348
349 switch (ifr->ifr_settings.type) {
350 case IF_GET_IFACE:
351 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
352 if (ifr->ifr_settings.size < size) {
353 ifr->ifr_settings.size = size; /* data size wanted */
354 return -ENOBUFS;
355 }
356 line.clock_type = get_status(port)->clocking;
357 line.clock_rate = 0;
358 line.loopback = 0;
359
360 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
361 return -EFAULT;
362 return 0;
363
364 case IF_IFACE_SYNC_SERIAL:
365 if (!capable(CAP_NET_ADMIN))
366 return -EPERM;
367 if (dev->flags & IFF_UP)
368 return -EBUSY;
369
370 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync,
371 size))
372 return -EFAULT;
373
374 if (line.clock_type != CLOCK_EXT &&
375 line.clock_type != CLOCK_TXFROMRX)
376 return -EINVAL; /* No such clock setting */
377
378 if (line.loopback != 0)
379 return -EINVAL;
380
381 get_status(port)->clocking = line.clock_type;
382 return 0;
383
384 default:
385 return hdlc_ioctl(dev, ifr, cmd);
386 }
387}
388
389
390
391static int wanxl_open(struct net_device *dev)
392{
393 port_t *port = dev_to_port(dev);
394 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
395 unsigned long timeout;
396 int i;
397
398 if (get_status(port)->open) {
399 printk(KERN_ERR "%s: port already open\n", dev->name);
400 return -EIO;
401 }
402 if ((i = hdlc_open(dev)) != 0)
403 return i;
404
405 port->tx_in = port->tx_out = 0;
406 for (i = 0; i < TX_BUFFERS; i++)
407 get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
408 /* signal the card */
409 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
410
411 timeout = jiffies + HZ;
d157e023 412 do {
1da177e4
LT		 413 if (get_status(port)->open) {
414 netif_start_queue(dev);
415 return 0;
416 }
d157e023 417 } while (time_after(timeout, jiffies));
1da177e4
LT		 418
419 printk(KERN_ERR "%s: unable to open port\n", dev->name);
420 /* ask the card to close the port, should it be still alive */
421 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
422 return -EFAULT;
423}
424
425
426
427static int wanxl_close(struct net_device *dev)
428{
429 port_t *port = dev_to_port(dev);
430 unsigned long timeout;
431 int i;
432
433 hdlc_close(dev);
434 /* signal the card */
435 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
436 port->card->plx + PLX_DOORBELL_TO_CARD);
437
438 timeout = jiffies + HZ;
d157e023 439 do {
1da177e4
LT		 440 if (!get_status(port)->open)
441 break;
d157e023 442 } while (time_after(timeout, jiffies));
1da177e4
LT		 443
444 if (get_status(port)->open)
445 printk(KERN_ERR "%s: unable to close port\n", dev->name);
446
447 netif_stop_queue(dev);
448
449 for (i = 0; i < TX_BUFFERS; i++) {
450 desc_t *desc = &get_status(port)->tx_descs[i];
451
452 if (desc->stat != PACKET_EMPTY) {
453 desc->stat = PACKET_EMPTY;
454 pci_unmap_single(port->card->pdev, desc->address,
455 port->tx_skbs[i]->len,
456 PCI_DMA_TODEVICE);
457 dev_kfree_skb(port->tx_skbs[i]);
458 }
459 }
460 return 0;
461}
462
463
464
465static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
466{
1da177e4
LT		 467 port_t *port = dev_to_port(dev);
468
198191c4
KH		 469 dev->stats.rx_over_errors = get_status(port)->rx_overruns;
470 dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors;
471 dev->stats.rx_errors = dev->stats.rx_over_errors +
472 dev->stats.rx_frame_errors;
473 return &dev->stats;
1da177e4
LT		 474}
475
476
477
478static int wanxl_puts_command(card_t *card, u32 cmd)
479{
480 unsigned long timeout = jiffies + 5 * HZ;
481
482 writel(cmd, card->plx + PLX_MAILBOX_1);
483 do {
484 if (readl(card->plx + PLX_MAILBOX_1) == 0)
485 return 0;
486
487 schedule();
488 }while (time_after(timeout, jiffies));
489
490 return -1;
491}
492
493
494
495static void wanxl_reset(card_t *card)
496{
497 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
498
499 writel(0x80, card->plx + PLX_MAILBOX_0);
500 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
501 readl(card->plx + PLX_CONTROL); /* wait for posted write */
502 udelay(1);
503 writel(old_value, card->plx + PLX_CONTROL);
504 readl(card->plx + PLX_CONTROL); /* wait for posted write */
505}
506
507
508
509static void wanxl_pci_remove_one(struct pci_dev *pdev)
510{
511 card_t *card = pci_get_drvdata(pdev);
512 int i;
513
514 for (i = 0; i < card->n_ports; i++) {
515 unregister_hdlc_device(card->ports[i].dev);
516 free_netdev(card->ports[i].dev);
517 }
518
519 /* unregister and free all host resources */
520 if (card->irq)
521 free_irq(card->irq, card);
522
523 wanxl_reset(card);
524
525 for (i = 0; i < RX_QUEUE_LENGTH; i++)
526 if (card->rx_skbs[i]) {
527 pci_unmap_single(card->pdev,
528 card->status->rx_descs[i].address,
529 BUFFER_LENGTH, PCI_DMA_FROMDEVICE);
530 dev_kfree_skb(card->rx_skbs[i]);
531 }
532
533 if (card->plx)
534 iounmap(card->plx);
535
536 if (card->status)
537 pci_free_consistent(pdev, sizeof(card_status_t),
538 card->status, card->status_address);
539
540 pci_release_regions(pdev);
541 pci_disable_device(pdev);
542 pci_set_drvdata(pdev, NULL);
543 kfree(card);
544}
545
546
547#include "wanxlfw.inc"
548
991990a1
KH		 549static const struct net_device_ops wanxl_ops = {
550 .ndo_open = wanxl_open,
551 .ndo_stop = wanxl_close,
552 .ndo_change_mtu = hdlc_change_mtu,
553 .ndo_start_xmit = hdlc_start_xmit,
554 .ndo_do_ioctl = wanxl_ioctl,
555 .ndo_get_stats = wanxl_get_stats,
556};
557
1da177e4
LT		 558static int __devinit wanxl_pci_init_one(struct pci_dev *pdev,
559 const struct pci_device_id *ent)
560{
561 card_t *card;
562 u32 ramsize, stat;
563 unsigned long timeout;
564 u32 plx_phy; /* PLX PCI base address */
565 u32 mem_phy; /* memory PCI base addr */
566 u8 __iomem *mem; /* memory virtual base addr */
567 int i, ports, alloc_size;
568
569#ifndef MODULE
570 static int printed_version;
571 if (!printed_version) {
572 printed_version++;
573 printk(KERN_INFO "%s\n", version);
574 }
575#endif
576
577 i = pci_enable_device(pdev);
578 if (i)
579 return i;
580
581 /* QUICC can only access first 256 MB of host RAM directly,
582 but PLX9060 DMA does 32-bits for actual packet data transfers */
583
584 /* FIXME when PCI/DMA subsystems are fixed.
585 We set both dma_mask and consistent_dma_mask to 28 bits
586 and pray pci_alloc_consistent() will use this info. It should
587 work on most platforms */
ce0b6201
YH		 588 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(28)) ||
589 pci_set_dma_mask(pdev, DMA_BIT_MASK(28))) {
1da177e4
LT		 590 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
591 return -EIO;
592 }
593
594 i = pci_request_regions(pdev, "wanXL");
595 if (i) {
596 pci_disable_device(pdev);
597 return i;
598 }
599
600 switch (pdev->device) {
601 case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break;
602 case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break;
603 default: ports = 4;
604 }
605
606 alloc_size = sizeof(card_t) + ports * sizeof(port_t);
dd00cc48 607 card = kzalloc(alloc_size, GFP_KERNEL);
1da177e4
LT		 608 if (card == NULL) {
609 printk(KERN_ERR "wanXL %s: unable to allocate memory\n",
610 pci_name(pdev));
611 pci_release_regions(pdev);
612 pci_disable_device(pdev);
613 return -ENOBUFS;
614 }
1da177e4
LT		 615
616 pci_set_drvdata(pdev, card);
617 card->pdev = pdev;
618
619 card->status = pci_alloc_consistent(pdev, sizeof(card_status_t),
620 &card->status_address);
621 if (card->status == NULL) {
622 wanxl_pci_remove_one(pdev);
623 return -ENOBUFS;
624 }
625
626#ifdef DEBUG_PCI
627 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
628 " at 0x%LX\n", pci_name(pdev),
629 (unsigned long long)card->status_address);
630#endif
631
632 /* FIXME when PCI/DMA subsystems are fixed.
633 We set both dma_mask and consistent_dma_mask back to 32 bits
634 to indicate the card can do 32-bit DMA addressing */
284901a9
YH		 635 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) ||
636 pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 637 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
638 wanxl_pci_remove_one(pdev);
639 return -EIO;
640 }
641
642 /* set up PLX mapping */
643 plx_phy = pci_resource_start(pdev, 0);
4446065a 644
1da177e4 645 card->plx = ioremap_nocache(plx_phy, 0x70);
4446065a
KH		 646 if (!card->plx) {
647 printk(KERN_ERR "wanxl: ioremap() failed\n");
648 wanxl_pci_remove_one(pdev);
649 return -EFAULT;
650 }
1da177e4
LT		 651
652#if RESET_WHILE_LOADING
653 wanxl_reset(card);
654#endif
655
656 timeout = jiffies + 20 * HZ;
657 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
658 if (time_before(timeout, jiffies)) {
659 printk(KERN_WARNING "wanXL %s: timeout waiting for"
660 " PUTS to complete\n", pci_name(pdev));
661 wanxl_pci_remove_one(pdev);
662 return -ENODEV;
663 }
664
665 switch(stat & 0xC0) {
666 case 0x00: /* hmm - PUTS completed with non-zero code? */
667 case 0x80: /* PUTS still testing the hardware */
668 break;
669
670 default:
671 printk(KERN_WARNING "wanXL %s: PUTS test 0x%X"
672 " failed\n", pci_name(pdev), stat & 0x30);
673 wanxl_pci_remove_one(pdev);
674 return -ENODEV;
675 }
676
677 schedule();
678 }
679
680 /* get on-board memory size (PUTS detects no more than 4 MB) */
681 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
682
683 /* set up on-board RAM mapping */
684 mem_phy = pci_resource_start(pdev, 2);
685
686
687 /* sanity check the board's reported memory size */
688 if (ramsize < BUFFERS_ADDR +
689 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
690 printk(KERN_WARNING "wanXL %s: no enough on-board RAM"
691 " (%u bytes detected, %u bytes required)\n",
692 pci_name(pdev), ramsize, BUFFERS_ADDR +
693 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
694 wanxl_pci_remove_one(pdev);
695 return -ENODEV;
696 }
697
698 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
699 printk(KERN_WARNING "wanXL %s: unable to Set Byte Swap"
700 " Mode\n", pci_name(pdev));
701 wanxl_pci_remove_one(pdev);
702 return -ENODEV;
703 }
704
705 for (i = 0; i < RX_QUEUE_LENGTH; i++) {
706 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
707 card->rx_skbs[i] = skb;
708 if (skb)
709 card->status->rx_descs[i].address =
710 pci_map_single(card->pdev, skb->data,
711 BUFFER_LENGTH,
712 PCI_DMA_FROMDEVICE);
713 }
714
715 mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware));
4446065a
KH		 716 if (!mem) {
717 printk(KERN_ERR "wanxl: ioremap() failed\n");
718 wanxl_pci_remove_one(pdev);
719 return -EFAULT;
720 }
721
1da177e4 722 for (i = 0; i < sizeof(firmware); i += 4)
90458401 723 writel(ntohl(*(__be32*)(firmware + i)), mem + PDM_OFFSET + i);
1da177e4
LT		 724
725 for (i = 0; i < ports; i++)
726 writel(card->status_address +
727 (void *)&card->status->port_status[i] -
728 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
729 writel(card->status_address, mem + PDM_OFFSET + 20);
730 writel(PDM_OFFSET, mem);
731 iounmap(mem);
732
733 writel(0, card->plx + PLX_MAILBOX_5);
734
735 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
736 printk(KERN_WARNING "wanXL %s: unable to Abort and Jump\n",
737 pci_name(pdev));
738 wanxl_pci_remove_one(pdev);
739 return -ENODEV;
740 }
741
742 stat = 0;
743 timeout = jiffies + 5 * HZ;
744 do {
745 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)
746 break;
747 schedule();
748 }while (time_after(timeout, jiffies));
749
750 if (!stat) {
93ab8e84 751 printk(KERN_WARNING "wanXL %s: timeout while initializing card "
1da177e4
LT		 752 "firmware\n", pci_name(pdev));
753 wanxl_pci_remove_one(pdev);
754 return -ENODEV;
755 }
756
757#if DETECT_RAM
758 ramsize = stat;
759#endif
760
761 printk(KERN_INFO "wanXL %s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n",
762 pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq);
763
764 /* Allocate IRQ */
1fb9df5d 765 if (request_irq(pdev->irq, wanxl_intr, IRQF_SHARED, "wanXL", card)) {
1da177e4
LT		 766 printk(KERN_WARNING "wanXL %s: could not allocate IRQ%i.\n",
767 pci_name(pdev), pdev->irq);
768 wanxl_pci_remove_one(pdev);
769 return -EBUSY;
770 }
771 card->irq = pdev->irq;
772
773 for (i = 0; i < ports; i++) {
774 hdlc_device *hdlc;
775 port_t *port = &card->ports[i];
776 struct net_device *dev = alloc_hdlcdev(port);
777 if (!dev) {
778 printk(KERN_ERR "wanXL %s: unable to allocate"
779 " memory\n", pci_name(pdev));
780 wanxl_pci_remove_one(pdev);
781 return -ENOMEM;
782 }
783
784 port->dev = dev;
785 hdlc = dev_to_hdlc(dev);
786 spin_lock_init(&port->lock);
1da177e4 787 dev->tx_queue_len = 50;
991990a1 788 dev->netdev_ops = &wanxl_ops;
1da177e4
LT		 789 hdlc->attach = wanxl_attach;
790 hdlc->xmit = wanxl_xmit;
1da177e4
LT		 791 port->card = card;
792 port->node = i;
793 get_status(port)->clocking = CLOCK_EXT;
794 if (register_hdlc_device(dev)) {
795 printk(KERN_ERR "wanXL %s: unable to register hdlc"
796 " device\n", pci_name(pdev));
797 free_netdev(dev);
798 wanxl_pci_remove_one(pdev);
799 return -ENOBUFS;
800 }
801 card->n_ports++;
802 }
803
804 printk(KERN_INFO "wanXL %s: port", pci_name(pdev));
805 for (i = 0; i < ports; i++)
806 printk("%s #%i: %s", i ? "," : "", i,
807 card->ports[i].dev->name);
808 printk("\n");
809
810 for (i = 0; i < ports; i++)
811 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/
812
813 return 0;
814}
815
a3aa1884 816static DEFINE_PCI_DEVICE_TABLE(wanxl_pci_tbl) = {
1da177e4
LT		 817 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID,
818 PCI_ANY_ID, 0, 0, 0 },
819 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID,
820 PCI_ANY_ID, 0, 0, 0 },
821 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID,
822 PCI_ANY_ID, 0, 0, 0 },
823 { 0, }
824};
825
826
827static struct pci_driver wanxl_pci_driver = {
828 .name = "wanXL",
829 .id_table = wanxl_pci_tbl,
830 .probe = wanxl_pci_init_one,
831 .remove = wanxl_pci_remove_one,
832};
833
834
835static int __init wanxl_init_module(void)
836{
837#ifdef MODULE
838 printk(KERN_INFO "%s\n", version);
839#endif
29917620 840 return pci_register_driver(&wanxl_pci_driver);
1da177e4
LT		 841}
842
843static void __exit wanxl_cleanup_module(void)
844{
845 pci_unregister_driver(&wanxl_pci_driver);
846}
847
848
849MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
850MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
851MODULE_LICENSE("GPL v2");
852MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
853
854module_init(wanxl_init_module);
855module_exit(wanxl_cleanup_module);
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