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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / wan / pc300_drv.c
CommitLineData
1da177e4 1#define USE_PCI_CLOCK
dcfc5d78 2static const char rcsid[] =
1da177e4
LT		 3"Revision: 3.4.5 Date: 2002/03/07 ";
4
5/*
6 * pc300.c Cyclades-PC300(tm) Driver.
7 *
8 * Author: Ivan Passos <ivan@cyclades.com>
9 * Maintainer: PC300 Maintainer <pc300@cyclades.com>
10 *
11 * Copyright: (c) 1999-2003 Cyclades Corp.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 * Using tabstop = 4.
19 *
20 * $Log: pc300_drv.c,v $
21 * Revision 3.23 2002/03/20 13:58:40 henrique
22 * Fixed ortographic mistakes
23 *
24 * Revision 3.22 2002/03/13 16:56:56 henrique
25 * Take out the debug messages
26 *
27 * Revision 3.21 2002/03/07 14:17:09 henrique
28 * License data fixed
29 *
30 * Revision 3.20 2002/01/17 17:58:52 ivan
31 * Support for PC300-TE/M (PMC).
32 *
33 * Revision 3.19 2002/01/03 17:08:47 daniela
34 * Enables DMA reception when the SCA-II disables it improperly.
35 *
36 * Revision 3.18 2001/12/03 18:47:50 daniela
37 * Esthetic changes.
38 *
39 * Revision 3.17 2001/10/19 16:50:13 henrique
40 * Patch to kernel 2.4.12 and new generic hdlc.
41 *
42 * Revision 3.16 2001/10/16 15:12:31 regina
43 * clear statistics
44 *
45 * Revision 3.11 to 3.15 2001/10/11 20:26:04 daniela
46 * More DMA fixes for noisy lines.
47 * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
48 * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
49 * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
50 * Fixed BOF interrupt treatment. Created dma_start routine.
51 * Changed min and max to cpc_min and cpc_max.
52 *
53 * Revision 3.10 2001/08/06 12:01:51 regina
54 * Fixed problem in DSR_DE bit.
55 *
56 * Revision 3.9 2001/07/18 19:27:26 daniela
57 * Added some history comments.
58 *
59 * Revision 3.8 2001/07/12 13:11:19 regina
60 * bug fix - DCD-OFF in pc300 tty driver
61 *
62 * Revision 3.3 to 3.7 2001/07/06 15:00:20 daniela
63 * Removing kernel 2.4.3 and previous support.
64 * DMA transmission bug fix.
65 * MTU check in cpc_net_rx fixed.
66 * Boot messages reviewed.
67 * New configuration parameters (line code, CRC calculation and clock).
68 *
69 * Revision 3.2 2001/06/22 13:13:02 regina
70 * MLPPP implementation. Changed the header of message trace to include
71 * the device name. New format : "hdlcX[R/T]: ".
72 * Default configuration changed.
73 *
74 * Revision 3.1 2001/06/15 regina
75 * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
76 * upping major version number
77 *
78 * Revision 1.1.1.1 2001/06/13 20:25:04 daniela
79 * PC300 initial CVS version (3.4.0-pre1)
80 *
81 * Revision 3.0.1.2 2001/06/08 daniela
82 * Did some changes in the DMA programming implementation to avoid the
83 * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
84 *
85 * Revision 3.0.1.1 2001/05/02 daniela
86 * Added kernel 2.4.3 support.
87 *
88 * Revision 3.0.1.0 2001/03/13 daniela, henrique
89 * Added Frame Relay Support.
90 * Driver now uses HDLC generic driver to provide protocol support.
91 *
92 * Revision 3.0.0.8 2001/03/02 daniela
93 * Fixed ram size detection.
94 * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
95 *
96 * Revision 3.0.0.7 2001/02/23 daniela
97 * netif_stop_queue called before the SCA-II transmition commands in
98 * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
99 * transmition interrupts.
100 * Fixed falc_check_status for Unframed E1.
101 *
102 * Revision 3.0.0.6 2000/12/13 daniela
103 * Implemented pc300util support: trace, statistics, status and loopback
104 * tests for the PC300 TE boards.
105 *
106 * Revision 3.0.0.5 2000/12/12 ivan
107 * Added support for Unframed E1.
108 * Implemented monitor mode.
109 * Fixed DCD sensitivity on the second channel.
110 * Driver now complies with new PCI kernel architecture.
111 *
112 * Revision 3.0.0.4 2000/09/28 ivan
113 * Implemented DCD sensitivity.
114 * Moved hardware-specific open to the end of cpc_open, to avoid race
115 * conditions with early reception interrupts.
116 * Included code for [request|release]_mem_region().
117 * Changed location of pc300.h .
118 * Minor code revision (contrib. of Jeff Garzik).
119 *
120 * Revision 3.0.0.3 2000/07/03 ivan
121 * Previous bugfix for the framing errors with external clock made X21
122 * boards stop working. This version fixes it.
123 *
124 * Revision 3.0.0.2 2000/06/23 ivan
125 * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
126 * handling when Tx timeouts occur.
127 * Revisited Rx statistics.
128 * Fixed a bug in the SCA-II programming that would cause framing errors
129 * when external clock was configured.
130 *
131 * Revision 3.0.0.1 2000/05/26 ivan
132 * Added logic in the SCA interrupt handler so that no board can monopolize
133 * the driver.
134 * Request PLX I/O region, although driver doesn't use it, to avoid
135 * problems with other drivers accessing it.
136 *
137 * Revision 3.0.0.0 2000/05/15 ivan
138 * Did some changes in the DMA programming implementation to avoid the
139 * occurrence of a SCA-II bug in the second channel.
140 * Implemented workaround for PLX9050 bug that would cause a system lockup
141 * in certain systems, depending on the MMIO addresses allocated to the
142 * board.
143 * Fixed the FALC chip programming to avoid synchronization problems in the
144 * second channel (TE only).
145 * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
146 * cpc_queue_xmit().
147 * Changed the built-in driver implementation so that the driver can use the
148 * general 'hdlcN' naming convention instead of proprietary device names.
149 * Driver load messages are now device-centric, instead of board-centric.
150 * Dynamic allocation of net_device structures.
151 * Code is now compliant with the new module interface (module_[init|exit]).
152 * Make use of the PCI helper functions to access PCI resources.
153 *
154 * Revision 2.0.0.0 2000/04/15 ivan
155 * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
156 *
157 * Revision 1.1.0.0 2000/02/28 ivan
158 * Major changes in the driver architecture.
159 * Softnet compliancy implemented.
160 * Driver now reports physical instead of virtual memory addresses.
161 * Added cpc_change_mtu function.
162 *
163 * Revision 1.0.0.0 1999/12/16 ivan
164 * First official release.
165 * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
166 * Support for monolythic installation (i.e., drv built into the kernel).
167 * X.25 additional checking when lapb_[dis]connect_request returns an error.
168 * SCA programming now covers X.21 as well.
169 *
170 * Revision 0.3.1.0 1999/11/18 ivan
171 * Made X.25 support configuration-dependent (as it depends on external
172 * modules to work).
173 * Changed X.25-specific function names to comply with adopted convention.
174 * Fixed typos in X.25 functions that would cause compile errors (Daniela).
175 * Fixed bug in ch_config that would disable interrupts on a previously
176 * enabled channel if the other channel on the same board was enabled later.
177 *
178 * Revision 0.3.0.0 1999/11/16 daniela
179 * X.25 support.
180 *
181 * Revision 0.2.3.0 1999/11/15 ivan
182 * Function cpc_ch_status now provides more detailed information.
183 * Added support for X.21 clock configuration.
184 * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
185 * Now using PCI clock instead of internal oscillator clock for the SCA.
186 *
187 * Revision 0.2.2.0 1999/11/10 ivan
188 * Changed the *_dma_buf_check functions so that they would print only
189 * the useful info instead of the whole buffer descriptor bank.
190 * Fixed bug in cpc_queue_xmit that would eventually crash the system
191 * in case of a packet drop.
192 * Implemented TX underrun handling.
193 * Improved SCA fine tuning to boost up its performance.
194 *
195 * Revision 0.2.1.0 1999/11/03 ivan
196 * Added functions *dma_buf_pt_init to allow independent initialization
197 * of the next-descr. and DMA buffer pointers on the DMA descriptors.
198 * Kernel buffer release and tbusy clearing is now done in the interrupt
199 * handler.
200 * Fixed bug in cpc_open that would cause an interface reopen to fail.
201 * Added a protocol-specific code section in cpc_net_rx.
202 * Removed printk level defs (they might be added back after the beta phase).
203 *
204 * Revision 0.2.0.0 1999/10/28 ivan
205 * Revisited the code so that new protocols can be easily added / supported.
206 *
207 * Revision 0.1.0.1 1999/10/20 ivan
208 * Mostly "esthetic" changes.
209 *
210 * Revision 0.1.0.0 1999/10/11 ivan
211 * Initial version.
212 *
213 */
214
215#include <linux/module.h>
216#include <linux/kernel.h>
217#include <linux/mm.h>
218#include <linux/ioport.h>
219#include <linux/pci.h>
220#include <linux/errno.h>
221#include <linux/string.h>
222#include <linux/init.h>
223#include <linux/delay.h>
224#include <linux/net.h>
225#include <linux/skbuff.h>
226#include <linux/if_arp.h>
227#include <linux/netdevice.h>
d32da050 228#include <linux/etherdevice.h>
1da177e4
LT		 229#include <linux/spinlock.h>
230#include <linux/if.h>
5a0e3ad6 231#include <linux/slab.h>
1da177e4
LT		 232#include <net/arp.h>
233
234#include <asm/io.h>
235#include <asm/uaccess.h>
236
237#include "pc300.h"
238
239#define CPC_LOCK(card,flags) \
240 do { \
241 spin_lock_irqsave(&card->card_lock, flags); \
242 } while (0)
243
244#define CPC_UNLOCK(card,flags) \
245 do { \
246 spin_unlock_irqrestore(&card->card_lock, flags); \
247 } while (0)
248
249#undef PC300_DEBUG_PCI
250#undef PC300_DEBUG_INTR
251#undef PC300_DEBUG_TX
252#undef PC300_DEBUG_RX
253#undef PC300_DEBUG_OTHER
254
a3aa1884 255static DEFINE_PCI_DEVICE_TABLE(cpc_pci_dev_id) = {
1da177e4
LT		 256 /* PC300/RSV or PC300/X21, 2 chan */
257 {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
258 /* PC300/RSV or PC300/X21, 1 chan */
259 {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
260 /* PC300/TE, 2 chan */
261 {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
262 /* PC300/TE, 1 chan */
263 {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
264 /* PC300/TE-M, 2 chan */
265 {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
266 /* PC300/TE-M, 1 chan */
267 {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
268 /* End of table */
269 {0,},
270};
271MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
272
273#ifndef cpc_min
274#define cpc_min(a,b) (((a)<(b))?(a):(b))
275#endif
276#ifndef cpc_max
277#define cpc_max(a,b) (((a)>(b))?(a):(b))
278#endif
279
280/* prototypes */
281static void tx_dma_buf_pt_init(pc300_t *, int);
282static void tx_dma_buf_init(pc300_t *, int);
283static void rx_dma_buf_pt_init(pc300_t *, int);
284static void rx_dma_buf_init(pc300_t *, int);
285static void tx_dma_buf_check(pc300_t *, int);
286static void rx_dma_buf_check(pc300_t *, int);
7d12e780 287static irqreturn_t cpc_intr(int, void *);
b22267d3
KH		 288static int clock_rate_calc(u32, u32, int *);
289static u32 detect_ram(pc300_t *);
1da177e4
LT		 290static void plx_init(pc300_t *);
291static void cpc_trace(struct net_device *, struct sk_buff *, char);
292static int cpc_attach(struct net_device *, unsigned short, unsigned short);
7665a089 293static int cpc_close(struct net_device *dev);
1da177e4
LT		 294
295#ifdef CONFIG_PC300_MLPPP
296void cpc_tty_init(pc300dev_t * dev);
297void cpc_tty_unregister_service(pc300dev_t * pc300dev);
298void cpc_tty_receive(pc300dev_t * pc300dev);
299void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
300void cpc_tty_reset_var(void);
301#endif
302
303/************************/
304/*** DMA Routines ***/
305/************************/
306static void tx_dma_buf_pt_init(pc300_t * card, int ch)
307{
308 int i;
309 int ch_factor = ch * N_DMA_TX_BUF;
310 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
311 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
312
313 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
b22267d3 314 cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE +
1da177e4 315 (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
b22267d3
KH		 316 cpc_writel(&ptdescr->ptbuf,
317 (u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
1da177e4
LT		 318 }
319}
320
321static void tx_dma_buf_init(pc300_t * card, int ch)
322{
323 int i;
324 int ch_factor = ch * N_DMA_TX_BUF;
325 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
326 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
327
328 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
329 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
330 cpc_writew(&ptdescr->len, 0);
331 cpc_writeb(&ptdescr->status, DST_OSB);
332 }
333 tx_dma_buf_pt_init(card, ch);
334}
335
336static void rx_dma_buf_pt_init(pc300_t * card, int ch)
337{
338 int i;
339 int ch_factor = ch * N_DMA_RX_BUF;
340 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
341 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
342
343 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
b22267d3
KH		 344 cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE +
345 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
1da177e4 346 cpc_writel(&ptdescr->ptbuf,
b22267d3 347 (u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
1da177e4
LT		 348 }
349}
350
351static void rx_dma_buf_init(pc300_t * card, int ch)
352{
353 int i;
354 int ch_factor = ch * N_DMA_RX_BUF;
355 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
356 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
357
358 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
359 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
360 cpc_writew(&ptdescr->len, 0);
361 cpc_writeb(&ptdescr->status, 0);
362 }
363 rx_dma_buf_pt_init(card, ch);
364}
365
366static void tx_dma_buf_check(pc300_t * card, int ch)
367{
368 volatile pcsca_bd_t __iomem *ptdescr;
369 int i;
b22267d3
KH		 370 u16 first_bd = card->chan[ch].tx_first_bd;
371 u16 next_bd = card->chan[ch].tx_next_bd;
1da177e4
LT		 372
373 printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
374 first_bd, TX_BD_ADDR(ch, first_bd),
375 next_bd, TX_BD_ADDR(ch, next_bd));
376 for (i = first_bd,
377 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
378 i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
379 i = (i + 1) & (N_DMA_TX_BUF - 1),
380 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
381 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
382 ch, i, cpc_readl(&ptdescr->next),
383 cpc_readl(&ptdescr->ptbuf),
384 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
385 }
386 printk("\n");
387}
388
389#ifdef PC300_DEBUG_OTHER
390/* Show all TX buffer descriptors */
391static void tx1_dma_buf_check(pc300_t * card, int ch)
392{
393 volatile pcsca_bd_t __iomem *ptdescr;
394 int i;
b22267d3
KH		 395 u16 first_bd = card->chan[ch].tx_first_bd;
396 u16 next_bd = card->chan[ch].tx_next_bd;
397 u32 scabase = card->hw.scabase;
1da177e4 398
2381a55c 399 printk ("\nnfree_tx_bd = %d\n", card->chan[ch].nfree_tx_bd);
1da177e4
LT		 400 printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
401 first_bd, TX_BD_ADDR(ch, first_bd),
402 next_bd, TX_BD_ADDR(ch, next_bd));
403 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
404 cpc_readl(scabase + DTX_REG(CDAL, ch)),
405 cpc_readl(scabase + DTX_REG(EDAL, ch)));
406 for (i = 0; i < N_DMA_TX_BUF; i++) {
407 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
408 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
409 ch, i, cpc_readl(&ptdescr->next),
410 cpc_readl(&ptdescr->ptbuf),
411 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
412 }
413 printk("\n");
414}
415#endif
b22267d3 416
1da177e4
LT		 417static void rx_dma_buf_check(pc300_t * card, int ch)
418{
419 volatile pcsca_bd_t __iomem *ptdescr;
420 int i;
b22267d3
KH		 421 u16 first_bd = card->chan[ch].rx_first_bd;
422 u16 last_bd = card->chan[ch].rx_last_bd;
1da177e4
LT		 423 int ch_factor;
424
425 ch_factor = ch * N_DMA_RX_BUF;
426 printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
427 for (i = 0, ptdescr = (card->hw.rambase +
428 DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
429 i < N_DMA_RX_BUF; i++, ptdescr++) {
430 if (cpc_readb(&ptdescr->status) & DST_OSB)
431 printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
432 ch, i, cpc_readl(&ptdescr->next),
433 cpc_readl(&ptdescr->ptbuf),
434 cpc_readb(&ptdescr->status),
435 cpc_readw(&ptdescr->len));
436 }
437 printk("\n");
438}
439
7665a089 440static int dma_get_rx_frame_size(pc300_t * card, int ch)
1da177e4
LT		 441{
442 volatile pcsca_bd_t __iomem *ptdescr;
b22267d3 443 u16 first_bd = card->chan[ch].rx_first_bd;
1da177e4 444 int rcvd = 0;
b22267d3 445 volatile u8 status;
1da177e4
LT		 446
447 ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
448 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
449 rcvd += cpc_readw(&ptdescr->len);
450 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
451 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
452 /* Return the size of a good frame or incomplete bad frame
453 * (dma_buf_read will clean the buffer descriptors in this case). */
807540ba 454 return rcvd;
1da177e4
LT		 455 }
456 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
457 }
807540ba 458 return -1;
1da177e4
LT		 459}
460
461/*
462 * dma_buf_write: writes a frame to the Tx DMA buffers
463 * NOTE: this function writes one frame at a time.
464 */
b22267d3 465static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len)
1da177e4
LT		 466{
467 int i, nchar;
468 volatile pcsca_bd_t __iomem *ptdescr;
469 int tosend = len;
b22267d3 470 u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1;
1da177e4
LT		 471
472 if (nbuf >= card->chan[ch].nfree_tx_bd) {
473 return -ENOMEM;
474 }
475
476 for (i = 0; i < nbuf; i++) {
477 ptdescr = (card->hw.rambase +
478 TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
479 nchar = cpc_min(BD_DEF_LEN, tosend);
480 if (cpc_readb(&ptdescr->status) & DST_OSB) {
481 memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
482 &ptdata[len - tosend], nchar);
483 cpc_writew(&ptdescr->len, nchar);
484 card->chan[ch].nfree_tx_bd--;
485 if ((i + 1) == nbuf) {
486 /* This must be the last BD to be used */
487 cpc_writeb(&ptdescr->status, DST_EOM);
488 } else {
489 cpc_writeb(&ptdescr->status, 0);
490 }
491 } else {
492 return -ENOMEM;
493 }
494 tosend -= nchar;
495 card->chan[ch].tx_next_bd =
496 (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
497 }
498 /* If it gets to here, it means we have sent the whole frame */
499 return 0;
500}
501
502/*
503 * dma_buf_read: reads a frame from the Rx DMA buffers
504 * NOTE: this function reads one frame at a time.
505 */
7665a089 506static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
1da177e4
LT		 507{
508 int nchar;
509 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
510 volatile pcsca_bd_t __iomem *ptdescr;
511 int rcvd = 0;
b22267d3 512 volatile u8 status;
1da177e4
LT		 513
514 ptdescr = (card->hw.rambase +
515 RX_BD_ADDR(ch, chan->rx_first_bd));
516 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
517 nchar = cpc_readw(&ptdescr->len);
8e95a202
JP		 518 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT)) ||
519 (nchar > BD_DEF_LEN)) {
1da177e4
LT		 520
521 if (nchar > BD_DEF_LEN)
522 status |= DST_RBIT;
523 rcvd = -status;
524 /* Discard remaining descriptors used by the bad frame */
525 while (chan->rx_first_bd != chan->rx_last_bd) {
526 cpc_writeb(&ptdescr->status, 0);
527 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
528 if (status & DST_EOM)
529 break;
530 ptdescr = (card->hw.rambase +
531 cpc_readl(&ptdescr->next));
532 status = cpc_readb(&ptdescr->status);
533 }
534 break;
535 }
536 if (nchar != 0) {
537 if (skb) {
538 memcpy_fromio(skb_put(skb, nchar),
539 (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
540 }
541 rcvd += nchar;
542 }
543 cpc_writeb(&ptdescr->status, 0);
544 cpc_writeb(&ptdescr->len, 0);
545 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
546
547 if (status & DST_EOM)
548 break;
549
550 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
551 }
552
553 if (rcvd != 0) {
554 /* Update pointer */
555 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
556 /* Update EDA */
557 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
558 RX_BD_ADDR(ch, chan->rx_last_bd));
559 }
807540ba 560 return rcvd;
1da177e4
LT		 561}
562
7665a089 563static void tx_dma_stop(pc300_t * card, int ch)
1da177e4
LT		 564{
565 void __iomem *scabase = card->hw.scabase;
b22267d3
KH		 566 u8 drr_ena_bit = 1 << (5 + 2 * ch);
567 u8 drr_rst_bit = 1 << (1 + 2 * ch);
1da177e4
LT		 568
569 /* Disable DMA */
570 cpc_writeb(scabase + DRR, drr_ena_bit);
571 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
572}
573
7665a089 574static void rx_dma_stop(pc300_t * card, int ch)
1da177e4
LT		 575{
576 void __iomem *scabase = card->hw.scabase;
b22267d3
KH		 577 u8 drr_ena_bit = 1 << (4 + 2 * ch);
578 u8 drr_rst_bit = 1 << (2 * ch);
1da177e4
LT		 579
580 /* Disable DMA */
581 cpc_writeb(scabase + DRR, drr_ena_bit);
582 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
583}
584
7665a089 585static void rx_dma_start(pc300_t * card, int ch)
1da177e4
LT		 586{
587 void __iomem *scabase = card->hw.scabase;
588 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
589
590 /* Start DMA */
591 cpc_writel(scabase + DRX_REG(CDAL, ch),
592 RX_BD_ADDR(ch, chan->rx_first_bd));
593 if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
594 RX_BD_ADDR(ch, chan->rx_first_bd)) {
595 cpc_writel(scabase + DRX_REG(CDAL, ch),
596 RX_BD_ADDR(ch, chan->rx_first_bd));
597 }
598 cpc_writel(scabase + DRX_REG(EDAL, ch),
599 RX_BD_ADDR(ch, chan->rx_last_bd));
600 cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
601 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
602 if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
603 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
604 }
605}
606
607/*************************/
608/*** FALC Routines ***/
609/*************************/
b22267d3 610static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd)
1da177e4
LT		 611{
612 void __iomem *falcbase = card->hw.falcbase;
613 unsigned long i = 0;
614
615 while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
616 if (i++ >= PC300_FALC_MAXLOOP) {
617 printk("%s: FALC command locked(cmd=0x%x).\n",
618 card->chan[ch].d.name, cmd);
619 break;
620 }
621 }
622 cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
623}
624
7665a089 625static void falc_intr_enable(pc300_t * card, int ch)
1da177e4
LT		 626{
627 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
628 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
629 falc_t *pfalc = (falc_t *) & chan->falc;
630 void __iomem *falcbase = card->hw.falcbase;
631
632 /* Interrupt pins are open-drain */
633 cpc_writeb(falcbase + F_REG(IPC, ch),
634 cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
635 /* Conters updated each second */
636 cpc_writeb(falcbase + F_REG(FMR1, ch),
637 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
638 /* Enable SEC and ES interrupts */
639 cpc_writeb(falcbase + F_REG(IMR3, ch),
640 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
641 if (conf->fr_mode == PC300_FR_UNFRAMED) {
642 cpc_writeb(falcbase + F_REG(IMR4, ch),
643 cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
644 } else {
645 cpc_writeb(falcbase + F_REG(IMR4, ch),
646 cpc_readb(falcbase + F_REG(IMR4, ch)) &
647 ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
648 }
649 if (conf->media == IF_IFACE_T1) {
650 cpc_writeb(falcbase + F_REG(IMR3, ch),
651 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
652 } else {
653 cpc_writeb(falcbase + F_REG(IPC, ch),
654 cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
655 if (conf->fr_mode == PC300_FR_UNFRAMED) {
656 cpc_writeb(falcbase + F_REG(IMR2, ch),
657 cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
658 } else {
659 cpc_writeb(falcbase + F_REG(IMR2, ch),
660 cpc_readb(falcbase + F_REG(IMR2, ch)) &
661 ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
662 if (pfalc->multiframe_mode) {
663 cpc_writeb(falcbase + F_REG(IMR2, ch),
664 cpc_readb(falcbase + F_REG(IMR2, ch)) &
665 ~(IMR2_T400MS | IMR2_MFAR));
666 } else {
667 cpc_writeb(falcbase + F_REG(IMR2, ch),
668 cpc_readb(falcbase + F_REG(IMR2, ch)) |
669 IMR2_T400MS | IMR2_MFAR);
670 }
671 }
672 }
673}
674
7665a089 675static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
1da177e4
LT		 676{
677 void __iomem *falcbase = card->hw.falcbase;
b22267d3 678 u8 tshf = card->chan[ch].falc.offset;
1da177e4
LT		 679
680 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
681 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
682 ~(0x80 >> ((timeslot - tshf) & 0x07)));
683 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
684 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
685 (0x80 >> (timeslot & 0x07)));
686 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
687 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
688 (0x80 >> (timeslot & 0x07)));
689}
690
7665a089 691static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
1da177e4
LT		 692{
693 void __iomem *falcbase = card->hw.falcbase;
b22267d3 694 u8 tshf = card->chan[ch].falc.offset;
1da177e4
LT		 695
696 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
697 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
698 (0x80 >> ((timeslot - tshf) & 0x07)));
699 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
700 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
701 ~(0x80 >> (timeslot & 0x07)));
702 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
703 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
704 ~(0x80 >> (timeslot & 0x07)));
705}
706
7665a089 707static void falc_close_all_timeslots(pc300_t * card, int ch)
1da177e4
LT		 708{
709 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
710 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
711 void __iomem *falcbase = card->hw.falcbase;
712
713 cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
714 cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
715 cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
716 cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
717 cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
718 cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
719 cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
720 cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
721 cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
722 if (conf->media == IF_IFACE_E1) {
723 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
724 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
725 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
726 }
727}
728
7665a089 729static void falc_open_all_timeslots(pc300_t * card, int ch)
1da177e4
LT		 730{
731 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
732 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
733 void __iomem *falcbase = card->hw.falcbase;
734
735 cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
736 if (conf->fr_mode == PC300_FR_UNFRAMED) {
737 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
738 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
739 } else {
740 /* Timeslot 0 is never enabled */
741 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
742 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
743 }
744 cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
745 cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
746 cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
747 cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
748 cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
749 cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
750 if (conf->media == IF_IFACE_E1) {
751 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
752 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
753 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
754 } else {
755 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
756 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
757 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
758 }
759}
760
7665a089 761static void falc_init_timeslot(pc300_t * card, int ch)
1da177e4
LT		 762{
763 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
764 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
765 falc_t *pfalc = (falc_t *) & chan->falc;
766 int tslot;
767
768 for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
769 if (conf->tslot_bitmap & (1 << tslot)) {
770 // Channel enabled
771 falc_open_timeslot(card, ch, tslot + 1);
772 } else {
773 // Channel disabled
774 falc_close_timeslot(card, ch, tslot + 1);
775 }
776 }
777}
778
7665a089 779static void falc_enable_comm(pc300_t * card, int ch)
1da177e4
LT		 780{
781 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
782 falc_t *pfalc = (falc_t *) & chan->falc;
783
784 if (pfalc->full_bandwidth) {
785 falc_open_all_timeslots(card, ch);
786 } else {
787 falc_init_timeslot(card, ch);
788 }
789 // CTS/DCD ON
790 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
791 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
792 ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
793}
794
7665a089 795static void falc_disable_comm(pc300_t * card, int ch)
1da177e4
LT		 796{
797 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
798 falc_t *pfalc = (falc_t *) & chan->falc;
799
800 if (pfalc->loop_active != 2) {
801 falc_close_all_timeslots(card, ch);
802 }
803 // CTS/DCD OFF
804 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
805 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
806 ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
807}
808
7665a089 809static void falc_init_t1(pc300_t * card, int ch)
1da177e4
LT		 810{
811 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
812 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
813 falc_t *pfalc = (falc_t *) & chan->falc;
814 void __iomem *falcbase = card->hw.falcbase;
b22267d3 815 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
1da177e4
LT		 816
817 /* Switch to T1 mode (PCM 24) */
818 cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
819
820 /* Wait 20 us for setup */
821 udelay(20);
822
823 /* Transmit Buffer Size (1 frame) */
824 cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
825
826 /* Clock mode */
827 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
828 cpc_writeb(falcbase + F_REG(LIM0, ch),
829 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
830 } else { /* Slave mode */
831 cpc_writeb(falcbase + F_REG(LIM0, ch),
832 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
833 cpc_writeb(falcbase + F_REG(LOOP, ch),
834 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
835 }
836
837 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
838 cpc_writeb(falcbase + F_REG(FMR0, ch),
839 cpc_readb(falcbase + F_REG(FMR0, ch)) &
840 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
841
842 switch (conf->lcode) {
843 case PC300_LC_AMI:
844 cpc_writeb(falcbase + F_REG(FMR0, ch),
845 cpc_readb(falcbase + F_REG(FMR0, ch)) |
846 FMR0_XC1 | FMR0_RC1);
847 /* Clear Channel register to ON for all channels */
848 cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
849 cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
850 cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
851 break;
852
853 case PC300_LC_B8ZS:
854 cpc_writeb(falcbase + F_REG(FMR0, ch),
855 cpc_readb(falcbase + F_REG(FMR0, ch)) |
856 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
857 break;
858
859 case PC300_LC_NRZ:
860 cpc_writeb(falcbase + F_REG(FMR0, ch),
861 cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
862 break;
863 }
864
865 cpc_writeb(falcbase + F_REG(LIM0, ch),
866 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
867 cpc_writeb(falcbase + F_REG(LIM0, ch),
868 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
869 /* Set interface mode to 2 MBPS */
870 cpc_writeb(falcbase + F_REG(FMR1, ch),
871 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
872
873 switch (conf->fr_mode) {
874 case PC300_FR_ESF:
875 pfalc->multiframe_mode = 0;
876 cpc_writeb(falcbase + F_REG(FMR4, ch),
877 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
878 cpc_writeb(falcbase + F_REG(FMR1, ch),
879 cpc_readb(falcbase + F_REG(FMR1, ch)) |
880 FMR1_CRC | FMR1_EDL);
881 cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
882 cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
883 cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
884 cpc_writeb(falcbase + F_REG(FMR0, ch),
885 cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
886 cpc_writeb(falcbase + F_REG(FMR2, ch),
887 cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
888 break;
889
890 case PC300_FR_D4:
891 pfalc->multiframe_mode = 1;
892 cpc_writeb(falcbase + F_REG(FMR4, ch),
893 cpc_readb(falcbase + F_REG(FMR4, ch)) &
894 ~(FMR4_FM1 | FMR4_FM0));
895 cpc_writeb(falcbase + F_REG(FMR0, ch),
896 cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
897 cpc_writeb(falcbase + F_REG(FMR2, ch),
898 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
899 break;
900 }
901
902 /* Enable Automatic Resynchronization */
903 cpc_writeb(falcbase + F_REG(FMR4, ch),
904 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
905
906 /* Transmit Automatic Remote Alarm */
907 cpc_writeb(falcbase + F_REG(FMR2, ch),
908 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
909
910 /* Channel translation mode 1 : one to one */
911 cpc_writeb(falcbase + F_REG(FMR1, ch),
912 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
913
914 /* No signaling */
915 cpc_writeb(falcbase + F_REG(FMR1, ch),
916 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
917 cpc_writeb(falcbase + F_REG(FMR5, ch),
918 cpc_readb(falcbase + F_REG(FMR5, ch)) &
919 ~(FMR5_EIBR | FMR5_SRS));
920 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
921
922 cpc_writeb(falcbase + F_REG(LIM1, ch),
923 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
924
925 switch (conf->lbo) {
926 /* Provides proper Line Build Out */
927 case PC300_LBO_0_DB:
928 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
929 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
930 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
931 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
932 break;
933 case PC300_LBO_7_5_DB:
934 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
935 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
936 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
937 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
938 break;
939 case PC300_LBO_15_DB:
940 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
941 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
942 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
943 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
944 break;
945 case PC300_LBO_22_5_DB:
946 cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
947 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
948 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
949 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
950 break;
951 }
952
953 /* Transmit Clock-Slot Offset */
954 cpc_writeb(falcbase + F_REG(XC0, ch),
955 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
956 /* Transmit Time-slot Offset */
957 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
958 /* Receive Clock-Slot offset */
959 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
960 /* Receive Time-slot offset */
961 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
962
963 /* LOS Detection after 176 consecutive 0s */
964 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
965 /* LOS Recovery after 22 ones in the time window of PCD */
966 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
967
968 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
969
970 if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
971 cpc_writeb(falcbase + F_REG(RC1, ch),
972 cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
973 }
974
975 falc_close_all_timeslots(card, ch);
976}
977
7665a089 978static void falc_init_e1(pc300_t * card, int ch)
1da177e4
LT		 979{
980 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
981 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
982 falc_t *pfalc = (falc_t *) & chan->falc;
983 void __iomem *falcbase = card->hw.falcbase;
b22267d3 984 u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
1da177e4
LT		 985
986 /* Switch to E1 mode (PCM 30) */
987 cpc_writeb(falcbase + F_REG(FMR1, ch),
988 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
989
990 /* Clock mode */
991 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
992 cpc_writeb(falcbase + F_REG(LIM0, ch),
993 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
994 } else { /* Slave mode */
995 cpc_writeb(falcbase + F_REG(LIM0, ch),
996 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
997 }
998 cpc_writeb(falcbase + F_REG(LOOP, ch),
999 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
1000
1001 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1002 cpc_writeb(falcbase + F_REG(FMR0, ch),
1003 cpc_readb(falcbase + F_REG(FMR0, ch)) &
1004 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1005
1006 switch (conf->lcode) {
1007 case PC300_LC_AMI:
1008 cpc_writeb(falcbase + F_REG(FMR0, ch),
1009 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1010 FMR0_XC1 | FMR0_RC1);
1011 break;
1012
1013 case PC300_LC_HDB3:
1014 cpc_writeb(falcbase + F_REG(FMR0, ch),
1015 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1016 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1017 break;
1018
1019 case PC300_LC_NRZ:
1020 break;
1021 }
1022
1023 cpc_writeb(falcbase + F_REG(LIM0, ch),
1024 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1025 /* Set interface mode to 2 MBPS */
1026 cpc_writeb(falcbase + F_REG(FMR1, ch),
1027 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1028
1029 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1030 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1031 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1032
1033 switch (conf->fr_mode) {
1034 case PC300_FR_MF_CRC4:
1035 pfalc->multiframe_mode = 1;
1036 cpc_writeb(falcbase + F_REG(FMR1, ch),
1037 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1038 cpc_writeb(falcbase + F_REG(FMR2, ch),
1039 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1040 cpc_writeb(falcbase + F_REG(FMR2, ch),
1041 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1042 cpc_writeb(falcbase + F_REG(FMR3, ch),
1043 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1044
1045 /* MultiFrame Resynchronization */
1046 cpc_writeb(falcbase + F_REG(FMR1, ch),
1047 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1048
1049 /* Automatic Loss of Multiframe > 914 CRC errors */
1050 cpc_writeb(falcbase + F_REG(FMR2, ch),
1051 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1052
1053 /* S1 and SI1/SI2 spare Bits set to 1 */
1054 cpc_writeb(falcbase + F_REG(XSP, ch),
1055 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1056 cpc_writeb(falcbase + F_REG(XSP, ch),
1057 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1058 cpc_writeb(falcbase + F_REG(XSP, ch),
1059 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1060
1061 /* Automatic Force Resynchronization */
1062 cpc_writeb(falcbase + F_REG(FMR1, ch),
1063 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1064
1065 /* Transmit Automatic Remote Alarm */
1066 cpc_writeb(falcbase + F_REG(FMR2, ch),
1067 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1068
1069 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1070 cpc_writeb(falcbase + F_REG(XSW, ch),
1071 cpc_readb(falcbase + F_REG(XSW, ch)) |
1072 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1073 break;
1074
1075 case PC300_FR_MF_NON_CRC4:
1076 case PC300_FR_D4:
1077 pfalc->multiframe_mode = 0;
1078 cpc_writeb(falcbase + F_REG(FMR1, ch),
1079 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1080 cpc_writeb(falcbase + F_REG(FMR2, ch),
1081 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1082 ~(FMR2_RFS1 | FMR2_RFS0));
1083 cpc_writeb(falcbase + F_REG(XSW, ch),
1084 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1085 cpc_writeb(falcbase + F_REG(XSP, ch),
1086 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1087
1088 /* Automatic Force Resynchronization */
1089 cpc_writeb(falcbase + F_REG(FMR1, ch),
1090 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1091
1092 /* Transmit Automatic Remote Alarm */
1093 cpc_writeb(falcbase + F_REG(FMR2, ch),
1094 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1095
1096 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1097 cpc_writeb(falcbase + F_REG(XSW, ch),
1098 cpc_readb(falcbase + F_REG(XSW, ch)) |
1099 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1100 break;
1101
1102 case PC300_FR_UNFRAMED:
1103 pfalc->multiframe_mode = 0;
1104 cpc_writeb(falcbase + F_REG(FMR1, ch),
1105 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1106 cpc_writeb(falcbase + F_REG(FMR2, ch),
1107 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1108 ~(FMR2_RFS1 | FMR2_RFS0));
1109 cpc_writeb(falcbase + F_REG(XSP, ch),
1110 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1111 cpc_writeb(falcbase + F_REG(XSW, ch),
1112 cpc_readb(falcbase + F_REG(XSW, ch)) &
1113 ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1114 cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1115 cpc_writeb(falcbase + F_REG(FMR2, ch),
1116 cpc_readb(falcbase + F_REG(FMR2, ch)) |
1117 (FMR2_RTM | FMR2_DAIS));
1118 cpc_writeb(falcbase + F_REG(FMR2, ch),
1119 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1120 cpc_writeb(falcbase + F_REG(FMR1, ch),
1121 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1122 pfalc->sync = 1;
1123 cpc_writeb(falcbase + card->hw.cpld_reg2,
1124 cpc_readb(falcbase + card->hw.cpld_reg2) |
1125 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1126 break;
1127 }
1128
1129 /* No signaling */
1130 cpc_writeb(falcbase + F_REG(XSP, ch),
1131 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1132 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1133
1134 cpc_writeb(falcbase + F_REG(LIM1, ch),
1135 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1136 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1137
1138 /* Transmit Clock-Slot Offset */
1139 cpc_writeb(falcbase + F_REG(XC0, ch),
1140 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1141 /* Transmit Time-slot Offset */
1142 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1143 /* Receive Clock-Slot offset */
1144 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1145 /* Receive Time-slot offset */
1146 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1147
1148 /* LOS Detection after 176 consecutive 0s */
1149 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1150 /* LOS Recovery after 22 ones in the time window of PCD */
1151 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1152
1153 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1154
1155 falc_close_all_timeslots(card, ch);
1156}
1157
7665a089 1158static void falc_init_hdlc(pc300_t * card, int ch)
1da177e4
LT		 1159{
1160 void __iomem *falcbase = card->hw.falcbase;
1161 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1162 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1163
1164 /* Enable transparent data transfer */
1165 if (conf->fr_mode == PC300_FR_UNFRAMED) {
1166 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1167 } else {
1168 cpc_writeb(falcbase + F_REG(MODE, ch),
1169 cpc_readb(falcbase + F_REG(MODE, ch)) |
1170 (MODE_HRAC | MODE_MDS2));
1171 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1172 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1173 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1174 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1175 }
1176
1177 /* Tx/Rx reset */
1178 falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1179
1180 /* Enable interrupt sources */
1181 falc_intr_enable(card, ch);
1182}
1183
7665a089 1184static void te_config(pc300_t * card, int ch)
1da177e4
LT		 1185{
1186 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1187 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1188 falc_t *pfalc = (falc_t *) & chan->falc;
1189 void __iomem *falcbase = card->hw.falcbase;
b22267d3 1190 u8 dummy;
1da177e4
LT		 1191 unsigned long flags;
1192
1193 memset(pfalc, 0, sizeof(falc_t));
1194 switch (conf->media) {
1195 case IF_IFACE_T1:
1196 pfalc->num_channels = NUM_OF_T1_CHANNELS;
1197 pfalc->offset = 1;
1198 break;
1199 case IF_IFACE_E1:
1200 pfalc->num_channels = NUM_OF_E1_CHANNELS;
1201 pfalc->offset = 0;
1202 break;
1203 }
1204 if (conf->tslot_bitmap == 0xffffffffUL)
1205 pfalc->full_bandwidth = 1;
1206 else
1207 pfalc->full_bandwidth = 0;
1208
1209 CPC_LOCK(card, flags);
1210 /* Reset the FALC chip */
1211 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1212 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1213 (CPLD_REG1_FALC_RESET << (2 * ch)));
1214 udelay(10000);
1215 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1216 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1217 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1218
1219 if (conf->media == IF_IFACE_T1) {
1220 falc_init_t1(card, ch);
1221 } else {
1222 falc_init_e1(card, ch);
1223 }
1224 falc_init_hdlc(card, ch);
1225 if (conf->rx_sens == PC300_RX_SENS_SH) {
1226 cpc_writeb(falcbase + F_REG(LIM0, ch),
1227 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1228 } else {
1229 cpc_writeb(falcbase + F_REG(LIM0, ch),
1230 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1231 }
1232 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1233 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1234 ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1235
1236 /* Clear all interrupt registers */
1237 dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1238 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1239 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1240 cpc_readb(falcbase + F_REG(FISR3, ch));
1241 CPC_UNLOCK(card, flags);
1242}
1243
7665a089 1244static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1da177e4
LT		 1245{
1246 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1247 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1248 falc_t *pfalc = (falc_t *) & chan->falc;
1249 void __iomem *falcbase = card->hw.falcbase;
1250
1251 /* Verify LOS */
1252 if (frs0 & FRS0_LOS) {
1253 if (!pfalc->red_alarm) {
1254 pfalc->red_alarm = 1;
1255 pfalc->los++;
1256 if (!pfalc->blue_alarm) {
1257 // EVENT_FALC_ABNORMAL
1258 if (conf->media == IF_IFACE_T1) {
1259 /* Disable this interrupt as it may otherwise interfere
1260 * with other working boards. */
1261 cpc_writeb(falcbase + F_REG(IMR0, ch),
1262 cpc_readb(falcbase + F_REG(IMR0, ch))
1263 | IMR0_PDEN);
1264 }
1265 falc_disable_comm(card, ch);
1266 // EVENT_FALC_ABNORMAL
1267 }
1268 }
1269 } else {
1270 if (pfalc->red_alarm) {
1271 pfalc->red_alarm = 0;
1272 pfalc->losr++;
1273 }
1274 }
1275
1276 if (conf->fr_mode != PC300_FR_UNFRAMED) {
1277 /* Verify AIS alarm */
1278 if (frs0 & FRS0_AIS) {
1279 if (!pfalc->blue_alarm) {
1280 pfalc->blue_alarm = 1;
1281 pfalc->ais++;
1282 // EVENT_AIS
1283 if (conf->media == IF_IFACE_T1) {
1284 /* Disable this interrupt as it may otherwise interfere with other working boards. */
1285 cpc_writeb(falcbase + F_REG(IMR0, ch),
1286 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1287 }
1288 falc_disable_comm(card, ch);
1289 // EVENT_AIS
1290 }
1291 } else {
1292 pfalc->blue_alarm = 0;
1293 }
1294
1295 /* Verify LFA */
1296 if (frs0 & FRS0_LFA) {
1297 if (!pfalc->loss_fa) {
1298 pfalc->loss_fa = 1;
1299 pfalc->lfa++;
1300 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1301 // EVENT_FALC_ABNORMAL
1302 if (conf->media == IF_IFACE_T1) {
1303 /* Disable this interrupt as it may otherwise
1304 * interfere with other working boards. */
1305 cpc_writeb(falcbase + F_REG(IMR0, ch),
1306 cpc_readb(falcbase + F_REG(IMR0, ch))
1307 | IMR0_PDEN);
1308 }
1309 falc_disable_comm(card, ch);
1310 // EVENT_FALC_ABNORMAL
1311 }
1312 }
1313 } else {
1314 if (pfalc->loss_fa) {
1315 pfalc->loss_fa = 0;
1316 pfalc->farec++;
1317 }
1318 }
1319
1320 /* Verify LMFA */
1321 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1322 /* D4 or CRC4 frame mode */
1323 if (!pfalc->loss_mfa) {
1324 pfalc->loss_mfa = 1;
1325 pfalc->lmfa++;
1326 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1327 !pfalc->loss_fa) {
1328 // EVENT_FALC_ABNORMAL
1329 if (conf->media == IF_IFACE_T1) {
1330 /* Disable this interrupt as it may otherwise
1331 * interfere with other working boards. */
1332 cpc_writeb(falcbase + F_REG(IMR0, ch),
1333 cpc_readb(falcbase + F_REG(IMR0, ch))
1334 | IMR0_PDEN);
1335 }
1336 falc_disable_comm(card, ch);
1337 // EVENT_FALC_ABNORMAL
1338 }
1339 }
1340 } else {
1341 pfalc->loss_mfa = 0;
1342 }
1343
1344 /* Verify Remote Alarm */
1345 if (frs0 & FRS0_RRA) {
1346 if (!pfalc->yellow_alarm) {
1347 pfalc->yellow_alarm = 1;
1348 pfalc->rai++;
1349 if (pfalc->sync) {
1350 // EVENT_RAI
1351 falc_disable_comm(card, ch);
1352 // EVENT_RAI
1353 }
1354 }
1355 } else {
1356 pfalc->yellow_alarm = 0;
1357 }
1358 } /* if !PC300_UNFRAMED */
1359
1360 if (pfalc->red_alarm || pfalc->loss_fa ||
1361 pfalc->loss_mfa || pfalc->blue_alarm) {
1362 if (pfalc->sync) {
1363 pfalc->sync = 0;
1364 chan->d.line_off++;
1365 cpc_writeb(falcbase + card->hw.cpld_reg2,
1366 cpc_readb(falcbase + card->hw.cpld_reg2) &
1367 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1368 }
1369 } else {
1370 if (!pfalc->sync) {
1371 pfalc->sync = 1;
1372 chan->d.line_on++;
1373 cpc_writeb(falcbase + card->hw.cpld_reg2,
1374 cpc_readb(falcbase + card->hw.cpld_reg2) |
1375 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1376 }
1377 }
1378
1379 if (pfalc->sync && !pfalc->yellow_alarm) {
1380 if (!pfalc->active) {
1381 // EVENT_FALC_NORMAL
1382 if (pfalc->loop_active) {
1383 return;
1384 }
1385 if (conf->media == IF_IFACE_T1) {
1386 cpc_writeb(falcbase + F_REG(IMR0, ch),
1387 cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1388 }
1389 falc_enable_comm(card, ch);
1390 // EVENT_FALC_NORMAL
1391 pfalc->active = 1;
1392 }
1393 } else {
1394 if (pfalc->active) {
1395 pfalc->active = 0;
1396 }
1397 }
1398}
1399
7665a089 1400static void falc_update_stats(pc300_t * card, int ch)
1da177e4
LT		 1401{
1402 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1403 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1404 falc_t *pfalc = (falc_t *) & chan->falc;
1405 void __iomem *falcbase = card->hw.falcbase;
b22267d3 1406 u16 counter;
1da177e4
LT		 1407
1408 counter = cpc_readb(falcbase + F_REG(FECL, ch));
1409 counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1410 pfalc->fec += counter;
1411
1412 counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1413 counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1414 pfalc->cvc += counter;
1415
1416 counter = cpc_readb(falcbase + F_REG(CECL, ch));
1417 counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1418 pfalc->cec += counter;
1419
1420 counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1421 counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1422 pfalc->ebc += counter;
1423
1424 if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1425 mdelay(10);
1426 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1427 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1428 pfalc->bec += counter;
1429
1430 if (((conf->media == IF_IFACE_T1) &&
1431 (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
8e95a202 1432 (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN))) ||
1da177e4
LT		 1433 ((conf->media == IF_IFACE_E1) &&
1434 (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1435 pfalc->prbs = 2;
1436 } else {
1437 pfalc->prbs = 1;
1438 }
1439 }
1440}
1441
1442/*----------------------------------------------------------------------------
1443 * falc_remote_loop
1444 *----------------------------------------------------------------------------
1445 * Description: In the remote loopback mode the clock and data recovered
1446 * from the line inputs RL1/2 or RDIP/RDIN are routed back
1447 * to the line outputs XL1/2 or XDOP/XDON via the analog
1448 * transmitter. As in normal mode they are processsed by
1449 * the synchronizer and then sent to the system interface.
1450 *----------------------------------------------------------------------------
1451 */
7665a089 1452static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1da177e4
LT		 1453{
1454 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1455 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1456 falc_t *pfalc = (falc_t *) & chan->falc;
1457 void __iomem *falcbase = card->hw.falcbase;
1458
1459 if (loop_on) {
1460 // EVENT_FALC_ABNORMAL
1461 if (conf->media == IF_IFACE_T1) {
1462 /* Disable this interrupt as it may otherwise interfere with
1463 * other working boards. */
1464 cpc_writeb(falcbase + F_REG(IMR0, ch),
1465 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1466 }
1467 falc_disable_comm(card, ch);
1468 // EVENT_FALC_ABNORMAL
1469 cpc_writeb(falcbase + F_REG(LIM1, ch),
1470 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1471 pfalc->loop_active = 1;
1472 } else {
1473 cpc_writeb(falcbase + F_REG(LIM1, ch),
1474 cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1475 pfalc->sync = 0;
1476 cpc_writeb(falcbase + card->hw.cpld_reg2,
1477 cpc_readb(falcbase + card->hw.cpld_reg2) &
1478 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1479 pfalc->active = 0;
1480 falc_issue_cmd(card, ch, CMDR_XRES);
1481 pfalc->loop_active = 0;
1482 }
1483}
1484
1485/*----------------------------------------------------------------------------
1486 * falc_local_loop
1487 *----------------------------------------------------------------------------
1488 * Description: The local loopback mode disconnects the receive lines
1489 * RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1490 * signals coming from the line the data provided by system
1491 * interface are routed through the analog receiver back to
1492 * the system interface. The unipolar bit stream will be
1493 * undisturbed transmitted on the line. Receiver and transmitter
1494 * coding must be identical.
1495 *----------------------------------------------------------------------------
1496 */
7665a089 1497static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1da177e4
LT		 1498{
1499 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1500 falc_t *pfalc = (falc_t *) & chan->falc;
1501 void __iomem *falcbase = card->hw.falcbase;
1502
1503 if (loop_on) {
1504 cpc_writeb(falcbase + F_REG(LIM0, ch),
1505 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1506 pfalc->loop_active = 1;
1507 } else {
1508 cpc_writeb(falcbase + F_REG(LIM0, ch),
1509 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1510 pfalc->loop_active = 0;
1511 }
1512}
1513
1514/*----------------------------------------------------------------------------
1515 * falc_payload_loop
1516 *----------------------------------------------------------------------------
1517 * Description: This routine allows to enable/disable payload loopback.
1518 * When the payload loop is activated, the received 192 bits
1519 * of payload data will be looped back to the transmit
1520 * direction. The framing bits, CRC6 and DL bits are not
1521 * looped. They are originated by the FALC-LH transmitter.
1522 *----------------------------------------------------------------------------
1523 */
7665a089 1524static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1da177e4
LT		 1525{
1526 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1527 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1528 falc_t *pfalc = (falc_t *) & chan->falc;
1529 void __iomem *falcbase = card->hw.falcbase;
1530
1531 if (loop_on) {
1532 // EVENT_FALC_ABNORMAL
1533 if (conf->media == IF_IFACE_T1) {
1534 /* Disable this interrupt as it may otherwise interfere with
1535 * other working boards. */
1536 cpc_writeb(falcbase + F_REG(IMR0, ch),
1537 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1538 }
1539 falc_disable_comm(card, ch);
1540 // EVENT_FALC_ABNORMAL
1541 cpc_writeb(falcbase + F_REG(FMR2, ch),
1542 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1543 if (conf->media == IF_IFACE_T1) {
1544 cpc_writeb(falcbase + F_REG(FMR4, ch),
1545 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1546 } else {
1547 cpc_writeb(falcbase + F_REG(FMR5, ch),
1548 cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1549 }
1550 falc_open_all_timeslots(card, ch);
1551 pfalc->loop_active = 2;
1552 } else {
1553 cpc_writeb(falcbase + F_REG(FMR2, ch),
1554 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1555 if (conf->media == IF_IFACE_T1) {
1556 cpc_writeb(falcbase + F_REG(FMR4, ch),
1557 cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1558 } else {
1559 cpc_writeb(falcbase + F_REG(FMR5, ch),
1560 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1561 }
1562 pfalc->sync = 0;
1563 cpc_writeb(falcbase + card->hw.cpld_reg2,
1564 cpc_readb(falcbase + card->hw.cpld_reg2) &
1565 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1566 pfalc->active = 0;
1567 falc_issue_cmd(card, ch, CMDR_XRES);
1568 pfalc->loop_active = 0;
1569 }
1570}
1571
1572/*----------------------------------------------------------------------------
1573 * turn_off_xlu
1574 *----------------------------------------------------------------------------
1575 * Description: Turns XLU bit off in the proper register
1576 *----------------------------------------------------------------------------
1577 */
7665a089 1578static void turn_off_xlu(pc300_t * card, int ch)
1da177e4
LT		 1579{
1580 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1581 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1582 void __iomem *falcbase = card->hw.falcbase;
1583
1584 if (conf->media == IF_IFACE_T1) {
1585 cpc_writeb(falcbase + F_REG(FMR5, ch),
1586 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1587 } else {
1588 cpc_writeb(falcbase + F_REG(FMR3, ch),
1589 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1590 }
1591}
1592
1593/*----------------------------------------------------------------------------
1594 * turn_off_xld
1595 *----------------------------------------------------------------------------
1596 * Description: Turns XLD bit off in the proper register
1597 *----------------------------------------------------------------------------
1598 */
7665a089 1599static void turn_off_xld(pc300_t * card, int ch)
1da177e4
LT		 1600{
1601 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1602 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1603 void __iomem *falcbase = card->hw.falcbase;
1604
1605 if (conf->media == IF_IFACE_T1) {
1606 cpc_writeb(falcbase + F_REG(FMR5, ch),
1607 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1608 } else {
1609 cpc_writeb(falcbase + F_REG(FMR3, ch),
1610 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1611 }
1612}
1613
1614/*----------------------------------------------------------------------------
1615 * falc_generate_loop_up_code
1616 *----------------------------------------------------------------------------
1617 * Description: This routine writes the proper FALC chip register in order
1618 * to generate a LOOP activation code over a T1/E1 line.
1619 *----------------------------------------------------------------------------
1620 */
7665a089 1621static void falc_generate_loop_up_code(pc300_t * card, int ch)
1da177e4
LT		 1622{
1623 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1624 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1625 falc_t *pfalc = (falc_t *) & chan->falc;
1626 void __iomem *falcbase = card->hw.falcbase;
1627
1628 if (conf->media == IF_IFACE_T1) {
1629 cpc_writeb(falcbase + F_REG(FMR5, ch),
1630 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1631 } else {
1632 cpc_writeb(falcbase + F_REG(FMR3, ch),
1633 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1634 }
1635 // EVENT_FALC_ABNORMAL
1636 if (conf->media == IF_IFACE_T1) {
1637 /* Disable this interrupt as it may otherwise interfere with
1638 * other working boards. */
1639 cpc_writeb(falcbase + F_REG(IMR0, ch),
1640 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1641 }
1642 falc_disable_comm(card, ch);
1643 // EVENT_FALC_ABNORMAL
1644 pfalc->loop_gen = 1;
1645}
1646
1647/*----------------------------------------------------------------------------
1648 * falc_generate_loop_down_code
1649 *----------------------------------------------------------------------------
1650 * Description: This routine writes the proper FALC chip register in order
1651 * to generate a LOOP deactivation code over a T1/E1 line.
1652 *----------------------------------------------------------------------------
1653 */
7665a089 1654static void falc_generate_loop_down_code(pc300_t * card, int ch)
1da177e4
LT		 1655{
1656 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1657 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1658 falc_t *pfalc = (falc_t *) & chan->falc;
1659 void __iomem *falcbase = card->hw.falcbase;
1660
1661 if (conf->media == IF_IFACE_T1) {
1662 cpc_writeb(falcbase + F_REG(FMR5, ch),
1663 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1664 } else {
1665 cpc_writeb(falcbase + F_REG(FMR3, ch),
1666 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1667 }
1668 pfalc->sync = 0;
1669 cpc_writeb(falcbase + card->hw.cpld_reg2,
1670 cpc_readb(falcbase + card->hw.cpld_reg2) &
1671 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1672 pfalc->active = 0;
1673//? falc_issue_cmd(card, ch, CMDR_XRES);
1674 pfalc->loop_gen = 0;
1675}
1676
1677/*----------------------------------------------------------------------------
1678 * falc_pattern_test
1679 *----------------------------------------------------------------------------
1680 * Description: This routine generates a pattern code and checks
1681 * it on the reception side.
1682 *----------------------------------------------------------------------------
1683 */
7665a089 1684static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1da177e4
LT		 1685{
1686 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1687 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1688 falc_t *pfalc = (falc_t *) & chan->falc;
1689 void __iomem *falcbase = card->hw.falcbase;
1690
1691 if (activate) {
1692 pfalc->prbs = 1;
1693 pfalc->bec = 0;
1694 if (conf->media == IF_IFACE_T1) {
1695 /* Disable local loop activation/deactivation detect */
1696 cpc_writeb(falcbase + F_REG(IMR3, ch),
1697 cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1698 } else {
1699 /* Disable local loop activation/deactivation detect */
1700 cpc_writeb(falcbase + F_REG(IMR1, ch),
1701 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1702 }
1703 /* Activates generation and monitoring of PRBS
1704 * (Pseudo Random Bit Sequence) */
1705 cpc_writeb(falcbase + F_REG(LCR1, ch),
1706 cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1707 } else {
1708 pfalc->prbs = 0;
1709 /* Deactivates generation and monitoring of PRBS
1710 * (Pseudo Random Bit Sequence) */
1711 cpc_writeb(falcbase + F_REG(LCR1, ch),
1712 cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1713 if (conf->media == IF_IFACE_T1) {
1714 /* Enable local loop activation/deactivation detect */
1715 cpc_writeb(falcbase + F_REG(IMR3, ch),
1716 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1717 } else {
1718 /* Enable local loop activation/deactivation detect */
1719 cpc_writeb(falcbase + F_REG(IMR1, ch),
1720 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1721 }
1722 }
1723}
1724
1725/*----------------------------------------------------------------------------
1726 * falc_pattern_test_error
1727 *----------------------------------------------------------------------------
1728 * Description: This routine returns the bit error counter value
1729 *----------------------------------------------------------------------------
1730 */
b22267d3 1731static u16 falc_pattern_test_error(pc300_t * card, int ch)
1da177e4
LT		 1732{
1733 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1734 falc_t *pfalc = (falc_t *) & chan->falc;
1735
807540ba 1736 return pfalc->bec;
1da177e4
LT		 1737}
1738
1739/**********************************/
1740/*** Net Interface Routines ***/
1741/**********************************/
1742
1743static void
1744cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1745{
1746 struct sk_buff *skb;
1747
1748 if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1749 printk("%s: out of memory\n", dev->name);
1750 return;
1751 }
1752 skb_put(skb, 10 + skb_main->len);
1753
1754 skb->dev = dev;
1755 skb->protocol = htons(ETH_P_CUST);
459a98ed 1756 skb_reset_mac_header(skb);
1da177e4
LT		 1757 skb->pkt_type = PACKET_HOST;
1758 skb->len = 10 + skb_main->len;
1759
27d7ff46 1760 skb_copy_to_linear_data(skb, dev->name, 5);
1da177e4
LT		 1761 skb->data[5] = '[';
1762 skb->data[6] = rx_tx;
1763 skb->data[7] = ']';
1764 skb->data[8] = ':';
1765 skb->data[9] = ' ';
d626f62b 1766 skb_copy_from_linear_data(skb_main, &skb->data[10], skb_main->len);
1da177e4
LT		 1767
1768 netif_rx(skb);
1769}
1770
7665a089 1771static void cpc_tx_timeout(struct net_device *dev)
1da177e4 1772{
6636e117 1773 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1da177e4
LT		 1774 pc300ch_t *chan = (pc300ch_t *) d->chan;
1775 pc300_t *card = (pc300_t *) chan->card;
1da177e4
LT		 1776 int ch = chan->channel;
1777 unsigned long flags;
b22267d3 1778 u8 ilar;
1da177e4 1779
198191c4
KH		 1780 dev->stats.tx_errors++;
1781 dev->stats.tx_aborted_errors++;
1da177e4
LT		 1782 CPC_LOCK(card, flags);
1783 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1784 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1785 cpc_writeb(card->hw.scabase + ILAR, ilar);
1786 cpc_writeb(card->hw.scabase + DMER, 0x80);
1787 }
1788 if (card->hw.type == PC300_TE) {
1789 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1790 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1791 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1792 }
1ae5dc34 1793 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT		 1794 CPC_UNLOCK(card, flags);
1795 netif_wake_queue(dev);
1796}
1797
7665a089 1798static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 1799{
6636e117 1800 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1da177e4
LT		 1801 pc300ch_t *chan = (pc300ch_t *) d->chan;
1802 pc300_t *card = (pc300_t *) chan->card;
1da177e4
LT		 1803 int ch = chan->channel;
1804 unsigned long flags;
1805#ifdef PC300_DEBUG_TX
1806 int i;
1807#endif
1808
c36936ce 1809 if (!netif_carrier_ok(dev)) {
1da177e4
LT		 1810 /* DCD must be OFF: drop packet */
1811 dev_kfree_skb(skb);
198191c4
KH		 1812 dev->stats.tx_errors++;
1813 dev->stats.tx_carrier_errors++;
1da177e4
LT		 1814 return 0;
1815 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1816 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
198191c4
KH		 1817 dev->stats.tx_errors++;
1818 dev->stats.tx_carrier_errors++;
1da177e4
LT		 1819 dev_kfree_skb(skb);
1820 netif_carrier_off(dev);
1821 CPC_LOCK(card, flags);
1822 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1823 if (card->hw.type == PC300_TE) {
1824 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1825 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1826 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1827 }
1828 CPC_UNLOCK(card, flags);
1829 netif_wake_queue(dev);
1830 return 0;
1831 }
1832
1833 /* Write buffer to DMA buffers */
b22267d3 1834 if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) {
1da177e4
LT		 1835// printk("%s: write error. Dropping TX packet.\n", dev->name);
1836 netif_stop_queue(dev);
1837 dev_kfree_skb(skb);
198191c4
KH		 1838 dev->stats.tx_errors++;
1839 dev->stats.tx_dropped++;
1da177e4
LT		 1840 return 0;
1841 }
1842#ifdef PC300_DEBUG_TX
1843 printk("%s T:", dev->name);
1844 for (i = 0; i < skb->len; i++)
1845 printk(" %02x", *(skb->data + i));
1846 printk("\n");
1847#endif
1848
1849 if (d->trace_on) {
1850 cpc_trace(dev, skb, 'T');
1851 }
1da177e4
LT		 1852
1853 /* Start transmission */
1854 CPC_LOCK(card, flags);
1855 /* verify if it has more than one free descriptor */
1856 if (card->chan[ch].nfree_tx_bd <= 1) {
1857 /* don't have so stop the queue */
1858 netif_stop_queue(dev);
1859 }
1860 cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1861 TX_BD_ADDR(ch, chan->tx_next_bd));
1862 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1863 cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1864 if (card->hw.type == PC300_TE) {
1865 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1866 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1867 (CPLD_REG2_FALC_LED1 << (2 * ch)));
1868 }
1869 CPC_UNLOCK(card, flags);
1870 dev_kfree_skb(skb);
1871
1872 return 0;
1873}
1874
7665a089 1875static void cpc_net_rx(struct net_device *dev)
1da177e4 1876{
6636e117 1877 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1da177e4
LT		 1878 pc300ch_t *chan = (pc300ch_t *) d->chan;
1879 pc300_t *card = (pc300_t *) chan->card;
1da177e4
LT		 1880 int ch = chan->channel;
1881#ifdef PC300_DEBUG_RX
1882 int i;
1883#endif
1884 int rxb;
1885 struct sk_buff *skb;
1886
1887 while (1) {
1888 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1889 return;
1890
1891 if (!netif_carrier_ok(dev)) {
1892 /* DCD must be OFF: drop packet */
1893 printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1894 skb = NULL;
1895 } else {
1896 if (rxb > (dev->mtu + 40)) { /* add headers */
1897 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1898 skb = NULL;
1899 } else {
1900 skb = dev_alloc_skb(rxb);
1901 if (skb == NULL) {
1902 printk("%s: Memory squeeze!!\n", dev->name);
1903 return;
1904 }
1905 skb->dev = dev;
1906 }
1907 }
1908
1909 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1910#ifdef PC300_DEBUG_RX
1911 printk("%s: rxb = %x\n", dev->name, rxb);
1912#endif
1913 if ((skb == NULL) && (rxb > 0)) {
1914 /* rxb > dev->mtu */
198191c4
KH		 1915 dev->stats.rx_errors++;
1916 dev->stats.rx_length_errors++;
1da177e4
LT		 1917 continue;
1918 }
1919
1920 if (rxb < 0) { /* Invalid frame */
1921 rxb = -rxb;
1922 if (rxb & DST_OVR) {
198191c4
KH		 1923 dev->stats.rx_errors++;
1924 dev->stats.rx_fifo_errors++;
1da177e4
LT		 1925 }
1926 if (rxb & DST_CRC) {
198191c4
KH		 1927 dev->stats.rx_errors++;
1928 dev->stats.rx_crc_errors++;
1da177e4
LT		 1929 }
1930 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
198191c4
KH		 1931 dev->stats.rx_errors++;
1932 dev->stats.rx_frame_errors++;
1da177e4
LT		 1933 }
1934 }
1935 if (skb) {
1936 dev_kfree_skb_irq(skb);
1937 }
1938 continue;
1939 }
1940
198191c4 1941 dev->stats.rx_bytes += rxb;
1da177e4
LT		 1942
1943#ifdef PC300_DEBUG_RX
1944 printk("%s R:", dev->name);
1945 for (i = 0; i < skb->len; i++)
1946 printk(" %02x", *(skb->data + i));
1947 printk("\n");
1948#endif
1949 if (d->trace_on) {
1950 cpc_trace(dev, skb, 'R');
1951 }
198191c4 1952 dev->stats.rx_packets++;
1da177e4
LT		 1953 skb->protocol = hdlc_type_trans(skb, dev);
1954 netif_rx(skb);
1955 }
1956}
1957
1958/************************************/
1959/*** PC300 Interrupt Routines ***/
1960/************************************/
1961static void sca_tx_intr(pc300dev_t *dev)
1962{
1963 pc300ch_t *chan = (pc300ch_t *)dev->chan;
1964 pc300_t *card = (pc300_t *)chan->card;
1965 int ch = chan->channel;
1966 volatile pcsca_bd_t __iomem * ptdescr;
1da177e4
LT		 1967
1968 /* Clean up descriptors from previous transmission */
1969 ptdescr = (card->hw.rambase +
1970 TX_BD_ADDR(ch,chan->tx_first_bd));
198191c4
KH		 1971 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1972 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1973 (cpc_readb(&ptdescr->status) & DST_OSB)) {
1974 dev->dev->stats.tx_packets++;
1975 dev->dev->stats.tx_bytes += cpc_readw(&ptdescr->len);
1da177e4
LT		 1976 cpc_writeb(&ptdescr->status, DST_OSB);
1977 cpc_writew(&ptdescr->len, 0);
1978 chan->nfree_tx_bd++;
1979 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1980 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1981 }
1982
1983#ifdef CONFIG_PC300_MLPPP
1984 if (chan->conf.proto == PC300_PROTO_MLPPP) {
1985 cpc_tty_trigger_poll(dev);
1986 } else {
1987#endif
1988 /* Tell the upper layer we are ready to transmit more packets */
1989 netif_wake_queue(dev->dev);
1990#ifdef CONFIG_PC300_MLPPP
1991 }
1992#endif
1993}
1994
1995static void sca_intr(pc300_t * card)
1996{
1997 void __iomem *scabase = card->hw.scabase;
b22267d3 1998 volatile u32 status;
1da177e4
LT		 1999 int ch;
2000 int intr_count = 0;
2001 unsigned char dsr_rx;
2002
2003 while ((status = cpc_readl(scabase + ISR0)) != 0) {
2004 for (ch = 0; ch < card->hw.nchan; ch++) {
2005 pc300ch_t *chan = &card->chan[ch];
2006 pc300dev_t *d = &chan->d;
2007 struct net_device *dev = d->dev;
1da177e4
LT		 2008
2009 spin_lock(&card->card_lock);
2010
2011 /**** Reception ****/
2012 if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
b22267d3 2013 u8 drx_stat = cpc_readb(scabase + DSR_RX(ch));
1da177e4
LT		 2014
2015 /* Clear RX interrupts */
2016 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2017
2018#ifdef PC300_DEBUG_INTR
2019 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2020 ch, status, drx_stat);
2021#endif
2022 if (status & IR0_DRX(IR0_DMIA, ch)) {
2023 if (drx_stat & DSR_BOF) {
2024#ifdef CONFIG_PC300_MLPPP
2025 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2026 /* verify if driver is TTY */
2027 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2028 rx_dma_stop(card, ch);
2029 }
2030 cpc_tty_receive(d);
2031 rx_dma_start(card, ch);
2032 } else
2033#endif
2034 {
2035 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2036 rx_dma_stop(card, ch);
2037 }
2038 cpc_net_rx(dev);
2039 /* Discard invalid frames */
198191c4
KH		 2040 dev->stats.rx_errors++;
2041 dev->stats.rx_over_errors++;
1da177e4
LT		 2042 chan->rx_first_bd = 0;
2043 chan->rx_last_bd = N_DMA_RX_BUF - 1;
2044 rx_dma_start(card, ch);
2045 }
2046 }
2047 }
2048 if (status & IR0_DRX(IR0_DMIB, ch)) {
2049 if (drx_stat & DSR_EOM) {
2050 if (card->hw.type == PC300_TE) {
2051 cpc_writeb(card->hw.falcbase +
2052 card->hw.cpld_reg2,
2053 cpc_readb (card->hw.falcbase +
2054 card->hw.cpld_reg2) |
2055 (CPLD_REG2_FALC_LED1 << (2 * ch)));
2056 }
2057#ifdef CONFIG_PC300_MLPPP
2058 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2059 /* verify if driver is TTY */
2060 cpc_tty_receive(d);
2061 } else {
2062 cpc_net_rx(dev);
2063 }
2064#else
2065 cpc_net_rx(dev);
2066#endif
2067 if (card->hw.type == PC300_TE) {
2068 cpc_writeb(card->hw.falcbase +
2069 card->hw.cpld_reg2,
2070 cpc_readb (card->hw.falcbase +
2071 card->hw.cpld_reg2) &
2072 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2073 }
2074 }
2075 }
2076 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2077#ifdef PC300_DEBUG_INTR
2078 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2079 dev->name, ch, status, drx_stat, dsr_rx);
2080#endif
2081 cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2082 }
2083 }
2084
2085 /**** Transmission ****/
2086 if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
b22267d3 2087 u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch));
1da177e4
LT		 2088
2089 /* Clear TX interrupts */
2090 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2091
2092#ifdef PC300_DEBUG_INTR
2093 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2094 ch, status, dtx_stat);
2095#endif
2096 if (status & IR0_DTX(IR0_EFT, ch)) {
2097 if (dtx_stat & DSR_UDRF) {
2098 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2099 cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2100 }
2101 if (card->hw.type == PC300_TE) {
2102 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2103 cpc_readb (card->hw.falcbase +
2104 card->hw.cpld_reg2) &
2105 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2106 }
198191c4
KH		 2107 dev->stats.tx_errors++;
2108 dev->stats.tx_fifo_errors++;
1da177e4
LT		 2109 sca_tx_intr(d);
2110 }
2111 }
2112 if (status & IR0_DTX(IR0_DMIA, ch)) {
2113 if (dtx_stat & DSR_BOF) {
2114 }
2115 }
2116 if (status & IR0_DTX(IR0_DMIB, ch)) {
2117 if (dtx_stat & DSR_EOM) {
2118 if (card->hw.type == PC300_TE) {
2119 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2120 cpc_readb (card->hw.falcbase +
2121 card->hw.cpld_reg2) &
2122 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2123 }
2124 sca_tx_intr(d);
2125 }
2126 }
2127 }
2128
2129 /**** MSCI ****/
2130 if (status & IR0_M(IR0_RXINTA, ch)) {
b22267d3 2131 u8 st1 = cpc_readb(scabase + M_REG(ST1, ch));
1da177e4
LT		 2132
2133 /* Clear MSCI interrupts */
2134 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2135
2136#ifdef PC300_DEBUG_INTR
2137 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2138 ch, status, st1);
2139#endif
2140 if (st1 & ST1_CDCD) { /* DCD changed */
2141 if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2142 printk ("%s: DCD is OFF. Going administrative down.\n",
2143 dev->name);
2144#ifdef CONFIG_PC300_MLPPP
2145 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2146 netif_carrier_off(dev);
2147 }
2148#else
2149 netif_carrier_off(dev);
2150
2151#endif
2152 card->chan[ch].d.line_off++;
2153 } else { /* DCD = 1 */
2154 printk ("%s: DCD is ON. Going administrative up.\n",
2155 dev->name);
2156#ifdef CONFIG_PC300_MLPPP
2157 if (chan->conf.proto != PC300_PROTO_MLPPP)
2158 /* verify if driver is not TTY */
2159#endif
2160 netif_carrier_on(dev);
2161 card->chan[ch].d.line_on++;
2162 }
2163 }
2164 }
2165 spin_unlock(&card->card_lock);
2166 }
2167 if (++intr_count == 10)
2168 /* Too much work at this board. Force exit */
2169 break;
2170 }
2171}
2172
b22267d3 2173static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1)
1da177e4
LT		 2174{
2175 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2176 falc_t *pfalc = (falc_t *) & chan->falc;
2177 void __iomem *falcbase = card->hw.falcbase;
2178
2179 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2180 !pfalc->loop_gen) {
2181 if (frs1 & FRS1_LLBDD) {
2182 // A Line Loop Back Deactivation signal detected
2183 if (pfalc->loop_active) {
2184 falc_remote_loop(card, ch, 0);
2185 }
2186 } else {
2187 if ((frs1 & FRS1_LLBAD) &&
2188 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2189 // A Line Loop Back Activation signal detected
2190 if (!pfalc->loop_active) {
2191 falc_remote_loop(card, ch, 1);
2192 }
2193 }
2194 }
2195 }
2196}
2197
b22267d3 2198static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp)
1da177e4
LT		 2199{
2200 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2201 falc_t *pfalc = (falc_t *) & chan->falc;
2202 void __iomem *falcbase = card->hw.falcbase;
2203
2204 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2205 !pfalc->loop_gen) {
2206 if (rsp & RSP_LLBDD) {
2207 // A Line Loop Back Deactivation signal detected
2208 if (pfalc->loop_active) {
2209 falc_remote_loop(card, ch, 0);
2210 }
2211 } else {
2212 if ((rsp & RSP_LLBAD) &&
2213 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2214 // A Line Loop Back Activation signal detected
2215 if (!pfalc->loop_active) {
2216 falc_remote_loop(card, ch, 1);
2217 }
2218 }
2219 }
2220 }
2221}
2222
2223static void falc_t1_intr(pc300_t * card, int ch)
2224{
2225 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2226 falc_t *pfalc = (falc_t *) & chan->falc;
2227 void __iomem *falcbase = card->hw.falcbase;
b22267d3
KH		 2228 u8 isr0, isr3, gis;
2229 u8 dummy;
1da177e4
LT		 2230
2231 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2232 if (gis & GIS_ISR0) {
2233 isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2234 if (isr0 & FISR0_PDEN) {
2235 /* Read the bit to clear the situation */
2236 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2237 FRS1_PDEN) {
2238 pfalc->pden++;
2239 }
2240 }
2241 }
2242
2243 if (gis & GIS_ISR1) {
2244 dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2245 }
2246
2247 if (gis & GIS_ISR2) {
2248 dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2249 }
2250
2251 if (gis & GIS_ISR3) {
2252 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2253 if (isr3 & FISR3_SEC) {
2254 pfalc->sec++;
2255 falc_update_stats(card, ch);
2256 falc_check_status(card, ch,
2257 cpc_readb(falcbase + F_REG(FRS0, ch)));
2258 }
2259 if (isr3 & FISR3_ES) {
2260 pfalc->es++;
2261 }
2262 if (isr3 & FISR3_LLBSC) {
2263 falc_t1_loop_detection(card, ch,
2264 cpc_readb(falcbase + F_REG(FRS1, ch)));
2265 }
2266 }
2267 }
2268}
2269
2270static void falc_e1_intr(pc300_t * card, int ch)
2271{
2272 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2273 falc_t *pfalc = (falc_t *) & chan->falc;
2274 void __iomem *falcbase = card->hw.falcbase;
b22267d3
KH		 2275 u8 isr1, isr2, isr3, gis, rsp;
2276 u8 dummy;
1da177e4
LT		 2277
2278 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2279 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2280
2281 if (gis & GIS_ISR0) {
2282 dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2283 }
2284 if (gis & GIS_ISR1) {
2285 isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2286 if (isr1 & FISR1_XMB) {
8e95a202
JP		 2287 if ((pfalc->xmb_cause & 2) &&
2288 pfalc->multiframe_mode) {
1da177e4
LT		 2289 if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2290 (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2291 cpc_writeb(falcbase + F_REG(XSP, ch),
2292 cpc_readb(falcbase + F_REG(XSP, ch))
2293 & ~XSP_AXS);
2294 } else {
2295 cpc_writeb(falcbase + F_REG(XSP, ch),
2296 cpc_readb(falcbase + F_REG(XSP, ch))
2297 | XSP_AXS);
2298 }
2299 }
2300 pfalc->xmb_cause = 0;
2301 cpc_writeb(falcbase + F_REG(IMR1, ch),
2302 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2303 }
2304 if (isr1 & FISR1_LLBSC) {
2305 falc_e1_loop_detection(card, ch, rsp);
2306 }
2307 }
2308 if (gis & GIS_ISR2) {
2309 isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2310 if (isr2 & FISR2_T400MS) {
2311 cpc_writeb(falcbase + F_REG(XSW, ch),
2312 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2313 }
2314 if (isr2 & FISR2_MFAR) {
2315 cpc_writeb(falcbase + F_REG(XSW, ch),
2316 cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2317 }
2318 if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2319 pfalc->xmb_cause |= 2;
2320 cpc_writeb(falcbase + F_REG(IMR1, ch),
2321 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2322 }
2323 }
2324 if (gis & GIS_ISR3) {
2325 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2326 if (isr3 & FISR3_SEC) {
2327 pfalc->sec++;
2328 falc_update_stats(card, ch);
2329 falc_check_status(card, ch,
2330 cpc_readb(falcbase + F_REG(FRS0, ch)));
2331 }
2332 if (isr3 & FISR3_ES) {
2333 pfalc->es++;
2334 }
2335 }
2336 }
2337}
2338
2339static void falc_intr(pc300_t * card)
2340{
2341 int ch;
2342
2343 for (ch = 0; ch < card->hw.nchan; ch++) {
2344 pc300ch_t *chan = &card->chan[ch];
2345 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2346
2347 if (conf->media == IF_IFACE_T1) {
2348 falc_t1_intr(card, ch);
2349 } else {
2350 falc_e1_intr(card, ch);
2351 }
2352 }
2353}
2354
7d12e780 2355static irqreturn_t cpc_intr(int irq, void *dev_id)
1da177e4 2356{
79ea13ce 2357 pc300_t *card = dev_id;
b22267d3 2358 volatile u8 plx_status;
1da177e4 2359
79ea13ce 2360 if (!card) {
1da177e4
LT		 2361#ifdef PC300_DEBUG_INTR
2362 printk("cpc_intr: spurious intr %d\n", irq);
2363#endif
2364 return IRQ_NONE; /* spurious intr */
2365 }
2366
79ea13ce 2367 if (!card->hw.rambase) {
1da177e4
LT		 2368#ifdef PC300_DEBUG_INTR
2369 printk("cpc_intr: spurious intr2 %d\n", irq);
2370#endif
2371 return IRQ_NONE; /* spurious intr */
2372 }
2373
2374 switch (card->hw.type) {
2375 case PC300_RSV:
2376 case PC300_X21:
2377 sca_intr(card);
2378 break;
2379
2380 case PC300_TE:
2381 while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2382 (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2383 if (plx_status & PLX_9050_LINT1_STATUS) { /* SCA Interrupt */
2384 sca_intr(card);
2385 }
2386 if (plx_status & PLX_9050_LINT2_STATUS) { /* FALC Interrupt */
2387 falc_intr(card);
2388 }
2389 }
2390 break;
2391 }
2392 return IRQ_HANDLED;
2393}
2394
7665a089 2395static void cpc_sca_status(pc300_t * card, int ch)
1da177e4 2396{
b22267d3 2397 u8 ilar;
1da177e4
LT		 2398 void __iomem *scabase = card->hw.scabase;
2399 unsigned long flags;
2400
2401 tx_dma_buf_check(card, ch);
2402 rx_dma_buf_check(card, ch);
2403 ilar = cpc_readb(scabase + ILAR);
2404 printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2405 ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2406 cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2407 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2408 cpc_readl(scabase + DTX_REG(CDAL, ch)),
2409 cpc_readl(scabase + DTX_REG(EDAL, ch)));
2410 printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2411 cpc_readl(scabase + DRX_REG(CDAL, ch)),
2412 cpc_readl(scabase + DRX_REG(EDAL, ch)),
2413 cpc_readw(scabase + DRX_REG(BFLL, ch)));
2414 printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2415 cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2416 cpc_readb(scabase + DSR_RX(ch)));
2417 printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2418 cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2419 cpc_readb(scabase + DIR_TX(ch)),
2420 cpc_readb(scabase + DIR_RX(ch)));
2421 printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2422 cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2423 cpc_readb(scabase + FCT_TX(ch)),
2424 cpc_readb(scabase + FCT_RX(ch)));
2425 printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2426 cpc_readb(scabase + M_REG(MD0, ch)),
2427 cpc_readb(scabase + M_REG(MD1, ch)),
2428 cpc_readb(scabase + M_REG(MD2, ch)),
2429 cpc_readb(scabase + M_REG(MD3, ch)),
2430 cpc_readb(scabase + M_REG(IDL, ch)));
2431 printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2432 cpc_readb(scabase + M_REG(CMD, ch)),
2433 cpc_readb(scabase + M_REG(SA0, ch)),
2434 cpc_readb(scabase + M_REG(SA1, ch)),
2435 cpc_readb(scabase + M_REG(TFN, ch)),
2436 cpc_readb(scabase + M_REG(CTL, ch)));
2437 printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2438 cpc_readb(scabase + M_REG(ST0, ch)),
2439 cpc_readb(scabase + M_REG(ST1, ch)),
2440 cpc_readb(scabase + M_REG(ST2, ch)),
2441 cpc_readb(scabase + M_REG(ST3, ch)),
2442 cpc_readb(scabase + M_REG(ST4, ch)));
2443 printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2444 cpc_readb(scabase + M_REG(CST0, ch)),
2445 cpc_readb(scabase + M_REG(CST1, ch)),
2446 cpc_readb(scabase + M_REG(CST2, ch)),
2447 cpc_readb(scabase + M_REG(CST3, ch)),
2448 cpc_readb(scabase + M_REG(FST, ch)));
2449 printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2450 cpc_readb(scabase + M_REG(TRC0, ch)),
2451 cpc_readb(scabase + M_REG(TRC1, ch)),
2452 cpc_readb(scabase + M_REG(RRC, ch)),
2453 cpc_readb(scabase + M_REG(TBN, ch)),
2454 cpc_readb(scabase + M_REG(RBN, ch)));
2455 printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2456 cpc_readb(scabase + M_REG(TFS, ch)),
2457 cpc_readb(scabase + M_REG(TNR0, ch)),
2458 cpc_readb(scabase + M_REG(TNR1, ch)),
2459 cpc_readb(scabase + M_REG(RNR, ch)));
2460 printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2461 cpc_readb(scabase + M_REG(TCR, ch)),
2462 cpc_readb(scabase + M_REG(RCR, ch)),
2463 cpc_readb(scabase + M_REG(TNR1, ch)),
2464 cpc_readb(scabase + M_REG(RNR, ch)));
2465 printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2466 cpc_readb(scabase + M_REG(TXS, ch)),
2467 cpc_readb(scabase + M_REG(RXS, ch)),
2468 cpc_readb(scabase + M_REG(EXS, ch)),
2469 cpc_readb(scabase + M_REG(TMCT, ch)),
2470 cpc_readb(scabase + M_REG(TMCR, ch)));
2471 printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2472 cpc_readb(scabase + M_REG(IE0, ch)),
2473 cpc_readb(scabase + M_REG(IE1, ch)),
2474 cpc_readb(scabase + M_REG(IE2, ch)),
2475 cpc_readb(scabase + M_REG(IE4, ch)),
2476 cpc_readb(scabase + M_REG(FIE, ch)));
2477 printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2478
2479 if (ilar != 0) {
2480 CPC_LOCK(card, flags);
2481 cpc_writeb(scabase + ILAR, ilar);
2482 cpc_writeb(scabase + DMER, 0x80);
2483 CPC_UNLOCK(card, flags);
2484 }
2485}
2486
7665a089 2487static void cpc_falc_status(pc300_t * card, int ch)
1da177e4
LT		 2488{
2489 pc300ch_t *chan = &card->chan[ch];
2490 falc_t *pfalc = (falc_t *) & chan->falc;
2491 unsigned long flags;
2492
2493 CPC_LOCK(card, flags);
2494 printk("CH%d: %s %s %d channels\n",
2495 ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2496 pfalc->num_channels);
2497
2498 printk(" pden=%d, los=%d, losr=%d, lfa=%d, farec=%d\n",
2499 pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2500 printk(" lmfa=%d, ais=%d, sec=%d, es=%d, rai=%d\n",
2501 pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2502 printk(" bec=%d, fec=%d, cvc=%d, cec=%d, ebc=%d\n",
2503 pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2504
2505 printk("\n");
2506 printk(" STATUS: %s %s %s %s %s %s\n",
2507 (pfalc->red_alarm ? "RED" : ""),
2508 (pfalc->blue_alarm ? "BLU" : ""),
2509 (pfalc->yellow_alarm ? "YEL" : ""),
2510 (pfalc->loss_fa ? "LFA" : ""),
2511 (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2512 CPC_UNLOCK(card, flags);
2513}
2514
7665a089 2515static int cpc_change_mtu(struct net_device *dev, int new_mtu)
1da177e4
LT		 2516{
2517 if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2518 return -EINVAL;
2519 dev->mtu = new_mtu;
2520 return 0;
2521}
2522
7665a089 2523static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2524{
6636e117 2525 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1da177e4
LT		 2526 pc300ch_t *chan = (pc300ch_t *) d->chan;
2527 pc300_t *card = (pc300_t *) chan->card;
2528 pc300conf_t conf_aux;
2529 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2530 int ch = chan->channel;
2531 void __user *arg = ifr->ifr_data;
2532 struct if_settings *settings = &ifr->ifr_settings;
2533 void __iomem *scabase = card->hw.scabase;
2534
2535 if (!capable(CAP_NET_ADMIN))
2536 return -EPERM;
2537
2538 switch (cmd) {
2539 case SIOCGPC300CONF:
2540#ifdef CONFIG_PC300_MLPPP
2541 if (conf->proto != PC300_PROTO_MLPPP) {
8aca2310 2542 conf->proto = /* FIXME hdlc->proto.id */ 0;
1da177e4
LT		 2543 }
2544#else
8aca2310 2545 conf->proto = /* FIXME hdlc->proto.id */ 0;
1da177e4
LT		 2546#endif
2547 memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2548 memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2549 if (!arg ||
2550 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2551 return -EINVAL;
2552 return 0;
2553 case SIOCSPC300CONF:
2554 if (!capable(CAP_NET_ADMIN))
2555 return -EPERM;
2556 if (!arg ||
2557 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2558 return -EINVAL;
2559 if (card->hw.cpld_id < 0x02 &&
2560 conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2561 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2562 return -EINVAL;
2563 }
2564#ifdef CONFIG_PC300_MLPPP
2565 if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2566 if (conf->proto != PC300_PROTO_MLPPP) {
2567 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2568 cpc_tty_init(d); /* init TTY driver */
2569 }
2570 } else {
2571 if (conf_aux.conf.proto == 0xffff) {
2572 if (conf->proto == PC300_PROTO_MLPPP){
2573 /* ifdown interface */
2574 cpc_close(dev);
2575 }
2576 } else {
2577 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
8aca2310 2578 /* FIXME hdlc->proto.id = conf->proto; */
1da177e4
LT		 2579 }
2580 }
2581#else
2582 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
8aca2310 2583 /* FIXME hdlc->proto.id = conf->proto; */
1da177e4
LT		 2584#endif
2585 return 0;
2586 case SIOCGPC300STATUS:
2587 cpc_sca_status(card, ch);
2588 return 0;
2589 case SIOCGPC300FALCSTATUS:
2590 cpc_falc_status(card, ch);
2591 return 0;
2592
2593 case SIOCGPC300UTILSTATS:
2594 {
2595 if (!arg) { /* clear statistics */
198191c4 2596 memset(&dev->stats, 0, sizeof(dev->stats));
1da177e4
LT		 2597 if (card->hw.type == PC300_TE) {
2598 memset(&chan->falc, 0, sizeof(falc_t));
2599 }
2600 } else {
2601 pc300stats_t pc300stats;
2602
2603 memset(&pc300stats, 0, sizeof(pc300stats_t));
2604 pc300stats.hw_type = card->hw.type;
2605 pc300stats.line_on = card->chan[ch].d.line_on;
2606 pc300stats.line_off = card->chan[ch].d.line_off;
198191c4
KH		 2607 memcpy(&pc300stats.gen_stats, &dev->stats,
2608 sizeof(dev->stats));
1da177e4
LT		 2609 if (card->hw.type == PC300_TE)
2610 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2611 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2612 return -EFAULT;
2613 }
2614 return 0;
2615 }
2616
2617 case SIOCGPC300UTILSTATUS:
2618 {
2619 struct pc300status pc300status;
2620
2621 pc300status.hw_type = card->hw.type;
2622 if (card->hw.type == PC300_TE) {
2623 pc300status.te_status.sync = chan->falc.sync;
2624 pc300status.te_status.red_alarm = chan->falc.red_alarm;
2625 pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2626 pc300status.te_status.loss_fa = chan->falc.loss_fa;
2627 pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2628 pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2629 pc300status.te_status.prbs = chan->falc.prbs;
2630 } else {
2631 pc300status.gen_status.dcd =
2632 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2633 pc300status.gen_status.cts =
2634 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2635 pc300status.gen_status.rts =
2636 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2637 pc300status.gen_status.dtr =
2638 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2639 /* There is no DSR in HD64572 */
2640 }
8e95a202
JP		 2641 if (!arg ||
2642 copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2643 return -EINVAL;
1da177e4
LT		 2644 return 0;
2645 }
2646
2647 case SIOCSPC300TRACE:
2648 /* Sets/resets a trace_flag for the respective device */
2649 if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2650 return -EINVAL;
2651 return 0;
2652
2653 case SIOCSPC300LOOPBACK:
2654 {
2655 struct pc300loopback pc300loop;
2656
2657 /* TE boards only */
2658 if (card->hw.type != PC300_TE)
2659 return -EINVAL;
2660
2661 if (!arg ||
2662 copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2663 return -EINVAL;
2664 switch (pc300loop.loop_type) {
2665 case PC300LOCLOOP: /* Turn the local loop on/off */
2666 falc_local_loop(card, ch, pc300loop.loop_on);
2667 return 0;
2668
2669 case PC300REMLOOP: /* Turn the remote loop on/off */
2670 falc_remote_loop(card, ch, pc300loop.loop_on);
2671 return 0;
2672
2673 case PC300PAYLOADLOOP: /* Turn the payload loop on/off */
2674 falc_payload_loop(card, ch, pc300loop.loop_on);
2675 return 0;
2676
2677 case PC300GENLOOPUP: /* Generate loop UP */
2678 if (pc300loop.loop_on) {
2679 falc_generate_loop_up_code (card, ch);
2680 } else {
2681 turn_off_xlu(card, ch);
2682 }
2683 return 0;
2684
2685 case PC300GENLOOPDOWN: /* Generate loop DOWN */
2686 if (pc300loop.loop_on) {
2687 falc_generate_loop_down_code (card, ch);
2688 } else {
2689 turn_off_xld(card, ch);
2690 }
2691 return 0;
2692
2693 default:
2694 return -EINVAL;
2695 }
2696 }
2697
2698 case SIOCSPC300PATTERNTEST:
2699 /* Turn the pattern test on/off and show the errors counter */
2700 {
2701 struct pc300patterntst pc300patrntst;
2702
2703 /* TE boards only */
2704 if (card->hw.type != PC300_TE)
2705 return -EINVAL;
2706
2707 if (card->hw.cpld_id < 0x02) {
2708 /* CPLD_ID < 0x02 doesn't support pattern test */
2709 return -EINVAL;
2710 }
2711
2712 if (!arg ||
2713 copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2714 return -EINVAL;
2715 if (pc300patrntst.patrntst_on == 2) {
2716 if (chan->falc.prbs == 0) {
2717 falc_pattern_test(card, ch, 1);
2718 }
2719 pc300patrntst.num_errors =
2720 falc_pattern_test_error(card, ch);
c14ea0ca
JL		 2721 if (copy_to_user(arg, &pc300patrntst,
2722 sizeof(pc300patterntst_t)))
1da177e4
LT		 2723 return -EINVAL;
2724 } else {
2725 falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2726 }
2727 return 0;
2728 }
2729
2730 case SIOCWANDEV:
2731 switch (ifr->ifr_settings.type) {
2732 case IF_GET_IFACE:
2733 {
2734 const size_t size = sizeof(sync_serial_settings);
2735 ifr->ifr_settings.type = conf->media;
2736 if (ifr->ifr_settings.size < size) {
2737 /* data size wanted */
2738 ifr->ifr_settings.size = size;
2739 return -ENOBUFS;
2740 }
2741
2742 if (copy_to_user(settings->ifs_ifsu.sync,
2743 &conf->phys_settings, size)) {
2744 return -EFAULT;
2745 }
2746 return 0;
2747 }
2748
2749 case IF_IFACE_V35:
2750 case IF_IFACE_V24:
2751 case IF_IFACE_X21:
2752 {
2753 const size_t size = sizeof(sync_serial_settings);
2754
2755 if (!capable(CAP_NET_ADMIN)) {
2756 return -EPERM;
2757 }
2758 /* incorrect data len? */
2759 if (ifr->ifr_settings.size != size) {
2760 return -ENOBUFS;
2761 }
2762
2763 if (copy_from_user(&conf->phys_settings,
2764 settings->ifs_ifsu.sync, size)) {
2765 return -EFAULT;
2766 }
2767
2768 if (conf->phys_settings.loopback) {
2769 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2770 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2771 MD2_LOOP_MIR);
2772 }
2773 conf->media = ifr->ifr_settings.type;
2774 return 0;
2775 }
2776
2777 case IF_IFACE_T1:
2778 case IF_IFACE_E1:
2779 {
2780 const size_t te_size = sizeof(te1_settings);
2781 const size_t size = sizeof(sync_serial_settings);
2782
2783 if (!capable(CAP_NET_ADMIN)) {
2784 return -EPERM;
2785 }
2786
2787 /* incorrect data len? */
2788 if (ifr->ifr_settings.size != te_size) {
2789 return -ENOBUFS;
2790 }
2791
2792 if (copy_from_user(&conf->phys_settings,
2793 settings->ifs_ifsu.te1, size)) {
2794 return -EFAULT;
2795 }/* Ignoring HDLC slot_map for a while */
2796
2797 if (conf->phys_settings.loopback) {
2798 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2799 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2800 MD2_LOOP_MIR);
2801 }
2802 conf->media = ifr->ifr_settings.type;
2803 return 0;
2804 }
2805 default:
2806 return hdlc_ioctl(dev, ifr, cmd);
2807 }
2808
2809 default:
2810 return hdlc_ioctl(dev, ifr, cmd);
2811 }
2812}
2813
b22267d3 2814static int clock_rate_calc(u32 rate, u32 clock, int *br_io)
1da177e4
LT		 2815{
2816 int br, tc;
2817 int br_pwr, error;
2818
79c63e19
JG		 2819 *br_io = 0;
2820
1da177e4 2821 if (rate == 0)
807540ba 2822 return 0;
1da177e4
LT		 2823
2824 for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2825 if ((tc = clock / br_pwr / rate) <= 0xff) {
2826 *br_io = br;
2827 break;
2828 }
2829 }
2830
2831 if (tc <= 0xff) {
2832 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2833 /* Errors bigger than +/- 1% won't be tolerated */
2834 if (error < -10 || error > 10)
807540ba 2835 return -1;
1da177e4 2836 else
807540ba 2837 return tc;
1da177e4 2838 } else {
807540ba 2839 return -1;
1da177e4
LT		 2840 }
2841}
2842
7665a089 2843static int ch_config(pc300dev_t * d)
1da177e4
LT		 2844{
2845 pc300ch_t *chan = (pc300ch_t *) d->chan;
2846 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2847 pc300_t *card = (pc300_t *) chan->card;
2848 void __iomem *scabase = card->hw.scabase;
2849 void __iomem *plxbase = card->hw.plxbase;
2850 int ch = chan->channel;
b22267d3
KH		 2851 u32 clkrate = chan->conf.phys_settings.clock_rate;
2852 u32 clktype = chan->conf.phys_settings.clock_type;
2853 u16 encoding = chan->conf.proto_settings.encoding;
2854 u16 parity = chan->conf.proto_settings.parity;
2855 u8 md0, md2;
2856
1da177e4
LT		 2857 /* Reset the channel */
2858 cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2859
2860 /* Configure the SCA registers */
2861 switch (parity) {
2862 case PARITY_NONE:
2863 md0 = MD0_BIT_SYNC;
2864 break;
2865 case PARITY_CRC16_PR0:
2866 md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2867 break;
2868 case PARITY_CRC16_PR1:
2869 md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2870 break;
2871 case PARITY_CRC32_PR1_CCITT:
2872 md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2873 break;
2874 case PARITY_CRC16_PR1_CCITT:
2875 default:
2876 md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2877 break;
2878 }
2879 switch (encoding) {
2880 case ENCODING_NRZI:
2881 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2882 break;
2883 case ENCODING_FM_MARK: /* FM1 */
2884 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2885 break;
2886 case ENCODING_FM_SPACE: /* FM0 */
2887 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2888 break;
2889 case ENCODING_MANCHESTER: /* It's not working... */
2890 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2891 break;
2892 case ENCODING_NRZ:
2893 default:
2894 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2895 break;
2896 }
2897 cpc_writeb(scabase + M_REG(MD0, ch), md0);
2898 cpc_writeb(scabase + M_REG(MD1, ch), 0);
2899 cpc_writeb(scabase + M_REG(MD2, ch), md2);
2900 cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2901 cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2902
2903 /* Configure HW media */
2904 switch (card->hw.type) {
2905 case PC300_RSV:
2906 if (conf->media == IF_IFACE_V35) {
2907 cpc_writel((plxbase + card->hw.gpioc_reg),
2908 cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2909 } else {
2910 cpc_writel((plxbase + card->hw.gpioc_reg),
2911 cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2912 }
2913 break;
2914
2915 case PC300_X21:
2916 break;
2917
2918 case PC300_TE:
2919 te_config(card, ch);
2920 break;
2921 }
2922
2923 switch (card->hw.type) {
2924 case PC300_RSV:
2925 case PC300_X21:
2926 if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
6f0f6d87
JG		 2927 int tmc, br;
2928
1da177e4
LT		 2929 /* Calculate the clkrate parameters */
2930 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
6f0f6d87
JG		 2931 if (tmc < 0)
2932 return -EIO;
1da177e4
LT		 2933 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2934 cpc_writeb(scabase + M_REG(TXS, ch),
2935 (TXS_DTRXC | TXS_IBRG | br));
2936 if (clktype == CLOCK_INT) {
2937 cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2938 cpc_writeb(scabase + M_REG(RXS, ch),
2939 (RXS_IBRG | br));
2940 } else {
2941 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2942 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2943 }
2944 if (card->hw.type == PC300_X21) {
2945 cpc_writeb(scabase + M_REG(GPO, ch), 1);
2946 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2947 } else {
2948 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2949 }
2950 } else {
2951 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2952 if (clktype == CLOCK_EXT) {
2953 cpc_writeb(scabase + M_REG(TXS, ch),
2954 TXS_DTRXC);
2955 } else {
2956 cpc_writeb(scabase + M_REG(TXS, ch),
2957 TXS_DTRXC|TXS_RCLK);
2958 }
2959 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2960 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2961 if (card->hw.type == PC300_X21) {
2962 cpc_writeb(scabase + M_REG(GPO, ch), 0);
2963 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2964 } else {
2965 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2966 }
2967 }
2968 break;
2969
2970 case PC300_TE:
2971 /* SCA always receives clock from the FALC chip */
2972 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2973 cpc_writeb(scabase + M_REG(TXS, ch), 0);
2974 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2975 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2976 cpc_writeb(scabase + M_REG(EXS, ch), 0);
2977 break;
2978 }
2979
2980 /* Enable Interrupts */
2981 cpc_writel(scabase + IER0,
2982 cpc_readl(scabase + IER0) |
2983 IR0_M(IR0_RXINTA, ch) |
2984 IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2985 IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
2986 cpc_writeb(scabase + M_REG(IE0, ch),
2987 cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
2988 cpc_writeb(scabase + M_REG(IE1, ch),
2989 cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
2990
2991 return 0;
2992}
2993
7665a089 2994static int rx_config(pc300dev_t * d)
1da177e4
LT		 2995{
2996 pc300ch_t *chan = (pc300ch_t *) d->chan;
2997 pc300_t *card = (pc300_t *) chan->card;
2998 void __iomem *scabase = card->hw.scabase;
2999 int ch = chan->channel;
3000
3001 cpc_writeb(scabase + DSR_RX(ch), 0);
3002
3003 /* General RX settings */
3004 cpc_writeb(scabase + M_REG(RRC, ch), 0);
3005 cpc_writeb(scabase + M_REG(RNR, ch), 16);
3006
3007 /* Enable reception */
3008 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3009 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3010
3011 /* Initialize DMA stuff */
3012 chan->rx_first_bd = 0;
3013 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3014 rx_dma_buf_init(card, ch);
3015 cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3016 cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3017 cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3018
3019 /* Start DMA */
3020 rx_dma_start(card, ch);
3021
3022 return 0;
3023}
3024
7665a089 3025static int tx_config(pc300dev_t * d)
1da177e4
LT		 3026{
3027 pc300ch_t *chan = (pc300ch_t *) d->chan;
3028 pc300_t *card = (pc300_t *) chan->card;
3029 void __iomem *scabase = card->hw.scabase;
3030 int ch = chan->channel;
3031
3032 cpc_writeb(scabase + DSR_TX(ch), 0);
3033
3034 /* General TX settings */
3035 cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3036 cpc_writeb(scabase + M_REG(TFS, ch), 32);
3037 cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3038 cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3039 cpc_writeb(scabase + M_REG(TCR, ch), 8);
3040
3041 /* Enable transmission */
3042 cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3043
3044 /* Initialize DMA stuff */
3045 chan->tx_first_bd = 0;
3046 chan->tx_next_bd = 0;
3047 tx_dma_buf_init(card, ch);
3048 cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3049 cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3050 cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3051 cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3052 cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3053
3054 return 0;
3055}
3056
3057static int cpc_attach(struct net_device *dev, unsigned short encoding,
3058 unsigned short parity)
3059{
6636e117 3060 pc300dev_t *d = (pc300dev_t *)dev_to_hdlc(dev)->priv;
1da177e4
LT		 3061 pc300ch_t *chan = (pc300ch_t *)d->chan;
3062 pc300_t *card = (pc300_t *)chan->card;
3063 pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3064
3065 if (card->hw.type == PC300_TE) {
3066 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3067 return -EINVAL;
3068 }
3069 } else {
3070 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3071 encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3072 /* Driver doesn't support ENCODING_MANCHESTER yet */
3073 return -EINVAL;
3074 }
3075 }
3076
3077 if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3078 parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3079 parity != PARITY_CRC16_PR1_CCITT) {
3080 return -EINVAL;
3081 }
3082
3083 conf->proto_settings.encoding = encoding;
3084 conf->proto_settings.parity = parity;
3085 return 0;
3086}
3087
6f0f6d87 3088static int cpc_opench(pc300dev_t * d)
1da177e4
LT		 3089{
3090 pc300ch_t *chan = (pc300ch_t *) d->chan;
3091 pc300_t *card = (pc300_t *) chan->card;
6f0f6d87 3092 int ch = chan->channel, rc;
1da177e4
LT		 3093 void __iomem *scabase = card->hw.scabase;
3094
6f0f6d87
JG		 3095 rc = ch_config(d);
3096 if (rc)
3097 return rc;
1da177e4
LT		 3098
3099 rx_config(d);
3100
3101 tx_config(d);
3102
3103 /* Assert RTS and DTR */
3104 cpc_writeb(scabase + M_REG(CTL, ch),
3105 cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
6f0f6d87
JG		 3106
3107 return 0;
1da177e4
LT		 3108}
3109
7665a089 3110static void cpc_closech(pc300dev_t * d)
1da177e4
LT		 3111{
3112 pc300ch_t *chan = (pc300ch_t *) d->chan;
3113 pc300_t *card = (pc300_t *) chan->card;
3114 falc_t *pfalc = (falc_t *) & chan->falc;
3115 int ch = chan->channel;
3116
3117 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3118 rx_dma_stop(card, ch);
3119 tx_dma_stop(card, ch);
3120
3121 if (card->hw.type == PC300_TE) {
3122 memset(pfalc, 0, sizeof(falc_t));
3123 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3124 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3125 ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3126 CPLD_REG2_FALC_LED2) << (2 * ch)));
3127 /* Reset the FALC chip */
3128 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3129 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3130 (CPLD_REG1_FALC_RESET << (2 * ch)));
3131 udelay(10000);
3132 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3133 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3134 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3135 }
3136}
3137
3138int cpc_open(struct net_device *dev)
3139{
6636e117 3140 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1da177e4
LT		 3141 struct ifreq ifr;
3142 int result;
3143
3144#ifdef PC300_DEBUG_OTHER
3145 printk("pc300: cpc_open");
3146#endif
3147
1da177e4 3148 result = hdlc_open(dev);
ea966165
KH		 3149
3150 if (result)
1da177e4 3151 return result;
1da177e4
LT		 3152
3153 sprintf(ifr.ifr_name, "%s", dev->name);
6f0f6d87
JG		 3154 result = cpc_opench(d);
3155 if (result)
3156 goto err_out;
3157
1da177e4
LT		 3158 netif_start_queue(dev);
3159 return 0;
6f0f6d87
JG		 3160
3161err_out:
3162 hdlc_close(dev);
3163 return result;
1da177e4
LT		 3164}
3165
7665a089 3166static int cpc_close(struct net_device *dev)
1da177e4 3167{
6636e117 3168 pc300dev_t *d = (pc300dev_t *) dev_to_hdlc(dev)->priv;
1da177e4
LT		 3169 pc300ch_t *chan = (pc300ch_t *) d->chan;
3170 pc300_t *card = (pc300_t *) chan->card;
3171 unsigned long flags;
3172
3173#ifdef PC300_DEBUG_OTHER
3174 printk("pc300: cpc_close");
3175#endif
3176
3177 netif_stop_queue(dev);
3178
3179 CPC_LOCK(card, flags);
3180 cpc_closech(d);
3181 CPC_UNLOCK(card, flags);
3182
3183 hdlc_close(dev);
ea966165 3184
1da177e4
LT		 3185#ifdef CONFIG_PC300_MLPPP
3186 if (chan->conf.proto == PC300_PROTO_MLPPP) {
3187 cpc_tty_unregister_service(d);
3188 chan->conf.proto = 0xffff;
3189 }
3190#endif
3191
3192 return 0;
3193}
3194
b22267d3 3195static u32 detect_ram(pc300_t * card)
1da177e4 3196{
b22267d3
KH		 3197 u32 i;
3198 u8 data;
1da177e4
LT		 3199 void __iomem *rambase = card->hw.rambase;
3200
3201 card->hw.ramsize = PC300_RAMSIZE;
3202 /* Let's find out how much RAM is present on this board */
3203 for (i = 0; i < card->hw.ramsize; i++) {
b22267d3 3204 data = (u8)(i & 0xff);
1da177e4
LT		 3205 cpc_writeb(rambase + i, data);
3206 if (cpc_readb(rambase + i) != data) {
3207 break;
3208 }
3209 }
807540ba 3210 return i;
1da177e4
LT		 3211}
3212
3213static void plx_init(pc300_t * card)
3214{
3215 struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3216
3217 /* Reset PLX */
3218 cpc_writel(&plx_ctl->init_ctrl,
3219 cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3220 udelay(10000L);
3221 cpc_writel(&plx_ctl->init_ctrl,
3222 cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3223
3224 /* Reload Config. Registers from EEPROM */
3225 cpc_writel(&plx_ctl->init_ctrl,
3226 cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3227 udelay(10000L);
3228 cpc_writel(&plx_ctl->init_ctrl,
3229 cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3230
3231}
3232
3233static inline void show_version(void)
3234{
3235 char *rcsvers, *rcsdate, *tmp;
3236
3237 rcsvers = strchr(rcsid, ' ');
3238 rcsvers++;
3239 tmp = strchr(rcsvers, ' ');
3240 *tmp++ = '\0';
3241 rcsdate = strchr(tmp, ' ');
3242 rcsdate++;
3243 tmp = strrchr(rcsdate, ' ');
3244 *tmp = '\0';
3245 printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n",
3246 rcsvers, rcsdate, __DATE__, __TIME__);
3247} /* show_version */
3248
d32da050
AB		 3249static const struct net_device_ops cpc_netdev_ops = {
3250 .ndo_open = cpc_open,
3251 .ndo_stop = cpc_close,
3252 .ndo_tx_timeout = cpc_tx_timeout,
3253 .ndo_set_mac_address = NULL,
3254 .ndo_change_mtu = cpc_change_mtu,
3255 .ndo_do_ioctl = cpc_ioctl,
3256 .ndo_validate_addr = eth_validate_addr,
3257};
3258
1da177e4
LT		 3259static void cpc_init_card(pc300_t * card)
3260{
3261 int i, devcount = 0;
3262 static int board_nbr = 1;
3263
3264 /* Enable interrupts on the PCI bridge */
3265 plx_init(card);
3266 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3267 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3268
3269#ifdef USE_PCI_CLOCK
3270 /* Set board clock to PCI clock */
3271 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3272 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3273 card->hw.clock = PC300_PCI_CLOCK;
3274#else
3275 /* Set board clock to internal oscillator clock */
3276 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3277 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3278 card->hw.clock = PC300_OSC_CLOCK;
3279#endif
3280
3281 /* Detect actual on-board RAM size */
3282 card->hw.ramsize = detect_ram(card);
3283
3284 /* Set Global SCA-II registers */
3285 cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3286 cpc_writeb(card->hw.scabase + BTCR, 0x10);
3287 cpc_writeb(card->hw.scabase + WCRL, 0);
3288 cpc_writeb(card->hw.scabase + DMER, 0x80);
3289
3290 if (card->hw.type == PC300_TE) {
b22267d3 3291 u8 reg1;
1da177e4
LT		 3292
3293 /* Check CPLD version */
3294 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3295 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3296 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3297 /* New CPLD */
3298 card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3299 card->hw.cpld_reg1 = CPLD_V2_REG1;
3300 card->hw.cpld_reg2 = CPLD_V2_REG2;
3301 } else {
3302 /* old CPLD */
3303 card->hw.cpld_id = 0;
3304 card->hw.cpld_reg1 = CPLD_REG1;
3305 card->hw.cpld_reg2 = CPLD_REG2;
3306 cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3307 }
3308
3309 /* Enable the board's global clock */
3310 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3311 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3312 CPLD_REG1_GLOBAL_CLK);
3313
3314 }
3315
3316 for (i = 0; i < card->hw.nchan; i++) {
3317 pc300ch_t *chan = &card->chan[i];
3318 pc300dev_t *d = &chan->d;
3319 hdlc_device *hdlc;
3320 struct net_device *dev;
3321
3322 chan->card = card;
3323 chan->channel = i;
3324 chan->conf.phys_settings.clock_rate = 0;
3325 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3326 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3327 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3328 switch (card->hw.type) {
3329 case PC300_TE:
3330 chan->conf.media = IF_IFACE_T1;
3331 chan->conf.lcode = PC300_LC_B8ZS;
3332 chan->conf.fr_mode = PC300_FR_ESF;
3333 chan->conf.lbo = PC300_LBO_0_DB;
3334 chan->conf.rx_sens = PC300_RX_SENS_SH;
3335 chan->conf.tslot_bitmap = 0xffffffffUL;
3336 break;
3337
3338 case PC300_X21:
3339 chan->conf.media = IF_IFACE_X21;
3340 break;
3341
3342 case PC300_RSV:
3343 default:
3344 chan->conf.media = IF_IFACE_V35;
3345 break;
3346 }
3347 chan->conf.proto = IF_PROTO_PPP;
3348 chan->tx_first_bd = 0;
3349 chan->tx_next_bd = 0;
3350 chan->rx_first_bd = 0;
3351 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3352 chan->nfree_tx_bd = N_DMA_TX_BUF;
3353
3354 d->chan = chan;
1da177e4
LT		 3355 d->trace_on = 0;
3356 d->line_on = 0;
3357 d->line_off = 0;
3358
6636e117 3359 dev = alloc_hdlcdev(d);
1da177e4
LT		 3360 if (dev == NULL)
3361 continue;
3362
3363 hdlc = dev_to_hdlc(dev);
3364 hdlc->xmit = cpc_queue_xmit;
3365 hdlc->attach = cpc_attach;
3366 d->dev = dev;
3367 dev->mem_start = card->hw.ramphys;
3368 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3369 dev->irq = card->hw.irq;
1da177e4
LT		 3370 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3371 dev->mtu = PC300_DEF_MTU;
3372
d32da050 3373 dev->netdev_ops = &cpc_netdev_ops;
1da177e4 3374 dev->watchdog_timeo = PC300_TX_TIMEOUT;
1da177e4
LT		 3375
3376 if (register_hdlc_device(dev) == 0) {
1da177e4
LT		 3377 printk("%s: Cyclades-PC300/", dev->name);
3378 switch (card->hw.type) {
3379 case PC300_TE:
3380 if (card->hw.bus == PC300_PMC) {
3381 printk("TE-M");
3382 } else {
3383 printk("TE ");
3384 }
3385 break;
3386
3387 case PC300_X21:
3388 printk("X21 ");
3389 break;
3390
3391 case PC300_RSV:
3392 default:
3393 printk("RSV ");
3394 break;
3395 }
3396 printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3397 board_nbr, card->hw.ramsize / 1024,
3398 card->hw.ramphys, card->hw.irq, i + 1);
3399 devcount++;
3400 } else {
3401 printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3402 i + 1, card->hw.ramphys);
3403 free_netdev(dev);
3404 continue;
3405 }
3406 }
3407 spin_lock_init(&card->card_lock);
3408
3409 board_nbr++;
3410}
3411
3412static int __devinit
3413cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3414{
3415 static int first_time = 1;
e8108c98 3416 int err, eeprom_outdated = 0;
b22267d3 3417 u16 device_id;
1da177e4
LT		 3418 pc300_t *card;
3419
3420 if (first_time) {
3421 first_time = 0;
3422 show_version();
3423#ifdef CONFIG_PC300_MLPPP
3424 cpc_tty_reset_var();
3425#endif
3426 }
3427
e8108c98
MT		 3428 if ((err = pci_enable_device(pdev)) < 0)
3429 return err;
3430
dd00cc48 3431 card = kzalloc(sizeof(pc300_t), GFP_KERNEL);
1da177e4 3432 if (card == NULL) {
7c7459d1 3433 printk("PC300 found at RAM 0x%016llx, "
1da177e4 3434 "but could not allocate card structure.\n",
7c7459d1 3435 (unsigned long long)pci_resource_start(pdev, 3));
e8108c98
MT		 3436 err = -ENOMEM;
3437 goto err_disable_dev;
1da177e4 3438 }
1da177e4 3439
e8108c98
MT		 3440 err = -ENODEV;
3441
1da177e4
LT		 3442 /* read PCI configuration area */
3443 device_id = ent->device;
3444 card->hw.irq = pdev->irq;
3445 card->hw.iophys = pci_resource_start(pdev, 1);
3446 card->hw.iosize = pci_resource_len(pdev, 1);
3447 card->hw.scaphys = pci_resource_start(pdev, 2);
3448 card->hw.scasize = pci_resource_len(pdev, 2);
3449 card->hw.ramphys = pci_resource_start(pdev, 3);
3450 card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3451 card->hw.falcphys = pci_resource_start(pdev, 4);
3452 card->hw.falcsize = pci_resource_len(pdev, 4);
3453 card->hw.plxphys = pci_resource_start(pdev, 5);
3454 card->hw.plxsize = pci_resource_len(pdev, 5);
1da177e4
LT		 3455
3456 switch (device_id) {
3457 case PCI_DEVICE_ID_PC300_RX_1:
3458 case PCI_DEVICE_ID_PC300_TE_1:
3459 case PCI_DEVICE_ID_PC300_TE_M_1:
3460 card->hw.nchan = 1;
3461 break;
3462
3463 case PCI_DEVICE_ID_PC300_RX_2:
3464 case PCI_DEVICE_ID_PC300_TE_2:
3465 case PCI_DEVICE_ID_PC300_TE_M_2:
3466 default:
3467 card->hw.nchan = PC300_MAXCHAN;
3468 break;
3469 }
3470#ifdef PC300_DEBUG_PCI
3471 printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
44c10138 3472 printk("rev_id=%d) IRQ%d\n", pdev->revision, card->hw.irq);
1da177e4
LT		 3473 printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
3474 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3475 card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3476 card->hw.falcphys);
3477#endif
3478 /* Although we don't use this I/O region, we should
3479 * request it from the kernel anyway, to avoid problems
3480 * with other drivers accessing it. */
3481 if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3482 /* In case we can't allocate it, warn user */
3483 printk("WARNING: couldn't allocate I/O region for PC300 board "
3484 "at 0x%08x!\n", card->hw.ramphys);
3485 }
3486
3487 if (card->hw.plxphys) {
3488 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3489 } else {
3490 eeprom_outdated = 1;
3491 card->hw.plxphys = pci_resource_start(pdev, 0);
3492 card->hw.plxsize = pci_resource_len(pdev, 0);
3493 }
3494
3495 if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3496 "PLX Registers")) {
3497 printk("PC300 found at RAM 0x%08x, "
3498 "but could not allocate PLX mem region.\n",
3499 card->hw.ramphys);
1da177e4
LT		 3500 goto err_release_io;
3501 }
3502 if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3503 "On-board RAM")) {
3504 printk("PC300 found at RAM 0x%08x, "
3505 "but could not allocate RAM mem region.\n",
3506 card->hw.ramphys);
1da177e4
LT		 3507 goto err_release_plx;
3508 }
3509 if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3510 "SCA-II Registers")) {
3511 printk("PC300 found at RAM 0x%08x, "
3512 "but could not allocate SCA mem region.\n",
3513 card->hw.ramphys);
1da177e4
LT		 3514 goto err_release_ram;
3515 }
3516
1da177e4
LT		 3517 card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3518 card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3519 card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3520 switch (device_id) {
3521 case PCI_DEVICE_ID_PC300_TE_1:
3522 case PCI_DEVICE_ID_PC300_TE_2:
3523 case PCI_DEVICE_ID_PC300_TE_M_1:
3524 case PCI_DEVICE_ID_PC300_TE_M_2:
3525 request_mem_region(card->hw.falcphys, card->hw.falcsize,
3526 "FALC Registers");
3527 card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3528 break;
3529
3530 case PCI_DEVICE_ID_PC300_RX_1:
3531 case PCI_DEVICE_ID_PC300_RX_2:
3532 default:
3533 card->hw.falcbase = NULL;
3534 break;
3535 }
3536
3537#ifdef PC300_DEBUG_PCI
3538 printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3539 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3540 card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3541 card->hw.falcbase);
3542#endif
3543
3544 /* Set PCI drv pointer to the card structure */
3545 pci_set_drvdata(pdev, card);
3546
3547 /* Set board type */
3548 switch (device_id) {
3549 case PCI_DEVICE_ID_PC300_TE_1:
3550 case PCI_DEVICE_ID_PC300_TE_2:
3551 case PCI_DEVICE_ID_PC300_TE_M_1:
3552 case PCI_DEVICE_ID_PC300_TE_M_2:
3553 card->hw.type = PC300_TE;
3554
3555 if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3556 (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3557 card->hw.bus = PC300_PMC;
3558 /* Set PLX register offsets */
3559 card->hw.gpioc_reg = 0x54;
3560 card->hw.intctl_reg = 0x4c;
3561 } else {
3562 card->hw.bus = PC300_PCI;
3563 /* Set PLX register offsets */
3564 card->hw.gpioc_reg = 0x50;
3565 card->hw.intctl_reg = 0x4c;
3566 }
3567 break;
3568
3569 case PCI_DEVICE_ID_PC300_RX_1:
3570 case PCI_DEVICE_ID_PC300_RX_2:
3571 default:
3572 card->hw.bus = PC300_PCI;
3573 /* Set PLX register offsets */
3574 card->hw.gpioc_reg = 0x50;
3575 card->hw.intctl_reg = 0x4c;
3576
3577 if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3578 card->hw.type = PC300_X21;
3579 } else {
3580 card->hw.type = PC300_RSV;
3581 }
3582 break;
3583 }
3584
3585 /* Allocate IRQ */
1fb9df5d 3586 if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
1da177e4
LT		 3587 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3588 card->hw.ramphys, card->hw.irq);
3589 goto err_io_unmap;
3590 }
3591
3592 cpc_init_card(card);
3593
3594 if (eeprom_outdated)
3595 printk("WARNING: PC300 with outdated EEPROM.\n");
3596 return 0;
3597
3598err_io_unmap:
3599 iounmap(card->hw.plxbase);
3600 iounmap(card->hw.scabase);
3601 iounmap(card->hw.rambase);
3602 if (card->hw.type == PC300_TE) {
3603 iounmap(card->hw.falcbase);
3604 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3605 }
1da177e4
LT		 3606 release_mem_region(card->hw.scaphys, card->hw.scasize);
3607err_release_ram:
3608 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3609err_release_plx:
3610 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3611err_release_io:
3612 release_region(card->hw.iophys, card->hw.iosize);
3613 kfree(card);
e8108c98
MT		 3614err_disable_dev:
3615 pci_disable_device(pdev);
3616 return err;
1da177e4
LT		 3617}
3618
3619static void __devexit cpc_remove_one(struct pci_dev *pdev)
3620{
3621 pc300_t *card = pci_get_drvdata(pdev);
3622
79ea13ce 3623 if (card->hw.rambase) {
1da177e4
LT		 3624 int i;
3625
3626 /* Disable interrupts on the PCI bridge */
3627 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3628 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3629
3630 for (i = 0; i < card->hw.nchan; i++) {
3631 unregister_hdlc_device(card->chan[i].d.dev);
3632 }
3633 iounmap(card->hw.plxbase);
3634 iounmap(card->hw.scabase);
3635 iounmap(card->hw.rambase);
3636 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3637 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3638 release_mem_region(card->hw.scaphys, card->hw.scasize);
3639 release_region(card->hw.iophys, card->hw.iosize);
3640 if (card->hw.type == PC300_TE) {
3641 iounmap(card->hw.falcbase);
3642 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3643 }
3644 for (i = 0; i < card->hw.nchan; i++)
3645 if (card->chan[i].d.dev)
3646 free_netdev(card->chan[i].d.dev);
3647 if (card->hw.irq)
3648 free_irq(card->hw.irq, card);
3649 kfree(card);
e8108c98 3650 pci_disable_device(pdev);
1da177e4
LT		 3651 }
3652}
3653
3654static struct pci_driver cpc_driver = {
3655 .name = "pc300",
3656 .id_table = cpc_pci_dev_id,
3657 .probe = cpc_init_one,
3658 .remove = __devexit_p(cpc_remove_one),
3659};
3660
3661static int __init cpc_init(void)
3662{
29917620 3663 return pci_register_driver(&cpc_driver);
1da177e4
LT		 3664}
3665
3666static void __exit cpc_cleanup_module(void)
3667{
3668 pci_unregister_driver(&cpc_driver);
3669}
3670
3671module_init(cpc_init);
3672module_exit(cpc_cleanup_module);
3673
3674MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3675MODULE_AUTHOR( "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3676 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3677MODULE_LICENSE("GPL");
3678
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