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vxge: Fix starvation of receive ring controller when blasted by short packets.
[net-next-2.6.git] / drivers / net / vxge / vxge-config.c
CommitLineData
40a3a915
RV		 1/******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
9 *
10 * vxge-config.c: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O
11 * Virtualized Server Adapter.
12 * Copyright(c) 2002-2009 Neterion Inc.
13 ******************************************************************************/
14#include <linux/vmalloc.h>
15#include <linux/etherdevice.h>
16#include <linux/pci.h>
17#include <linux/pci_hotplug.h>
18
19#include "vxge-traffic.h"
20#include "vxge-config.h"
21
22/*
23 * __vxge_hw_channel_allocate - Allocate memory for channel
24 * This function allocates required memory for the channel and various arrays
25 * in the channel
26 */
27struct __vxge_hw_channel*
28__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
29 enum __vxge_hw_channel_type type,
30 u32 length, u32 per_dtr_space, void *userdata)
31{
32 struct __vxge_hw_channel *channel;
33 struct __vxge_hw_device *hldev;
34 int size = 0;
35 u32 vp_id;
36
37 hldev = vph->vpath->hldev;
38 vp_id = vph->vpath->vp_id;
39
40 switch (type) {
41 case VXGE_HW_CHANNEL_TYPE_FIFO:
42 size = sizeof(struct __vxge_hw_fifo);
43 break;
44 case VXGE_HW_CHANNEL_TYPE_RING:
45 size = sizeof(struct __vxge_hw_ring);
46 break;
47 default:
48 break;
49 }
50
51 channel = kzalloc(size, GFP_KERNEL);
52 if (channel == NULL)
53 goto exit0;
54 INIT_LIST_HEAD(&channel->item);
55
56 channel->common_reg = hldev->common_reg;
57 channel->first_vp_id = hldev->first_vp_id;
58 channel->type = type;
59 channel->devh = hldev;
60 channel->vph = vph;
61 channel->userdata = userdata;
62 channel->per_dtr_space = per_dtr_space;
63 channel->length = length;
64 channel->vp_id = vp_id;
65
66 channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
67 if (channel->work_arr == NULL)
68 goto exit1;
69
70 channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
71 if (channel->free_arr == NULL)
72 goto exit1;
73 channel->free_ptr = length;
74
75 channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
76 if (channel->reserve_arr == NULL)
77 goto exit1;
78 channel->reserve_ptr = length;
79 channel->reserve_top = 0;
80
81 channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
82 if (channel->orig_arr == NULL)
83 goto exit1;
84
85 return channel;
86exit1:
87 __vxge_hw_channel_free(channel);
88
89exit0:
90 return NULL;
91}
92
93/*
94 * __vxge_hw_channel_free - Free memory allocated for channel
95 * This function deallocates memory from the channel and various arrays
96 * in the channel
97 */
98void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
99{
100 kfree(channel->work_arr);
101 kfree(channel->free_arr);
102 kfree(channel->reserve_arr);
103 kfree(channel->orig_arr);
104 kfree(channel);
105}
106
107/*
108 * __vxge_hw_channel_initialize - Initialize a channel
109 * This function initializes a channel by properly setting the
110 * various references
111 */
112enum vxge_hw_status
113__vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
114{
115 u32 i;
116 struct __vxge_hw_virtualpath *vpath;
117
118 vpath = channel->vph->vpath;
119
120 if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
121 for (i = 0; i < channel->length; i++)
122 channel->orig_arr[i] = channel->reserve_arr[i];
123 }
124
125 switch (channel->type) {
126 case VXGE_HW_CHANNEL_TYPE_FIFO:
127 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
128 channel->stats = &((struct __vxge_hw_fifo *)
129 channel)->stats->common_stats;
130 break;
131 case VXGE_HW_CHANNEL_TYPE_RING:
132 vpath->ringh = (struct __vxge_hw_ring *)channel;
133 channel->stats = &((struct __vxge_hw_ring *)
134 channel)->stats->common_stats;
135 break;
136 default:
137 break;
138 }
139
140 return VXGE_HW_OK;
141}
142
143/*
144 * __vxge_hw_channel_reset - Resets a channel
145 * This function resets a channel by properly setting the various references
146 */
147enum vxge_hw_status
148__vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
149{
150 u32 i;
151
152 for (i = 0; i < channel->length; i++) {
153 if (channel->reserve_arr != NULL)
154 channel->reserve_arr[i] = channel->orig_arr[i];
155 if (channel->free_arr != NULL)
156 channel->free_arr[i] = NULL;
157 if (channel->work_arr != NULL)
158 channel->work_arr[i] = NULL;
159 }
160 channel->free_ptr = channel->length;
161 channel->reserve_ptr = channel->length;
162 channel->reserve_top = 0;
163 channel->post_index = 0;
164 channel->compl_index = 0;
165
166 return VXGE_HW_OK;
167}
168
169/*
170 * __vxge_hw_device_pci_e_init
171 * Initialize certain PCI/PCI-X configuration registers
172 * with recommended values. Save config space for future hw resets.
173 */
174void
175__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
176{
177 u16 cmd = 0;
178
179 /* Set the PErr Repconse bit and SERR in PCI command register. */
180 pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
181 cmd |= 0x140;
182 pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
183
184 pci_save_state(hldev->pdev);
185
186 return;
187}
188
189/*
190 * __vxge_hw_device_register_poll
191 * Will poll certain register for specified amount of time.
192 * Will poll until masked bit is not cleared.
193 */
194enum vxge_hw_status
195__vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
196{
197 u64 val64;
198 u32 i = 0;
199 enum vxge_hw_status ret = VXGE_HW_FAIL;
200
201 udelay(10);
202
203 do {
204 val64 = readq(reg);
205 if (!(val64 & mask))
206 return VXGE_HW_OK;
207 udelay(100);
208 } while (++i <= 9);
209
210 i = 0;
211 do {
212 val64 = readq(reg);
213 if (!(val64 & mask))
214 return VXGE_HW_OK;
215 mdelay(1);
216 } while (++i <= max_millis);
217
218 return ret;
219}
220
221 /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
222 * in progress
223 * This routine checks the vpath reset in progress register is turned zero
224 */
225enum vxge_hw_status
226__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
227{
228 enum vxge_hw_status status;
229 status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
230 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
231 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
232 return status;
233}
234
235/*
236 * __vxge_hw_device_toc_get
237 * This routine sets the swapper and reads the toc pointer and returns the
238 * memory mapped address of the toc
239 */
240struct vxge_hw_toc_reg __iomem *
241__vxge_hw_device_toc_get(void __iomem *bar0)
242{
243 u64 val64;
244 struct vxge_hw_toc_reg __iomem *toc = NULL;
245 enum vxge_hw_status status;
246
247 struct vxge_hw_legacy_reg __iomem *legacy_reg =
248 (struct vxge_hw_legacy_reg __iomem *)bar0;
249
250 status = __vxge_hw_legacy_swapper_set(legacy_reg);
251 if (status != VXGE_HW_OK)
252 goto exit;
253
254 val64 = readq(&legacy_reg->toc_first_pointer);
255 toc = (struct vxge_hw_toc_reg __iomem *)(bar0+val64);
256exit:
257 return toc;
258}
259
260/*
261 * __vxge_hw_device_reg_addr_get
262 * This routine sets the swapper and reads the toc pointer and initializes the
263 * register location pointers in the device object. It waits until the ric is
264 * completed initializing registers.
265 */
266enum vxge_hw_status
267__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
268{
269 u64 val64;
270 u32 i;
271 enum vxge_hw_status status = VXGE_HW_OK;
272
273 hldev->legacy_reg = (struct vxge_hw_legacy_reg __iomem *)hldev->bar0;
274
275 hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
276 if (hldev->toc_reg == NULL) {
277 status = VXGE_HW_FAIL;
278 goto exit;
279 }
280
281 val64 = readq(&hldev->toc_reg->toc_common_pointer);
282 hldev->common_reg =
283 (struct vxge_hw_common_reg __iomem *)(hldev->bar0 + val64);
284
285 val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
286 hldev->mrpcim_reg =
287 (struct vxge_hw_mrpcim_reg __iomem *)(hldev->bar0 + val64);
288
289 for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
290 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
291 hldev->srpcim_reg[i] =
292 (struct vxge_hw_srpcim_reg __iomem *)
293 (hldev->bar0 + val64);
294 }
295
296 for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
297 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
298 hldev->vpmgmt_reg[i] =
299 (struct vxge_hw_vpmgmt_reg __iomem *)(hldev->bar0 + val64);
300 }
301
302 for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
303 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
304 hldev->vpath_reg[i] =
305 (struct vxge_hw_vpath_reg __iomem *)
306 (hldev->bar0 + val64);
307 }
308
309 val64 = readq(&hldev->toc_reg->toc_kdfc);
310
311 switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
312 case 0:
313 hldev->kdfc = (u8 __iomem *)(hldev->bar0 +
314 VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64));
315 break;
40a3a915
RV		 316 default:
317 break;
318 }
319
320 status = __vxge_hw_device_vpath_reset_in_prog_check(
321 (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
322exit:
323 return status;
324}
325
326/*
327 * __vxge_hw_device_id_get
328 * This routine returns sets the device id and revision numbers into the device
329 * structure
330 */
331void __vxge_hw_device_id_get(struct __vxge_hw_device *hldev)
332{
333 u64 val64;
334
335 val64 = readq(&hldev->common_reg->titan_asic_id);
336 hldev->device_id =
337 (u16)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(val64);
338
339 hldev->major_revision =
340 (u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(val64);
341
342 hldev->minor_revision =
343 (u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(val64);
344
345 return;
346}
347
348/*
349 * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
350 * This routine returns the Access Rights of the driver
351 */
352static u32
353__vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
354{
355 u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
356
357 switch (host_type) {
358 case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
92cdd7c3
SH		 359 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
360 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
40a3a915
RV		 361 break;
362 case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
363 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
364 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
365 break;
366 case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
367 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
368 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
369 break;
370 case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
371 case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
372 case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
373 break;
374 case VXGE_HW_SR_VH_FUNCTION0:
375 case VXGE_HW_VH_NORMAL_FUNCTION:
376 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
377 break;
378 }
379
380 return access_rights;
381}
92cdd7c3
SH		 382/*
383 * __vxge_hw_device_is_privilaged
384 * This routine checks if the device function is privilaged or not
385 */
386
387enum vxge_hw_status
388__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
389{
390 if (__vxge_hw_device_access_rights_get(host_type,
391 func_id) &
392 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
393 return VXGE_HW_OK;
394 else
395 return VXGE_HW_ERR_PRIVILAGED_OPEARATION;
396}
397
40a3a915
RV		 398/*
399 * __vxge_hw_device_host_info_get
400 * This routine returns the host type assignments
401 */
402void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
403{
404 u64 val64;
405 u32 i;
406
407 val64 = readq(&hldev->common_reg->host_type_assignments);
408
409 hldev->host_type =
410 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
411
412 hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
413
414 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
415
416 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
417 continue;
418
419 hldev->func_id =
420 __vxge_hw_vpath_func_id_get(i, hldev->vpmgmt_reg[i]);
421
422 hldev->access_rights = __vxge_hw_device_access_rights_get(
423 hldev->host_type, hldev->func_id);
424
425 hldev->first_vp_id = i;
426 break;
427 }
428
429 return;
430}
431
432/*
433 * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
434 * link width and signalling rate.
435 */
436static enum vxge_hw_status
437__vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
438{
439 int exp_cap;
440 u16 lnk;
441
442 /* Get the negotiated link width and speed from PCI config space */
443 exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
444 pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
445
446 if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
447 return VXGE_HW_ERR_INVALID_PCI_INFO;
448
449 switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
450 case PCIE_LNK_WIDTH_RESRV:
451 case PCIE_LNK_X1:
452 case PCIE_LNK_X2:
453 case PCIE_LNK_X4:
454 case PCIE_LNK_X8:
455 break;
456 default:
457 return VXGE_HW_ERR_INVALID_PCI_INFO;
458 }
459
460 return VXGE_HW_OK;
461}
462
40a3a915
RV		 463/*
464 * __vxge_hw_device_initialize
465 * Initialize Titan-V hardware.
466 */
467enum vxge_hw_status __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
468{
469 enum vxge_hw_status status = VXGE_HW_OK;
470
92cdd7c3
SH		 471 if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
472 hldev->func_id)) {
5dbc9011
SS		 473 /* Validate the pci-e link width and speed */
474 status = __vxge_hw_verify_pci_e_info(hldev);
475 if (status != VXGE_HW_OK)
476 goto exit;
477 }
40a3a915 478
40a3a915
RV		 479exit:
480 return status;
481}
482
483/**
484 * vxge_hw_device_hw_info_get - Get the hw information
485 * Returns the vpath mask that has the bits set for each vpath allocated
486 * for the driver, FW version information and the first mac addresse for
487 * each vpath
488 */
489enum vxge_hw_status __devinit
490vxge_hw_device_hw_info_get(void __iomem *bar0,
491 struct vxge_hw_device_hw_info *hw_info)
492{
493 u32 i;
494 u64 val64;
495 struct vxge_hw_toc_reg __iomem *toc;
496 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
497 struct vxge_hw_common_reg __iomem *common_reg;
498 struct vxge_hw_vpath_reg __iomem *vpath_reg;
499 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
500 enum vxge_hw_status status;
501
502 memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
503
504 toc = __vxge_hw_device_toc_get(bar0);
505 if (toc == NULL) {
506 status = VXGE_HW_ERR_CRITICAL;
507 goto exit;
508 }
509
510 val64 = readq(&toc->toc_common_pointer);
511 common_reg = (struct vxge_hw_common_reg __iomem *)(bar0 + val64);
512
513 status = __vxge_hw_device_vpath_reset_in_prog_check(
514 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
515 if (status != VXGE_HW_OK)
516 goto exit;
517
518 hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
519
520 val64 = readq(&common_reg->host_type_assignments);
521
522 hw_info->host_type =
523 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
524
525 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
526
527 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
528 continue;
529
530 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
531
532 vpmgmt_reg = (struct vxge_hw_vpmgmt_reg __iomem *)
533 (bar0 + val64);
534
535 hw_info->func_id = __vxge_hw_vpath_func_id_get(i, vpmgmt_reg);
536 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
537 hw_info->func_id) &
538 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
539
540 val64 = readq(&toc->toc_mrpcim_pointer);
541
542 mrpcim_reg = (struct vxge_hw_mrpcim_reg __iomem *)
543 (bar0 + val64);
544
545 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
546 wmb();
547 }
548
549 val64 = readq(&toc->toc_vpath_pointer[i]);
550
551 vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64);
552
553 hw_info->function_mode =
554 __vxge_hw_vpath_pci_func_mode_get(i, vpath_reg);
555
556 status = __vxge_hw_vpath_fw_ver_get(i, vpath_reg, hw_info);
557 if (status != VXGE_HW_OK)
558 goto exit;
559
560 status = __vxge_hw_vpath_card_info_get(i, vpath_reg, hw_info);
561 if (status != VXGE_HW_OK)
562 goto exit;
563
564 break;
565 }
566
567 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
568
569 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
570 continue;
571
572 val64 = readq(&toc->toc_vpath_pointer[i]);
573 vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64);
574
575 status = __vxge_hw_vpath_addr_get(i, vpath_reg,
576 hw_info->mac_addrs[i],
577 hw_info->mac_addr_masks[i]);
578 if (status != VXGE_HW_OK)
579 goto exit;
580 }
581exit:
582 return status;
583}
584
585/*
586 * vxge_hw_device_initialize - Initialize Titan device.
587 * Initialize Titan device. Note that all the arguments of this public API
588 * are 'IN', including @hldev. Driver cooperates with
589 * OS to find new Titan device, locate its PCI and memory spaces.
590 *
591 * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
592 * to enable the latter to perform Titan hardware initialization.
593 */
594enum vxge_hw_status __devinit
595vxge_hw_device_initialize(
596 struct __vxge_hw_device **devh,
597 struct vxge_hw_device_attr *attr,
598 struct vxge_hw_device_config *device_config)
599{
600 u32 i;
601 u32 nblocks = 0;
602 struct __vxge_hw_device *hldev = NULL;
603 enum vxge_hw_status status = VXGE_HW_OK;
604
605 status = __vxge_hw_device_config_check(device_config);
606 if (status != VXGE_HW_OK)
607 goto exit;
608
609 hldev = (struct __vxge_hw_device *)
610 vmalloc(sizeof(struct __vxge_hw_device));
611 if (hldev == NULL) {
612 status = VXGE_HW_ERR_OUT_OF_MEMORY;
613 goto exit;
614 }
615
616 memset(hldev, 0, sizeof(struct __vxge_hw_device));
617 hldev->magic = VXGE_HW_DEVICE_MAGIC;
618
619 vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
620
621 /* apply config */
622 memcpy(&hldev->config, device_config,
623 sizeof(struct vxge_hw_device_config));
624
625 hldev->bar0 = attr->bar0;
40a3a915
RV		 626 hldev->pdev = attr->pdev;
627
628 hldev->uld_callbacks.link_up = attr->uld_callbacks.link_up;
629 hldev->uld_callbacks.link_down = attr->uld_callbacks.link_down;
630 hldev->uld_callbacks.crit_err = attr->uld_callbacks.crit_err;
631
632 __vxge_hw_device_pci_e_init(hldev);
633
634 status = __vxge_hw_device_reg_addr_get(hldev);
635 if (status != VXGE_HW_OK)
636 goto exit;
637 __vxge_hw_device_id_get(hldev);
638
639 __vxge_hw_device_host_info_get(hldev);
640
641 /* Incrementing for stats blocks */
642 nblocks++;
643
644 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
645
646 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
647 continue;
648
649 if (device_config->vp_config[i].ring.enable ==
650 VXGE_HW_RING_ENABLE)
651 nblocks += device_config->vp_config[i].ring.ring_blocks;
652
653 if (device_config->vp_config[i].fifo.enable ==
654 VXGE_HW_FIFO_ENABLE)
655 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
656 nblocks++;
657 }
658
659 if (__vxge_hw_blockpool_create(hldev,
660 &hldev->block_pool,
661 device_config->dma_blockpool_initial + nblocks,
662 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
663
664 vxge_hw_device_terminate(hldev);
665 status = VXGE_HW_ERR_OUT_OF_MEMORY;
666 goto exit;
667 }
668
669 status = __vxge_hw_device_initialize(hldev);
670
671 if (status != VXGE_HW_OK) {
672 vxge_hw_device_terminate(hldev);
673 goto exit;
674 }
675
676 *devh = hldev;
677exit:
678 return status;
679}
680
681/*
682 * vxge_hw_device_terminate - Terminate Titan device.
683 * Terminate HW device.
684 */
685void
686vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
687{
688 vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
689
690 hldev->magic = VXGE_HW_DEVICE_DEAD;
691 __vxge_hw_blockpool_destroy(&hldev->block_pool);
692 vfree(hldev);
693}
694
695/*
696 * vxge_hw_device_stats_get - Get the device hw statistics.
697 * Returns the vpath h/w stats for the device.
698 */
699enum vxge_hw_status
700vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
701 struct vxge_hw_device_stats_hw_info *hw_stats)
702{
703 u32 i;
704 enum vxge_hw_status status = VXGE_HW_OK;
705
706 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
707
708 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
709 (hldev->virtual_paths[i].vp_open ==
710 VXGE_HW_VP_NOT_OPEN))
711 continue;
712
713 memcpy(hldev->virtual_paths[i].hw_stats_sav,
714 hldev->virtual_paths[i].hw_stats,
715 sizeof(struct vxge_hw_vpath_stats_hw_info));
716
717 status = __vxge_hw_vpath_stats_get(
718 &hldev->virtual_paths[i],
719 hldev->virtual_paths[i].hw_stats);
720 }
721
722 memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
723 sizeof(struct vxge_hw_device_stats_hw_info));
724
725 return status;
726}
727
728/*
729 * vxge_hw_driver_stats_get - Get the device sw statistics.
730 * Returns the vpath s/w stats for the device.
731 */
732enum vxge_hw_status vxge_hw_driver_stats_get(
733 struct __vxge_hw_device *hldev,
734 struct vxge_hw_device_stats_sw_info *sw_stats)
735{
736 enum vxge_hw_status status = VXGE_HW_OK;
737
738 memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
739 sizeof(struct vxge_hw_device_stats_sw_info));
740
741 return status;
742}
743
744/*
745 * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
746 * and offset and perform an operation
747 * Get the statistics from the given location and offset.
748 */
749enum vxge_hw_status
750vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
751 u32 operation, u32 location, u32 offset, u64 *stat)
752{
753 u64 val64;
754 enum vxge_hw_status status = VXGE_HW_OK;
755
92cdd7c3
SH		 756 status = __vxge_hw_device_is_privilaged(hldev->host_type,
757 hldev->func_id);
40a3a915
RV		 758 if (status != VXGE_HW_OK)
759 goto exit;
760
761 val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
762 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
763 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
764 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
765
766 status = __vxge_hw_pio_mem_write64(val64,
767 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
768 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
769 hldev->config.device_poll_millis);
770
771 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
772 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
773 else
774 *stat = 0;
775exit:
776 return status;
777}
778
779/*
780 * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
781 * Get the Statistics on aggregate port
782 */
783enum vxge_hw_status
784vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
785 struct vxge_hw_xmac_aggr_stats *aggr_stats)
786{
787 u64 *val64;
788 int i;
789 u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
790 enum vxge_hw_status status = VXGE_HW_OK;
791
792 val64 = (u64 *)aggr_stats;
793
92cdd7c3
SH		 794 status = __vxge_hw_device_is_privilaged(hldev->host_type,
795 hldev->func_id);
40a3a915
RV		 796 if (status != VXGE_HW_OK)
797 goto exit;
798
799 for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
800 status = vxge_hw_mrpcim_stats_access(hldev,
801 VXGE_HW_STATS_OP_READ,
802 VXGE_HW_STATS_LOC_AGGR,
803 ((offset + (104 * port)) >> 3), val64);
804 if (status != VXGE_HW_OK)
805 goto exit;
806
807 offset += 8;
808 val64++;
809 }
810exit:
811 return status;
812}
813
814/*
815 * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
816 * Get the Statistics on port
817 */
818enum vxge_hw_status
819vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
820 struct vxge_hw_xmac_port_stats *port_stats)
821{
822 u64 *val64;
823 enum vxge_hw_status status = VXGE_HW_OK;
824 int i;
825 u32 offset = 0x0;
826 val64 = (u64 *) port_stats;
827
92cdd7c3
SH		 828 status = __vxge_hw_device_is_privilaged(hldev->host_type,
829 hldev->func_id);
40a3a915
RV		 830 if (status != VXGE_HW_OK)
831 goto exit;
832
833 for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
834 status = vxge_hw_mrpcim_stats_access(hldev,
835 VXGE_HW_STATS_OP_READ,
836 VXGE_HW_STATS_LOC_AGGR,
837 ((offset + (608 * port)) >> 3), val64);
838 if (status != VXGE_HW_OK)
839 goto exit;
840
841 offset += 8;
842 val64++;
843 }
844
845exit:
846 return status;
847}
848
849/*
850 * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
851 * Get the XMAC Statistics
852 */
853enum vxge_hw_status
854vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
855 struct vxge_hw_xmac_stats *xmac_stats)
856{
857 enum vxge_hw_status status = VXGE_HW_OK;
858 u32 i;
859
860 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
861 0, &xmac_stats->aggr_stats[0]);
862
863 if (status != VXGE_HW_OK)
864 goto exit;
865
866 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
867 1, &xmac_stats->aggr_stats[1]);
868 if (status != VXGE_HW_OK)
869 goto exit;
870
871 for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
872
873 status = vxge_hw_device_xmac_port_stats_get(hldev,
874 i, &xmac_stats->port_stats[i]);
875 if (status != VXGE_HW_OK)
876 goto exit;
877 }
878
879 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
880
881 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
882 continue;
883
884 status = __vxge_hw_vpath_xmac_tx_stats_get(
885 &hldev->virtual_paths[i],
886 &xmac_stats->vpath_tx_stats[i]);
887 if (status != VXGE_HW_OK)
888 goto exit;
889
890 status = __vxge_hw_vpath_xmac_rx_stats_get(
891 &hldev->virtual_paths[i],
892 &xmac_stats->vpath_rx_stats[i]);
893 if (status != VXGE_HW_OK)
894 goto exit;
895 }
896exit:
897 return status;
898}
899
900/*
901 * vxge_hw_device_debug_set - Set the debug module, level and timestamp
902 * This routine is used to dynamically change the debug output
903 */
904void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
905 enum vxge_debug_level level, u32 mask)
906{
907 if (hldev == NULL)
908 return;
909
910#if defined(VXGE_DEBUG_TRACE_MASK) || \
911 defined(VXGE_DEBUG_ERR_MASK)
912 hldev->debug_module_mask = mask;
913 hldev->debug_level = level;
914#endif
915
916#if defined(VXGE_DEBUG_ERR_MASK)
917 hldev->level_err = level & VXGE_ERR;
918#endif
919
920#if defined(VXGE_DEBUG_TRACE_MASK)
921 hldev->level_trace = level & VXGE_TRACE;
922#endif
923}
924
925/*
926 * vxge_hw_device_error_level_get - Get the error level
927 * This routine returns the current error level set
928 */
929u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
930{
931#if defined(VXGE_DEBUG_ERR_MASK)
932 if (hldev == NULL)
933 return VXGE_ERR;
934 else
935 return hldev->level_err;
936#else
937 return 0;
938#endif
939}
940
941/*
942 * vxge_hw_device_trace_level_get - Get the trace level
943 * This routine returns the current trace level set
944 */
945u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
946{
947#if defined(VXGE_DEBUG_TRACE_MASK)
948 if (hldev == NULL)
949 return VXGE_TRACE;
950 else
951 return hldev->level_trace;
952#else
953 return 0;
954#endif
955}
956/*
957 * vxge_hw_device_debug_mask_get - Get the debug mask
958 * This routine returns the current debug mask set
959 */
960u32 vxge_hw_device_debug_mask_get(struct __vxge_hw_device *hldev)
961{
962#if defined(VXGE_DEBUG_TRACE_MASK) || defined(VXGE_DEBUG_ERR_MASK)
963 if (hldev == NULL)
964 return 0;
965 return hldev->debug_module_mask;
966#else
967 return 0;
968#endif
969}
970
971/*
972 * vxge_hw_getpause_data -Pause frame frame generation and reception.
973 * Returns the Pause frame generation and reception capability of the NIC.
974 */
975enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
976 u32 port, u32 *tx, u32 *rx)
977{
978 u64 val64;
979 enum vxge_hw_status status = VXGE_HW_OK;
980
981 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
982 status = VXGE_HW_ERR_INVALID_DEVICE;
983 goto exit;
984 }
985
986 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
987 status = VXGE_HW_ERR_INVALID_PORT;
988 goto exit;
989 }
990
991 if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
992 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
993 goto exit;
994 }
995
996 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
997 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
998 *tx = 1;
999 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1000 *rx = 1;
1001exit:
1002 return status;
1003}
1004
1005/*
1006 * vxge_hw_device_setpause_data - set/reset pause frame generation.
1007 * It can be used to set or reset Pause frame generation or reception
1008 * support of the NIC.
1009 */
1010
1011enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1012 u32 port, u32 tx, u32 rx)
1013{
1014 u64 val64;
1015 enum vxge_hw_status status = VXGE_HW_OK;
1016
1017 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1018 status = VXGE_HW_ERR_INVALID_DEVICE;
1019 goto exit;
1020 }
1021
1022 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1023 status = VXGE_HW_ERR_INVALID_PORT;
1024 goto exit;
1025 }
1026
92cdd7c3
SH		 1027 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1028 hldev->func_id);
40a3a915
RV		 1029 if (status != VXGE_HW_OK)
1030 goto exit;
1031
1032 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1033 if (tx)
1034 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1035 else
1036 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1037 if (rx)
1038 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1039 else
1040 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1041
1042 writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1043exit:
1044 return status;
1045}
1046
1047u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1048{
1049 int link_width, exp_cap;
1050 u16 lnk;
1051
1052 exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
1053 pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
1054 link_width = (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1055 return link_width;
1056}
1057
1058/*
1059 * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1060 * This function returns the index of memory block
1061 */
1062static inline u32
1063__vxge_hw_ring_block_memblock_idx(u8 *block)
1064{
1065 return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1066}
1067
1068/*
1069 * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1070 * This function sets index to a memory block
1071 */
1072static inline void
1073__vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
1074{
1075 *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
1076}
1077
1078/*
1079 * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
1080 * in RxD block
1081 * Sets the next block pointer in RxD block
1082 */
1083static inline void
1084__vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
1085{
1086 *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
1087}
1088
1089/*
1090 * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
1091 * first block
1092 * Returns the dma address of the first RxD block
1093 */
1094u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
1095{
1096 struct vxge_hw_mempool_dma *dma_object;
1097
1098 dma_object = ring->mempool->memblocks_dma_arr;
1099 vxge_assert(dma_object != NULL);
1100
1101 return dma_object->addr;
1102}
1103
1104/*
1105 * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
1106 * This function returns the dma address of a given item
1107 */
1108static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
1109 void *item)
1110{
1111 u32 memblock_idx;
1112 void *memblock;
1113 struct vxge_hw_mempool_dma *memblock_dma_object;
1114 ptrdiff_t dma_item_offset;
1115
1116 /* get owner memblock index */
1117 memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
1118
1119 /* get owner memblock by memblock index */
1120 memblock = mempoolh->memblocks_arr[memblock_idx];
1121
1122 /* get memblock DMA object by memblock index */
1123 memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
1124
1125 /* calculate offset in the memblock of this item */
1126 dma_item_offset = (u8 *)item - (u8 *)memblock;
1127
1128 return memblock_dma_object->addr + dma_item_offset;
1129}
1130
1131/*
1132 * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
1133 * This function returns the dma address of a given item
1134 */
1135static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
1136 struct __vxge_hw_ring *ring, u32 from,
1137 u32 to)
1138{
1139 u8 *to_item , *from_item;
1140 dma_addr_t to_dma;
1141
1142 /* get "from" RxD block */
1143 from_item = mempoolh->items_arr[from];
1144 vxge_assert(from_item);
1145
1146 /* get "to" RxD block */
1147 to_item = mempoolh->items_arr[to];
1148 vxge_assert(to_item);
1149
1150 /* return address of the beginning of previous RxD block */
1151 to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
1152
1153 /* set next pointer for this RxD block to point on
1154 * previous item's DMA start address */
1155 __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
1156}
1157
1158/*
1159 * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
1160 * block callback
1161 * This function is callback passed to __vxge_hw_mempool_create to create memory
1162 * pool for RxD block
1163 */
1164static void
1165__vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
1166 u32 memblock_index,
1167 struct vxge_hw_mempool_dma *dma_object,
1168 u32 index, u32 is_last)
1169{
1170 u32 i;
1171 void *item = mempoolh->items_arr[index];
1172 struct __vxge_hw_ring *ring =
1173 (struct __vxge_hw_ring *)mempoolh->userdata;
1174
1175 /* format rxds array */
1176 for (i = 0; i < ring->rxds_per_block; i++) {
1177 void *rxdblock_priv;
1178 void *uld_priv;
1179 struct vxge_hw_ring_rxd_1 *rxdp;
1180
1181 u32 reserve_index = ring->channel.reserve_ptr -
1182 (index * ring->rxds_per_block + i + 1);
1183 u32 memblock_item_idx;
1184
1185 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
1186 i * ring->rxd_size;
1187
1188 /* Note: memblock_item_idx is index of the item within
1189 * the memblock. For instance, in case of three RxD-blocks
1190 * per memblock this value can be 0, 1 or 2. */
1191 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
1192 memblock_index, item,
1193 &memblock_item_idx);
1194
1195 rxdp = (struct vxge_hw_ring_rxd_1 *)
1196 ring->channel.reserve_arr[reserve_index];
1197
1198 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
1199
1200 /* pre-format Host_Control */
1201 rxdp->host_control = (u64)(size_t)uld_priv;
1202 }
1203
1204 __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
1205
1206 if (is_last) {
1207 /* link last one with first one */
1208 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
1209 }
1210
1211 if (index > 0) {
1212 /* link this RxD block with previous one */
1213 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
1214 }
1215
1216 return;
1217}
1218
1219/*
3363276f 1220 * __vxge_hw_ring_replenish - Initial replenish of RxDs
40a3a915
RV		 1221 * This function replenishes the RxDs from reserve array to work array
1222 */
1223enum vxge_hw_status
3363276f 1224vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
40a3a915
RV		 1225{
1226 void *rxd;
40a3a915
RV		 1227 struct __vxge_hw_channel *channel;
1228 enum vxge_hw_status status = VXGE_HW_OK;
1229
1230 channel = &ring->channel;
1231
1232 while (vxge_hw_channel_dtr_count(channel) > 0) {
1233
1234 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
1235
1236 vxge_assert(status == VXGE_HW_OK);
1237
1238 if (ring->rxd_init) {
1239 status = ring->rxd_init(rxd, channel->userdata);
1240 if (status != VXGE_HW_OK) {
1241 vxge_hw_ring_rxd_free(ring, rxd);
1242 goto exit;
1243 }
1244 }
1245
1246 vxge_hw_ring_rxd_post(ring, rxd);
40a3a915
RV		 1247 }
1248 status = VXGE_HW_OK;
1249exit:
1250 return status;
1251}
1252
1253/*
1254 * __vxge_hw_ring_create - Create a Ring
1255 * This function creates Ring and initializes it.
1256 *
1257 */
1258enum vxge_hw_status
1259__vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
1260 struct vxge_hw_ring_attr *attr)
1261{
1262 enum vxge_hw_status status = VXGE_HW_OK;
1263 struct __vxge_hw_ring *ring;
1264 u32 ring_length;
1265 struct vxge_hw_ring_config *config;
1266 struct __vxge_hw_device *hldev;
1267 u32 vp_id;
1268 struct vxge_hw_mempool_cbs ring_mp_callback;
1269
1270 if ((vp == NULL) || (attr == NULL)) {
1271 status = VXGE_HW_FAIL;
1272 goto exit;
1273 }
1274
1275 hldev = vp->vpath->hldev;
1276 vp_id = vp->vpath->vp_id;
1277
1278 config = &hldev->config.vp_config[vp_id].ring;
1279
1280 ring_length = config->ring_blocks *
1281 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
1282
1283 ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
1284 VXGE_HW_CHANNEL_TYPE_RING,
1285 ring_length,
1286 attr->per_rxd_space,
1287 attr->userdata);
1288
1289 if (ring == NULL) {
1290 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1291 goto exit;
1292 }
1293
1294 vp->vpath->ringh = ring;
1295 ring->vp_id = vp_id;
1296 ring->vp_reg = vp->vpath->vp_reg;
1297 ring->common_reg = hldev->common_reg;
1298 ring->stats = &vp->vpath->sw_stats->ring_stats;
1299 ring->config = config;
1300 ring->callback = attr->callback;
1301 ring->rxd_init = attr->rxd_init;
1302 ring->rxd_term = attr->rxd_term;
1303 ring->buffer_mode = config->buffer_mode;
1304 ring->rxds_limit = config->rxds_limit;
1305
1306 ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
1307 ring->rxd_priv_size =
1308 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
1309 ring->per_rxd_space = attr->per_rxd_space;
1310
1311 ring->rxd_priv_size =
1312 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
1313 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
1314
1315 /* how many RxDs can fit into one block. Depends on configured
1316 * buffer_mode. */
1317 ring->rxds_per_block =
1318 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
1319
1320 /* calculate actual RxD block private size */
1321 ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
1322 ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc;
1323 ring->mempool = __vxge_hw_mempool_create(hldev,
1324 VXGE_HW_BLOCK_SIZE,
1325 VXGE_HW_BLOCK_SIZE,
1326 ring->rxdblock_priv_size,
1327 ring->config->ring_blocks,
1328 ring->config->ring_blocks,
1329 &ring_mp_callback,
1330 ring);
1331
1332 if (ring->mempool == NULL) {
1333 __vxge_hw_ring_delete(vp);
1334 return VXGE_HW_ERR_OUT_OF_MEMORY;
1335 }
1336
1337 status = __vxge_hw_channel_initialize(&ring->channel);
1338 if (status != VXGE_HW_OK) {
1339 __vxge_hw_ring_delete(vp);
1340 goto exit;
1341 }
1342
1343 /* Note:
1344 * Specifying rxd_init callback means two things:
1345 * 1) rxds need to be initialized by driver at channel-open time;
1346 * 2) rxds need to be posted at channel-open time
1347 * (that's what the initial_replenish() below does)
1348 * Currently we don't have a case when the 1) is done without the 2).
1349 */
1350 if (ring->rxd_init) {
3363276f 1351 status = vxge_hw_ring_replenish(ring);
40a3a915
RV		 1352 if (status != VXGE_HW_OK) {
1353 __vxge_hw_ring_delete(vp);
1354 goto exit;
1355 }
1356 }
1357
1358 /* initial replenish will increment the counter in its post() routine,
1359 * we have to reset it */
1360 ring->stats->common_stats.usage_cnt = 0;
1361exit:
1362 return status;
1363}
1364
1365/*
1366 * __vxge_hw_ring_abort - Returns the RxD
1367 * This function terminates the RxDs of ring
1368 */
1369enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
1370{
1371 void *rxdh;
1372 struct __vxge_hw_channel *channel;
1373
1374 channel = &ring->channel;
1375
1376 for (;;) {
1377 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
1378
1379 if (rxdh == NULL)
1380 break;
1381
1382 vxge_hw_channel_dtr_complete(channel);
1383
1384 if (ring->rxd_term)
1385 ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
1386 channel->userdata);
1387
1388 vxge_hw_channel_dtr_free(channel, rxdh);
1389 }
1390
1391 return VXGE_HW_OK;
1392}
1393
1394/*
1395 * __vxge_hw_ring_reset - Resets the ring
1396 * This function resets the ring during vpath reset operation
1397 */
1398enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
1399{
1400 enum vxge_hw_status status = VXGE_HW_OK;
1401 struct __vxge_hw_channel *channel;
1402
1403 channel = &ring->channel;
1404
1405 __vxge_hw_ring_abort(ring);
1406
1407 status = __vxge_hw_channel_reset(channel);
1408
1409 if (status != VXGE_HW_OK)
1410 goto exit;
1411
1412 if (ring->rxd_init) {
3363276f 1413 status = vxge_hw_ring_replenish(ring);
40a3a915
RV		 1414 if (status != VXGE_HW_OK)
1415 goto exit;
1416 }
1417exit:
1418 return status;
1419}
1420
1421/*
1422 * __vxge_hw_ring_delete - Removes the ring
1423 * This function freeup the memory pool and removes the ring
1424 */
1425enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
1426{
1427 struct __vxge_hw_ring *ring = vp->vpath->ringh;
1428
1429 __vxge_hw_ring_abort(ring);
1430
1431 if (ring->mempool)
1432 __vxge_hw_mempool_destroy(ring->mempool);
1433
1434 vp->vpath->ringh = NULL;
1435 __vxge_hw_channel_free(&ring->channel);
1436
1437 return VXGE_HW_OK;
1438}
1439
1440/*
1441 * __vxge_hw_mempool_grow
1442 * Will resize mempool up to %num_allocate value.
1443 */
1444enum vxge_hw_status
1445__vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
1446 u32 *num_allocated)
1447{
1448 u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
1449 u32 n_items = mempool->items_per_memblock;
1450 u32 start_block_idx = mempool->memblocks_allocated;
1451 u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
1452 enum vxge_hw_status status = VXGE_HW_OK;
1453
1454 *num_allocated = 0;
1455
1456 if (end_block_idx > mempool->memblocks_max) {
1457 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1458 goto exit;
1459 }
1460
1461 for (i = start_block_idx; i < end_block_idx; i++) {
1462 u32 j;
1463 u32 is_last = ((end_block_idx - 1) == i);
1464 struct vxge_hw_mempool_dma *dma_object =
1465 mempool->memblocks_dma_arr + i;
1466 void *the_memblock;
1467
1468 /* allocate memblock's private part. Each DMA memblock
1469 * has a space allocated for item's private usage upon
1470 * mempool's user request. Each time mempool grows, it will
1471 * allocate new memblock and its private part at once.
1472 * This helps to minimize memory usage a lot. */
1473 mempool->memblocks_priv_arr[i] =
1474 vmalloc(mempool->items_priv_size * n_items);
1475 if (mempool->memblocks_priv_arr[i] == NULL) {
1476 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1477 goto exit;
1478 }
1479
1480 memset(mempool->memblocks_priv_arr[i], 0,
1481 mempool->items_priv_size * n_items);
1482
1483 /* allocate DMA-capable memblock */
1484 mempool->memblocks_arr[i] =
1485 __vxge_hw_blockpool_malloc(mempool->devh,
1486 mempool->memblock_size, dma_object);
1487 if (mempool->memblocks_arr[i] == NULL) {
1488 vfree(mempool->memblocks_priv_arr[i]);
1489 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1490 goto exit;
1491 }
1492
1493 (*num_allocated)++;
1494 mempool->memblocks_allocated++;
1495
1496 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
1497
1498 the_memblock = mempool->memblocks_arr[i];
1499
1500 /* fill the items hash array */
1501 for (j = 0; j < n_items; j++) {
1502 u32 index = i * n_items + j;
1503
1504 if (first_time && index >= mempool->items_initial)
1505 break;
1506
1507 mempool->items_arr[index] =
1508 ((char *)the_memblock + j*mempool->item_size);
1509
1510 /* let caller to do more job on each item */
1511 if (mempool->item_func_alloc != NULL)
1512 mempool->item_func_alloc(mempool, i,
1513 dma_object, index, is_last);
1514
1515 mempool->items_current = index + 1;
1516 }
1517
1518 if (first_time && mempool->items_current ==
1519 mempool->items_initial)
1520 break;
1521 }
1522exit:
1523 return status;
1524}
1525
1526/*
1527 * vxge_hw_mempool_create
1528 * This function will create memory pool object. Pool may grow but will
1529 * never shrink. Pool consists of number of dynamically allocated blocks
1530 * with size enough to hold %items_initial number of items. Memory is
1531 * DMA-able but client must map/unmap before interoperating with the device.
1532 */
1533struct vxge_hw_mempool*
1534__vxge_hw_mempool_create(
1535 struct __vxge_hw_device *devh,
1536 u32 memblock_size,
1537 u32 item_size,
1538 u32 items_priv_size,
1539 u32 items_initial,
1540 u32 items_max,
1541 struct vxge_hw_mempool_cbs *mp_callback,
1542 void *userdata)
1543{
1544 enum vxge_hw_status status = VXGE_HW_OK;
1545 u32 memblocks_to_allocate;
1546 struct vxge_hw_mempool *mempool = NULL;
1547 u32 allocated;
1548
1549 if (memblock_size < item_size) {
1550 status = VXGE_HW_FAIL;
1551 goto exit;
1552 }
1553
1554 mempool = (struct vxge_hw_mempool *)
1555 vmalloc(sizeof(struct vxge_hw_mempool));
1556 if (mempool == NULL) {
1557 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1558 goto exit;
1559 }
1560 memset(mempool, 0, sizeof(struct vxge_hw_mempool));
1561
1562 mempool->devh = devh;
1563 mempool->memblock_size = memblock_size;
1564 mempool->items_max = items_max;
1565 mempool->items_initial = items_initial;
1566 mempool->item_size = item_size;
1567 mempool->items_priv_size = items_priv_size;
1568 mempool->item_func_alloc = mp_callback->item_func_alloc;
1569 mempool->userdata = userdata;
1570
1571 mempool->memblocks_allocated = 0;
1572
1573 mempool->items_per_memblock = memblock_size / item_size;
1574
1575 mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
1576 mempool->items_per_memblock;
1577
1578 /* allocate array of memblocks */
1579 mempool->memblocks_arr =
1580 (void **) vmalloc(sizeof(void *) * mempool->memblocks_max);
1581 if (mempool->memblocks_arr == NULL) {
1582 __vxge_hw_mempool_destroy(mempool);
1583 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1584 mempool = NULL;
1585 goto exit;
1586 }
1587 memset(mempool->memblocks_arr, 0,
1588 sizeof(void *) * mempool->memblocks_max);
1589
1590 /* allocate array of private parts of items per memblocks */
1591 mempool->memblocks_priv_arr =
1592 (void **) vmalloc(sizeof(void *) * mempool->memblocks_max);
1593 if (mempool->memblocks_priv_arr == NULL) {
1594 __vxge_hw_mempool_destroy(mempool);
1595 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1596 mempool = NULL;
1597 goto exit;
1598 }
1599 memset(mempool->memblocks_priv_arr, 0,
1600 sizeof(void *) * mempool->memblocks_max);
1601
1602 /* allocate array of memblocks DMA objects */
1603 mempool->memblocks_dma_arr = (struct vxge_hw_mempool_dma *)
1604 vmalloc(sizeof(struct vxge_hw_mempool_dma) *
1605 mempool->memblocks_max);
1606
1607 if (mempool->memblocks_dma_arr == NULL) {
1608 __vxge_hw_mempool_destroy(mempool);
1609 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1610 mempool = NULL;
1611 goto exit;
1612 }
1613 memset(mempool->memblocks_dma_arr, 0,
1614 sizeof(struct vxge_hw_mempool_dma) *
1615 mempool->memblocks_max);
1616
1617 /* allocate hash array of items */
1618 mempool->items_arr =
1619 (void **) vmalloc(sizeof(void *) * mempool->items_max);
1620 if (mempool->items_arr == NULL) {
1621 __vxge_hw_mempool_destroy(mempool);
1622 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1623 mempool = NULL;
1624 goto exit;
1625 }
1626 memset(mempool->items_arr, 0, sizeof(void *) * mempool->items_max);
1627
1628 /* calculate initial number of memblocks */
1629 memblocks_to_allocate = (mempool->items_initial +
1630 mempool->items_per_memblock - 1) /
1631 mempool->items_per_memblock;
1632
1633 /* pre-allocate the mempool */
1634 status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
1635 &allocated);
1636 if (status != VXGE_HW_OK) {
1637 __vxge_hw_mempool_destroy(mempool);
1638 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1639 mempool = NULL;
1640 goto exit;
1641 }
1642
1643exit:
1644 return mempool;
1645}
1646
1647/*
1648 * vxge_hw_mempool_destroy
1649 */
1650void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
1651{
1652 u32 i, j;
1653 struct __vxge_hw_device *devh = mempool->devh;
1654
1655 for (i = 0; i < mempool->memblocks_allocated; i++) {
1656 struct vxge_hw_mempool_dma *dma_object;
1657
1658 vxge_assert(mempool->memblocks_arr[i]);
1659 vxge_assert(mempool->memblocks_dma_arr + i);
1660
1661 dma_object = mempool->memblocks_dma_arr + i;
1662
1663 for (j = 0; j < mempool->items_per_memblock; j++) {
1664 u32 index = i * mempool->items_per_memblock + j;
1665
1666 /* to skip last partially filled(if any) memblock */
1667 if (index >= mempool->items_current)
1668 break;
1669 }
1670
1671 vfree(mempool->memblocks_priv_arr[i]);
1672
1673 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
1674 mempool->memblock_size, dma_object);
1675 }
1676
50d36a93 1677 vfree(mempool->items_arr);
40a3a915 1678
50d36a93 1679 vfree(mempool->memblocks_dma_arr);
40a3a915 1680
50d36a93 1681 vfree(mempool->memblocks_priv_arr);
40a3a915 1682
50d36a93 1683 vfree(mempool->memblocks_arr);
40a3a915
RV		 1684
1685 vfree(mempool);
1686}
1687
1688/*
1689 * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1690 * Check the fifo configuration
1691 */
1692enum vxge_hw_status
1693__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1694{
1695 if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1696 (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1697 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1698
1699 return VXGE_HW_OK;
1700}
1701
1702/*
1703 * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1704 * Check the vpath configuration
1705 */
1706enum vxge_hw_status
1707__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1708{
1709 enum vxge_hw_status status;
1710
1711 if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1712 (vp_config->min_bandwidth >
1713 VXGE_HW_VPATH_BANDWIDTH_MAX))
1714 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1715
1716 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1717 if (status != VXGE_HW_OK)
1718 return status;
1719
1720 if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1721 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1722 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1723 return VXGE_HW_BADCFG_VPATH_MTU;
1724
1725 if ((vp_config->rpa_strip_vlan_tag !=
1726 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1727 (vp_config->rpa_strip_vlan_tag !=
1728 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1729 (vp_config->rpa_strip_vlan_tag !=
1730 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1731 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1732
1733 return VXGE_HW_OK;
1734}
1735
1736/*
1737 * __vxge_hw_device_config_check - Check device configuration.
1738 * Check the device configuration
1739 */
1740enum vxge_hw_status
1741__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1742{
1743 u32 i;
1744 enum vxge_hw_status status;
1745
1746 if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1747 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1748 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1749 (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1750 return VXGE_HW_BADCFG_INTR_MODE;
1751
1752 if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1753 (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1754 return VXGE_HW_BADCFG_RTS_MAC_EN;
1755
1756 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1757 status = __vxge_hw_device_vpath_config_check(
1758 &new_config->vp_config[i]);
1759 if (status != VXGE_HW_OK)
1760 return status;
1761 }
1762
1763 return VXGE_HW_OK;
1764}
1765
1766/*
1767 * vxge_hw_device_config_default_get - Initialize device config with defaults.
1768 * Initialize Titan device config with default values.
1769 */
1770enum vxge_hw_status __devinit
1771vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
1772{
1773 u32 i;
1774
1775 device_config->dma_blockpool_initial =
1776 VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
1777 device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
1778 device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
1779 device_config->rth_en = VXGE_HW_RTH_DEFAULT;
1780 device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
1781 device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS;
1782 device_config->rts_mac_en = VXGE_HW_RTS_MAC_DEFAULT;
1783
1784 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1785
1786 device_config->vp_config[i].vp_id = i;
1787
1788 device_config->vp_config[i].min_bandwidth =
1789 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
1790
1791 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
1792
1793 device_config->vp_config[i].ring.ring_blocks =
1794 VXGE_HW_DEF_RING_BLOCKS;
1795
1796 device_config->vp_config[i].ring.buffer_mode =
1797 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
1798
1799 device_config->vp_config[i].ring.scatter_mode =
1800 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
1801
1802 device_config->vp_config[i].ring.rxds_limit =
1803 VXGE_HW_DEF_RING_RXDS_LIMIT;
1804
1805 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
1806
1807 device_config->vp_config[i].fifo.fifo_blocks =
1808 VXGE_HW_MIN_FIFO_BLOCKS;
1809
1810 device_config->vp_config[i].fifo.max_frags =
1811 VXGE_HW_MAX_FIFO_FRAGS;
1812
1813 device_config->vp_config[i].fifo.memblock_size =
1814 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
1815
1816 device_config->vp_config[i].fifo.alignment_size =
1817 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
1818
1819 device_config->vp_config[i].fifo.intr =
1820 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
1821
1822 device_config->vp_config[i].fifo.no_snoop_bits =
1823 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
1824 device_config->vp_config[i].tti.intr_enable =
1825 VXGE_HW_TIM_INTR_DEFAULT;
1826
1827 device_config->vp_config[i].tti.btimer_val =
1828 VXGE_HW_USE_FLASH_DEFAULT;
1829
1830 device_config->vp_config[i].tti.timer_ac_en =
1831 VXGE_HW_USE_FLASH_DEFAULT;
1832
1833 device_config->vp_config[i].tti.timer_ci_en =
1834 VXGE_HW_USE_FLASH_DEFAULT;
1835
1836 device_config->vp_config[i].tti.timer_ri_en =
1837 VXGE_HW_USE_FLASH_DEFAULT;
1838
1839 device_config->vp_config[i].tti.rtimer_val =
1840 VXGE_HW_USE_FLASH_DEFAULT;
1841
1842 device_config->vp_config[i].tti.util_sel =
1843 VXGE_HW_USE_FLASH_DEFAULT;
1844
1845 device_config->vp_config[i].tti.ltimer_val =
1846 VXGE_HW_USE_FLASH_DEFAULT;
1847
1848 device_config->vp_config[i].tti.urange_a =
1849 VXGE_HW_USE_FLASH_DEFAULT;
1850
1851 device_config->vp_config[i].tti.uec_a =
1852 VXGE_HW_USE_FLASH_DEFAULT;
1853
1854 device_config->vp_config[i].tti.urange_b =
1855 VXGE_HW_USE_FLASH_DEFAULT;
1856
1857 device_config->vp_config[i].tti.uec_b =
1858 VXGE_HW_USE_FLASH_DEFAULT;
1859
1860 device_config->vp_config[i].tti.urange_c =
1861 VXGE_HW_USE_FLASH_DEFAULT;
1862
1863 device_config->vp_config[i].tti.uec_c =
1864 VXGE_HW_USE_FLASH_DEFAULT;
1865
1866 device_config->vp_config[i].tti.uec_d =
1867 VXGE_HW_USE_FLASH_DEFAULT;
1868
1869 device_config->vp_config[i].rti.intr_enable =
1870 VXGE_HW_TIM_INTR_DEFAULT;
1871
1872 device_config->vp_config[i].rti.btimer_val =
1873 VXGE_HW_USE_FLASH_DEFAULT;
1874
1875 device_config->vp_config[i].rti.timer_ac_en =
1876 VXGE_HW_USE_FLASH_DEFAULT;
1877
1878 device_config->vp_config[i].rti.timer_ci_en =
1879 VXGE_HW_USE_FLASH_DEFAULT;
1880
1881 device_config->vp_config[i].rti.timer_ri_en =
1882 VXGE_HW_USE_FLASH_DEFAULT;
1883
1884 device_config->vp_config[i].rti.rtimer_val =
1885 VXGE_HW_USE_FLASH_DEFAULT;
1886
1887 device_config->vp_config[i].rti.util_sel =
1888 VXGE_HW_USE_FLASH_DEFAULT;
1889
1890 device_config->vp_config[i].rti.ltimer_val =
1891 VXGE_HW_USE_FLASH_DEFAULT;
1892
1893 device_config->vp_config[i].rti.urange_a =
1894 VXGE_HW_USE_FLASH_DEFAULT;
1895
1896 device_config->vp_config[i].rti.uec_a =
1897 VXGE_HW_USE_FLASH_DEFAULT;
1898
1899 device_config->vp_config[i].rti.urange_b =
1900 VXGE_HW_USE_FLASH_DEFAULT;
1901
1902 device_config->vp_config[i].rti.uec_b =
1903 VXGE_HW_USE_FLASH_DEFAULT;
1904
1905 device_config->vp_config[i].rti.urange_c =
1906 VXGE_HW_USE_FLASH_DEFAULT;
1907
1908 device_config->vp_config[i].rti.uec_c =
1909 VXGE_HW_USE_FLASH_DEFAULT;
1910
1911 device_config->vp_config[i].rti.uec_d =
1912 VXGE_HW_USE_FLASH_DEFAULT;
1913
1914 device_config->vp_config[i].mtu =
1915 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
1916
1917 device_config->vp_config[i].rpa_strip_vlan_tag =
1918 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
1919 }
1920
1921 return VXGE_HW_OK;
1922}
1923
1924/*
1925 * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
1926 * Set the swapper bits appropriately for the lagacy section.
1927 */
1928enum vxge_hw_status
1929__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
1930{
1931 u64 val64;
1932 enum vxge_hw_status status = VXGE_HW_OK;
1933
1934 val64 = readq(&legacy_reg->toc_swapper_fb);
1935
1936 wmb();
1937
1938 switch (val64) {
1939
1940 case VXGE_HW_SWAPPER_INITIAL_VALUE:
1941 return status;
1942
1943 case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
1944 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
1945 &legacy_reg->pifm_rd_swap_en);
1946 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
1947 &legacy_reg->pifm_rd_flip_en);
1948 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
1949 &legacy_reg->pifm_wr_swap_en);
1950 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
1951 &legacy_reg->pifm_wr_flip_en);
1952 break;
1953
1954 case VXGE_HW_SWAPPER_BYTE_SWAPPED:
1955 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
1956 &legacy_reg->pifm_rd_swap_en);
1957 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
1958 &legacy_reg->pifm_wr_swap_en);
1959 break;
1960
1961 case VXGE_HW_SWAPPER_BIT_FLIPPED:
1962 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
1963 &legacy_reg->pifm_rd_flip_en);
1964 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
1965 &legacy_reg->pifm_wr_flip_en);
1966 break;
1967 }
1968
1969 wmb();
1970
1971 val64 = readq(&legacy_reg->toc_swapper_fb);
1972
1973 if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
1974 status = VXGE_HW_ERR_SWAPPER_CTRL;
1975
1976 return status;
1977}
1978
1979/*
1980 * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
1981 * Set the swapper bits appropriately for the vpath.
1982 */
1983enum vxge_hw_status
1984__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
1985{
1986#ifndef __BIG_ENDIAN
1987 u64 val64;
1988
1989 val64 = readq(&vpath_reg->vpath_general_cfg1);
1990 wmb();
1991 val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
1992 writeq(val64, &vpath_reg->vpath_general_cfg1);
1993 wmb();
1994#endif
1995 return VXGE_HW_OK;
1996}
1997
1998/*
1999 * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
2000 * Set the swapper bits appropriately for the vpath.
2001 */
2002enum vxge_hw_status
2003__vxge_hw_kdfc_swapper_set(
2004 struct vxge_hw_legacy_reg __iomem *legacy_reg,
2005 struct vxge_hw_vpath_reg __iomem *vpath_reg)
2006{
2007 u64 val64;
2008
2009 val64 = readq(&legacy_reg->pifm_wr_swap_en);
2010
2011 if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
2012 val64 = readq(&vpath_reg->kdfcctl_cfg0);
2013 wmb();
2014
2015 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
2016 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
2017 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
2018
2019 writeq(val64, &vpath_reg->kdfcctl_cfg0);
2020 wmb();
2021 }
2022
2023 return VXGE_HW_OK;
2024}
2025
2026/*
2027 * vxge_hw_mgmt_device_config - Retrieve device configuration.
2028 * Get device configuration. Permits to retrieve at run-time configuration
2029 * values that were used to initialize and configure the device.
2030 */
2031enum vxge_hw_status
2032vxge_hw_mgmt_device_config(struct __vxge_hw_device *hldev,
2033 struct vxge_hw_device_config *dev_config, int size)
2034{
2035
2036 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC))
2037 return VXGE_HW_ERR_INVALID_DEVICE;
2038
2039 if (size != sizeof(struct vxge_hw_device_config))
2040 return VXGE_HW_ERR_VERSION_CONFLICT;
2041
2042 memcpy(dev_config, &hldev->config,
2043 sizeof(struct vxge_hw_device_config));
2044
2045 return VXGE_HW_OK;
2046}
2047
2048/*
2049 * vxge_hw_mgmt_reg_read - Read Titan register.
2050 */
2051enum vxge_hw_status
2052vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
2053 enum vxge_hw_mgmt_reg_type type,
2054 u32 index, u32 offset, u64 *value)
2055{
2056 enum vxge_hw_status status = VXGE_HW_OK;
2057
2058 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
2059 status = VXGE_HW_ERR_INVALID_DEVICE;
2060 goto exit;
2061 }
2062
2063 switch (type) {
2064 case vxge_hw_mgmt_reg_type_legacy:
2065 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
2066 status = VXGE_HW_ERR_INVALID_OFFSET;
2067 break;
2068 }
2069 *value = readq((void __iomem *)hldev->legacy_reg + offset);
2070 break;
2071 case vxge_hw_mgmt_reg_type_toc:
2072 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
2073 status = VXGE_HW_ERR_INVALID_OFFSET;
2074 break;
2075 }
2076 *value = readq((void __iomem *)hldev->toc_reg + offset);
2077 break;
2078 case vxge_hw_mgmt_reg_type_common:
2079 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
2080 status = VXGE_HW_ERR_INVALID_OFFSET;
2081 break;
2082 }
2083 *value = readq((void __iomem *)hldev->common_reg + offset);
2084 break;
2085 case vxge_hw_mgmt_reg_type_mrpcim:
2086 if (!(hldev->access_rights &
2087 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2088 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2089 break;
2090 }
2091 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
2092 status = VXGE_HW_ERR_INVALID_OFFSET;
2093 break;
2094 }
2095 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
2096 break;
2097 case vxge_hw_mgmt_reg_type_srpcim:
2098 if (!(hldev->access_rights &
2099 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
2100 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2101 break;
2102 }
2103 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
2104 status = VXGE_HW_ERR_INVALID_INDEX;
2105 break;
2106 }
2107 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
2108 status = VXGE_HW_ERR_INVALID_OFFSET;
2109 break;
2110 }
2111 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
2112 offset);
2113 break;
2114 case vxge_hw_mgmt_reg_type_vpmgmt:
2115 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
2116 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2117 status = VXGE_HW_ERR_INVALID_INDEX;
2118 break;
2119 }
2120 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
2121 status = VXGE_HW_ERR_INVALID_OFFSET;
2122 break;
2123 }
2124 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
2125 offset);
2126 break;
2127 case vxge_hw_mgmt_reg_type_vpath:
2128 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
2129 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2130 status = VXGE_HW_ERR_INVALID_INDEX;
2131 break;
2132 }
2133 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
2134 status = VXGE_HW_ERR_INVALID_INDEX;
2135 break;
2136 }
2137 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
2138 status = VXGE_HW_ERR_INVALID_OFFSET;
2139 break;
2140 }
2141 *value = readq((void __iomem *)hldev->vpath_reg[index] +
2142 offset);
2143 break;
2144 default:
2145 status = VXGE_HW_ERR_INVALID_TYPE;
2146 break;
2147 }
2148
2149exit:
2150 return status;
2151}
2152
fa41fd10
SH		 2153/*
2154 * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
2155 */
2156enum vxge_hw_status
2157vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
2158{
2159 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
2160 enum vxge_hw_status status = VXGE_HW_OK;
2161 int i = 0, j = 0;
2162
2163 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2164 if (!((vpath_mask) & vxge_mBIT(i)))
2165 continue;
2166 vpmgmt_reg = hldev->vpmgmt_reg[i];
2167 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
2168 if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
2169 & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
2170 return VXGE_HW_FAIL;
2171 }
2172 }
2173 return status;
2174}
40a3a915
RV		 2175/*
2176 * vxge_hw_mgmt_reg_Write - Write Titan register.
2177 */
2178enum vxge_hw_status
2179vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
2180 enum vxge_hw_mgmt_reg_type type,
2181 u32 index, u32 offset, u64 value)
2182{
2183 enum vxge_hw_status status = VXGE_HW_OK;
2184
2185 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
2186 status = VXGE_HW_ERR_INVALID_DEVICE;
2187 goto exit;
2188 }
2189
2190 switch (type) {
2191 case vxge_hw_mgmt_reg_type_legacy:
2192 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
2193 status = VXGE_HW_ERR_INVALID_OFFSET;
2194 break;
2195 }
2196 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
2197 break;
2198 case vxge_hw_mgmt_reg_type_toc:
2199 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
2200 status = VXGE_HW_ERR_INVALID_OFFSET;
2201 break;
2202 }
2203 writeq(value, (void __iomem *)hldev->toc_reg + offset);
2204 break;
2205 case vxge_hw_mgmt_reg_type_common:
2206 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
2207 status = VXGE_HW_ERR_INVALID_OFFSET;
2208 break;
2209 }
2210 writeq(value, (void __iomem *)hldev->common_reg + offset);
2211 break;
2212 case vxge_hw_mgmt_reg_type_mrpcim:
2213 if (!(hldev->access_rights &
2214 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2215 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2216 break;
2217 }
2218 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
2219 status = VXGE_HW_ERR_INVALID_OFFSET;
2220 break;
2221 }
2222 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
2223 break;
2224 case vxge_hw_mgmt_reg_type_srpcim:
2225 if (!(hldev->access_rights &
2226 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
2227 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2228 break;
2229 }
2230 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
2231 status = VXGE_HW_ERR_INVALID_INDEX;
2232 break;
2233 }
2234 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
2235 status = VXGE_HW_ERR_INVALID_OFFSET;
2236 break;
2237 }
2238 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
2239 offset);
2240
2241 break;
2242 case vxge_hw_mgmt_reg_type_vpmgmt:
2243 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
2244 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2245 status = VXGE_HW_ERR_INVALID_INDEX;
2246 break;
2247 }
2248 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
2249 status = VXGE_HW_ERR_INVALID_OFFSET;
2250 break;
2251 }
2252 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
2253 offset);
2254 break;
2255 case vxge_hw_mgmt_reg_type_vpath:
2256 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
2257 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2258 status = VXGE_HW_ERR_INVALID_INDEX;
2259 break;
2260 }
2261 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
2262 status = VXGE_HW_ERR_INVALID_OFFSET;
2263 break;
2264 }
2265 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
2266 offset);
2267 break;
2268 default:
2269 status = VXGE_HW_ERR_INVALID_TYPE;
2270 break;
2271 }
2272exit:
2273 return status;
2274}
2275
2276/*
2277 * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
2278 * list callback
2279 * This function is callback passed to __vxge_hw_mempool_create to create memory
2280 * pool for TxD list
2281 */
2282static void
2283__vxge_hw_fifo_mempool_item_alloc(
2284 struct vxge_hw_mempool *mempoolh,
2285 u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
2286 u32 index, u32 is_last)
2287{
2288 u32 memblock_item_idx;
2289 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
2290 struct vxge_hw_fifo_txd *txdp =
2291 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
2292 struct __vxge_hw_fifo *fifo =
2293 (struct __vxge_hw_fifo *)mempoolh->userdata;
2294 void *memblock = mempoolh->memblocks_arr[memblock_index];
2295
2296 vxge_assert(txdp);
2297
2298 txdp->host_control = (u64) (size_t)
2299 __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
2300 &memblock_item_idx);
2301
2302 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
2303
2304 vxge_assert(txdl_priv);
2305
2306 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
2307
2308 /* pre-format HW's TxDL's private */
2309 txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
2310 txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
2311 txdl_priv->dma_handle = dma_object->handle;
2312 txdl_priv->memblock = memblock;
2313 txdl_priv->first_txdp = txdp;
2314 txdl_priv->next_txdl_priv = NULL;
2315 txdl_priv->alloc_frags = 0;
2316
2317 return;
2318}
2319
2320/*
2321 * __vxge_hw_fifo_create - Create a FIFO
2322 * This function creates FIFO and initializes it.
2323 */
2324enum vxge_hw_status
2325__vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
2326 struct vxge_hw_fifo_attr *attr)
2327{
2328 enum vxge_hw_status status = VXGE_HW_OK;
2329 struct __vxge_hw_fifo *fifo;
2330 struct vxge_hw_fifo_config *config;
2331 u32 txdl_size, txdl_per_memblock;
2332 struct vxge_hw_mempool_cbs fifo_mp_callback;
2333 struct __vxge_hw_virtualpath *vpath;
2334
2335 if ((vp == NULL) || (attr == NULL)) {
2336 status = VXGE_HW_ERR_INVALID_HANDLE;
2337 goto exit;
2338 }
2339 vpath = vp->vpath;
2340 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
2341
2342 txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
2343
2344 txdl_per_memblock = config->memblock_size / txdl_size;
2345
2346 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
2347 VXGE_HW_CHANNEL_TYPE_FIFO,
2348 config->fifo_blocks * txdl_per_memblock,
2349 attr->per_txdl_space, attr->userdata);
2350
2351 if (fifo == NULL) {
2352 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2353 goto exit;
2354 }
2355
2356 vpath->fifoh = fifo;
2357 fifo->nofl_db = vpath->nofl_db;
2358
2359 fifo->vp_id = vpath->vp_id;
2360 fifo->vp_reg = vpath->vp_reg;
2361 fifo->stats = &vpath->sw_stats->fifo_stats;
2362
2363 fifo->config = config;
2364
2365 /* apply "interrupts per txdl" attribute */
2366 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
2367
2368 if (fifo->config->intr)
2369 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
2370
2371 fifo->no_snoop_bits = config->no_snoop_bits;
2372
2373 /*
2374 * FIFO memory management strategy:
2375 *
2376 * TxDL split into three independent parts:
2377 * - set of TxD's
2378 * - TxD HW private part
2379 * - driver private part
2380 *
2381 * Adaptative memory allocation used. i.e. Memory allocated on
2382 * demand with the size which will fit into one memory block.
2383 * One memory block may contain more than one TxDL.
2384 *
2385 * During "reserve" operations more memory can be allocated on demand
2386 * for example due to FIFO full condition.
2387 *
2388 * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
2389 * routine which will essentially stop the channel and free resources.
2390 */
2391
2392 /* TxDL common private size == TxDL private + driver private */
2393 fifo->priv_size =
2394 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
2395 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2396 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2397
2398 fifo->per_txdl_space = attr->per_txdl_space;
2399
2400 /* recompute txdl size to be cacheline aligned */
2401 fifo->txdl_size = txdl_size;
2402 fifo->txdl_per_memblock = txdl_per_memblock;
2403
2404 fifo->txdl_term = attr->txdl_term;
2405 fifo->callback = attr->callback;
2406
2407 if (fifo->txdl_per_memblock == 0) {
2408 __vxge_hw_fifo_delete(vp);
2409 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
2410 goto exit;
2411 }
2412
2413 fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
2414
2415 fifo->mempool =
2416 __vxge_hw_mempool_create(vpath->hldev,
2417 fifo->config->memblock_size,
2418 fifo->txdl_size,
2419 fifo->priv_size,
2420 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
2421 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
2422 &fifo_mp_callback,
2423 fifo);
2424
2425 if (fifo->mempool == NULL) {
2426 __vxge_hw_fifo_delete(vp);
2427 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2428 goto exit;
2429 }
2430
2431 status = __vxge_hw_channel_initialize(&fifo->channel);
2432 if (status != VXGE_HW_OK) {
2433 __vxge_hw_fifo_delete(vp);
2434 goto exit;
2435 }
2436
2437 vxge_assert(fifo->channel.reserve_ptr);
2438exit:
2439 return status;
2440}
2441
2442/*
2443 * __vxge_hw_fifo_abort - Returns the TxD
2444 * This function terminates the TxDs of fifo
2445 */
2446enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
2447{
2448 void *txdlh;
2449
2450 for (;;) {
2451 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
2452
2453 if (txdlh == NULL)
2454 break;
2455
2456 vxge_hw_channel_dtr_complete(&fifo->channel);
2457
2458 if (fifo->txdl_term) {
2459 fifo->txdl_term(txdlh,
2460 VXGE_HW_TXDL_STATE_POSTED,
2461 fifo->channel.userdata);
2462 }
2463
2464 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
2465 }
2466
2467 return VXGE_HW_OK;
2468}
2469
2470/*
2471 * __vxge_hw_fifo_reset - Resets the fifo
2472 * This function resets the fifo during vpath reset operation
2473 */
2474enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
2475{
2476 enum vxge_hw_status status = VXGE_HW_OK;
2477
2478 __vxge_hw_fifo_abort(fifo);
2479 status = __vxge_hw_channel_reset(&fifo->channel);
2480
2481 return status;
2482}
2483
2484/*
2485 * __vxge_hw_fifo_delete - Removes the FIFO
2486 * This function freeup the memory pool and removes the FIFO
2487 */
2488enum vxge_hw_status __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
2489{
2490 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
2491
2492 __vxge_hw_fifo_abort(fifo);
2493
2494 if (fifo->mempool)
2495 __vxge_hw_mempool_destroy(fifo->mempool);
2496
2497 vp->vpath->fifoh = NULL;
2498
2499 __vxge_hw_channel_free(&fifo->channel);
2500
2501 return VXGE_HW_OK;
2502}
2503
2504/*
2505 * __vxge_hw_vpath_pci_read - Read the content of given address
2506 * in pci config space.
2507 * Read from the vpath pci config space.
2508 */
2509enum vxge_hw_status
2510__vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
2511 u32 phy_func_0, u32 offset, u32 *val)
2512{
2513 u64 val64;
2514 enum vxge_hw_status status = VXGE_HW_OK;
2515 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
2516
2517 val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
2518
2519 if (phy_func_0)
2520 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
2521
2522 writeq(val64, &vp_reg->pci_config_access_cfg1);
2523 wmb();
2524 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
2525 &vp_reg->pci_config_access_cfg2);
2526 wmb();
2527
2528 status = __vxge_hw_device_register_poll(
2529 &vp_reg->pci_config_access_cfg2,
2530 VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2531
2532 if (status != VXGE_HW_OK)
2533 goto exit;
2534
2535 val64 = readq(&vp_reg->pci_config_access_status);
2536
2537 if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
2538 status = VXGE_HW_FAIL;
2539 *val = 0;
2540 } else
2541 *val = (u32)vxge_bVALn(val64, 32, 32);
2542exit:
2543 return status;
2544}
2545
2546/*
2547 * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
2548 * Returns the function number of the vpath.
2549 */
2550u32
2551__vxge_hw_vpath_func_id_get(u32 vp_id,
2552 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
2553{
2554 u64 val64;
2555
2556 val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
2557
2558 return
2559 (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
2560}
2561
2562/*
2563 * __vxge_hw_read_rts_ds - Program RTS steering critieria
2564 */
2565static inline void
2566__vxge_hw_read_rts_ds(struct vxge_hw_vpath_reg __iomem *vpath_reg,
2567 u64 dta_struct_sel)
2568{
2569 writeq(0, &vpath_reg->rts_access_steer_ctrl);
2570 wmb();
2571 writeq(dta_struct_sel, &vpath_reg->rts_access_steer_data0);
2572 writeq(0, &vpath_reg->rts_access_steer_data1);
2573 wmb();
2574 return;
2575}
2576
2577
2578/*
2579 * __vxge_hw_vpath_card_info_get - Get the serial numbers,
2580 * part number and product description.
2581 */
2582enum vxge_hw_status
2583__vxge_hw_vpath_card_info_get(
2584 u32 vp_id,
2585 struct vxge_hw_vpath_reg __iomem *vpath_reg,
2586 struct vxge_hw_device_hw_info *hw_info)
2587{
2588 u32 i, j;
2589 u64 val64;
2590 u64 data1 = 0ULL;
2591 u64 data2 = 0ULL;
2592 enum vxge_hw_status status = VXGE_HW_OK;
2593 u8 *serial_number = hw_info->serial_number;
2594 u8 *part_number = hw_info->part_number;
2595 u8 *product_desc = hw_info->product_desc;
2596
2597 __vxge_hw_read_rts_ds(vpath_reg,
2598 VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER);
2599
2600 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2601 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
2602 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2603 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2604 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2605 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2606
2607 status = __vxge_hw_pio_mem_write64(val64,
2608 &vpath_reg->rts_access_steer_ctrl,
2609 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2610 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2611
2612 if (status != VXGE_HW_OK)
2613 return status;
2614
2615 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2616
2617 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2618 data1 = readq(&vpath_reg->rts_access_steer_data0);
2619 ((u64 *)serial_number)[0] = be64_to_cpu(data1);
2620
2621 data2 = readq(&vpath_reg->rts_access_steer_data1);
2622 ((u64 *)serial_number)[1] = be64_to_cpu(data2);
2623 status = VXGE_HW_OK;
2624 } else
2625 *serial_number = 0;
2626
2627 __vxge_hw_read_rts_ds(vpath_reg,
2628 VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER);
2629
2630 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2631 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
2632 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2633 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2634 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2635 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2636
2637 status = __vxge_hw_pio_mem_write64(val64,
2638 &vpath_reg->rts_access_steer_ctrl,
2639 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2640 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2641
2642 if (status != VXGE_HW_OK)
2643 return status;
2644
2645 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2646
2647 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2648
2649 data1 = readq(&vpath_reg->rts_access_steer_data0);
2650 ((u64 *)part_number)[0] = be64_to_cpu(data1);
2651
2652 data2 = readq(&vpath_reg->rts_access_steer_data1);
2653 ((u64 *)part_number)[1] = be64_to_cpu(data2);
2654
2655 status = VXGE_HW_OK;
2656
2657 } else
2658 *part_number = 0;
2659
2660 j = 0;
2661
2662 for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
2663 i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
2664
2665 __vxge_hw_read_rts_ds(vpath_reg, i);
2666
2667 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2668 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
2669 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2670 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2671 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2672 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2673
2674 status = __vxge_hw_pio_mem_write64(val64,
2675 &vpath_reg->rts_access_steer_ctrl,
2676 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2677 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2678
2679 if (status != VXGE_HW_OK)
2680 return status;
2681
2682 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2683
2684 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2685
2686 data1 = readq(&vpath_reg->rts_access_steer_data0);
2687 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
2688
2689 data2 = readq(&vpath_reg->rts_access_steer_data1);
2690 ((u64 *)product_desc)[j++] = be64_to_cpu(data2);
2691
2692 status = VXGE_HW_OK;
2693 } else
2694 *product_desc = 0;
2695 }
2696
2697 return status;
2698}
2699
2700/*
2701 * __vxge_hw_vpath_fw_ver_get - Get the fw version
2702 * Returns FW Version
2703 */
2704enum vxge_hw_status
2705__vxge_hw_vpath_fw_ver_get(
2706 u32 vp_id,
2707 struct vxge_hw_vpath_reg __iomem *vpath_reg,
2708 struct vxge_hw_device_hw_info *hw_info)
2709{
2710 u64 val64;
2711 u64 data1 = 0ULL;
2712 u64 data2 = 0ULL;
2713 struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
2714 struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
2715 struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
2716 struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
2717 enum vxge_hw_status status = VXGE_HW_OK;
2718
2719 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2720 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY) |
2721 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2722 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2723 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2724 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2725
2726 status = __vxge_hw_pio_mem_write64(val64,
2727 &vpath_reg->rts_access_steer_ctrl,
2728 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2729 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2730
2731 if (status != VXGE_HW_OK)
2732 goto exit;
2733
2734 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2735
2736 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2737
2738 data1 = readq(&vpath_reg->rts_access_steer_data0);
2739 data2 = readq(&vpath_reg->rts_access_steer_data1);
2740
2741 fw_date->day =
2742 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(
2743 data1);
2744 fw_date->month =
2745 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(
2746 data1);
2747 fw_date->year =
2748 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(
2749 data1);
2750
2751 snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
2752 fw_date->month, fw_date->day, fw_date->year);
2753
2754 fw_version->major =
2755 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1);
2756 fw_version->minor =
2757 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1);
2758 fw_version->build =
2759 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1);
2760
2761 snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
2762 fw_version->major, fw_version->minor, fw_version->build);
2763
2764 flash_date->day =
2765 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data2);
2766 flash_date->month =
2767 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data2);
2768 flash_date->year =
2769 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data2);
2770
2771 snprintf(flash_date->date, VXGE_HW_FW_STRLEN,
2772 "%2.2d/%2.2d/%4.4d",
2773 flash_date->month, flash_date->day, flash_date->year);
2774
2775 flash_version->major =
2776 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data2);
2777 flash_version->minor =
2778 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data2);
2779 flash_version->build =
2780 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data2);
2781
2782 snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
2783 flash_version->major, flash_version->minor,
2784 flash_version->build);
2785
2786 status = VXGE_HW_OK;
2787
2788 } else
2789 status = VXGE_HW_FAIL;
2790exit:
2791 return status;
2792}
2793
2794/*
2795 * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
2796 * Returns pci function mode
2797 */
2798u64
2799__vxge_hw_vpath_pci_func_mode_get(
2800 u32 vp_id,
2801 struct vxge_hw_vpath_reg __iomem *vpath_reg)
2802{
2803 u64 val64;
2804 u64 data1 = 0ULL;
2805 enum vxge_hw_status status = VXGE_HW_OK;
2806
2807 __vxge_hw_read_rts_ds(vpath_reg,
2808 VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE);
2809
2810 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2811 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
2812 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2813 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2814 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2815 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2816
2817 status = __vxge_hw_pio_mem_write64(val64,
2818 &vpath_reg->rts_access_steer_ctrl,
2819 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2820 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2821
2822 if (status != VXGE_HW_OK)
2823 goto exit;
2824
2825 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2826
2827 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2828 data1 = readq(&vpath_reg->rts_access_steer_data0);
2829 status = VXGE_HW_OK;
2830 } else {
2831 data1 = 0;
2832 status = VXGE_HW_FAIL;
2833 }
2834exit:
2835 return data1;
2836}
2837
2838/**
2839 * vxge_hw_device_flick_link_led - Flick (blink) link LED.
2840 * @hldev: HW device.
2841 * @on_off: TRUE if flickering to be on, FALSE to be off
2842 *
2843 * Flicker the link LED.
2844 */
2845enum vxge_hw_status
2846vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev,
2847 u64 on_off)
2848{
2849 u64 val64;
2850 enum vxge_hw_status status = VXGE_HW_OK;
2851 struct vxge_hw_vpath_reg __iomem *vp_reg;
2852
2853 if (hldev == NULL) {
2854 status = VXGE_HW_ERR_INVALID_DEVICE;
2855 goto exit;
2856 }
2857
2858 vp_reg = hldev->vpath_reg[hldev->first_vp_id];
2859
2860 writeq(0, &vp_reg->rts_access_steer_ctrl);
2861 wmb();
2862 writeq(on_off, &vp_reg->rts_access_steer_data0);
2863 writeq(0, &vp_reg->rts_access_steer_data1);
2864 wmb();
2865
2866 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2867 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL) |
2868 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2869 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2870 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2871 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2872
2873 status = __vxge_hw_pio_mem_write64(val64,
2874 &vp_reg->rts_access_steer_ctrl,
2875 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2876 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2877exit:
2878 return status;
2879}
2880
2881/*
2882 * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
2883 */
2884enum vxge_hw_status
2885__vxge_hw_vpath_rts_table_get(
2886 struct __vxge_hw_vpath_handle *vp,
2887 u32 action, u32 rts_table, u32 offset, u64 *data1, u64 *data2)
2888{
2889 u64 val64;
2890 struct __vxge_hw_virtualpath *vpath;
2891 struct vxge_hw_vpath_reg __iomem *vp_reg;
2892
2893 enum vxge_hw_status status = VXGE_HW_OK;
2894
2895 if (vp == NULL) {
2896 status = VXGE_HW_ERR_INVALID_HANDLE;
2897 goto exit;
2898 }
2899
2900 vpath = vp->vpath;
2901 vp_reg = vpath->vp_reg;
2902
2903 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
2904 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
2905 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2906 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
2907
2908 if ((rts_table ==
2909 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
2910 (rts_table ==
2911 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
2912 (rts_table ==
2913 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
2914 (rts_table ==
2915 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
2916 val64 = val64 | VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
2917 }
2918
2919 status = __vxge_hw_pio_mem_write64(val64,
2920 &vp_reg->rts_access_steer_ctrl,
2921 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2922 vpath->hldev->config.device_poll_millis);
2923
2924 if (status != VXGE_HW_OK)
2925 goto exit;
2926
2927 val64 = readq(&vp_reg->rts_access_steer_ctrl);
2928
2929 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2930
2931 *data1 = readq(&vp_reg->rts_access_steer_data0);
2932
2933 if ((rts_table ==
2934 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
2935 (rts_table ==
2936 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
2937 *data2 = readq(&vp_reg->rts_access_steer_data1);
2938 }
2939 status = VXGE_HW_OK;
2940 } else
2941 status = VXGE_HW_FAIL;
2942exit:
2943 return status;
2944}
2945
2946/*
2947 * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
2948 */
2949enum vxge_hw_status
2950__vxge_hw_vpath_rts_table_set(
2951 struct __vxge_hw_vpath_handle *vp, u32 action, u32 rts_table,
2952 u32 offset, u64 data1, u64 data2)
2953{
2954 u64 val64;
2955 struct __vxge_hw_virtualpath *vpath;
2956 enum vxge_hw_status status = VXGE_HW_OK;
2957 struct vxge_hw_vpath_reg __iomem *vp_reg;
2958
2959 if (vp == NULL) {
2960 status = VXGE_HW_ERR_INVALID_HANDLE;
2961 goto exit;
2962 }
2963
2964 vpath = vp->vpath;
2965 vp_reg = vpath->vp_reg;
2966
2967 writeq(data1, &vp_reg->rts_access_steer_data0);
2968 wmb();
2969
2970 if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
2971 (rts_table ==
2972 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
2973 writeq(data2, &vp_reg->rts_access_steer_data1);
2974 wmb();
2975 }
2976
2977 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
2978 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
2979 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2980 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
2981
2982 status = __vxge_hw_pio_mem_write64(val64,
2983 &vp_reg->rts_access_steer_ctrl,
2984 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2985 vpath->hldev->config.device_poll_millis);
2986
2987 if (status != VXGE_HW_OK)
2988 goto exit;
2989
2990 val64 = readq(&vp_reg->rts_access_steer_ctrl);
2991
2992 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)
2993 status = VXGE_HW_OK;
2994 else
2995 status = VXGE_HW_FAIL;
2996exit:
2997 return status;
2998}
2999
3000/*
3001 * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
3002 * from MAC address table.
3003 */
3004enum vxge_hw_status
3005__vxge_hw_vpath_addr_get(
3006 u32 vp_id, struct vxge_hw_vpath_reg __iomem *vpath_reg,
3007 u8 (macaddr)[ETH_ALEN], u8 (macaddr_mask)[ETH_ALEN])
3008{
3009 u32 i;
3010 u64 val64;
3011 u64 data1 = 0ULL;
3012 u64 data2 = 0ULL;
3013 enum vxge_hw_status status = VXGE_HW_OK;
3014
3015 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
3016 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY) |
3017 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
3018 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) |
3019 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
3020 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
3021
3022 status = __vxge_hw_pio_mem_write64(val64,
3023 &vpath_reg->rts_access_steer_ctrl,
3024 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
3025 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3026
3027 if (status != VXGE_HW_OK)
3028 goto exit;
3029
3030 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
3031
3032 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
3033
3034 data1 = readq(&vpath_reg->rts_access_steer_data0);
3035 data2 = readq(&vpath_reg->rts_access_steer_data1);
3036
3037 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
3038 data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
3039 data2);
3040
3041 for (i = ETH_ALEN; i > 0; i--) {
3042 macaddr[i-1] = (u8)(data1 & 0xFF);
3043 data1 >>= 8;
3044
3045 macaddr_mask[i-1] = (u8)(data2 & 0xFF);
3046 data2 >>= 8;
3047 }
3048 status = VXGE_HW_OK;
3049 } else
3050 status = VXGE_HW_FAIL;
3051exit:
3052 return status;
3053}
3054
3055/*
3056 * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3057 */
3058enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3059 struct __vxge_hw_vpath_handle *vp,
3060 enum vxge_hw_rth_algoritms algorithm,
3061 struct vxge_hw_rth_hash_types *hash_type,
3062 u16 bucket_size)
3063{
3064 u64 data0, data1;
3065 enum vxge_hw_status status = VXGE_HW_OK;
3066
3067 if (vp == NULL) {
3068 status = VXGE_HW_ERR_INVALID_HANDLE;
3069 goto exit;
3070 }
3071
3072 status = __vxge_hw_vpath_rts_table_get(vp,
3073 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3074 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3075 0, &data0, &data1);
3076
3077 data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3078 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3079
3080 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3081 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3082 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3083
3084 if (hash_type->hash_type_tcpipv4_en)
3085 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3086
3087 if (hash_type->hash_type_ipv4_en)
3088 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3089
3090 if (hash_type->hash_type_tcpipv6_en)
3091 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3092
3093 if (hash_type->hash_type_ipv6_en)
3094 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3095
3096 if (hash_type->hash_type_tcpipv6ex_en)
3097 data0 |=
3098 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3099
3100 if (hash_type->hash_type_ipv6ex_en)
3101 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3102
3103 if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3104 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3105 else
3106 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3107
3108 status = __vxge_hw_vpath_rts_table_set(vp,
3109 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3110 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3111 0, data0, 0);
3112exit:
3113 return status;
3114}
3115
3116static void
3117vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3118 u16 flag, u8 *itable)
3119{
3120 switch (flag) {
3121 case 1:
3122 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3123 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3124 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3125 itable[j]);
3126 case 2:
3127 *data0 |=
3128 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3129 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3130 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3131 itable[j]);
3132 case 3:
3133 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3134 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3135 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3136 itable[j]);
3137 case 4:
3138 *data1 |=
3139 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3140 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3141 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3142 itable[j]);
3143 default:
3144 return;
3145 }
3146}
3147/*
3148 * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3149 */
3150enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3151 struct __vxge_hw_vpath_handle **vpath_handles,
3152 u32 vpath_count,
3153 u8 *mtable,
3154 u8 *itable,
3155 u32 itable_size)
3156{
3157 u32 i, j, action, rts_table;
3158 u64 data0;
3159 u64 data1;
3160 u32 max_entries;
3161 enum vxge_hw_status status = VXGE_HW_OK;
3162 struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3163
3164 if (vp == NULL) {
3165 status = VXGE_HW_ERR_INVALID_HANDLE;
3166 goto exit;
3167 }
3168
3169 max_entries = (((u32)1) << itable_size);
3170
3171 if (vp->vpath->hldev->config.rth_it_type
3172 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3173 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3174 rts_table =
3175 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3176
3177 for (j = 0; j < max_entries; j++) {
3178
3179 data1 = 0;
3180
3181 data0 =
3182 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3183 itable[j]);
3184
3185 status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3186 action, rts_table, j, data0, data1);
3187
3188 if (status != VXGE_HW_OK)
3189 goto exit;
3190 }
3191
3192 for (j = 0; j < max_entries; j++) {
3193
3194 data1 = 0;
3195
3196 data0 =
3197 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3198 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3199 itable[j]);
3200
3201 status = __vxge_hw_vpath_rts_table_set(
3202 vpath_handles[mtable[itable[j]]], action,
3203 rts_table, j, data0, data1);
3204
3205 if (status != VXGE_HW_OK)
3206 goto exit;
3207 }
3208 } else {
3209 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3210 rts_table =
3211 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3212 for (i = 0; i < vpath_count; i++) {
3213
3214 for (j = 0; j < max_entries;) {
3215
3216 data0 = 0;
3217 data1 = 0;
3218
3219 while (j < max_entries) {
3220 if (mtable[itable[j]] != i) {
3221 j++;
3222 continue;
3223 }
3224 vxge_hw_rts_rth_data0_data1_get(j,
3225 &data0, &data1, 1, itable);
3226 j++;
3227 break;
3228 }
3229
3230 while (j < max_entries) {
3231 if (mtable[itable[j]] != i) {
3232 j++;
3233 continue;
3234 }
3235 vxge_hw_rts_rth_data0_data1_get(j,
3236 &data0, &data1, 2, itable);
3237 j++;
3238 break;
3239 }
3240
3241 while (j < max_entries) {
3242 if (mtable[itable[j]] != i) {
3243 j++;
3244 continue;
3245 }
3246 vxge_hw_rts_rth_data0_data1_get(j,
3247 &data0, &data1, 3, itable);
3248 j++;
3249 break;
3250 }
3251
3252 while (j < max_entries) {
3253 if (mtable[itable[j]] != i) {
3254 j++;
3255 continue;
3256 }
3257 vxge_hw_rts_rth_data0_data1_get(j,
3258 &data0, &data1, 4, itable);
3259 j++;
3260 break;
3261 }
3262
3263 if (data0 != 0) {
3264 status = __vxge_hw_vpath_rts_table_set(
3265 vpath_handles[i],
3266 action, rts_table,
3267 0, data0, data1);
3268
3269 if (status != VXGE_HW_OK)
3270 goto exit;
3271 }
3272 }
3273 }
3274 }
3275exit:
3276 return status;
3277}
3278
3279/**
3280 * vxge_hw_vpath_check_leak - Check for memory leak
3281 * @ringh: Handle to the ring object used for receive
3282 *
3283 * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3284 * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3285 * Returns: VXGE_HW_FAIL, if leak has occurred.
3286 *
3287 */
3288enum vxge_hw_status
3289vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3290{
3291 enum vxge_hw_status status = VXGE_HW_OK;
3292 u64 rxd_new_count, rxd_spat;
3293
3294 if (ring == NULL)
3295 return status;
3296
3297 rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3298 rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3299 rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3300
3301 if (rxd_new_count >= rxd_spat)
3302 status = VXGE_HW_FAIL;
3303
3304 return status;
3305}
3306
3307/*
3308 * __vxge_hw_vpath_mgmt_read
3309 * This routine reads the vpath_mgmt registers
3310 */
3311static enum vxge_hw_status
3312__vxge_hw_vpath_mgmt_read(
3313 struct __vxge_hw_device *hldev,
3314 struct __vxge_hw_virtualpath *vpath)
3315{
3316 u32 i, mtu = 0, max_pyld = 0;
3317 u64 val64;
3318 enum vxge_hw_status status = VXGE_HW_OK;
3319
3320 for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3321
3322 val64 = readq(&vpath->vpmgmt_reg->
3323 rxmac_cfg0_port_vpmgmt_clone[i]);
3324 max_pyld =
3325 (u32)
3326 VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3327 (val64);
3328 if (mtu < max_pyld)
3329 mtu = max_pyld;
3330 }
3331
3332 vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3333
3334 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3335
3336 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3337 if (val64 & vxge_mBIT(i))
3338 vpath->vsport_number = i;
3339 }
3340
3341 val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
3342
3343 if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
3344 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
3345 else
3346 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
3347
3348 return status;
3349}
3350
3351/*
3352 * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
3353 * This routine checks the vpath_rst_in_prog register to see if
3354 * adapter completed the reset process for the vpath
3355 */
3356enum vxge_hw_status
3357__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
3358{
3359 enum vxge_hw_status status;
3360
3361 status = __vxge_hw_device_register_poll(
3362 &vpath->hldev->common_reg->vpath_rst_in_prog,
3363 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
3364 1 << (16 - vpath->vp_id)),
3365 vpath->hldev->config.device_poll_millis);
3366
3367 return status;
3368}
3369
3370/*
3371 * __vxge_hw_vpath_reset
3372 * This routine resets the vpath on the device
3373 */
3374enum vxge_hw_status
3375__vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
3376{
3377 u64 val64;
3378 enum vxge_hw_status status = VXGE_HW_OK;
3379
3380 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
3381
3382 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
3383 &hldev->common_reg->cmn_rsthdlr_cfg0);
3384
3385 return status;
3386}
3387
3388/*
3389 * __vxge_hw_vpath_sw_reset
3390 * This routine resets the vpath structures
3391 */
3392enum vxge_hw_status
3393__vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
3394{
3395 enum vxge_hw_status status = VXGE_HW_OK;
3396 struct __vxge_hw_virtualpath *vpath;
3397
3398 vpath = (struct __vxge_hw_virtualpath *)&hldev->virtual_paths[vp_id];
3399
3400 if (vpath->ringh) {
3401 status = __vxge_hw_ring_reset(vpath->ringh);
3402 if (status != VXGE_HW_OK)
3403 goto exit;
3404 }
3405
3406 if (vpath->fifoh)
3407 status = __vxge_hw_fifo_reset(vpath->fifoh);
3408exit:
3409 return status;
3410}
3411
3412/*
3413 * __vxge_hw_vpath_prc_configure
3414 * This routine configures the prc registers of virtual path using the config
3415 * passed
3416 */
3417void
3418__vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3419{
3420 u64 val64;
3421 struct __vxge_hw_virtualpath *vpath;
3422 struct vxge_hw_vp_config *vp_config;
3423 struct vxge_hw_vpath_reg __iomem *vp_reg;
3424
3425 vpath = &hldev->virtual_paths[vp_id];
3426 vp_reg = vpath->vp_reg;
3427 vp_config = vpath->vp_config;
3428
3429 if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
3430 return;
3431
3432 val64 = readq(&vp_reg->prc_cfg1);
3433 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
3434 writeq(val64, &vp_reg->prc_cfg1);
3435
3436 val64 = readq(&vpath->vp_reg->prc_cfg6);
3437 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
3438 writeq(val64, &vpath->vp_reg->prc_cfg6);
3439
3440 val64 = readq(&vp_reg->prc_cfg7);
3441
3442 if (vpath->vp_config->ring.scatter_mode !=
3443 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
3444
3445 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
3446
3447 switch (vpath->vp_config->ring.scatter_mode) {
3448 case VXGE_HW_RING_SCATTER_MODE_A:
3449 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3450 VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
3451 break;
3452 case VXGE_HW_RING_SCATTER_MODE_B:
3453 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3454 VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
3455 break;
3456 case VXGE_HW_RING_SCATTER_MODE_C:
3457 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3458 VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
3459 break;
3460 }
3461 }
3462
3463 writeq(val64, &vp_reg->prc_cfg7);
3464
3465 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
3466 __vxge_hw_ring_first_block_address_get(
3467 vpath->ringh) >> 3), &vp_reg->prc_cfg5);
3468
3469 val64 = readq(&vp_reg->prc_cfg4);
3470 val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
3471 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
3472
3473 val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
3474 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
3475
3476 if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
3477 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
3478 else
3479 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
3480
3481 writeq(val64, &vp_reg->prc_cfg4);
3482 return;
3483}
3484
3485/*
3486 * __vxge_hw_vpath_kdfc_configure
3487 * This routine configures the kdfc registers of virtual path using the
3488 * config passed
3489 */
3490enum vxge_hw_status
3491__vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3492{
3493 u64 val64;
3494 u64 vpath_stride;
3495 enum vxge_hw_status status = VXGE_HW_OK;
3496 struct __vxge_hw_virtualpath *vpath;
3497 struct vxge_hw_vpath_reg __iomem *vp_reg;
3498
3499 vpath = &hldev->virtual_paths[vp_id];
3500 vp_reg = vpath->vp_reg;
3501 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
3502
3503 if (status != VXGE_HW_OK)
3504 goto exit;
3505
3506 val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
3507
3508 vpath->max_kdfc_db =
3509 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
3510 val64+1)/2;
3511
3512 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3513
3514 vpath->max_nofl_db = vpath->max_kdfc_db;
3515
3516 if (vpath->max_nofl_db <
3517 ((vpath->vp_config->fifo.memblock_size /
3518 (vpath->vp_config->fifo.max_frags *
3519 sizeof(struct vxge_hw_fifo_txd))) *
3520 vpath->vp_config->fifo.fifo_blocks)) {
3521
3522 return VXGE_HW_BADCFG_FIFO_BLOCKS;
3523 }
3524 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
3525 (vpath->max_nofl_db*2)-1);
3526 }
3527
3528 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
3529
3530 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
3531 &vp_reg->kdfc_fifo_trpl_ctrl);
3532
3533 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
3534
3535 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
3536 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
3537
3538 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
3539 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
3540#ifndef __BIG_ENDIAN
3541 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
3542#endif
3543 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
3544
3545 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
3546 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
3547 wmb();
3548 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
3549
3550 vpath->nofl_db =
3551 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
3552 (hldev->kdfc + (vp_id *
3553 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
3554 vpath_stride)));
3555exit:
3556 return status;
3557}
3558
3559/*
3560 * __vxge_hw_vpath_mac_configure
3561 * This routine configures the mac of virtual path using the config passed
3562 */
3563enum vxge_hw_status
3564__vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3565{
3566 u64 val64;
3567 enum vxge_hw_status status = VXGE_HW_OK;
3568 struct __vxge_hw_virtualpath *vpath;
3569 struct vxge_hw_vp_config *vp_config;
3570 struct vxge_hw_vpath_reg __iomem *vp_reg;
3571
3572 vpath = &hldev->virtual_paths[vp_id];
3573 vp_reg = vpath->vp_reg;
3574 vp_config = vpath->vp_config;
3575
3576 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
3577 vpath->vsport_number), &vp_reg->xmac_vsport_choice);
3578
3579 if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
3580
3581 val64 = readq(&vp_reg->xmac_rpa_vcfg);
3582
3583 if (vp_config->rpa_strip_vlan_tag !=
3584 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
3585 if (vp_config->rpa_strip_vlan_tag)
3586 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
3587 else
3588 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
3589 }
3590
3591 writeq(val64, &vp_reg->xmac_rpa_vcfg);
3592 val64 = readq(&vp_reg->rxmac_vcfg0);
3593
3594 if (vp_config->mtu !=
3595 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
3596 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
3597 if ((vp_config->mtu +
3598 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
3599 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
3600 vp_config->mtu +
3601 VXGE_HW_MAC_HEADER_MAX_SIZE);
3602 else
3603 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
3604 vpath->max_mtu);
3605 }
3606
3607 writeq(val64, &vp_reg->rxmac_vcfg0);
3608
3609 val64 = readq(&vp_reg->rxmac_vcfg1);
3610
3611 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
3612 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
3613
3614 if (hldev->config.rth_it_type ==
3615 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
3616 val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
3617 0x2) |
3618 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
3619 }
3620
3621 writeq(val64, &vp_reg->rxmac_vcfg1);
3622 }
3623 return status;
3624}
3625
3626/*
3627 * __vxge_hw_vpath_tim_configure
3628 * This routine configures the tim registers of virtual path using the config
3629 * passed
3630 */
3631enum vxge_hw_status
3632__vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3633{
3634 u64 val64;
3635 enum vxge_hw_status status = VXGE_HW_OK;
3636 struct __vxge_hw_virtualpath *vpath;
3637 struct vxge_hw_vpath_reg __iomem *vp_reg;
3638 struct vxge_hw_vp_config *config;
3639
3640 vpath = &hldev->virtual_paths[vp_id];
3641 vp_reg = vpath->vp_reg;
3642 config = vpath->vp_config;
3643
3644 writeq((u64)0, &vp_reg->tim_dest_addr);
3645 writeq((u64)0, &vp_reg->tim_vpath_map);
3646 writeq((u64)0, &vp_reg->tim_bitmap);
3647 writeq((u64)0, &vp_reg->tim_remap);
3648
3649 if (config->ring.enable == VXGE_HW_RING_ENABLE)
3650 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
3651 (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
3652 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
3653
3654 val64 = readq(&vp_reg->tim_pci_cfg);
3655 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
3656 writeq(val64, &vp_reg->tim_pci_cfg);
3657
3658 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3659
3660 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3661
3662 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3663 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3664 0x3ffffff);
3665 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3666 config->tti.btimer_val);
3667 }
3668
3669 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
3670
3671 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
3672 if (config->tti.timer_ac_en)
3673 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3674 else
3675 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3676 }
3677
3678 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
3679 if (config->tti.timer_ci_en)
3680 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3681 else
3682 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3683 }
3684
3685 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
3686 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
3687 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
3688 config->tti.urange_a);
3689 }
3690
3691 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
3692 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
3693 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
3694 config->tti.urange_b);
3695 }
3696
3697 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
3698 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
3699 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
3700 config->tti.urange_c);
3701 }
3702
3703 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3704 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3705
3706 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
3707 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
3708 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
3709 config->tti.uec_a);
3710 }
3711
3712 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
3713 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
3714 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
3715 config->tti.uec_b);
3716 }
3717
3718 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
3719 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
3720 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
3721 config->tti.uec_c);
3722 }
3723
3724 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
3725 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
3726 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
3727 config->tti.uec_d);
3728 }
3729
3730 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3731 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3732
3733 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
3734 if (config->tti.timer_ri_en)
3735 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3736 else
3737 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3738 }
3739
3740 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3741 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3742 0x3ffffff);
3743 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3744 config->tti.rtimer_val);
3745 }
3746
3747 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
3748 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
3749 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
3750 config->tti.util_sel);
3751 }
3752
3753 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3754 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3755 0x3ffffff);
3756 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3757 config->tti.ltimer_val);
3758 }
3759
3760 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3761 }
3762
3763 if (config->ring.enable == VXGE_HW_RING_ENABLE) {
3764
3765 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3766
3767 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3768 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3769 0x3ffffff);
3770 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3771 config->rti.btimer_val);
3772 }
3773
3774 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
3775
3776 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
3777 if (config->rti.timer_ac_en)
3778 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3779 else
3780 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3781 }
3782
3783 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
3784 if (config->rti.timer_ci_en)
3785 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3786 else
3787 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3788 }
3789
3790 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
3791 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
3792 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
3793 config->rti.urange_a);
3794 }
3795
3796 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
3797 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
3798 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
3799 config->rti.urange_b);
3800 }
3801
3802 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
3803 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
3804 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
3805 config->rti.urange_c);
3806 }
3807
3808 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3809 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3810
3811 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
3812 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
3813 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
3814 config->rti.uec_a);
3815 }
3816
3817 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
3818 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
3819 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
3820 config->rti.uec_b);
3821 }
3822
3823 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
3824 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
3825 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
3826 config->rti.uec_c);
3827 }
3828
3829 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
3830 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
3831 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
3832 config->rti.uec_d);
3833 }
3834
3835 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3836 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
3837
3838 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
3839 if (config->rti.timer_ri_en)
3840 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3841 else
3842 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3843 }
3844
3845 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3846 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3847 0x3ffffff);
3848 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3849 config->rti.rtimer_val);
3850 }
3851
3852 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
3853 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
3854 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
3855 config->rti.util_sel);
3856 }
3857
3858 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3859 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3860 0x3ffffff);
3861 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3862 config->rti.ltimer_val);
3863 }
3864
3865 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
3866 }
3867
3868 val64 = 0;
3869 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3870 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3871 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3872 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3873 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3874 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3875
3876 return status;
3877}
3878
eb5f10c2
SH		 3879void
3880vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
3881{
3882 struct __vxge_hw_virtualpath *vpath;
3883 struct vxge_hw_vpath_reg __iomem *vp_reg;
3884 struct vxge_hw_vp_config *config;
3885 u64 val64;
3886
3887 vpath = &hldev->virtual_paths[vp_id];
3888 vp_reg = vpath->vp_reg;
3889 config = vpath->vp_config;
3890
3891 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3892 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3893
3894 if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
3895 config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
3896 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3897 writeq(val64,
3898 &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3899 }
3900 }
3901 return;
3902}
40a3a915
RV		 3903/*
3904 * __vxge_hw_vpath_initialize
3905 * This routine is the final phase of init which initializes the
3906 * registers of the vpath using the configuration passed.
3907 */
3908enum vxge_hw_status
3909__vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
3910{
3911 u64 val64;
3912 u32 val32;
3913 enum vxge_hw_status status = VXGE_HW_OK;
3914 struct __vxge_hw_virtualpath *vpath;
3915 struct vxge_hw_vpath_reg __iomem *vp_reg;
3916
3917 vpath = &hldev->virtual_paths[vp_id];
3918
3919 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
3920 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
3921 goto exit;
3922 }
3923 vp_reg = vpath->vp_reg;
3924
3925 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
3926
3927 if (status != VXGE_HW_OK)
3928 goto exit;
3929
3930 status = __vxge_hw_vpath_mac_configure(hldev, vp_id);
3931
3932 if (status != VXGE_HW_OK)
3933 goto exit;
3934
3935 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
3936
3937 if (status != VXGE_HW_OK)
3938 goto exit;
3939
3940 status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
3941
3942 if (status != VXGE_HW_OK)
3943 goto exit;
3944
40a3a915
RV		 3945 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
3946
3947 /* Get MRRS value from device control */
3948 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
3949
3950 if (status == VXGE_HW_OK) {
3951 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
3952 val64 &=
3953 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
3954 val64 |=
3955 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
3956
3957 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
3958 }
3959
3960 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
3961 val64 |=
3962 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
3963 VXGE_HW_MAX_PAYLOAD_SIZE_512);
3964
3965 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
3966 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
3967
3968exit:
3969 return status;
3970}
3971
3972/*
3973 * __vxge_hw_vp_initialize - Initialize Virtual Path structure
3974 * This routine is the initial phase of init which resets the vpath and
3975 * initializes the software support structures.
3976 */
3977enum vxge_hw_status
3978__vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
3979 struct vxge_hw_vp_config *config)
3980{
3981 struct __vxge_hw_virtualpath *vpath;
3982 enum vxge_hw_status status = VXGE_HW_OK;
3983
3984 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
3985 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
3986 goto exit;
3987 }
3988
3989 vpath = &hldev->virtual_paths[vp_id];
3990
3991 vpath->vp_id = vp_id;
3992 vpath->vp_open = VXGE_HW_VP_OPEN;
3993 vpath->hldev = hldev;
3994 vpath->vp_config = config;
3995 vpath->vp_reg = hldev->vpath_reg[vp_id];
3996 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
3997
3998 __vxge_hw_vpath_reset(hldev, vp_id);
3999
4000 status = __vxge_hw_vpath_reset_check(vpath);
4001
4002 if (status != VXGE_HW_OK) {
4003 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4004 goto exit;
4005 }
4006
4007 status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4008
4009 if (status != VXGE_HW_OK) {
4010 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4011 goto exit;
4012 }
4013
4014 INIT_LIST_HEAD(&vpath->vpath_handles);
4015
4016 vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4017
4018 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4019 hldev->tim_int_mask1, vp_id);
4020
4021 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4022
4023 if (status != VXGE_HW_OK)
4024 __vxge_hw_vp_terminate(hldev, vp_id);
4025exit:
4026 return status;
4027}
4028
4029/*
4030 * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4031 * This routine closes all channels it opened and freeup memory
4032 */
4033void
4034__vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4035{
4036 struct __vxge_hw_virtualpath *vpath;
4037
4038 vpath = &hldev->virtual_paths[vp_id];
4039
4040 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4041 goto exit;
4042
4043 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4044 vpath->hldev->tim_int_mask1, vpath->vp_id);
4045 hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4046
4047 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4048exit:
4049 return;
4050}
4051
4052/*
4053 * vxge_hw_vpath_mtu_set - Set MTU.
4054 * Set new MTU value. Example, to use jumbo frames:
4055 * vxge_hw_vpath_mtu_set(my_device, 9600);
4056 */
4057enum vxge_hw_status
4058vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4059{
4060 u64 val64;
4061 enum vxge_hw_status status = VXGE_HW_OK;
4062 struct __vxge_hw_virtualpath *vpath;
4063
4064 if (vp == NULL) {
4065 status = VXGE_HW_ERR_INVALID_HANDLE;
4066 goto exit;
4067 }
4068 vpath = vp->vpath;
4069
4070 new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4071
4072 if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4073 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4074
4075 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4076
4077 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4078 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4079
4080 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4081
4082 vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4083
4084exit:
4085 return status;
4086}
4087
4088/*
4089 * vxge_hw_vpath_open - Open a virtual path on a given adapter
4090 * This function is used to open access to virtual path of an
4091 * adapter for offload, GRO operations. This function returns
4092 * synchronously.
4093 */
4094enum vxge_hw_status
4095vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4096 struct vxge_hw_vpath_attr *attr,
4097 struct __vxge_hw_vpath_handle **vpath_handle)
4098{
4099 struct __vxge_hw_virtualpath *vpath;
4100 struct __vxge_hw_vpath_handle *vp;
4101 enum vxge_hw_status status;
4102
4103 vpath = &hldev->virtual_paths[attr->vp_id];
4104
4105 if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4106 status = VXGE_HW_ERR_INVALID_STATE;
4107 goto vpath_open_exit1;
4108 }
4109
4110 status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4111 &hldev->config.vp_config[attr->vp_id]);
4112
4113 if (status != VXGE_HW_OK)
4114 goto vpath_open_exit1;
4115
4116 vp = (struct __vxge_hw_vpath_handle *)
4117 vmalloc(sizeof(struct __vxge_hw_vpath_handle));
4118 if (vp == NULL) {
4119 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4120 goto vpath_open_exit2;
4121 }
4122
4123 memset(vp, 0, sizeof(struct __vxge_hw_vpath_handle));
4124
4125 vp->vpath = vpath;
4126
4127 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4128 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4129 if (status != VXGE_HW_OK)
4130 goto vpath_open_exit6;
4131 }
4132
4133 if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4134 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4135 if (status != VXGE_HW_OK)
4136 goto vpath_open_exit7;
4137
4138 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4139 }
4140
4141 vpath->fifoh->tx_intr_num =
4142 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4143 VXGE_HW_VPATH_INTR_TX;
4144
4145 vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4146 VXGE_HW_BLOCK_SIZE);
4147
4148 if (vpath->stats_block == NULL) {
4149 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4150 goto vpath_open_exit8;
4151 }
4152
4153 vpath->hw_stats = (struct vxge_hw_vpath_stats_hw_info *)vpath->
4154 stats_block->memblock;
4155 memset(vpath->hw_stats, 0,
4156 sizeof(struct vxge_hw_vpath_stats_hw_info));
4157
4158 hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4159 vpath->hw_stats;
4160
4161 vpath->hw_stats_sav =
4162 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4163 memset(vpath->hw_stats_sav, 0,
4164 sizeof(struct vxge_hw_vpath_stats_hw_info));
4165
4166 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4167
4168 status = vxge_hw_vpath_stats_enable(vp);
4169 if (status != VXGE_HW_OK)
4170 goto vpath_open_exit8;
4171
4172 list_add(&vp->item, &vpath->vpath_handles);
4173
4174 hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4175
4176 *vpath_handle = vp;
4177
4178 attr->fifo_attr.userdata = vpath->fifoh;
4179 attr->ring_attr.userdata = vpath->ringh;
4180
4181 return VXGE_HW_OK;
4182
4183vpath_open_exit8:
4184 if (vpath->ringh != NULL)
4185 __vxge_hw_ring_delete(vp);
4186vpath_open_exit7:
4187 if (vpath->fifoh != NULL)
4188 __vxge_hw_fifo_delete(vp);
4189vpath_open_exit6:
4190 vfree(vp);
4191vpath_open_exit2:
4192 __vxge_hw_vp_terminate(hldev, attr->vp_id);
4193vpath_open_exit1:
4194
4195 return status;
4196}
4197
4198/**
4199 * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4200 * (vpath) open
4201 * @vp: Handle got from previous vpath open
4202 *
4203 * This function is used to close access to virtual path opened
4204 * earlier.
4205 */
4206void
4207vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4208{
4209 struct __vxge_hw_virtualpath *vpath = NULL;
4210 u64 new_count, val64, val164;
4211 struct __vxge_hw_ring *ring;
4212
4213 vpath = vp->vpath;
4214 ring = vpath->ringh;
4215
4216 new_count = readq(&vpath->vp_reg->rxdmem_size);
4217 new_count &= 0x1fff;
4218 val164 = (VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count));
4219
4220 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4221 &vpath->vp_reg->prc_rxd_doorbell);
4222 readl(&vpath->vp_reg->prc_rxd_doorbell);
4223
4224 val164 /= 2;
4225 val64 = readq(&vpath->vp_reg->prc_cfg6);
4226 val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4227 val64 &= 0x1ff;
4228
4229 /*
4230 * Each RxD is of 4 qwords
4231 */
4232 new_count -= (val64 + 1);
4233 val64 = min(val164, new_count) / 4;
4234
4235 ring->rxds_limit = min(ring->rxds_limit, val64);
4236 if (ring->rxds_limit < 4)
4237 ring->rxds_limit = 4;
4238}
4239
4240/*
4241 * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4242 * This function is used to close access to virtual path opened
4243 * earlier.
4244 */
4245enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4246{
4247 struct __vxge_hw_virtualpath *vpath = NULL;
4248 struct __vxge_hw_device *devh = NULL;
4249 u32 vp_id = vp->vpath->vp_id;
4250 u32 is_empty = TRUE;
4251 enum vxge_hw_status status = VXGE_HW_OK;
4252
4253 vpath = vp->vpath;
4254 devh = vpath->hldev;
4255
4256 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4257 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4258 goto vpath_close_exit;
4259 }
4260
4261 list_del(&vp->item);
4262
4263 if (!list_empty(&vpath->vpath_handles)) {
4264 list_add(&vp->item, &vpath->vpath_handles);
4265 is_empty = FALSE;
4266 }
4267
4268 if (!is_empty) {
4269 status = VXGE_HW_FAIL;
4270 goto vpath_close_exit;
4271 }
4272
4273 devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
4274
4275 if (vpath->ringh != NULL)
4276 __vxge_hw_ring_delete(vp);
4277
4278 if (vpath->fifoh != NULL)
4279 __vxge_hw_fifo_delete(vp);
4280
4281 if (vpath->stats_block != NULL)
4282 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
4283
4284 vfree(vp);
4285
4286 __vxge_hw_vp_terminate(devh, vp_id);
4287
4288 vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4289
4290vpath_close_exit:
4291 return status;
4292}
4293
4294/*
4295 * vxge_hw_vpath_reset - Resets vpath
4296 * This function is used to request a reset of vpath
4297 */
4298enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
4299{
4300 enum vxge_hw_status status;
4301 u32 vp_id;
4302 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4303
4304 vp_id = vpath->vp_id;
4305
4306 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4307 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4308 goto exit;
4309 }
4310
4311 status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
4312 if (status == VXGE_HW_OK)
4313 vpath->sw_stats->soft_reset_cnt++;
4314exit:
4315 return status;
4316}
4317
4318/*
4319 * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
4320 * This function poll's for the vpath reset completion and re initializes
4321 * the vpath.
4322 */
4323enum vxge_hw_status
4324vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
4325{
4326 struct __vxge_hw_virtualpath *vpath = NULL;
4327 enum vxge_hw_status status;
4328 struct __vxge_hw_device *hldev;
4329 u32 vp_id;
4330
4331 vp_id = vp->vpath->vp_id;
4332 vpath = vp->vpath;
4333 hldev = vpath->hldev;
4334
4335 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4336 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4337 goto exit;
4338 }
4339
4340 status = __vxge_hw_vpath_reset_check(vpath);
4341 if (status != VXGE_HW_OK)
4342 goto exit;
4343
4344 status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
4345 if (status != VXGE_HW_OK)
4346 goto exit;
4347
4348 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4349 if (status != VXGE_HW_OK)
4350 goto exit;
4351
4352 if (vpath->ringh != NULL)
4353 __vxge_hw_vpath_prc_configure(hldev, vp_id);
4354
4355 memset(vpath->hw_stats, 0,
4356 sizeof(struct vxge_hw_vpath_stats_hw_info));
4357
4358 memset(vpath->hw_stats_sav, 0,
4359 sizeof(struct vxge_hw_vpath_stats_hw_info));
4360
4361 writeq(vpath->stats_block->dma_addr,
4362 &vpath->vp_reg->stats_cfg);
4363
4364 status = vxge_hw_vpath_stats_enable(vp);
4365
4366exit:
4367 return status;
4368}
4369
4370/*
4371 * vxge_hw_vpath_enable - Enable vpath.
4372 * This routine clears the vpath reset thereby enabling a vpath
4373 * to start forwarding frames and generating interrupts.
4374 */
4375void
4376vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
4377{
4378 struct __vxge_hw_device *hldev;
4379 u64 val64;
4380
4381 hldev = vp->vpath->hldev;
4382
4383 val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
4384 1 << (16 - vp->vpath->vp_id));
4385
4386 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4387 &hldev->common_reg->cmn_rsthdlr_cfg1);
4388}
4389
4390/*
4391 * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4392 * Enable the DMA vpath statistics. The function is to be called to re-enable
4393 * the adapter to update stats into the host memory
4394 */
4395enum vxge_hw_status
4396vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4397{
4398 enum vxge_hw_status status = VXGE_HW_OK;
4399 struct __vxge_hw_virtualpath *vpath;
4400
4401 vpath = vp->vpath;
4402
4403 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4404 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4405 goto exit;
4406 }
4407
4408 memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4409 sizeof(struct vxge_hw_vpath_stats_hw_info));
4410
4411 status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4412exit:
4413 return status;
4414}
4415
4416/*
4417 * __vxge_hw_vpath_stats_access - Get the statistics from the given location
4418 * and offset and perform an operation
4419 */
4420enum vxge_hw_status
4421__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
4422 u32 operation, u32 offset, u64 *stat)
4423{
4424 u64 val64;
4425 enum vxge_hw_status status = VXGE_HW_OK;
4426 struct vxge_hw_vpath_reg __iomem *vp_reg;
4427
4428 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4429 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4430 goto vpath_stats_access_exit;
4431 }
4432
4433 vp_reg = vpath->vp_reg;
4434
4435 val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
4436 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
4437 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
4438
4439 status = __vxge_hw_pio_mem_write64(val64,
4440 &vp_reg->xmac_stats_access_cmd,
4441 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
4442 vpath->hldev->config.device_poll_millis);
4443
4444 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
4445 *stat = readq(&vp_reg->xmac_stats_access_data);
4446 else
4447 *stat = 0;
4448
4449vpath_stats_access_exit:
4450 return status;
4451}
4452
4453/*
4454 * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
4455 */
4456enum vxge_hw_status
4457__vxge_hw_vpath_xmac_tx_stats_get(
4458 struct __vxge_hw_virtualpath *vpath,
4459 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
4460{
4461 u64 *val64;
4462 int i;
4463 u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
4464 enum vxge_hw_status status = VXGE_HW_OK;
4465
4466 val64 = (u64 *) vpath_tx_stats;
4467
4468 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4469 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4470 goto exit;
4471 }
4472
4473 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
4474 status = __vxge_hw_vpath_stats_access(vpath,
4475 VXGE_HW_STATS_OP_READ,
4476 offset, val64);
4477 if (status != VXGE_HW_OK)
4478 goto exit;
4479 offset++;
4480 val64++;
4481 }
4482exit:
4483 return status;
4484}
4485
4486/*
4487 * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
4488 */
4489enum vxge_hw_status
4490__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
4491 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
4492{
4493 u64 *val64;
4494 enum vxge_hw_status status = VXGE_HW_OK;
4495 int i;
4496 u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
4497 val64 = (u64 *) vpath_rx_stats;
4498
4499 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4500 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4501 goto exit;
4502 }
4503 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
4504 status = __vxge_hw_vpath_stats_access(vpath,
4505 VXGE_HW_STATS_OP_READ,
4506 offset >> 3, val64);
4507 if (status != VXGE_HW_OK)
4508 goto exit;
4509
4510 offset += 8;
4511 val64++;
4512 }
4513exit:
4514 return status;
4515}
4516
4517/*
4518 * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
4519 */
4520enum vxge_hw_status __vxge_hw_vpath_stats_get(
4521 struct __vxge_hw_virtualpath *vpath,
4522 struct vxge_hw_vpath_stats_hw_info *hw_stats)
4523{
4524 u64 val64;
4525 enum vxge_hw_status status = VXGE_HW_OK;
4526 struct vxge_hw_vpath_reg __iomem *vp_reg;
4527
4528 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4529 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4530 goto exit;
4531 }
4532 vp_reg = vpath->vp_reg;
4533
4534 val64 = readq(&vp_reg->vpath_debug_stats0);
4535 hw_stats->ini_num_mwr_sent =
4536 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
4537
4538 val64 = readq(&vp_reg->vpath_debug_stats1);
4539 hw_stats->ini_num_mrd_sent =
4540 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
4541
4542 val64 = readq(&vp_reg->vpath_debug_stats2);
4543 hw_stats->ini_num_cpl_rcvd =
4544 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
4545
4546 val64 = readq(&vp_reg->vpath_debug_stats3);
4547 hw_stats->ini_num_mwr_byte_sent =
4548 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
4549
4550 val64 = readq(&vp_reg->vpath_debug_stats4);
4551 hw_stats->ini_num_cpl_byte_rcvd =
4552 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
4553
4554 val64 = readq(&vp_reg->vpath_debug_stats5);
4555 hw_stats->wrcrdtarb_xoff =
4556 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
4557
4558 val64 = readq(&vp_reg->vpath_debug_stats6);
4559 hw_stats->rdcrdtarb_xoff =
4560 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
4561
4562 val64 = readq(&vp_reg->vpath_genstats_count01);
4563 hw_stats->vpath_genstats_count0 =
4564 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
4565 val64);
4566
4567 val64 = readq(&vp_reg->vpath_genstats_count01);
4568 hw_stats->vpath_genstats_count1 =
4569 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
4570 val64);
4571
4572 val64 = readq(&vp_reg->vpath_genstats_count23);
4573 hw_stats->vpath_genstats_count2 =
4574 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
4575 val64);
4576
4577 val64 = readq(&vp_reg->vpath_genstats_count01);
4578 hw_stats->vpath_genstats_count3 =
4579 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
4580 val64);
4581
4582 val64 = readq(&vp_reg->vpath_genstats_count4);
4583 hw_stats->vpath_genstats_count4 =
4584 (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
4585 val64);
4586
4587 val64 = readq(&vp_reg->vpath_genstats_count5);
4588 hw_stats->vpath_genstats_count5 =
4589 (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
4590 val64);
4591
4592 status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
4593 if (status != VXGE_HW_OK)
4594 goto exit;
4595
4596 status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
4597 if (status != VXGE_HW_OK)
4598 goto exit;
4599
4600 VXGE_HW_VPATH_STATS_PIO_READ(
4601 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
4602
4603 hw_stats->prog_event_vnum0 =
4604 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
4605
4606 hw_stats->prog_event_vnum1 =
4607 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
4608
4609 VXGE_HW_VPATH_STATS_PIO_READ(
4610 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
4611
4612 hw_stats->prog_event_vnum2 =
4613 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
4614
4615 hw_stats->prog_event_vnum3 =
4616 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
4617
4618 val64 = readq(&vp_reg->rx_multi_cast_stats);
4619 hw_stats->rx_multi_cast_frame_discard =
4620 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
4621
4622 val64 = readq(&vp_reg->rx_frm_transferred);
4623 hw_stats->rx_frm_transferred =
4624 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
4625
4626 val64 = readq(&vp_reg->rxd_returned);
4627 hw_stats->rxd_returned =
4628 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
4629
4630 val64 = readq(&vp_reg->dbg_stats_rx_mpa);
4631 hw_stats->rx_mpa_len_fail_frms =
4632 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
4633 hw_stats->rx_mpa_mrk_fail_frms =
4634 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
4635 hw_stats->rx_mpa_crc_fail_frms =
4636 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
4637
4638 val64 = readq(&vp_reg->dbg_stats_rx_fau);
4639 hw_stats->rx_permitted_frms =
4640 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
4641 hw_stats->rx_vp_reset_discarded_frms =
4642 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
4643 hw_stats->rx_wol_frms =
4644 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
4645
4646 val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
4647 hw_stats->tx_vp_reset_discarded_frms =
4648 (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
4649 val64);
4650exit:
4651 return status;
4652}
4653
4654/*
4655 * __vxge_hw_blockpool_create - Create block pool
4656 */
4657
4658enum vxge_hw_status
4659__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
4660 struct __vxge_hw_blockpool *blockpool,
4661 u32 pool_size,
4662 u32 pool_max)
4663{
4664 u32 i;
4665 struct __vxge_hw_blockpool_entry *entry = NULL;
4666 void *memblock;
4667 dma_addr_t dma_addr;
4668 struct pci_dev *dma_handle;
4669 struct pci_dev *acc_handle;
4670 enum vxge_hw_status status = VXGE_HW_OK;
4671
4672 if (blockpool == NULL) {
4673 status = VXGE_HW_FAIL;
4674 goto blockpool_create_exit;
4675 }
4676
4677 blockpool->hldev = hldev;
4678 blockpool->block_size = VXGE_HW_BLOCK_SIZE;
4679 blockpool->pool_size = 0;
4680 blockpool->pool_max = pool_max;
4681 blockpool->req_out = 0;
4682
4683 INIT_LIST_HEAD(&blockpool->free_block_list);
4684 INIT_LIST_HEAD(&blockpool->free_entry_list);
4685
4686 for (i = 0; i < pool_size + pool_max; i++) {
4687 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
4688 GFP_KERNEL);
4689 if (entry == NULL) {
4690 __vxge_hw_blockpool_destroy(blockpool);
4691 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4692 goto blockpool_create_exit;
4693 }
4694 list_add(&entry->item, &blockpool->free_entry_list);
4695 }
4696
4697 for (i = 0; i < pool_size; i++) {
4698
4699 memblock = vxge_os_dma_malloc(
4700 hldev->pdev,
4701 VXGE_HW_BLOCK_SIZE,
4702 &dma_handle,
4703 &acc_handle);
4704
4705 if (memblock == NULL) {
4706 __vxge_hw_blockpool_destroy(blockpool);
4707 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4708 goto blockpool_create_exit;
4709 }
4710
4711 dma_addr = pci_map_single(hldev->pdev, memblock,
4712 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
4713
4714 if (unlikely(pci_dma_mapping_error(hldev->pdev,
4715 dma_addr))) {
4716
4717 vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
4718 __vxge_hw_blockpool_destroy(blockpool);
4719 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4720 goto blockpool_create_exit;
4721 }
4722
4723 if (!list_empty(&blockpool->free_entry_list))
4724 entry = (struct __vxge_hw_blockpool_entry *)
4725 list_first_entry(&blockpool->free_entry_list,
4726 struct __vxge_hw_blockpool_entry,
4727 item);
4728
4729 if (entry == NULL)
4730 entry =
4731 kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
4732 GFP_KERNEL);
4733 if (entry != NULL) {
4734 list_del(&entry->item);
4735 entry->length = VXGE_HW_BLOCK_SIZE;
4736 entry->memblock = memblock;
4737 entry->dma_addr = dma_addr;
4738 entry->acc_handle = acc_handle;
4739 entry->dma_handle = dma_handle;
4740 list_add(&entry->item,
4741 &blockpool->free_block_list);
4742 blockpool->pool_size++;
4743 } else {
4744 __vxge_hw_blockpool_destroy(blockpool);
4745 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4746 goto blockpool_create_exit;
4747 }
4748 }
4749
4750blockpool_create_exit:
4751 return status;
4752}
4753
4754/*
4755 * __vxge_hw_blockpool_destroy - Deallocates the block pool
4756 */
4757
4758void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
4759{
4760
4761 struct __vxge_hw_device *hldev;
4762 struct list_head *p, *n;
4763 u16 ret;
4764
4765 if (blockpool == NULL) {
4766 ret = 1;
4767 goto exit;
4768 }
4769
4770 hldev = blockpool->hldev;
4771
4772 list_for_each_safe(p, n, &blockpool->free_block_list) {
4773
4774 pci_unmap_single(hldev->pdev,
4775 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
4776 ((struct __vxge_hw_blockpool_entry *)p)->length,
4777 PCI_DMA_BIDIRECTIONAL);
4778
4779 vxge_os_dma_free(hldev->pdev,
4780 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
4781 &((struct __vxge_hw_blockpool_entry *) p)->acc_handle);
4782
4783 list_del(
4784 &((struct __vxge_hw_blockpool_entry *)p)->item);
4785 kfree(p);
4786 blockpool->pool_size--;
4787 }
4788
4789 list_for_each_safe(p, n, &blockpool->free_entry_list) {
4790 list_del(
4791 &((struct __vxge_hw_blockpool_entry *)p)->item);
4792 kfree((void *)p);
4793 }
4794 ret = 0;
4795exit:
4796 return;
4797}
4798
4799/*
4800 * __vxge_hw_blockpool_blocks_add - Request additional blocks
4801 */
4802static
4803void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
4804{
4805 u32 nreq = 0, i;
4806
4807 if ((blockpool->pool_size + blockpool->req_out) <
4808 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
4809 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
4810 blockpool->req_out += nreq;
4811 }
4812
4813 for (i = 0; i < nreq; i++)
4814 vxge_os_dma_malloc_async(
4815 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
4816 blockpool->hldev, VXGE_HW_BLOCK_SIZE);
4817}
4818
4819/*
4820 * __vxge_hw_blockpool_blocks_remove - Free additional blocks
4821 */
4822static
4823void __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
4824{
4825 struct list_head *p, *n;
4826
4827 list_for_each_safe(p, n, &blockpool->free_block_list) {
4828
4829 if (blockpool->pool_size < blockpool->pool_max)
4830 break;
4831
4832 pci_unmap_single(
4833 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
4834 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
4835 ((struct __vxge_hw_blockpool_entry *)p)->length,
4836 PCI_DMA_BIDIRECTIONAL);
4837
4838 vxge_os_dma_free(
4839 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
4840 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
4841 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
4842
4843 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
4844
4845 list_add(p, &blockpool->free_entry_list);
4846
4847 blockpool->pool_size--;
4848
4849 }
4850}
4851
4852/*
4853 * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
4854 * Adds a block to block pool
4855 */
4856void vxge_hw_blockpool_block_add(
4857 struct __vxge_hw_device *devh,
4858 void *block_addr,
4859 u32 length,
4860 struct pci_dev *dma_h,
4861 struct pci_dev *acc_handle)
4862{
4863 struct __vxge_hw_blockpool *blockpool;
4864 struct __vxge_hw_blockpool_entry *entry = NULL;
4865 dma_addr_t dma_addr;
4866 enum vxge_hw_status status = VXGE_HW_OK;
4867 u32 req_out;
4868
4869 blockpool = &devh->block_pool;
4870
4871 if (block_addr == NULL) {
4872 blockpool->req_out--;
4873 status = VXGE_HW_FAIL;
4874 goto exit;
4875 }
4876
4877 dma_addr = pci_map_single(devh->pdev, block_addr, length,
4878 PCI_DMA_BIDIRECTIONAL);
4879
4880 if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
4881
4882 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
4883 blockpool->req_out--;
4884 status = VXGE_HW_FAIL;
4885 goto exit;
4886 }
4887
4888
4889 if (!list_empty(&blockpool->free_entry_list))
4890 entry = (struct __vxge_hw_blockpool_entry *)
4891 list_first_entry(&blockpool->free_entry_list,
4892 struct __vxge_hw_blockpool_entry,
4893 item);
4894
4895 if (entry == NULL)
4896 entry = (struct __vxge_hw_blockpool_entry *)
4897 vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
4898 else
4899 list_del(&entry->item);
4900
4901 if (entry != NULL) {
4902 entry->length = length;
4903 entry->memblock = block_addr;
4904 entry->dma_addr = dma_addr;
4905 entry->acc_handle = acc_handle;
4906 entry->dma_handle = dma_h;
4907 list_add(&entry->item, &blockpool->free_block_list);
4908 blockpool->pool_size++;
4909 status = VXGE_HW_OK;
4910 } else
4911 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4912
4913 blockpool->req_out--;
4914
4915 req_out = blockpool->req_out;
4916exit:
4917 return;
4918}
4919
4920/*
4921 * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
4922 * Allocates a block of memory of given size, either from block pool
4923 * or by calling vxge_os_dma_malloc()
4924 */
4925void *
4926__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
4927 struct vxge_hw_mempool_dma *dma_object)
4928{
4929 struct __vxge_hw_blockpool_entry *entry = NULL;
4930 struct __vxge_hw_blockpool *blockpool;
4931 void *memblock = NULL;
4932 enum vxge_hw_status status = VXGE_HW_OK;
4933
4934 blockpool = &devh->block_pool;
4935
4936 if (size != blockpool->block_size) {
4937
4938 memblock = vxge_os_dma_malloc(devh->pdev, size,
4939 &dma_object->handle,
4940 &dma_object->acc_handle);
4941
4942 if (memblock == NULL) {
4943 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4944 goto exit;
4945 }
4946
4947 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
4948 PCI_DMA_BIDIRECTIONAL);
4949
4950 if (unlikely(pci_dma_mapping_error(devh->pdev,
4951 dma_object->addr))) {
4952 vxge_os_dma_free(devh->pdev, memblock,
4953 &dma_object->acc_handle);
4954 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4955 goto exit;
4956 }
4957
4958 } else {
4959
4960 if (!list_empty(&blockpool->free_block_list))
4961 entry = (struct __vxge_hw_blockpool_entry *)
4962 list_first_entry(&blockpool->free_block_list,
4963 struct __vxge_hw_blockpool_entry,
4964 item);
4965
4966 if (entry != NULL) {
4967 list_del(&entry->item);
4968 dma_object->addr = entry->dma_addr;
4969 dma_object->handle = entry->dma_handle;
4970 dma_object->acc_handle = entry->acc_handle;
4971 memblock = entry->memblock;
4972
4973 list_add(&entry->item,
4974 &blockpool->free_entry_list);
4975 blockpool->pool_size--;
4976 }
4977
4978 if (memblock != NULL)
4979 __vxge_hw_blockpool_blocks_add(blockpool);
4980 }
4981exit:
4982 return memblock;
4983}
4984
4985/*
4986 * __vxge_hw_blockpool_free - Frees the memory allcoated with
4987 __vxge_hw_blockpool_malloc
4988 */
4989void
4990__vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
4991 void *memblock, u32 size,
4992 struct vxge_hw_mempool_dma *dma_object)
4993{
4994 struct __vxge_hw_blockpool_entry *entry = NULL;
4995 struct __vxge_hw_blockpool *blockpool;
4996 enum vxge_hw_status status = VXGE_HW_OK;
4997
4998 blockpool = &devh->block_pool;
4999
5000 if (size != blockpool->block_size) {
5001 pci_unmap_single(devh->pdev, dma_object->addr, size,
5002 PCI_DMA_BIDIRECTIONAL);
5003 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
5004 } else {
5005
5006 if (!list_empty(&blockpool->free_entry_list))
5007 entry = (struct __vxge_hw_blockpool_entry *)
5008 list_first_entry(&blockpool->free_entry_list,
5009 struct __vxge_hw_blockpool_entry,
5010 item);
5011
5012 if (entry == NULL)
5013 entry = (struct __vxge_hw_blockpool_entry *)
5014 vmalloc(sizeof(
5015 struct __vxge_hw_blockpool_entry));
5016 else
5017 list_del(&entry->item);
5018
5019 if (entry != NULL) {
5020 entry->length = size;
5021 entry->memblock = memblock;
5022 entry->dma_addr = dma_object->addr;
5023 entry->acc_handle = dma_object->acc_handle;
5024 entry->dma_handle = dma_object->handle;
5025 list_add(&entry->item,
5026 &blockpool->free_block_list);
5027 blockpool->pool_size++;
5028 status = VXGE_HW_OK;
5029 } else
5030 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5031
5032 if (status == VXGE_HW_OK)
5033 __vxge_hw_blockpool_blocks_remove(blockpool);
5034 }
5035
5036 return;
5037}
5038
5039/*
5040 * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
5041 * This function allocates a block from block pool or from the system
5042 */
5043struct __vxge_hw_blockpool_entry *
5044__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
5045{
5046 struct __vxge_hw_blockpool_entry *entry = NULL;
5047 struct __vxge_hw_blockpool *blockpool;
5048
5049 blockpool = &devh->block_pool;
5050
5051 if (size == blockpool->block_size) {
5052
5053 if (!list_empty(&blockpool->free_block_list))
5054 entry = (struct __vxge_hw_blockpool_entry *)
5055 list_first_entry(&blockpool->free_block_list,
5056 struct __vxge_hw_blockpool_entry,
5057 item);
5058
5059 if (entry != NULL) {
5060 list_del(&entry->item);
5061 blockpool->pool_size--;
5062 }
5063 }
5064
5065 if (entry != NULL)
5066 __vxge_hw_blockpool_blocks_add(blockpool);
5067
5068 return entry;
5069}
5070
5071/*
5072 * __vxge_hw_blockpool_block_free - Frees a block from block pool
5073 * @devh: Hal device
5074 * @entry: Entry of block to be freed
5075 *
5076 * This function frees a block from block pool
5077 */
5078void
5079__vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
5080 struct __vxge_hw_blockpool_entry *entry)
5081{
5082 struct __vxge_hw_blockpool *blockpool;
5083
5084 blockpool = &devh->block_pool;
5085
5086 if (entry->length == blockpool->block_size) {
5087 list_add(&entry->item, &blockpool->free_block_list);
5088 blockpool->pool_size++;
5089 }
5090
5091 __vxge_hw_blockpool_blocks_remove(blockpool);
5092
5093 return;
5094}
Clone of davem's net-next-2.6 tree