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vxge: sparse and other clean-ups
[net-next-2.6.git] / drivers / net / vxge / vxge-config.c
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40a3a915
RV		 1/******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
9 *
926bd900 10 * vxge-config.c: Driver for Exar Corp's X3100 Series 10GbE PCIe I/O
40a3a915 11 * Virtualized Server Adapter.
926bd900 12 * Copyright(c) 2002-2010 Exar Corp.
40a3a915
RV		 13 ******************************************************************************/
14#include <linux/vmalloc.h>
15#include <linux/etherdevice.h>
16#include <linux/pci.h>
17#include <linux/pci_hotplug.h>
5a0e3ad6 18#include <linux/slab.h>
40a3a915
RV		 19
20#include "vxge-traffic.h"
21#include "vxge-config.h"
8424e00d 22#include "vxge-main.h"
40a3a915 23
42821a5b 24static enum vxge_hw_status
25__vxge_hw_fifo_delete(
26 struct __vxge_hw_vpath_handle *vpath_handle);
27
28static struct __vxge_hw_blockpool_entry *
29__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *hldev,
30 u32 size);
31
32static void
33__vxge_hw_blockpool_block_free(struct __vxge_hw_device *hldev,
34 struct __vxge_hw_blockpool_entry *entry);
35
36static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
37 void *block_addr,
38 u32 length,
39 struct pci_dev *dma_h,
40 struct pci_dev *acc_handle);
41
42static enum vxge_hw_status
43__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
44 struct __vxge_hw_blockpool *blockpool,
45 u32 pool_size,
46 u32 pool_max);
47
48static void
49__vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool);
50
51static void *
52__vxge_hw_blockpool_malloc(struct __vxge_hw_device *hldev,
53 u32 size,
54 struct vxge_hw_mempool_dma *dma_object);
55
56static void
57__vxge_hw_blockpool_free(struct __vxge_hw_device *hldev,
58 void *memblock,
59 u32 size,
60 struct vxge_hw_mempool_dma *dma_object);
61
42821a5b 62static void
63__vxge_hw_channel_free(
64 struct __vxge_hw_channel *channel);
65
42821a5b 66static enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp);
67
42821a5b 68static enum vxge_hw_status
69__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config);
70
42821a5b 71static enum vxge_hw_status
72__vxge_hw_device_register_poll(
73 void __iomem *reg,
74 u64 mask, u32 max_millis);
75
76static inline enum vxge_hw_status
77__vxge_hw_pio_mem_write64(u64 val64, void __iomem *addr,
78 u64 mask, u32 max_millis)
79{
80 __vxge_hw_pio_mem_write32_lower((u32)vxge_bVALn(val64, 32, 32), addr);
81 wmb();
82
83 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32), addr);
84 wmb();
85
86 return __vxge_hw_device_register_poll(addr, mask, max_millis);
87}
88
89static struct vxge_hw_mempool*
90__vxge_hw_mempool_create(struct __vxge_hw_device *devh, u32 memblock_size,
2c91308f
JM		 91 u32 item_size, u32 private_size, u32 items_initial,
92 u32 items_max, struct vxge_hw_mempool_cbs *mp_callback,
93 void *userdata);
94
42821a5b 95static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool);
96
97static enum vxge_hw_status
98__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
99 struct vxge_hw_vpath_stats_hw_info *hw_stats);
100
101static enum vxge_hw_status
102vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vpath_handle);
103
104static enum vxge_hw_status
105__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg);
106
42821a5b 107static void
108__vxge_hw_vp_terminate(struct __vxge_hw_device *devh, u32 vp_id);
109
42821a5b 110static enum vxge_hw_status
111__vxge_hw_vpath_xmac_tx_stats_get(struct __vxge_hw_virtualpath *vpath,
112 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats);
113
114static enum vxge_hw_status
115__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
116 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats);
117
4d2a5b40
JM		 118static void
119vxge_hw_vpath_set_zero_rx_frm_len(struct vxge_hw_vpath_reg __iomem *vp_reg)
120{
121 u64 val64;
122
123 val64 = readq(&vp_reg->rxmac_vcfg0);
124 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
125 writeq(val64, &vp_reg->rxmac_vcfg0);
126 val64 = readq(&vp_reg->rxmac_vcfg0);
127
128 return;
129}
130
131/*
132 * vxge_hw_vpath_wait_receive_idle - Wait for Rx to become idle
133 */
134int vxge_hw_vpath_wait_receive_idle(struct __vxge_hw_device *hldev, u32 vp_id)
135{
136 struct vxge_hw_vpath_reg __iomem *vp_reg;
137 struct __vxge_hw_virtualpath *vpath;
138 u64 val64, rxd_count, rxd_spat;
139 int count = 0, total_count = 0;
140
141 vpath = &hldev->virtual_paths[vp_id];
142 vp_reg = vpath->vp_reg;
143
144 vxge_hw_vpath_set_zero_rx_frm_len(vp_reg);
145
146 /* Check that the ring controller for this vpath has enough free RxDs
147 * to send frames to the host. This is done by reading the
148 * PRC_RXD_DOORBELL_VPn register and comparing the read value to the
149 * RXD_SPAT value for the vpath.
150 */
151 val64 = readq(&vp_reg->prc_cfg6);
152 rxd_spat = VXGE_HW_PRC_CFG6_GET_RXD_SPAT(val64) + 1;
153 /* Use a factor of 2 when comparing rxd_count against rxd_spat for some
154 * leg room.
155 */
156 rxd_spat *= 2;
157
158 do {
159 mdelay(1);
160
161 rxd_count = readq(&vp_reg->prc_rxd_doorbell);
162
163 /* Check that the ring controller for this vpath does
164 * not have any frame in its pipeline.
165 */
166 val64 = readq(&vp_reg->frm_in_progress_cnt);
167 if ((rxd_count <= rxd_spat) || (val64 > 0))
168 count = 0;
169 else
170 count++;
171 total_count++;
172 } while ((count < VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT) &&
173 (total_count < VXGE_HW_MAX_POLLING_COUNT));
174
175 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
176 printk(KERN_ALERT "%s: Still Receiving traffic. Abort wait\n",
177 __func__);
178
179 return total_count;
180}
181
182/* vxge_hw_device_wait_receive_idle - This function waits until all frames
183 * stored in the frame buffer for each vpath assigned to the given
184 * function (hldev) have been sent to the host.
185 */
186void vxge_hw_device_wait_receive_idle(struct __vxge_hw_device *hldev)
187{
188 int i, total_count = 0;
189
190 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
191 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
192 continue;
193
194 total_count += vxge_hw_vpath_wait_receive_idle(hldev, i);
195 if (total_count >= VXGE_HW_MAX_POLLING_COUNT)
196 break;
197 }
198}
199
8424e00d
JM		 200static enum vxge_hw_status
201vxge_hw_vpath_fw_api(struct __vxge_hw_virtualpath *vpath, u32 action,
202 u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
203 u64 *steer_ctrl)
204{
205 struct vxge_hw_vpath_reg __iomem *vp_reg;
206 enum vxge_hw_status status;
207 u64 val64;
208 u32 retry = 0, max_retry = 100;
209
210 vp_reg = vpath->vp_reg;
211
212 if (vpath->vp_open) {
213 max_retry = 3;
214 spin_lock(&vpath->lock);
215 }
216
217 writeq(*data0, &vp_reg->rts_access_steer_data0);
218 writeq(*data1, &vp_reg->rts_access_steer_data1);
219 wmb();
220
221 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
222 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(fw_memo) |
223 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset) |
224 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
225 *steer_ctrl;
226
227 status = __vxge_hw_pio_mem_write64(val64,
228 &vp_reg->rts_access_steer_ctrl,
229 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
230 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
231
232 /* The __vxge_hw_device_register_poll can udelay for a significant
233 * amount of time, blocking other proccess from the CPU. If it delays
234 * for ~5secs, a NMI error can occur. A way around this is to give up
235 * the processor via msleep, but this is not allowed is under lock.
236 * So, only allow it to sleep for ~4secs if open. Otherwise, delay for
237 * 1sec and sleep for 10ms until the firmware operation has completed
238 * or timed-out.
239 */
240 while ((status != VXGE_HW_OK) && retry++ < max_retry) {
241 if (!vpath->vp_open)
242 msleep(20);
243 status = __vxge_hw_device_register_poll(
244 &vp_reg->rts_access_steer_ctrl,
245 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
246 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
247 }
248
249 if (status != VXGE_HW_OK)
250 goto out;
251
252 val64 = readq(&vp_reg->rts_access_steer_ctrl);
253 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
254 *data0 = readq(&vp_reg->rts_access_steer_data0);
255 *data1 = readq(&vp_reg->rts_access_steer_data1);
256 *steer_ctrl = val64;
257 } else
258 status = VXGE_HW_FAIL;
259
260out:
261 if (vpath->vp_open)
262 spin_unlock(&vpath->lock);
263 return status;
264}
265
e8ac1756
JM		 266enum vxge_hw_status
267vxge_hw_upgrade_read_version(struct __vxge_hw_device *hldev, u32 *major,
268 u32 *minor, u32 *build)
269{
270 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
271 struct __vxge_hw_virtualpath *vpath;
272 enum vxge_hw_status status;
273
274 vpath = &hldev->virtual_paths[hldev->first_vp_id];
275
276 status = vxge_hw_vpath_fw_api(vpath,
277 VXGE_HW_FW_UPGRADE_ACTION,
278 VXGE_HW_FW_UPGRADE_MEMO,
279 VXGE_HW_FW_UPGRADE_OFFSET_READ,
280 &data0, &data1, &steer_ctrl);
281 if (status != VXGE_HW_OK)
282 return status;
283
284 *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
285 *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
286 *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
287
288 return status;
289}
290
291enum vxge_hw_status vxge_hw_flash_fw(struct __vxge_hw_device *hldev)
292{
293 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
294 struct __vxge_hw_virtualpath *vpath;
295 enum vxge_hw_status status;
296 u32 ret;
297
298 vpath = &hldev->virtual_paths[hldev->first_vp_id];
299
300 status = vxge_hw_vpath_fw_api(vpath,
301 VXGE_HW_FW_UPGRADE_ACTION,
302 VXGE_HW_FW_UPGRADE_MEMO,
303 VXGE_HW_FW_UPGRADE_OFFSET_COMMIT,
304 &data0, &data1, &steer_ctrl);
305 if (status != VXGE_HW_OK) {
306 vxge_debug_init(VXGE_ERR, "%s: FW upgrade failed", __func__);
307 goto exit;
308 }
309
310 ret = VXGE_HW_RTS_ACCESS_STEER_CTRL_GET_ACTION(steer_ctrl) & 0x7F;
311 if (ret != 1) {
312 vxge_debug_init(VXGE_ERR, "%s: FW commit failed with error %d",
313 __func__, ret);
314 status = VXGE_HW_FAIL;
315 }
316
317exit:
318 return status;
319}
320
321enum vxge_hw_status
322vxge_update_fw_image(struct __vxge_hw_device *hldev, const u8 *fwdata, int size)
323{
324 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
325 struct __vxge_hw_virtualpath *vpath;
326 enum vxge_hw_status status;
327 int ret_code, sec_code;
328
329 vpath = &hldev->virtual_paths[hldev->first_vp_id];
330
331 /* send upgrade start command */
332 status = vxge_hw_vpath_fw_api(vpath,
333 VXGE_HW_FW_UPGRADE_ACTION,
334 VXGE_HW_FW_UPGRADE_MEMO,
335 VXGE_HW_FW_UPGRADE_OFFSET_START,
336 &data0, &data1, &steer_ctrl);
337 if (status != VXGE_HW_OK) {
338 vxge_debug_init(VXGE_ERR, " %s: Upgrade start cmd failed",
339 __func__);
340 return status;
341 }
342
343 /* Transfer fw image to adapter 16 bytes at a time */
344 for (; size > 0; size -= VXGE_HW_FW_UPGRADE_BLK_SIZE) {
345 steer_ctrl = 0;
346
347 /* The next 128bits of fwdata to be loaded onto the adapter */
348 data0 = *((u64 *)fwdata);
349 data1 = *((u64 *)fwdata + 1);
350
351 status = vxge_hw_vpath_fw_api(vpath,
352 VXGE_HW_FW_UPGRADE_ACTION,
353 VXGE_HW_FW_UPGRADE_MEMO,
354 VXGE_HW_FW_UPGRADE_OFFSET_SEND,
355 &data0, &data1, &steer_ctrl);
356 if (status != VXGE_HW_OK) {
357 vxge_debug_init(VXGE_ERR, "%s: Upgrade send failed",
358 __func__);
359 goto out;
360 }
361
362 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
363 switch (ret_code) {
364 case VXGE_HW_FW_UPGRADE_OK:
365 /* All OK, send next 16 bytes. */
366 break;
367 case VXGE_FW_UPGRADE_BYTES2SKIP:
368 /* skip bytes in the stream */
369 fwdata += (data0 >> 8) & 0xFFFFFFFF;
370 break;
371 case VXGE_HW_FW_UPGRADE_DONE:
372 goto out;
373 case VXGE_HW_FW_UPGRADE_ERR:
374 sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
375 switch (sec_code) {
376 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_1:
377 case VXGE_HW_FW_UPGRADE_ERR_CORRUPT_DATA_7:
378 printk(KERN_ERR
379 "corrupted data from .ncf file\n");
380 break;
381 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_3:
382 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_4:
383 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_5:
384 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_6:
385 case VXGE_HW_FW_UPGRADE_ERR_INV_NCF_FILE_8:
386 printk(KERN_ERR "invalid .ncf file\n");
387 break;
388 case VXGE_HW_FW_UPGRADE_ERR_BUFFER_OVERFLOW:
389 printk(KERN_ERR "buffer overflow\n");
390 break;
391 case VXGE_HW_FW_UPGRADE_ERR_FAILED_TO_FLASH:
392 printk(KERN_ERR "failed to flash the image\n");
393 break;
394 case VXGE_HW_FW_UPGRADE_ERR_GENERIC_ERROR_UNKNOWN:
395 printk(KERN_ERR
396 "generic error. Unknown error type\n");
397 break;
398 default:
399 printk(KERN_ERR "Unknown error of type %d\n",
400 sec_code);
401 break;
402 }
403 status = VXGE_HW_FAIL;
404 goto out;
405 default:
406 printk(KERN_ERR "Unknown FW error: %d\n", ret_code);
407 status = VXGE_HW_FAIL;
408 goto out;
409 }
410 /* point to next 16 bytes */
411 fwdata += VXGE_HW_FW_UPGRADE_BLK_SIZE;
412 }
413out:
414 return status;
415}
416
417enum vxge_hw_status
418vxge_hw_vpath_eprom_img_ver_get(struct __vxge_hw_device *hldev,
419 struct eprom_image *img)
420{
421 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
422 struct __vxge_hw_virtualpath *vpath;
423 enum vxge_hw_status status;
424 int i;
425
426 vpath = &hldev->virtual_paths[hldev->first_vp_id];
427
428 for (i = 0; i < VXGE_HW_MAX_ROM_IMAGES; i++) {
429 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
430 data1 = steer_ctrl = 0;
431
432 status = vxge_hw_vpath_fw_api(vpath,
433 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
434 VXGE_HW_FW_API_GET_EPROM_REV,
435 0, &data0, &data1, &steer_ctrl);
436 if (status != VXGE_HW_OK)
437 break;
438
439 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
440 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
441 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
442 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
443 }
444
445 return status;
446}
447
40a3a915
RV		 448/*
449 * __vxge_hw_channel_allocate - Allocate memory for channel
450 * This function allocates required memory for the channel and various arrays
451 * in the channel
452 */
2c91308f 453static struct __vxge_hw_channel *
40a3a915
RV		 454__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
455 enum __vxge_hw_channel_type type,
456 u32 length, u32 per_dtr_space, void *userdata)
457{
458 struct __vxge_hw_channel *channel;
459 struct __vxge_hw_device *hldev;
460 int size = 0;
461 u32 vp_id;
462
463 hldev = vph->vpath->hldev;
464 vp_id = vph->vpath->vp_id;
465
466 switch (type) {
467 case VXGE_HW_CHANNEL_TYPE_FIFO:
468 size = sizeof(struct __vxge_hw_fifo);
469 break;
470 case VXGE_HW_CHANNEL_TYPE_RING:
471 size = sizeof(struct __vxge_hw_ring);
472 break;
473 default:
474 break;
475 }
476
477 channel = kzalloc(size, GFP_KERNEL);
478 if (channel == NULL)
479 goto exit0;
480 INIT_LIST_HEAD(&channel->item);
481
482 channel->common_reg = hldev->common_reg;
483 channel->first_vp_id = hldev->first_vp_id;
484 channel->type = type;
485 channel->devh = hldev;
486 channel->vph = vph;
487 channel->userdata = userdata;
488 channel->per_dtr_space = per_dtr_space;
489 channel->length = length;
490 channel->vp_id = vp_id;
491
492 channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
493 if (channel->work_arr == NULL)
494 goto exit1;
495
496 channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
497 if (channel->free_arr == NULL)
498 goto exit1;
499 channel->free_ptr = length;
500
501 channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
502 if (channel->reserve_arr == NULL)
503 goto exit1;
504 channel->reserve_ptr = length;
505 channel->reserve_top = 0;
506
507 channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
508 if (channel->orig_arr == NULL)
509 goto exit1;
510
511 return channel;
512exit1:
513 __vxge_hw_channel_free(channel);
514
515exit0:
516 return NULL;
517}
518
519/*
520 * __vxge_hw_channel_free - Free memory allocated for channel
521 * This function deallocates memory from the channel and various arrays
522 * in the channel
523 */
2c91308f 524static void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
40a3a915
RV		 525{
526 kfree(channel->work_arr);
527 kfree(channel->free_arr);
528 kfree(channel->reserve_arr);
529 kfree(channel->orig_arr);
530 kfree(channel);
531}
532
533/*
534 * __vxge_hw_channel_initialize - Initialize a channel
535 * This function initializes a channel by properly setting the
536 * various references
537 */
2c91308f 538static enum vxge_hw_status
40a3a915
RV		 539__vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
540{
541 u32 i;
542 struct __vxge_hw_virtualpath *vpath;
543
544 vpath = channel->vph->vpath;
545
546 if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
547 for (i = 0; i < channel->length; i++)
548 channel->orig_arr[i] = channel->reserve_arr[i];
549 }
550
551 switch (channel->type) {
552 case VXGE_HW_CHANNEL_TYPE_FIFO:
553 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
554 channel->stats = &((struct __vxge_hw_fifo *)
555 channel)->stats->common_stats;
556 break;
557 case VXGE_HW_CHANNEL_TYPE_RING:
558 vpath->ringh = (struct __vxge_hw_ring *)channel;
559 channel->stats = &((struct __vxge_hw_ring *)
560 channel)->stats->common_stats;
561 break;
562 default:
563 break;
564 }
565
566 return VXGE_HW_OK;
567}
568
569/*
570 * __vxge_hw_channel_reset - Resets a channel
571 * This function resets a channel by properly setting the various references
572 */
2c91308f 573static enum vxge_hw_status
40a3a915
RV		 574__vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
575{
576 u32 i;
577
578 for (i = 0; i < channel->length; i++) {
579 if (channel->reserve_arr != NULL)
580 channel->reserve_arr[i] = channel->orig_arr[i];
581 if (channel->free_arr != NULL)
582 channel->free_arr[i] = NULL;
583 if (channel->work_arr != NULL)
584 channel->work_arr[i] = NULL;
585 }
586 channel->free_ptr = channel->length;
587 channel->reserve_ptr = channel->length;
588 channel->reserve_top = 0;
589 channel->post_index = 0;
590 channel->compl_index = 0;
591
592 return VXGE_HW_OK;
593}
594
595/*
596 * __vxge_hw_device_pci_e_init
597 * Initialize certain PCI/PCI-X configuration registers
598 * with recommended values. Save config space for future hw resets.
599 */
2c91308f 600static void __vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
40a3a915
RV		 601{
602 u16 cmd = 0;
603
604 /* Set the PErr Repconse bit and SERR in PCI command register. */
605 pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
606 cmd |= 0x140;
607 pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
608
609 pci_save_state(hldev->pdev);
40a3a915
RV		 610}
611
612/*
613 * __vxge_hw_device_register_poll
614 * Will poll certain register for specified amount of time.
615 * Will poll until masked bit is not cleared.
616 */
42821a5b 617static enum vxge_hw_status
40a3a915
RV		 618__vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
619{
620 u64 val64;
621 u32 i = 0;
622 enum vxge_hw_status ret = VXGE_HW_FAIL;
623
624 udelay(10);
625
626 do {
627 val64 = readq(reg);
628 if (!(val64 & mask))
629 return VXGE_HW_OK;
630 udelay(100);
631 } while (++i <= 9);
632
633 i = 0;
634 do {
635 val64 = readq(reg);
636 if (!(val64 & mask))
637 return VXGE_HW_OK;
638 mdelay(1);
639 } while (++i <= max_millis);
640
641 return ret;
642}
643
4d2a5b40 644/* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
40a3a915
RV		 645 * in progress
646 * This routine checks the vpath reset in progress register is turned zero
647 */
42821a5b 648static enum vxge_hw_status
40a3a915
RV		 649__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
650{
651 enum vxge_hw_status status;
652 status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
653 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
654 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
655 return status;
656}
657
658/*
659 * __vxge_hw_device_toc_get
660 * This routine sets the swapper and reads the toc pointer and returns the
661 * memory mapped address of the toc
662 */
42821a5b 663static struct vxge_hw_toc_reg __iomem *
40a3a915
RV		 664__vxge_hw_device_toc_get(void __iomem *bar0)
665{
666 u64 val64;
667 struct vxge_hw_toc_reg __iomem *toc = NULL;
668 enum vxge_hw_status status;
669
670 struct vxge_hw_legacy_reg __iomem *legacy_reg =
671 (struct vxge_hw_legacy_reg __iomem *)bar0;
672
673 status = __vxge_hw_legacy_swapper_set(legacy_reg);
674 if (status != VXGE_HW_OK)
675 goto exit;
676
677 val64 = readq(&legacy_reg->toc_first_pointer);
678 toc = (struct vxge_hw_toc_reg __iomem *)(bar0+val64);
679exit:
680 return toc;
681}
682
683/*
684 * __vxge_hw_device_reg_addr_get
685 * This routine sets the swapper and reads the toc pointer and initializes the
686 * register location pointers in the device object. It waits until the ric is
687 * completed initializing registers.
688 */
2c91308f 689static enum vxge_hw_status
40a3a915
RV		 690__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
691{
692 u64 val64;
693 u32 i;
694 enum vxge_hw_status status = VXGE_HW_OK;
695
696 hldev->legacy_reg = (struct vxge_hw_legacy_reg __iomem *)hldev->bar0;
697
698 hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
699 if (hldev->toc_reg == NULL) {
700 status = VXGE_HW_FAIL;
701 goto exit;
702 }
703
704 val64 = readq(&hldev->toc_reg->toc_common_pointer);
705 hldev->common_reg =
706 (struct vxge_hw_common_reg __iomem *)(hldev->bar0 + val64);
707
708 val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
709 hldev->mrpcim_reg =
710 (struct vxge_hw_mrpcim_reg __iomem *)(hldev->bar0 + val64);
711
712 for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
713 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
714 hldev->srpcim_reg[i] =
715 (struct vxge_hw_srpcim_reg __iomem *)
716 (hldev->bar0 + val64);
717 }
718
719 for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
720 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
721 hldev->vpmgmt_reg[i] =
722 (struct vxge_hw_vpmgmt_reg __iomem *)(hldev->bar0 + val64);
723 }
724
725 for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
726 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
727 hldev->vpath_reg[i] =
728 (struct vxge_hw_vpath_reg __iomem *)
729 (hldev->bar0 + val64);
730 }
731
732 val64 = readq(&hldev->toc_reg->toc_kdfc);
733
734 switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
735 case 0:
736 hldev->kdfc = (u8 __iomem *)(hldev->bar0 +
737 VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64));
738 break;
40a3a915
RV		 739 default:
740 break;
741 }
742
743 status = __vxge_hw_device_vpath_reset_in_prog_check(
744 (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
745exit:
746 return status;
747}
748
40a3a915
RV		 749/*
750 * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
751 * This routine returns the Access Rights of the driver
752 */
753static u32
754__vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
755{
756 u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
757
758 switch (host_type) {
759 case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
1dc47a9b
SH		 760 if (func_id == 0) {
761 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
762 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
763 }
40a3a915
RV		 764 break;
765 case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
766 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
767 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
768 break;
769 case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
770 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
771 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
772 break;
773 case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
774 case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
775 case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
776 break;
777 case VXGE_HW_SR_VH_FUNCTION0:
778 case VXGE_HW_VH_NORMAL_FUNCTION:
779 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
780 break;
781 }
782
783 return access_rights;
784}
92cdd7c3
SH		 785/*
786 * __vxge_hw_device_is_privilaged
787 * This routine checks if the device function is privilaged or not
788 */
789
790enum vxge_hw_status
791__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
792{
793 if (__vxge_hw_device_access_rights_get(host_type,
794 func_id) &
795 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
796 return VXGE_HW_OK;
797 else
798 return VXGE_HW_ERR_PRIVILAGED_OPEARATION;
799}
800
8424e00d
JM		 801/*
802 * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
803 * Returns the function number of the vpath.
804 */
805static u32
806__vxge_hw_vpath_func_id_get(struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
807{
808 u64 val64;
809
810 val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
811
812 return
813 (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
814}
815
40a3a915
RV		 816/*
817 * __vxge_hw_device_host_info_get
818 * This routine returns the host type assignments
819 */
8424e00d 820static void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
40a3a915
RV		 821{
822 u64 val64;
823 u32 i;
824
825 val64 = readq(&hldev->common_reg->host_type_assignments);
826
827 hldev->host_type =
828 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
829
830 hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
831
832 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 833 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
834 continue;
835
836 hldev->func_id =
8424e00d 837 __vxge_hw_vpath_func_id_get(hldev->vpmgmt_reg[i]);
40a3a915
RV		 838
839 hldev->access_rights = __vxge_hw_device_access_rights_get(
840 hldev->host_type, hldev->func_id);
841
8424e00d
JM		 842 hldev->virtual_paths[i].vp_open = VXGE_HW_VP_NOT_OPEN;
843 hldev->virtual_paths[i].vp_reg = hldev->vpath_reg[i];
844
40a3a915
RV		 845 hldev->first_vp_id = i;
846 break;
847 }
40a3a915
RV		 848}
849
850/*
851 * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
852 * link width and signalling rate.
853 */
854static enum vxge_hw_status
855__vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
856{
857 int exp_cap;
858 u16 lnk;
859
860 /* Get the negotiated link width and speed from PCI config space */
861 exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
862 pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
863
864 if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
865 return VXGE_HW_ERR_INVALID_PCI_INFO;
866
867 switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
868 case PCIE_LNK_WIDTH_RESRV:
869 case PCIE_LNK_X1:
870 case PCIE_LNK_X2:
871 case PCIE_LNK_X4:
872 case PCIE_LNK_X8:
873 break;
874 default:
875 return VXGE_HW_ERR_INVALID_PCI_INFO;
876 }
877
878 return VXGE_HW_OK;
879}
880
40a3a915
RV		 881/*
882 * __vxge_hw_device_initialize
883 * Initialize Titan-V hardware.
884 */
2c91308f
JM		 885static enum vxge_hw_status
886__vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
40a3a915
RV		 887{
888 enum vxge_hw_status status = VXGE_HW_OK;
889
92cdd7c3
SH		 890 if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
891 hldev->func_id)) {
5dbc9011
SS		 892 /* Validate the pci-e link width and speed */
893 status = __vxge_hw_verify_pci_e_info(hldev);
894 if (status != VXGE_HW_OK)
895 goto exit;
896 }
40a3a915 897
40a3a915
RV		 898exit:
899 return status;
900}
901
8424e00d
JM		 902/*
903 * __vxge_hw_vpath_fw_ver_get - Get the fw version
904 * Returns FW Version
905 */
906static enum vxge_hw_status
907__vxge_hw_vpath_fw_ver_get(struct __vxge_hw_virtualpath *vpath,
908 struct vxge_hw_device_hw_info *hw_info)
909{
910 struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
911 struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
912 struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
913 struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
914 u64 data0, data1 = 0, steer_ctrl = 0;
915 enum vxge_hw_status status;
916
917 status = vxge_hw_vpath_fw_api(vpath,
918 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
919 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
920 0, &data0, &data1, &steer_ctrl);
921 if (status != VXGE_HW_OK)
922 goto exit;
923
924 fw_date->day =
925 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
926 fw_date->month =
927 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
928 fw_date->year =
929 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
930
931 snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
932 fw_date->month, fw_date->day, fw_date->year);
933
934 fw_version->major =
935 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
936 fw_version->minor =
937 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
938 fw_version->build =
939 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
940
941 snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
942 fw_version->major, fw_version->minor, fw_version->build);
943
944 flash_date->day =
945 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data1);
946 flash_date->month =
947 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data1);
948 flash_date->year =
949 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data1);
950
951 snprintf(flash_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
952 flash_date->month, flash_date->day, flash_date->year);
953
954 flash_version->major =
955 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data1);
956 flash_version->minor =
957 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data1);
958 flash_version->build =
959 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data1);
960
961 snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
962 flash_version->major, flash_version->minor,
963 flash_version->build);
964
965exit:
966 return status;
967}
968
969/*
970 * __vxge_hw_vpath_card_info_get - Get the serial numbers,
971 * part number and product description.
972 */
973static enum vxge_hw_status
974__vxge_hw_vpath_card_info_get(struct __vxge_hw_virtualpath *vpath,
975 struct vxge_hw_device_hw_info *hw_info)
976{
977 enum vxge_hw_status status;
978 u64 data0, data1 = 0, steer_ctrl = 0;
979 u8 *serial_number = hw_info->serial_number;
980 u8 *part_number = hw_info->part_number;
981 u8 *product_desc = hw_info->product_desc;
982 u32 i, j = 0;
983
984 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
985
986 status = vxge_hw_vpath_fw_api(vpath,
987 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
988 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
989 0, &data0, &data1, &steer_ctrl);
990 if (status != VXGE_HW_OK)
991 return status;
992
993 ((u64 *)serial_number)[0] = be64_to_cpu(data0);
994 ((u64 *)serial_number)[1] = be64_to_cpu(data1);
995
996 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
997 data1 = steer_ctrl = 0;
998
999 status = vxge_hw_vpath_fw_api(vpath,
1000 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
1001 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
1002 0, &data0, &data1, &steer_ctrl);
1003 if (status != VXGE_HW_OK)
1004 return status;
1005
1006 ((u64 *)part_number)[0] = be64_to_cpu(data0);
1007 ((u64 *)part_number)[1] = be64_to_cpu(data1);
1008
1009 for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
1010 i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
1011 data0 = i;
1012 data1 = steer_ctrl = 0;
1013
1014 status = vxge_hw_vpath_fw_api(vpath,
1015 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY,
1016 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
1017 0, &data0, &data1, &steer_ctrl);
1018 if (status != VXGE_HW_OK)
1019 return status;
1020
1021 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
1022 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
1023 }
1024
1025 return status;
1026}
1027
1028/*
1029 * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
1030 * Returns pci function mode
1031 */
c3150eac
JM		 1032static enum vxge_hw_status
1033__vxge_hw_vpath_pci_func_mode_get(struct __vxge_hw_virtualpath *vpath,
1034 struct vxge_hw_device_hw_info *hw_info)
8424e00d
JM		 1035{
1036 u64 data0, data1 = 0, steer_ctrl = 0;
1037 enum vxge_hw_status status;
1038
ca3e3b8f 1039 data0 = 0;
8424e00d
JM		 1040
1041 status = vxge_hw_vpath_fw_api(vpath,
ca3e3b8f 1042 VXGE_HW_FW_API_GET_FUNC_MODE,
8424e00d
JM		 1043 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
1044 0, &data0, &data1, &steer_ctrl);
c3150eac
JM		 1045 if (status != VXGE_HW_OK)
1046 return status;
8424e00d 1047
ca3e3b8f 1048 hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
c3150eac 1049 return status;
8424e00d
JM		 1050}
1051
1052/*
1053 * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
1054 * from MAC address table.
1055 */
1056static enum vxge_hw_status
1057__vxge_hw_vpath_addr_get(struct __vxge_hw_virtualpath *vpath,
1058 u8 *macaddr, u8 *macaddr_mask)
1059{
1060 u64 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY,
1061 data0 = 0, data1 = 0, steer_ctrl = 0;
1062 enum vxge_hw_status status;
1063 int i;
1064
1065 do {
1066 status = vxge_hw_vpath_fw_api(vpath, action,
1067 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA,
1068 0, &data0, &data1, &steer_ctrl);
1069 if (status != VXGE_HW_OK)
1070 goto exit;
1071
1072 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
1073 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
1074 data1);
1075
1076 for (i = ETH_ALEN; i > 0; i--) {
1077 macaddr[i - 1] = (u8) (data0 & 0xFF);
1078 data0 >>= 8;
1079
1080 macaddr_mask[i - 1] = (u8) (data1 & 0xFF);
1081 data1 >>= 8;
1082 }
1083
1084 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_NEXT_ENTRY;
1085 data0 = 0, data1 = 0, steer_ctrl = 0;
1086
1087 } while (!is_valid_ether_addr(macaddr));
1088exit:
1089 return status;
1090}
1091
40a3a915
RV		 1092/**
1093 * vxge_hw_device_hw_info_get - Get the hw information
1094 * Returns the vpath mask that has the bits set for each vpath allocated
1095 * for the driver, FW version information and the first mac addresse for
1096 * each vpath
1097 */
1098enum vxge_hw_status __devinit
1099vxge_hw_device_hw_info_get(void __iomem *bar0,
1100 struct vxge_hw_device_hw_info *hw_info)
1101{
1102 u32 i;
1103 u64 val64;
1104 struct vxge_hw_toc_reg __iomem *toc;
1105 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
1106 struct vxge_hw_common_reg __iomem *common_reg;
40a3a915
RV		 1107 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
1108 enum vxge_hw_status status;
8424e00d 1109 struct __vxge_hw_virtualpath vpath;
40a3a915
RV		 1110
1111 memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
1112
1113 toc = __vxge_hw_device_toc_get(bar0);
1114 if (toc == NULL) {
1115 status = VXGE_HW_ERR_CRITICAL;
1116 goto exit;
1117 }
1118
1119 val64 = readq(&toc->toc_common_pointer);
1120 common_reg = (struct vxge_hw_common_reg __iomem *)(bar0 + val64);
1121
1122 status = __vxge_hw_device_vpath_reset_in_prog_check(
1123 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
1124 if (status != VXGE_HW_OK)
1125 goto exit;
1126
1127 hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
1128
1129 val64 = readq(&common_reg->host_type_assignments);
1130
1131 hw_info->host_type =
1132 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
1133
1134 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1135
1136 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1137 continue;
1138
1139 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
1140
1141 vpmgmt_reg = (struct vxge_hw_vpmgmt_reg __iomem *)
1142 (bar0 + val64);
1143
8424e00d 1144 hw_info->func_id = __vxge_hw_vpath_func_id_get(vpmgmt_reg);
40a3a915
RV		 1145 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
1146 hw_info->func_id) &
1147 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
1148
1149 val64 = readq(&toc->toc_mrpcim_pointer);
1150
1151 mrpcim_reg = (struct vxge_hw_mrpcim_reg __iomem *)
1152 (bar0 + val64);
1153
1154 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
1155 wmb();
1156 }
1157
1158 val64 = readq(&toc->toc_vpath_pointer[i]);
1159
8424e00d
JM		 1160 vpath.vp_reg = (struct vxge_hw_vpath_reg __iomem *)
1161 (bar0 + val64);
1162 vpath.vp_open = 0;
40a3a915 1163
c3150eac
JM		 1164 status = __vxge_hw_vpath_pci_func_mode_get(&vpath, hw_info);
1165 if (status != VXGE_HW_OK)
1166 goto exit;
40a3a915 1167
8424e00d 1168 status = __vxge_hw_vpath_fw_ver_get(&vpath, hw_info);
40a3a915
RV		 1169 if (status != VXGE_HW_OK)
1170 goto exit;
1171
8424e00d 1172 status = __vxge_hw_vpath_card_info_get(&vpath, hw_info);
40a3a915
RV		 1173 if (status != VXGE_HW_OK)
1174 goto exit;
1175
1176 break;
1177 }
1178
1179 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 1180 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
1181 continue;
1182
1183 val64 = readq(&toc->toc_vpath_pointer[i]);
8424e00d
JM		 1184 vpath.vp_reg = (struct vxge_hw_vpath_reg __iomem *)
1185 (bar0 + val64);
1186 vpath.vp_open = 0;
40a3a915 1187
8424e00d 1188 status = __vxge_hw_vpath_addr_get(&vpath,
40a3a915
RV		 1189 hw_info->mac_addrs[i],
1190 hw_info->mac_addr_masks[i]);
1191 if (status != VXGE_HW_OK)
1192 goto exit;
1193 }
1194exit:
1195 return status;
1196}
1197
1198/*
1199 * vxge_hw_device_initialize - Initialize Titan device.
1200 * Initialize Titan device. Note that all the arguments of this public API
1201 * are 'IN', including @hldev. Driver cooperates with
1202 * OS to find new Titan device, locate its PCI and memory spaces.
1203 *
1204 * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
1205 * to enable the latter to perform Titan hardware initialization.
1206 */
1207enum vxge_hw_status __devinit
1208vxge_hw_device_initialize(
1209 struct __vxge_hw_device **devh,
1210 struct vxge_hw_device_attr *attr,
1211 struct vxge_hw_device_config *device_config)
1212{
1213 u32 i;
1214 u32 nblocks = 0;
1215 struct __vxge_hw_device *hldev = NULL;
1216 enum vxge_hw_status status = VXGE_HW_OK;
1217
1218 status = __vxge_hw_device_config_check(device_config);
1219 if (status != VXGE_HW_OK)
1220 goto exit;
1221
1222 hldev = (struct __vxge_hw_device *)
1223 vmalloc(sizeof(struct __vxge_hw_device));
1224 if (hldev == NULL) {
1225 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1226 goto exit;
1227 }
1228
1229 memset(hldev, 0, sizeof(struct __vxge_hw_device));
1230 hldev->magic = VXGE_HW_DEVICE_MAGIC;
1231
1232 vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
1233
1234 /* apply config */
1235 memcpy(&hldev->config, device_config,
1236 sizeof(struct vxge_hw_device_config));
1237
1238 hldev->bar0 = attr->bar0;
40a3a915
RV		 1239 hldev->pdev = attr->pdev;
1240
1241 hldev->uld_callbacks.link_up = attr->uld_callbacks.link_up;
1242 hldev->uld_callbacks.link_down = attr->uld_callbacks.link_down;
1243 hldev->uld_callbacks.crit_err = attr->uld_callbacks.crit_err;
1244
1245 __vxge_hw_device_pci_e_init(hldev);
1246
1247 status = __vxge_hw_device_reg_addr_get(hldev);
aaffbd9f
SH		 1248 if (status != VXGE_HW_OK) {
1249 vfree(hldev);
40a3a915 1250 goto exit;
aaffbd9f 1251 }
40a3a915
RV		 1252
1253 __vxge_hw_device_host_info_get(hldev);
1254
1255 /* Incrementing for stats blocks */
1256 nblocks++;
1257
1258 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 1259 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
1260 continue;
1261
1262 if (device_config->vp_config[i].ring.enable ==
1263 VXGE_HW_RING_ENABLE)
1264 nblocks += device_config->vp_config[i].ring.ring_blocks;
1265
1266 if (device_config->vp_config[i].fifo.enable ==
1267 VXGE_HW_FIFO_ENABLE)
1268 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
1269 nblocks++;
1270 }
1271
1272 if (__vxge_hw_blockpool_create(hldev,
1273 &hldev->block_pool,
1274 device_config->dma_blockpool_initial + nblocks,
1275 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
1276
1277 vxge_hw_device_terminate(hldev);
1278 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1279 goto exit;
1280 }
1281
1282 status = __vxge_hw_device_initialize(hldev);
40a3a915
RV		 1283 if (status != VXGE_HW_OK) {
1284 vxge_hw_device_terminate(hldev);
1285 goto exit;
1286 }
1287
1288 *devh = hldev;
1289exit:
1290 return status;
1291}
1292
1293/*
1294 * vxge_hw_device_terminate - Terminate Titan device.
1295 * Terminate HW device.
1296 */
1297void
1298vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
1299{
1300 vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
1301
1302 hldev->magic = VXGE_HW_DEVICE_DEAD;
1303 __vxge_hw_blockpool_destroy(&hldev->block_pool);
1304 vfree(hldev);
1305}
1306
1307/*
1308 * vxge_hw_device_stats_get - Get the device hw statistics.
1309 * Returns the vpath h/w stats for the device.
1310 */
1311enum vxge_hw_status
1312vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
1313 struct vxge_hw_device_stats_hw_info *hw_stats)
1314{
1315 u32 i;
1316 enum vxge_hw_status status = VXGE_HW_OK;
1317
1318 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
40a3a915
RV		 1319 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
1320 (hldev->virtual_paths[i].vp_open ==
1321 VXGE_HW_VP_NOT_OPEN))
1322 continue;
1323
1324 memcpy(hldev->virtual_paths[i].hw_stats_sav,
1325 hldev->virtual_paths[i].hw_stats,
1326 sizeof(struct vxge_hw_vpath_stats_hw_info));
1327
1328 status = __vxge_hw_vpath_stats_get(
1329 &hldev->virtual_paths[i],
1330 hldev->virtual_paths[i].hw_stats);
1331 }
1332
1333 memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
1334 sizeof(struct vxge_hw_device_stats_hw_info));
1335
1336 return status;
1337}
1338
1339/*
1340 * vxge_hw_driver_stats_get - Get the device sw statistics.
1341 * Returns the vpath s/w stats for the device.
1342 */
1343enum vxge_hw_status vxge_hw_driver_stats_get(
1344 struct __vxge_hw_device *hldev,
1345 struct vxge_hw_device_stats_sw_info *sw_stats)
1346{
1347 enum vxge_hw_status status = VXGE_HW_OK;
1348
1349 memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
1350 sizeof(struct vxge_hw_device_stats_sw_info));
1351
1352 return status;
1353}
1354
1355/*
1356 * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
1357 * and offset and perform an operation
1358 * Get the statistics from the given location and offset.
1359 */
1360enum vxge_hw_status
1361vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
1362 u32 operation, u32 location, u32 offset, u64 *stat)
1363{
1364 u64 val64;
1365 enum vxge_hw_status status = VXGE_HW_OK;
1366
92cdd7c3
SH		 1367 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1368 hldev->func_id);
40a3a915
RV		 1369 if (status != VXGE_HW_OK)
1370 goto exit;
1371
1372 val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
1373 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
1374 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
1375 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
1376
1377 status = __vxge_hw_pio_mem_write64(val64,
1378 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
1379 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
1380 hldev->config.device_poll_millis);
1381
1382 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
1383 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
1384 else
1385 *stat = 0;
1386exit:
1387 return status;
1388}
1389
1390/*
1391 * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
1392 * Get the Statistics on aggregate port
1393 */
42821a5b 1394static enum vxge_hw_status
40a3a915
RV		 1395vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
1396 struct vxge_hw_xmac_aggr_stats *aggr_stats)
1397{
1398 u64 *val64;
1399 int i;
1400 u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
1401 enum vxge_hw_status status = VXGE_HW_OK;
1402
1403 val64 = (u64 *)aggr_stats;
1404
92cdd7c3
SH		 1405 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1406 hldev->func_id);
40a3a915
RV		 1407 if (status != VXGE_HW_OK)
1408 goto exit;
1409
1410 for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
1411 status = vxge_hw_mrpcim_stats_access(hldev,
1412 VXGE_HW_STATS_OP_READ,
1413 VXGE_HW_STATS_LOC_AGGR,
1414 ((offset + (104 * port)) >> 3), val64);
1415 if (status != VXGE_HW_OK)
1416 goto exit;
1417
1418 offset += 8;
1419 val64++;
1420 }
1421exit:
1422 return status;
1423}
1424
1425/*
1426 * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
1427 * Get the Statistics on port
1428 */
42821a5b 1429static enum vxge_hw_status
40a3a915
RV		 1430vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
1431 struct vxge_hw_xmac_port_stats *port_stats)
1432{
1433 u64 *val64;
1434 enum vxge_hw_status status = VXGE_HW_OK;
1435 int i;
1436 u32 offset = 0x0;
1437 val64 = (u64 *) port_stats;
1438
92cdd7c3
SH		 1439 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1440 hldev->func_id);
40a3a915
RV		 1441 if (status != VXGE_HW_OK)
1442 goto exit;
1443
1444 for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
1445 status = vxge_hw_mrpcim_stats_access(hldev,
1446 VXGE_HW_STATS_OP_READ,
1447 VXGE_HW_STATS_LOC_AGGR,
1448 ((offset + (608 * port)) >> 3), val64);
1449 if (status != VXGE_HW_OK)
1450 goto exit;
1451
1452 offset += 8;
1453 val64++;
1454 }
1455
1456exit:
1457 return status;
1458}
1459
1460/*
1461 * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
1462 * Get the XMAC Statistics
1463 */
1464enum vxge_hw_status
1465vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
1466 struct vxge_hw_xmac_stats *xmac_stats)
1467{
1468 enum vxge_hw_status status = VXGE_HW_OK;
1469 u32 i;
1470
1471 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1472 0, &xmac_stats->aggr_stats[0]);
1473
1474 if (status != VXGE_HW_OK)
1475 goto exit;
1476
1477 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
1478 1, &xmac_stats->aggr_stats[1]);
1479 if (status != VXGE_HW_OK)
1480 goto exit;
1481
1482 for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
1483
1484 status = vxge_hw_device_xmac_port_stats_get(hldev,
1485 i, &xmac_stats->port_stats[i]);
1486 if (status != VXGE_HW_OK)
1487 goto exit;
1488 }
1489
1490 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1491
1492 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
1493 continue;
1494
1495 status = __vxge_hw_vpath_xmac_tx_stats_get(
1496 &hldev->virtual_paths[i],
1497 &xmac_stats->vpath_tx_stats[i]);
1498 if (status != VXGE_HW_OK)
1499 goto exit;
1500
1501 status = __vxge_hw_vpath_xmac_rx_stats_get(
1502 &hldev->virtual_paths[i],
1503 &xmac_stats->vpath_rx_stats[i]);
1504 if (status != VXGE_HW_OK)
1505 goto exit;
1506 }
1507exit:
1508 return status;
1509}
1510
1511/*
1512 * vxge_hw_device_debug_set - Set the debug module, level and timestamp
1513 * This routine is used to dynamically change the debug output
1514 */
1515void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
1516 enum vxge_debug_level level, u32 mask)
1517{
1518 if (hldev == NULL)
1519 return;
1520
1521#if defined(VXGE_DEBUG_TRACE_MASK) || \
1522 defined(VXGE_DEBUG_ERR_MASK)
1523 hldev->debug_module_mask = mask;
1524 hldev->debug_level = level;
1525#endif
1526
1527#if defined(VXGE_DEBUG_ERR_MASK)
1528 hldev->level_err = level & VXGE_ERR;
1529#endif
1530
1531#if defined(VXGE_DEBUG_TRACE_MASK)
1532 hldev->level_trace = level & VXGE_TRACE;
1533#endif
1534}
1535
1536/*
1537 * vxge_hw_device_error_level_get - Get the error level
1538 * This routine returns the current error level set
1539 */
1540u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
1541{
1542#if defined(VXGE_DEBUG_ERR_MASK)
1543 if (hldev == NULL)
1544 return VXGE_ERR;
1545 else
1546 return hldev->level_err;
1547#else
1548 return 0;
1549#endif
1550}
1551
1552/*
1553 * vxge_hw_device_trace_level_get - Get the trace level
1554 * This routine returns the current trace level set
1555 */
1556u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
1557{
1558#if defined(VXGE_DEBUG_TRACE_MASK)
1559 if (hldev == NULL)
1560 return VXGE_TRACE;
1561 else
1562 return hldev->level_trace;
1563#else
1564 return 0;
1565#endif
1566}
40a3a915
RV		 1567
1568/*
1569 * vxge_hw_getpause_data -Pause frame frame generation and reception.
1570 * Returns the Pause frame generation and reception capability of the NIC.
1571 */
1572enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
1573 u32 port, u32 *tx, u32 *rx)
1574{
1575 u64 val64;
1576 enum vxge_hw_status status = VXGE_HW_OK;
1577
1578 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1579 status = VXGE_HW_ERR_INVALID_DEVICE;
1580 goto exit;
1581 }
1582
1583 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1584 status = VXGE_HW_ERR_INVALID_PORT;
1585 goto exit;
1586 }
1587
1588 if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
1589 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
1590 goto exit;
1591 }
1592
1593 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1594 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
1595 *tx = 1;
1596 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1597 *rx = 1;
1598exit:
1599 return status;
1600}
1601
1602/*
1603 * vxge_hw_device_setpause_data - set/reset pause frame generation.
1604 * It can be used to set or reset Pause frame generation or reception
1605 * support of the NIC.
1606 */
40a3a915
RV		 1607enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1608 u32 port, u32 tx, u32 rx)
1609{
1610 u64 val64;
1611 enum vxge_hw_status status = VXGE_HW_OK;
1612
1613 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1614 status = VXGE_HW_ERR_INVALID_DEVICE;
1615 goto exit;
1616 }
1617
1618 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1619 status = VXGE_HW_ERR_INVALID_PORT;
1620 goto exit;
1621 }
1622
92cdd7c3
SH		 1623 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1624 hldev->func_id);
40a3a915
RV		 1625 if (status != VXGE_HW_OK)
1626 goto exit;
1627
1628 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1629 if (tx)
1630 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1631 else
1632 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1633 if (rx)
1634 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1635 else
1636 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1637
1638 writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1639exit:
1640 return status;
1641}
1642
1643u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1644{
1645 int link_width, exp_cap;
1646 u16 lnk;
1647
1648 exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
1649 pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
1650 link_width = (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1651 return link_width;
1652}
1653
1654/*
1655 * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1656 * This function returns the index of memory block
1657 */
1658static inline u32
1659__vxge_hw_ring_block_memblock_idx(u8 *block)
1660{
1661 return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1662}
1663
1664/*
1665 * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1666 * This function sets index to a memory block
1667 */
1668static inline void
1669__vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
1670{
1671 *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
1672}
1673
1674/*
1675 * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
1676 * in RxD block
1677 * Sets the next block pointer in RxD block
1678 */
1679static inline void
1680__vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
1681{
1682 *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
1683}
1684
1685/*
1686 * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
1687 * first block
1688 * Returns the dma address of the first RxD block
1689 */
42821a5b 1690static u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
40a3a915
RV		 1691{
1692 struct vxge_hw_mempool_dma *dma_object;
1693
1694 dma_object = ring->mempool->memblocks_dma_arr;
1695 vxge_assert(dma_object != NULL);
1696
1697 return dma_object->addr;
1698}
1699
1700/*
1701 * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
1702 * This function returns the dma address of a given item
1703 */
1704static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
1705 void *item)
1706{
1707 u32 memblock_idx;
1708 void *memblock;
1709 struct vxge_hw_mempool_dma *memblock_dma_object;
1710 ptrdiff_t dma_item_offset;
1711
1712 /* get owner memblock index */
1713 memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
1714
1715 /* get owner memblock by memblock index */
1716 memblock = mempoolh->memblocks_arr[memblock_idx];
1717
1718 /* get memblock DMA object by memblock index */
1719 memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
1720
1721 /* calculate offset in the memblock of this item */
1722 dma_item_offset = (u8 *)item - (u8 *)memblock;
1723
1724 return memblock_dma_object->addr + dma_item_offset;
1725}
1726
1727/*
1728 * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
1729 * This function returns the dma address of a given item
1730 */
1731static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
1732 struct __vxge_hw_ring *ring, u32 from,
1733 u32 to)
1734{
1735 u8 *to_item , *from_item;
1736 dma_addr_t to_dma;
1737
1738 /* get "from" RxD block */
1739 from_item = mempoolh->items_arr[from];
1740 vxge_assert(from_item);
1741
1742 /* get "to" RxD block */
1743 to_item = mempoolh->items_arr[to];
1744 vxge_assert(to_item);
1745
1746 /* return address of the beginning of previous RxD block */
1747 to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
1748
1749 /* set next pointer for this RxD block to point on
1750 * previous item's DMA start address */
1751 __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
1752}
1753
1754/*
1755 * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
1756 * block callback
1757 * This function is callback passed to __vxge_hw_mempool_create to create memory
1758 * pool for RxD block
1759 */
1760static void
1761__vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
1762 u32 memblock_index,
1763 struct vxge_hw_mempool_dma *dma_object,
1764 u32 index, u32 is_last)
1765{
1766 u32 i;
1767 void *item = mempoolh->items_arr[index];
1768 struct __vxge_hw_ring *ring =
1769 (struct __vxge_hw_ring *)mempoolh->userdata;
1770
1771 /* format rxds array */
1772 for (i = 0; i < ring->rxds_per_block; i++) {
1773 void *rxdblock_priv;
1774 void *uld_priv;
1775 struct vxge_hw_ring_rxd_1 *rxdp;
1776
1777 u32 reserve_index = ring->channel.reserve_ptr -
1778 (index * ring->rxds_per_block + i + 1);
1779 u32 memblock_item_idx;
1780
1781 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
1782 i * ring->rxd_size;
1783
1784 /* Note: memblock_item_idx is index of the item within
1785 * the memblock. For instance, in case of three RxD-blocks
1786 * per memblock this value can be 0, 1 or 2. */
1787 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
1788 memblock_index, item,
1789 &memblock_item_idx);
1790
1791 rxdp = (struct vxge_hw_ring_rxd_1 *)
1792 ring->channel.reserve_arr[reserve_index];
1793
1794 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
1795
1796 /* pre-format Host_Control */
1797 rxdp->host_control = (u64)(size_t)uld_priv;
1798 }
1799
1800 __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
1801
1802 if (is_last) {
1803 /* link last one with first one */
1804 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
1805 }
1806
1807 if (index > 0) {
1808 /* link this RxD block with previous one */
1809 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
1810 }
40a3a915
RV		 1811}
1812
1813/*
3363276f 1814 * __vxge_hw_ring_replenish - Initial replenish of RxDs
40a3a915
RV		 1815 * This function replenishes the RxDs from reserve array to work array
1816 */
1817enum vxge_hw_status
3363276f 1818vxge_hw_ring_replenish(struct __vxge_hw_ring *ring)
40a3a915
RV		 1819{
1820 void *rxd;
40a3a915
RV		 1821 struct __vxge_hw_channel *channel;
1822 enum vxge_hw_status status = VXGE_HW_OK;
1823
1824 channel = &ring->channel;
1825
1826 while (vxge_hw_channel_dtr_count(channel) > 0) {
1827
1828 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
1829
1830 vxge_assert(status == VXGE_HW_OK);
1831
1832 if (ring->rxd_init) {
1833 status = ring->rxd_init(rxd, channel->userdata);
1834 if (status != VXGE_HW_OK) {
1835 vxge_hw_ring_rxd_free(ring, rxd);
1836 goto exit;
1837 }
1838 }
1839
1840 vxge_hw_ring_rxd_post(ring, rxd);
40a3a915
RV		 1841 }
1842 status = VXGE_HW_OK;
1843exit:
1844 return status;
1845}
1846
1847/*
1848 * __vxge_hw_ring_create - Create a Ring
1849 * This function creates Ring and initializes it.
40a3a915 1850 */
42821a5b 1851static enum vxge_hw_status
40a3a915
RV		 1852__vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
1853 struct vxge_hw_ring_attr *attr)
1854{
1855 enum vxge_hw_status status = VXGE_HW_OK;
1856 struct __vxge_hw_ring *ring;
1857 u32 ring_length;
1858 struct vxge_hw_ring_config *config;
1859 struct __vxge_hw_device *hldev;
1860 u32 vp_id;
1861 struct vxge_hw_mempool_cbs ring_mp_callback;
1862
1863 if ((vp == NULL) || (attr == NULL)) {
1864 status = VXGE_HW_FAIL;
1865 goto exit;
1866 }
1867
1868 hldev = vp->vpath->hldev;
1869 vp_id = vp->vpath->vp_id;
1870
1871 config = &hldev->config.vp_config[vp_id].ring;
1872
1873 ring_length = config->ring_blocks *
1874 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
1875
1876 ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
1877 VXGE_HW_CHANNEL_TYPE_RING,
1878 ring_length,
1879 attr->per_rxd_space,
1880 attr->userdata);
1881
1882 if (ring == NULL) {
1883 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1884 goto exit;
1885 }
1886
1887 vp->vpath->ringh = ring;
1888 ring->vp_id = vp_id;
1889 ring->vp_reg = vp->vpath->vp_reg;
1890 ring->common_reg = hldev->common_reg;
1891 ring->stats = &vp->vpath->sw_stats->ring_stats;
1892 ring->config = config;
1893 ring->callback = attr->callback;
1894 ring->rxd_init = attr->rxd_init;
1895 ring->rxd_term = attr->rxd_term;
1896 ring->buffer_mode = config->buffer_mode;
1897 ring->rxds_limit = config->rxds_limit;
1898
1899 ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
1900 ring->rxd_priv_size =
1901 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
1902 ring->per_rxd_space = attr->per_rxd_space;
1903
1904 ring->rxd_priv_size =
1905 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
1906 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
1907
1908 /* how many RxDs can fit into one block. Depends on configured
1909 * buffer_mode. */
1910 ring->rxds_per_block =
1911 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
1912
1913 /* calculate actual RxD block private size */
1914 ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
1915 ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc;
1916 ring->mempool = __vxge_hw_mempool_create(hldev,
1917 VXGE_HW_BLOCK_SIZE,
1918 VXGE_HW_BLOCK_SIZE,
1919 ring->rxdblock_priv_size,
1920 ring->config->ring_blocks,
1921 ring->config->ring_blocks,
1922 &ring_mp_callback,
1923 ring);
1924
1925 if (ring->mempool == NULL) {
1926 __vxge_hw_ring_delete(vp);
1927 return VXGE_HW_ERR_OUT_OF_MEMORY;
1928 }
1929
1930 status = __vxge_hw_channel_initialize(&ring->channel);
1931 if (status != VXGE_HW_OK) {
1932 __vxge_hw_ring_delete(vp);
1933 goto exit;
1934 }
1935
1936 /* Note:
1937 * Specifying rxd_init callback means two things:
1938 * 1) rxds need to be initialized by driver at channel-open time;
1939 * 2) rxds need to be posted at channel-open time
1940 * (that's what the initial_replenish() below does)
1941 * Currently we don't have a case when the 1) is done without the 2).
1942 */
1943 if (ring->rxd_init) {
3363276f 1944 status = vxge_hw_ring_replenish(ring);
40a3a915
RV		 1945 if (status != VXGE_HW_OK) {
1946 __vxge_hw_ring_delete(vp);
1947 goto exit;
1948 }
1949 }
1950
1951 /* initial replenish will increment the counter in its post() routine,
1952 * we have to reset it */
1953 ring->stats->common_stats.usage_cnt = 0;
1954exit:
1955 return status;
1956}
1957
1958/*
1959 * __vxge_hw_ring_abort - Returns the RxD
1960 * This function terminates the RxDs of ring
1961 */
42821a5b 1962static enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
40a3a915
RV		 1963{
1964 void *rxdh;
1965 struct __vxge_hw_channel *channel;
1966
1967 channel = &ring->channel;
1968
1969 for (;;) {
1970 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
1971
1972 if (rxdh == NULL)
1973 break;
1974
1975 vxge_hw_channel_dtr_complete(channel);
1976
1977 if (ring->rxd_term)
1978 ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
1979 channel->userdata);
1980
1981 vxge_hw_channel_dtr_free(channel, rxdh);
1982 }
1983
1984 return VXGE_HW_OK;
1985}
1986
1987/*
1988 * __vxge_hw_ring_reset - Resets the ring
1989 * This function resets the ring during vpath reset operation
1990 */
42821a5b 1991static enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
40a3a915
RV		 1992{
1993 enum vxge_hw_status status = VXGE_HW_OK;
1994 struct __vxge_hw_channel *channel;
1995
1996 channel = &ring->channel;
1997
1998 __vxge_hw_ring_abort(ring);
1999
2000 status = __vxge_hw_channel_reset(channel);
2001
2002 if (status != VXGE_HW_OK)
2003 goto exit;
2004
2005 if (ring->rxd_init) {
3363276f 2006 status = vxge_hw_ring_replenish(ring);
40a3a915
RV		 2007 if (status != VXGE_HW_OK)
2008 goto exit;
2009 }
2010exit:
2011 return status;
2012}
2013
2014/*
2015 * __vxge_hw_ring_delete - Removes the ring
2016 * This function freeup the memory pool and removes the ring
2017 */
42821a5b 2018static enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
40a3a915
RV		 2019{
2020 struct __vxge_hw_ring *ring = vp->vpath->ringh;
2021
2022 __vxge_hw_ring_abort(ring);
2023
2024 if (ring->mempool)
2025 __vxge_hw_mempool_destroy(ring->mempool);
2026
2027 vp->vpath->ringh = NULL;
2028 __vxge_hw_channel_free(&ring->channel);
2029
2030 return VXGE_HW_OK;
2031}
2032
2033/*
2034 * __vxge_hw_mempool_grow
2035 * Will resize mempool up to %num_allocate value.
2036 */
42821a5b 2037static enum vxge_hw_status
40a3a915
RV		 2038__vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
2039 u32 *num_allocated)
2040{
2041 u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
2042 u32 n_items = mempool->items_per_memblock;
2043 u32 start_block_idx = mempool->memblocks_allocated;
2044 u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
2045 enum vxge_hw_status status = VXGE_HW_OK;
2046
2047 *num_allocated = 0;
2048
2049 if (end_block_idx > mempool->memblocks_max) {
2050 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2051 goto exit;
2052 }
2053
2054 for (i = start_block_idx; i < end_block_idx; i++) {
2055 u32 j;
2056 u32 is_last = ((end_block_idx - 1) == i);
2057 struct vxge_hw_mempool_dma *dma_object =
2058 mempool->memblocks_dma_arr + i;
2059 void *the_memblock;
2060
2061 /* allocate memblock's private part. Each DMA memblock
2062 * has a space allocated for item's private usage upon
2063 * mempool's user request. Each time mempool grows, it will
2064 * allocate new memblock and its private part at once.
2065 * This helps to minimize memory usage a lot. */
2066 mempool->memblocks_priv_arr[i] =
2067 vmalloc(mempool->items_priv_size * n_items);
2068 if (mempool->memblocks_priv_arr[i] == NULL) {
2069 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2070 goto exit;
2071 }
2072
2073 memset(mempool->memblocks_priv_arr[i], 0,
2074 mempool->items_priv_size * n_items);
2075
2076 /* allocate DMA-capable memblock */
2077 mempool->memblocks_arr[i] =
2078 __vxge_hw_blockpool_malloc(mempool->devh,
2079 mempool->memblock_size, dma_object);
2080 if (mempool->memblocks_arr[i] == NULL) {
2081 vfree(mempool->memblocks_priv_arr[i]);
2082 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2083 goto exit;
2084 }
2085
2086 (*num_allocated)++;
2087 mempool->memblocks_allocated++;
2088
2089 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
2090
2091 the_memblock = mempool->memblocks_arr[i];
2092
2093 /* fill the items hash array */
2094 for (j = 0; j < n_items; j++) {
2095 u32 index = i * n_items + j;
2096
2097 if (first_time && index >= mempool->items_initial)
2098 break;
2099
2100 mempool->items_arr[index] =
2101 ((char *)the_memblock + j*mempool->item_size);
2102
2103 /* let caller to do more job on each item */
2104 if (mempool->item_func_alloc != NULL)
2105 mempool->item_func_alloc(mempool, i,
2106 dma_object, index, is_last);
2107
2108 mempool->items_current = index + 1;
2109 }
2110
2111 if (first_time && mempool->items_current ==
2112 mempool->items_initial)
2113 break;
2114 }
2115exit:
2116 return status;
2117}
2118
2119/*
2120 * vxge_hw_mempool_create
2121 * This function will create memory pool object. Pool may grow but will
2122 * never shrink. Pool consists of number of dynamically allocated blocks
2123 * with size enough to hold %items_initial number of items. Memory is
2124 * DMA-able but client must map/unmap before interoperating with the device.
2125 */
42821a5b 2126static struct vxge_hw_mempool*
40a3a915
RV		 2127__vxge_hw_mempool_create(
2128 struct __vxge_hw_device *devh,
2129 u32 memblock_size,
2130 u32 item_size,
2131 u32 items_priv_size,
2132 u32 items_initial,
2133 u32 items_max,
2134 struct vxge_hw_mempool_cbs *mp_callback,
2135 void *userdata)
2136{
2137 enum vxge_hw_status status = VXGE_HW_OK;
2138 u32 memblocks_to_allocate;
2139 struct vxge_hw_mempool *mempool = NULL;
2140 u32 allocated;
2141
2142 if (memblock_size < item_size) {
2143 status = VXGE_HW_FAIL;
2144 goto exit;
2145 }
2146
2147 mempool = (struct vxge_hw_mempool *)
2148 vmalloc(sizeof(struct vxge_hw_mempool));
2149 if (mempool == NULL) {
2150 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2151 goto exit;
2152 }
2153 memset(mempool, 0, sizeof(struct vxge_hw_mempool));
2154
2155 mempool->devh = devh;
2156 mempool->memblock_size = memblock_size;
2157 mempool->items_max = items_max;
2158 mempool->items_initial = items_initial;
2159 mempool->item_size = item_size;
2160 mempool->items_priv_size = items_priv_size;
2161 mempool->item_func_alloc = mp_callback->item_func_alloc;
2162 mempool->userdata = userdata;
2163
2164 mempool->memblocks_allocated = 0;
2165
2166 mempool->items_per_memblock = memblock_size / item_size;
2167
2168 mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
2169 mempool->items_per_memblock;
2170
2171 /* allocate array of memblocks */
2172 mempool->memblocks_arr =
2173 (void **) vmalloc(sizeof(void *) * mempool->memblocks_max);
2174 if (mempool->memblocks_arr == NULL) {
2175 __vxge_hw_mempool_destroy(mempool);
2176 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2177 mempool = NULL;
2178 goto exit;
2179 }
2180 memset(mempool->memblocks_arr, 0,
2181 sizeof(void *) * mempool->memblocks_max);
2182
2183 /* allocate array of private parts of items per memblocks */
2184 mempool->memblocks_priv_arr =
2185 (void **) vmalloc(sizeof(void *) * mempool->memblocks_max);
2186 if (mempool->memblocks_priv_arr == NULL) {
2187 __vxge_hw_mempool_destroy(mempool);
2188 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2189 mempool = NULL;
2190 goto exit;
2191 }
2192 memset(mempool->memblocks_priv_arr, 0,
2193 sizeof(void *) * mempool->memblocks_max);
2194
2195 /* allocate array of memblocks DMA objects */
2196 mempool->memblocks_dma_arr = (struct vxge_hw_mempool_dma *)
2197 vmalloc(sizeof(struct vxge_hw_mempool_dma) *
2198 mempool->memblocks_max);
2199
2200 if (mempool->memblocks_dma_arr == NULL) {
2201 __vxge_hw_mempool_destroy(mempool);
2202 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2203 mempool = NULL;
2204 goto exit;
2205 }
2206 memset(mempool->memblocks_dma_arr, 0,
2207 sizeof(struct vxge_hw_mempool_dma) *
2208 mempool->memblocks_max);
2209
2210 /* allocate hash array of items */
2211 mempool->items_arr =
2212 (void **) vmalloc(sizeof(void *) * mempool->items_max);
2213 if (mempool->items_arr == NULL) {
2214 __vxge_hw_mempool_destroy(mempool);
2215 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2216 mempool = NULL;
2217 goto exit;
2218 }
2219 memset(mempool->items_arr, 0, sizeof(void *) * mempool->items_max);
2220
2221 /* calculate initial number of memblocks */
2222 memblocks_to_allocate = (mempool->items_initial +
2223 mempool->items_per_memblock - 1) /
2224 mempool->items_per_memblock;
2225
2226 /* pre-allocate the mempool */
2227 status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
2228 &allocated);
2229 if (status != VXGE_HW_OK) {
2230 __vxge_hw_mempool_destroy(mempool);
2231 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2232 mempool = NULL;
2233 goto exit;
2234 }
2235
2236exit:
2237 return mempool;
2238}
2239
2240/*
2241 * vxge_hw_mempool_destroy
2242 */
42821a5b 2243static void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
40a3a915
RV		 2244{
2245 u32 i, j;
2246 struct __vxge_hw_device *devh = mempool->devh;
2247
2248 for (i = 0; i < mempool->memblocks_allocated; i++) {
2249 struct vxge_hw_mempool_dma *dma_object;
2250
2251 vxge_assert(mempool->memblocks_arr[i]);
2252 vxge_assert(mempool->memblocks_dma_arr + i);
2253
2254 dma_object = mempool->memblocks_dma_arr + i;
2255
2256 for (j = 0; j < mempool->items_per_memblock; j++) {
2257 u32 index = i * mempool->items_per_memblock + j;
2258
2259 /* to skip last partially filled(if any) memblock */
2260 if (index >= mempool->items_current)
2261 break;
2262 }
2263
2264 vfree(mempool->memblocks_priv_arr[i]);
2265
2266 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
2267 mempool->memblock_size, dma_object);
2268 }
2269
50d36a93 2270 vfree(mempool->items_arr);
40a3a915 2271
50d36a93 2272 vfree(mempool->memblocks_dma_arr);
40a3a915 2273
50d36a93 2274 vfree(mempool->memblocks_priv_arr);
40a3a915 2275
50d36a93 2276 vfree(mempool->memblocks_arr);
40a3a915
RV		 2277
2278 vfree(mempool);
2279}
2280
2281/*
2282 * __vxge_hw_device_fifo_config_check - Check fifo configuration.
2283 * Check the fifo configuration
2284 */
2c91308f 2285static enum vxge_hw_status
40a3a915
RV		 2286__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
2287{
2288 if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
2289 (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
2290 return VXGE_HW_BADCFG_FIFO_BLOCKS;
2291
2292 return VXGE_HW_OK;
2293}
2294
2295/*
2296 * __vxge_hw_device_vpath_config_check - Check vpath configuration.
2297 * Check the vpath configuration
2298 */
42821a5b 2299static enum vxge_hw_status
40a3a915
RV		 2300__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
2301{
2302 enum vxge_hw_status status;
2303
2304 if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
2305 (vp_config->min_bandwidth >
2306 VXGE_HW_VPATH_BANDWIDTH_MAX))
2307 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
2308
2309 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
2310 if (status != VXGE_HW_OK)
2311 return status;
2312
2313 if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
2314 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
2315 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
2316 return VXGE_HW_BADCFG_VPATH_MTU;
2317
2318 if ((vp_config->rpa_strip_vlan_tag !=
2319 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
2320 (vp_config->rpa_strip_vlan_tag !=
2321 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
2322 (vp_config->rpa_strip_vlan_tag !=
2323 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
2324 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
2325
2326 return VXGE_HW_OK;
2327}
2328
2329/*
2330 * __vxge_hw_device_config_check - Check device configuration.
2331 * Check the device configuration
2332 */
2c91308f 2333static enum vxge_hw_status
40a3a915
RV		 2334__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
2335{
2336 u32 i;
2337 enum vxge_hw_status status;
2338
2339 if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
2340 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
2341 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
2342 (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
2343 return VXGE_HW_BADCFG_INTR_MODE;
2344
2345 if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
2346 (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
2347 return VXGE_HW_BADCFG_RTS_MAC_EN;
2348
2349 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2350 status = __vxge_hw_device_vpath_config_check(
2351 &new_config->vp_config[i]);
2352 if (status != VXGE_HW_OK)
2353 return status;
2354 }
2355
2356 return VXGE_HW_OK;
2357}
2358
2359/*
2360 * vxge_hw_device_config_default_get - Initialize device config with defaults.
2361 * Initialize Titan device config with default values.
2362 */
2363enum vxge_hw_status __devinit
2364vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
2365{
2366 u32 i;
2367
2368 device_config->dma_blockpool_initial =
2369 VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
2370 device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
2371 device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
2372 device_config->rth_en = VXGE_HW_RTH_DEFAULT;
2373 device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
2374 device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS;
2375 device_config->rts_mac_en = VXGE_HW_RTS_MAC_DEFAULT;
2376
2377 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2378
2379 device_config->vp_config[i].vp_id = i;
2380
2381 device_config->vp_config[i].min_bandwidth =
2382 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
2383
2384 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
2385
2386 device_config->vp_config[i].ring.ring_blocks =
2387 VXGE_HW_DEF_RING_BLOCKS;
2388
2389 device_config->vp_config[i].ring.buffer_mode =
2390 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
2391
2392 device_config->vp_config[i].ring.scatter_mode =
2393 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
2394
2395 device_config->vp_config[i].ring.rxds_limit =
2396 VXGE_HW_DEF_RING_RXDS_LIMIT;
2397
2398 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2399
2400 device_config->vp_config[i].fifo.fifo_blocks =
2401 VXGE_HW_MIN_FIFO_BLOCKS;
2402
2403 device_config->vp_config[i].fifo.max_frags =
2404 VXGE_HW_MAX_FIFO_FRAGS;
2405
2406 device_config->vp_config[i].fifo.memblock_size =
2407 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
2408
2409 device_config->vp_config[i].fifo.alignment_size =
2410 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
2411
2412 device_config->vp_config[i].fifo.intr =
2413 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
2414
2415 device_config->vp_config[i].fifo.no_snoop_bits =
2416 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
2417 device_config->vp_config[i].tti.intr_enable =
2418 VXGE_HW_TIM_INTR_DEFAULT;
2419
2420 device_config->vp_config[i].tti.btimer_val =
2421 VXGE_HW_USE_FLASH_DEFAULT;
2422
2423 device_config->vp_config[i].tti.timer_ac_en =
2424 VXGE_HW_USE_FLASH_DEFAULT;
2425
2426 device_config->vp_config[i].tti.timer_ci_en =
2427 VXGE_HW_USE_FLASH_DEFAULT;
2428
2429 device_config->vp_config[i].tti.timer_ri_en =
2430 VXGE_HW_USE_FLASH_DEFAULT;
2431
2432 device_config->vp_config[i].tti.rtimer_val =
2433 VXGE_HW_USE_FLASH_DEFAULT;
2434
2435 device_config->vp_config[i].tti.util_sel =
2436 VXGE_HW_USE_FLASH_DEFAULT;
2437
2438 device_config->vp_config[i].tti.ltimer_val =
2439 VXGE_HW_USE_FLASH_DEFAULT;
2440
2441 device_config->vp_config[i].tti.urange_a =
2442 VXGE_HW_USE_FLASH_DEFAULT;
2443
2444 device_config->vp_config[i].tti.uec_a =
2445 VXGE_HW_USE_FLASH_DEFAULT;
2446
2447 device_config->vp_config[i].tti.urange_b =
2448 VXGE_HW_USE_FLASH_DEFAULT;
2449
2450 device_config->vp_config[i].tti.uec_b =
2451 VXGE_HW_USE_FLASH_DEFAULT;
2452
2453 device_config->vp_config[i].tti.urange_c =
2454 VXGE_HW_USE_FLASH_DEFAULT;
2455
2456 device_config->vp_config[i].tti.uec_c =
2457 VXGE_HW_USE_FLASH_DEFAULT;
2458
2459 device_config->vp_config[i].tti.uec_d =
2460 VXGE_HW_USE_FLASH_DEFAULT;
2461
2462 device_config->vp_config[i].rti.intr_enable =
2463 VXGE_HW_TIM_INTR_DEFAULT;
2464
2465 device_config->vp_config[i].rti.btimer_val =
2466 VXGE_HW_USE_FLASH_DEFAULT;
2467
2468 device_config->vp_config[i].rti.timer_ac_en =
2469 VXGE_HW_USE_FLASH_DEFAULT;
2470
2471 device_config->vp_config[i].rti.timer_ci_en =
2472 VXGE_HW_USE_FLASH_DEFAULT;
2473
2474 device_config->vp_config[i].rti.timer_ri_en =
2475 VXGE_HW_USE_FLASH_DEFAULT;
2476
2477 device_config->vp_config[i].rti.rtimer_val =
2478 VXGE_HW_USE_FLASH_DEFAULT;
2479
2480 device_config->vp_config[i].rti.util_sel =
2481 VXGE_HW_USE_FLASH_DEFAULT;
2482
2483 device_config->vp_config[i].rti.ltimer_val =
2484 VXGE_HW_USE_FLASH_DEFAULT;
2485
2486 device_config->vp_config[i].rti.urange_a =
2487 VXGE_HW_USE_FLASH_DEFAULT;
2488
2489 device_config->vp_config[i].rti.uec_a =
2490 VXGE_HW_USE_FLASH_DEFAULT;
2491
2492 device_config->vp_config[i].rti.urange_b =
2493 VXGE_HW_USE_FLASH_DEFAULT;
2494
2495 device_config->vp_config[i].rti.uec_b =
2496 VXGE_HW_USE_FLASH_DEFAULT;
2497
2498 device_config->vp_config[i].rti.urange_c =
2499 VXGE_HW_USE_FLASH_DEFAULT;
2500
2501 device_config->vp_config[i].rti.uec_c =
2502 VXGE_HW_USE_FLASH_DEFAULT;
2503
2504 device_config->vp_config[i].rti.uec_d =
2505 VXGE_HW_USE_FLASH_DEFAULT;
2506
2507 device_config->vp_config[i].mtu =
2508 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
2509
2510 device_config->vp_config[i].rpa_strip_vlan_tag =
2511 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
2512 }
2513
2514 return VXGE_HW_OK;
2515}
2516
2517/*
2518 * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
2519 * Set the swapper bits appropriately for the lagacy section.
2520 */
42821a5b 2521static enum vxge_hw_status
40a3a915
RV		 2522__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
2523{
2524 u64 val64;
2525 enum vxge_hw_status status = VXGE_HW_OK;
2526
2527 val64 = readq(&legacy_reg->toc_swapper_fb);
2528
2529 wmb();
2530
2531 switch (val64) {
2532
2533 case VXGE_HW_SWAPPER_INITIAL_VALUE:
2534 return status;
2535
2536 case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
2537 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
2538 &legacy_reg->pifm_rd_swap_en);
2539 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
2540 &legacy_reg->pifm_rd_flip_en);
2541 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
2542 &legacy_reg->pifm_wr_swap_en);
2543 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
2544 &legacy_reg->pifm_wr_flip_en);
2545 break;
2546
2547 case VXGE_HW_SWAPPER_BYTE_SWAPPED:
2548 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
2549 &legacy_reg->pifm_rd_swap_en);
2550 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
2551 &legacy_reg->pifm_wr_swap_en);
2552 break;
2553
2554 case VXGE_HW_SWAPPER_BIT_FLIPPED:
2555 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
2556 &legacy_reg->pifm_rd_flip_en);
2557 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
2558 &legacy_reg->pifm_wr_flip_en);
2559 break;
2560 }
2561
2562 wmb();
2563
2564 val64 = readq(&legacy_reg->toc_swapper_fb);
2565
2566 if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
2567 status = VXGE_HW_ERR_SWAPPER_CTRL;
2568
2569 return status;
2570}
2571
2572/*
2573 * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
2574 * Set the swapper bits appropriately for the vpath.
2575 */
42821a5b 2576static enum vxge_hw_status
40a3a915
RV		 2577__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
2578{
2579#ifndef __BIG_ENDIAN
2580 u64 val64;
2581
2582 val64 = readq(&vpath_reg->vpath_general_cfg1);
2583 wmb();
2584 val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
2585 writeq(val64, &vpath_reg->vpath_general_cfg1);
2586 wmb();
2587#endif
2588 return VXGE_HW_OK;
2589}
2590
2591/*
2592 * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
2593 * Set the swapper bits appropriately for the vpath.
2594 */
42821a5b 2595static enum vxge_hw_status
40a3a915
RV		 2596__vxge_hw_kdfc_swapper_set(
2597 struct vxge_hw_legacy_reg __iomem *legacy_reg,
2598 struct vxge_hw_vpath_reg __iomem *vpath_reg)
2599{
2600 u64 val64;
2601
2602 val64 = readq(&legacy_reg->pifm_wr_swap_en);
2603
2604 if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
2605 val64 = readq(&vpath_reg->kdfcctl_cfg0);
2606 wmb();
2607
2608 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
2609 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
2610 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
2611
2612 writeq(val64, &vpath_reg->kdfcctl_cfg0);
2613 wmb();
2614 }
2615
2616 return VXGE_HW_OK;
2617}
2618
40a3a915
RV		 2619/*
2620 * vxge_hw_mgmt_reg_read - Read Titan register.
2621 */
2622enum vxge_hw_status
2623vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
2624 enum vxge_hw_mgmt_reg_type type,
2625 u32 index, u32 offset, u64 *value)
2626{
2627 enum vxge_hw_status status = VXGE_HW_OK;
2628
2629 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
2630 status = VXGE_HW_ERR_INVALID_DEVICE;
2631 goto exit;
2632 }
2633
2634 switch (type) {
2635 case vxge_hw_mgmt_reg_type_legacy:
2636 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
2637 status = VXGE_HW_ERR_INVALID_OFFSET;
2638 break;
2639 }
2640 *value = readq((void __iomem *)hldev->legacy_reg + offset);
2641 break;
2642 case vxge_hw_mgmt_reg_type_toc:
2643 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
2644 status = VXGE_HW_ERR_INVALID_OFFSET;
2645 break;
2646 }
2647 *value = readq((void __iomem *)hldev->toc_reg + offset);
2648 break;
2649 case vxge_hw_mgmt_reg_type_common:
2650 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
2651 status = VXGE_HW_ERR_INVALID_OFFSET;
2652 break;
2653 }
2654 *value = readq((void __iomem *)hldev->common_reg + offset);
2655 break;
2656 case vxge_hw_mgmt_reg_type_mrpcim:
2657 if (!(hldev->access_rights &
2658 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2659 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2660 break;
2661 }
2662 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
2663 status = VXGE_HW_ERR_INVALID_OFFSET;
2664 break;
2665 }
2666 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
2667 break;
2668 case vxge_hw_mgmt_reg_type_srpcim:
2669 if (!(hldev->access_rights &
2670 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
2671 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2672 break;
2673 }
2674 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
2675 status = VXGE_HW_ERR_INVALID_INDEX;
2676 break;
2677 }
2678 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
2679 status = VXGE_HW_ERR_INVALID_OFFSET;
2680 break;
2681 }
2682 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
2683 offset);
2684 break;
2685 case vxge_hw_mgmt_reg_type_vpmgmt:
2686 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
2687 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2688 status = VXGE_HW_ERR_INVALID_INDEX;
2689 break;
2690 }
2691 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
2692 status = VXGE_HW_ERR_INVALID_OFFSET;
2693 break;
2694 }
2695 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
2696 offset);
2697 break;
2698 case vxge_hw_mgmt_reg_type_vpath:
2699 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
2700 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2701 status = VXGE_HW_ERR_INVALID_INDEX;
2702 break;
2703 }
2704 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
2705 status = VXGE_HW_ERR_INVALID_INDEX;
2706 break;
2707 }
2708 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
2709 status = VXGE_HW_ERR_INVALID_OFFSET;
2710 break;
2711 }
2712 *value = readq((void __iomem *)hldev->vpath_reg[index] +
2713 offset);
2714 break;
2715 default:
2716 status = VXGE_HW_ERR_INVALID_TYPE;
2717 break;
2718 }
2719
2720exit:
2721 return status;
2722}
2723
fa41fd10
SH		 2724/*
2725 * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
2726 */
2727enum vxge_hw_status
2728vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
2729{
2730 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
2731 enum vxge_hw_status status = VXGE_HW_OK;
2732 int i = 0, j = 0;
2733
2734 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2735 if (!((vpath_mask) & vxge_mBIT(i)))
2736 continue;
2737 vpmgmt_reg = hldev->vpmgmt_reg[i];
2738 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
2739 if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
2740 & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
2741 return VXGE_HW_FAIL;
2742 }
2743 }
2744 return status;
2745}
40a3a915
RV		 2746/*
2747 * vxge_hw_mgmt_reg_Write - Write Titan register.
2748 */
2749enum vxge_hw_status
2750vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
2751 enum vxge_hw_mgmt_reg_type type,
2752 u32 index, u32 offset, u64 value)
2753{
2754 enum vxge_hw_status status = VXGE_HW_OK;
2755
2756 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
2757 status = VXGE_HW_ERR_INVALID_DEVICE;
2758 goto exit;
2759 }
2760
2761 switch (type) {
2762 case vxge_hw_mgmt_reg_type_legacy:
2763 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
2764 status = VXGE_HW_ERR_INVALID_OFFSET;
2765 break;
2766 }
2767 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
2768 break;
2769 case vxge_hw_mgmt_reg_type_toc:
2770 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
2771 status = VXGE_HW_ERR_INVALID_OFFSET;
2772 break;
2773 }
2774 writeq(value, (void __iomem *)hldev->toc_reg + offset);
2775 break;
2776 case vxge_hw_mgmt_reg_type_common:
2777 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
2778 status = VXGE_HW_ERR_INVALID_OFFSET;
2779 break;
2780 }
2781 writeq(value, (void __iomem *)hldev->common_reg + offset);
2782 break;
2783 case vxge_hw_mgmt_reg_type_mrpcim:
2784 if (!(hldev->access_rights &
2785 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2786 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2787 break;
2788 }
2789 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
2790 status = VXGE_HW_ERR_INVALID_OFFSET;
2791 break;
2792 }
2793 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
2794 break;
2795 case vxge_hw_mgmt_reg_type_srpcim:
2796 if (!(hldev->access_rights &
2797 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
2798 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2799 break;
2800 }
2801 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
2802 status = VXGE_HW_ERR_INVALID_INDEX;
2803 break;
2804 }
2805 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
2806 status = VXGE_HW_ERR_INVALID_OFFSET;
2807 break;
2808 }
2809 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
2810 offset);
2811
2812 break;
2813 case vxge_hw_mgmt_reg_type_vpmgmt:
2814 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
2815 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2816 status = VXGE_HW_ERR_INVALID_INDEX;
2817 break;
2818 }
2819 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
2820 status = VXGE_HW_ERR_INVALID_OFFSET;
2821 break;
2822 }
2823 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
2824 offset);
2825 break;
2826 case vxge_hw_mgmt_reg_type_vpath:
2827 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
2828 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2829 status = VXGE_HW_ERR_INVALID_INDEX;
2830 break;
2831 }
2832 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
2833 status = VXGE_HW_ERR_INVALID_OFFSET;
2834 break;
2835 }
2836 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
2837 offset);
2838 break;
2839 default:
2840 status = VXGE_HW_ERR_INVALID_TYPE;
2841 break;
2842 }
2843exit:
2844 return status;
2845}
2846
2847/*
2848 * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
2849 * list callback
2850 * This function is callback passed to __vxge_hw_mempool_create to create memory
2851 * pool for TxD list
2852 */
2853static void
2854__vxge_hw_fifo_mempool_item_alloc(
2855 struct vxge_hw_mempool *mempoolh,
2856 u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
2857 u32 index, u32 is_last)
2858{
2859 u32 memblock_item_idx;
2860 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
2861 struct vxge_hw_fifo_txd *txdp =
2862 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
2863 struct __vxge_hw_fifo *fifo =
2864 (struct __vxge_hw_fifo *)mempoolh->userdata;
2865 void *memblock = mempoolh->memblocks_arr[memblock_index];
2866
2867 vxge_assert(txdp);
2868
2869 txdp->host_control = (u64) (size_t)
2870 __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
2871 &memblock_item_idx);
2872
2873 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
2874
2875 vxge_assert(txdl_priv);
2876
2877 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
2878
2879 /* pre-format HW's TxDL's private */
2880 txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
2881 txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
2882 txdl_priv->dma_handle = dma_object->handle;
2883 txdl_priv->memblock = memblock;
2884 txdl_priv->first_txdp = txdp;
2885 txdl_priv->next_txdl_priv = NULL;
2886 txdl_priv->alloc_frags = 0;
40a3a915
RV		 2887}
2888
2889/*
2890 * __vxge_hw_fifo_create - Create a FIFO
2891 * This function creates FIFO and initializes it.
2892 */
2c91308f 2893static enum vxge_hw_status
40a3a915
RV		 2894__vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
2895 struct vxge_hw_fifo_attr *attr)
2896{
2897 enum vxge_hw_status status = VXGE_HW_OK;
2898 struct __vxge_hw_fifo *fifo;
2899 struct vxge_hw_fifo_config *config;
2900 u32 txdl_size, txdl_per_memblock;
2901 struct vxge_hw_mempool_cbs fifo_mp_callback;
2902 struct __vxge_hw_virtualpath *vpath;
2903
2904 if ((vp == NULL) || (attr == NULL)) {
2905 status = VXGE_HW_ERR_INVALID_HANDLE;
2906 goto exit;
2907 }
2908 vpath = vp->vpath;
2909 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
2910
2911 txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
2912
2913 txdl_per_memblock = config->memblock_size / txdl_size;
2914
2915 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
2916 VXGE_HW_CHANNEL_TYPE_FIFO,
2917 config->fifo_blocks * txdl_per_memblock,
2918 attr->per_txdl_space, attr->userdata);
2919
2920 if (fifo == NULL) {
2921 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2922 goto exit;
2923 }
2924
2925 vpath->fifoh = fifo;
2926 fifo->nofl_db = vpath->nofl_db;
2927
2928 fifo->vp_id = vpath->vp_id;
2929 fifo->vp_reg = vpath->vp_reg;
2930 fifo->stats = &vpath->sw_stats->fifo_stats;
2931
2932 fifo->config = config;
2933
2934 /* apply "interrupts per txdl" attribute */
2935 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
2936
2937 if (fifo->config->intr)
2938 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
2939
2940 fifo->no_snoop_bits = config->no_snoop_bits;
2941
2942 /*
2943 * FIFO memory management strategy:
2944 *
2945 * TxDL split into three independent parts:
2946 * - set of TxD's
2947 * - TxD HW private part
2948 * - driver private part
2949 *
2950 * Adaptative memory allocation used. i.e. Memory allocated on
2951 * demand with the size which will fit into one memory block.
2952 * One memory block may contain more than one TxDL.
2953 *
2954 * During "reserve" operations more memory can be allocated on demand
2955 * for example due to FIFO full condition.
2956 *
2957 * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
2958 * routine which will essentially stop the channel and free resources.
2959 */
2960
2961 /* TxDL common private size == TxDL private + driver private */
2962 fifo->priv_size =
2963 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
2964 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2965 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2966
2967 fifo->per_txdl_space = attr->per_txdl_space;
2968
2969 /* recompute txdl size to be cacheline aligned */
2970 fifo->txdl_size = txdl_size;
2971 fifo->txdl_per_memblock = txdl_per_memblock;
2972
2973 fifo->txdl_term = attr->txdl_term;
2974 fifo->callback = attr->callback;
2975
2976 if (fifo->txdl_per_memblock == 0) {
2977 __vxge_hw_fifo_delete(vp);
2978 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
2979 goto exit;
2980 }
2981
2982 fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
2983
2984 fifo->mempool =
2985 __vxge_hw_mempool_create(vpath->hldev,
2986 fifo->config->memblock_size,
2987 fifo->txdl_size,
2988 fifo->priv_size,
2989 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
2990 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
2991 &fifo_mp_callback,
2992 fifo);
2993
2994 if (fifo->mempool == NULL) {
2995 __vxge_hw_fifo_delete(vp);
2996 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2997 goto exit;
2998 }
2999
3000 status = __vxge_hw_channel_initialize(&fifo->channel);
3001 if (status != VXGE_HW_OK) {
3002 __vxge_hw_fifo_delete(vp);
3003 goto exit;
3004 }
3005
3006 vxge_assert(fifo->channel.reserve_ptr);
3007exit:
3008 return status;
3009}
3010
3011/*
3012 * __vxge_hw_fifo_abort - Returns the TxD
3013 * This function terminates the TxDs of fifo
3014 */
42821a5b 3015static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
40a3a915
RV		 3016{
3017 void *txdlh;
3018
3019 for (;;) {
3020 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3021
3022 if (txdlh == NULL)
3023 break;
3024
3025 vxge_hw_channel_dtr_complete(&fifo->channel);
3026
3027 if (fifo->txdl_term) {
3028 fifo->txdl_term(txdlh,
3029 VXGE_HW_TXDL_STATE_POSTED,
3030 fifo->channel.userdata);
3031 }
3032
3033 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3034 }
3035
3036 return VXGE_HW_OK;
3037}
3038
3039/*
3040 * __vxge_hw_fifo_reset - Resets the fifo
3041 * This function resets the fifo during vpath reset operation
3042 */
42821a5b 3043static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
40a3a915
RV		 3044{
3045 enum vxge_hw_status status = VXGE_HW_OK;
3046
3047 __vxge_hw_fifo_abort(fifo);
3048 status = __vxge_hw_channel_reset(&fifo->channel);
3049
3050 return status;
3051}
3052
3053/*
3054 * __vxge_hw_fifo_delete - Removes the FIFO
3055 * This function freeup the memory pool and removes the FIFO
3056 */
2c91308f
JM		 3057static enum vxge_hw_status
3058__vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
40a3a915
RV		 3059{
3060 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3061
3062 __vxge_hw_fifo_abort(fifo);
3063
3064 if (fifo->mempool)
3065 __vxge_hw_mempool_destroy(fifo->mempool);
3066
3067 vp->vpath->fifoh = NULL;
3068
3069 __vxge_hw_channel_free(&fifo->channel);
3070
3071 return VXGE_HW_OK;
3072}
3073
3074/*
3075 * __vxge_hw_vpath_pci_read - Read the content of given address
3076 * in pci config space.
3077 * Read from the vpath pci config space.
3078 */
42821a5b 3079static enum vxge_hw_status
40a3a915
RV		 3080__vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
3081 u32 phy_func_0, u32 offset, u32 *val)
3082{
3083 u64 val64;
3084 enum vxge_hw_status status = VXGE_HW_OK;
3085 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
3086
3087 val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
3088
3089 if (phy_func_0)
3090 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
3091
3092 writeq(val64, &vp_reg->pci_config_access_cfg1);
3093 wmb();
3094 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
3095 &vp_reg->pci_config_access_cfg2);
3096 wmb();
3097
3098 status = __vxge_hw_device_register_poll(
3099 &vp_reg->pci_config_access_cfg2,
3100 VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3101
3102 if (status != VXGE_HW_OK)
3103 goto exit;
3104
3105 val64 = readq(&vp_reg->pci_config_access_status);
3106
3107 if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
3108 status = VXGE_HW_FAIL;
3109 *val = 0;
3110 } else
3111 *val = (u32)vxge_bVALn(val64, 32, 32);
3112exit:
3113 return status;
3114}
3115
40a3a915
RV		 3116/**
3117 * vxge_hw_device_flick_link_led - Flick (blink) link LED.
3118 * @hldev: HW device.
3119 * @on_off: TRUE if flickering to be on, FALSE to be off
3120 *
3121 * Flicker the link LED.
3122 */
3123enum vxge_hw_status
8424e00d 3124vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev, u64 on_off)
40a3a915 3125{
8424e00d
JM		 3126 struct __vxge_hw_virtualpath *vpath;
3127 u64 data0, data1 = 0, steer_ctrl = 0;
3128 enum vxge_hw_status status;
40a3a915
RV		 3129
3130 if (hldev == NULL) {
3131 status = VXGE_HW_ERR_INVALID_DEVICE;
3132 goto exit;
3133 }
3134
8424e00d 3135 vpath = &hldev->virtual_paths[hldev->first_vp_id];
40a3a915 3136
8424e00d
JM		 3137 data0 = on_off;
3138 status = vxge_hw_vpath_fw_api(vpath,
3139 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL,
3140 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO,
3141 0, &data0, &data1, &steer_ctrl);
40a3a915
RV		 3142exit:
3143 return status;
3144}
3145
3146/*
3147 * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
3148 */
3149enum vxge_hw_status
8424e00d
JM		 3150__vxge_hw_vpath_rts_table_get(struct __vxge_hw_vpath_handle *vp,
3151 u32 action, u32 rts_table, u32 offset,
3152 u64 *data0, u64 *data1)
40a3a915 3153{
8424e00d
JM		 3154 enum vxge_hw_status status;
3155 u64 steer_ctrl = 0;
40a3a915
RV		 3156
3157 if (vp == NULL) {
3158 status = VXGE_HW_ERR_INVALID_HANDLE;
3159 goto exit;
3160 }
3161
40a3a915 3162 if ((rts_table ==
8424e00d 3163 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
40a3a915 3164 (rts_table ==
8424e00d 3165 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
40a3a915 3166 (rts_table ==
8424e00d 3167 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
40a3a915 3168 (rts_table ==
8424e00d
JM		 3169 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
3170 steer_ctrl = VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
40a3a915
RV		 3171 }
3172
8424e00d
JM		 3173 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3174 data0, data1, &steer_ctrl);
40a3a915
RV		 3175 if (status != VXGE_HW_OK)
3176 goto exit;
3177
8424e00d
JM		 3178 if ((rts_table != VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3179 (rts_table !=
3180 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3181 *data1 = 0;
40a3a915
RV		 3182exit:
3183 return status;
3184}
3185
3186/*
3187 * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
3188 */
3189enum vxge_hw_status
8424e00d
JM		 3190__vxge_hw_vpath_rts_table_set(struct __vxge_hw_vpath_handle *vp, u32 action,
3191 u32 rts_table, u32 offset, u64 steer_data0,
3192 u64 steer_data1)
40a3a915 3193{
8424e00d
JM		 3194 u64 data0, data1 = 0, steer_ctrl = 0;
3195 enum vxge_hw_status status;
40a3a915
RV		 3196
3197 if (vp == NULL) {
3198 status = VXGE_HW_ERR_INVALID_HANDLE;
3199 goto exit;
3200 }
3201
8424e00d 3202 data0 = steer_data0;
40a3a915
RV		 3203
3204 if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
3205 (rts_table ==
8424e00d
JM		 3206 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT))
3207 data1 = steer_data1;
40a3a915 3208
8424e00d
JM		 3209 status = vxge_hw_vpath_fw_api(vp->vpath, action, rts_table, offset,
3210 &data0, &data1, &steer_ctrl);
40a3a915
RV		 3211exit:
3212 return status;
3213}
3214
3215/*
3216 * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3217 */
3218enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3219 struct __vxge_hw_vpath_handle *vp,
3220 enum vxge_hw_rth_algoritms algorithm,
3221 struct vxge_hw_rth_hash_types *hash_type,
3222 u16 bucket_size)
3223{
3224 u64 data0, data1;
3225 enum vxge_hw_status status = VXGE_HW_OK;
3226
3227 if (vp == NULL) {
3228 status = VXGE_HW_ERR_INVALID_HANDLE;
3229 goto exit;
3230 }
3231
3232 status = __vxge_hw_vpath_rts_table_get(vp,
3233 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3234 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3235 0, &data0, &data1);
47f01db4
JM		 3236 if (status != VXGE_HW_OK)
3237 goto exit;
40a3a915
RV		 3238
3239 data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3240 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3241
3242 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3243 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3244 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3245
3246 if (hash_type->hash_type_tcpipv4_en)
3247 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3248
3249 if (hash_type->hash_type_ipv4_en)
3250 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3251
3252 if (hash_type->hash_type_tcpipv6_en)
3253 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3254
3255 if (hash_type->hash_type_ipv6_en)
3256 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3257
3258 if (hash_type->hash_type_tcpipv6ex_en)
3259 data0 |=
3260 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3261
3262 if (hash_type->hash_type_ipv6ex_en)
3263 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3264
3265 if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3266 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3267 else
3268 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3269
3270 status = __vxge_hw_vpath_rts_table_set(vp,
3271 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3272 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3273 0, data0, 0);
3274exit:
3275 return status;
3276}
3277
3278static void
3279vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3280 u16 flag, u8 *itable)
3281{
3282 switch (flag) {
3283 case 1:
3284 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3285 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3286 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3287 itable[j]);
3288 case 2:
3289 *data0 |=
3290 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3291 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3292 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3293 itable[j]);
3294 case 3:
3295 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3296 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3297 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3298 itable[j]);
3299 case 4:
3300 *data1 |=
3301 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3302 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3303 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3304 itable[j]);
3305 default:
3306 return;
3307 }
3308}
3309/*
3310 * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3311 */
3312enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3313 struct __vxge_hw_vpath_handle **vpath_handles,
3314 u32 vpath_count,
3315 u8 *mtable,
3316 u8 *itable,
3317 u32 itable_size)
3318{
3319 u32 i, j, action, rts_table;
3320 u64 data0;
3321 u64 data1;
3322 u32 max_entries;
3323 enum vxge_hw_status status = VXGE_HW_OK;
3324 struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3325
3326 if (vp == NULL) {
3327 status = VXGE_HW_ERR_INVALID_HANDLE;
3328 goto exit;
3329 }
3330
3331 max_entries = (((u32)1) << itable_size);
3332
3333 if (vp->vpath->hldev->config.rth_it_type
3334 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3335 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3336 rts_table =
3337 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3338
3339 for (j = 0; j < max_entries; j++) {
3340
3341 data1 = 0;
3342
3343 data0 =
3344 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3345 itable[j]);
3346
3347 status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3348 action, rts_table, j, data0, data1);
3349
3350 if (status != VXGE_HW_OK)
3351 goto exit;
3352 }
3353
3354 for (j = 0; j < max_entries; j++) {
3355
3356 data1 = 0;
3357
3358 data0 =
3359 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3360 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3361 itable[j]);
3362
3363 status = __vxge_hw_vpath_rts_table_set(
3364 vpath_handles[mtable[itable[j]]], action,
3365 rts_table, j, data0, data1);
3366
3367 if (status != VXGE_HW_OK)
3368 goto exit;
3369 }
3370 } else {
3371 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3372 rts_table =
3373 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3374 for (i = 0; i < vpath_count; i++) {
3375
3376 for (j = 0; j < max_entries;) {
3377
3378 data0 = 0;
3379 data1 = 0;
3380
3381 while (j < max_entries) {
3382 if (mtable[itable[j]] != i) {
3383 j++;
3384 continue;
3385 }
3386 vxge_hw_rts_rth_data0_data1_get(j,
3387 &data0, &data1, 1, itable);
3388 j++;
3389 break;
3390 }
3391
3392 while (j < max_entries) {
3393 if (mtable[itable[j]] != i) {
3394 j++;
3395 continue;
3396 }
3397 vxge_hw_rts_rth_data0_data1_get(j,
3398 &data0, &data1, 2, itable);
3399 j++;
3400 break;
3401 }
3402
3403 while (j < max_entries) {
3404 if (mtable[itable[j]] != i) {
3405 j++;
3406 continue;
3407 }
3408 vxge_hw_rts_rth_data0_data1_get(j,
3409 &data0, &data1, 3, itable);
3410 j++;
3411 break;
3412 }
3413
3414 while (j < max_entries) {
3415 if (mtable[itable[j]] != i) {
3416 j++;
3417 continue;
3418 }
3419 vxge_hw_rts_rth_data0_data1_get(j,
3420 &data0, &data1, 4, itable);
3421 j++;
3422 break;
3423 }
3424
3425 if (data0 != 0) {
3426 status = __vxge_hw_vpath_rts_table_set(
3427 vpath_handles[i],
3428 action, rts_table,
3429 0, data0, data1);
3430
3431 if (status != VXGE_HW_OK)
3432 goto exit;
3433 }
3434 }
3435 }
3436 }
3437exit:
3438 return status;
3439}
3440
3441/**
3442 * vxge_hw_vpath_check_leak - Check for memory leak
3443 * @ringh: Handle to the ring object used for receive
3444 *
3445 * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3446 * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3447 * Returns: VXGE_HW_FAIL, if leak has occurred.
3448 *
3449 */
3450enum vxge_hw_status
3451vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3452{
3453 enum vxge_hw_status status = VXGE_HW_OK;
3454 u64 rxd_new_count, rxd_spat;
3455
3456 if (ring == NULL)
3457 return status;
3458
3459 rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3460 rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3461 rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3462
3463 if (rxd_new_count >= rxd_spat)
3464 status = VXGE_HW_FAIL;
3465
3466 return status;
3467}
3468
3469/*
3470 * __vxge_hw_vpath_mgmt_read
3471 * This routine reads the vpath_mgmt registers
3472 */
3473static enum vxge_hw_status
3474__vxge_hw_vpath_mgmt_read(
3475 struct __vxge_hw_device *hldev,
3476 struct __vxge_hw_virtualpath *vpath)
3477{
3478 u32 i, mtu = 0, max_pyld = 0;
3479 u64 val64;
3480 enum vxge_hw_status status = VXGE_HW_OK;
3481
3482 for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3483
3484 val64 = readq(&vpath->vpmgmt_reg->
3485 rxmac_cfg0_port_vpmgmt_clone[i]);
3486 max_pyld =
3487 (u32)
3488 VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3489 (val64);
3490 if (mtu < max_pyld)
3491 mtu = max_pyld;
3492 }
3493
3494 vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3495
3496 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3497
3498 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3499 if (val64 & vxge_mBIT(i))
3500 vpath->vsport_number = i;
3501 }
3502
3503 val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
3504
3505 if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
3506 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
3507 else
3508 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
3509
3510 return status;
3511}
3512
3513/*
3514 * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
3515 * This routine checks the vpath_rst_in_prog register to see if
3516 * adapter completed the reset process for the vpath
3517 */
42821a5b 3518static enum vxge_hw_status
40a3a915
RV		 3519__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
3520{
3521 enum vxge_hw_status status;
3522
3523 status = __vxge_hw_device_register_poll(
3524 &vpath->hldev->common_reg->vpath_rst_in_prog,
3525 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
3526 1 << (16 - vpath->vp_id)),
3527 vpath->hldev->config.device_poll_millis);
3528
3529 return status;
3530}
3531
3532/*
3533 * __vxge_hw_vpath_reset
3534 * This routine resets the vpath on the device
3535 */
42821a5b 3536static enum vxge_hw_status
40a3a915
RV		 3537__vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
3538{
3539 u64 val64;
3540 enum vxge_hw_status status = VXGE_HW_OK;
3541
3542 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
3543
3544 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
3545 &hldev->common_reg->cmn_rsthdlr_cfg0);
3546
3547 return status;
3548}
3549
3550/*
3551 * __vxge_hw_vpath_sw_reset
3552 * This routine resets the vpath structures
3553 */
42821a5b 3554static enum vxge_hw_status
40a3a915
RV		 3555__vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
3556{
3557 enum vxge_hw_status status = VXGE_HW_OK;
3558 struct __vxge_hw_virtualpath *vpath;
3559
3560 vpath = (struct __vxge_hw_virtualpath *)&hldev->virtual_paths[vp_id];
3561
3562 if (vpath->ringh) {
3563 status = __vxge_hw_ring_reset(vpath->ringh);
3564 if (status != VXGE_HW_OK)
3565 goto exit;
3566 }
3567
3568 if (vpath->fifoh)
3569 status = __vxge_hw_fifo_reset(vpath->fifoh);
3570exit:
3571 return status;
3572}
3573
3574/*
3575 * __vxge_hw_vpath_prc_configure
3576 * This routine configures the prc registers of virtual path using the config
3577 * passed
3578 */
42821a5b 3579static void
40a3a915
RV		 3580__vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3581{
3582 u64 val64;
3583 struct __vxge_hw_virtualpath *vpath;
3584 struct vxge_hw_vp_config *vp_config;
3585 struct vxge_hw_vpath_reg __iomem *vp_reg;
3586
3587 vpath = &hldev->virtual_paths[vp_id];
3588 vp_reg = vpath->vp_reg;
3589 vp_config = vpath->vp_config;
3590
3591 if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
3592 return;
3593
3594 val64 = readq(&vp_reg->prc_cfg1);
3595 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
3596 writeq(val64, &vp_reg->prc_cfg1);
3597
3598 val64 = readq(&vpath->vp_reg->prc_cfg6);
3599 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
3600 writeq(val64, &vpath->vp_reg->prc_cfg6);
3601
3602 val64 = readq(&vp_reg->prc_cfg7);
3603
3604 if (vpath->vp_config->ring.scatter_mode !=
3605 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
3606
3607 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
3608
3609 switch (vpath->vp_config->ring.scatter_mode) {
3610 case VXGE_HW_RING_SCATTER_MODE_A:
3611 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3612 VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
3613 break;
3614 case VXGE_HW_RING_SCATTER_MODE_B:
3615 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3616 VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
3617 break;
3618 case VXGE_HW_RING_SCATTER_MODE_C:
3619 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3620 VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
3621 break;
3622 }
3623 }
3624
3625 writeq(val64, &vp_reg->prc_cfg7);
3626
3627 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
3628 __vxge_hw_ring_first_block_address_get(
3629 vpath->ringh) >> 3), &vp_reg->prc_cfg5);
3630
3631 val64 = readq(&vp_reg->prc_cfg4);
3632 val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
3633 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
3634
3635 val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
3636 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
3637
3638 if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
3639 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
3640 else
3641 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
3642
3643 writeq(val64, &vp_reg->prc_cfg4);
40a3a915
RV		 3644}
3645
3646/*
3647 * __vxge_hw_vpath_kdfc_configure
3648 * This routine configures the kdfc registers of virtual path using the
3649 * config passed
3650 */
42821a5b 3651static enum vxge_hw_status
40a3a915
RV		 3652__vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3653{
3654 u64 val64;
3655 u64 vpath_stride;
3656 enum vxge_hw_status status = VXGE_HW_OK;
3657 struct __vxge_hw_virtualpath *vpath;
3658 struct vxge_hw_vpath_reg __iomem *vp_reg;
3659
3660 vpath = &hldev->virtual_paths[vp_id];
3661 vp_reg = vpath->vp_reg;
3662 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
3663
3664 if (status != VXGE_HW_OK)
3665 goto exit;
3666
3667 val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
3668
3669 vpath->max_kdfc_db =
3670 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
3671 val64+1)/2;
3672
3673 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3674
3675 vpath->max_nofl_db = vpath->max_kdfc_db;
3676
3677 if (vpath->max_nofl_db <
3678 ((vpath->vp_config->fifo.memblock_size /
3679 (vpath->vp_config->fifo.max_frags *
3680 sizeof(struct vxge_hw_fifo_txd))) *
3681 vpath->vp_config->fifo.fifo_blocks)) {
3682
3683 return VXGE_HW_BADCFG_FIFO_BLOCKS;
3684 }
3685 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
3686 (vpath->max_nofl_db*2)-1);
3687 }
3688
3689 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
3690
3691 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
3692 &vp_reg->kdfc_fifo_trpl_ctrl);
3693
3694 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
3695
3696 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
3697 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
3698
3699 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
3700 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
3701#ifndef __BIG_ENDIAN
3702 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
3703#endif
3704 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
3705
3706 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
3707 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
3708 wmb();
3709 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
3710
3711 vpath->nofl_db =
3712 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
3713 (hldev->kdfc + (vp_id *
3714 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
3715 vpath_stride)));
3716exit:
3717 return status;
3718}
3719
3720/*
3721 * __vxge_hw_vpath_mac_configure
3722 * This routine configures the mac of virtual path using the config passed
3723 */
42821a5b 3724static enum vxge_hw_status
40a3a915
RV		 3725__vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3726{
3727 u64 val64;
3728 enum vxge_hw_status status = VXGE_HW_OK;
3729 struct __vxge_hw_virtualpath *vpath;
3730 struct vxge_hw_vp_config *vp_config;
3731 struct vxge_hw_vpath_reg __iomem *vp_reg;
3732
3733 vpath = &hldev->virtual_paths[vp_id];
3734 vp_reg = vpath->vp_reg;
3735 vp_config = vpath->vp_config;
3736
3737 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
3738 vpath->vsport_number), &vp_reg->xmac_vsport_choice);
3739
3740 if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
3741
3742 val64 = readq(&vp_reg->xmac_rpa_vcfg);
3743
3744 if (vp_config->rpa_strip_vlan_tag !=
3745 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
3746 if (vp_config->rpa_strip_vlan_tag)
3747 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
3748 else
3749 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
3750 }
3751
3752 writeq(val64, &vp_reg->xmac_rpa_vcfg);
3753 val64 = readq(&vp_reg->rxmac_vcfg0);
3754
3755 if (vp_config->mtu !=
3756 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
3757 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
3758 if ((vp_config->mtu +
3759 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
3760 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
3761 vp_config->mtu +
3762 VXGE_HW_MAC_HEADER_MAX_SIZE);
3763 else
3764 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
3765 vpath->max_mtu);
3766 }
3767
3768 writeq(val64, &vp_reg->rxmac_vcfg0);
3769
3770 val64 = readq(&vp_reg->rxmac_vcfg1);
3771
3772 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
3773 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
3774
3775 if (hldev->config.rth_it_type ==
3776 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
3777 val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
3778 0x2) |
3779 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
3780 }
3781
3782 writeq(val64, &vp_reg->rxmac_vcfg1);
3783 }
3784 return status;
3785}
3786
3787/*
3788 * __vxge_hw_vpath_tim_configure
3789 * This routine configures the tim registers of virtual path using the config
3790 * passed
3791 */
42821a5b 3792static enum vxge_hw_status
40a3a915
RV		 3793__vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3794{
3795 u64 val64;
3796 enum vxge_hw_status status = VXGE_HW_OK;
3797 struct __vxge_hw_virtualpath *vpath;
3798 struct vxge_hw_vpath_reg __iomem *vp_reg;
3799 struct vxge_hw_vp_config *config;
3800
3801 vpath = &hldev->virtual_paths[vp_id];
3802 vp_reg = vpath->vp_reg;
3803 config = vpath->vp_config;
3804
3805 writeq((u64)0, &vp_reg->tim_dest_addr);
3806 writeq((u64)0, &vp_reg->tim_vpath_map);
3807 writeq((u64)0, &vp_reg->tim_bitmap);
3808 writeq((u64)0, &vp_reg->tim_remap);
3809
3810 if (config->ring.enable == VXGE_HW_RING_ENABLE)
3811 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
3812 (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
3813 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
3814
3815 val64 = readq(&vp_reg->tim_pci_cfg);
3816 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
3817 writeq(val64, &vp_reg->tim_pci_cfg);
3818
3819 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3820
3821 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3822
3823 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3824 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3825 0x3ffffff);
3826 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3827 config->tti.btimer_val);
3828 }
3829
3830 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
3831
3832 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
3833 if (config->tti.timer_ac_en)
3834 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3835 else
3836 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3837 }
3838
3839 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
3840 if (config->tti.timer_ci_en)
3841 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3842 else
3843 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3844 }
3845
3846 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
3847 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
3848 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
3849 config->tti.urange_a);
3850 }
3851
3852 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
3853 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
3854 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
3855 config->tti.urange_b);
3856 }
3857
3858 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
3859 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
3860 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
3861 config->tti.urange_c);
3862 }
3863
3864 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3865 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3866
3867 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
3868 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
3869 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
3870 config->tti.uec_a);
3871 }
3872
3873 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
3874 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
3875 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
3876 config->tti.uec_b);
3877 }
3878
3879 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
3880 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
3881 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
3882 config->tti.uec_c);
3883 }
3884
3885 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
3886 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
3887 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
3888 config->tti.uec_d);
3889 }
3890
3891 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3892 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3893
3894 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
3895 if (config->tti.timer_ri_en)
3896 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3897 else
3898 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3899 }
3900
3901 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3902 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3903 0x3ffffff);
3904 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3905 config->tti.rtimer_val);
3906 }
3907
3908 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
3909 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
3910 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
3911 config->tti.util_sel);
3912 }
3913
3914 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3915 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3916 0x3ffffff);
3917 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3918 config->tti.ltimer_val);
3919 }
3920
3921 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3922 }
3923
3924 if (config->ring.enable == VXGE_HW_RING_ENABLE) {
3925
3926 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3927
3928 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3929 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3930 0x3ffffff);
3931 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3932 config->rti.btimer_val);
3933 }
3934
3935 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
3936
3937 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
3938 if (config->rti.timer_ac_en)
3939 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3940 else
3941 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3942 }
3943
3944 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
3945 if (config->rti.timer_ci_en)
3946 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3947 else
3948 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3949 }
3950
3951 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
3952 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
3953 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
3954 config->rti.urange_a);
3955 }
3956
3957 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
3958 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
3959 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
3960 config->rti.urange_b);
3961 }
3962
3963 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
3964 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
3965 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
3966 config->rti.urange_c);
3967 }
3968
3969 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3970 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3971
3972 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
3973 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
3974 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
3975 config->rti.uec_a);
3976 }
3977
3978 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
3979 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
3980 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
3981 config->rti.uec_b);
3982 }
3983
3984 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
3985 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
3986 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
3987 config->rti.uec_c);
3988 }
3989
3990 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
3991 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
3992 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
3993 config->rti.uec_d);
3994 }
3995
3996 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3997 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
3998
3999 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
4000 if (config->rti.timer_ri_en)
4001 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4002 else
4003 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
4004 }
4005
4006 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4007 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4008 0x3ffffff);
4009 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
4010 config->rti.rtimer_val);
4011 }
4012
4013 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
4014 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
4015 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
4016 config->rti.util_sel);
4017 }
4018
4019 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
4020 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4021 0x3ffffff);
4022 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
4023 config->rti.ltimer_val);
4024 }
4025
4026 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
4027 }
4028
4029 val64 = 0;
4030 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4031 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4032 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
4033 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4034 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4035 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
4036
4037 return status;
4038}
4039
eb5f10c2
SH		 4040void
4041vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
4042{
4043 struct __vxge_hw_virtualpath *vpath;
4044 struct vxge_hw_vpath_reg __iomem *vp_reg;
4045 struct vxge_hw_vp_config *config;
4046 u64 val64;
4047
4048 vpath = &hldev->virtual_paths[vp_id];
4049 vp_reg = vpath->vp_reg;
4050 config = vpath->vp_config;
4051
4052 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4053 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4054
4055 if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
4056 config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
4057 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
4058 writeq(val64,
4059 &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
4060 }
4061 }
eb5f10c2 4062}
40a3a915
RV		 4063/*
4064 * __vxge_hw_vpath_initialize
4065 * This routine is the final phase of init which initializes the
4066 * registers of the vpath using the configuration passed.
4067 */
42821a5b 4068static enum vxge_hw_status
40a3a915
RV		 4069__vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
4070{
4071 u64 val64;
4072 u32 val32;
4073 enum vxge_hw_status status = VXGE_HW_OK;
4074 struct __vxge_hw_virtualpath *vpath;
4075 struct vxge_hw_vpath_reg __iomem *vp_reg;
4076
4077 vpath = &hldev->virtual_paths[vp_id];
4078
4079 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4080 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4081 goto exit;
4082 }
4083 vp_reg = vpath->vp_reg;
4084
4085 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
4086
4087 if (status != VXGE_HW_OK)
4088 goto exit;
4089
4090 status = __vxge_hw_vpath_mac_configure(hldev, vp_id);
4091
4092 if (status != VXGE_HW_OK)
4093 goto exit;
4094
4095 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
4096
4097 if (status != VXGE_HW_OK)
4098 goto exit;
4099
4100 status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
4101
4102 if (status != VXGE_HW_OK)
4103 goto exit;
4104
40a3a915
RV		 4105 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
4106
4107 /* Get MRRS value from device control */
4108 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
4109
4110 if (status == VXGE_HW_OK) {
4111 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
4112 val64 &=
4113 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
4114 val64 |=
4115 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
4116
4117 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
4118 }
4119
4120 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
4121 val64 |=
4122 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
4123 VXGE_HW_MAX_PAYLOAD_SIZE_512);
4124
4125 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
4126 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
4127
4128exit:
4129 return status;
4130}
4131
4132/*
4133 * __vxge_hw_vp_initialize - Initialize Virtual Path structure
4134 * This routine is the initial phase of init which resets the vpath and
4135 * initializes the software support structures.
4136 */
42821a5b 4137static enum vxge_hw_status
40a3a915
RV		 4138__vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
4139 struct vxge_hw_vp_config *config)
4140{
4141 struct __vxge_hw_virtualpath *vpath;
4142 enum vxge_hw_status status = VXGE_HW_OK;
4143
4144 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
4145 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
4146 goto exit;
4147 }
4148
4149 vpath = &hldev->virtual_paths[vp_id];
4150
8424e00d 4151 spin_lock_init(&hldev->virtual_paths[vp_id].lock);
40a3a915
RV		 4152 vpath->vp_id = vp_id;
4153 vpath->vp_open = VXGE_HW_VP_OPEN;
4154 vpath->hldev = hldev;
4155 vpath->vp_config = config;
4156 vpath->vp_reg = hldev->vpath_reg[vp_id];
4157 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4158
4159 __vxge_hw_vpath_reset(hldev, vp_id);
4160
4161 status = __vxge_hw_vpath_reset_check(vpath);
40a3a915
RV		 4162 if (status != VXGE_HW_OK) {
4163 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4164 goto exit;
4165 }
4166
4167 status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
40a3a915
RV		 4168 if (status != VXGE_HW_OK) {
4169 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4170 goto exit;
4171 }
4172
4173 INIT_LIST_HEAD(&vpath->vpath_handles);
4174
4175 vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4176
4177 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4178 hldev->tim_int_mask1, vp_id);
4179
4180 status = __vxge_hw_vpath_initialize(hldev, vp_id);
40a3a915
RV		 4181 if (status != VXGE_HW_OK)
4182 __vxge_hw_vp_terminate(hldev, vp_id);
4183exit:
4184 return status;
4185}
4186
4187/*
4188 * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4189 * This routine closes all channels it opened and freeup memory
4190 */
42821a5b 4191static void
40a3a915
RV		 4192__vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4193{
4194 struct __vxge_hw_virtualpath *vpath;
4195
4196 vpath = &hldev->virtual_paths[vp_id];
4197
4198 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4199 goto exit;
4200
4201 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4202 vpath->hldev->tim_int_mask1, vpath->vp_id);
4203 hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4204
4205 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4206exit:
4207 return;
4208}
4209
4210/*
4211 * vxge_hw_vpath_mtu_set - Set MTU.
4212 * Set new MTU value. Example, to use jumbo frames:
4213 * vxge_hw_vpath_mtu_set(my_device, 9600);
4214 */
4215enum vxge_hw_status
4216vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4217{
4218 u64 val64;
4219 enum vxge_hw_status status = VXGE_HW_OK;
4220 struct __vxge_hw_virtualpath *vpath;
4221
4222 if (vp == NULL) {
4223 status = VXGE_HW_ERR_INVALID_HANDLE;
4224 goto exit;
4225 }
4226 vpath = vp->vpath;
4227
4228 new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4229
4230 if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4231 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4232
4233 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4234
4235 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4236 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4237
4238 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4239
4240 vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4241
4242exit:
4243 return status;
4244}
4245
4246/*
4247 * vxge_hw_vpath_open - Open a virtual path on a given adapter
4248 * This function is used to open access to virtual path of an
4249 * adapter for offload, GRO operations. This function returns
4250 * synchronously.
4251 */
4252enum vxge_hw_status
4253vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4254 struct vxge_hw_vpath_attr *attr,
4255 struct __vxge_hw_vpath_handle **vpath_handle)
4256{
4257 struct __vxge_hw_virtualpath *vpath;
4258 struct __vxge_hw_vpath_handle *vp;
4259 enum vxge_hw_status status;
4260
4261 vpath = &hldev->virtual_paths[attr->vp_id];
4262
4263 if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4264 status = VXGE_HW_ERR_INVALID_STATE;
4265 goto vpath_open_exit1;
4266 }
4267
4268 status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4269 &hldev->config.vp_config[attr->vp_id]);
4270
4271 if (status != VXGE_HW_OK)
4272 goto vpath_open_exit1;
4273
4274 vp = (struct __vxge_hw_vpath_handle *)
4275 vmalloc(sizeof(struct __vxge_hw_vpath_handle));
4276 if (vp == NULL) {
4277 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4278 goto vpath_open_exit2;
4279 }
4280
4281 memset(vp, 0, sizeof(struct __vxge_hw_vpath_handle));
4282
4283 vp->vpath = vpath;
4284
4285 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4286 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4287 if (status != VXGE_HW_OK)
4288 goto vpath_open_exit6;
4289 }
4290
4291 if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4292 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4293 if (status != VXGE_HW_OK)
4294 goto vpath_open_exit7;
4295
4296 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4297 }
4298
4299 vpath->fifoh->tx_intr_num =
4300 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4301 VXGE_HW_VPATH_INTR_TX;
4302
4303 vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4304 VXGE_HW_BLOCK_SIZE);
4305
4306 if (vpath->stats_block == NULL) {
4307 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4308 goto vpath_open_exit8;
4309 }
4310
4311 vpath->hw_stats = (struct vxge_hw_vpath_stats_hw_info *)vpath->
4312 stats_block->memblock;
4313 memset(vpath->hw_stats, 0,
4314 sizeof(struct vxge_hw_vpath_stats_hw_info));
4315
4316 hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4317 vpath->hw_stats;
4318
4319 vpath->hw_stats_sav =
4320 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4321 memset(vpath->hw_stats_sav, 0,
4322 sizeof(struct vxge_hw_vpath_stats_hw_info));
4323
4324 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4325
4326 status = vxge_hw_vpath_stats_enable(vp);
4327 if (status != VXGE_HW_OK)
4328 goto vpath_open_exit8;
4329
4330 list_add(&vp->item, &vpath->vpath_handles);
4331
4332 hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4333
4334 *vpath_handle = vp;
4335
4336 attr->fifo_attr.userdata = vpath->fifoh;
4337 attr->ring_attr.userdata = vpath->ringh;
4338
4339 return VXGE_HW_OK;
4340
4341vpath_open_exit8:
4342 if (vpath->ringh != NULL)
4343 __vxge_hw_ring_delete(vp);
4344vpath_open_exit7:
4345 if (vpath->fifoh != NULL)
4346 __vxge_hw_fifo_delete(vp);
4347vpath_open_exit6:
4348 vfree(vp);
4349vpath_open_exit2:
4350 __vxge_hw_vp_terminate(hldev, attr->vp_id);
4351vpath_open_exit1:
4352
4353 return status;
4354}
4355
4356/**
4357 * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4358 * (vpath) open
4359 * @vp: Handle got from previous vpath open
4360 *
4361 * This function is used to close access to virtual path opened
4362 * earlier.
4363 */
4364void
4365vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4366{
e7935c96
JM		 4367 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4368 struct __vxge_hw_ring *ring = vpath->ringh;
4369 struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
40a3a915 4370 u64 new_count, val64, val164;
40a3a915 4371
e7935c96
JM		 4372 if (vdev->titan1) {
4373 new_count = readq(&vpath->vp_reg->rxdmem_size);
4374 new_count &= 0x1fff;
4375 } else
4376 new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
40a3a915 4377
e7935c96 4378 val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
40a3a915
RV		 4379
4380 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4381 &vpath->vp_reg->prc_rxd_doorbell);
4382 readl(&vpath->vp_reg->prc_rxd_doorbell);
4383
4384 val164 /= 2;
4385 val64 = readq(&vpath->vp_reg->prc_cfg6);
4386 val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4387 val64 &= 0x1ff;
4388
4389 /*
4390 * Each RxD is of 4 qwords
4391 */
4392 new_count -= (val64 + 1);
4393 val64 = min(val164, new_count) / 4;
4394
4395 ring->rxds_limit = min(ring->rxds_limit, val64);
4396 if (ring->rxds_limit < 4)
4397 ring->rxds_limit = 4;
4398}
4399
4400/*
4401 * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4402 * This function is used to close access to virtual path opened
4403 * earlier.
4404 */
4405enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4406{
4407 struct __vxge_hw_virtualpath *vpath = NULL;
4408 struct __vxge_hw_device *devh = NULL;
4409 u32 vp_id = vp->vpath->vp_id;
4410 u32 is_empty = TRUE;
4411 enum vxge_hw_status status = VXGE_HW_OK;
4412
4413 vpath = vp->vpath;
4414 devh = vpath->hldev;
4415
4416 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4417 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4418 goto vpath_close_exit;
4419 }
4420
4421 list_del(&vp->item);
4422
4423 if (!list_empty(&vpath->vpath_handles)) {
4424 list_add(&vp->item, &vpath->vpath_handles);
4425 is_empty = FALSE;
4426 }
4427
4428 if (!is_empty) {
4429 status = VXGE_HW_FAIL;
4430 goto vpath_close_exit;
4431 }
4432
4433 devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
4434
4435 if (vpath->ringh != NULL)
4436 __vxge_hw_ring_delete(vp);
4437
4438 if (vpath->fifoh != NULL)
4439 __vxge_hw_fifo_delete(vp);
4440
4441 if (vpath->stats_block != NULL)
4442 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
4443
4444 vfree(vp);
4445
4446 __vxge_hw_vp_terminate(devh, vp_id);
4447
8424e00d 4448 spin_lock(&vpath->lock);
40a3a915 4449 vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
8424e00d 4450 spin_unlock(&vpath->lock);
40a3a915
RV		 4451
4452vpath_close_exit:
4453 return status;
4454}
4455
4456/*
4457 * vxge_hw_vpath_reset - Resets vpath
4458 * This function is used to request a reset of vpath
4459 */
4460enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
4461{
4462 enum vxge_hw_status status;
4463 u32 vp_id;
4464 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4465
4466 vp_id = vpath->vp_id;
4467
4468 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4469 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4470 goto exit;
4471 }
4472
4473 status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
4474 if (status == VXGE_HW_OK)
4475 vpath->sw_stats->soft_reset_cnt++;
4476exit:
4477 return status;
4478}
4479
4480/*
4481 * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
4482 * This function poll's for the vpath reset completion and re initializes
4483 * the vpath.
4484 */
4485enum vxge_hw_status
4486vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
4487{
4488 struct __vxge_hw_virtualpath *vpath = NULL;
4489 enum vxge_hw_status status;
4490 struct __vxge_hw_device *hldev;
4491 u32 vp_id;
4492
4493 vp_id = vp->vpath->vp_id;
4494 vpath = vp->vpath;
4495 hldev = vpath->hldev;
4496
4497 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4498 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4499 goto exit;
4500 }
4501
4502 status = __vxge_hw_vpath_reset_check(vpath);
4503 if (status != VXGE_HW_OK)
4504 goto exit;
4505
4506 status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
4507 if (status != VXGE_HW_OK)
4508 goto exit;
4509
4510 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4511 if (status != VXGE_HW_OK)
4512 goto exit;
4513
4514 if (vpath->ringh != NULL)
4515 __vxge_hw_vpath_prc_configure(hldev, vp_id);
4516
4517 memset(vpath->hw_stats, 0,
4518 sizeof(struct vxge_hw_vpath_stats_hw_info));
4519
4520 memset(vpath->hw_stats_sav, 0,
4521 sizeof(struct vxge_hw_vpath_stats_hw_info));
4522
4523 writeq(vpath->stats_block->dma_addr,
4524 &vpath->vp_reg->stats_cfg);
4525
4526 status = vxge_hw_vpath_stats_enable(vp);
4527
4528exit:
4529 return status;
4530}
4531
4532/*
4533 * vxge_hw_vpath_enable - Enable vpath.
4534 * This routine clears the vpath reset thereby enabling a vpath
4535 * to start forwarding frames and generating interrupts.
4536 */
4537void
4538vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
4539{
4540 struct __vxge_hw_device *hldev;
4541 u64 val64;
4542
4543 hldev = vp->vpath->hldev;
4544
4545 val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
4546 1 << (16 - vp->vpath->vp_id));
4547
4548 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4549 &hldev->common_reg->cmn_rsthdlr_cfg1);
4550}
4551
4552/*
4553 * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4554 * Enable the DMA vpath statistics. The function is to be called to re-enable
4555 * the adapter to update stats into the host memory
4556 */
42821a5b 4557static enum vxge_hw_status
40a3a915
RV		 4558vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4559{
4560 enum vxge_hw_status status = VXGE_HW_OK;
4561 struct __vxge_hw_virtualpath *vpath;
4562
4563 vpath = vp->vpath;
4564
4565 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4566 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4567 goto exit;
4568 }
4569
4570 memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4571 sizeof(struct vxge_hw_vpath_stats_hw_info));
4572
4573 status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4574exit:
4575 return status;
4576}
4577
4578/*
4579 * __vxge_hw_vpath_stats_access - Get the statistics from the given location
4580 * and offset and perform an operation
4581 */
42821a5b 4582static enum vxge_hw_status
40a3a915
RV		 4583__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
4584 u32 operation, u32 offset, u64 *stat)
4585{
4586 u64 val64;
4587 enum vxge_hw_status status = VXGE_HW_OK;
4588 struct vxge_hw_vpath_reg __iomem *vp_reg;
4589
4590 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4591 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4592 goto vpath_stats_access_exit;
4593 }
4594
4595 vp_reg = vpath->vp_reg;
4596
4597 val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
4598 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
4599 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
4600
4601 status = __vxge_hw_pio_mem_write64(val64,
4602 &vp_reg->xmac_stats_access_cmd,
4603 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
4604 vpath->hldev->config.device_poll_millis);
4605
4606 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
4607 *stat = readq(&vp_reg->xmac_stats_access_data);
4608 else
4609 *stat = 0;
4610
4611vpath_stats_access_exit:
4612 return status;
4613}
4614
4615/*
4616 * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
4617 */
42821a5b 4618static enum vxge_hw_status
40a3a915
RV		 4619__vxge_hw_vpath_xmac_tx_stats_get(
4620 struct __vxge_hw_virtualpath *vpath,
4621 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
4622{
4623 u64 *val64;
4624 int i;
4625 u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
4626 enum vxge_hw_status status = VXGE_HW_OK;
4627
4628 val64 = (u64 *) vpath_tx_stats;
4629
4630 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4631 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4632 goto exit;
4633 }
4634
4635 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
4636 status = __vxge_hw_vpath_stats_access(vpath,
4637 VXGE_HW_STATS_OP_READ,
4638 offset, val64);
4639 if (status != VXGE_HW_OK)
4640 goto exit;
4641 offset++;
4642 val64++;
4643 }
4644exit:
4645 return status;
4646}
4647
4648/*
4649 * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
4650 */
42821a5b 4651static enum vxge_hw_status
40a3a915 4652__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
42821a5b 4653 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
40a3a915
RV		 4654{
4655 u64 *val64;
4656 enum vxge_hw_status status = VXGE_HW_OK;
4657 int i;
4658 u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
4659 val64 = (u64 *) vpath_rx_stats;
4660
4661 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4662 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4663 goto exit;
4664 }
4665 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
4666 status = __vxge_hw_vpath_stats_access(vpath,
4667 VXGE_HW_STATS_OP_READ,
4668 offset >> 3, val64);
4669 if (status != VXGE_HW_OK)
4670 goto exit;
4671
4672 offset += 8;
4673 val64++;
4674 }
4675exit:
4676 return status;
4677}
4678
4679/*
4680 * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
4681 */
42821a5b 4682static enum vxge_hw_status
4683__vxge_hw_vpath_stats_get(struct __vxge_hw_virtualpath *vpath,
4684 struct vxge_hw_vpath_stats_hw_info *hw_stats)
40a3a915
RV		 4685{
4686 u64 val64;
4687 enum vxge_hw_status status = VXGE_HW_OK;
4688 struct vxge_hw_vpath_reg __iomem *vp_reg;
4689
4690 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4691 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4692 goto exit;
4693 }
4694 vp_reg = vpath->vp_reg;
4695
4696 val64 = readq(&vp_reg->vpath_debug_stats0);
4697 hw_stats->ini_num_mwr_sent =
4698 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
4699
4700 val64 = readq(&vp_reg->vpath_debug_stats1);
4701 hw_stats->ini_num_mrd_sent =
4702 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
4703
4704 val64 = readq(&vp_reg->vpath_debug_stats2);
4705 hw_stats->ini_num_cpl_rcvd =
4706 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
4707
4708 val64 = readq(&vp_reg->vpath_debug_stats3);
4709 hw_stats->ini_num_mwr_byte_sent =
4710 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
4711
4712 val64 = readq(&vp_reg->vpath_debug_stats4);
4713 hw_stats->ini_num_cpl_byte_rcvd =
4714 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
4715
4716 val64 = readq(&vp_reg->vpath_debug_stats5);
4717 hw_stats->wrcrdtarb_xoff =
4718 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
4719
4720 val64 = readq(&vp_reg->vpath_debug_stats6);
4721 hw_stats->rdcrdtarb_xoff =
4722 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
4723
4724 val64 = readq(&vp_reg->vpath_genstats_count01);
4725 hw_stats->vpath_genstats_count0 =
4726 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
4727 val64);
4728
4729 val64 = readq(&vp_reg->vpath_genstats_count01);
4730 hw_stats->vpath_genstats_count1 =
4731 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
4732 val64);
4733
4734 val64 = readq(&vp_reg->vpath_genstats_count23);
4735 hw_stats->vpath_genstats_count2 =
4736 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
4737 val64);
4738
4739 val64 = readq(&vp_reg->vpath_genstats_count01);
4740 hw_stats->vpath_genstats_count3 =
4741 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
4742 val64);
4743
4744 val64 = readq(&vp_reg->vpath_genstats_count4);
4745 hw_stats->vpath_genstats_count4 =
4746 (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
4747 val64);
4748
4749 val64 = readq(&vp_reg->vpath_genstats_count5);
4750 hw_stats->vpath_genstats_count5 =
4751 (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
4752 val64);
4753
4754 status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
4755 if (status != VXGE_HW_OK)
4756 goto exit;
4757
4758 status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
4759 if (status != VXGE_HW_OK)
4760 goto exit;
4761
4762 VXGE_HW_VPATH_STATS_PIO_READ(
4763 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
4764
4765 hw_stats->prog_event_vnum0 =
4766 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
4767
4768 hw_stats->prog_event_vnum1 =
4769 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
4770
4771 VXGE_HW_VPATH_STATS_PIO_READ(
4772 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
4773
4774 hw_stats->prog_event_vnum2 =
4775 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
4776
4777 hw_stats->prog_event_vnum3 =
4778 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
4779
4780 val64 = readq(&vp_reg->rx_multi_cast_stats);
4781 hw_stats->rx_multi_cast_frame_discard =
4782 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
4783
4784 val64 = readq(&vp_reg->rx_frm_transferred);
4785 hw_stats->rx_frm_transferred =
4786 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
4787
4788 val64 = readq(&vp_reg->rxd_returned);
4789 hw_stats->rxd_returned =
4790 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
4791
4792 val64 = readq(&vp_reg->dbg_stats_rx_mpa);
4793 hw_stats->rx_mpa_len_fail_frms =
4794 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
4795 hw_stats->rx_mpa_mrk_fail_frms =
4796 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
4797 hw_stats->rx_mpa_crc_fail_frms =
4798 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
4799
4800 val64 = readq(&vp_reg->dbg_stats_rx_fau);
4801 hw_stats->rx_permitted_frms =
4802 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
4803 hw_stats->rx_vp_reset_discarded_frms =
4804 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
4805 hw_stats->rx_wol_frms =
4806 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
4807
4808 val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
4809 hw_stats->tx_vp_reset_discarded_frms =
4810 (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
4811 val64);
4812exit:
4813 return status;
4814}
4815
42821a5b 4816
4817static void vxge_os_dma_malloc_async(struct pci_dev *pdev, void *devh,
4818 unsigned long size)
4819{
4820 gfp_t flags;
4821 void *vaddr;
4822
4823 if (in_interrupt())
4824 flags = GFP_ATOMIC | GFP_DMA;
4825 else
4826 flags = GFP_KERNEL | GFP_DMA;
4827
4828 vaddr = kmalloc((size), flags);
4829
4830 vxge_hw_blockpool_block_add(devh, vaddr, size, pdev, pdev);
4831}
4832
4833static void vxge_os_dma_free(struct pci_dev *pdev, const void *vaddr,
4834 struct pci_dev **p_dma_acch)
4835{
4836 unsigned long misaligned = *(unsigned long *)p_dma_acch;
4837 u8 *tmp = (u8 *)vaddr;
4838 tmp -= misaligned;
4839 kfree((void *)tmp);
4840}
4841
40a3a915
RV		 4842/*
4843 * __vxge_hw_blockpool_create - Create block pool
4844 */
4845
2c91308f 4846static enum vxge_hw_status
40a3a915
RV		 4847__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
4848 struct __vxge_hw_blockpool *blockpool,
4849 u32 pool_size,
4850 u32 pool_max)
4851{
4852 u32 i;
4853 struct __vxge_hw_blockpool_entry *entry = NULL;
4854 void *memblock;
4855 dma_addr_t dma_addr;
4856 struct pci_dev *dma_handle;
4857 struct pci_dev *acc_handle;
4858 enum vxge_hw_status status = VXGE_HW_OK;
4859
4860 if (blockpool == NULL) {
4861 status = VXGE_HW_FAIL;
4862 goto blockpool_create_exit;
4863 }
4864
4865 blockpool->hldev = hldev;
4866 blockpool->block_size = VXGE_HW_BLOCK_SIZE;
4867 blockpool->pool_size = 0;
4868 blockpool->pool_max = pool_max;
4869 blockpool->req_out = 0;
4870
4871 INIT_LIST_HEAD(&blockpool->free_block_list);
4872 INIT_LIST_HEAD(&blockpool->free_entry_list);
4873
4874 for (i = 0; i < pool_size + pool_max; i++) {
4875 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
4876 GFP_KERNEL);
4877 if (entry == NULL) {
4878 __vxge_hw_blockpool_destroy(blockpool);
4879 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4880 goto blockpool_create_exit;
4881 }
4882 list_add(&entry->item, &blockpool->free_entry_list);
4883 }
4884
4885 for (i = 0; i < pool_size; i++) {
4886
4887 memblock = vxge_os_dma_malloc(
4888 hldev->pdev,
4889 VXGE_HW_BLOCK_SIZE,
4890 &dma_handle,
4891 &acc_handle);
4892
4893 if (memblock == NULL) {
4894 __vxge_hw_blockpool_destroy(blockpool);
4895 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4896 goto blockpool_create_exit;
4897 }
4898
4899 dma_addr = pci_map_single(hldev->pdev, memblock,
4900 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
4901
4902 if (unlikely(pci_dma_mapping_error(hldev->pdev,
4903 dma_addr))) {
4904
4905 vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
4906 __vxge_hw_blockpool_destroy(blockpool);
4907 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4908 goto blockpool_create_exit;
4909 }
4910
4911 if (!list_empty(&blockpool->free_entry_list))
4912 entry = (struct __vxge_hw_blockpool_entry *)
4913 list_first_entry(&blockpool->free_entry_list,
4914 struct __vxge_hw_blockpool_entry,
4915 item);
4916
4917 if (entry == NULL)
4918 entry =
4919 kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
4920 GFP_KERNEL);
4921 if (entry != NULL) {
4922 list_del(&entry->item);
4923 entry->length = VXGE_HW_BLOCK_SIZE;
4924 entry->memblock = memblock;
4925 entry->dma_addr = dma_addr;
4926 entry->acc_handle = acc_handle;
4927 entry->dma_handle = dma_handle;
4928 list_add(&entry->item,
4929 &blockpool->free_block_list);
4930 blockpool->pool_size++;
4931 } else {
4932 __vxge_hw_blockpool_destroy(blockpool);
4933 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4934 goto blockpool_create_exit;
4935 }
4936 }
4937
4938blockpool_create_exit:
4939 return status;
4940}
4941
4942/*
4943 * __vxge_hw_blockpool_destroy - Deallocates the block pool
4944 */
4945
2c91308f 4946static void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
40a3a915
RV		 4947{
4948
4949 struct __vxge_hw_device *hldev;
4950 struct list_head *p, *n;
4951 u16 ret;
4952
4953 if (blockpool == NULL) {
4954 ret = 1;
4955 goto exit;
4956 }
4957
4958 hldev = blockpool->hldev;
4959
4960 list_for_each_safe(p, n, &blockpool->free_block_list) {
4961
4962 pci_unmap_single(hldev->pdev,
4963 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
4964 ((struct __vxge_hw_blockpool_entry *)p)->length,
4965 PCI_DMA_BIDIRECTIONAL);
4966
4967 vxge_os_dma_free(hldev->pdev,
4968 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
4969 &((struct __vxge_hw_blockpool_entry *) p)->acc_handle);
4970
4971 list_del(
4972 &((struct __vxge_hw_blockpool_entry *)p)->item);
4973 kfree(p);
4974 blockpool->pool_size--;
4975 }
4976
4977 list_for_each_safe(p, n, &blockpool->free_entry_list) {
4978 list_del(
4979 &((struct __vxge_hw_blockpool_entry *)p)->item);
4980 kfree((void *)p);
4981 }
4982 ret = 0;
4983exit:
4984 return;
4985}
4986
4987/*
4988 * __vxge_hw_blockpool_blocks_add - Request additional blocks
4989 */
4990static
4991void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
4992{
4993 u32 nreq = 0, i;
4994
4995 if ((blockpool->pool_size + blockpool->req_out) <
4996 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
4997 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
4998 blockpool->req_out += nreq;
4999 }
5000
5001 for (i = 0; i < nreq; i++)
5002 vxge_os_dma_malloc_async(
5003 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
5004 blockpool->hldev, VXGE_HW_BLOCK_SIZE);
5005}
5006
5007/*
5008 * __vxge_hw_blockpool_blocks_remove - Free additional blocks
5009 */
5010static
5011void __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
5012{
5013 struct list_head *p, *n;
5014
5015 list_for_each_safe(p, n, &blockpool->free_block_list) {
5016
5017 if (blockpool->pool_size < blockpool->pool_max)
5018 break;
5019
5020 pci_unmap_single(
5021 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
5022 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
5023 ((struct __vxge_hw_blockpool_entry *)p)->length,
5024 PCI_DMA_BIDIRECTIONAL);
5025
5026 vxge_os_dma_free(
5027 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
5028 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
5029 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
5030
5031 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
5032
5033 list_add(p, &blockpool->free_entry_list);
5034
5035 blockpool->pool_size--;
5036
5037 }
5038}
5039
5040/*
5041 * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
5042 * Adds a block to block pool
5043 */
42821a5b 5044static void vxge_hw_blockpool_block_add(struct __vxge_hw_device *devh,
5045 void *block_addr,
5046 u32 length,
5047 struct pci_dev *dma_h,
5048 struct pci_dev *acc_handle)
40a3a915
RV		 5049{
5050 struct __vxge_hw_blockpool *blockpool;
5051 struct __vxge_hw_blockpool_entry *entry = NULL;
5052 dma_addr_t dma_addr;
5053 enum vxge_hw_status status = VXGE_HW_OK;
5054 u32 req_out;
5055
5056 blockpool = &devh->block_pool;
5057
5058 if (block_addr == NULL) {
5059 blockpool->req_out--;
5060 status = VXGE_HW_FAIL;
5061 goto exit;
5062 }
5063
5064 dma_addr = pci_map_single(devh->pdev, block_addr, length,
5065 PCI_DMA_BIDIRECTIONAL);
5066
5067 if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
5068
5069 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
5070 blockpool->req_out--;
5071 status = VXGE_HW_FAIL;
5072 goto exit;
5073 }
5074
5075
5076 if (!list_empty(&blockpool->free_entry_list))
5077 entry = (struct __vxge_hw_blockpool_entry *)
5078 list_first_entry(&blockpool->free_entry_list,
5079 struct __vxge_hw_blockpool_entry,
5080 item);
5081
5082 if (entry == NULL)
5083 entry = (struct __vxge_hw_blockpool_entry *)
5084 vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
5085 else
5086 list_del(&entry->item);
5087
5088 if (entry != NULL) {
5089 entry->length = length;
5090 entry->memblock = block_addr;
5091 entry->dma_addr = dma_addr;
5092 entry->acc_handle = acc_handle;
5093 entry->dma_handle = dma_h;
5094 list_add(&entry->item, &blockpool->free_block_list);
5095 blockpool->pool_size++;
5096 status = VXGE_HW_OK;
5097 } else
5098 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5099
5100 blockpool->req_out--;
5101
5102 req_out = blockpool->req_out;
5103exit:
5104 return;
5105}
5106
5107/*
5108 * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
5109 * Allocates a block of memory of given size, either from block pool
5110 * or by calling vxge_os_dma_malloc()
5111 */
2c91308f 5112static void *
40a3a915
RV		 5113__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
5114 struct vxge_hw_mempool_dma *dma_object)
5115{
5116 struct __vxge_hw_blockpool_entry *entry = NULL;
5117 struct __vxge_hw_blockpool *blockpool;
5118 void *memblock = NULL;
5119 enum vxge_hw_status status = VXGE_HW_OK;
5120
5121 blockpool = &devh->block_pool;
5122
5123 if (size != blockpool->block_size) {
5124
5125 memblock = vxge_os_dma_malloc(devh->pdev, size,
5126 &dma_object->handle,
5127 &dma_object->acc_handle);
5128
5129 if (memblock == NULL) {
5130 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5131 goto exit;
5132 }
5133
5134 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
5135 PCI_DMA_BIDIRECTIONAL);
5136
5137 if (unlikely(pci_dma_mapping_error(devh->pdev,
5138 dma_object->addr))) {
5139 vxge_os_dma_free(devh->pdev, memblock,
5140 &dma_object->acc_handle);
5141 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5142 goto exit;
5143 }
5144
5145 } else {
5146
5147 if (!list_empty(&blockpool->free_block_list))
5148 entry = (struct __vxge_hw_blockpool_entry *)
5149 list_first_entry(&blockpool->free_block_list,
5150 struct __vxge_hw_blockpool_entry,
5151 item);
5152
5153 if (entry != NULL) {
5154 list_del(&entry->item);
5155 dma_object->addr = entry->dma_addr;
5156 dma_object->handle = entry->dma_handle;
5157 dma_object->acc_handle = entry->acc_handle;
5158 memblock = entry->memblock;
5159
5160 list_add(&entry->item,
5161 &blockpool->free_entry_list);
5162 blockpool->pool_size--;
5163 }
5164
5165 if (memblock != NULL)
5166 __vxge_hw_blockpool_blocks_add(blockpool);
5167 }
5168exit:
5169 return memblock;
5170}
5171
5172/*
5173 * __vxge_hw_blockpool_free - Frees the memory allcoated with
5174 __vxge_hw_blockpool_malloc
5175 */
2c91308f 5176static void
40a3a915
RV		 5177__vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
5178 void *memblock, u32 size,
5179 struct vxge_hw_mempool_dma *dma_object)
5180{
5181 struct __vxge_hw_blockpool_entry *entry = NULL;
5182 struct __vxge_hw_blockpool *blockpool;
5183 enum vxge_hw_status status = VXGE_HW_OK;
5184
5185 blockpool = &devh->block_pool;
5186
5187 if (size != blockpool->block_size) {
5188 pci_unmap_single(devh->pdev, dma_object->addr, size,
5189 PCI_DMA_BIDIRECTIONAL);
5190 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
5191 } else {
5192
5193 if (!list_empty(&blockpool->free_entry_list))
5194 entry = (struct __vxge_hw_blockpool_entry *)
5195 list_first_entry(&blockpool->free_entry_list,
5196 struct __vxge_hw_blockpool_entry,
5197 item);
5198
5199 if (entry == NULL)
5200 entry = (struct __vxge_hw_blockpool_entry *)
5201 vmalloc(sizeof(
5202 struct __vxge_hw_blockpool_entry));
5203 else
5204 list_del(&entry->item);
5205
5206 if (entry != NULL) {
5207 entry->length = size;
5208 entry->memblock = memblock;
5209 entry->dma_addr = dma_object->addr;
5210 entry->acc_handle = dma_object->acc_handle;
5211 entry->dma_handle = dma_object->handle;
5212 list_add(&entry->item,
5213 &blockpool->free_block_list);
5214 blockpool->pool_size++;
5215 status = VXGE_HW_OK;
5216 } else
5217 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5218
5219 if (status == VXGE_HW_OK)
5220 __vxge_hw_blockpool_blocks_remove(blockpool);
5221 }
40a3a915
RV		 5222}
5223
5224/*
5225 * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
5226 * This function allocates a block from block pool or from the system
5227 */
2c91308f 5228static struct __vxge_hw_blockpool_entry *
40a3a915
RV		 5229__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
5230{
5231 struct __vxge_hw_blockpool_entry *entry = NULL;
5232 struct __vxge_hw_blockpool *blockpool;
5233
5234 blockpool = &devh->block_pool;
5235
5236 if (size == blockpool->block_size) {
5237
5238 if (!list_empty(&blockpool->free_block_list))
5239 entry = (struct __vxge_hw_blockpool_entry *)
5240 list_first_entry(&blockpool->free_block_list,
5241 struct __vxge_hw_blockpool_entry,
5242 item);
5243
5244 if (entry != NULL) {
5245 list_del(&entry->item);
5246 blockpool->pool_size--;
5247 }
5248 }
5249
5250 if (entry != NULL)
5251 __vxge_hw_blockpool_blocks_add(blockpool);
5252
5253 return entry;
5254}
5255
5256/*
5257 * __vxge_hw_blockpool_block_free - Frees a block from block pool
5258 * @devh: Hal device
5259 * @entry: Entry of block to be freed
5260 *
5261 * This function frees a block from block pool
5262 */
2c91308f 5263static void
40a3a915
RV		 5264__vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
5265 struct __vxge_hw_blockpool_entry *entry)
5266{
5267 struct __vxge_hw_blockpool *blockpool;
5268
5269 blockpool = &devh->block_pool;
5270
5271 if (entry->length == blockpool->block_size) {
5272 list_add(&entry->item, &blockpool->free_block_list);
5273 blockpool->pool_size++;
5274 }
5275
5276 __vxge_hw_blockpool_blocks_remove(blockpool);
40a3a915 5277}
Clone of davem's net-next-2.6 tree