git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. | |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * This software may be redistributed and/or modified under | |
| 6 | * the terms of the GNU General Public License as published by the Free | |
| 7 | * Software Foundation; either version 2 of the License, or | |
| 8 | * any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, but | |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 12 | * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 13 | * for more details. | |
| 14 | * | |
| 15 | * File: via-velocity.h | |
| 16 | * | |
| 17 | * Purpose: Header file to define driver's private structures. | |
| 18 | * | |
| 19 | * Author: Chuang Liang-Shing, AJ Jiang | |
| 20 | * | |
| 21 | * Date: Jan 24, 2003 | |
| 22 | */ | |
| 23 | ||
| 24 | ||
| 25 | #ifndef VELOCITY_H | |
| 26 | #define VELOCITY_H | |
| 27 | ||
| 28 | #define VELOCITY_TX_CSUM_SUPPORT | |
| 29 | ||
| 30 | #define VELOCITY_NAME "via-velocity" | |
| 31 | #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver" | |
| 1bda8aa8 | 32 | #define VELOCITY_VERSION "1.15" |
| 1da177e4 | 33 | |
| cabb7667 | 34 | #define VELOCITY_IO_SIZE 256 |
| dfff7144 | 35 | #define VELOCITY_NAPI_WEIGHT 64 |
| cabb7667 | 36 | |
| 1da177e4 LT |
37 | #define PKT_BUF_SZ 1540 |
| 38 | ||
| 39 | #define MAX_UNITS 8 | |
| 40 | #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1} | |
| 41 | ||
| 42 | #define REV_ID_VT6110 (0) | |
| 43 | ||
| 44 | #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0) | |
| 45 | #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0) | |
| 46 | #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0) | |
| 47 | ||
| 48 | #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x)) | |
| 49 | #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x)) | |
| 50 | #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x)) | |
| 51 | ||
| 52 | #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0) | |
| 53 | #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0) | |
| 54 | #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0) | |
| 55 | ||
| 56 | #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0) | |
| 57 | #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0) | |
| 58 | #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0) | |
| 59 | ||
| 60 | #define VAR_USED(p) do {(p)=(p);} while (0) | |
| 61 | ||
| 62 | /* | |
| 63 | * Purpose: Structures for MAX RX/TX descriptors. | |
| 64 | */ | |
| 65 | ||
| 66 | ||
| 67 | #define B_OWNED_BY_CHIP 1 | |
| 68 | #define B_OWNED_BY_HOST 0 | |
| 69 | ||
| 70 | /* | |
| 71 | * Bits in the RSR0 register | |
| 72 | */ | |
| 73 | ||
| 4a51c0d0 AV |
74 | #define RSR_DETAG cpu_to_le16(0x0080) |
| 75 | #define RSR_SNTAG cpu_to_le16(0x0040) | |
| 76 | #define RSR_RXER cpu_to_le16(0x0020) | |
| 77 | #define RSR_RL cpu_to_le16(0x0010) | |
| 78 | #define RSR_CE cpu_to_le16(0x0008) | |
| 79 | #define RSR_FAE cpu_to_le16(0x0004) | |
| 80 | #define RSR_CRC cpu_to_le16(0x0002) | |
| 81 | #define RSR_VIDM cpu_to_le16(0x0001) | |
| 1da177e4 LT |
82 | |
| 83 | /* | |
| 84 | * Bits in the RSR1 register | |
| 85 | */ | |
| 86 | ||
| 4a51c0d0 AV |
87 | #define RSR_RXOK cpu_to_le16(0x8000) // rx OK |
| 88 | #define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match | |
| 89 | #define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet | |
| 90 | #define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet | |
| 91 | #define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet | |
| 92 | #define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator | |
| 93 | #define RSR_STP cpu_to_le16(0x0200) // start of packet | |
| 94 | #define RSR_EDP cpu_to_le16(0x0100) // end of packet | |
| 1da177e4 LT |
95 | |
| 96 | /* | |
| 97 | * Bits in the CSM register | |
| 98 | */ | |
| 99 | ||
| 5a6338db DJ |
100 | #define CSM_IPOK 0x40 //IP Checksum validation ok |
| 101 | #define CSM_TUPOK 0x20 //TCP/UDP Checksum validation ok | |
| 1da177e4 LT |
102 | #define CSM_FRAG 0x10 //Fragment IP datagram |
| 103 | #define CSM_IPKT 0x04 //Received an IP packet | |
| 104 | #define CSM_TCPKT 0x02 //Received a TCP packet | |
| 105 | #define CSM_UDPKT 0x01 //Received a UDP packet | |
| 106 | ||
| 107 | /* | |
| 108 | * Bits in the TSR0 register | |
| 109 | */ | |
| 110 | ||
| 4a51c0d0 AV |
111 | #define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision |
| 112 | #define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort | |
| 113 | #define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision | |
| 114 | #define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event | |
| 115 | #define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3] | |
| 116 | #define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2] | |
| 117 | #define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1] | |
| 118 | #define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0] | |
| 119 | #define TSR0_TERR cpu_to_le16(0x8000) // | |
| 120 | #define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode | |
| 121 | #define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode | |
| 122 | #define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down | |
| 123 | #define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case | |
| 124 | #define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost | |
| 125 | #define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat) | |
| 1da177e4 LT |
126 | |
| 127 | // | |
| 128 | // Bits in the TCR0 register | |
| 129 | // | |
| 130 | #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete | |
| 131 | #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme | |
| 132 | #define TCR0_VETAG 0x20 // enable VLAN tag | |
| 133 | #define TCR0_IPCK 0x10 // request IP checksum calculation. | |
| 134 | #define TCR0_UDPCK 0x08 // request UDP checksum calculation. | |
| 135 | #define TCR0_TCPCK 0x04 // request TCP checksum calculation. | |
| 136 | #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side | |
| 137 | #define TCR0_CRC 0x01 // disable CRC generation | |
| 138 | ||
| 139 | #define TCPLS_NORMAL 3 | |
| 140 | #define TCPLS_START 2 | |
| 141 | #define TCPLS_END 1 | |
| 142 | #define TCPLS_MED 0 | |
| 143 | ||
| 144 | ||
| 145 | // max transmit or receive buffer size | |
| 146 | #define CB_RX_BUF_SIZE 2048UL // max buffer size | |
| 147 | // NOTE: must be multiple of 4 | |
| 148 | ||
| 149 | #define CB_MAX_RD_NUM 512 // MAX # of RD | |
| 150 | #define CB_MAX_TD_NUM 256 // MAX # of TD | |
| 151 | ||
| 152 | #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119 | |
| 153 | #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119 | |
| 154 | ||
| 155 | #define CB_INIT_RD_NUM 128 // init # of RD, for setup default | |
| 156 | #define CB_INIT_TD_NUM 64 // init # of TD, for setup default | |
| 157 | ||
| 158 | // for 3119 | |
| 159 | #define CB_TD_RING_NUM 4 // # of TD rings. | |
| 160 | #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx) | |
| 161 | ||
| 162 | ||
| 163 | /* | |
| 164 | * If collisions excess 15 times , tx will abort, and | |
| 165 | * if tx fifo underflow, tx will fail | |
| 166 | * we should try to resend it | |
| 167 | */ | |
| 168 | ||
| 169 | #define CB_MAX_TX_ABORT_RETRY 3 | |
| 170 | ||
| 171 | /* | |
| 172 | * Receive descriptor | |
| 173 | */ | |
| 174 | ||
| 175 | struct rdesc0 { | |
| 4a51c0d0 AV |
176 | __le16 RSR; /* Receive status */ |
| 177 | __le16 len; /* bits 0--13; bit 15 - owner */ | |
| 1da177e4 LT |
178 | }; |
| 179 | ||
| 180 | struct rdesc1 { | |
| 4a51c0d0 | 181 | __le16 PQTAG; |
| 1da177e4 LT |
182 | u8 CSM; |
| 183 | u8 IPKT; | |
| 184 | }; | |
| 185 | ||
| 4a51c0d0 | 186 | enum { |
| 09640e63 | 187 | RX_INTEN = cpu_to_le16(0x8000) |
| 4a51c0d0 AV |
188 | }; |
| 189 | ||
| 1da177e4 LT |
190 | struct rx_desc { |
| 191 | struct rdesc0 rdesc0; | |
| 192 | struct rdesc1 rdesc1; | |
| 4a51c0d0 AV |
193 | __le32 pa_low; /* Low 32 bit PCI address */ |
| 194 | __le16 pa_high; /* Next 16 bit PCI address (48 total) */ | |
| 195 | __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */ | |
| ba2d3587 | 196 | } __packed; |
| 1da177e4 LT |
197 | |
| 198 | /* | |
| 199 | * Transmit descriptor | |
| 200 | */ | |
| 201 | ||
| 202 | struct tdesc0 { | |
| 4a51c0d0 AV |
203 | __le16 TSR; /* Transmit status register */ |
| 204 | __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */ | |
| 1da177e4 LT |
205 | }; |
| 206 | ||
| 1da177e4 | 207 | struct tdesc1 { |
| 4a51c0d0 | 208 | __le16 vlan; |
| 1da177e4 | 209 | u8 TCR; |
| 4a51c0d0 | 210 | u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */ |
| ba2d3587 | 211 | } __packed; |
| 1da177e4 | 212 | |
| 4a51c0d0 | 213 | enum { |
| 09640e63 | 214 | TD_QUEUE = cpu_to_le16(0x8000) |
| 4a51c0d0 AV |
215 | }; |
| 216 | ||
| 1da177e4 | 217 | struct td_buf { |
| 4a51c0d0 AV |
218 | __le32 pa_low; |
| 219 | __le16 pa_high; | |
| 220 | __le16 size; /* bits 0--13 - size, bit 15 - queue */ | |
| ba2d3587 | 221 | } __packed; |
| 1da177e4 LT |
222 | |
| 223 | struct tx_desc { | |
| 224 | struct tdesc0 tdesc0; | |
| 225 | struct tdesc1 tdesc1; | |
| 226 | struct td_buf td_buf[7]; | |
| 227 | }; | |
| 228 | ||
| 229 | struct velocity_rd_info { | |
| 230 | struct sk_buff *skb; | |
| 231 | dma_addr_t skb_dma; | |
| 232 | }; | |
| 233 | ||
| 1da177e4 LT |
234 | /* |
| 235 | * Used to track transmit side buffers. | |
| 236 | */ | |
| 237 | ||
| 238 | struct velocity_td_info { | |
| 239 | struct sk_buff *skb; | |
| 1da177e4 LT |
240 | int nskb_dma; |
| 241 | dma_addr_t skb_dma[7]; | |
| 1da177e4 LT |
242 | }; |
| 243 | ||
| 244 | enum velocity_owner { | |
| 245 | OWNED_BY_HOST = 0, | |
| 09640e63 | 246 | OWNED_BY_NIC = cpu_to_le16(0x8000) |
| 1da177e4 LT |
247 | }; |
| 248 | ||
| 249 | ||
| 250 | /* | |
| 251 | * MAC registers and macros. | |
| 252 | */ | |
| 253 | ||
| 254 | ||
| 255 | #define MCAM_SIZE 64 | |
| 256 | #define VCAM_SIZE 64 | |
| 257 | #define TX_QUEUE_NO 4 | |
| 258 | ||
| 259 | #define MAX_HW_MIB_COUNTER 32 | |
| 83055d46 | 260 | #define VELOCITY_MIN_MTU (64) |
| 1da177e4 LT |
261 | #define VELOCITY_MAX_MTU (9000) |
| 262 | ||
| 263 | /* | |
| 264 | * Registers in the MAC | |
| 265 | */ | |
| 266 | ||
| 267 | #define MAC_REG_PAR 0x00 // physical address | |
| 268 | #define MAC_REG_RCR 0x06 | |
| 269 | #define MAC_REG_TCR 0x07 | |
| 270 | #define MAC_REG_CR0_SET 0x08 | |
| 271 | #define MAC_REG_CR1_SET 0x09 | |
| 272 | #define MAC_REG_CR2_SET 0x0A | |
| 273 | #define MAC_REG_CR3_SET 0x0B | |
| 274 | #define MAC_REG_CR0_CLR 0x0C | |
| 275 | #define MAC_REG_CR1_CLR 0x0D | |
| 276 | #define MAC_REG_CR2_CLR 0x0E | |
| 277 | #define MAC_REG_CR3_CLR 0x0F | |
| 278 | #define MAC_REG_MAR 0x10 | |
| 279 | #define MAC_REG_CAM 0x10 | |
| 280 | #define MAC_REG_DEC_BASE_HI 0x18 | |
| 281 | #define MAC_REG_DBF_BASE_HI 0x1C | |
| 282 | #define MAC_REG_ISR_CTL 0x20 | |
| 283 | #define MAC_REG_ISR_HOTMR 0x20 | |
| 284 | #define MAC_REG_ISR_TSUPTHR 0x20 | |
| 285 | #define MAC_REG_ISR_RSUPTHR 0x20 | |
| 286 | #define MAC_REG_ISR_CTL1 0x21 | |
| 287 | #define MAC_REG_TXE_SR 0x22 | |
| 288 | #define MAC_REG_RXE_SR 0x23 | |
| 289 | #define MAC_REG_ISR 0x24 | |
| 290 | #define MAC_REG_ISR0 0x24 | |
| 291 | #define MAC_REG_ISR1 0x25 | |
| 292 | #define MAC_REG_ISR2 0x26 | |
| 293 | #define MAC_REG_ISR3 0x27 | |
| 294 | #define MAC_REG_IMR 0x28 | |
| 295 | #define MAC_REG_IMR0 0x28 | |
| 296 | #define MAC_REG_IMR1 0x29 | |
| 297 | #define MAC_REG_IMR2 0x2A | |
| 298 | #define MAC_REG_IMR3 0x2B | |
| 299 | #define MAC_REG_TDCSR_SET 0x30 | |
| 300 | #define MAC_REG_RDCSR_SET 0x32 | |
| 301 | #define MAC_REG_TDCSR_CLR 0x34 | |
| 302 | #define MAC_REG_RDCSR_CLR 0x36 | |
| 303 | #define MAC_REG_RDBASE_LO 0x38 | |
| 304 | #define MAC_REG_RDINDX 0x3C | |
| 305 | #define MAC_REG_TDBASE_LO 0x40 | |
| 306 | #define MAC_REG_RDCSIZE 0x50 | |
| 307 | #define MAC_REG_TDCSIZE 0x52 | |
| 308 | #define MAC_REG_TDINDX 0x54 | |
| 309 | #define MAC_REG_TDIDX0 0x54 | |
| 310 | #define MAC_REG_TDIDX1 0x56 | |
| 311 | #define MAC_REG_TDIDX2 0x58 | |
| 312 | #define MAC_REG_TDIDX3 0x5A | |
| 313 | #define MAC_REG_PAUSE_TIMER 0x5C | |
| 314 | #define MAC_REG_RBRDU 0x5E | |
| 315 | #define MAC_REG_FIFO_TEST0 0x60 | |
| 316 | #define MAC_REG_FIFO_TEST1 0x64 | |
| 317 | #define MAC_REG_CAMADDR 0x68 | |
| 318 | #define MAC_REG_CAMCR 0x69 | |
| 319 | #define MAC_REG_GFTEST 0x6A | |
| 320 | #define MAC_REG_FTSTCMD 0x6B | |
| 321 | #define MAC_REG_MIICFG 0x6C | |
| 322 | #define MAC_REG_MIISR 0x6D | |
| 323 | #define MAC_REG_PHYSR0 0x6E | |
| 324 | #define MAC_REG_PHYSR1 0x6F | |
| 325 | #define MAC_REG_MIICR 0x70 | |
| 326 | #define MAC_REG_MIIADR 0x71 | |
| 327 | #define MAC_REG_MIIDATA 0x72 | |
| 328 | #define MAC_REG_SOFT_TIMER0 0x74 | |
| 329 | #define MAC_REG_SOFT_TIMER1 0x76 | |
| 330 | #define MAC_REG_CFGA 0x78 | |
| 331 | #define MAC_REG_CFGB 0x79 | |
| 332 | #define MAC_REG_CFGC 0x7A | |
| 333 | #define MAC_REG_CFGD 0x7B | |
| 334 | #define MAC_REG_DCFG0 0x7C | |
| 335 | #define MAC_REG_DCFG1 0x7D | |
| 336 | #define MAC_REG_MCFG0 0x7E | |
| 337 | #define MAC_REG_MCFG1 0x7F | |
| 338 | ||
| 339 | #define MAC_REG_TBIST 0x80 | |
| 340 | #define MAC_REG_RBIST 0x81 | |
| 341 | #define MAC_REG_PMCC 0x82 | |
| 342 | #define MAC_REG_STICKHW 0x83 | |
| 343 | #define MAC_REG_MIBCR 0x84 | |
| 344 | #define MAC_REG_EERSV 0x85 | |
| 345 | #define MAC_REG_REVID 0x86 | |
| 346 | #define MAC_REG_MIBREAD 0x88 | |
| 347 | #define MAC_REG_BPMA 0x8C | |
| 348 | #define MAC_REG_EEWR_DATA 0x8C | |
| 349 | #define MAC_REG_BPMD_WR 0x8F | |
| 350 | #define MAC_REG_BPCMD 0x90 | |
| 351 | #define MAC_REG_BPMD_RD 0x91 | |
| 352 | #define MAC_REG_EECHKSUM 0x92 | |
| 353 | #define MAC_REG_EECSR 0x93 | |
| 354 | #define MAC_REG_EERD_DATA 0x94 | |
| 355 | #define MAC_REG_EADDR 0x96 | |
| 356 | #define MAC_REG_EMBCMD 0x97 | |
| 357 | #define MAC_REG_JMPSR0 0x98 | |
| 358 | #define MAC_REG_JMPSR1 0x99 | |
| 359 | #define MAC_REG_JMPSR2 0x9A | |
| 360 | #define MAC_REG_JMPSR3 0x9B | |
| 361 | #define MAC_REG_CHIPGSR 0x9C | |
| 362 | #define MAC_REG_TESTCFG 0x9D | |
| 363 | #define MAC_REG_DEBUG 0x9E | |
| 364 | #define MAC_REG_CHIPGCR 0x9F | |
| 365 | #define MAC_REG_WOLCR0_SET 0xA0 | |
| 366 | #define MAC_REG_WOLCR1_SET 0xA1 | |
| 367 | #define MAC_REG_PWCFG_SET 0xA2 | |
| 368 | #define MAC_REG_WOLCFG_SET 0xA3 | |
| 369 | #define MAC_REG_WOLCR0_CLR 0xA4 | |
| 370 | #define MAC_REG_WOLCR1_CLR 0xA5 | |
| 371 | #define MAC_REG_PWCFG_CLR 0xA6 | |
| 372 | #define MAC_REG_WOLCFG_CLR 0xA7 | |
| 373 | #define MAC_REG_WOLSR0_SET 0xA8 | |
| 374 | #define MAC_REG_WOLSR1_SET 0xA9 | |
| 375 | #define MAC_REG_WOLSR0_CLR 0xAC | |
| 376 | #define MAC_REG_WOLSR1_CLR 0xAD | |
| 377 | #define MAC_REG_PATRN_CRC0 0xB0 | |
| 378 | #define MAC_REG_PATRN_CRC1 0xB2 | |
| 379 | #define MAC_REG_PATRN_CRC2 0xB4 | |
| 380 | #define MAC_REG_PATRN_CRC3 0xB6 | |
| 381 | #define MAC_REG_PATRN_CRC4 0xB8 | |
| 382 | #define MAC_REG_PATRN_CRC5 0xBA | |
| 383 | #define MAC_REG_PATRN_CRC6 0xBC | |
| 384 | #define MAC_REG_PATRN_CRC7 0xBE | |
| 385 | #define MAC_REG_BYTEMSK0_0 0xC0 | |
| 386 | #define MAC_REG_BYTEMSK0_1 0xC4 | |
| 387 | #define MAC_REG_BYTEMSK0_2 0xC8 | |
| 388 | #define MAC_REG_BYTEMSK0_3 0xCC | |
| 389 | #define MAC_REG_BYTEMSK1_0 0xD0 | |
| 390 | #define MAC_REG_BYTEMSK1_1 0xD4 | |
| 391 | #define MAC_REG_BYTEMSK1_2 0xD8 | |
| 392 | #define MAC_REG_BYTEMSK1_3 0xDC | |
| 393 | #define MAC_REG_BYTEMSK2_0 0xE0 | |
| 394 | #define MAC_REG_BYTEMSK2_1 0xE4 | |
| 395 | #define MAC_REG_BYTEMSK2_2 0xE8 | |
| 396 | #define MAC_REG_BYTEMSK2_3 0xEC | |
| 397 | #define MAC_REG_BYTEMSK3_0 0xF0 | |
| 398 | #define MAC_REG_BYTEMSK3_1 0xF4 | |
| 399 | #define MAC_REG_BYTEMSK3_2 0xF8 | |
| 400 | #define MAC_REG_BYTEMSK3_3 0xFC | |
| 401 | ||
| 402 | /* | |
| 403 | * Bits in the RCR register | |
| 404 | */ | |
| 405 | ||
| 406 | #define RCR_AS 0x80 | |
| 407 | #define RCR_AP 0x40 | |
| 408 | #define RCR_AL 0x20 | |
| 409 | #define RCR_PROM 0x10 | |
| 410 | #define RCR_AB 0x08 | |
| 411 | #define RCR_AM 0x04 | |
| 412 | #define RCR_AR 0x02 | |
| 413 | #define RCR_SEP 0x01 | |
| 414 | ||
| 415 | /* | |
| 416 | * Bits in the TCR register | |
| 417 | */ | |
| 418 | ||
| 419 | #define TCR_TB2BDIS 0x80 | |
| 420 | #define TCR_COLTMC1 0x08 | |
| 421 | #define TCR_COLTMC0 0x04 | |
| 422 | #define TCR_LB1 0x02 /* loopback[1] */ | |
| 423 | #define TCR_LB0 0x01 /* loopback[0] */ | |
| 424 | ||
| 425 | /* | |
| 426 | * Bits in the CR0 register | |
| 427 | */ | |
| 428 | ||
| 429 | #define CR0_TXON 0x00000008UL | |
| 430 | #define CR0_RXON 0x00000004UL | |
| 431 | #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */ | |
| 432 | #define CR0_STRT 0x00000001UL /* start MAC */ | |
| 433 | #define CR0_SFRST 0x00008000UL /* software reset */ | |
| 434 | #define CR0_TM1EN 0x00004000UL | |
| 435 | #define CR0_TM0EN 0x00002000UL | |
| 436 | #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */ | |
| 437 | #define CR0_DISAU 0x00000100UL | |
| 438 | #define CR0_XONEN 0x00800000UL | |
| 439 | #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */ | |
| 440 | #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */ | |
| 441 | #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */ | |
| 442 | #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */ | |
| 443 | #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */ | |
| 444 | #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */ | |
| 445 | #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */ | |
| 446 | #define CR0_GSPRST 0x80000000UL | |
| 447 | #define CR0_FORSRST 0x40000000UL | |
| 448 | #define CR0_FPHYRST 0x20000000UL | |
| 449 | #define CR0_DIAG 0x10000000UL | |
| 450 | #define CR0_INTPCTL 0x04000000UL | |
| 451 | #define CR0_GINTMSK1 0x02000000UL | |
| 452 | #define CR0_GINTMSK0 0x01000000UL | |
| 453 | ||
| 454 | /* | |
| 455 | * Bits in the CR1 register | |
| 456 | */ | |
| 457 | ||
| 458 | #define CR1_SFRST 0x80 /* software reset */ | |
| 459 | #define CR1_TM1EN 0x40 | |
| 460 | #define CR1_TM0EN 0x20 | |
| 461 | #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */ | |
| 462 | #define CR1_DISAU 0x01 | |
| 463 | ||
| 464 | /* | |
| 465 | * Bits in the CR2 register | |
| 466 | */ | |
| 467 | ||
| 468 | #define CR2_XONEN 0x80 | |
| 469 | #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */ | |
| 470 | #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */ | |
| 471 | #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */ | |
| 472 | #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */ | |
| 473 | #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */ | |
| 474 | #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */ | |
| 475 | #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */ | |
| 476 | ||
| 477 | /* | |
| 478 | * Bits in the CR3 register | |
| 479 | */ | |
| 480 | ||
| 481 | #define CR3_GSPRST 0x80 | |
| 482 | #define CR3_FORSRST 0x40 | |
| 483 | #define CR3_FPHYRST 0x20 | |
| 484 | #define CR3_DIAG 0x10 | |
| 485 | #define CR3_INTPCTL 0x04 | |
| 486 | #define CR3_GINTMSK1 0x02 | |
| 487 | #define CR3_GINTMSK0 0x01 | |
| 488 | ||
| 489 | #define ISRCTL_UDPINT 0x8000 | |
| 490 | #define ISRCTL_TSUPDIS 0x4000 | |
| 491 | #define ISRCTL_RSUPDIS 0x2000 | |
| 492 | #define ISRCTL_PMSK1 0x1000 | |
| 493 | #define ISRCTL_PMSK0 0x0800 | |
| 494 | #define ISRCTL_INTPD 0x0400 | |
| 495 | #define ISRCTL_HCRLD 0x0200 | |
| 496 | #define ISRCTL_SCRLD 0x0100 | |
| 497 | ||
| 498 | /* | |
| 499 | * Bits in the ISR_CTL1 register | |
| 500 | */ | |
| 501 | ||
| 502 | #define ISRCTL1_UDPINT 0x80 | |
| 503 | #define ISRCTL1_TSUPDIS 0x40 | |
| 504 | #define ISRCTL1_RSUPDIS 0x20 | |
| 505 | #define ISRCTL1_PMSK1 0x10 | |
| 506 | #define ISRCTL1_PMSK0 0x08 | |
| 507 | #define ISRCTL1_INTPD 0x04 | |
| 508 | #define ISRCTL1_HCRLD 0x02 | |
| 509 | #define ISRCTL1_SCRLD 0x01 | |
| 510 | ||
| 511 | /* | |
| 512 | * Bits in the TXE_SR register | |
| 513 | */ | |
| 514 | ||
| 515 | #define TXESR_TFDBS 0x08 | |
| 516 | #define TXESR_TDWBS 0x04 | |
| 517 | #define TXESR_TDRBS 0x02 | |
| 518 | #define TXESR_TDSTR 0x01 | |
| 519 | ||
| 520 | /* | |
| 521 | * Bits in the RXE_SR register | |
| 522 | */ | |
| 523 | ||
| 524 | #define RXESR_RFDBS 0x08 | |
| 525 | #define RXESR_RDWBS 0x04 | |
| 526 | #define RXESR_RDRBS 0x02 | |
| 527 | #define RXESR_RDSTR 0x01 | |
| 528 | ||
| 529 | /* | |
| 530 | * Bits in the ISR register | |
| 531 | */ | |
| 532 | ||
| 533 | #define ISR_ISR3 0x80000000UL | |
| 534 | #define ISR_ISR2 0x40000000UL | |
| 535 | #define ISR_ISR1 0x20000000UL | |
| 536 | #define ISR_ISR0 0x10000000UL | |
| 537 | #define ISR_TXSTLI 0x02000000UL | |
| 538 | #define ISR_RXSTLI 0x01000000UL | |
| 539 | #define ISR_HFLD 0x00800000UL | |
| 540 | #define ISR_UDPI 0x00400000UL | |
| 541 | #define ISR_MIBFI 0x00200000UL | |
| 542 | #define ISR_SHDNI 0x00100000UL | |
| 543 | #define ISR_PHYI 0x00080000UL | |
| 544 | #define ISR_PWEI 0x00040000UL | |
| 545 | #define ISR_TMR1I 0x00020000UL | |
| 546 | #define ISR_TMR0I 0x00010000UL | |
| 547 | #define ISR_SRCI 0x00008000UL | |
| 548 | #define ISR_LSTPEI 0x00004000UL | |
| 549 | #define ISR_LSTEI 0x00002000UL | |
| 550 | #define ISR_OVFI 0x00001000UL | |
| 551 | #define ISR_FLONI 0x00000800UL | |
| 552 | #define ISR_RACEI 0x00000400UL | |
| 553 | #define ISR_TXWB1I 0x00000200UL | |
| 554 | #define ISR_TXWB0I 0x00000100UL | |
| 555 | #define ISR_PTX3I 0x00000080UL | |
| 556 | #define ISR_PTX2I 0x00000040UL | |
| 557 | #define ISR_PTX1I 0x00000020UL | |
| 558 | #define ISR_PTX0I 0x00000010UL | |
| 559 | #define ISR_PTXI 0x00000008UL | |
| 560 | #define ISR_PRXI 0x00000004UL | |
| 561 | #define ISR_PPTXI 0x00000002UL | |
| 562 | #define ISR_PPRXI 0x00000001UL | |
| 563 | ||
| 564 | /* | |
| 565 | * Bits in the IMR register | |
| 566 | */ | |
| 567 | ||
| 568 | #define IMR_TXSTLM 0x02000000UL | |
| 569 | #define IMR_UDPIM 0x00400000UL | |
| 570 | #define IMR_MIBFIM 0x00200000UL | |
| 571 | #define IMR_SHDNIM 0x00100000UL | |
| 572 | #define IMR_PHYIM 0x00080000UL | |
| 573 | #define IMR_PWEIM 0x00040000UL | |
| 574 | #define IMR_TMR1IM 0x00020000UL | |
| 575 | #define IMR_TMR0IM 0x00010000UL | |
| 576 | ||
| 577 | #define IMR_SRCIM 0x00008000UL | |
| 578 | #define IMR_LSTPEIM 0x00004000UL | |
| 579 | #define IMR_LSTEIM 0x00002000UL | |
| 580 | #define IMR_OVFIM 0x00001000UL | |
| 581 | #define IMR_FLONIM 0x00000800UL | |
| 582 | #define IMR_RACEIM 0x00000400UL | |
| 583 | #define IMR_TXWB1IM 0x00000200UL | |
| 584 | #define IMR_TXWB0IM 0x00000100UL | |
| 585 | ||
| 586 | #define IMR_PTX3IM 0x00000080UL | |
| 587 | #define IMR_PTX2IM 0x00000040UL | |
| 588 | #define IMR_PTX1IM 0x00000020UL | |
| 589 | #define IMR_PTX0IM 0x00000010UL | |
| 590 | #define IMR_PTXIM 0x00000008UL | |
| 591 | #define IMR_PRXIM 0x00000004UL | |
| 592 | #define IMR_PPTXIM 0x00000002UL | |
| 593 | #define IMR_PPRXIM 0x00000001UL | |
| 594 | ||
| 595 | /* 0x0013FB0FUL = initial value of IMR */ | |
| 596 | ||
| 597 | #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\ | |
| 598 | IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\ | |
| 599 | IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\ | |
| 600 | IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM) | |
| 601 | ||
| 602 | /* | |
| 603 | * Bits in the TDCSR0/1, RDCSR0 register | |
| 604 | */ | |
| 605 | ||
| 606 | #define TRDCSR_DEAD 0x0008 | |
| 607 | #define TRDCSR_WAK 0x0004 | |
| 608 | #define TRDCSR_ACT 0x0002 | |
| 609 | #define TRDCSR_RUN 0x0001 | |
| 610 | ||
| 611 | /* | |
| 612 | * Bits in the CAMADDR register | |
| 613 | */ | |
| 614 | ||
| 615 | #define CAMADDR_CAMEN 0x80 | |
| 616 | #define CAMADDR_VCAMSL 0x40 | |
| 617 | ||
| 618 | /* | |
| 619 | * Bits in the CAMCR register | |
| 620 | */ | |
| 621 | ||
| 622 | #define CAMCR_PS1 0x80 | |
| 623 | #define CAMCR_PS0 0x40 | |
| 624 | #define CAMCR_AITRPKT 0x20 | |
| 625 | #define CAMCR_AITR16 0x10 | |
| 626 | #define CAMCR_CAMRD 0x08 | |
| 627 | #define CAMCR_CAMWR 0x04 | |
| 628 | #define CAMCR_PS_CAM_MASK 0x40 | |
| 629 | #define CAMCR_PS_CAM_DATA 0x80 | |
| 630 | #define CAMCR_PS_MAR 0x00 | |
| 631 | ||
| 632 | /* | |
| 633 | * Bits in the MIICFG register | |
| 634 | */ | |
| 635 | ||
| 636 | #define MIICFG_MPO1 0x80 | |
| 637 | #define MIICFG_MPO0 0x40 | |
| 638 | #define MIICFG_MFDC 0x20 | |
| 639 | ||
| 640 | /* | |
| 641 | * Bits in the MIISR register | |
| 642 | */ | |
| 643 | ||
| 644 | #define MIISR_MIDLE 0x80 | |
| 645 | ||
| 646 | /* | |
| 647 | * Bits in the PHYSR0 register | |
| 648 | */ | |
| 649 | ||
| 650 | #define PHYSR0_PHYRST 0x80 | |
| 651 | #define PHYSR0_LINKGD 0x40 | |
| 652 | #define PHYSR0_FDPX 0x10 | |
| 653 | #define PHYSR0_SPDG 0x08 | |
| 654 | #define PHYSR0_SPD10 0x04 | |
| 655 | #define PHYSR0_RXFLC 0x02 | |
| 656 | #define PHYSR0_TXFLC 0x01 | |
| 657 | ||
| 658 | /* | |
| 659 | * Bits in the PHYSR1 register | |
| 660 | */ | |
| 661 | ||
| 662 | #define PHYSR1_PHYTBI 0x01 | |
| 663 | ||
| 664 | /* | |
| 665 | * Bits in the MIICR register | |
| 666 | */ | |
| 667 | ||
| 668 | #define MIICR_MAUTO 0x80 | |
| 669 | #define MIICR_RCMD 0x40 | |
| 670 | #define MIICR_WCMD 0x20 | |
| 671 | #define MIICR_MDPM 0x10 | |
| 672 | #define MIICR_MOUT 0x08 | |
| 673 | #define MIICR_MDO 0x04 | |
| 674 | #define MIICR_MDI 0x02 | |
| 675 | #define MIICR_MDC 0x01 | |
| 676 | ||
| 677 | /* | |
| 678 | * Bits in the MIIADR register | |
| 679 | */ | |
| 680 | ||
| 681 | #define MIIADR_SWMPL 0x80 | |
| 682 | ||
| 683 | /* | |
| 684 | * Bits in the CFGA register | |
| 685 | */ | |
| 686 | ||
| 687 | #define CFGA_PMHCTG 0x08 | |
| 688 | #define CFGA_GPIO1PD 0x04 | |
| 689 | #define CFGA_ABSHDN 0x02 | |
| 690 | #define CFGA_PACPI 0x01 | |
| 691 | ||
| 692 | /* | |
| 693 | * Bits in the CFGB register | |
| 694 | */ | |
| 695 | ||
| 696 | #define CFGB_GTCKOPT 0x80 | |
| 697 | #define CFGB_MIIOPT 0x40 | |
| 698 | #define CFGB_CRSEOPT 0x20 | |
| 699 | #define CFGB_OFSET 0x10 | |
| 700 | #define CFGB_CRANDOM 0x08 | |
| 701 | #define CFGB_CAP 0x04 | |
| 702 | #define CFGB_MBA 0x02 | |
| 703 | #define CFGB_BAKOPT 0x01 | |
| 704 | ||
| 705 | /* | |
| 706 | * Bits in the CFGC register | |
| 707 | */ | |
| 708 | ||
| 709 | #define CFGC_EELOAD 0x80 | |
| 710 | #define CFGC_BROPT 0x40 | |
| 711 | #define CFGC_DLYEN 0x20 | |
| 712 | #define CFGC_DTSEL 0x10 | |
| 713 | #define CFGC_BTSEL 0x08 | |
| 714 | #define CFGC_BPS2 0x04 /* bootrom select[2] */ | |
| 715 | #define CFGC_BPS1 0x02 /* bootrom select[1] */ | |
| 716 | #define CFGC_BPS0 0x01 /* bootrom select[0] */ | |
| 717 | ||
| 718 | /* | |
| 719 | * Bits in the CFGD register | |
| 720 | */ | |
| 721 | ||
| 722 | #define CFGD_IODIS 0x80 | |
| 723 | #define CFGD_MSLVDACEN 0x40 | |
| 724 | #define CFGD_CFGDACEN 0x20 | |
| 725 | #define CFGD_PCI64EN 0x10 | |
| 726 | #define CFGD_HTMRL4 0x08 | |
| 727 | ||
| 728 | /* | |
| 729 | * Bits in the DCFG1 register | |
| 730 | */ | |
| 731 | ||
| 732 | #define DCFG_XMWI 0x8000 | |
| 733 | #define DCFG_XMRM 0x4000 | |
| 734 | #define DCFG_XMRL 0x2000 | |
| 735 | #define DCFG_PERDIS 0x1000 | |
| 736 | #define DCFG_MRWAIT 0x0400 | |
| 737 | #define DCFG_MWWAIT 0x0200 | |
| 738 | #define DCFG_LATMEN 0x0100 | |
| 739 | ||
| 740 | /* | |
| 741 | * Bits in the MCFG0 register | |
| 742 | */ | |
| 743 | ||
| 744 | #define MCFG_RXARB 0x0080 | |
| 745 | #define MCFG_RFT1 0x0020 | |
| 746 | #define MCFG_RFT0 0x0010 | |
| 747 | #define MCFG_LOWTHOPT 0x0008 | |
| 748 | #define MCFG_PQEN 0x0004 | |
| 749 | #define MCFG_RTGOPT 0x0002 | |
| 750 | #define MCFG_VIDFR 0x0001 | |
| 751 | ||
| 752 | /* | |
| 753 | * Bits in the MCFG1 register | |
| 754 | */ | |
| 755 | ||
| 756 | #define MCFG_TXARB 0x8000 | |
| 757 | #define MCFG_TXQBK1 0x0800 | |
| 758 | #define MCFG_TXQBK0 0x0400 | |
| 759 | #define MCFG_TXQNOBK 0x0200 | |
| 760 | #define MCFG_SNAPOPT 0x0100 | |
| 761 | ||
| 762 | /* | |
| 763 | * Bits in the PMCC register | |
| 764 | */ | |
| 765 | ||
| 766 | #define PMCC_DSI 0x80 | |
| 767 | #define PMCC_D2_DIS 0x40 | |
| 768 | #define PMCC_D1_DIS 0x20 | |
| 769 | #define PMCC_D3C_EN 0x10 | |
| 770 | #define PMCC_D3H_EN 0x08 | |
| 771 | #define PMCC_D2_EN 0x04 | |
| 772 | #define PMCC_D1_EN 0x02 | |
| 773 | #define PMCC_D0_EN 0x01 | |
| 774 | ||
| 775 | /* | |
| 776 | * Bits in STICKHW | |
| 777 | */ | |
| 778 | ||
| 779 | #define STICKHW_SWPTAG 0x10 | |
| 780 | #define STICKHW_WOLSR 0x08 | |
| 781 | #define STICKHW_WOLEN 0x04 | |
| 782 | #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */ | |
| 783 | #define STICKHW_DS0 0x01 /* suspend well DS write port */ | |
| 784 | ||
| 785 | /* | |
| 786 | * Bits in the MIBCR register | |
| 787 | */ | |
| 788 | ||
| 789 | #define MIBCR_MIBISTOK 0x80 | |
| 790 | #define MIBCR_MIBISTGO 0x40 | |
| 791 | #define MIBCR_MIBINC 0x20 | |
| 792 | #define MIBCR_MIBHI 0x10 | |
| 793 | #define MIBCR_MIBFRZ 0x08 | |
| 794 | #define MIBCR_MIBFLSH 0x04 | |
| 795 | #define MIBCR_MPTRINI 0x02 | |
| 796 | #define MIBCR_MIBCLR 0x01 | |
| 797 | ||
| 798 | /* | |
| 799 | * Bits in the EERSV register | |
| 800 | */ | |
| 801 | ||
| 802 | #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */ | |
| 803 | ||
| 804 | #define EERSV_BOOT_MASK ((u8) 0x06) | |
| 805 | #define EERSV_BOOT_INT19 ((u8) 0x00) | |
| 806 | #define EERSV_BOOT_INT18 ((u8) 0x02) | |
| 807 | #define EERSV_BOOT_LOCAL ((u8) 0x04) | |
| 808 | #define EERSV_BOOT_BEV ((u8) 0x06) | |
| 809 | ||
| 810 | ||
| 811 | /* | |
| 812 | * Bits in BPCMD | |
| 813 | */ | |
| 814 | ||
| 815 | #define BPCMD_BPDNE 0x80 | |
| 816 | #define BPCMD_EBPWR 0x02 | |
| 817 | #define BPCMD_EBPRD 0x01 | |
| 818 | ||
| 819 | /* | |
| 820 | * Bits in the EECSR register | |
| 821 | */ | |
| 822 | ||
| 5a6338db | 823 | #define EECSR_EMBP 0x40 /* eeprom embedded programming */ |
| 1da177e4 LT |
824 | #define EECSR_RELOAD 0x20 /* eeprom content reload */ |
| 825 | #define EECSR_DPM 0x10 /* eeprom direct programming */ | |
| 826 | #define EECSR_ECS 0x08 /* eeprom CS pin */ | |
| 827 | #define EECSR_ECK 0x04 /* eeprom CK pin */ | |
| 828 | #define EECSR_EDI 0x02 /* eeprom DI pin */ | |
| 829 | #define EECSR_EDO 0x01 /* eeprom DO pin */ | |
| 830 | ||
| 831 | /* | |
| 832 | * Bits in the EMBCMD register | |
| 833 | */ | |
| 834 | ||
| 835 | #define EMBCMD_EDONE 0x80 | |
| 836 | #define EMBCMD_EWDIS 0x08 | |
| 837 | #define EMBCMD_EWEN 0x04 | |
| 838 | #define EMBCMD_EWR 0x02 | |
| 839 | #define EMBCMD_ERD 0x01 | |
| 840 | ||
| 841 | /* | |
| 842 | * Bits in TESTCFG register | |
| 843 | */ | |
| 844 | ||
| 845 | #define TESTCFG_HBDIS 0x80 | |
| 846 | ||
| 847 | /* | |
| 848 | * Bits in CHIPGCR register | |
| 849 | */ | |
| 850 | ||
| 15419227 | 851 | #define CHIPGCR_FCGMII 0x80 /* enable GMII mode */ |
| 1da177e4 LT |
852 | #define CHIPGCR_FCFDX 0x40 |
| 853 | #define CHIPGCR_FCRESV 0x20 | |
| 854 | #define CHIPGCR_FCMODE 0x10 | |
| 855 | #define CHIPGCR_LPSOPT 0x08 | |
| 856 | #define CHIPGCR_TM1US 0x04 | |
| 857 | #define CHIPGCR_TM0US 0x02 | |
| 858 | #define CHIPGCR_PHYINTEN 0x01 | |
| 859 | ||
| 860 | /* | |
| 861 | * Bits in WOLCR0 | |
| 862 | */ | |
| 863 | ||
| 864 | #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */ | |
| 865 | #define WOLCR_MSWOLEN6 0x0040 | |
| 866 | #define WOLCR_MSWOLEN5 0x0020 | |
| 867 | #define WOLCR_MSWOLEN4 0x0010 | |
| 868 | #define WOLCR_MSWOLEN3 0x0008 | |
| 869 | #define WOLCR_MSWOLEN2 0x0004 | |
| 870 | #define WOLCR_MSWOLEN1 0x0002 | |
| 871 | #define WOLCR_MSWOLEN0 0x0001 | |
| 872 | #define WOLCR_ARP_EN 0x0001 | |
| 873 | ||
| 874 | /* | |
| 875 | * Bits in WOLCR1 | |
| 876 | */ | |
| 877 | ||
| 878 | #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */ | |
| 879 | #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */ | |
| 880 | #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */ | |
| 881 | #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */ | |
| 882 | ||
| 883 | ||
| 884 | /* | |
| 885 | * Bits in PWCFG | |
| 886 | */ | |
| 887 | ||
| 888 | #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */ | |
| 889 | #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */ | |
| 890 | #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */ | |
| 891 | #define PWCFG_LEGCY_WOL 0x10 | |
| 892 | #define PWCFG_PMCSR_PME_SR 0x08 | |
| 893 | #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */ | |
| 894 | #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */ | |
| 895 | #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */ | |
| 896 | ||
| 897 | /* | |
| 898 | * Bits in WOLCFG | |
| 899 | */ | |
| 900 | ||
| 901 | #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */ | |
| 902 | #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */ | |
| 903 | #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */ | |
| 904 | #define WOLCFG_SMIIACC 0x08 /* ?? */ | |
| 905 | #define WOLCFG_SGENWH 0x02 | |
| 906 | #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII | |
| 907 | to report status change */ | |
| 908 | /* | |
| 909 | * Bits in WOLSR1 | |
| 910 | */ | |
| 911 | ||
| 912 | #define WOLSR_LINKOFF_INT 0x0800 | |
| 913 | #define WOLSR_LINKON_INT 0x0400 | |
| 914 | #define WOLSR_MAGIC_INT 0x0200 | |
| 915 | #define WOLSR_UNICAST_INT 0x0100 | |
| 916 | ||
| 917 | /* | |
| 918 | * Ethernet address filter type | |
| 919 | */ | |
| 920 | ||
| 921 | #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */ | |
| 922 | #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */ | |
| 923 | #define PKT_TYPE_MULTICAST 0x0002 | |
| 924 | #define PKT_TYPE_ALL_MULTICAST 0x0004 | |
| 925 | #define PKT_TYPE_BROADCAST 0x0008 | |
| 926 | #define PKT_TYPE_PROMISCUOUS 0x0020 | |
| 927 | #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */ | |
| 928 | #define PKT_TYPE_RUNT 0x4000 | |
| 929 | #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */ | |
| 930 | ||
| 931 | /* | |
| 932 | * Loopback mode | |
| 933 | */ | |
| 934 | ||
| 935 | #define MAC_LB_NONE 0x00 | |
| 936 | #define MAC_LB_INTERNAL 0x01 | |
| 937 | #define MAC_LB_EXTERNAL 0x02 | |
| 938 | ||
| 939 | /* | |
| 940 | * Enabled mask value of irq | |
| 941 | */ | |
| 942 | ||
| 943 | #if defined(_SIM) | |
| 944 | #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR | |
| 945 | set IMR0 to 0x0F according to spec */ | |
| 946 | ||
| 947 | #else | |
| 948 | #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR | |
| 949 | ignore MIBFI,RACEI to | |
| 950 | reduce intr. frequency | |
| 951 | NOTE.... do not enable NoBuf int mask at driver driver | |
| 952 | when (1) NoBuf -> RxThreshold = SF | |
| 953 | (2) OK -> RxThreshold = original value | |
| 954 | */ | |
| 955 | #endif | |
| 956 | ||
| 957 | /* | |
| 958 | * Revision id | |
| 959 | */ | |
| 960 | ||
| 961 | #define REV_ID_VT3119_A0 0x00 | |
| 962 | #define REV_ID_VT3119_A1 0x01 | |
| 963 | #define REV_ID_VT3216_A0 0x10 | |
| 964 | ||
| 965 | /* | |
| 966 | * Max time out delay time | |
| 967 | */ | |
| 968 | ||
| 969 | #define W_MAX_TIMEOUT 0x0FFFU | |
| 970 | ||
| 971 | ||
| 972 | /* | |
| 973 | * MAC registers as a structure. Cannot be directly accessed this | |
| 974 | * way but generates offsets for readl/writel() calls | |
| 975 | */ | |
| 976 | ||
| 977 | struct mac_regs { | |
| 978 | volatile u8 PAR[6]; /* 0x00 */ | |
| 979 | volatile u8 RCR; | |
| 980 | volatile u8 TCR; | |
| 981 | ||
| 4a51c0d0 AV |
982 | volatile __le32 CR0Set; /* 0x08 */ |
| 983 | volatile __le32 CR0Clr; /* 0x0C */ | |
| 1da177e4 LT |
984 | |
| 985 | volatile u8 MARCAM[8]; /* 0x10 */ | |
| 986 | ||
| 4a51c0d0 AV |
987 | volatile __le32 DecBaseHi; /* 0x18 */ |
| 988 | volatile __le16 DbfBaseHi; /* 0x1C */ | |
| 989 | volatile __le16 reserved_1E; | |
| 1da177e4 | 990 | |
| 4a51c0d0 | 991 | volatile __le16 ISRCTL; /* 0x20 */ |
| 1da177e4 LT |
992 | volatile u8 TXESR; |
| 993 | volatile u8 RXESR; | |
| 994 | ||
| 4a51c0d0 AV |
995 | volatile __le32 ISR; /* 0x24 */ |
| 996 | volatile __le32 IMR; | |
| 1da177e4 | 997 | |
| 4a51c0d0 | 998 | volatile __le32 TDStatusPort; /* 0x2C */ |
| 1da177e4 | 999 | |
| 4a51c0d0 | 1000 | volatile __le16 TDCSRSet; /* 0x30 */ |
| 1da177e4 LT |
1001 | volatile u8 RDCSRSet; |
| 1002 | volatile u8 reserved_33; | |
| 4a51c0d0 | 1003 | volatile __le16 TDCSRClr; |
| 1da177e4 LT |
1004 | volatile u8 RDCSRClr; |
| 1005 | volatile u8 reserved_37; | |
| 1006 | ||
| 4a51c0d0 AV |
1007 | volatile __le32 RDBaseLo; /* 0x38 */ |
| 1008 | volatile __le16 RDIdx; /* 0x3C */ | |
| 6dfc4b95 SK |
1009 | volatile u8 TQETMR; /* 0x3E, VT3216 and above only */ |
| 1010 | volatile u8 RQETMR; /* 0x3F, VT3216 and above only */ | |
| 1da177e4 | 1011 | |
| 4a51c0d0 | 1012 | volatile __le32 TDBaseLo[4]; /* 0x40 */ |
| 1da177e4 | 1013 | |
| 4a51c0d0 AV |
1014 | volatile __le16 RDCSize; /* 0x50 */ |
| 1015 | volatile __le16 TDCSize; /* 0x52 */ | |
| 1016 | volatile __le16 TDIdx[4]; /* 0x54 */ | |
| 1017 | volatile __le16 tx_pause_timer; /* 0x5C */ | |
| 1018 | volatile __le16 RBRDU; /* 0x5E */ | |
| 1da177e4 | 1019 | |
| 4a51c0d0 AV |
1020 | volatile __le32 FIFOTest0; /* 0x60 */ |
| 1021 | volatile __le32 FIFOTest1; /* 0x64 */ | |
| 1da177e4 LT |
1022 | |
| 1023 | volatile u8 CAMADDR; /* 0x68 */ | |
| 1024 | volatile u8 CAMCR; /* 0x69 */ | |
| 1025 | volatile u8 GFTEST; /* 0x6A */ | |
| 1026 | volatile u8 FTSTCMD; /* 0x6B */ | |
| 1027 | ||
| 1028 | volatile u8 MIICFG; /* 0x6C */ | |
| 1029 | volatile u8 MIISR; | |
| 1030 | volatile u8 PHYSR0; | |
| 1031 | volatile u8 PHYSR1; | |
| 1032 | volatile u8 MIICR; | |
| 1033 | volatile u8 MIIADR; | |
| 4a51c0d0 | 1034 | volatile __le16 MIIDATA; |
| 1da177e4 | 1035 | |
| 4a51c0d0 AV |
1036 | volatile __le16 SoftTimer0; /* 0x74 */ |
| 1037 | volatile __le16 SoftTimer1; | |
| 1da177e4 LT |
1038 | |
| 1039 | volatile u8 CFGA; /* 0x78 */ | |
| 1040 | volatile u8 CFGB; | |
| 1041 | volatile u8 CFGC; | |
| 1042 | volatile u8 CFGD; | |
| 1043 | ||
| 4a51c0d0 AV |
1044 | volatile __le16 DCFG; /* 0x7C */ |
| 1045 | volatile __le16 MCFG; | |
| 1da177e4 LT |
1046 | |
| 1047 | volatile u8 TBIST; /* 0x80 */ | |
| 1048 | volatile u8 RBIST; | |
| 1049 | volatile u8 PMCPORT; | |
| 1050 | volatile u8 STICKHW; | |
| 1051 | ||
| 1052 | volatile u8 MIBCR; /* 0x84 */ | |
| 1053 | volatile u8 reserved_85; | |
| 1054 | volatile u8 rev_id; | |
| 1055 | volatile u8 PORSTS; | |
| 1056 | ||
| 4a51c0d0 | 1057 | volatile __le32 MIBData; /* 0x88 */ |
| 1da177e4 | 1058 | |
| 4a51c0d0 | 1059 | volatile __le16 EEWrData; |
| 1da177e4 LT |
1060 | |
| 1061 | volatile u8 reserved_8E; | |
| 1062 | volatile u8 BPMDWr; | |
| 1063 | volatile u8 BPCMD; | |
| 1064 | volatile u8 BPMDRd; | |
| 1065 | ||
| 1066 | volatile u8 EECHKSUM; /* 0x92 */ | |
| 1067 | volatile u8 EECSR; | |
| 1068 | ||
| 4a51c0d0 | 1069 | volatile __le16 EERdData; /* 0x94 */ |
| 1da177e4 LT |
1070 | volatile u8 EADDR; |
| 1071 | volatile u8 EMBCMD; | |
| 1072 | ||
| 1073 | ||
| 1074 | volatile u8 JMPSR0; /* 0x98 */ | |
| 1075 | volatile u8 JMPSR1; | |
| 1076 | volatile u8 JMPSR2; | |
| 1077 | volatile u8 JMPSR3; | |
| 1078 | volatile u8 CHIPGSR; /* 0x9C */ | |
| 1079 | volatile u8 TESTCFG; | |
| 1080 | volatile u8 DEBUG; | |
| 1081 | volatile u8 CHIPGCR; | |
| 1082 | ||
| 4a51c0d0 | 1083 | volatile __le16 WOLCRSet; /* 0xA0 */ |
| 1da177e4 LT |
1084 | volatile u8 PWCFGSet; |
| 1085 | volatile u8 WOLCFGSet; | |
| 1086 | ||
| 4a51c0d0 | 1087 | volatile __le16 WOLCRClr; /* 0xA4 */ |
| 1da177e4 LT |
1088 | volatile u8 PWCFGCLR; |
| 1089 | volatile u8 WOLCFGClr; | |
| 1090 | ||
| 4a51c0d0 AV |
1091 | volatile __le16 WOLSRSet; /* 0xA8 */ |
| 1092 | volatile __le16 reserved_AA; | |
| 1da177e4 | 1093 | |
| 4a51c0d0 AV |
1094 | volatile __le16 WOLSRClr; /* 0xAC */ |
| 1095 | volatile __le16 reserved_AE; | |
| 1da177e4 | 1096 | |
| 4a51c0d0 AV |
1097 | volatile __le16 PatternCRC[8]; /* 0xB0 */ |
| 1098 | volatile __le32 ByteMask[4][4]; /* 0xC0 */ | |
| ba2d3587 | 1099 | } __packed; |
| 1da177e4 LT |
1100 | |
| 1101 | ||
| 1102 | enum hw_mib { | |
| 1103 | HW_MIB_ifRxAllPkts = 0, | |
| 1104 | HW_MIB_ifRxOkPkts, | |
| 1105 | HW_MIB_ifTxOkPkts, | |
| 1106 | HW_MIB_ifRxErrorPkts, | |
| 1107 | HW_MIB_ifRxRuntOkPkt, | |
| 1108 | HW_MIB_ifRxRuntErrPkt, | |
| 1109 | HW_MIB_ifRx64Pkts, | |
| 1110 | HW_MIB_ifTx64Pkts, | |
| 1111 | HW_MIB_ifRx65To127Pkts, | |
| 1112 | HW_MIB_ifTx65To127Pkts, | |
| 1113 | HW_MIB_ifRx128To255Pkts, | |
| 1114 | HW_MIB_ifTx128To255Pkts, | |
| 1115 | HW_MIB_ifRx256To511Pkts, | |
| 1116 | HW_MIB_ifTx256To511Pkts, | |
| 1117 | HW_MIB_ifRx512To1023Pkts, | |
| 1118 | HW_MIB_ifTx512To1023Pkts, | |
| 1119 | HW_MIB_ifRx1024To1518Pkts, | |
| 1120 | HW_MIB_ifTx1024To1518Pkts, | |
| 1121 | HW_MIB_ifTxEtherCollisions, | |
| 1122 | HW_MIB_ifRxPktCRCE, | |
| 1123 | HW_MIB_ifRxJumboPkts, | |
| 1124 | HW_MIB_ifTxJumboPkts, | |
| 1125 | HW_MIB_ifRxMacControlFrames, | |
| 1126 | HW_MIB_ifTxMacControlFrames, | |
| 1127 | HW_MIB_ifRxPktFAE, | |
| 1128 | HW_MIB_ifRxLongOkPkt, | |
| 1129 | HW_MIB_ifRxLongPktErrPkt, | |
| 1130 | HW_MIB_ifTXSQEErrors, | |
| 1131 | HW_MIB_ifRxNobuf, | |
| 1132 | HW_MIB_ifRxSymbolErrors, | |
| 1133 | HW_MIB_ifInRangeLengthErrors, | |
| 1134 | HW_MIB_ifLateCollisions, | |
| 1135 | HW_MIB_SIZE | |
| 1136 | }; | |
| 1137 | ||
| 1138 | enum chip_type { | |
| 1139 | CHIP_TYPE_VT6110 = 1, | |
| 1140 | }; | |
| 1141 | ||
| 1142 | struct velocity_info_tbl { | |
| 1143 | enum chip_type chip_id; | |
| 01faccbf | 1144 | const char *name; |
| 1da177e4 LT |
1145 | int txqueue; |
| 1146 | u32 flags; | |
| 1147 | }; | |
| 1148 | ||
| 1149 | #define mac_hw_mibs_init(regs) {\ | |
| 1150 | BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\ | |
| 1151 | BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\ | |
| 1152 | do {}\ | |
| 1153 | while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\ | |
| 1154 | BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\ | |
| 1155 | } | |
| 1156 | ||
| 1157 | #define mac_read_isr(regs) readl(&((regs)->ISR)) | |
| 1158 | #define mac_write_isr(regs, x) writel((x),&((regs)->ISR)) | |
| 1159 | #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR)) | |
| 1160 | ||
| 1161 | #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR)); | |
| 1162 | #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr)) | |
| 1163 | #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set)) | |
| 1164 | ||
| 1da177e4 LT |
1165 | #define mac_set_dma_length(regs, n) {\ |
| 1166 | BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\ | |
| 1167 | } | |
| 1168 | ||
| 1169 | #define mac_set_rx_thresh(regs, n) {\ | |
| 1170 | BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\ | |
| 1171 | } | |
| 1172 | ||
| 1173 | #define mac_rx_queue_run(regs) {\ | |
| 1174 | writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\ | |
| 1175 | } | |
| 1176 | ||
| 1177 | #define mac_rx_queue_wake(regs) {\ | |
| 1178 | writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\ | |
| 1179 | } | |
| 1180 | ||
| 1181 | #define mac_tx_queue_run(regs, n) {\ | |
| 1182 | writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\ | |
| 1183 | } | |
| 1184 | ||
| 1185 | #define mac_tx_queue_wake(regs, n) {\ | |
| 1186 | writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\ | |
| 1187 | } | |
| 1188 | ||
| 01faccbf SH |
1189 | static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) { |
| 1190 | int i=0; | |
| 1da177e4 | 1191 | |
| 01faccbf SH |
1192 | BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR)); |
| 1193 | do { | |
| 1194 | udelay(10); | |
| 1195 | if (i++>0x1000) | |
| 1196 | break; | |
| 1197 | } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR))); | |
| 1da177e4 LT |
1198 | } |
| 1199 | ||
| 1da177e4 LT |
1200 | /* |
| 1201 | * Header for WOL definitions. Used to compute hashes | |
| 1202 | */ | |
| 1203 | ||
| 1204 | typedef u8 MCAM_ADDR[ETH_ALEN]; | |
| 1205 | ||
| 1206 | struct arp_packet { | |
| 1207 | u8 dest_mac[ETH_ALEN]; | |
| 1208 | u8 src_mac[ETH_ALEN]; | |
| 4a51c0d0 AV |
1209 | __be16 type; |
| 1210 | __be16 ar_hrd; | |
| 1211 | __be16 ar_pro; | |
| 1da177e4 LT |
1212 | u8 ar_hln; |
| 1213 | u8 ar_pln; | |
| 4a51c0d0 | 1214 | __be16 ar_op; |
| 1da177e4 LT |
1215 | u8 ar_sha[ETH_ALEN]; |
| 1216 | u8 ar_sip[4]; | |
| 1217 | u8 ar_tha[ETH_ALEN]; | |
| 1218 | u8 ar_tip[4]; | |
| ba2d3587 | 1219 | } __packed; |
| 1da177e4 LT |
1220 | |
| 1221 | struct _magic_packet { | |
| 1222 | u8 dest_mac[6]; | |
| 1223 | u8 src_mac[6]; | |
| 4a51c0d0 | 1224 | __be16 type; |
| 1da177e4 LT |
1225 | u8 MAC[16][6]; |
| 1226 | u8 password[6]; | |
| ba2d3587 | 1227 | } __packed; |
| 1da177e4 LT |
1228 | |
| 1229 | /* | |
| 1230 | * Store for chip context when saving and restoring status. Not | |
| 1231 | * all fields are saved/restored currently. | |
| 1232 | */ | |
| 1233 | ||
| 1234 | struct velocity_context { | |
| 1235 | u8 mac_reg[256]; | |
| 1236 | MCAM_ADDR cam_addr[MCAM_SIZE]; | |
| 1237 | u16 vcam[VCAM_SIZE]; | |
| 1238 | u32 cammask[2]; | |
| 1239 | u32 patcrc[2]; | |
| 1240 | u32 pattern[8]; | |
| 1241 | }; | |
| 1242 | ||
| 1da177e4 LT |
1243 | /* |
| 1244 | * Registers in the MII (offset unit is WORD) | |
| 1245 | */ | |
| 1246 | ||
| 1da177e4 LT |
1247 | // Marvell 88E1000/88E1000S |
| 1248 | #define MII_REG_PSCR 0x10 // PHY specific control register | |
| 1249 | ||
| 1250 | // | |
| 3a7f8681 | 1251 | // Bits in the Silicon revision register |
| 1da177e4 | 1252 | // |
| 1da177e4 LT |
1253 | |
| 1254 | #define TCSR_ECHODIS 0x2000 // | |
| 1255 | #define AUXCR_MDPPS 0x0004 // | |
| 1256 | ||
| 1257 | // Bits in the PLED register | |
| 1258 | #define PLED_LALBE 0x0004 // | |
| 1259 | ||
| 1260 | // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h) | |
| 1261 | #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit | |
| 1262 | ||
| 1263 | #define PHYID_CICADA_CS8201 0x000FC410UL | |
| 1264 | #define PHYID_VT3216_32BIT 0x000FC610UL | |
| 1265 | #define PHYID_VT3216_64BIT 0x000FC600UL | |
| 1266 | #define PHYID_MARVELL_1000 0x01410C50UL | |
| 1267 | #define PHYID_MARVELL_1000S 0x01410C40UL | |
| 1268 | ||
| 1269 | #define PHYID_REV_ID_MASK 0x0000000FUL | |
| 1270 | ||
| 1da177e4 LT |
1271 | #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK) |
| 1272 | ||
| 1273 | #define MII_REG_BITS_ON(x,i,p) do {\ | |
| 1274 | u16 w;\ | |
| 1275 | velocity_mii_read((p),(i),&(w));\ | |
| 1276 | (w)|=(x);\ | |
| 1277 | velocity_mii_write((p),(i),(w));\ | |
| 1278 | } while (0) | |
| 1279 | ||
| 1280 | #define MII_REG_BITS_OFF(x,i,p) do {\ | |
| 1281 | u16 w;\ | |
| 1282 | velocity_mii_read((p),(i),&(w));\ | |
| 1283 | (w)&=(~(x));\ | |
| 1284 | velocity_mii_write((p),(i),(w));\ | |
| 1285 | } while (0) | |
| 1286 | ||
| 1287 | #define MII_REG_BITS_IS_ON(x,i,p) ({\ | |
| 1288 | u16 w;\ | |
| 1289 | velocity_mii_read((p),(i),&(w));\ | |
| 1290 | ((int) ((w) & (x)));}) | |
| 1291 | ||
| 1292 | #define MII_GET_PHY_ID(p) ({\ | |
| 1293 | u32 id;\ | |
| 3a7f8681 FR |
1294 | velocity_mii_read((p),MII_PHYSID2,(u16 *) &id);\ |
| 1295 | velocity_mii_read((p),MII_PHYSID1,((u16 *) &id)+1);\ | |
| 1da177e4 LT |
1296 | (id);}) |
| 1297 | ||
| 1298 | /* | |
| 1299 | * Inline debug routine | |
| 1300 | */ | |
| 1301 | ||
| 1302 | ||
| 1303 | enum velocity_msg_level { | |
| 1304 | MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation. | |
| 1305 | MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified. | |
| 1306 | MSG_LEVEL_INFO = 2, //Normal message. | |
| 1307 | MSG_LEVEL_VERBOSE = 3, //Will report all trival errors. | |
| 1308 | MSG_LEVEL_DEBUG = 4 //Only for debug purpose. | |
| 1309 | }; | |
| 1310 | ||
| 1311 | #ifdef VELOCITY_DEBUG | |
| 1312 | #define ASSERT(x) { \ | |
| 1313 | if (!(x)) { \ | |
| 1314 | printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\ | |
| b39d66a8 | 1315 | __func__, __LINE__);\ |
| 1da177e4 LT |
1316 | BUG(); \ |
| 1317 | }\ | |
| 1318 | } | |
| 1319 | #define VELOCITY_DBG(p,args...) printk(p, ##args) | |
| 1320 | #else | |
| 1321 | #define ASSERT(x) | |
| 1322 | #define VELOCITY_DBG(x) | |
| 1323 | #endif | |
| 1324 | ||
| 1325 | #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printk( p ,##args);} while (0) | |
| 1326 | ||
| 1327 | #define VELOCITY_PRT_CAMMASK(p,t) {\ | |
| 1328 | int i;\ | |
| 1329 | if ((t)==VELOCITY_MULTICAST_CAM) {\ | |
| 1330 | for (i=0;i<(MCAM_SIZE/8);i++)\ | |
| 1331 | printk("%02X",(p)->mCAMmask[i]);\ | |
| 1332 | }\ | |
| 1333 | else {\ | |
| 1334 | for (i=0;i<(VCAM_SIZE/8);i++)\ | |
| 1335 | printk("%02X",(p)->vCAMmask[i]);\ | |
| 1336 | }\ | |
| 1337 | printk("\n");\ | |
| 1338 | } | |
| 1339 | ||
| 1340 | ||
| 1341 | ||
| 1342 | #define VELOCITY_WOL_MAGIC 0x00000000UL | |
| 1343 | #define VELOCITY_WOL_PHY 0x00000001UL | |
| 1344 | #define VELOCITY_WOL_ARP 0x00000002UL | |
| 1345 | #define VELOCITY_WOL_UCAST 0x00000004UL | |
| 1346 | #define VELOCITY_WOL_BCAST 0x00000010UL | |
| 1347 | #define VELOCITY_WOL_MCAST 0x00000020UL | |
| 1348 | #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL | |
| 1349 | ||
| 1350 | /* | |
| 1351 | * Flags for options | |
| 1352 | */ | |
| 1353 | ||
| 1354 | #define VELOCITY_FLAGS_TAGGING 0x00000001UL | |
| 1da177e4 LT |
1355 | #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL |
| 1356 | #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL | |
| 1357 | #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL | |
| 1358 | ||
| 1359 | #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL | |
| 1360 | ||
| 1361 | /* | |
| 1362 | * Flags for driver status | |
| 1363 | */ | |
| 1364 | ||
| 1365 | #define VELOCITY_FLAGS_OPENED 0x00010000UL | |
| 1366 | #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL | |
| 1367 | #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL | |
| 1368 | #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL | |
| 1369 | ||
| 1370 | /* | |
| 1371 | * Flags for MII status | |
| 1372 | */ | |
| 1373 | ||
| 1374 | #define VELOCITY_LINK_FAIL 0x00000001UL | |
| 1375 | #define VELOCITY_SPEED_10 0x00000002UL | |
| 1376 | #define VELOCITY_SPEED_100 0x00000004UL | |
| 1377 | #define VELOCITY_SPEED_1000 0x00000008UL | |
| 1378 | #define VELOCITY_DUPLEX_FULL 0x00000010UL | |
| 1379 | #define VELOCITY_AUTONEG_ENABLE 0x00000020UL | |
| 1380 | #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL | |
| 1381 | ||
| 1382 | /* | |
| 1383 | * For velocity_set_media_duplex | |
| 1384 | */ | |
| 1385 | ||
| 1386 | #define VELOCITY_LINK_CHANGE 0x00000001UL | |
| 1387 | ||
| 1388 | enum speed_opt { | |
| 1389 | SPD_DPX_AUTO = 0, | |
| 1390 | SPD_DPX_100_HALF = 1, | |
| 1391 | SPD_DPX_100_FULL = 2, | |
| 1392 | SPD_DPX_10_HALF = 3, | |
| 15419227 | 1393 | SPD_DPX_10_FULL = 4, |
| 1394 | SPD_DPX_1000_FULL = 5 | |
| 1da177e4 LT |
1395 | }; |
| 1396 | ||
| 1397 | enum velocity_init_type { | |
| 1398 | VELOCITY_INIT_COLD = 0, | |
| 1399 | VELOCITY_INIT_RESET, | |
| 1400 | VELOCITY_INIT_WOL | |
| 1401 | }; | |
| 1402 | ||
| 1403 | enum velocity_flow_cntl_type { | |
| 1404 | FLOW_CNTL_DEFAULT = 1, | |
| 1405 | FLOW_CNTL_TX, | |
| 1406 | FLOW_CNTL_RX, | |
| 1407 | FLOW_CNTL_TX_RX, | |
| 1408 | FLOW_CNTL_DISABLE, | |
| 1409 | }; | |
| 1410 | ||
| 1411 | struct velocity_opt { | |
| 1412 | int numrx; /* Number of RX descriptors */ | |
| 1413 | int numtx; /* Number of TX descriptors */ | |
| 1414 | enum speed_opt spd_dpx; /* Media link mode */ | |
| 501e4d24 | 1415 | |
| 1da177e4 LT |
1416 | int DMA_length; /* DMA length */ |
| 1417 | int rx_thresh; /* RX_THRESH */ | |
| 1418 | int flow_cntl; | |
| 1419 | int wol_opts; /* Wake on lan options */ | |
| 1420 | int td_int_count; | |
| 1421 | int int_works; | |
| 1422 | int rx_bandwidth_hi; | |
| 1423 | int rx_bandwidth_lo; | |
| 1424 | int rx_bandwidth_en; | |
| 6dfc4b95 SK |
1425 | int rxqueue_timer; |
| 1426 | int txqueue_timer; | |
| 1427 | int tx_intsup; | |
| 1428 | int rx_intsup; | |
| 1da177e4 LT |
1429 | u32 flags; |
| 1430 | }; | |
| 1431 | ||
| 0fe9f15e FR |
1432 | #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->tx.used[(q)])) |
| 1433 | ||
| 1434 | #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx]) | |
| 1435 | ||
| 1da177e4 | 1436 | struct velocity_info { |
| 1da177e4 LT |
1437 | struct pci_dev *pdev; |
| 1438 | struct net_device *dev; | |
| 1da177e4 | 1439 | |
| 501e4d24 | 1440 | struct vlan_group *vlgrp; |
| 1da177e4 LT |
1441 | u8 ip_addr[4]; |
| 1442 | enum chip_type chip_id; | |
| 1443 | ||
| 1444 | struct mac_regs __iomem * mac_regs; | |
| 1445 | unsigned long memaddr; | |
| 1446 | unsigned long ioaddr; | |
| 1da177e4 | 1447 | |
| 0fe9f15e FR |
1448 | struct tx_info { |
| 1449 | int numq; | |
| 1450 | ||
| 1451 | /* FIXME: the locality of the data seems rather poor. */ | |
| 1452 | int used[TX_QUEUE_NO]; | |
| 1453 | int curr[TX_QUEUE_NO]; | |
| 1454 | int tail[TX_QUEUE_NO]; | |
| 1455 | struct tx_desc *rings[TX_QUEUE_NO]; | |
| 1456 | struct velocity_td_info *infos[TX_QUEUE_NO]; | |
| 1457 | dma_addr_t pool_dma[TX_QUEUE_NO]; | |
| 1458 | } tx; | |
| 1459 | ||
| 1460 | struct rx_info { | |
| 1461 | int buf_sz; | |
| 1462 | ||
| 1463 | int dirty; | |
| 1464 | int curr; | |
| 1465 | u32 filled; | |
| 1466 | struct rx_desc *ring; | |
| 1467 | struct velocity_rd_info *info; /* It's an array */ | |
| 1468 | dma_addr_t pool_dma; | |
| 1469 | } rx; | |
| 1da177e4 | 1470 | |
| 1da177e4 LT |
1471 | u32 mib_counter[MAX_HW_MIB_COUNTER]; |
| 1472 | struct velocity_opt options; | |
| 1473 | ||
| 1474 | u32 int_mask; | |
| 1475 | ||
| 1476 | u32 flags; | |
| 1477 | ||
| 1da177e4 LT |
1478 | u32 mii_status; |
| 1479 | u32 phy_id; | |
| 1480 | int multicast_limit; | |
| 1481 | ||
| 1482 | u8 vCAMmask[(VCAM_SIZE / 8)]; | |
| 1483 | u8 mCAMmask[(MCAM_SIZE / 8)]; | |
| 1484 | ||
| 1485 | spinlock_t lock; | |
| 1486 | ||
| 1487 | int wol_opts; | |
| 1488 | u8 wol_passwd[6]; | |
| 1489 | ||
| 1490 | struct velocity_context context; | |
| 1491 | ||
| 1492 | u32 ticks; | |
| 1da177e4 | 1493 | |
| 0fe9f15e | 1494 | u8 rev_id; |
| dfff7144 SK |
1495 | |
| 1496 | struct napi_struct napi; | |
| 1da177e4 LT |
1497 | }; |
| 1498 | ||
| 1499 | /** | |
| 1500 | * velocity_get_ip - find an IP address for the device | |
| 1501 | * @vptr: Velocity to query | |
| 1502 | * | |
| 1503 | * Dig out an IP address for this interface so that we can | |
| 1504 | * configure wakeup with WOL for ARP. If there are multiple IP | |
| 1505 | * addresses on this chain then we use the first - multi-IP WOL is not | |
| 1506 | * supported. | |
| 1507 | * | |
| 1da177e4 LT |
1508 | */ |
| 1509 | ||
| 77933d72 | 1510 | static inline int velocity_get_ip(struct velocity_info *vptr) |
| 1da177e4 | 1511 | { |
| 95ae6b22 | 1512 | struct in_device *in_dev; |
| 1da177e4 | 1513 | struct in_ifaddr *ifa; |
| 95ae6b22 | 1514 | int res = -ENOENT; |
| 1da177e4 | 1515 | |
| 95ae6b22 ED |
1516 | rcu_read_lock(); |
| 1517 | in_dev = __in_dev_get_rcu(vptr->dev); | |
| 1da177e4 LT |
1518 | if (in_dev != NULL) { |
| 1519 | ifa = (struct in_ifaddr *) in_dev->ifa_list; | |
| 1520 | if (ifa != NULL) { | |
| 1521 | memcpy(vptr->ip_addr, &ifa->ifa_address, 4); | |
| 95ae6b22 | 1522 | res = 0; |
| 1da177e4 LT |
1523 | } |
| 1524 | } | |
| 95ae6b22 ED |
1525 | rcu_read_unlock(); |
| 1526 | return res; | |
| 1da177e4 LT |
1527 | } |
| 1528 | ||
| 1529 | /** | |
| 1530 | * velocity_update_hw_mibs - fetch MIB counters from chip | |
| 1531 | * @vptr: velocity to update | |
| 1532 | * | |
| 1533 | * The velocity hardware keeps certain counters in the hardware | |
| 1534 | * side. We need to read these when the user asks for statistics | |
| 1535 | * or when they overflow (causing an interrupt). The read of the | |
| 1536 | * statistic clears it, so we keep running master counters in user | |
| 1537 | * space. | |
| 1538 | */ | |
| 1539 | ||
| 1540 | static inline void velocity_update_hw_mibs(struct velocity_info *vptr) | |
| 1541 | { | |
| 1542 | u32 tmp; | |
| 1543 | int i; | |
| 1544 | BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)); | |
| 1545 | ||
| 1546 | while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR))); | |
| 1547 | ||
| 1548 | BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR)); | |
| 1549 | for (i = 0; i < HW_MIB_SIZE; i++) { | |
| 1550 | tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL; | |
| 1551 | vptr->mib_counter[i] += tmp; | |
| 1552 | } | |
| 1553 | } | |
| 1554 | ||
| 1555 | /** | |
| 1556 | * init_flow_control_register - set up flow control | |
| 1557 | * @vptr: velocity to configure | |
| 1558 | * | |
| 1559 | * Configure the flow control registers for this velocity device. | |
| 1560 | */ | |
| 1561 | ||
| 1562 | static inline void init_flow_control_register(struct velocity_info *vptr) | |
| 1563 | { | |
| 1564 | struct mac_regs __iomem * regs = vptr->mac_regs; | |
| 1565 | ||
| 1566 | /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1} | |
| 1567 | depend on RD=64, and Turn on XNOEN in FlowCR1 */ | |
| 1568 | writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set); | |
| 1569 | writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr); | |
| 1570 | ||
| 1571 | /* Set TxPauseTimer to 0xFFFF */ | |
| 1572 | writew(0xFFFF, ®s->tx_pause_timer); | |
| 1573 | ||
| 1574 | /* Initialize RBRDU to Rx buffer count. */ | |
| 1575 | writew(vptr->options.numrx, ®s->RBRDU); | |
| 1576 | } | |
| 1577 | ||
| 1578 | ||
| 1579 | #endif |