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ucc_geth: Fix empty TX queue processing
[net-next-2.6.git] / drivers / net / ucc_geth.c
CommitLineData
ce973b14 1/*
047584ce 2 * Copyright (C) 2006-2009 Freescale Semicondutor, Inc. All rights reserved.
ce973b14
LY		 3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
18a8e864 5 * Li Yang <leoli@freescale.com>
ce973b14
LY		 6 *
7 * Description:
8 * QE UCC Gigabit Ethernet Driver
9 *
ce973b14
LY		 10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/slab.h>
19#include <linux/stddef.h>
20#include <linux/interrupt.h>
21#include <linux/netdevice.h>
22#include <linux/etherdevice.h>
23#include <linux/skbuff.h>
24#include <linux/spinlock.h>
25#include <linux/mm.h>
ce973b14 26#include <linux/dma-mapping.h>
ce973b14 27#include <linux/mii.h>
728de4c9 28#include <linux/phy.h>
df19b6b0 29#include <linux/workqueue.h>
0b9da337 30#include <linux/of_mdio.h>
55b6c8e9 31#include <linux/of_platform.h>
ce973b14
LY		 32
33#include <asm/uaccess.h>
34#include <asm/irq.h>
35#include <asm/io.h>
36#include <asm/immap_qe.h>
37#include <asm/qe.h>
38#include <asm/ucc.h>
39#include <asm/ucc_fast.h>
40
41#include "ucc_geth.h"
1577ecef 42#include "fsl_pq_mdio.h"
ce973b14
LY		 43
44#undef DEBUG
45
ce973b14
LY		 46#define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
48
49#define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51#define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53#define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55#define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
57
58#ifdef UGETH_VERBOSE_DEBUG
59#define ugeth_vdbg ugeth_dbg
60#else
61#define ugeth_vdbg(fmt, args...) do { } while (0)
62#endif /* UGETH_VERBOSE_DEBUG */
890de95e 63#define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
ce973b14 64
88a15f2e 65
ce973b14
LY		 66static DEFINE_SPINLOCK(ugeth_lock);
67
890de95e
LY		 68static struct {
69 u32 msg_enable;
70} debug = { -1 };
71
72module_param_named(debug, debug.msg_enable, int, 0);
73MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 0xffff=all)");
74
18a8e864 75static struct ucc_geth_info ugeth_primary_info = {
ce973b14
LY		 76 .uf_info = {
77 .bd_mem_part = MEM_PART_SYSTEM,
78 .rtsm = UCC_FAST_SEND_IDLES_BETWEEN_FRAMES,
79 .max_rx_buf_length = 1536,
728de4c9 80 /* adjusted at startup if max-speed 1000 */
ce973b14
LY		 81 .urfs = UCC_GETH_URFS_INIT,
82 .urfet = UCC_GETH_URFET_INIT,
83 .urfset = UCC_GETH_URFSET_INIT,
84 .utfs = UCC_GETH_UTFS_INIT,
85 .utfet = UCC_GETH_UTFET_INIT,
86 .utftt = UCC_GETH_UTFTT_INIT,
ce973b14
LY		 87 .ufpt = 256,
88 .mode = UCC_FAST_PROTOCOL_MODE_ETHERNET,
89 .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
90 .tenc = UCC_FAST_TX_ENCODING_NRZ,
91 .renc = UCC_FAST_RX_ENCODING_NRZ,
92 .tcrc = UCC_FAST_16_BIT_CRC,
93 .synl = UCC_FAST_SYNC_LEN_NOT_USED,
94 },
95 .numQueuesTx = 1,
96 .numQueuesRx = 1,
97 .extendedFilteringChainPointer = ((uint32_t) NULL),
98 .typeorlen = 3072 /*1536 */ ,
99 .nonBackToBackIfgPart1 = 0x40,
100 .nonBackToBackIfgPart2 = 0x60,
101 .miminumInterFrameGapEnforcement = 0x50,
102 .backToBackInterFrameGap = 0x60,
103 .mblinterval = 128,
104 .nortsrbytetime = 5,
105 .fracsiz = 1,
106 .strictpriorityq = 0xff,
107 .altBebTruncation = 0xa,
108 .excessDefer = 1,
109 .maxRetransmission = 0xf,
110 .collisionWindow = 0x37,
111 .receiveFlowControl = 1,
ac421852 112 .transmitFlowControl = 1,
ce973b14
LY		 113 .maxGroupAddrInHash = 4,
114 .maxIndAddrInHash = 4,
115 .prel = 7,
116 .maxFrameLength = 1518,
117 .minFrameLength = 64,
118 .maxD1Length = 1520,
119 .maxD2Length = 1520,
120 .vlantype = 0x8100,
121 .ecamptr = ((uint32_t) NULL),
122 .eventRegMask = UCCE_OTHER,
123 .pausePeriod = 0xf000,
124 .interruptcoalescingmaxvalue = {1, 1, 1, 1, 1, 1, 1, 1},
125 .bdRingLenTx = {
126 TX_BD_RING_LEN,
127 TX_BD_RING_LEN,
128 TX_BD_RING_LEN,
129 TX_BD_RING_LEN,
130 TX_BD_RING_LEN,
131 TX_BD_RING_LEN,
132 TX_BD_RING_LEN,
133 TX_BD_RING_LEN},
134
135 .bdRingLenRx = {
136 RX_BD_RING_LEN,
137 RX_BD_RING_LEN,
138 RX_BD_RING_LEN,
139 RX_BD_RING_LEN,
140 RX_BD_RING_LEN,
141 RX_BD_RING_LEN,
142 RX_BD_RING_LEN,
143 RX_BD_RING_LEN},
144
145 .numStationAddresses = UCC_GETH_NUM_OF_STATION_ADDRESSES_1,
146 .largestexternallookupkeysize =
147 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE,
ac421852
LY		 148 .statisticsMode = UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE |
149 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX |
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX,
ce973b14
LY		 151 .vlanOperationTagged = UCC_GETH_VLAN_OPERATION_TAGGED_NOP,
152 .vlanOperationNonTagged = UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP,
153 .rxQoSMode = UCC_GETH_QOS_MODE_DEFAULT,
154 .aufc = UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE,
155 .padAndCrc = MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC,
ffea31ed
JT		 156 .numThreadsTx = UCC_GETH_NUM_OF_THREADS_1,
157 .numThreadsRx = UCC_GETH_NUM_OF_THREADS_1,
ce973b14
LY		 158 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
159 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
160};
161
18a8e864 162static struct ucc_geth_info ugeth_info[8];
ce973b14
LY		 163
164#ifdef DEBUG
165static void mem_disp(u8 *addr, int size)
166{
167 u8 *i;
168 int size16Aling = (size >> 4) << 4;
169 int size4Aling = (size >> 2) << 2;
170 int notAlign = 0;
171 if (size % 16)
172 notAlign = 1;
173
174 for (i = addr; (u32) i < (u32) addr + size16Aling; i += 16)
175 printk("0x%08x: %08x %08x %08x %08x\r\n",
176 (u32) i,
177 *((u32 *) (i)),
178 *((u32 *) (i + 4)),
179 *((u32 *) (i + 8)), *((u32 *) (i + 12)));
180 if (notAlign == 1)
181 printk("0x%08x: ", (u32) i);
182 for (; (u32) i < (u32) addr + size4Aling; i += 4)
183 printk("%08x ", *((u32 *) (i)));
184 for (; (u32) i < (u32) addr + size; i++)
185 printk("%02x", *((u8 *) (i)));
186 if (notAlign == 1)
187 printk("\r\n");
188}
189#endif /* DEBUG */
190
ce973b14
LY		 191static struct list_head *dequeue(struct list_head *lh)
192{
193 unsigned long flags;
194
1083cfe1 195 spin_lock_irqsave(&ugeth_lock, flags);
ce973b14
LY		 196 if (!list_empty(lh)) {
197 struct list_head *node = lh->next;
198 list_del(node);
1083cfe1 199 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 200 return node;
201 } else {
1083cfe1 202 spin_unlock_irqrestore(&ugeth_lock, flags);
ce973b14
LY		 203 return NULL;
204 }
205}
206
6fee40e9
AF		 207static struct sk_buff *get_new_skb(struct ucc_geth_private *ugeth,
208 u8 __iomem *bd)
ce973b14
LY		 209{
210 struct sk_buff *skb = NULL;
211
50f238fd
AV		 212 skb = __skb_dequeue(&ugeth->rx_recycle);
213 if (!skb)
214 skb = dev_alloc_skb(ugeth->ug_info->uf_info.max_rx_buf_length +
215 UCC_GETH_RX_DATA_BUF_ALIGNMENT);
ce973b14
LY		 216 if (skb == NULL)
217 return NULL;
218
219 /* We need the data buffer to be aligned properly. We will reserve
220 * as many bytes as needed to align the data properly
221 */
222 skb_reserve(skb,
223 UCC_GETH_RX_DATA_BUF_ALIGNMENT -
224 (((unsigned)skb->data) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT -
225 1)));
226
da1aa63e 227 skb->dev = ugeth->ndev;
ce973b14 228
6fee40e9 229 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 230 dma_map_single(ugeth->dev,
ce973b14
LY		 231 skb->data,
232 ugeth->ug_info->uf_info.max_rx_buf_length +
233 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
234 DMA_FROM_DEVICE));
235
6fee40e9
AF		 236 out_be32((u32 __iomem *)bd,
237 (R_E | R_I | (in_be32((u32 __iomem*)bd) & R_W)));
ce973b14
LY		 238
239 return skb;
240}
241
18a8e864 242static int rx_bd_buffer_set(struct ucc_geth_private *ugeth, u8 rxQ)
ce973b14 243{
6fee40e9 244 u8 __iomem *bd;
ce973b14
LY		 245 u32 bd_status;
246 struct sk_buff *skb;
247 int i;
248
249 bd = ugeth->p_rx_bd_ring[rxQ];
250 i = 0;
251
252 do {
6fee40e9 253 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 254 skb = get_new_skb(ugeth, bd);
255
256 if (!skb) /* If can not allocate data buffer,
257 abort. Cleanup will be elsewhere */
258 return -ENOMEM;
259
260 ugeth->rx_skbuff[rxQ][i] = skb;
261
262 /* advance the BD pointer */
18a8e864 263 bd += sizeof(struct qe_bd);
ce973b14
LY		 264 i++;
265 } while (!(bd_status & R_W));
266
267 return 0;
268}
269
18a8e864 270static int fill_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 271 u32 *p_start,
ce973b14
LY		 272 u8 num_entries,
273 u32 thread_size,
274 u32 thread_alignment,
345f8422 275 unsigned int risc,
ce973b14
LY		 276 int skip_page_for_first_entry)
277{
278 u32 init_enet_offset;
279 u8 i;
280 int snum;
281
282 for (i = 0; i < num_entries; i++) {
283 if ((snum = qe_get_snum()) < 0) {
890de95e
LY		 284 if (netif_msg_ifup(ugeth))
285 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
ce973b14
LY		 286 return snum;
287 }
288 if ((i == 0) && skip_page_for_first_entry)
289 /* First entry of Rx does not have page */
290 init_enet_offset = 0;
291 else {
292 init_enet_offset =
293 qe_muram_alloc(thread_size, thread_alignment);
4c35630c 294 if (IS_ERR_VALUE(init_enet_offset)) {
890de95e
LY		 295 if (netif_msg_ifup(ugeth))
296 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
ce973b14
LY		 297 qe_put_snum((u8) snum);
298 return -ENOMEM;
299 }
300 }
301 *(p_start++) =
302 ((u8) snum << ENET_INIT_PARAM_SNUM_SHIFT) | init_enet_offset
303 | risc;
304 }
305
306 return 0;
307}
308
18a8e864 309static int return_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 310 u32 *p_start,
ce973b14 311 u8 num_entries,
345f8422 312 unsigned int risc,
ce973b14
LY		 313 int skip_page_for_first_entry)
314{
315 u32 init_enet_offset;
316 u8 i;
317 int snum;
318
319 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 320 u32 val = *p_start;
321
ce973b14
LY		 322 /* Check that this entry was actually valid --
323 needed in case failed in allocations */
6fee40e9 324 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 325 snum =
6fee40e9 326 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 327 ENET_INIT_PARAM_SNUM_SHIFT;
328 qe_put_snum((u8) snum);
329 if (!((i == 0) && skip_page_for_first_entry)) {
330 /* First entry of Rx does not have page */
331 init_enet_offset =
6fee40e9 332 (val & ENET_INIT_PARAM_PTR_MASK);
ce973b14
LY		 333 qe_muram_free(init_enet_offset);
334 }
6fee40e9 335 *p_start++ = 0;
ce973b14
LY		 336 }
337 }
338
339 return 0;
340}
341
342#ifdef DEBUG
18a8e864 343static int dump_init_enet_entries(struct ucc_geth_private *ugeth,
6fee40e9 344 u32 __iomem *p_start,
ce973b14
LY		 345 u8 num_entries,
346 u32 thread_size,
345f8422 347 unsigned int risc,
ce973b14
LY		 348 int skip_page_for_first_entry)
349{
350 u32 init_enet_offset;
351 u8 i;
352 int snum;
353
354 for (i = 0; i < num_entries; i++) {
6fee40e9
AF		 355 u32 val = in_be32(p_start);
356
ce973b14
LY		 357 /* Check that this entry was actually valid --
358 needed in case failed in allocations */
6fee40e9 359 if ((val & ENET_INIT_PARAM_RISC_MASK) == risc) {
ce973b14 360 snum =
6fee40e9 361 (u32) (val & ENET_INIT_PARAM_SNUM_MASK) >>
ce973b14
LY		 362 ENET_INIT_PARAM_SNUM_SHIFT;
363 qe_put_snum((u8) snum);
364 if (!((i == 0) && skip_page_for_first_entry)) {
365 /* First entry of Rx does not have page */
366 init_enet_offset =
367 (in_be32(p_start) &
368 ENET_INIT_PARAM_PTR_MASK);
369 ugeth_info("Init enet entry %d:", i);
370 ugeth_info("Base address: 0x%08x",
371 (u32)
372 qe_muram_addr(init_enet_offset));
373 mem_disp(qe_muram_addr(init_enet_offset),
374 thread_size);
375 }
376 p_start++;
377 }
378 }
379
380 return 0;
381}
382#endif
383
18a8e864 384static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
ce973b14
LY		 385{
386 kfree(enet_addr_cont);
387}
388
df19b6b0 389static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
18a8e864
LY		 390{
391 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
392 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
393 out_be16(&reg[2], ((u16)mac[1] << 8) | mac[0]);
394}
395
18a8e864 396static int hw_clear_addr_in_paddr(struct ucc_geth_private *ugeth, u8 paddr_num)
ce973b14 397{
6fee40e9 398 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 399
400 if (!(paddr_num < NUM_OF_PADDRS)) {
b39d66a8 401 ugeth_warn("%s: Illagel paddr_num.", __func__);
ce973b14
LY		 402 return -EINVAL;
403 }
404
405 p_82xx_addr_filt =
6fee40e9 406 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 407 addressfiltering;
408
409 /* Writing address ff.ff.ff.ff.ff.ff disables address
410 recognition for this register */
411 out_be16(&p_82xx_addr_filt->paddr[paddr_num].h, 0xffff);
412 out_be16(&p_82xx_addr_filt->paddr[paddr_num].m, 0xffff);
413 out_be16(&p_82xx_addr_filt->paddr[paddr_num].l, 0xffff);
414
415 return 0;
416}
417
18a8e864
LY		 418static void hw_add_addr_in_hash(struct ucc_geth_private *ugeth,
419 u8 *p_enet_addr)
ce973b14 420{
6fee40e9 421 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
ce973b14
LY		 422 u32 cecr_subblock;
423
424 p_82xx_addr_filt =
6fee40e9 425 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->p_rx_glbl_pram->
ce973b14
LY		 426 addressfiltering;
427
428 cecr_subblock =
429 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
430
431 /* Ethernet frames are defined in Little Endian mode,
432 therefor to insert */
433 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
18a8e864
LY		 434
435 set_mac_addr(&p_82xx_addr_filt->taddr.h, p_enet_addr);
ce973b14
LY		 436
437 qe_issue_cmd(QE_SET_GROUP_ADDRESS, cecr_subblock,
18a8e864 438 QE_CR_PROTOCOL_ETHERNET, 0);
ce973b14
LY		 439}
440
18a8e864 441static inline int compare_addr(u8 **addr1, u8 **addr2)
ce973b14
LY		 442{
443 return memcmp(addr1, addr2, ENET_NUM_OCTETS_PER_ADDRESS);
444}
445
446#ifdef DEBUG
18a8e864
LY		 447static void get_statistics(struct ucc_geth_private *ugeth,
448 struct ucc_geth_tx_firmware_statistics *
ce973b14 449 tx_firmware_statistics,
18a8e864 450 struct ucc_geth_rx_firmware_statistics *
ce973b14 451 rx_firmware_statistics,
18a8e864 452 struct ucc_geth_hardware_statistics *hardware_statistics)
ce973b14 453{
6fee40e9
AF		 454 struct ucc_fast __iomem *uf_regs;
455 struct ucc_geth __iomem *ug_regs;
18a8e864
LY		 456 struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
457 struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
ce973b14
LY		 458
459 ug_regs = ugeth->ug_regs;
6fee40e9 460 uf_regs = (struct ucc_fast __iomem *) ug_regs;
ce973b14
LY		 461 p_tx_fw_statistics_pram = ugeth->p_tx_fw_statistics_pram;
462 p_rx_fw_statistics_pram = ugeth->p_rx_fw_statistics_pram;
463
464 /* Tx firmware only if user handed pointer and driver actually
465 gathers Tx firmware statistics */
466 if (tx_firmware_statistics && p_tx_fw_statistics_pram) {
467 tx_firmware_statistics->sicoltx =
468 in_be32(&p_tx_fw_statistics_pram->sicoltx);
469 tx_firmware_statistics->mulcoltx =
470 in_be32(&p_tx_fw_statistics_pram->mulcoltx);
471 tx_firmware_statistics->latecoltxfr =
472 in_be32(&p_tx_fw_statistics_pram->latecoltxfr);
473 tx_firmware_statistics->frabortduecol =
474 in_be32(&p_tx_fw_statistics_pram->frabortduecol);
475 tx_firmware_statistics->frlostinmactxer =
476 in_be32(&p_tx_fw_statistics_pram->frlostinmactxer);
477 tx_firmware_statistics->carriersenseertx =
478 in_be32(&p_tx_fw_statistics_pram->carriersenseertx);
479 tx_firmware_statistics->frtxok =
480 in_be32(&p_tx_fw_statistics_pram->frtxok);
481 tx_firmware_statistics->txfrexcessivedefer =
482 in_be32(&p_tx_fw_statistics_pram->txfrexcessivedefer);
483 tx_firmware_statistics->txpkts256 =
484 in_be32(&p_tx_fw_statistics_pram->txpkts256);
485 tx_firmware_statistics->txpkts512 =
486 in_be32(&p_tx_fw_statistics_pram->txpkts512);
487 tx_firmware_statistics->txpkts1024 =
488 in_be32(&p_tx_fw_statistics_pram->txpkts1024);
489 tx_firmware_statistics->txpktsjumbo =
490 in_be32(&p_tx_fw_statistics_pram->txpktsjumbo);
491 }
492
493 /* Rx firmware only if user handed pointer and driver actually
494 * gathers Rx firmware statistics */
495 if (rx_firmware_statistics && p_rx_fw_statistics_pram) {
496 int i;
497 rx_firmware_statistics->frrxfcser =
498 in_be32(&p_rx_fw_statistics_pram->frrxfcser);
499 rx_firmware_statistics->fraligner =
500 in_be32(&p_rx_fw_statistics_pram->fraligner);
501 rx_firmware_statistics->inrangelenrxer =
502 in_be32(&p_rx_fw_statistics_pram->inrangelenrxer);
503 rx_firmware_statistics->outrangelenrxer =
504 in_be32(&p_rx_fw_statistics_pram->outrangelenrxer);
505 rx_firmware_statistics->frtoolong =
506 in_be32(&p_rx_fw_statistics_pram->frtoolong);
507 rx_firmware_statistics->runt =
508 in_be32(&p_rx_fw_statistics_pram->runt);
509 rx_firmware_statistics->verylongevent =
510 in_be32(&p_rx_fw_statistics_pram->verylongevent);
511 rx_firmware_statistics->symbolerror =
512 in_be32(&p_rx_fw_statistics_pram->symbolerror);
513 rx_firmware_statistics->dropbsy =
514 in_be32(&p_rx_fw_statistics_pram->dropbsy);
515 for (i = 0; i < 0x8; i++)
516 rx_firmware_statistics->res0[i] =
517 p_rx_fw_statistics_pram->res0[i];
518 rx_firmware_statistics->mismatchdrop =
519 in_be32(&p_rx_fw_statistics_pram->mismatchdrop);
520 rx_firmware_statistics->underpkts =
521 in_be32(&p_rx_fw_statistics_pram->underpkts);
522 rx_firmware_statistics->pkts256 =
523 in_be32(&p_rx_fw_statistics_pram->pkts256);
524 rx_firmware_statistics->pkts512 =
525 in_be32(&p_rx_fw_statistics_pram->pkts512);
526 rx_firmware_statistics->pkts1024 =
527 in_be32(&p_rx_fw_statistics_pram->pkts1024);
528 rx_firmware_statistics->pktsjumbo =
529 in_be32(&p_rx_fw_statistics_pram->pktsjumbo);
530 rx_firmware_statistics->frlossinmacer =
531 in_be32(&p_rx_fw_statistics_pram->frlossinmacer);
532 rx_firmware_statistics->pausefr =
533 in_be32(&p_rx_fw_statistics_pram->pausefr);
534 for (i = 0; i < 0x4; i++)
535 rx_firmware_statistics->res1[i] =
536 p_rx_fw_statistics_pram->res1[i];
537 rx_firmware_statistics->removevlan =
538 in_be32(&p_rx_fw_statistics_pram->removevlan);
539 rx_firmware_statistics->replacevlan =
540 in_be32(&p_rx_fw_statistics_pram->replacevlan);
541 rx_firmware_statistics->insertvlan =
542 in_be32(&p_rx_fw_statistics_pram->insertvlan);
543 }
544
545 /* Hardware only if user handed pointer and driver actually
546 gathers hardware statistics */
3bc53427
TT		 547 if (hardware_statistics &&
548 (in_be32(&uf_regs->upsmr) & UCC_GETH_UPSMR_HSE)) {
ce973b14
LY		 549 hardware_statistics->tx64 = in_be32(&ug_regs->tx64);
550 hardware_statistics->tx127 = in_be32(&ug_regs->tx127);
551 hardware_statistics->tx255 = in_be32(&ug_regs->tx255);
552 hardware_statistics->rx64 = in_be32(&ug_regs->rx64);
553 hardware_statistics->rx127 = in_be32(&ug_regs->rx127);
554 hardware_statistics->rx255 = in_be32(&ug_regs->rx255);
555 hardware_statistics->txok = in_be32(&ug_regs->txok);
556 hardware_statistics->txcf = in_be16(&ug_regs->txcf);
557 hardware_statistics->tmca = in_be32(&ug_regs->tmca);
558 hardware_statistics->tbca = in_be32(&ug_regs->tbca);
559 hardware_statistics->rxfok = in_be32(&ug_regs->rxfok);
560 hardware_statistics->rxbok = in_be32(&ug_regs->rxbok);
561 hardware_statistics->rbyt = in_be32(&ug_regs->rbyt);
562 hardware_statistics->rmca = in_be32(&ug_regs->rmca);
563 hardware_statistics->rbca = in_be32(&ug_regs->rbca);
564 }
565}
566
18a8e864 567static void dump_bds(struct ucc_geth_private *ugeth)
ce973b14
LY		 568{
569 int i;
570 int length;
571
572 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
573 if (ugeth->p_tx_bd_ring[i]) {
574 length =
575 (ugeth->ug_info->bdRingLenTx[i] *
18a8e864 576 sizeof(struct qe_bd));
ce973b14
LY		 577 ugeth_info("TX BDs[%d]", i);
578 mem_disp(ugeth->p_tx_bd_ring[i], length);
579 }
580 }
581 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
582 if (ugeth->p_rx_bd_ring[i]) {
583 length =
584 (ugeth->ug_info->bdRingLenRx[i] *
18a8e864 585 sizeof(struct qe_bd));
ce973b14
LY		 586 ugeth_info("RX BDs[%d]", i);
587 mem_disp(ugeth->p_rx_bd_ring[i], length);
588 }
589 }
590}
591
18a8e864 592static void dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 593{
594 int i;
595
596 ugeth_info("UCC%d Geth registers:", ugeth->ug_info->uf_info.ucc_num);
597 ugeth_info("Base address: 0x%08x", (u32) ugeth->ug_regs);
598
599 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
600 (u32) & ugeth->ug_regs->maccfg1,
601 in_be32(&ugeth->ug_regs->maccfg1));
602 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
603 (u32) & ugeth->ug_regs->maccfg2,
604 in_be32(&ugeth->ug_regs->maccfg2));
605 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
606 (u32) & ugeth->ug_regs->ipgifg,
607 in_be32(&ugeth->ug_regs->ipgifg));
608 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
609 (u32) & ugeth->ug_regs->hafdup,
610 in_be32(&ugeth->ug_regs->hafdup));
ce973b14
LY		 611 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
612 (u32) & ugeth->ug_regs->ifctl,
613 in_be32(&ugeth->ug_regs->ifctl));
614 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
615 (u32) & ugeth->ug_regs->ifstat,
616 in_be32(&ugeth->ug_regs->ifstat));
617 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
618 (u32) & ugeth->ug_regs->macstnaddr1,
619 in_be32(&ugeth->ug_regs->macstnaddr1));
620 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
621 (u32) & ugeth->ug_regs->macstnaddr2,
622 in_be32(&ugeth->ug_regs->macstnaddr2));
623 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
624 (u32) & ugeth->ug_regs->uempr,
625 in_be32(&ugeth->ug_regs->uempr));
626 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
627 (u32) & ugeth->ug_regs->utbipar,
628 in_be32(&ugeth->ug_regs->utbipar));
629 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
630 (u32) & ugeth->ug_regs->uescr,
631 in_be16(&ugeth->ug_regs->uescr));
632 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
633 (u32) & ugeth->ug_regs->tx64,
634 in_be32(&ugeth->ug_regs->tx64));
635 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
636 (u32) & ugeth->ug_regs->tx127,
637 in_be32(&ugeth->ug_regs->tx127));
638 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
639 (u32) & ugeth->ug_regs->tx255,
640 in_be32(&ugeth->ug_regs->tx255));
641 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
642 (u32) & ugeth->ug_regs->rx64,
643 in_be32(&ugeth->ug_regs->rx64));
644 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
645 (u32) & ugeth->ug_regs->rx127,
646 in_be32(&ugeth->ug_regs->rx127));
647 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
648 (u32) & ugeth->ug_regs->rx255,
649 in_be32(&ugeth->ug_regs->rx255));
650 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
651 (u32) & ugeth->ug_regs->txok,
652 in_be32(&ugeth->ug_regs->txok));
653 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
654 (u32) & ugeth->ug_regs->txcf,
655 in_be16(&ugeth->ug_regs->txcf));
656 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
657 (u32) & ugeth->ug_regs->tmca,
658 in_be32(&ugeth->ug_regs->tmca));
659 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
660 (u32) & ugeth->ug_regs->tbca,
661 in_be32(&ugeth->ug_regs->tbca));
662 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
663 (u32) & ugeth->ug_regs->rxfok,
664 in_be32(&ugeth->ug_regs->rxfok));
665 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
666 (u32) & ugeth->ug_regs->rxbok,
667 in_be32(&ugeth->ug_regs->rxbok));
668 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
669 (u32) & ugeth->ug_regs->rbyt,
670 in_be32(&ugeth->ug_regs->rbyt));
671 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
672 (u32) & ugeth->ug_regs->rmca,
673 in_be32(&ugeth->ug_regs->rmca));
674 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
675 (u32) & ugeth->ug_regs->rbca,
676 in_be32(&ugeth->ug_regs->rbca));
677 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
678 (u32) & ugeth->ug_regs->scar,
679 in_be32(&ugeth->ug_regs->scar));
680 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
681 (u32) & ugeth->ug_regs->scam,
682 in_be32(&ugeth->ug_regs->scam));
683
684 if (ugeth->p_thread_data_tx) {
685 int numThreadsTxNumerical;
686 switch (ugeth->ug_info->numThreadsTx) {
687 case UCC_GETH_NUM_OF_THREADS_1:
688 numThreadsTxNumerical = 1;
689 break;
690 case UCC_GETH_NUM_OF_THREADS_2:
691 numThreadsTxNumerical = 2;
692 break;
693 case UCC_GETH_NUM_OF_THREADS_4:
694 numThreadsTxNumerical = 4;
695 break;
696 case UCC_GETH_NUM_OF_THREADS_6:
697 numThreadsTxNumerical = 6;
698 break;
699 case UCC_GETH_NUM_OF_THREADS_8:
700 numThreadsTxNumerical = 8;
701 break;
702 default:
703 numThreadsTxNumerical = 0;
704 break;
705 }
706
707 ugeth_info("Thread data TXs:");
708 ugeth_info("Base address: 0x%08x",
709 (u32) ugeth->p_thread_data_tx);
710 for (i = 0; i < numThreadsTxNumerical; i++) {
711 ugeth_info("Thread data TX[%d]:", i);
712 ugeth_info("Base address: 0x%08x",
713 (u32) & ugeth->p_thread_data_tx[i]);
714 mem_disp((u8 *) & ugeth->p_thread_data_tx[i],
18a8e864 715 sizeof(struct ucc_geth_thread_data_tx));
ce973b14
LY		 716 }
717 }
718 if (ugeth->p_thread_data_rx) {
719 int numThreadsRxNumerical;
720 switch (ugeth->ug_info->numThreadsRx) {
721 case UCC_GETH_NUM_OF_THREADS_1:
722 numThreadsRxNumerical = 1;
723 break;
724 case UCC_GETH_NUM_OF_THREADS_2:
725 numThreadsRxNumerical = 2;
726 break;
727 case UCC_GETH_NUM_OF_THREADS_4:
728 numThreadsRxNumerical = 4;
729 break;
730 case UCC_GETH_NUM_OF_THREADS_6:
731 numThreadsRxNumerical = 6;
732 break;
733 case UCC_GETH_NUM_OF_THREADS_8:
734 numThreadsRxNumerical = 8;
735 break;
736 default:
737 numThreadsRxNumerical = 0;
738 break;
739 }
740
741 ugeth_info("Thread data RX:");
742 ugeth_info("Base address: 0x%08x",
743 (u32) ugeth->p_thread_data_rx);
744 for (i = 0; i < numThreadsRxNumerical; i++) {
745 ugeth_info("Thread data RX[%d]:", i);
746 ugeth_info("Base address: 0x%08x",
747 (u32) & ugeth->p_thread_data_rx[i]);
748 mem_disp((u8 *) & ugeth->p_thread_data_rx[i],
18a8e864 749 sizeof(struct ucc_geth_thread_data_rx));
ce973b14
LY		 750 }
751 }
752 if (ugeth->p_exf_glbl_param) {
753 ugeth_info("EXF global param:");
754 ugeth_info("Base address: 0x%08x",
755 (u32) ugeth->p_exf_glbl_param);
756 mem_disp((u8 *) ugeth->p_exf_glbl_param,
757 sizeof(*ugeth->p_exf_glbl_param));
758 }
759 if (ugeth->p_tx_glbl_pram) {
760 ugeth_info("TX global param:");
761 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_tx_glbl_pram);
762 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
763 (u32) & ugeth->p_tx_glbl_pram->temoder,
764 in_be16(&ugeth->p_tx_glbl_pram->temoder));
765 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
766 (u32) & ugeth->p_tx_glbl_pram->sqptr,
767 in_be32(&ugeth->p_tx_glbl_pram->sqptr));
768 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
769 (u32) & ugeth->p_tx_glbl_pram->schedulerbasepointer,
770 in_be32(&ugeth->p_tx_glbl_pram->
771 schedulerbasepointer));
772 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
773 (u32) & ugeth->p_tx_glbl_pram->txrmonbaseptr,
774 in_be32(&ugeth->p_tx_glbl_pram->txrmonbaseptr));
775 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
776 (u32) & ugeth->p_tx_glbl_pram->tstate,
777 in_be32(&ugeth->p_tx_glbl_pram->tstate));
778 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
779 (u32) & ugeth->p_tx_glbl_pram->iphoffset[0],
780 ugeth->p_tx_glbl_pram->iphoffset[0]);
781 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
782 (u32) & ugeth->p_tx_glbl_pram->iphoffset[1],
783 ugeth->p_tx_glbl_pram->iphoffset[1]);
784 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
785 (u32) & ugeth->p_tx_glbl_pram->iphoffset[2],
786 ugeth->p_tx_glbl_pram->iphoffset[2]);
787 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
788 (u32) & ugeth->p_tx_glbl_pram->iphoffset[3],
789 ugeth->p_tx_glbl_pram->iphoffset[3]);
790 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
791 (u32) & ugeth->p_tx_glbl_pram->iphoffset[4],
792 ugeth->p_tx_glbl_pram->iphoffset[4]);
793 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
794 (u32) & ugeth->p_tx_glbl_pram->iphoffset[5],
795 ugeth->p_tx_glbl_pram->iphoffset[5]);
796 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
797 (u32) & ugeth->p_tx_glbl_pram->iphoffset[6],
798 ugeth->p_tx_glbl_pram->iphoffset[6]);
799 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
800 (u32) & ugeth->p_tx_glbl_pram->iphoffset[7],
801 ugeth->p_tx_glbl_pram->iphoffset[7]);
802 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
803 (u32) & ugeth->p_tx_glbl_pram->vtagtable[0],
804 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[0]));
805 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
806 (u32) & ugeth->p_tx_glbl_pram->vtagtable[1],
807 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[1]));
808 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
809 (u32) & ugeth->p_tx_glbl_pram->vtagtable[2],
810 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[2]));
811 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
812 (u32) & ugeth->p_tx_glbl_pram->vtagtable[3],
813 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[3]));
814 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
815 (u32) & ugeth->p_tx_glbl_pram->vtagtable[4],
816 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[4]));
817 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
818 (u32) & ugeth->p_tx_glbl_pram->vtagtable[5],
819 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[5]));
820 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
821 (u32) & ugeth->p_tx_glbl_pram->vtagtable[6],
822 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[6]));
823 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
824 (u32) & ugeth->p_tx_glbl_pram->vtagtable[7],
825 in_be32(&ugeth->p_tx_glbl_pram->vtagtable[7]));
826 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
827 (u32) & ugeth->p_tx_glbl_pram->tqptr,
828 in_be32(&ugeth->p_tx_glbl_pram->tqptr));
829 }
830 if (ugeth->p_rx_glbl_pram) {
831 ugeth_info("RX global param:");
832 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_glbl_pram);
833 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
834 (u32) & ugeth->p_rx_glbl_pram->remoder,
835 in_be32(&ugeth->p_rx_glbl_pram->remoder));
836 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
837 (u32) & ugeth->p_rx_glbl_pram->rqptr,
838 in_be32(&ugeth->p_rx_glbl_pram->rqptr));
839 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
840 (u32) & ugeth->p_rx_glbl_pram->typeorlen,
841 in_be16(&ugeth->p_rx_glbl_pram->typeorlen));
842 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
843 (u32) & ugeth->p_rx_glbl_pram->rxgstpack,
844 ugeth->p_rx_glbl_pram->rxgstpack);
845 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
846 (u32) & ugeth->p_rx_glbl_pram->rxrmonbaseptr,
847 in_be32(&ugeth->p_rx_glbl_pram->rxrmonbaseptr));
848 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
849 (u32) & ugeth->p_rx_glbl_pram->intcoalescingptr,
850 in_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr));
851 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
852 (u32) & ugeth->p_rx_glbl_pram->rstate,
853 ugeth->p_rx_glbl_pram->rstate);
854 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
855 (u32) & ugeth->p_rx_glbl_pram->mrblr,
856 in_be16(&ugeth->p_rx_glbl_pram->mrblr));
857 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
858 (u32) & ugeth->p_rx_glbl_pram->rbdqptr,
859 in_be32(&ugeth->p_rx_glbl_pram->rbdqptr));
860 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
861 (u32) & ugeth->p_rx_glbl_pram->mflr,
862 in_be16(&ugeth->p_rx_glbl_pram->mflr));
863 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
864 (u32) & ugeth->p_rx_glbl_pram->minflr,
865 in_be16(&ugeth->p_rx_glbl_pram->minflr));
866 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
867 (u32) & ugeth->p_rx_glbl_pram->maxd1,
868 in_be16(&ugeth->p_rx_glbl_pram->maxd1));
869 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
870 (u32) & ugeth->p_rx_glbl_pram->maxd2,
871 in_be16(&ugeth->p_rx_glbl_pram->maxd2));
872 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
873 (u32) & ugeth->p_rx_glbl_pram->ecamptr,
874 in_be32(&ugeth->p_rx_glbl_pram->ecamptr));
875 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
876 (u32) & ugeth->p_rx_glbl_pram->l2qt,
877 in_be32(&ugeth->p_rx_glbl_pram->l2qt));
878 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
879 (u32) & ugeth->p_rx_glbl_pram->l3qt[0],
880 in_be32(&ugeth->p_rx_glbl_pram->l3qt[0]));
881 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
882 (u32) & ugeth->p_rx_glbl_pram->l3qt[1],
883 in_be32(&ugeth->p_rx_glbl_pram->l3qt[1]));
884 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
885 (u32) & ugeth->p_rx_glbl_pram->l3qt[2],
886 in_be32(&ugeth->p_rx_glbl_pram->l3qt[2]));
887 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
888 (u32) & ugeth->p_rx_glbl_pram->l3qt[3],
889 in_be32(&ugeth->p_rx_glbl_pram->l3qt[3]));
890 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
891 (u32) & ugeth->p_rx_glbl_pram->l3qt[4],
892 in_be32(&ugeth->p_rx_glbl_pram->l3qt[4]));
893 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
894 (u32) & ugeth->p_rx_glbl_pram->l3qt[5],
895 in_be32(&ugeth->p_rx_glbl_pram->l3qt[5]));
896 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
897 (u32) & ugeth->p_rx_glbl_pram->l3qt[6],
898 in_be32(&ugeth->p_rx_glbl_pram->l3qt[6]));
899 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
900 (u32) & ugeth->p_rx_glbl_pram->l3qt[7],
901 in_be32(&ugeth->p_rx_glbl_pram->l3qt[7]));
902 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
903 (u32) & ugeth->p_rx_glbl_pram->vlantype,
904 in_be16(&ugeth->p_rx_glbl_pram->vlantype));
905 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
906 (u32) & ugeth->p_rx_glbl_pram->vlantci,
907 in_be16(&ugeth->p_rx_glbl_pram->vlantci));
908 for (i = 0; i < 64; i++)
909 ugeth_info
910 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
911 i,
912 (u32) & ugeth->p_rx_glbl_pram->addressfiltering[i],
913 ugeth->p_rx_glbl_pram->addressfiltering[i]);
914 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
915 (u32) & ugeth->p_rx_glbl_pram->exfGlobalParam,
916 in_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam));
917 }
918 if (ugeth->p_send_q_mem_reg) {
919 ugeth_info("Send Q memory registers:");
920 ugeth_info("Base address: 0x%08x",
921 (u32) ugeth->p_send_q_mem_reg);
922 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
923 ugeth_info("SQQD[%d]:", i);
924 ugeth_info("Base address: 0x%08x",
925 (u32) & ugeth->p_send_q_mem_reg->sqqd[i]);
926 mem_disp((u8 *) & ugeth->p_send_q_mem_reg->sqqd[i],
18a8e864 927 sizeof(struct ucc_geth_send_queue_qd));
ce973b14
LY		 928 }
929 }
930 if (ugeth->p_scheduler) {
931 ugeth_info("Scheduler:");
932 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_scheduler);
933 mem_disp((u8 *) ugeth->p_scheduler,
934 sizeof(*ugeth->p_scheduler));
935 }
936 if (ugeth->p_tx_fw_statistics_pram) {
937 ugeth_info("TX FW statistics pram:");
938 ugeth_info("Base address: 0x%08x",
939 (u32) ugeth->p_tx_fw_statistics_pram);
940 mem_disp((u8 *) ugeth->p_tx_fw_statistics_pram,
941 sizeof(*ugeth->p_tx_fw_statistics_pram));
942 }
943 if (ugeth->p_rx_fw_statistics_pram) {
944 ugeth_info("RX FW statistics pram:");
945 ugeth_info("Base address: 0x%08x",
946 (u32) ugeth->p_rx_fw_statistics_pram);
947 mem_disp((u8 *) ugeth->p_rx_fw_statistics_pram,
948 sizeof(*ugeth->p_rx_fw_statistics_pram));
949 }
950 if (ugeth->p_rx_irq_coalescing_tbl) {
951 ugeth_info("RX IRQ coalescing tables:");
952 ugeth_info("Base address: 0x%08x",
953 (u32) ugeth->p_rx_irq_coalescing_tbl);
954 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
955 ugeth_info("RX IRQ coalescing table entry[%d]:", i);
956 ugeth_info("Base address: 0x%08x",
957 (u32) & ugeth->p_rx_irq_coalescing_tbl->
958 coalescingentry[i]);
959 ugeth_info
960 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
961 (u32) & ugeth->p_rx_irq_coalescing_tbl->
962 coalescingentry[i].interruptcoalescingmaxvalue,
963 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
964 coalescingentry[i].
965 interruptcoalescingmaxvalue));
966 ugeth_info
967 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
968 (u32) & ugeth->p_rx_irq_coalescing_tbl->
969 coalescingentry[i].interruptcoalescingcounter,
970 in_be32(&ugeth->p_rx_irq_coalescing_tbl->
971 coalescingentry[i].
972 interruptcoalescingcounter));
973 }
974 }
975 if (ugeth->p_rx_bd_qs_tbl) {
976 ugeth_info("RX BD QS tables:");
977 ugeth_info("Base address: 0x%08x", (u32) ugeth->p_rx_bd_qs_tbl);
978 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
979 ugeth_info("RX BD QS table[%d]:", i);
980 ugeth_info("Base address: 0x%08x",
981 (u32) & ugeth->p_rx_bd_qs_tbl[i]);
982 ugeth_info
983 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
984 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdbaseptr,
985 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdbaseptr));
986 ugeth_info
987 ("bdptr : addr - 0x%08x, val - 0x%08x",
988 (u32) & ugeth->p_rx_bd_qs_tbl[i].bdptr,
989 in_be32(&ugeth->p_rx_bd_qs_tbl[i].bdptr));
990 ugeth_info
991 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
992 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
993 in_be32(&ugeth->p_rx_bd_qs_tbl[i].
994 externalbdbaseptr));
995 ugeth_info
996 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
997 (u32) & ugeth->p_rx_bd_qs_tbl[i].externalbdptr,
998 in_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdptr));
999 ugeth_info("ucode RX Prefetched BDs:");
1000 ugeth_info("Base address: 0x%08x",
1001 (u32)
1002 qe_muram_addr(in_be32
1003 (&ugeth->p_rx_bd_qs_tbl[i].
1004 bdbaseptr)));
1005 mem_disp((u8 *)
1006 qe_muram_addr(in_be32
1007 (&ugeth->p_rx_bd_qs_tbl[i].
1008 bdbaseptr)),
18a8e864 1009 sizeof(struct ucc_geth_rx_prefetched_bds));
ce973b14
LY		 1010 }
1011 }
1012 if (ugeth->p_init_enet_param_shadow) {
1013 int size;
1014 ugeth_info("Init enet param shadow:");
1015 ugeth_info("Base address: 0x%08x",
1016 (u32) ugeth->p_init_enet_param_shadow);
1017 mem_disp((u8 *) ugeth->p_init_enet_param_shadow,
1018 sizeof(*ugeth->p_init_enet_param_shadow));
1019
18a8e864 1020 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 1021 if (ugeth->ug_info->rxExtendedFiltering) {
1022 size +=
1023 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
1024 if (ugeth->ug_info->largestexternallookupkeysize ==
1025 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
1026 size +=
1027 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
1028 if (ugeth->ug_info->largestexternallookupkeysize ==
1029 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
1030 size +=
1031 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
1032 }
1033
1034 dump_init_enet_entries(ugeth,
1035 &(ugeth->p_init_enet_param_shadow->
1036 txthread[0]),
1037 ENET_INIT_PARAM_MAX_ENTRIES_TX,
18a8e864 1038 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 1039 ugeth->ug_info->riscTx, 0);
1040 dump_init_enet_entries(ugeth,
1041 &(ugeth->p_init_enet_param_shadow->
1042 rxthread[0]),
1043 ENET_INIT_PARAM_MAX_ENTRIES_RX, size,
1044 ugeth->ug_info->riscRx, 1);
1045 }
1046}
1047#endif /* DEBUG */
1048
6fee40e9
AF		 1049static void init_default_reg_vals(u32 __iomem *upsmr_register,
1050 u32 __iomem *maccfg1_register,
1051 u32 __iomem *maccfg2_register)
ce973b14
LY		 1052{
1053 out_be32(upsmr_register, UCC_GETH_UPSMR_INIT);
1054 out_be32(maccfg1_register, UCC_GETH_MACCFG1_INIT);
1055 out_be32(maccfg2_register, UCC_GETH_MACCFG2_INIT);
1056}
1057
1058static int init_half_duplex_params(int alt_beb,
1059 int back_pressure_no_backoff,
1060 int no_backoff,
1061 int excess_defer,
1062 u8 alt_beb_truncation,
1063 u8 max_retransmissions,
1064 u8 collision_window,
6fee40e9 1065 u32 __iomem *hafdup_register)
ce973b14
LY		 1066{
1067 u32 value = 0;
1068
1069 if ((alt_beb_truncation > HALFDUP_ALT_BEB_TRUNCATION_MAX) ||
1070 (max_retransmissions > HALFDUP_MAX_RETRANSMISSION_MAX) ||
1071 (collision_window > HALFDUP_COLLISION_WINDOW_MAX))
1072 return -EINVAL;
1073
1074 value = (u32) (alt_beb_truncation << HALFDUP_ALT_BEB_TRUNCATION_SHIFT);
1075
1076 if (alt_beb)
1077 value |= HALFDUP_ALT_BEB;
1078 if (back_pressure_no_backoff)
1079 value |= HALFDUP_BACK_PRESSURE_NO_BACKOFF;
1080 if (no_backoff)
1081 value |= HALFDUP_NO_BACKOFF;
1082 if (excess_defer)
1083 value |= HALFDUP_EXCESSIVE_DEFER;
1084
1085 value |= (max_retransmissions << HALFDUP_MAX_RETRANSMISSION_SHIFT);
1086
1087 value |= collision_window;
1088
1089 out_be32(hafdup_register, value);
1090 return 0;
1091}
1092
1093static int init_inter_frame_gap_params(u8 non_btb_cs_ipg,
1094 u8 non_btb_ipg,
1095 u8 min_ifg,
1096 u8 btb_ipg,
6fee40e9 1097 u32 __iomem *ipgifg_register)
ce973b14
LY		 1098{
1099 u32 value = 0;
1100
1101 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1102 IPG part 2 */
1103 if (non_btb_cs_ipg > non_btb_ipg)
1104 return -EINVAL;
1105
1106 if ((non_btb_cs_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX) ||
1107 (non_btb_ipg > IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX) ||
1108 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1109 (btb_ipg > IPGIFG_BACK_TO_BACK_IFG_MAX))
1110 return -EINVAL;
1111
1112 value |=
1113 ((non_btb_cs_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT) &
1114 IPGIFG_NBTB_CS_IPG_MASK);
1115 value |=
1116 ((non_btb_ipg << IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT) &
1117 IPGIFG_NBTB_IPG_MASK);
1118 value |=
1119 ((min_ifg << IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT) &
1120 IPGIFG_MIN_IFG_MASK);
1121 value |= (btb_ipg & IPGIFG_BTB_IPG_MASK);
1122
1123 out_be32(ipgifg_register, value);
1124 return 0;
1125}
1126
ac421852 1127int init_flow_control_params(u32 automatic_flow_control_mode,
ce973b14
LY		 1128 int rx_flow_control_enable,
1129 int tx_flow_control_enable,
1130 u16 pause_period,
1131 u16 extension_field,
6fee40e9
AF		 1132 u32 __iomem *upsmr_register,
1133 u32 __iomem *uempr_register,
1134 u32 __iomem *maccfg1_register)
ce973b14
LY		 1135{
1136 u32 value = 0;
1137
1138 /* Set UEMPR register */
1139 value = (u32) pause_period << UEMPR_PAUSE_TIME_VALUE_SHIFT;
1140 value |= (u32) extension_field << UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT;
1141 out_be32(uempr_register, value);
1142
1143 /* Set UPSMR register */
3bc53427 1144 setbits32(upsmr_register, automatic_flow_control_mode);
ce973b14
LY		 1145
1146 value = in_be32(maccfg1_register);
1147 if (rx_flow_control_enable)
1148 value |= MACCFG1_FLOW_RX;
1149 if (tx_flow_control_enable)
1150 value |= MACCFG1_FLOW_TX;
1151 out_be32(maccfg1_register, value);
1152
1153 return 0;
1154}
1155
1156static int init_hw_statistics_gathering_mode(int enable_hardware_statistics,
1157 int auto_zero_hardware_statistics,
6fee40e9
AF		 1158 u32 __iomem *upsmr_register,
1159 u16 __iomem *uescr_register)
ce973b14 1160{
ce973b14 1161 u16 uescr_value = 0;
3bc53427 1162
ce973b14 1163 /* Enable hardware statistics gathering if requested */
3bc53427
TT		 1164 if (enable_hardware_statistics)
1165 setbits32(upsmr_register, UCC_GETH_UPSMR_HSE);
ce973b14
LY		 1166
1167 /* Clear hardware statistics counters */
1168 uescr_value = in_be16(uescr_register);
1169 uescr_value |= UESCR_CLRCNT;
1170 /* Automatically zero hardware statistics counters on read,
1171 if requested */
1172 if (auto_zero_hardware_statistics)
1173 uescr_value |= UESCR_AUTOZ;
1174 out_be16(uescr_register, uescr_value);
1175
1176 return 0;
1177}
1178
1179static int init_firmware_statistics_gathering_mode(int
1180 enable_tx_firmware_statistics,
1181 int enable_rx_firmware_statistics,
6fee40e9 1182 u32 __iomem *tx_rmon_base_ptr,
ce973b14 1183 u32 tx_firmware_statistics_structure_address,
6fee40e9 1184 u32 __iomem *rx_rmon_base_ptr,
ce973b14 1185 u32 rx_firmware_statistics_structure_address,
6fee40e9
AF		 1186 u16 __iomem *temoder_register,
1187 u32 __iomem *remoder_register)
ce973b14
LY		 1188{
1189 /* Note: this function does not check if */
1190 /* the parameters it receives are NULL */
ce973b14
LY		 1191
1192 if (enable_tx_firmware_statistics) {
1193 out_be32(tx_rmon_base_ptr,
1194 tx_firmware_statistics_structure_address);
3bc53427 1195 setbits16(temoder_register, TEMODER_TX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1196 }
1197
1198 if (enable_rx_firmware_statistics) {
1199 out_be32(rx_rmon_base_ptr,
1200 rx_firmware_statistics_structure_address);
3bc53427 1201 setbits32(remoder_register, REMODER_RX_RMON_STATISTICS_ENABLE);
ce973b14
LY		 1202 }
1203
1204 return 0;
1205}
1206
1207static int init_mac_station_addr_regs(u8 address_byte_0,
1208 u8 address_byte_1,
1209 u8 address_byte_2,
1210 u8 address_byte_3,
1211 u8 address_byte_4,
1212 u8 address_byte_5,
6fee40e9
AF		 1213 u32 __iomem *macstnaddr1_register,
1214 u32 __iomem *macstnaddr2_register)
ce973b14
LY		 1215{
1216 u32 value = 0;
1217
1218 /* Example: for a station address of 0x12345678ABCD, */
1219 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1220
1221 /* MACSTNADDR1 Register: */
1222
1223 /* 0 7 8 15 */
1224 /* station address byte 5 station address byte 4 */
1225 /* 16 23 24 31 */
1226 /* station address byte 3 station address byte 2 */
1227 value |= (u32) ((address_byte_2 << 0) & 0x000000FF);
1228 value |= (u32) ((address_byte_3 << 8) & 0x0000FF00);
1229 value |= (u32) ((address_byte_4 << 16) & 0x00FF0000);
1230 value |= (u32) ((address_byte_5 << 24) & 0xFF000000);
1231
1232 out_be32(macstnaddr1_register, value);
1233
1234 /* MACSTNADDR2 Register: */
1235
1236 /* 0 7 8 15 */
1237 /* station address byte 1 station address byte 0 */
1238 /* 16 23 24 31 */
1239 /* reserved reserved */
1240 value = 0;
1241 value |= (u32) ((address_byte_0 << 16) & 0x00FF0000);
1242 value |= (u32) ((address_byte_1 << 24) & 0xFF000000);
1243
1244 out_be32(macstnaddr2_register, value);
1245
1246 return 0;
1247}
1248
ce973b14 1249static int init_check_frame_length_mode(int length_check,
6fee40e9 1250 u32 __iomem *maccfg2_register)
ce973b14
LY		 1251{
1252 u32 value = 0;
1253
1254 value = in_be32(maccfg2_register);
1255
1256 if (length_check)
1257 value |= MACCFG2_LC;
1258 else
1259 value &= ~MACCFG2_LC;
1260
1261 out_be32(maccfg2_register, value);
1262 return 0;
1263}
1264
1265static int init_preamble_length(u8 preamble_length,
6fee40e9 1266 u32 __iomem *maccfg2_register)
ce973b14 1267{
ce973b14
LY		 1268 if ((preamble_length < 3) || (preamble_length > 7))
1269 return -EINVAL;
1270
3bc53427
TT		 1271 clrsetbits_be32(maccfg2_register, MACCFG2_PREL_MASK,
1272 preamble_length << MACCFG2_PREL_SHIFT);
1273
ce973b14
LY		 1274 return 0;
1275}
1276
ce973b14
LY		 1277static int init_rx_parameters(int reject_broadcast,
1278 int receive_short_frames,
6fee40e9 1279 int promiscuous, u32 __iomem *upsmr_register)
ce973b14
LY		 1280{
1281 u32 value = 0;
1282
1283 value = in_be32(upsmr_register);
1284
1285 if (reject_broadcast)
3bc53427 1286 value |= UCC_GETH_UPSMR_BRO;
ce973b14 1287 else
3bc53427 1288 value &= ~UCC_GETH_UPSMR_BRO;
ce973b14
LY		 1289
1290 if (receive_short_frames)
3bc53427 1291 value |= UCC_GETH_UPSMR_RSH;
ce973b14 1292 else
3bc53427 1293 value &= ~UCC_GETH_UPSMR_RSH;
ce973b14
LY		 1294
1295 if (promiscuous)
3bc53427 1296 value |= UCC_GETH_UPSMR_PRO;
ce973b14 1297 else
3bc53427 1298 value &= ~UCC_GETH_UPSMR_PRO;
ce973b14
LY		 1299
1300 out_be32(upsmr_register, value);
1301
1302 return 0;
1303}
1304
1305static int init_max_rx_buff_len(u16 max_rx_buf_len,
6fee40e9 1306 u16 __iomem *mrblr_register)
ce973b14
LY		 1307{
1308 /* max_rx_buf_len value must be a multiple of 128 */
8e95a202
JP		 1309 if ((max_rx_buf_len == 0) ||
1310 (max_rx_buf_len % UCC_GETH_MRBLR_ALIGNMENT))
ce973b14
LY		 1311 return -EINVAL;
1312
1313 out_be16(mrblr_register, max_rx_buf_len);
1314 return 0;
1315}
1316
1317static int init_min_frame_len(u16 min_frame_length,
6fee40e9
AF		 1318 u16 __iomem *minflr_register,
1319 u16 __iomem *mrblr_register)
ce973b14
LY		 1320{
1321 u16 mrblr_value = 0;
1322
1323 mrblr_value = in_be16(mrblr_register);
1324 if (min_frame_length >= (mrblr_value - 4))
1325 return -EINVAL;
1326
1327 out_be16(minflr_register, min_frame_length);
1328 return 0;
1329}
1330
18a8e864 1331static int adjust_enet_interface(struct ucc_geth_private *ugeth)
ce973b14 1332{
18a8e864 1333 struct ucc_geth_info *ug_info;
6fee40e9
AF		 1334 struct ucc_geth __iomem *ug_regs;
1335 struct ucc_fast __iomem *uf_regs;
728de4c9
KP		 1336 int ret_val;
1337 u32 upsmr, maccfg2, tbiBaseAddress;
ce973b14
LY		 1338 u16 value;
1339
b39d66a8 1340 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 1341
1342 ug_info = ugeth->ug_info;
1343 ug_regs = ugeth->ug_regs;
1344 uf_regs = ugeth->uccf->uf_regs;
1345
ce973b14
LY		 1346 /* Set MACCFG2 */
1347 maccfg2 = in_be32(&ug_regs->maccfg2);
1348 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
728de4c9
KP		 1349 if ((ugeth->max_speed == SPEED_10) ||
1350 (ugeth->max_speed == SPEED_100))
ce973b14 1351 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
728de4c9 1352 else if (ugeth->max_speed == SPEED_1000)
ce973b14
LY		 1353 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
1354 maccfg2 |= ug_info->padAndCrc;
1355 out_be32(&ug_regs->maccfg2, maccfg2);
1356
1357 /* Set UPSMR */
1358 upsmr = in_be32(&uf_regs->upsmr);
3bc53427
TT		 1359 upsmr &= ~(UCC_GETH_UPSMR_RPM | UCC_GETH_UPSMR_R10M |
1360 UCC_GETH_UPSMR_TBIM | UCC_GETH_UPSMR_RMM);
728de4c9
KP		 1361 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1362 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1363 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1364 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1365 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9 1366 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
cef309cf
HS		 1367 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RMII)
1368 upsmr |= UCC_GETH_UPSMR_RPM;
728de4c9
KP		 1369 switch (ugeth->max_speed) {
1370 case SPEED_10:
3bc53427 1371 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9
KP		 1372 /* FALLTHROUGH */
1373 case SPEED_100:
1374 if (ugeth->phy_interface != PHY_INTERFACE_MODE_RTBI)
3bc53427 1375 upsmr |= UCC_GETH_UPSMR_RMM;
728de4c9
KP		 1376 }
1377 }
1378 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1379 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
3bc53427 1380 upsmr |= UCC_GETH_UPSMR_TBIM;
728de4c9 1381 }
047584ce
HW		 1382 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_SGMII))
1383 upsmr |= UCC_GETH_UPSMR_SGMM;
1384
ce973b14
LY		 1385 out_be32(&uf_regs->upsmr, upsmr);
1386
ce973b14
LY		 1387 /* Disable autonegotiation in tbi mode, because by default it
1388 comes up in autonegotiation mode. */
1389 /* Note that this depends on proper setting in utbipar register. */
728de4c9
KP		 1390 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_TBI) ||
1391 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
ce973b14
LY		 1392 tbiBaseAddress = in_be32(&ug_regs->utbipar);
1393 tbiBaseAddress &= UTBIPAR_PHY_ADDRESS_MASK;
1394 tbiBaseAddress >>= UTBIPAR_PHY_ADDRESS_SHIFT;
728de4c9
KP		 1395 value = ugeth->phydev->bus->read(ugeth->phydev->bus,
1396 (u8) tbiBaseAddress, ENET_TBI_MII_CR);
ce973b14 1397 value &= ~0x1000; /* Turn off autonegotiation */
728de4c9
KP		 1398 ugeth->phydev->bus->write(ugeth->phydev->bus,
1399 (u8) tbiBaseAddress, ENET_TBI_MII_CR, value);
ce973b14
LY		 1400 }
1401
1402 init_check_frame_length_mode(ug_info->lengthCheckRx, &ug_regs->maccfg2);
1403
1404 ret_val = init_preamble_length(ug_info->prel, &ug_regs->maccfg2);
1405 if (ret_val != 0) {
890de95e
LY		 1406 if (netif_msg_probe(ugeth))
1407 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
b39d66a8 1408 __func__);
ce973b14
LY		 1409 return ret_val;
1410 }
1411
1412 return 0;
1413}
1414
7de8ee78
AV		 1415static int ugeth_graceful_stop_tx(struct ucc_geth_private *ugeth)
1416{
1417 struct ucc_fast_private *uccf;
1418 u32 cecr_subblock;
1419 u32 temp;
1420 int i = 10;
1421
1422 uccf = ugeth->uccf;
1423
1424 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1425 clrbits32(uccf->p_uccm, UCC_GETH_UCCE_GRA);
1426 out_be32(uccf->p_ucce, UCC_GETH_UCCE_GRA); /* clear by writing 1 */
1427
1428 /* Issue host command */
1429 cecr_subblock =
1430 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1431 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
1432 QE_CR_PROTOCOL_ETHERNET, 0);
1433
1434 /* Wait for command to complete */
1435 do {
1436 msleep(10);
1437 temp = in_be32(uccf->p_ucce);
1438 } while (!(temp & UCC_GETH_UCCE_GRA) && --i);
1439
1440 uccf->stopped_tx = 1;
1441
1442 return 0;
1443}
1444
1445static int ugeth_graceful_stop_rx(struct ucc_geth_private *ugeth)
1446{
1447 struct ucc_fast_private *uccf;
1448 u32 cecr_subblock;
1449 u8 temp;
1450 int i = 10;
1451
1452 uccf = ugeth->uccf;
1453
1454 /* Clear acknowledge bit */
1455 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1456 temp &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
1457 out_8(&ugeth->p_rx_glbl_pram->rxgstpack, temp);
1458
1459 /* Keep issuing command and checking acknowledge bit until
1460 it is asserted, according to spec */
1461 do {
1462 /* Issue host command */
1463 cecr_subblock =
1464 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.
1465 ucc_num);
1466 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
1467 QE_CR_PROTOCOL_ETHERNET, 0);
1468 msleep(10);
1469 temp = in_8(&ugeth->p_rx_glbl_pram->rxgstpack);
1470 } while (!(temp & GRACEFUL_STOP_ACKNOWLEDGE_RX) && --i);
1471
1472 uccf->stopped_rx = 1;
1473
1474 return 0;
1475}
1476
1477static int ugeth_restart_tx(struct ucc_geth_private *ugeth)
1478{
1479 struct ucc_fast_private *uccf;
1480 u32 cecr_subblock;
1481
1482 uccf = ugeth->uccf;
1483
1484 cecr_subblock =
1485 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1486 qe_issue_cmd(QE_RESTART_TX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET, 0);
1487 uccf->stopped_tx = 0;
1488
1489 return 0;
1490}
1491
1492static int ugeth_restart_rx(struct ucc_geth_private *ugeth)
1493{
1494 struct ucc_fast_private *uccf;
1495 u32 cecr_subblock;
1496
1497 uccf = ugeth->uccf;
1498
1499 cecr_subblock =
1500 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
1501 qe_issue_cmd(QE_RESTART_RX, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
1502 0);
1503 uccf->stopped_rx = 0;
1504
1505 return 0;
1506}
1507
1508static int ugeth_enable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1509{
1510 struct ucc_fast_private *uccf;
1511 int enabled_tx, enabled_rx;
1512
1513 uccf = ugeth->uccf;
1514
1515 /* check if the UCC number is in range. */
1516 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1517 if (netif_msg_probe(ugeth))
1518 ugeth_err("%s: ucc_num out of range.", __func__);
1519 return -EINVAL;
1520 }
1521
1522 enabled_tx = uccf->enabled_tx;
1523 enabled_rx = uccf->enabled_rx;
1524
1525 /* Get Tx and Rx going again, in case this channel was actively
1526 disabled. */
1527 if ((mode & COMM_DIR_TX) && (!enabled_tx) && uccf->stopped_tx)
1528 ugeth_restart_tx(ugeth);
1529 if ((mode & COMM_DIR_RX) && (!enabled_rx) && uccf->stopped_rx)
1530 ugeth_restart_rx(ugeth);
1531
1532 ucc_fast_enable(uccf, mode); /* OK to do even if not disabled */
1533
1534 return 0;
1535
1536}
1537
1538static int ugeth_disable(struct ucc_geth_private *ugeth, enum comm_dir mode)
1539{
1540 struct ucc_fast_private *uccf;
1541
1542 uccf = ugeth->uccf;
1543
1544 /* check if the UCC number is in range. */
1545 if (ugeth->ug_info->uf_info.ucc_num >= UCC_MAX_NUM) {
1546 if (netif_msg_probe(ugeth))
1547 ugeth_err("%s: ucc_num out of range.", __func__);
1548 return -EINVAL;
1549 }
1550
1551 /* Stop any transmissions */
1552 if ((mode & COMM_DIR_TX) && uccf->enabled_tx && !uccf->stopped_tx)
1553 ugeth_graceful_stop_tx(ugeth);
1554
1555 /* Stop any receptions */
1556 if ((mode & COMM_DIR_RX) && uccf->enabled_rx && !uccf->stopped_rx)
1557 ugeth_graceful_stop_rx(ugeth);
1558
1559 ucc_fast_disable(ugeth->uccf, mode); /* OK to do even if not enabled */
1560
1561 return 0;
1562}
1563
864fdf88
AV		 1564static void ugeth_quiesce(struct ucc_geth_private *ugeth)
1565{
1566 /* Wait for and prevent any further xmits. */
1567 netif_tx_disable(ugeth->ndev);
1568
1569 /* Disable the interrupt to avoid NAPI rescheduling. */
1570 disable_irq(ugeth->ug_info->uf_info.irq);
1571
1572 /* Stop NAPI, and possibly wait for its completion. */
1573 napi_disable(&ugeth->napi);
1574}
1575
1576static void ugeth_activate(struct ucc_geth_private *ugeth)
1577{
1578 napi_enable(&ugeth->napi);
1579 enable_irq(ugeth->ug_info->uf_info.irq);
1580 netif_tx_wake_all_queues(ugeth->ndev);
1581}
1582
ce973b14
LY		 1583/* Called every time the controller might need to be made
1584 * aware of new link state. The PHY code conveys this
1585 * information through variables in the ugeth structure, and this
1586 * function converts those variables into the appropriate
1587 * register values, and can bring down the device if needed.
1588 */
728de4c9 1589
ce973b14
LY		 1590static void adjust_link(struct net_device *dev)
1591{
18a8e864 1592 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9
AF		 1593 struct ucc_geth __iomem *ug_regs;
1594 struct ucc_fast __iomem *uf_regs;
728de4c9 1595 struct phy_device *phydev = ugeth->phydev;
728de4c9 1596 int new_state = 0;
ce973b14
LY		 1597
1598 ug_regs = ugeth->ug_regs;
728de4c9 1599 uf_regs = ugeth->uccf->uf_regs;
ce973b14 1600
728de4c9
KP		 1601 if (phydev->link) {
1602 u32 tempval = in_be32(&ug_regs->maccfg2);
1603 u32 upsmr = in_be32(&uf_regs->upsmr);
ce973b14
LY		 1604 /* Now we make sure that we can be in full duplex mode.
1605 * If not, we operate in half-duplex mode. */
728de4c9
KP		 1606 if (phydev->duplex != ugeth->oldduplex) {
1607 new_state = 1;
1608 if (!(phydev->duplex))
ce973b14 1609 tempval &= ~(MACCFG2_FDX);
728de4c9 1610 else
ce973b14 1611 tempval |= MACCFG2_FDX;
728de4c9 1612 ugeth->oldduplex = phydev->duplex;
ce973b14
LY		 1613 }
1614
728de4c9
KP		 1615 if (phydev->speed != ugeth->oldspeed) {
1616 new_state = 1;
1617 switch (phydev->speed) {
1618 case SPEED_1000:
1619 tempval = ((tempval &
1620 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1621 MACCFG2_INTERFACE_MODE_BYTE);
a1862a53 1622 break;
728de4c9
KP		 1623 case SPEED_100:
1624 case SPEED_10:
1625 tempval = ((tempval &
1626 ~(MACCFG2_INTERFACE_MODE_MASK)) |
1627 MACCFG2_INTERFACE_MODE_NIBBLE);
1628 /* if reduced mode, re-set UPSMR.R10M */
1629 if ((ugeth->phy_interface == PHY_INTERFACE_MODE_RMII) ||
1630 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII) ||
1631 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
bd0ceaab
KP		 1632 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
1633 (ugeth->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) ||
728de4c9
KP		 1634 (ugeth->phy_interface == PHY_INTERFACE_MODE_RTBI)) {
1635 if (phydev->speed == SPEED_10)
3bc53427 1636 upsmr |= UCC_GETH_UPSMR_R10M;
728de4c9 1637 else
3bc53427 1638 upsmr &= ~UCC_GETH_UPSMR_R10M;
728de4c9 1639 }
ce973b14
LY		 1640 break;
1641 default:
728de4c9
KP		 1642 if (netif_msg_link(ugeth))
1643 ugeth_warn(
1644 "%s: Ack! Speed (%d) is not 10/100/1000!",
1645 dev->name, phydev->speed);
ce973b14
LY		 1646 break;
1647 }
728de4c9 1648 ugeth->oldspeed = phydev->speed;
ce973b14
LY		 1649 }
1650
864fdf88
AV		 1651 /*
1652 * To change the MAC configuration we need to disable the
1653 * controller. To do so, we have to either grab ugeth->lock,
1654 * which is a bad idea since 'graceful stop' commands might
1655 * take quite a while, or we can quiesce driver's activity.
1656 */
1657 ugeth_quiesce(ugeth);
1658 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
1659
728de4c9
KP		 1660 out_be32(&ug_regs->maccfg2, tempval);
1661 out_be32(&uf_regs->upsmr, upsmr);
1662
864fdf88
AV		 1663 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
1664 ugeth_activate(ugeth);
1665
ce973b14 1666 if (!ugeth->oldlink) {
728de4c9 1667 new_state = 1;
ce973b14 1668 ugeth->oldlink = 1;
ce973b14 1669 }
728de4c9
KP		 1670 } else if (ugeth->oldlink) {
1671 new_state = 1;
ce973b14
LY		 1672 ugeth->oldlink = 0;
1673 ugeth->oldspeed = 0;
1674 ugeth->oldduplex = -1;
ce973b14 1675 }
728de4c9
KP		 1676
1677 if (new_state && netif_msg_link(ugeth))
1678 phy_print_status(phydev);
ce973b14
LY		 1679}
1680
fb1001f3
HW		 1681/* Initialize TBI PHY interface for communicating with the
1682 * SERDES lynx PHY on the chip. We communicate with this PHY
1683 * through the MDIO bus on each controller, treating it as a
1684 * "normal" PHY at the address found in the UTBIPA register. We assume
1685 * that the UTBIPA register is valid. Either the MDIO bus code will set
1686 * it to a value that doesn't conflict with other PHYs on the bus, or the
1687 * value doesn't matter, as there are no other PHYs on the bus.
1688 */
1689static void uec_configure_serdes(struct net_device *dev)
1690{
1691 struct ucc_geth_private *ugeth = netdev_priv(dev);
1692 struct ucc_geth_info *ug_info = ugeth->ug_info;
1693 struct phy_device *tbiphy;
1694
1695 if (!ug_info->tbi_node) {
1696 dev_warn(&dev->dev, "SGMII mode requires that the device "
1697 "tree specify a tbi-handle\n");
1698 return;
1699 }
1700
1701 tbiphy = of_phy_find_device(ug_info->tbi_node);
1702 if (!tbiphy) {
1703 dev_err(&dev->dev, "error: Could not get TBI device\n");
1704 return;
1705 }
1706
1707 /*
1708 * If the link is already up, we must already be ok, and don't need to
1709 * configure and reset the TBI<->SerDes link. Maybe U-Boot configured
1710 * everything for us? Resetting it takes the link down and requires
1711 * several seconds for it to come back.
1712 */
1713 if (phy_read(tbiphy, ENET_TBI_MII_SR) & TBISR_LSTATUS)
1714 return;
1715
1716 /* Single clk mode, mii mode off(for serdes communication) */
1717 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS);
1718
1719 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
1720
1721 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS);
1722}
1723
ce973b14
LY		 1724/* Configure the PHY for dev.
1725 * returns 0 if success. -1 if failure
1726 */
1727static int init_phy(struct net_device *dev)
1728{
728de4c9 1729 struct ucc_geth_private *priv = netdev_priv(dev);
61fa9dcf 1730 struct ucc_geth_info *ug_info = priv->ug_info;
728de4c9 1731 struct phy_device *phydev;
ce973b14 1732
728de4c9
KP		 1733 priv->oldlink = 0;
1734 priv->oldspeed = 0;
1735 priv->oldduplex = -1;
ce973b14 1736
0b9da337
GL		 1737 phydev = of_phy_connect(dev, ug_info->phy_node, &adjust_link, 0,
1738 priv->phy_interface);
3104a6ff
AV		 1739 if (!phydev)
1740 phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1741 priv->phy_interface);
0b9da337 1742 if (!phydev) {
3104a6ff 1743 dev_err(&dev->dev, "Could not attach to PHY\n");
0b9da337 1744 return -ENODEV;
ce973b14
LY		 1745 }
1746
047584ce
HW		 1747 if (priv->phy_interface == PHY_INTERFACE_MODE_SGMII)
1748 uec_configure_serdes(dev);
1749
728de4c9 1750 phydev->supported &= (ADVERTISED_10baseT_Half |
ce973b14
LY		 1751 ADVERTISED_10baseT_Full |
1752 ADVERTISED_100baseT_Half |
728de4c9 1753 ADVERTISED_100baseT_Full);
ce973b14 1754
728de4c9
KP		 1755 if (priv->max_speed == SPEED_1000)
1756 phydev->supported |= ADVERTISED_1000baseT_Full;
ce973b14 1757
728de4c9 1758 phydev->advertising = phydev->supported;
68dc44af 1759
728de4c9 1760 priv->phydev = phydev;
ce973b14
LY		 1761
1762 return 0;
ce973b14
LY		 1763}
1764
18a8e864 1765static void ugeth_dump_regs(struct ucc_geth_private *ugeth)
ce973b14
LY		 1766{
1767#ifdef DEBUG
1768 ucc_fast_dump_regs(ugeth->uccf);
1769 dump_regs(ugeth);
1770 dump_bds(ugeth);
1771#endif
1772}
1773
18a8e864 1774static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private *
ce973b14 1775 ugeth,
18a8e864 1776 enum enet_addr_type
ce973b14
LY		 1777 enet_addr_type)
1778{
6fee40e9 1779 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
18a8e864
LY		 1780 struct ucc_fast_private *uccf;
1781 enum comm_dir comm_dir;
ce973b14
LY		 1782 struct list_head *p_lh;
1783 u16 i, num;
6fee40e9
AF		 1784 u32 __iomem *addr_h;
1785 u32 __iomem *addr_l;
ce973b14
LY		 1786 u8 *p_counter;
1787
1788 uccf = ugeth->uccf;
1789
1790 p_82xx_addr_filt =
6fee40e9
AF		 1791 (struct ucc_geth_82xx_address_filtering_pram __iomem *)
1792 ugeth->p_rx_glbl_pram->addressfiltering;
ce973b14
LY		 1793
1794 if (enet_addr_type == ENET_ADDR_TYPE_GROUP) {
1795 addr_h = &(p_82xx_addr_filt->gaddr_h);
1796 addr_l = &(p_82xx_addr_filt->gaddr_l);
1797 p_lh = &ugeth->group_hash_q;
1798 p_counter = &(ugeth->numGroupAddrInHash);
1799 } else if (enet_addr_type == ENET_ADDR_TYPE_INDIVIDUAL) {
1800 addr_h = &(p_82xx_addr_filt->iaddr_h);
1801 addr_l = &(p_82xx_addr_filt->iaddr_l);
1802 p_lh = &ugeth->ind_hash_q;
1803 p_counter = &(ugeth->numIndAddrInHash);
1804 } else
1805 return -EINVAL;
1806
1807 comm_dir = 0;
1808 if (uccf->enabled_tx)
1809 comm_dir |= COMM_DIR_TX;
1810 if (uccf->enabled_rx)
1811 comm_dir |= COMM_DIR_RX;
1812 if (comm_dir)
1813 ugeth_disable(ugeth, comm_dir);
1814
1815 /* Clear the hash table. */
1816 out_be32(addr_h, 0x00000000);
1817 out_be32(addr_l, 0x00000000);
1818
1819 if (!p_lh)
1820 return 0;
1821
1822 num = *p_counter;
1823
1824 /* Delete all remaining CQ elements */
1825 for (i = 0; i < num; i++)
1826 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh)));
1827
1828 *p_counter = 0;
1829
1830 if (comm_dir)
1831 ugeth_enable(ugeth, comm_dir);
1832
1833 return 0;
1834}
1835
18a8e864 1836static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private *ugeth,
ce973b14
LY		 1837 u8 paddr_num)
1838{
1839 ugeth->indAddrRegUsed[paddr_num] = 0; /* mark this paddr as not used */
1840 return hw_clear_addr_in_paddr(ugeth, paddr_num);/* clear in hardware */
1841}
1842
18a8e864 1843static void ucc_geth_memclean(struct ucc_geth_private *ugeth)
ce973b14
LY		 1844{
1845 u16 i, j;
6fee40e9 1846 u8 __iomem *bd;
ce973b14
LY		 1847
1848 if (!ugeth)
1849 return;
1850
80a9fad8 1851 if (ugeth->uccf) {
ce973b14 1852 ucc_fast_free(ugeth->uccf);
80a9fad8
AV		 1853 ugeth->uccf = NULL;
1854 }
ce973b14
LY		 1855
1856 if (ugeth->p_thread_data_tx) {
1857 qe_muram_free(ugeth->thread_dat_tx_offset);
1858 ugeth->p_thread_data_tx = NULL;
1859 }
1860 if (ugeth->p_thread_data_rx) {
1861 qe_muram_free(ugeth->thread_dat_rx_offset);
1862 ugeth->p_thread_data_rx = NULL;
1863 }
1864 if (ugeth->p_exf_glbl_param) {
1865 qe_muram_free(ugeth->exf_glbl_param_offset);
1866 ugeth->p_exf_glbl_param = NULL;
1867 }
1868 if (ugeth->p_rx_glbl_pram) {
1869 qe_muram_free(ugeth->rx_glbl_pram_offset);
1870 ugeth->p_rx_glbl_pram = NULL;
1871 }
1872 if (ugeth->p_tx_glbl_pram) {
1873 qe_muram_free(ugeth->tx_glbl_pram_offset);
1874 ugeth->p_tx_glbl_pram = NULL;
1875 }
1876 if (ugeth->p_send_q_mem_reg) {
1877 qe_muram_free(ugeth->send_q_mem_reg_offset);
1878 ugeth->p_send_q_mem_reg = NULL;
1879 }
1880 if (ugeth->p_scheduler) {
1881 qe_muram_free(ugeth->scheduler_offset);
1882 ugeth->p_scheduler = NULL;
1883 }
1884 if (ugeth->p_tx_fw_statistics_pram) {
1885 qe_muram_free(ugeth->tx_fw_statistics_pram_offset);
1886 ugeth->p_tx_fw_statistics_pram = NULL;
1887 }
1888 if (ugeth->p_rx_fw_statistics_pram) {
1889 qe_muram_free(ugeth->rx_fw_statistics_pram_offset);
1890 ugeth->p_rx_fw_statistics_pram = NULL;
1891 }
1892 if (ugeth->p_rx_irq_coalescing_tbl) {
1893 qe_muram_free(ugeth->rx_irq_coalescing_tbl_offset);
1894 ugeth->p_rx_irq_coalescing_tbl = NULL;
1895 }
1896 if (ugeth->p_rx_bd_qs_tbl) {
1897 qe_muram_free(ugeth->rx_bd_qs_tbl_offset);
1898 ugeth->p_rx_bd_qs_tbl = NULL;
1899 }
1900 if (ugeth->p_init_enet_param_shadow) {
1901 return_init_enet_entries(ugeth,
1902 &(ugeth->p_init_enet_param_shadow->
1903 rxthread[0]),
1904 ENET_INIT_PARAM_MAX_ENTRIES_RX,
1905 ugeth->ug_info->riscRx, 1);
1906 return_init_enet_entries(ugeth,
1907 &(ugeth->p_init_enet_param_shadow->
1908 txthread[0]),
1909 ENET_INIT_PARAM_MAX_ENTRIES_TX,
1910 ugeth->ug_info->riscTx, 0);
1911 kfree(ugeth->p_init_enet_param_shadow);
1912 ugeth->p_init_enet_param_shadow = NULL;
1913 }
1914 for (i = 0; i < ugeth->ug_info->numQueuesTx; i++) {
1915 bd = ugeth->p_tx_bd_ring[i];
3a8205ea
NIP		 1916 if (!bd)
1917 continue;
ce973b14
LY		 1918 for (j = 0; j < ugeth->ug_info->bdRingLenTx[i]; j++) {
1919 if (ugeth->tx_skbuff[i][j]) {
da1aa63e 1920 dma_unmap_single(ugeth->dev,
6fee40e9
AF		 1921 in_be32(&((struct qe_bd __iomem *)bd)->buf),
1922 (in_be32((u32 __iomem *)bd) &
ce973b14
LY		 1923 BD_LENGTH_MASK),
1924 DMA_TO_DEVICE);
1925 dev_kfree_skb_any(ugeth->tx_skbuff[i][j]);
1926 ugeth->tx_skbuff[i][j] = NULL;
1927 }
1928 }
1929
1930 kfree(ugeth->tx_skbuff[i]);
1931
1932 if (ugeth->p_tx_bd_ring[i]) {
1933 if (ugeth->ug_info->uf_info.bd_mem_part ==
1934 MEM_PART_SYSTEM)
1935 kfree((void *)ugeth->tx_bd_ring_offset[i]);
1936 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1937 MEM_PART_MURAM)
1938 qe_muram_free(ugeth->tx_bd_ring_offset[i]);
1939 ugeth->p_tx_bd_ring[i] = NULL;
1940 }
1941 }
1942 for (i = 0; i < ugeth->ug_info->numQueuesRx; i++) {
1943 if (ugeth->p_rx_bd_ring[i]) {
1944 /* Return existing data buffers in ring */
1945 bd = ugeth->p_rx_bd_ring[i];
1946 for (j = 0; j < ugeth->ug_info->bdRingLenRx[i]; j++) {
1947 if (ugeth->rx_skbuff[i][j]) {
da1aa63e 1948 dma_unmap_single(ugeth->dev,
6fee40e9 1949 in_be32(&((struct qe_bd __iomem *)bd)->buf),
18a8e864
LY		 1950 ugeth->ug_info->
1951 uf_info.max_rx_buf_length +
1952 UCC_GETH_RX_DATA_BUF_ALIGNMENT,
1953 DMA_FROM_DEVICE);
1954 dev_kfree_skb_any(
1955 ugeth->rx_skbuff[i][j]);
ce973b14
LY		 1956 ugeth->rx_skbuff[i][j] = NULL;
1957 }
18a8e864 1958 bd += sizeof(struct qe_bd);
ce973b14
LY		 1959 }
1960
1961 kfree(ugeth->rx_skbuff[i]);
1962
1963 if (ugeth->ug_info->uf_info.bd_mem_part ==
1964 MEM_PART_SYSTEM)
1965 kfree((void *)ugeth->rx_bd_ring_offset[i]);
1966 else if (ugeth->ug_info->uf_info.bd_mem_part ==
1967 MEM_PART_MURAM)
1968 qe_muram_free(ugeth->rx_bd_ring_offset[i]);
1969 ugeth->p_rx_bd_ring[i] = NULL;
1970 }
1971 }
1972 while (!list_empty(&ugeth->group_hash_q))
1973 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1974 (dequeue(&ugeth->group_hash_q)));
1975 while (!list_empty(&ugeth->ind_hash_q))
1976 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
1977 (dequeue(&ugeth->ind_hash_q)));
3e73fc9a
AV		 1978 if (ugeth->ug_regs) {
1979 iounmap(ugeth->ug_regs);
1980 ugeth->ug_regs = NULL;
1981 }
50f238fd
AV		 1982
1983 skb_queue_purge(&ugeth->rx_recycle);
ce973b14
LY		 1984}
1985
1986static void ucc_geth_set_multi(struct net_device *dev)
1987{
18a8e864 1988 struct ucc_geth_private *ugeth;
ce973b14 1989 struct dev_mc_list *dmi;
6fee40e9
AF		 1990 struct ucc_fast __iomem *uf_regs;
1991 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
9030b3dd 1992 int i;
ce973b14
LY		 1993
1994 ugeth = netdev_priv(dev);
1995
1996 uf_regs = ugeth->uccf->uf_regs;
1997
1998 if (dev->flags & IFF_PROMISC) {
3bc53427 1999 setbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14 2000 } else {
3bc53427 2001 clrbits32(&uf_regs->upsmr, UCC_GETH_UPSMR_PRO);
ce973b14
LY		 2002
2003 p_82xx_addr_filt =
6fee40e9 2004 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2005 p_rx_glbl_pram->addressfiltering;
2006
2007 if (dev->flags & IFF_ALLMULTI) {
2008 /* Catch all multicast addresses, so set the
2009 * filter to all 1's.
2010 */
2011 out_be32(&p_82xx_addr_filt->gaddr_h, 0xffffffff);
2012 out_be32(&p_82xx_addr_filt->gaddr_l, 0xffffffff);
2013 } else {
2014 /* Clear filter and add the addresses in the list.
2015 */
2016 out_be32(&p_82xx_addr_filt->gaddr_h, 0x0);
2017 out_be32(&p_82xx_addr_filt->gaddr_l, 0x0);
2018
2019 dmi = dev->mc_list;
2020
2021 for (i = 0; i < dev->mc_count; i++, dmi = dmi->next) {
2022
2023 /* Only support group multicast for now.
2024 */
2025 if (!(dmi->dmi_addr[0] & 1))
2026 continue;
2027
ce973b14
LY		 2028 /* Ask CPM to run CRC and set bit in
2029 * filter mask.
2030 */
9030b3dd 2031 hw_add_addr_in_hash(ugeth, dmi->dmi_addr);
ce973b14
LY		 2032 }
2033 }
2034 }
2035}
2036
18a8e864 2037static void ucc_geth_stop(struct ucc_geth_private *ugeth)
ce973b14 2038{
6fee40e9 2039 struct ucc_geth __iomem *ug_regs = ugeth->ug_regs;
728de4c9 2040 struct phy_device *phydev = ugeth->phydev;
ce973b14 2041
b39d66a8 2042 ugeth_vdbg("%s: IN", __func__);
ce973b14
LY		 2043
2044 /* Disable the controller */
2045 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
2046
2047 /* Tell the kernel the link is down */
728de4c9 2048 phy_stop(phydev);
ce973b14
LY		 2049
2050 /* Mask all interrupts */
c6f5047b 2051 out_be32(ugeth->uccf->p_uccm, 0x00000000);
ce973b14
LY		 2052
2053 /* Clear all interrupts */
2054 out_be32(ugeth->uccf->p_ucce, 0xffffffff);
2055
2056 /* Disable Rx and Tx */
3bc53427 2057 clrbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14 2058
79675900
AV		 2059 phy_disconnect(ugeth->phydev);
2060 ugeth->phydev = NULL;
2061
ce973b14
LY		 2062 ucc_geth_memclean(ugeth);
2063}
2064
728de4c9 2065static int ucc_struct_init(struct ucc_geth_private *ugeth)
ce973b14 2066{
18a8e864
LY		 2067 struct ucc_geth_info *ug_info;
2068 struct ucc_fast_info *uf_info;
728de4c9 2069 int i;
ce973b14
LY		 2070
2071 ug_info = ugeth->ug_info;
2072 uf_info = &ug_info->uf_info;
2073
2074 if (!((uf_info->bd_mem_part == MEM_PART_SYSTEM) ||
2075 (uf_info->bd_mem_part == MEM_PART_MURAM))) {
890de95e
LY		 2076 if (netif_msg_probe(ugeth))
2077 ugeth_err("%s: Bad memory partition value.",
b39d66a8 2078 __func__);
ce973b14
LY		 2079 return -EINVAL;
2080 }
2081
2082 /* Rx BD lengths */
2083 for (i = 0; i < ug_info->numQueuesRx; i++) {
2084 if ((ug_info->bdRingLenRx[i] < UCC_GETH_RX_BD_RING_SIZE_MIN) ||
2085 (ug_info->bdRingLenRx[i] %
2086 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT)) {
890de95e
LY		 2087 if (netif_msg_probe(ugeth))
2088 ugeth_err
2089 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
b39d66a8 2090 __func__);
ce973b14
LY		 2091 return -EINVAL;
2092 }
2093 }
2094
2095 /* Tx BD lengths */
2096 for (i = 0; i < ug_info->numQueuesTx; i++) {
2097 if (ug_info->bdRingLenTx[i] < UCC_GETH_TX_BD_RING_SIZE_MIN) {
890de95e
LY		 2098 if (netif_msg_probe(ugeth))
2099 ugeth_err
2100 ("%s: Tx BD ring length must be no smaller than 2.",
b39d66a8 2101 __func__);
ce973b14
LY		 2102 return -EINVAL;
2103 }
2104 }
2105
2106 /* mrblr */
2107 if ((uf_info->max_rx_buf_length == 0) ||
2108 (uf_info->max_rx_buf_length % UCC_GETH_MRBLR_ALIGNMENT)) {
890de95e
LY		 2109 if (netif_msg_probe(ugeth))
2110 ugeth_err
2111 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
b39d66a8 2112 __func__);
ce973b14
LY		 2113 return -EINVAL;
2114 }
2115
2116 /* num Tx queues */
2117 if (ug_info->numQueuesTx > NUM_TX_QUEUES) {
890de95e 2118 if (netif_msg_probe(ugeth))
b39d66a8 2119 ugeth_err("%s: number of tx queues too large.", __func__);
ce973b14
LY		 2120 return -EINVAL;
2121 }
2122
2123 /* num Rx queues */
2124 if (ug_info->numQueuesRx > NUM_RX_QUEUES) {
890de95e 2125 if (netif_msg_probe(ugeth))
b39d66a8 2126 ugeth_err("%s: number of rx queues too large.", __func__);
ce973b14
LY		 2127 return -EINVAL;
2128 }
2129
2130 /* l2qt */
2131 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++) {
2132 if (ug_info->l2qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2133 if (netif_msg_probe(ugeth))
2134 ugeth_err
2135 ("%s: VLAN priority table entry must not be"
2136 " larger than number of Rx queues.",
b39d66a8 2137 __func__);
ce973b14
LY		 2138 return -EINVAL;
2139 }
2140 }
2141
2142 /* l3qt */
2143 for (i = 0; i < UCC_GETH_IP_PRIORITY_MAX; i++) {
2144 if (ug_info->l3qt[i] >= ug_info->numQueuesRx) {
890de95e
LY		 2145 if (netif_msg_probe(ugeth))
2146 ugeth_err
2147 ("%s: IP priority table entry must not be"
2148 " larger than number of Rx queues.",
b39d66a8 2149 __func__);
ce973b14
LY		 2150 return -EINVAL;
2151 }
2152 }
2153
2154 if (ug_info->cam && !ug_info->ecamptr) {
890de95e
LY		 2155 if (netif_msg_probe(ugeth))
2156 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
b39d66a8 2157 __func__);
ce973b14
LY		 2158 return -EINVAL;
2159 }
2160
2161 if ((ug_info->numStationAddresses !=
8e95a202
JP		 2162 UCC_GETH_NUM_OF_STATION_ADDRESSES_1) &&
2163 ug_info->rxExtendedFiltering) {
890de95e
LY		 2164 if (netif_msg_probe(ugeth))
2165 ugeth_err("%s: Number of station addresses greater than 1 "
2166 "not allowed in extended parsing mode.",
b39d66a8 2167 __func__);
ce973b14
LY		 2168 return -EINVAL;
2169 }
2170
2171 /* Generate uccm_mask for receive */
2172 uf_info->uccm_mask = ug_info->eventRegMask & UCCE_OTHER;/* Errors */
2173 for (i = 0; i < ug_info->numQueuesRx; i++)
3bc53427 2174 uf_info->uccm_mask |= (UCC_GETH_UCCE_RXF0 << i);
ce973b14
LY		 2175
2176 for (i = 0; i < ug_info->numQueuesTx; i++)
3bc53427 2177 uf_info->uccm_mask |= (UCC_GETH_UCCE_TXB0 << i);
ce973b14 2178 /* Initialize the general fast UCC block. */
728de4c9 2179 if (ucc_fast_init(uf_info, &ugeth->uccf)) {
890de95e 2180 if (netif_msg_probe(ugeth))
b39d66a8 2181 ugeth_err("%s: Failed to init uccf.", __func__);
ce973b14
LY		 2182 return -ENOMEM;
2183 }
728de4c9 2184
345f8422
HW		 2185 /* read the number of risc engines, update the riscTx and riscRx
2186 * if there are 4 riscs in QE
2187 */
2188 if (qe_get_num_of_risc() == 4) {
2189 ug_info->riscTx = QE_RISC_ALLOCATION_FOUR_RISCS;
2190 ug_info->riscRx = QE_RISC_ALLOCATION_FOUR_RISCS;
2191 }
2192
3e73fc9a
AV		 2193 ugeth->ug_regs = ioremap(uf_info->regs, sizeof(*ugeth->ug_regs));
2194 if (!ugeth->ug_regs) {
2195 if (netif_msg_probe(ugeth))
2196 ugeth_err("%s: Failed to ioremap regs.", __func__);
2197 return -ENOMEM;
2198 }
728de4c9 2199
50f238fd
AV		 2200 skb_queue_head_init(&ugeth->rx_recycle);
2201
728de4c9
KP		 2202 return 0;
2203}
2204
2205static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2206{
6fee40e9
AF		 2207 struct ucc_geth_82xx_address_filtering_pram __iomem *p_82xx_addr_filt;
2208 struct ucc_geth_init_pram __iomem *p_init_enet_pram;
728de4c9
KP		 2209 struct ucc_fast_private *uccf;
2210 struct ucc_geth_info *ug_info;
2211 struct ucc_fast_info *uf_info;
6fee40e9
AF		 2212 struct ucc_fast __iomem *uf_regs;
2213 struct ucc_geth __iomem *ug_regs;
728de4c9
KP		 2214 int ret_val = -EINVAL;
2215 u32 remoder = UCC_GETH_REMODER_INIT;
3bc53427 2216 u32 init_enet_pram_offset, cecr_subblock, command;
728de4c9
KP		 2217 u32 ifstat, i, j, size, l2qt, l3qt, length;
2218 u16 temoder = UCC_GETH_TEMODER_INIT;
2219 u16 test;
2220 u8 function_code = 0;
6fee40e9
AF		 2221 u8 __iomem *bd;
2222 u8 __iomem *endOfRing;
728de4c9
KP		 2223 u8 numThreadsRxNumerical, numThreadsTxNumerical;
2224
b39d66a8 2225 ugeth_vdbg("%s: IN", __func__);
728de4c9
KP		 2226 uccf = ugeth->uccf;
2227 ug_info = ugeth->ug_info;
2228 uf_info = &ug_info->uf_info;
2229 uf_regs = uccf->uf_regs;
2230 ug_regs = ugeth->ug_regs;
ce973b14
LY		 2231
2232 switch (ug_info->numThreadsRx) {
2233 case UCC_GETH_NUM_OF_THREADS_1:
2234 numThreadsRxNumerical = 1;
2235 break;
2236 case UCC_GETH_NUM_OF_THREADS_2:
2237 numThreadsRxNumerical = 2;
2238 break;
2239 case UCC_GETH_NUM_OF_THREADS_4:
2240 numThreadsRxNumerical = 4;
2241 break;
2242 case UCC_GETH_NUM_OF_THREADS_6:
2243 numThreadsRxNumerical = 6;
2244 break;
2245 case UCC_GETH_NUM_OF_THREADS_8:
2246 numThreadsRxNumerical = 8;
2247 break;
2248 default:
890de95e
LY		 2249 if (netif_msg_ifup(ugeth))
2250 ugeth_err("%s: Bad number of Rx threads value.",
b39d66a8 2251 __func__);
ce973b14
LY		 2252 return -EINVAL;
2253 break;
2254 }
2255
2256 switch (ug_info->numThreadsTx) {
2257 case UCC_GETH_NUM_OF_THREADS_1:
2258 numThreadsTxNumerical = 1;
2259 break;
2260 case UCC_GETH_NUM_OF_THREADS_2:
2261 numThreadsTxNumerical = 2;
2262 break;
2263 case UCC_GETH_NUM_OF_THREADS_4:
2264 numThreadsTxNumerical = 4;
2265 break;
2266 case UCC_GETH_NUM_OF_THREADS_6:
2267 numThreadsTxNumerical = 6;
2268 break;
2269 case UCC_GETH_NUM_OF_THREADS_8:
2270 numThreadsTxNumerical = 8;
2271 break;
2272 default:
890de95e
LY		 2273 if (netif_msg_ifup(ugeth))
2274 ugeth_err("%s: Bad number of Tx threads value.",
b39d66a8 2275 __func__);
ce973b14
LY		 2276 return -EINVAL;
2277 break;
2278 }
2279
2280 /* Calculate rx_extended_features */
2281 ugeth->rx_non_dynamic_extended_features = ug_info->ipCheckSumCheck ||
2282 ug_info->ipAddressAlignment ||
2283 (ug_info->numStationAddresses !=
2284 UCC_GETH_NUM_OF_STATION_ADDRESSES_1);
2285
2286 ugeth->rx_extended_features = ugeth->rx_non_dynamic_extended_features ||
8e95a202
JP		 2287 (ug_info->vlanOperationTagged != UCC_GETH_VLAN_OPERATION_TAGGED_NOP) ||
2288 (ug_info->vlanOperationNonTagged !=
2289 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP);
ce973b14 2290
ce973b14
LY		 2291 init_default_reg_vals(&uf_regs->upsmr,
2292 &ug_regs->maccfg1, &ug_regs->maccfg2);
2293
2294 /* Set UPSMR */
2295 /* For more details see the hardware spec. */
2296 init_rx_parameters(ug_info->bro,
2297 ug_info->rsh, ug_info->pro, &uf_regs->upsmr);
2298
2299 /* We're going to ignore other registers for now, */
2300 /* except as needed to get up and running */
2301
2302 /* Set MACCFG1 */
2303 /* For more details see the hardware spec. */
2304 init_flow_control_params(ug_info->aufc,
2305 ug_info->receiveFlowControl,
ac421852 2306 ug_info->transmitFlowControl,
ce973b14
LY		 2307 ug_info->pausePeriod,
2308 ug_info->extensionField,
2309 &uf_regs->upsmr,
2310 &ug_regs->uempr, &ug_regs->maccfg1);
2311
3bc53427 2312 setbits32(&ug_regs->maccfg1, MACCFG1_ENABLE_RX | MACCFG1_ENABLE_TX);
ce973b14
LY		 2313
2314 /* Set IPGIFG */
2315 /* For more details see the hardware spec. */
2316 ret_val = init_inter_frame_gap_params(ug_info->nonBackToBackIfgPart1,
2317 ug_info->nonBackToBackIfgPart2,
2318 ug_info->
2319 miminumInterFrameGapEnforcement,
2320 ug_info->backToBackInterFrameGap,
2321 &ug_regs->ipgifg);
2322 if (ret_val != 0) {
890de95e
LY		 2323 if (netif_msg_ifup(ugeth))
2324 ugeth_err("%s: IPGIFG initialization parameter too large.",
b39d66a8 2325 __func__);
ce973b14
LY		 2326 return ret_val;
2327 }
2328
2329 /* Set HAFDUP */
2330 /* For more details see the hardware spec. */
2331 ret_val = init_half_duplex_params(ug_info->altBeb,
2332 ug_info->backPressureNoBackoff,
2333 ug_info->noBackoff,
2334 ug_info->excessDefer,
2335 ug_info->altBebTruncation,
2336 ug_info->maxRetransmission,
2337 ug_info->collisionWindow,
2338 &ug_regs->hafdup);
2339 if (ret_val != 0) {
890de95e
LY		 2340 if (netif_msg_ifup(ugeth))
2341 ugeth_err("%s: Half Duplex initialization parameter too large.",
b39d66a8 2342 __func__);
ce973b14
LY		 2343 return ret_val;
2344 }
2345
2346 /* Set IFSTAT */
2347 /* For more details see the hardware spec. */
2348 /* Read only - resets upon read */
2349 ifstat = in_be32(&ug_regs->ifstat);
2350
2351 /* Clear UEMPR */
2352 /* For more details see the hardware spec. */
2353 out_be32(&ug_regs->uempr, 0);
2354
2355 /* Set UESCR */
2356 /* For more details see the hardware spec. */
2357 init_hw_statistics_gathering_mode((ug_info->statisticsMode &
2358 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE),
2359 0, &uf_regs->upsmr, &ug_regs->uescr);
2360
2361 /* Allocate Tx bds */
2362 for (j = 0; j < ug_info->numQueuesTx; j++) {
2363 /* Allocate in multiple of
2364 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2365 according to spec */
18a8e864 2366 length = ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd))
ce973b14
LY		 2367 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2368 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
18a8e864 2369 if ((ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)) %
ce973b14
LY		 2370 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
2371 length += UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
2372 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2373 u32 align = 4;
2374 if (UCC_GETH_TX_BD_RING_ALIGNMENT > 4)
2375 align = UCC_GETH_TX_BD_RING_ALIGNMENT;
2376 ugeth->tx_bd_ring_offset[j] =
6fee40e9 2377 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
04b588d7 2378
ce973b14
LY		 2379 if (ugeth->tx_bd_ring_offset[j] != 0)
2380 ugeth->p_tx_bd_ring[j] =
6fee40e9 2381 (u8 __iomem *)((ugeth->tx_bd_ring_offset[j] +
ce973b14
LY		 2382 align) & ~(align - 1));
2383 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2384 ugeth->tx_bd_ring_offset[j] =
2385 qe_muram_alloc(length,
2386 UCC_GETH_TX_BD_RING_ALIGNMENT);
4c35630c 2387 if (!IS_ERR_VALUE(ugeth->tx_bd_ring_offset[j]))
ce973b14 2388 ugeth->p_tx_bd_ring[j] =
6fee40e9 2389 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2390 tx_bd_ring_offset[j]);
2391 }
2392 if (!ugeth->p_tx_bd_ring[j]) {
890de95e
LY		 2393 if (netif_msg_ifup(ugeth))
2394 ugeth_err
2395 ("%s: Can not allocate memory for Tx bd rings.",
b39d66a8 2396 __func__);
ce973b14
LY		 2397 return -ENOMEM;
2398 }
2399 /* Zero unused end of bd ring, according to spec */
6fee40e9
AF		 2400 memset_io((void __iomem *)(ugeth->p_tx_bd_ring[j] +
2401 ug_info->bdRingLenTx[j] * sizeof(struct qe_bd)), 0,
18a8e864 2402 length - ug_info->bdRingLenTx[j] * sizeof(struct qe_bd));
ce973b14
LY		 2403 }
2404
2405 /* Allocate Rx bds */
2406 for (j = 0; j < ug_info->numQueuesRx; j++) {
18a8e864 2407 length = ug_info->bdRingLenRx[j] * sizeof(struct qe_bd);
ce973b14
LY		 2408 if (uf_info->bd_mem_part == MEM_PART_SYSTEM) {
2409 u32 align = 4;
2410 if (UCC_GETH_RX_BD_RING_ALIGNMENT > 4)
2411 align = UCC_GETH_RX_BD_RING_ALIGNMENT;
2412 ugeth->rx_bd_ring_offset[j] =
6fee40e9 2413 (u32) kmalloc((u32) (length + align), GFP_KERNEL);
ce973b14
LY		 2414 if (ugeth->rx_bd_ring_offset[j] != 0)
2415 ugeth->p_rx_bd_ring[j] =
6fee40e9 2416 (u8 __iomem *)((ugeth->rx_bd_ring_offset[j] +
ce973b14
LY		 2417 align) & ~(align - 1));
2418 } else if (uf_info->bd_mem_part == MEM_PART_MURAM) {
2419 ugeth->rx_bd_ring_offset[j] =
2420 qe_muram_alloc(length,
2421 UCC_GETH_RX_BD_RING_ALIGNMENT);
4c35630c 2422 if (!IS_ERR_VALUE(ugeth->rx_bd_ring_offset[j]))
ce973b14 2423 ugeth->p_rx_bd_ring[j] =
6fee40e9 2424 (u8 __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2425 rx_bd_ring_offset[j]);
2426 }
2427 if (!ugeth->p_rx_bd_ring[j]) {
890de95e
LY		 2428 if (netif_msg_ifup(ugeth))
2429 ugeth_err
2430 ("%s: Can not allocate memory for Rx bd rings.",
b39d66a8 2431 __func__);
ce973b14
LY		 2432 return -ENOMEM;
2433 }
2434 }
2435
2436 /* Init Tx bds */
2437 for (j = 0; j < ug_info->numQueuesTx; j++) {
2438 /* Setup the skbuff rings */
04b588d7
AD		 2439 ugeth->tx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2440 ugeth->ug_info->bdRingLenTx[j],
2441 GFP_KERNEL);
ce973b14
LY		 2442
2443 if (ugeth->tx_skbuff[j] == NULL) {
890de95e
LY		 2444 if (netif_msg_ifup(ugeth))
2445 ugeth_err("%s: Could not allocate tx_skbuff",
b39d66a8 2446 __func__);
ce973b14
LY		 2447 return -ENOMEM;
2448 }
2449
2450 for (i = 0; i < ugeth->ug_info->bdRingLenTx[j]; i++)
2451 ugeth->tx_skbuff[j][i] = NULL;
2452
2453 ugeth->skb_curtx[j] = ugeth->skb_dirtytx[j] = 0;
2454 bd = ugeth->confBd[j] = ugeth->txBd[j] = ugeth->p_tx_bd_ring[j];
2455 for (i = 0; i < ug_info->bdRingLenTx[j]; i++) {
18a8e864 2456 /* clear bd buffer */
6fee40e9 2457 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2458 /* set bd status and length */
6fee40e9 2459 out_be32((u32 __iomem *)bd, 0);
18a8e864 2460 bd += sizeof(struct qe_bd);
ce973b14 2461 }
18a8e864
LY		 2462 bd -= sizeof(struct qe_bd);
2463 /* set bd status and length */
6fee40e9 2464 out_be32((u32 __iomem *)bd, T_W); /* for last BD set Wrap bit */
ce973b14
LY		 2465 }
2466
2467 /* Init Rx bds */
2468 for (j = 0; j < ug_info->numQueuesRx; j++) {
2469 /* Setup the skbuff rings */
04b588d7
AD		 2470 ugeth->rx_skbuff[j] = kmalloc(sizeof(struct sk_buff *) *
2471 ugeth->ug_info->bdRingLenRx[j],
2472 GFP_KERNEL);
ce973b14
LY		 2473
2474 if (ugeth->rx_skbuff[j] == NULL) {
890de95e
LY		 2475 if (netif_msg_ifup(ugeth))
2476 ugeth_err("%s: Could not allocate rx_skbuff",
b39d66a8 2477 __func__);
ce973b14
LY		 2478 return -ENOMEM;
2479 }
2480
2481 for (i = 0; i < ugeth->ug_info->bdRingLenRx[j]; i++)
2482 ugeth->rx_skbuff[j][i] = NULL;
2483
2484 ugeth->skb_currx[j] = 0;
2485 bd = ugeth->rxBd[j] = ugeth->p_rx_bd_ring[j];
2486 for (i = 0; i < ug_info->bdRingLenRx[j]; i++) {
18a8e864 2487 /* set bd status and length */
6fee40e9 2488 out_be32((u32 __iomem *)bd, R_I);
18a8e864 2489 /* clear bd buffer */
6fee40e9 2490 out_be32(&((struct qe_bd __iomem *)bd)->buf, 0);
18a8e864 2491 bd += sizeof(struct qe_bd);
ce973b14 2492 }
18a8e864
LY		 2493 bd -= sizeof(struct qe_bd);
2494 /* set bd status and length */
6fee40e9 2495 out_be32((u32 __iomem *)bd, R_W); /* for last BD set Wrap bit */
ce973b14
LY		 2496 }
2497
2498 /*
2499 * Global PRAM
2500 */
2501 /* Tx global PRAM */
2502 /* Allocate global tx parameter RAM page */
2503 ugeth->tx_glbl_pram_offset =
18a8e864 2504 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram),
ce973b14 2505 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2506 if (IS_ERR_VALUE(ugeth->tx_glbl_pram_offset)) {
890de95e
LY		 2507 if (netif_msg_ifup(ugeth))
2508 ugeth_err
2509 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
b39d66a8 2510 __func__);
ce973b14
LY		 2511 return -ENOMEM;
2512 }
2513 ugeth->p_tx_glbl_pram =
6fee40e9 2514 (struct ucc_geth_tx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2515 tx_glbl_pram_offset);
2516 /* Zero out p_tx_glbl_pram */
6fee40e9 2517 memset_io((void __iomem *)ugeth->p_tx_glbl_pram, 0, sizeof(struct ucc_geth_tx_global_pram));
ce973b14
LY		 2518
2519 /* Fill global PRAM */
2520
2521 /* TQPTR */
2522 /* Size varies with number of Tx threads */
2523 ugeth->thread_dat_tx_offset =
2524 qe_muram_alloc(numThreadsTxNumerical *
18a8e864 2525 sizeof(struct ucc_geth_thread_data_tx) +
ce973b14
LY		 2526 32 * (numThreadsTxNumerical == 1),
2527 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2528 if (IS_ERR_VALUE(ugeth->thread_dat_tx_offset)) {
890de95e
LY		 2529 if (netif_msg_ifup(ugeth))
2530 ugeth_err
2531 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
b39d66a8 2532 __func__);
ce973b14
LY		 2533 return -ENOMEM;
2534 }
2535
2536 ugeth->p_thread_data_tx =
6fee40e9 2537 (struct ucc_geth_thread_data_tx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2538 thread_dat_tx_offset);
2539 out_be32(&ugeth->p_tx_glbl_pram->tqptr, ugeth->thread_dat_tx_offset);
2540
2541 /* vtagtable */
2542 for (i = 0; i < UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX; i++)
2543 out_be32(&ugeth->p_tx_glbl_pram->vtagtable[i],
2544 ug_info->vtagtable[i]);
2545
2546 /* iphoffset */
2547 for (i = 0; i < TX_IP_OFFSET_ENTRY_MAX; i++)
6fee40e9
AF		 2548 out_8(&ugeth->p_tx_glbl_pram->iphoffset[i],
2549 ug_info->iphoffset[i]);
ce973b14
LY		 2550
2551 /* SQPTR */
2552 /* Size varies with number of Tx queues */
2553 ugeth->send_q_mem_reg_offset =
2554 qe_muram_alloc(ug_info->numQueuesTx *
18a8e864 2555 sizeof(struct ucc_geth_send_queue_qd),
ce973b14 2556 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
4c35630c 2557 if (IS_ERR_VALUE(ugeth->send_q_mem_reg_offset)) {
890de95e
LY		 2558 if (netif_msg_ifup(ugeth))
2559 ugeth_err
2560 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
b39d66a8 2561 __func__);
ce973b14
LY		 2562 return -ENOMEM;
2563 }
2564
2565 ugeth->p_send_q_mem_reg =
6fee40e9 2566 (struct ucc_geth_send_queue_mem_region __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2567 send_q_mem_reg_offset);
2568 out_be32(&ugeth->p_tx_glbl_pram->sqptr, ugeth->send_q_mem_reg_offset);
2569
2570 /* Setup the table */
2571 /* Assume BD rings are already established */
2572 for (i = 0; i < ug_info->numQueuesTx; i++) {
2573 endOfRing =
2574 ugeth->p_tx_bd_ring[i] + (ug_info->bdRingLenTx[i] -
18a8e864 2575 1) * sizeof(struct qe_bd);
ce973b14
LY		 2576 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2577 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2578 (u32) virt_to_phys(ugeth->p_tx_bd_ring[i]));
2579 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2580 last_bd_completed_address,
2581 (u32) virt_to_phys(endOfRing));
2582 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2583 MEM_PART_MURAM) {
2584 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].bd_ring_base,
2585 (u32) immrbar_virt_to_phys(ugeth->
2586 p_tx_bd_ring[i]));
2587 out_be32(&ugeth->p_send_q_mem_reg->sqqd[i].
2588 last_bd_completed_address,
2589 (u32) immrbar_virt_to_phys(endOfRing));
2590 }
2591 }
2592
2593 /* schedulerbasepointer */
2594
2595 if (ug_info->numQueuesTx > 1) {
2596 /* scheduler exists only if more than 1 tx queue */
2597 ugeth->scheduler_offset =
18a8e864 2598 qe_muram_alloc(sizeof(struct ucc_geth_scheduler),
ce973b14 2599 UCC_GETH_SCHEDULER_ALIGNMENT);
4c35630c 2600 if (IS_ERR_VALUE(ugeth->scheduler_offset)) {
890de95e
LY		 2601 if (netif_msg_ifup(ugeth))
2602 ugeth_err
2603 ("%s: Can not allocate DPRAM memory for p_scheduler.",
b39d66a8 2604 __func__);
ce973b14
LY		 2605 return -ENOMEM;
2606 }
2607
2608 ugeth->p_scheduler =
6fee40e9 2609 (struct ucc_geth_scheduler __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2610 scheduler_offset);
2611 out_be32(&ugeth->p_tx_glbl_pram->schedulerbasepointer,
2612 ugeth->scheduler_offset);
2613 /* Zero out p_scheduler */
6fee40e9 2614 memset_io((void __iomem *)ugeth->p_scheduler, 0, sizeof(struct ucc_geth_scheduler));
ce973b14
LY		 2615
2616 /* Set values in scheduler */
2617 out_be32(&ugeth->p_scheduler->mblinterval,
2618 ug_info->mblinterval);
2619 out_be16(&ugeth->p_scheduler->nortsrbytetime,
2620 ug_info->nortsrbytetime);
6fee40e9
AF		 2621 out_8(&ugeth->p_scheduler->fracsiz, ug_info->fracsiz);
2622 out_8(&ugeth->p_scheduler->strictpriorityq,
2623 ug_info->strictpriorityq);
2624 out_8(&ugeth->p_scheduler->txasap, ug_info->txasap);
2625 out_8(&ugeth->p_scheduler->extrabw, ug_info->extrabw);
ce973b14 2626 for (i = 0; i < NUM_TX_QUEUES; i++)
6fee40e9
AF		 2627 out_8(&ugeth->p_scheduler->weightfactor[i],
2628 ug_info->weightfactor[i]);
ce973b14
LY		 2629
2630 /* Set pointers to cpucount registers in scheduler */
2631 ugeth->p_cpucount[0] = &(ugeth->p_scheduler->cpucount0);
2632 ugeth->p_cpucount[1] = &(ugeth->p_scheduler->cpucount1);
2633 ugeth->p_cpucount[2] = &(ugeth->p_scheduler->cpucount2);
2634 ugeth->p_cpucount[3] = &(ugeth->p_scheduler->cpucount3);
2635 ugeth->p_cpucount[4] = &(ugeth->p_scheduler->cpucount4);
2636 ugeth->p_cpucount[5] = &(ugeth->p_scheduler->cpucount5);
2637 ugeth->p_cpucount[6] = &(ugeth->p_scheduler->cpucount6);
2638 ugeth->p_cpucount[7] = &(ugeth->p_scheduler->cpucount7);
2639 }
2640
2641 /* schedulerbasepointer */
2642 /* TxRMON_PTR (statistics) */
2643 if (ug_info->
2644 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX) {
2645 ugeth->tx_fw_statistics_pram_offset =
2646 qe_muram_alloc(sizeof
18a8e864 2647 (struct ucc_geth_tx_firmware_statistics_pram),
ce973b14 2648 UCC_GETH_TX_STATISTICS_ALIGNMENT);
4c35630c 2649 if (IS_ERR_VALUE(ugeth->tx_fw_statistics_pram_offset)) {
890de95e
LY		 2650 if (netif_msg_ifup(ugeth))
2651 ugeth_err
2652 ("%s: Can not allocate DPRAM memory for"
2653 " p_tx_fw_statistics_pram.",
b39d66a8 2654 __func__);
ce973b14
LY		 2655 return -ENOMEM;
2656 }
2657 ugeth->p_tx_fw_statistics_pram =
6fee40e9 2658 (struct ucc_geth_tx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2659 qe_muram_addr(ugeth->tx_fw_statistics_pram_offset);
2660 /* Zero out p_tx_fw_statistics_pram */
6fee40e9 2661 memset_io((void __iomem *)ugeth->p_tx_fw_statistics_pram,
18a8e864 2662 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram));
ce973b14
LY		 2663 }
2664
2665 /* temoder */
2666 /* Already has speed set */
2667
2668 if (ug_info->numQueuesTx > 1)
2669 temoder |= TEMODER_SCHEDULER_ENABLE;
2670 if (ug_info->ipCheckSumGenerate)
2671 temoder |= TEMODER_IP_CHECKSUM_GENERATE;
2672 temoder |= ((ug_info->numQueuesTx - 1) << TEMODER_NUM_OF_QUEUES_SHIFT);
2673 out_be16(&ugeth->p_tx_glbl_pram->temoder, temoder);
2674
2675 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2676
2677 /* Function code register value to be used later */
6b0b594b 2678 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
ce973b14
LY		 2679 /* Required for QE */
2680
2681 /* function code register */
2682 out_be32(&ugeth->p_tx_glbl_pram->tstate, ((u32) function_code) << 24);
2683
2684 /* Rx global PRAM */
2685 /* Allocate global rx parameter RAM page */
2686 ugeth->rx_glbl_pram_offset =
18a8e864 2687 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram),
ce973b14 2688 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT);
4c35630c 2689 if (IS_ERR_VALUE(ugeth->rx_glbl_pram_offset)) {
890de95e
LY		 2690 if (netif_msg_ifup(ugeth))
2691 ugeth_err
2692 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
b39d66a8 2693 __func__);
ce973b14
LY		 2694 return -ENOMEM;
2695 }
2696 ugeth->p_rx_glbl_pram =
6fee40e9 2697 (struct ucc_geth_rx_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2698 rx_glbl_pram_offset);
2699 /* Zero out p_rx_glbl_pram */
6fee40e9 2700 memset_io((void __iomem *)ugeth->p_rx_glbl_pram, 0, sizeof(struct ucc_geth_rx_global_pram));
ce973b14
LY		 2701
2702 /* Fill global PRAM */
2703
2704 /* RQPTR */
2705 /* Size varies with number of Rx threads */
2706 ugeth->thread_dat_rx_offset =
2707 qe_muram_alloc(numThreadsRxNumerical *
18a8e864 2708 sizeof(struct ucc_geth_thread_data_rx),
ce973b14 2709 UCC_GETH_THREAD_DATA_ALIGNMENT);
4c35630c 2710 if (IS_ERR_VALUE(ugeth->thread_dat_rx_offset)) {
890de95e
LY		 2711 if (netif_msg_ifup(ugeth))
2712 ugeth_err
2713 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
b39d66a8 2714 __func__);
ce973b14
LY		 2715 return -ENOMEM;
2716 }
2717
2718 ugeth->p_thread_data_rx =
6fee40e9 2719 (struct ucc_geth_thread_data_rx __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2720 thread_dat_rx_offset);
2721 out_be32(&ugeth->p_rx_glbl_pram->rqptr, ugeth->thread_dat_rx_offset);
2722
2723 /* typeorlen */
2724 out_be16(&ugeth->p_rx_glbl_pram->typeorlen, ug_info->typeorlen);
2725
2726 /* rxrmonbaseptr (statistics) */
2727 if (ug_info->
2728 statisticsMode & UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX) {
2729 ugeth->rx_fw_statistics_pram_offset =
2730 qe_muram_alloc(sizeof
18a8e864 2731 (struct ucc_geth_rx_firmware_statistics_pram),
ce973b14 2732 UCC_GETH_RX_STATISTICS_ALIGNMENT);
4c35630c 2733 if (IS_ERR_VALUE(ugeth->rx_fw_statistics_pram_offset)) {
890de95e
LY		 2734 if (netif_msg_ifup(ugeth))
2735 ugeth_err
2736 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2737 " p_rx_fw_statistics_pram.", __func__);
ce973b14
LY		 2738 return -ENOMEM;
2739 }
2740 ugeth->p_rx_fw_statistics_pram =
6fee40e9 2741 (struct ucc_geth_rx_firmware_statistics_pram __iomem *)
ce973b14
LY		 2742 qe_muram_addr(ugeth->rx_fw_statistics_pram_offset);
2743 /* Zero out p_rx_fw_statistics_pram */
6fee40e9 2744 memset_io((void __iomem *)ugeth->p_rx_fw_statistics_pram, 0,
18a8e864 2745 sizeof(struct ucc_geth_rx_firmware_statistics_pram));
ce973b14
LY		 2746 }
2747
2748 /* intCoalescingPtr */
2749
2750 /* Size varies with number of Rx queues */
2751 ugeth->rx_irq_coalescing_tbl_offset =
2752 qe_muram_alloc(ug_info->numQueuesRx *
7563907e
MB		 2753 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry)
2754 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT);
4c35630c 2755 if (IS_ERR_VALUE(ugeth->rx_irq_coalescing_tbl_offset)) {
890de95e
LY		 2756 if (netif_msg_ifup(ugeth))
2757 ugeth_err
2758 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2759 " p_rx_irq_coalescing_tbl.", __func__);
ce973b14
LY		 2760 return -ENOMEM;
2761 }
2762
2763 ugeth->p_rx_irq_coalescing_tbl =
6fee40e9 2764 (struct ucc_geth_rx_interrupt_coalescing_table __iomem *)
ce973b14
LY		 2765 qe_muram_addr(ugeth->rx_irq_coalescing_tbl_offset);
2766 out_be32(&ugeth->p_rx_glbl_pram->intcoalescingptr,
2767 ugeth->rx_irq_coalescing_tbl_offset);
2768
2769 /* Fill interrupt coalescing table */
2770 for (i = 0; i < ug_info->numQueuesRx; i++) {
2771 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2772 interruptcoalescingmaxvalue,
2773 ug_info->interruptcoalescingmaxvalue[i]);
2774 out_be32(&ugeth->p_rx_irq_coalescing_tbl->coalescingentry[i].
2775 interruptcoalescingcounter,
2776 ug_info->interruptcoalescingmaxvalue[i]);
2777 }
2778
2779 /* MRBLR */
2780 init_max_rx_buff_len(uf_info->max_rx_buf_length,
2781 &ugeth->p_rx_glbl_pram->mrblr);
2782 /* MFLR */
2783 out_be16(&ugeth->p_rx_glbl_pram->mflr, ug_info->maxFrameLength);
2784 /* MINFLR */
2785 init_min_frame_len(ug_info->minFrameLength,
2786 &ugeth->p_rx_glbl_pram->minflr,
2787 &ugeth->p_rx_glbl_pram->mrblr);
2788 /* MAXD1 */
2789 out_be16(&ugeth->p_rx_glbl_pram->maxd1, ug_info->maxD1Length);
2790 /* MAXD2 */
2791 out_be16(&ugeth->p_rx_glbl_pram->maxd2, ug_info->maxD2Length);
2792
2793 /* l2qt */
2794 l2qt = 0;
2795 for (i = 0; i < UCC_GETH_VLAN_PRIORITY_MAX; i++)
2796 l2qt |= (ug_info->l2qt[i] << (28 - 4 * i));
2797 out_be32(&ugeth->p_rx_glbl_pram->l2qt, l2qt);
2798
2799 /* l3qt */
2800 for (j = 0; j < UCC_GETH_IP_PRIORITY_MAX; j += 8) {
2801 l3qt = 0;
2802 for (i = 0; i < 8; i++)
2803 l3qt |= (ug_info->l3qt[j + i] << (28 - 4 * i));
18a8e864 2804 out_be32(&ugeth->p_rx_glbl_pram->l3qt[j/8], l3qt);
ce973b14
LY		 2805 }
2806
2807 /* vlantype */
2808 out_be16(&ugeth->p_rx_glbl_pram->vlantype, ug_info->vlantype);
2809
2810 /* vlantci */
2811 out_be16(&ugeth->p_rx_glbl_pram->vlantci, ug_info->vlantci);
2812
2813 /* ecamptr */
2814 out_be32(&ugeth->p_rx_glbl_pram->ecamptr, ug_info->ecamptr);
2815
2816 /* RBDQPTR */
2817 /* Size varies with number of Rx queues */
2818 ugeth->rx_bd_qs_tbl_offset =
2819 qe_muram_alloc(ug_info->numQueuesRx *
18a8e864
LY		 2820 (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2821 sizeof(struct ucc_geth_rx_prefetched_bds)),
ce973b14 2822 UCC_GETH_RX_BD_QUEUES_ALIGNMENT);
4c35630c 2823 if (IS_ERR_VALUE(ugeth->rx_bd_qs_tbl_offset)) {
890de95e
LY		 2824 if (netif_msg_ifup(ugeth))
2825 ugeth_err
2826 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
b39d66a8 2827 __func__);
ce973b14
LY		 2828 return -ENOMEM;
2829 }
2830
2831 ugeth->p_rx_bd_qs_tbl =
6fee40e9 2832 (struct ucc_geth_rx_bd_queues_entry __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2833 rx_bd_qs_tbl_offset);
2834 out_be32(&ugeth->p_rx_glbl_pram->rbdqptr, ugeth->rx_bd_qs_tbl_offset);
2835 /* Zero out p_rx_bd_qs_tbl */
6fee40e9 2836 memset_io((void __iomem *)ugeth->p_rx_bd_qs_tbl,
ce973b14 2837 0,
18a8e864
LY		 2838 ug_info->numQueuesRx * (sizeof(struct ucc_geth_rx_bd_queues_entry) +
2839 sizeof(struct ucc_geth_rx_prefetched_bds)));
ce973b14
LY		 2840
2841 /* Setup the table */
2842 /* Assume BD rings are already established */
2843 for (i = 0; i < ug_info->numQueuesRx; i++) {
2844 if (ugeth->ug_info->uf_info.bd_mem_part == MEM_PART_SYSTEM) {
2845 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2846 (u32) virt_to_phys(ugeth->p_rx_bd_ring[i]));
2847 } else if (ugeth->ug_info->uf_info.bd_mem_part ==
2848 MEM_PART_MURAM) {
2849 out_be32(&ugeth->p_rx_bd_qs_tbl[i].externalbdbaseptr,
2850 (u32) immrbar_virt_to_phys(ugeth->
2851 p_rx_bd_ring[i]));
2852 }
2853 /* rest of fields handled by QE */
2854 }
2855
2856 /* remoder */
2857 /* Already has speed set */
2858
2859 if (ugeth->rx_extended_features)
2860 remoder |= REMODER_RX_EXTENDED_FEATURES;
2861 if (ug_info->rxExtendedFiltering)
2862 remoder |= REMODER_RX_EXTENDED_FILTERING;
2863 if (ug_info->dynamicMaxFrameLength)
2864 remoder |= REMODER_DYNAMIC_MAX_FRAME_LENGTH;
2865 if (ug_info->dynamicMinFrameLength)
2866 remoder |= REMODER_DYNAMIC_MIN_FRAME_LENGTH;
2867 remoder |=
2868 ug_info->vlanOperationTagged << REMODER_VLAN_OPERATION_TAGGED_SHIFT;
2869 remoder |=
2870 ug_info->
2871 vlanOperationNonTagged << REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT;
2872 remoder |= ug_info->rxQoSMode << REMODER_RX_QOS_MODE_SHIFT;
2873 remoder |= ((ug_info->numQueuesRx - 1) << REMODER_NUM_OF_QUEUES_SHIFT);
2874 if (ug_info->ipCheckSumCheck)
2875 remoder |= REMODER_IP_CHECKSUM_CHECK;
2876 if (ug_info->ipAddressAlignment)
2877 remoder |= REMODER_IP_ADDRESS_ALIGNMENT;
2878 out_be32(&ugeth->p_rx_glbl_pram->remoder, remoder);
2879
2880 /* Note that this function must be called */
2881 /* ONLY AFTER p_tx_fw_statistics_pram */
2882 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
2883 init_firmware_statistics_gathering_mode((ug_info->
2884 statisticsMode &
2885 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX),
2886 (ug_info->statisticsMode &
2887 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX),
2888 &ugeth->p_tx_glbl_pram->txrmonbaseptr,
2889 ugeth->tx_fw_statistics_pram_offset,
2890 &ugeth->p_rx_glbl_pram->rxrmonbaseptr,
2891 ugeth->rx_fw_statistics_pram_offset,
2892 &ugeth->p_tx_glbl_pram->temoder,
2893 &ugeth->p_rx_glbl_pram->remoder);
2894
2895 /* function code register */
6fee40e9 2896 out_8(&ugeth->p_rx_glbl_pram->rstate, function_code);
ce973b14
LY		 2897
2898 /* initialize extended filtering */
2899 if (ug_info->rxExtendedFiltering) {
2900 if (!ug_info->extendedFilteringChainPointer) {
890de95e
LY		 2901 if (netif_msg_ifup(ugeth))
2902 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
b39d66a8 2903 __func__);
ce973b14
LY		 2904 return -EINVAL;
2905 }
2906
2907 /* Allocate memory for extended filtering Mode Global
2908 Parameters */
2909 ugeth->exf_glbl_param_offset =
18a8e864 2910 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram),
ce973b14 2911 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT);
4c35630c 2912 if (IS_ERR_VALUE(ugeth->exf_glbl_param_offset)) {
890de95e
LY		 2913 if (netif_msg_ifup(ugeth))
2914 ugeth_err
2915 ("%s: Can not allocate DPRAM memory for"
b39d66a8 2916 " p_exf_glbl_param.", __func__);
ce973b14
LY		 2917 return -ENOMEM;
2918 }
2919
2920 ugeth->p_exf_glbl_param =
6fee40e9 2921 (struct ucc_geth_exf_global_pram __iomem *) qe_muram_addr(ugeth->
ce973b14
LY		 2922 exf_glbl_param_offset);
2923 out_be32(&ugeth->p_rx_glbl_pram->exfGlobalParam,
2924 ugeth->exf_glbl_param_offset);
2925 out_be32(&ugeth->p_exf_glbl_param->l2pcdptr,
2926 (u32) ug_info->extendedFilteringChainPointer);
2927
2928 } else { /* initialize 82xx style address filtering */
2929
2930 /* Init individual address recognition registers to disabled */
2931
2932 for (j = 0; j < NUM_OF_PADDRS; j++)
2933 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth, (u8) j);
2934
ce973b14 2935 p_82xx_addr_filt =
6fee40e9 2936 (struct ucc_geth_82xx_address_filtering_pram __iomem *) ugeth->
ce973b14
LY		 2937 p_rx_glbl_pram->addressfiltering;
2938
2939 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2940 ENET_ADDR_TYPE_GROUP);
2941 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth,
2942 ENET_ADDR_TYPE_INDIVIDUAL);
2943 }
2944
2945 /*
2946 * Initialize UCC at QE level
2947 */
2948
2949 command = QE_INIT_TX_RX;
2950
2951 /* Allocate shadow InitEnet command parameter structure.
2952 * This is needed because after the InitEnet command is executed,
2953 * the structure in DPRAM is released, because DPRAM is a premium
2954 * resource.
2955 * This shadow structure keeps a copy of what was done so that the
2956 * allocated resources can be released when the channel is freed.
2957 */
2958 if (!(ugeth->p_init_enet_param_shadow =
04b588d7 2959 kmalloc(sizeof(struct ucc_geth_init_pram), GFP_KERNEL))) {
890de95e
LY		 2960 if (netif_msg_ifup(ugeth))
2961 ugeth_err
2962 ("%s: Can not allocate memory for"
b39d66a8 2963 " p_UccInitEnetParamShadows.", __func__);
ce973b14
LY		 2964 return -ENOMEM;
2965 }
2966 /* Zero out *p_init_enet_param_shadow */
2967 memset((char *)ugeth->p_init_enet_param_shadow,
18a8e864 2968 0, sizeof(struct ucc_geth_init_pram));
ce973b14
LY		 2969
2970 /* Fill shadow InitEnet command parameter structure */
2971
2972 ugeth->p_init_enet_param_shadow->resinit1 =
2973 ENET_INIT_PARAM_MAGIC_RES_INIT1;
2974 ugeth->p_init_enet_param_shadow->resinit2 =
2975 ENET_INIT_PARAM_MAGIC_RES_INIT2;
2976 ugeth->p_init_enet_param_shadow->resinit3 =
2977 ENET_INIT_PARAM_MAGIC_RES_INIT3;
2978 ugeth->p_init_enet_param_shadow->resinit4 =
2979 ENET_INIT_PARAM_MAGIC_RES_INIT4;
2980 ugeth->p_init_enet_param_shadow->resinit5 =
2981 ENET_INIT_PARAM_MAGIC_RES_INIT5;
2982 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2983 ((u32) ug_info->numThreadsRx) << ENET_INIT_PARAM_RGF_SHIFT;
2984 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2985 ((u32) ug_info->numThreadsTx) << ENET_INIT_PARAM_TGF_SHIFT;
2986
2987 ugeth->p_init_enet_param_shadow->rgftgfrxglobal |=
2988 ugeth->rx_glbl_pram_offset | ug_info->riscRx;
2989 if ((ug_info->largestexternallookupkeysize !=
8e95a202
JP		 2990 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE) &&
2991 (ug_info->largestexternallookupkeysize !=
2992 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES) &&
2993 (ug_info->largestexternallookupkeysize !=
2994 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES)) {
890de95e
LY		 2995 if (netif_msg_ifup(ugeth))
2996 ugeth_err("%s: Invalid largest External Lookup Key Size.",
b39d66a8 2997 __func__);
ce973b14
LY		 2998 return -EINVAL;
2999 }
3000 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize =
3001 ug_info->largestexternallookupkeysize;
18a8e864 3002 size = sizeof(struct ucc_geth_thread_rx_pram);
ce973b14
LY		 3003 if (ug_info->rxExtendedFiltering) {
3004 size += THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING;
3005 if (ug_info->largestexternallookupkeysize ==
3006 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES)
3007 size +=
3008 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8;
3009 if (ug_info->largestexternallookupkeysize ==
3010 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES)
3011 size +=
3012 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16;
3013 }
3014
3015 if ((ret_val = fill_init_enet_entries(ugeth, &(ugeth->
3016 p_init_enet_param_shadow->rxthread[0]),
3017 (u8) (numThreadsRxNumerical + 1)
3018 /* Rx needs one extra for terminator */
3019 , size, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT,
3020 ug_info->riscRx, 1)) != 0) {
890de95e
LY		 3021 if (netif_msg_ifup(ugeth))
3022 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3023 __func__);
ce973b14
LY		 3024 return ret_val;
3025 }
3026
3027 ugeth->p_init_enet_param_shadow->txglobal =
3028 ugeth->tx_glbl_pram_offset | ug_info->riscTx;
3029 if ((ret_val =
3030 fill_init_enet_entries(ugeth,
3031 &(ugeth->p_init_enet_param_shadow->
3032 txthread[0]), numThreadsTxNumerical,
18a8e864 3033 sizeof(struct ucc_geth_thread_tx_pram),
ce973b14
LY		 3034 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT,
3035 ug_info->riscTx, 0)) != 0) {
890de95e
LY		 3036 if (netif_msg_ifup(ugeth))
3037 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
b39d66a8 3038 __func__);
ce973b14
LY		 3039 return ret_val;
3040 }
3041
3042 /* Load Rx bds with buffers */
3043 for (i = 0; i < ug_info->numQueuesRx; i++) {
3044 if ((ret_val = rx_bd_buffer_set(ugeth, (u8) i)) != 0) {
890de95e
LY		 3045 if (netif_msg_ifup(ugeth))
3046 ugeth_err("%s: Can not fill Rx bds with buffers.",
b39d66a8 3047 __func__);
ce973b14
LY		 3048 return ret_val;
3049 }
3050 }
3051
3052 /* Allocate InitEnet command parameter structure */
18a8e864 3053 init_enet_pram_offset = qe_muram_alloc(sizeof(struct ucc_geth_init_pram), 4);
4c35630c 3054 if (IS_ERR_VALUE(init_enet_pram_offset)) {
890de95e
LY		 3055 if (netif_msg_ifup(ugeth))
3056 ugeth_err
3057 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
b39d66a8 3058 __func__);
ce973b14
LY		 3059 return -ENOMEM;
3060 }
3061 p_init_enet_pram =
6fee40e9 3062 (struct ucc_geth_init_pram __iomem *) qe_muram_addr(init_enet_pram_offset);
ce973b14
LY		 3063
3064 /* Copy shadow InitEnet command parameter structure into PRAM */
6fee40e9
AF		 3065 out_8(&p_init_enet_pram->resinit1,
3066 ugeth->p_init_enet_param_shadow->resinit1);
3067 out_8(&p_init_enet_pram->resinit2,
3068 ugeth->p_init_enet_param_shadow->resinit2);
3069 out_8(&p_init_enet_pram->resinit3,
3070 ugeth->p_init_enet_param_shadow->resinit3);
3071 out_8(&p_init_enet_pram->resinit4,
3072 ugeth->p_init_enet_param_shadow->resinit4);
ce973b14
LY		 3073 out_be16(&p_init_enet_pram->resinit5,
3074 ugeth->p_init_enet_param_shadow->resinit5);
6fee40e9
AF		 3075 out_8(&p_init_enet_pram->largestexternallookupkeysize,
3076 ugeth->p_init_enet_param_shadow->largestexternallookupkeysize);
ce973b14
LY		 3077 out_be32(&p_init_enet_pram->rgftgfrxglobal,
3078 ugeth->p_init_enet_param_shadow->rgftgfrxglobal);
3079 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_RX; i++)
3080 out_be32(&p_init_enet_pram->rxthread[i],
3081 ugeth->p_init_enet_param_shadow->rxthread[i]);
3082 out_be32(&p_init_enet_pram->txglobal,
3083 ugeth->p_init_enet_param_shadow->txglobal);
3084 for (i = 0; i < ENET_INIT_PARAM_MAX_ENTRIES_TX; i++)
3085 out_be32(&p_init_enet_pram->txthread[i],
3086 ugeth->p_init_enet_param_shadow->txthread[i]);
3087
3088 /* Issue QE command */
3089 cecr_subblock =
3090 ucc_fast_get_qe_cr_subblock(ugeth->ug_info->uf_info.ucc_num);
18a8e864 3091 qe_issue_cmd(command, cecr_subblock, QE_CR_PROTOCOL_ETHERNET,
ce973b14
LY		 3092 init_enet_pram_offset);
3093
3094 /* Free InitEnet command parameter */
3095 qe_muram_free(init_enet_pram_offset);
3096
3097 return 0;
3098}
3099
ce973b14
LY		 3100/* This is called by the kernel when a frame is ready for transmission. */
3101/* It is pointed to by the dev->hard_start_xmit function pointer */
3102static int ucc_geth_start_xmit(struct sk_buff *skb, struct net_device *dev)
3103{
18a8e864 3104 struct ucc_geth_private *ugeth = netdev_priv(dev);
d5b9049d
MR		 3105#ifdef CONFIG_UGETH_TX_ON_DEMAND
3106 struct ucc_fast_private *uccf;
3107#endif
6fee40e9 3108 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3109 u32 bd_status;
3110 u8 txQ = 0;
22580f89 3111 unsigned long flags;
ce973b14 3112
b39d66a8 3113 ugeth_vdbg("%s: IN", __func__);
ce973b14 3114
22580f89 3115 spin_lock_irqsave(&ugeth->lock, flags);
ce973b14 3116
09f75cd7 3117 dev->stats.tx_bytes += skb->len;
ce973b14
LY		 3118
3119 /* Start from the next BD that should be filled */
3120 bd = ugeth->txBd[txQ];
6fee40e9 3121 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3122 /* Save the skb pointer so we can free it later */
3123 ugeth->tx_skbuff[txQ][ugeth->skb_curtx[txQ]] = skb;
3124
3125 /* Update the current skb pointer (wrapping if this was the last) */
3126 ugeth->skb_curtx[txQ] =
3127 (ugeth->skb_curtx[txQ] +
3128 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3129
3130 /* set up the buffer descriptor */
6fee40e9 3131 out_be32(&((struct qe_bd __iomem *)bd)->buf,
da1aa63e 3132 dma_map_single(ugeth->dev, skb->data,
7f80202b 3133 skb->len, DMA_TO_DEVICE));
ce973b14 3134
18a8e864 3135 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
ce973b14
LY		 3136
3137 bd_status = (bd_status & T_W) | T_R | T_I | T_L | skb->len;
3138
18a8e864 3139 /* set bd status and length */
6fee40e9 3140 out_be32((u32 __iomem *)bd, bd_status);
ce973b14
LY		 3141
3142 dev->trans_start = jiffies;
3143
3144 /* Move to next BD in the ring */
3145 if (!(bd_status & T_W))
a394f013 3146 bd += sizeof(struct qe_bd);
ce973b14 3147 else
a394f013 3148 bd = ugeth->p_tx_bd_ring[txQ];
ce973b14
LY		 3149
3150 /* If the next BD still needs to be cleaned up, then the bds
3151 are full. We need to tell the kernel to stop sending us stuff. */
3152 if (bd == ugeth->confBd[txQ]) {
3153 if (!netif_queue_stopped(dev))
3154 netif_stop_queue(dev);
3155 }
3156
a394f013
LY		 3157 ugeth->txBd[txQ] = bd;
3158
ce973b14
LY		 3159 if (ugeth->p_scheduler) {
3160 ugeth->cpucount[txQ]++;
3161 /* Indicate to QE that there are more Tx bds ready for
3162 transmission */
3163 /* This is done by writing a running counter of the bd
3164 count to the scheduler PRAM. */
3165 out_be16(ugeth->p_cpucount[txQ], ugeth->cpucount[txQ]);
3166 }
3167
d5b9049d
MR		 3168#ifdef CONFIG_UGETH_TX_ON_DEMAND
3169 uccf = ugeth->uccf;
3170 out_be16(uccf->p_utodr, UCC_FAST_TOD);
3171#endif
22580f89 3172 spin_unlock_irqrestore(&ugeth->lock, flags);
ce973b14 3173
6ed10654 3174 return NETDEV_TX_OK;
ce973b14
LY		 3175}
3176
18a8e864 3177static int ucc_geth_rx(struct ucc_geth_private *ugeth, u8 rxQ, int rx_work_limit)
ce973b14
LY		 3178{
3179 struct sk_buff *skb;
6fee40e9 3180 u8 __iomem *bd;
ce973b14
LY		 3181 u16 length, howmany = 0;
3182 u32 bd_status;
3183 u8 *bdBuffer;
4b8fdefa 3184 struct net_device *dev;
ce973b14 3185
b39d66a8 3186 ugeth_vdbg("%s: IN", __func__);
ce973b14 3187
da1aa63e 3188 dev = ugeth->ndev;
88a15f2e 3189
ce973b14
LY		 3190 /* collect received buffers */
3191 bd = ugeth->rxBd[rxQ];
3192
6fee40e9 3193 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3194
3195 /* while there are received buffers and BD is full (~R_E) */
3196 while (!((bd_status & (R_E)) || (--rx_work_limit < 0))) {
6fee40e9 3197 bdBuffer = (u8 *) in_be32(&((struct qe_bd __iomem *)bd)->buf);
ce973b14
LY		 3198 length = (u16) ((bd_status & BD_LENGTH_MASK) - 4);
3199 skb = ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]];
3200
3201 /* determine whether buffer is first, last, first and last
3202 (single buffer frame) or middle (not first and not last) */
3203 if (!skb ||
3204 (!(bd_status & (R_F | R_L))) ||
3205 (bd_status & R_ERRORS_FATAL)) {
890de95e
LY		 3206 if (netif_msg_rx_err(ugeth))
3207 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
b39d66a8 3208 __func__, __LINE__, (u32) skb);
50f238fd
AV		 3209 if (skb) {
3210 skb->data = skb->head + NET_SKB_PAD;
3211 __skb_queue_head(&ugeth->rx_recycle, skb);
3212 }
ce973b14
LY		 3213
3214 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = NULL;
09f75cd7 3215 dev->stats.rx_dropped++;
ce973b14 3216 } else {
09f75cd7 3217 dev->stats.rx_packets++;
ce973b14
LY		 3218 howmany++;
3219
3220 /* Prep the skb for the packet */
3221 skb_put(skb, length);
3222
3223 /* Tell the skb what kind of packet this is */
da1aa63e 3224 skb->protocol = eth_type_trans(skb, ugeth->ndev);
ce973b14 3225
09f75cd7 3226 dev->stats.rx_bytes += length;
ce973b14 3227 /* Send the packet up the stack */
ce973b14 3228 netif_receive_skb(skb);
ce973b14
LY		 3229 }
3230
ce973b14
LY		 3231 skb = get_new_skb(ugeth, bd);
3232 if (!skb) {
890de95e 3233 if (netif_msg_rx_err(ugeth))
b39d66a8 3234 ugeth_warn("%s: No Rx Data Buffer", __func__);
09f75cd7 3235 dev->stats.rx_dropped++;
ce973b14
LY		 3236 break;
3237 }
3238
3239 ugeth->rx_skbuff[rxQ][ugeth->skb_currx[rxQ]] = skb;
3240
3241 /* update to point at the next skb */
3242 ugeth->skb_currx[rxQ] =
3243 (ugeth->skb_currx[rxQ] +
3244 1) & RX_RING_MOD_MASK(ugeth->ug_info->bdRingLenRx[rxQ]);
3245
3246 if (bd_status & R_W)
3247 bd = ugeth->p_rx_bd_ring[rxQ];
3248 else
18a8e864 3249 bd += sizeof(struct qe_bd);
ce973b14 3250
6fee40e9 3251 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3252 }
3253
3254 ugeth->rxBd[rxQ] = bd;
ce973b14
LY		 3255 return howmany;
3256}
3257
3258static int ucc_geth_tx(struct net_device *dev, u8 txQ)
3259{
3260 /* Start from the next BD that should be filled */
18a8e864 3261 struct ucc_geth_private *ugeth = netdev_priv(dev);
6fee40e9 3262 u8 __iomem *bd; /* BD pointer */
ce973b14
LY		 3263 u32 bd_status;
3264
3265 bd = ugeth->confBd[txQ];
6fee40e9 3266 bd_status = in_be32((u32 __iomem *)bd);
ce973b14
LY		 3267
3268 /* Normal processing. */
3269 while ((bd_status & T_R) == 0) {
50f238fd
AV		 3270 struct sk_buff *skb;
3271
ce973b14
LY		 3272 /* BD contains already transmitted buffer. */
3273 /* Handle the transmitted buffer and release */
3274 /* the BD to be used with the current frame */
3275
7583605b 3276 if (bd == ugeth->txBd[txQ]) /* queue empty? */
ce973b14
LY		 3277 break;
3278
09f75cd7 3279 dev->stats.tx_packets++;
ce973b14 3280
50f238fd
AV		 3281 skb = ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]];
3282
3283 if (skb_queue_len(&ugeth->rx_recycle) < RX_BD_RING_LEN &&
3284 skb_recycle_check(skb,
3285 ugeth->ug_info->uf_info.max_rx_buf_length +
3286 UCC_GETH_RX_DATA_BUF_ALIGNMENT))
3287 __skb_queue_head(&ugeth->rx_recycle, skb);
3288 else
3289 dev_kfree_skb(skb);
3290
ce973b14
LY		 3291 ugeth->tx_skbuff[txQ][ugeth->skb_dirtytx[txQ]] = NULL;
3292 ugeth->skb_dirtytx[txQ] =
3293 (ugeth->skb_dirtytx[txQ] +
3294 1) & TX_RING_MOD_MASK(ugeth->ug_info->bdRingLenTx[txQ]);
3295
3296 /* We freed a buffer, so now we can restart transmission */
3297 if (netif_queue_stopped(dev))
3298 netif_wake_queue(dev);
3299
3300 /* Advance the confirmation BD pointer */
3301 if (!(bd_status & T_W))
a394f013 3302 bd += sizeof(struct qe_bd);
ce973b14 3303 else
a394f013 3304 bd = ugeth->p_tx_bd_ring[txQ];
6fee40e9 3305 bd_status = in_be32((u32 __iomem *)bd);
ce973b14 3306 }
a394f013 3307 ugeth->confBd[txQ] = bd;
ce973b14
LY		 3308 return 0;
3309}
3310
bea3348e 3311static int ucc_geth_poll(struct napi_struct *napi, int budget)
ce973b14 3312{
bea3348e 3313 struct ucc_geth_private *ugeth = container_of(napi, struct ucc_geth_private, napi);
702ff12c 3314 struct ucc_geth_info *ug_info;
bea3348e 3315 int howmany, i;
ce973b14 3316
702ff12c
MR		 3317 ug_info = ugeth->ug_info;
3318
0cededf3
JT		 3319 /* Tx event processing */
3320 spin_lock(&ugeth->lock);
3321 for (i = 0; i < ug_info->numQueuesTx; i++)
3322 ucc_geth_tx(ugeth->ndev, i);
3323 spin_unlock(&ugeth->lock);
3324
50f238fd
AV		 3325 howmany = 0;
3326 for (i = 0; i < ug_info->numQueuesRx; i++)
3327 howmany += ucc_geth_rx(ugeth, i, budget - howmany);
3328
bea3348e 3329 if (howmany < budget) {
288379f0 3330 napi_complete(napi);
0cededf3 3331 setbits32(ugeth->uccf->p_uccm, UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3332 }
ce973b14 3333
bea3348e 3334 return howmany;
ce973b14 3335}
ce973b14 3336
7d12e780 3337static irqreturn_t ucc_geth_irq_handler(int irq, void *info)
ce973b14 3338{
06efcad0 3339 struct net_device *dev = info;
18a8e864
LY		 3340 struct ucc_geth_private *ugeth = netdev_priv(dev);
3341 struct ucc_fast_private *uccf;
3342 struct ucc_geth_info *ug_info;
702ff12c
MR		 3343 register u32 ucce;
3344 register u32 uccm;
ce973b14 3345
b39d66a8 3346 ugeth_vdbg("%s: IN", __func__);
ce973b14 3347
ce973b14
LY		 3348 uccf = ugeth->uccf;
3349 ug_info = ugeth->ug_info;
3350
702ff12c
MR		 3351 /* read and clear events */
3352 ucce = (u32) in_be32(uccf->p_ucce);
3353 uccm = (u32) in_be32(uccf->p_uccm);
3354 ucce &= uccm;
3355 out_be32(uccf->p_ucce, ucce);
ce973b14 3356
702ff12c 3357 /* check for receive events that require processing */
0cededf3 3358 if (ucce & (UCCE_RX_EVENTS | UCCE_TX_EVENTS)) {
288379f0 3359 if (napi_schedule_prep(&ugeth->napi)) {
0cededf3 3360 uccm &= ~(UCCE_RX_EVENTS | UCCE_TX_EVENTS);
702ff12c 3361 out_be32(uccf->p_uccm, uccm);
288379f0 3362 __napi_schedule(&ugeth->napi);
702ff12c 3363 }
702ff12c 3364 }
ce973b14 3365
702ff12c
MR		 3366 /* Errors and other events */
3367 if (ucce & UCCE_OTHER) {
3bc53427 3368 if (ucce & UCC_GETH_UCCE_BSY)
09f75cd7 3369 dev->stats.rx_errors++;
3bc53427 3370 if (ucce & UCC_GETH_UCCE_TXE)
09f75cd7 3371 dev->stats.tx_errors++;
ce973b14 3372 }
ce973b14
LY		 3373
3374 return IRQ_HANDLED;
3375}
3376
26d29ea7
AV		 3377#ifdef CONFIG_NET_POLL_CONTROLLER
3378/*
3379 * Polling 'interrupt' - used by things like netconsole to send skbs
3380 * without having to re-enable interrupts. It's not called while
3381 * the interrupt routine is executing.
3382 */
3383static void ucc_netpoll(struct net_device *dev)
3384{
3385 struct ucc_geth_private *ugeth = netdev_priv(dev);
3386 int irq = ugeth->ug_info->uf_info.irq;
3387
3388 disable_irq(irq);
3389 ucc_geth_irq_handler(irq, dev);
3390 enable_irq(irq);
3391}
3392#endif /* CONFIG_NET_POLL_CONTROLLER */
3393
3d6593e9
KH		 3394static int ucc_geth_set_mac_addr(struct net_device *dev, void *p)
3395{
3396 struct ucc_geth_private *ugeth = netdev_priv(dev);
3397 struct sockaddr *addr = p;
3398
3399 if (!is_valid_ether_addr(addr->sa_data))
3400 return -EADDRNOTAVAIL;
3401
3402 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3403
3404 /*
3405 * If device is not running, we will set mac addr register
3406 * when opening the device.
3407 */
3408 if (!netif_running(dev))
3409 return 0;
3410
3411 spin_lock_irq(&ugeth->lock);
3412 init_mac_station_addr_regs(dev->dev_addr[0],
3413 dev->dev_addr[1],
3414 dev->dev_addr[2],
3415 dev->dev_addr[3],
3416 dev->dev_addr[4],
3417 dev->dev_addr[5],
3418 &ugeth->ug_regs->macstnaddr1,
3419 &ugeth->ug_regs->macstnaddr2);
3420 spin_unlock_irq(&ugeth->lock);
3421
3422 return 0;
3423}
3424
54b15983 3425static int ucc_geth_init_mac(struct ucc_geth_private *ugeth)
ce973b14 3426{
54b15983 3427 struct net_device *dev = ugeth->ndev;
ce973b14
LY		 3428 int err;
3429
728de4c9
KP		 3430 err = ucc_struct_init(ugeth);
3431 if (err) {
890de95e 3432 if (netif_msg_ifup(ugeth))
54b15983
AV		 3433 ugeth_err("%s: Cannot configure internal struct, "
3434 "aborting.", dev->name);
3435 goto err;
728de4c9
KP		 3436 }
3437
ce973b14
LY		 3438 err = ucc_geth_startup(ugeth);
3439 if (err) {
890de95e
LY		 3440 if (netif_msg_ifup(ugeth))
3441 ugeth_err("%s: Cannot configure net device, aborting.",
3442 dev->name);
54b15983 3443 goto err;
ce973b14
LY		 3444 }
3445
3446 err = adjust_enet_interface(ugeth);
3447 if (err) {
890de95e
LY		 3448 if (netif_msg_ifup(ugeth))
3449 ugeth_err("%s: Cannot configure net device, aborting.",
3450 dev->name);
54b15983 3451 goto err;
ce973b14
LY		 3452 }
3453
3454 /* Set MACSTNADDR1, MACSTNADDR2 */
3455 /* For more details see the hardware spec. */
3456 init_mac_station_addr_regs(dev->dev_addr[0],
3457 dev->dev_addr[1],
3458 dev->dev_addr[2],
3459 dev->dev_addr[3],
3460 dev->dev_addr[4],
3461 dev->dev_addr[5],
3462 &ugeth->ug_regs->macstnaddr1,
3463 &ugeth->ug_regs->macstnaddr2);
3464
67c2fb8f 3465 err = ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
ce973b14 3466 if (err) {
890de95e 3467 if (netif_msg_ifup(ugeth))
67c2fb8f 3468 ugeth_err("%s: Cannot enable net device, aborting.", dev->name);
54b15983
AV		 3469 goto err;
3470 }
3471
3472 return 0;
3473err:
3474 ucc_geth_stop(ugeth);
3475 return err;
3476}
3477
3478/* Called when something needs to use the ethernet device */
3479/* Returns 0 for success. */
3480static int ucc_geth_open(struct net_device *dev)
3481{
3482 struct ucc_geth_private *ugeth = netdev_priv(dev);
3483 int err;
3484
3485 ugeth_vdbg("%s: IN", __func__);
3486
3487 /* Test station address */
3488 if (dev->dev_addr[0] & ENET_GROUP_ADDR) {
3489 if (netif_msg_ifup(ugeth))
3490 ugeth_err("%s: Multicast address used for station "
3491 "address - is this what you wanted?",
3492 __func__);
3493 return -EINVAL;
3494 }
3495
3496 err = init_phy(dev);
3497 if (err) {
3498 if (netif_msg_ifup(ugeth))
3499 ugeth_err("%s: Cannot initialize PHY, aborting.",
3500 dev->name);
3501 return err;
3502 }
3503
3504 err = ucc_geth_init_mac(ugeth);
3505 if (err) {
3506 if (netif_msg_ifup(ugeth))
3507 ugeth_err("%s: Cannot initialize MAC, aborting.",
3508 dev->name);
3509 goto err;
ce973b14 3510 }
ce973b14 3511
67c2fb8f
AV		 3512 err = request_irq(ugeth->ug_info->uf_info.irq, ucc_geth_irq_handler,
3513 0, "UCC Geth", dev);
ce973b14 3514 if (err) {
890de95e 3515 if (netif_msg_ifup(ugeth))
67c2fb8f
AV		 3516 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3517 dev->name);
54b15983 3518 goto err;
ce973b14
LY		 3519 }
3520
54b15983
AV		 3521 phy_start(ugeth->phydev);
3522 napi_enable(&ugeth->napi);
ce973b14
LY		 3523 netif_start_queue(dev);
3524
2394905f
AV		 3525 device_set_wakeup_capable(&dev->dev,
3526 qe_alive_during_sleep() || ugeth->phydev->irq);
3527 device_set_wakeup_enable(&dev->dev, ugeth->wol_en);
3528
ce973b14 3529 return err;
bea3348e 3530
54b15983 3531err:
ba574696 3532 ucc_geth_stop(ugeth);
bea3348e 3533 return err;
ce973b14
LY		 3534}
3535
3536/* Stops the kernel queue, and halts the controller */
3537static int ucc_geth_close(struct net_device *dev)
3538{
18a8e864 3539 struct ucc_geth_private *ugeth = netdev_priv(dev);
ce973b14 3540
b39d66a8 3541 ugeth_vdbg("%s: IN", __func__);
ce973b14 3542
bea3348e 3543 napi_disable(&ugeth->napi);
bea3348e 3544
ce973b14
LY		 3545 ucc_geth_stop(ugeth);
3546
da1aa63e 3547 free_irq(ugeth->ug_info->uf_info.irq, ugeth->ndev);
67c2fb8f 3548
ce973b14
LY		 3549 netif_stop_queue(dev);
3550
3551 return 0;
3552}
3553
fdb614c2
AV		 3554/* Reopen device. This will reset the MAC and PHY. */
3555static void ucc_geth_timeout_work(struct work_struct *work)
3556{
3557 struct ucc_geth_private *ugeth;
3558 struct net_device *dev;
3559
3560 ugeth = container_of(work, struct ucc_geth_private, timeout_work);
da1aa63e 3561 dev = ugeth->ndev;
fdb614c2
AV		 3562
3563 ugeth_vdbg("%s: IN", __func__);
3564
3565 dev->stats.tx_errors++;
3566
3567 ugeth_dump_regs(ugeth);
3568
3569 if (dev->flags & IFF_UP) {
3570 /*
3571 * Must reset MAC *and* PHY. This is done by reopening
3572 * the device.
3573 */
3574 ucc_geth_close(dev);
3575 ucc_geth_open(dev);
3576 }
3577
3578 netif_tx_schedule_all(dev);
3579}
3580
3581/*
3582 * ucc_geth_timeout gets called when a packet has not been
3583 * transmitted after a set amount of time.
3584 */
3585static void ucc_geth_timeout(struct net_device *dev)
3586{
3587 struct ucc_geth_private *ugeth = netdev_priv(dev);
3588
3589 netif_carrier_off(dev);
3590 schedule_work(&ugeth->timeout_work);
3591}
3592
2394905f
AV		 3593
3594#ifdef CONFIG_PM
3595
3596static int ucc_geth_suspend(struct of_device *ofdev, pm_message_t state)
3597{
3598 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3599 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3600
3601 if (!netif_running(ndev))
3602 return 0;
3603
3604 napi_disable(&ugeth->napi);
3605
3606 /*
3607 * Disable the controller, otherwise we'll wakeup on any network
3608 * activity.
3609 */
3610 ugeth_disable(ugeth, COMM_DIR_RX_AND_TX);
3611
3612 if (ugeth->wol_en & WAKE_MAGIC) {
3613 setbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3614 setbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3615 ucc_fast_enable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3616 } else if (!(ugeth->wol_en & WAKE_PHY)) {
3617 phy_stop(ugeth->phydev);
3618 }
3619
3620 return 0;
3621}
3622
3623static int ucc_geth_resume(struct of_device *ofdev)
3624{
3625 struct net_device *ndev = dev_get_drvdata(&ofdev->dev);
3626 struct ucc_geth_private *ugeth = netdev_priv(ndev);
3627 int err;
3628
3629 if (!netif_running(ndev))
3630 return 0;
3631
3632 if (qe_alive_during_sleep()) {
3633 if (ugeth->wol_en & WAKE_MAGIC) {
3634 ucc_fast_disable(ugeth->uccf, COMM_DIR_RX_AND_TX);
3635 clrbits32(&ugeth->ug_regs->maccfg2, MACCFG2_MPE);
3636 clrbits32(ugeth->uccf->p_uccm, UCC_GETH_UCCE_MPD);
3637 }
3638 ugeth_enable(ugeth, COMM_DIR_RX_AND_TX);
3639 } else {
3640 /*
3641 * Full reinitialization is required if QE shuts down
3642 * during sleep.
3643 */
3644 ucc_geth_memclean(ugeth);
3645
3646 err = ucc_geth_init_mac(ugeth);
3647 if (err) {
3648 ugeth_err("%s: Cannot initialize MAC, aborting.",
3649 ndev->name);
3650 return err;
3651 }
3652 }
3653
3654 ugeth->oldlink = 0;
3655 ugeth->oldspeed = 0;
3656 ugeth->oldduplex = -1;
3657
3658 phy_stop(ugeth->phydev);
3659 phy_start(ugeth->phydev);
3660
3661 napi_enable(&ugeth->napi);
3662 netif_start_queue(ndev);
3663
3664 return 0;
3665}
3666
3667#else
3668#define ucc_geth_suspend NULL
3669#define ucc_geth_resume NULL
3670#endif
3671
4e19b5c1 3672static phy_interface_t to_phy_interface(const char *phy_connection_type)
728de4c9 3673{
4e19b5c1 3674 if (strcasecmp(phy_connection_type, "mii") == 0)
728de4c9 3675 return PHY_INTERFACE_MODE_MII;
4e19b5c1 3676 if (strcasecmp(phy_connection_type, "gmii") == 0)
728de4c9 3677 return PHY_INTERFACE_MODE_GMII;
4e19b5c1 3678 if (strcasecmp(phy_connection_type, "tbi") == 0)
728de4c9 3679 return PHY_INTERFACE_MODE_TBI;
4e19b5c1 3680 if (strcasecmp(phy_connection_type, "rmii") == 0)
728de4c9 3681 return PHY_INTERFACE_MODE_RMII;
4e19b5c1 3682 if (strcasecmp(phy_connection_type, "rgmii") == 0)
728de4c9 3683 return PHY_INTERFACE_MODE_RGMII;
4e19b5c1 3684 if (strcasecmp(phy_connection_type, "rgmii-id") == 0)
728de4c9 3685 return PHY_INTERFACE_MODE_RGMII_ID;
bd0ceaab
KP		 3686 if (strcasecmp(phy_connection_type, "rgmii-txid") == 0)
3687 return PHY_INTERFACE_MODE_RGMII_TXID;
3688 if (strcasecmp(phy_connection_type, "rgmii-rxid") == 0)
3689 return PHY_INTERFACE_MODE_RGMII_RXID;
4e19b5c1 3690 if (strcasecmp(phy_connection_type, "rtbi") == 0)
728de4c9 3691 return PHY_INTERFACE_MODE_RTBI;
047584ce
HW		 3692 if (strcasecmp(phy_connection_type, "sgmii") == 0)
3693 return PHY_INTERFACE_MODE_SGMII;
728de4c9
KP		 3694
3695 return PHY_INTERFACE_MODE_MII;
3696}
3697
a9dbae78
JT		 3698static const struct net_device_ops ucc_geth_netdev_ops = {
3699 .ndo_open = ucc_geth_open,
3700 .ndo_stop = ucc_geth_close,
3701 .ndo_start_xmit = ucc_geth_start_xmit,
3702 .ndo_validate_addr = eth_validate_addr,
3d6593e9 3703 .ndo_set_mac_address = ucc_geth_set_mac_addr,
a9dbae78
JT		 3704 .ndo_change_mtu = eth_change_mtu,
3705 .ndo_set_multicast_list = ucc_geth_set_multi,
3706 .ndo_tx_timeout = ucc_geth_timeout,
3707#ifdef CONFIG_NET_POLL_CONTROLLER
3708 .ndo_poll_controller = ucc_netpoll,
3709#endif
3710};
3711
18a8e864 3712static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *match)
ce973b14 3713{
18a8e864
LY		 3714 struct device *device = &ofdev->dev;
3715 struct device_node *np = ofdev->node;
ce973b14
LY		 3716 struct net_device *dev = NULL;
3717 struct ucc_geth_private *ugeth = NULL;
3718 struct ucc_geth_info *ug_info;
18a8e864 3719 struct resource res;
728de4c9 3720 int err, ucc_num, max_speed = 0;
18a8e864 3721 const unsigned int *prop;
9fb1e350 3722 const char *sprop;
9b4c7a4e 3723 const void *mac_addr;
728de4c9
KP		 3724 phy_interface_t phy_interface;
3725 static const int enet_to_speed[] = {
3726 SPEED_10, SPEED_10, SPEED_10,
3727 SPEED_100, SPEED_100, SPEED_100,
3728 SPEED_1000, SPEED_1000, SPEED_1000, SPEED_1000,
3729 };
3730 static const phy_interface_t enet_to_phy_interface[] = {
3731 PHY_INTERFACE_MODE_MII, PHY_INTERFACE_MODE_RMII,
3732 PHY_INTERFACE_MODE_RGMII, PHY_INTERFACE_MODE_MII,
3733 PHY_INTERFACE_MODE_RMII, PHY_INTERFACE_MODE_RGMII,
3734 PHY_INTERFACE_MODE_GMII, PHY_INTERFACE_MODE_RGMII,
3735 PHY_INTERFACE_MODE_TBI, PHY_INTERFACE_MODE_RTBI,
047584ce 3736 PHY_INTERFACE_MODE_SGMII,
728de4c9 3737 };
ce973b14 3738
b39d66a8 3739 ugeth_vdbg("%s: IN", __func__);
ce973b14 3740
56626f33
AV		 3741 prop = of_get_property(np, "cell-index", NULL);
3742 if (!prop) {
3743 prop = of_get_property(np, "device-id", NULL);
3744 if (!prop)
3745 return -ENODEV;
3746 }
3747
18a8e864
LY		 3748 ucc_num = *prop - 1;
3749 if ((ucc_num < 0) || (ucc_num > 7))
3750 return -ENODEV;
3751
3752 ug_info = &ugeth_info[ucc_num];
890de95e
LY		 3753 if (ug_info == NULL) {
3754 if (netif_msg_probe(&debug))
3755 ugeth_err("%s: [%d] Missing additional data!",
b39d66a8 3756 __func__, ucc_num);
890de95e
LY		 3757 return -ENODEV;
3758 }
3759
18a8e864 3760 ug_info->uf_info.ucc_num = ucc_num;
728de4c9 3761
9fb1e350
TT		 3762 sprop = of_get_property(np, "rx-clock-name", NULL);
3763 if (sprop) {
3764 ug_info->uf_info.rx_clock = qe_clock_source(sprop);
3765 if ((ug_info->uf_info.rx_clock < QE_CLK_NONE) ||
3766 (ug_info->uf_info.rx_clock > QE_CLK24)) {
3767 printk(KERN_ERR
3768 "ucc_geth: invalid rx-clock-name property\n");
3769 return -EINVAL;
3770 }
3771 } else {
3772 prop = of_get_property(np, "rx-clock", NULL);
3773 if (!prop) {
3774 /* If both rx-clock-name and rx-clock are missing,
3775 we want to tell people to use rx-clock-name. */
3776 printk(KERN_ERR
3777 "ucc_geth: missing rx-clock-name property\n");
3778 return -EINVAL;
3779 }
3780 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3781 printk(KERN_ERR
3782 "ucc_geth: invalid rx-clock propperty\n");
3783 return -EINVAL;
3784 }
3785 ug_info->uf_info.rx_clock = *prop;
3786 }
3787
3788 sprop = of_get_property(np, "tx-clock-name", NULL);
3789 if (sprop) {
3790 ug_info->uf_info.tx_clock = qe_clock_source(sprop);
3791 if ((ug_info->uf_info.tx_clock < QE_CLK_NONE) ||
3792 (ug_info->uf_info.tx_clock > QE_CLK24)) {
3793 printk(KERN_ERR
3794 "ucc_geth: invalid tx-clock-name property\n");
3795 return -EINVAL;
3796 }
3797 } else {
e410553f 3798 prop = of_get_property(np, "tx-clock", NULL);
9fb1e350
TT		 3799 if (!prop) {
3800 printk(KERN_ERR
af901ca1 3801 "ucc_geth: missing tx-clock-name property\n");
9fb1e350
TT		 3802 return -EINVAL;
3803 }
3804 if ((*prop < QE_CLK_NONE) || (*prop > QE_CLK24)) {
3805 printk(KERN_ERR
3806 "ucc_geth: invalid tx-clock property\n");
3807 return -EINVAL;
3808 }
3809 ug_info->uf_info.tx_clock = *prop;
3810 }
3811
18a8e864
LY		 3812 err = of_address_to_resource(np, 0, &res);
3813 if (err)
3814 return -EINVAL;
3815
3816 ug_info->uf_info.regs = res.start;
3817 ug_info->uf_info.irq = irq_of_parse_and_map(np, 0);
3104a6ff
AV		 3818
3819 ug_info->phy_node = of_parse_phandle(np, "phy-handle", 0);
728de4c9 3820
fb1001f3
HW		 3821 /* Find the TBI PHY node. If it's not there, we don't support SGMII */
3822 ug_info->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
3823
728de4c9 3824 /* get the phy interface type, or default to MII */
4e19b5c1 3825 prop = of_get_property(np, "phy-connection-type", NULL);
728de4c9
KP		 3826 if (!prop) {
3827 /* handle interface property present in old trees */
3104a6ff 3828 prop = of_get_property(ug_info->phy_node, "interface", NULL);
4e19b5c1 3829 if (prop != NULL) {
728de4c9 3830 phy_interface = enet_to_phy_interface[*prop];
4e19b5c1
KP		 3831 max_speed = enet_to_speed[*prop];
3832 } else
728de4c9
KP		 3833 phy_interface = PHY_INTERFACE_MODE_MII;
3834 } else {
3835 phy_interface = to_phy_interface((const char *)prop);
3836 }
3837
4e19b5c1
KP		 3838 /* get speed, or derive from PHY interface */
3839 if (max_speed == 0)
728de4c9
KP		 3840 switch (phy_interface) {
3841 case PHY_INTERFACE_MODE_GMII:
3842 case PHY_INTERFACE_MODE_RGMII:
3843 case PHY_INTERFACE_MODE_RGMII_ID:
bd0ceaab
KP		 3844 case PHY_INTERFACE_MODE_RGMII_RXID:
3845 case PHY_INTERFACE_MODE_RGMII_TXID:
728de4c9
KP		 3846 case PHY_INTERFACE_MODE_TBI:
3847 case PHY_INTERFACE_MODE_RTBI:
047584ce 3848 case PHY_INTERFACE_MODE_SGMII:
728de4c9
KP		 3849 max_speed = SPEED_1000;
3850 break;
3851 default:
3852 max_speed = SPEED_100;
3853 break;
3854 }
728de4c9
KP		 3855
3856 if (max_speed == SPEED_1000) {
4e19b5c1 3857 /* configure muram FIFOs for gigabit operation */
728de4c9
KP		 3858 ug_info->uf_info.urfs = UCC_GETH_URFS_GIGA_INIT;
3859 ug_info->uf_info.urfet = UCC_GETH_URFET_GIGA_INIT;
3860 ug_info->uf_info.urfset = UCC_GETH_URFSET_GIGA_INIT;
3861 ug_info->uf_info.utfs = UCC_GETH_UTFS_GIGA_INIT;
3862 ug_info->uf_info.utfet = UCC_GETH_UTFET_GIGA_INIT;
3863 ug_info->uf_info.utftt = UCC_GETH_UTFTT_GIGA_INIT;
ffea31ed 3864 ug_info->numThreadsTx = UCC_GETH_NUM_OF_THREADS_4;
674e4f93
HW		 3865
3866 /* If QE's snum number is 46 which means we need to support
3867 * 4 UECs at 1000Base-T simultaneously, we need to allocate
3868 * more Threads to Rx.
3869 */
3870 if (qe_get_num_of_snums() == 46)
3871 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_6;
3872 else
3873 ug_info->numThreadsRx = UCC_GETH_NUM_OF_THREADS_4;
728de4c9
KP		 3874 }
3875
890de95e
LY		 3876 if (netif_msg_probe(&debug))
3877 printk(KERN_INFO "ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3878 ug_info->uf_info.ucc_num + 1, ug_info->uf_info.regs,
3879 ug_info->uf_info.irq);
ce973b14 3880
ce973b14
LY		 3881 /* Create an ethernet device instance */
3882 dev = alloc_etherdev(sizeof(*ugeth));
3883
3884 if (dev == NULL)
3885 return -ENOMEM;
3886
3887 ugeth = netdev_priv(dev);
3888 spin_lock_init(&ugeth->lock);
3889
80a9fad8
AV		 3890 /* Create CQs for hash tables */
3891 INIT_LIST_HEAD(&ugeth->group_hash_q);
3892 INIT_LIST_HEAD(&ugeth->ind_hash_q);
3893
ce973b14
LY		 3894 dev_set_drvdata(device, dev);
3895
3896 /* Set the dev->base_addr to the gfar reg region */
3897 dev->base_addr = (unsigned long)(ug_info->uf_info.regs);
3898
ce973b14
LY		 3899 SET_NETDEV_DEV(dev, device);
3900
3901 /* Fill in the dev structure */
ac421852 3902 uec_set_ethtool_ops(dev);
a9dbae78 3903 dev->netdev_ops = &ucc_geth_netdev_ops;
ce973b14 3904 dev->watchdog_timeo = TX_TIMEOUT;
1762a29a 3905 INIT_WORK(&ugeth->timeout_work, ucc_geth_timeout_work);
0cededf3 3906 netif_napi_add(dev, &ugeth->napi, ucc_geth_poll, 64);
ce973b14 3907 dev->mtu = 1500;
ce973b14 3908
890de95e 3909 ugeth->msg_enable = netif_msg_init(debug.msg_enable, UGETH_MSG_DEFAULT);
728de4c9
KP		 3910 ugeth->phy_interface = phy_interface;
3911 ugeth->max_speed = max_speed;
3912
ce973b14
LY		 3913 err = register_netdev(dev);
3914 if (err) {
890de95e
LY		 3915 if (netif_msg_probe(ugeth))
3916 ugeth_err("%s: Cannot register net device, aborting.",
3917 dev->name);
ce973b14
LY		 3918 free_netdev(dev);
3919 return err;
3920 }
3921
e9eb70c9 3922 mac_addr = of_get_mac_address(np);
9b4c7a4e
LY		 3923 if (mac_addr)
3924 memcpy(dev->dev_addr, mac_addr, 6);
ce973b14 3925
728de4c9 3926 ugeth->ug_info = ug_info;
da1aa63e
AV		 3927 ugeth->dev = device;
3928 ugeth->ndev = dev;
b1c4a9dd 3929 ugeth->node = np;
728de4c9 3930
ce973b14
LY		 3931 return 0;
3932}
3933
18a8e864 3934static int ucc_geth_remove(struct of_device* ofdev)
ce973b14 3935{
18a8e864 3936 struct device *device = &ofdev->dev;
ce973b14
LY		 3937 struct net_device *dev = dev_get_drvdata(device);
3938 struct ucc_geth_private *ugeth = netdev_priv(dev);
3939
80a9fad8 3940 unregister_netdev(dev);
ce973b14 3941 free_netdev(dev);
80a9fad8
AV		 3942 ucc_geth_memclean(ugeth);
3943 dev_set_drvdata(device, NULL);
ce973b14
LY		 3944
3945 return 0;
3946}
3947
18a8e864
LY		 3948static struct of_device_id ucc_geth_match[] = {
3949 {
3950 .type = "network",
3951 .compatible = "ucc_geth",
3952 },
3953 {},
3954};
3955
3956MODULE_DEVICE_TABLE(of, ucc_geth_match);
3957
3958static struct of_platform_driver ucc_geth_driver = {
3959 .name = DRV_NAME,
3960 .match_table = ucc_geth_match,
3961 .probe = ucc_geth_probe,
3962 .remove = ucc_geth_remove,
2394905f
AV		 3963 .suspend = ucc_geth_suspend,
3964 .resume = ucc_geth_resume,
ce973b14
LY		 3965};
3966
3967static int __init ucc_geth_init(void)
3968{
728de4c9
KP		 3969 int i, ret;
3970
890de95e
LY		 3971 if (netif_msg_drv(&debug))
3972 printk(KERN_INFO "ucc_geth: " DRV_DESC "\n");
ce973b14
LY		 3973 for (i = 0; i < 8; i++)
3974 memcpy(&(ugeth_info[i]), &ugeth_primary_info,
3975 sizeof(ugeth_primary_info));
3976
728de4c9
KP		 3977 ret = of_register_platform_driver(&ucc_geth_driver);
3978
728de4c9 3979 return ret;
ce973b14
LY		 3980}
3981
3982static void __exit ucc_geth_exit(void)
3983{
a4f0c2ca 3984 of_unregister_platform_driver(&ucc_geth_driver);
ce973b14
LY		 3985}
3986
3987module_init(ucc_geth_init);
3988module_exit(ucc_geth_exit);
3989
3990MODULE_AUTHOR("Freescale Semiconductor, Inc");
3991MODULE_DESCRIPTION(DRV_DESC);
c2bcf00b 3992MODULE_VERSION(DRV_VERSION);
ce973b14 3993MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree