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drivers/net: Remove address use from assignments of function pointers
[net-next-2.6.git] / drivers / net / tulip / winbond-840.c
CommitLineData
1da177e4
LT		 1/* winbond-840.c: A Linux PCI network adapter device driver. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
19
20 Do not remove the copyright information.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
23 as an improvement.
24
25 Changelog:
26 * ported to 2.4
27 ???
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
35 * further cleanups
36 power management.
37 support for big endian descriptors
38 Copyright (C) 2001 Manfred Spraul
39 * ethtool support (jgarzik)
40 * Replace some MII-related magic numbers with constants (jgarzik)
f3b197ac 41
1da177e4
LT		 42 TODO:
43 * enable pci_power_off
44 * Wake-On-LAN
45*/
f3b197ac 46
1da177e4 47#define DRV_NAME "winbond-840"
d5b20697
AG		 48#define DRV_VERSION "1.01-e"
49#define DRV_RELDATE "Sep-11-2006"
1da177e4
LT		 50
51
52/* Automatically extracted configuration info:
53probe-func: winbond840_probe
54config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
55
56c-help-name: Winbond W89c840 PCI Ethernet support
57c-help-symbol: CONFIG_WINBOND_840
58c-help: This driver is for the Winbond W89c840 chip. It also works with
59c-help: the TX9882 chip on the Compex RL100-ATX board.
f3b197ac 60c-help: More specific information and updates are available from
1da177e4
LT		 61c-help: http://www.scyld.com/network/drivers.html
62*/
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
68static int max_interrupt_work = 20;
69/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
70 The '840 uses a 64 element hash table based on the Ethernet CRC. */
71static int multicast_filter_limit = 32;
72
73/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
74 Setting to > 1518 effectively disables this feature. */
75static int rx_copybreak;
76
77/* Used to pass the media type, etc.
78 Both 'options[]' and 'full_duplex[]' should exist for driver
79 interoperability.
80 The media type is usually passed in 'options[]'.
81*/
82#define MAX_UNITS 8 /* More are supported, limit only on options */
83static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
84static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
85
86/* Operational parameters that are set at compile time. */
87
88/* Keep the ring sizes a power of two for compile efficiency.
89 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
90 Making the Tx ring too large decreases the effectiveness of channel
91 bonding and packet priority.
92 There are no ill effects from too-large receive rings. */
1da177e4
LT		 93#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
94#define TX_QUEUE_LEN_RESTART 5
1da177e4
LT		 95
96#define TX_BUFLIMIT (1024-128)
97
98/* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
99 To avoid overflowing we don't queue again until we have room for a
100 full-size packet.
101 */
102#define TX_FIFO_SIZE (2048)
103#define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
104
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
1da177e4
LT		 110/* Include files, designed to support most kernel versions 2.0.0 and later. */
111#include <linux/module.h>
112#include <linux/kernel.h>
113#include <linux/string.h>
114#include <linux/timer.h>
115#include <linux/errno.h>
116#include <linux/ioport.h>
1da177e4
LT		 117#include <linux/interrupt.h>
118#include <linux/pci.h>
10a87fcf 119#include <linux/dma-mapping.h>
1da177e4
LT		 120#include <linux/netdevice.h>
121#include <linux/etherdevice.h>
122#include <linux/skbuff.h>
123#include <linux/init.h>
124#include <linux/delay.h>
125#include <linux/ethtool.h>
126#include <linux/mii.h>
127#include <linux/rtnetlink.h>
128#include <linux/crc32.h>
129#include <linux/bitops.h>
130#include <asm/uaccess.h>
131#include <asm/processor.h> /* Processor type for cache alignment. */
132#include <asm/io.h>
133#include <asm/irq.h>
134
42eab567
GG		 135#include "tulip.h"
136
48dd59e3
JG		 137#undef PKT_BUF_SZ /* tulip.h also defines this */
138#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
139
1da177e4 140/* These identify the driver base version and may not be removed. */
03f54b3d
SH		 141static const char version[] __initconst =
142 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) "
143 DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
ad361c98 144 " http://www.scyld.com/network/drivers.html\n";
1da177e4
LT		 145
146MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
147MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
148MODULE_LICENSE("GPL");
149MODULE_VERSION(DRV_VERSION);
150
151module_param(max_interrupt_work, int, 0);
152module_param(debug, int, 0);
153module_param(rx_copybreak, int, 0);
154module_param(multicast_filter_limit, int, 0);
155module_param_array(options, int, NULL, 0);
156module_param_array(full_duplex, int, NULL, 0);
157MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
158MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
159MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
160MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
161MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
162MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
163
164/*
165 Theory of Operation
166
167I. Board Compatibility
168
169This driver is for the Winbond w89c840 chip.
170
171II. Board-specific settings
172
173None.
174
175III. Driver operation
176
177This chip is very similar to the Digital 21*4* "Tulip" family. The first
178twelve registers and the descriptor format are nearly identical. Read a
179Tulip manual for operational details.
180
181A significant difference is that the multicast filter and station address are
182stored in registers rather than loaded through a pseudo-transmit packet.
183
184Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
185full-sized packet we must use both data buffers in a descriptor. Thus the
186driver uses ring mode where descriptors are implicitly sequential in memory,
187rather than using the second descriptor address as a chain pointer to
188subsequent descriptors.
189
190IV. Notes
191
192If you are going to almost clone a Tulip, why not go all the way and avoid
193the need for a new driver?
194
195IVb. References
196
197http://www.scyld.com/expert/100mbps.html
198http://www.scyld.com/expert/NWay.html
199http://www.winbond.com.tw/
200
201IVc. Errata
202
203A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
204correctly detect a full FIFO, and queuing more than 2048 bytes may result in
205silent data corruption.
206
207Test with 'ping -s 10000' on a fast computer.
208
209*/
210
f3b197ac 211
1da177e4
LT		 212
213/*
214 PCI probe table.
215*/
1da177e4 216enum chip_capability_flags {
1f1bd5fc
JG		 217 CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,
218};
219
a3aa1884 220static DEFINE_PCI_DEVICE_TABLE(w840_pci_tbl) = {
1da177e4
LT		 221 { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
222 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
223 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
1f1bd5fc 224 { }
1da177e4
LT		 225};
226MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
227
c3d8e682
JG		 228enum {
229 netdev_res_size = 128, /* size of PCI BAR resource */
230};
231
1da177e4
LT		 232struct pci_id_info {
233 const char *name;
c3d8e682 234 int drv_flags; /* Driver use, intended as capability flags. */
1da177e4 235};
c3d8e682
JG		 236
237static const struct pci_id_info pci_id_tbl[] __devinitdata = {
238 { /* Sometime a Level-One switch card. */
239 "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII},
240 { "Winbond W89c840", CanHaveMII | HasBrokenTx},
241 { "Compex RL100-ATX", CanHaveMII | HasBrokenTx},
242 { } /* terminate list. */
1da177e4
LT		 243};
244
245/* This driver was written to use PCI memory space, however some x86 systems
42eab567
GG		 246 work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config
247*/
1da177e4
LT		 248
249/* Offsets to the Command and Status Registers, "CSRs".
250 While similar to the Tulip, these registers are longword aligned.
251 Note: It's not useful to define symbolic names for every register bit in
252 the device. The name can only partially document the semantics and make
253 the driver longer and more difficult to read.
254*/
255enum w840_offsets {
256 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
257 RxRingPtr=0x0C, TxRingPtr=0x10,
258 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
259 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
260 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
261 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
262 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
263};
264
1da177e4
LT		 265/* Bits in the NetworkConfig register. */
266enum rx_mode_bits {
42eab567
GG		 267 AcceptErr=0x80,
268 RxAcceptBroadcast=0x20, AcceptMulticast=0x10,
269 RxAcceptAllPhys=0x08, AcceptMyPhys=0x02,
1da177e4
LT		 270};
271
272enum mii_reg_bits {
273 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
274 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
275};
276
277/* The Tulip Rx and Tx buffer descriptors. */
278struct w840_rx_desc {
279 s32 status;
280 s32 length;
281 u32 buffer1;
282 u32 buffer2;
283};
284
285struct w840_tx_desc {
286 s32 status;
287 s32 length;
288 u32 buffer1, buffer2;
289};
290
1da177e4
LT		 291#define MII_CNT 1 /* winbond only supports one MII */
292struct netdev_private {
293 struct w840_rx_desc *rx_ring;
294 dma_addr_t rx_addr[RX_RING_SIZE];
295 struct w840_tx_desc *tx_ring;
296 dma_addr_t tx_addr[TX_RING_SIZE];
297 dma_addr_t ring_dma_addr;
298 /* The addresses of receive-in-place skbuffs. */
299 struct sk_buff* rx_skbuff[RX_RING_SIZE];
300 /* The saved address of a sent-in-place packet/buffer, for later free(). */
301 struct sk_buff* tx_skbuff[TX_RING_SIZE];
302 struct net_device_stats stats;
303 struct timer_list timer; /* Media monitoring timer. */
304 /* Frequently used values: keep some adjacent for cache effect. */
305 spinlock_t lock;
306 int chip_id, drv_flags;
307 struct pci_dev *pci_dev;
308 int csr6;
309 struct w840_rx_desc *rx_head_desc;
310 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
311 unsigned int rx_buf_sz; /* Based on MTU+slack. */
312 unsigned int cur_tx, dirty_tx;
313 unsigned int tx_q_bytes;
314 unsigned int tx_full; /* The Tx queue is full. */
315 /* MII transceiver section. */
316 int mii_cnt; /* MII device addresses. */
317 unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
318 u32 mii;
319 struct mii_if_info mii_if;
320 void __iomem *base_addr;
321};
322
323static int eeprom_read(void __iomem *ioaddr, int location);
324static int mdio_read(struct net_device *dev, int phy_id, int location);
325static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
326static int netdev_open(struct net_device *dev);
327static int update_link(struct net_device *dev);
328static void netdev_timer(unsigned long data);
329static void init_rxtx_rings(struct net_device *dev);
330static void free_rxtx_rings(struct netdev_private *np);
331static void init_registers(struct net_device *dev);
332static void tx_timeout(struct net_device *dev);
333static int alloc_ringdesc(struct net_device *dev);
334static void free_ringdesc(struct netdev_private *np);
ad096463 335static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 336static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4
LT		 337static void netdev_error(struct net_device *dev, int intr_status);
338static int netdev_rx(struct net_device *dev);
339static u32 __set_rx_mode(struct net_device *dev);
340static void set_rx_mode(struct net_device *dev);
341static struct net_device_stats *get_stats(struct net_device *dev);
342static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
7282d491 343static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 344static int netdev_close(struct net_device *dev);
345
2a97e6b7
SH		 346static const struct net_device_ops netdev_ops = {
347 .ndo_open = netdev_open,
348 .ndo_stop = netdev_close,
349 .ndo_start_xmit = start_tx,
350 .ndo_get_stats = get_stats,
351 .ndo_set_multicast_list = set_rx_mode,
352 .ndo_do_ioctl = netdev_ioctl,
353 .ndo_tx_timeout = tx_timeout,
354 .ndo_change_mtu = eth_change_mtu,
355 .ndo_set_mac_address = eth_mac_addr,
356 .ndo_validate_addr = eth_validate_addr,
357};
1da177e4
LT		 358
359static int __devinit w840_probe1 (struct pci_dev *pdev,
360 const struct pci_device_id *ent)
361{
362 struct net_device *dev;
363 struct netdev_private *np;
364 static int find_cnt;
365 int chip_idx = ent->driver_data;
366 int irq;
367 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
368 void __iomem *ioaddr;
1da177e4
LT		 369
370 i = pci_enable_device(pdev);
371 if (i) return i;
372
373 pci_set_master(pdev);
374
375 irq = pdev->irq;
376
284901a9 377 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
a1e37bc5
JP		 378 pr_warning("Winbond-840: Device %s disabled due to DMA limitations\n",
379 pci_name(pdev));
1da177e4
LT		 380 return -EIO;
381 }
382 dev = alloc_etherdev(sizeof(*np));
383 if (!dev)
384 return -ENOMEM;
1da177e4
LT		 385 SET_NETDEV_DEV(dev, &pdev->dev);
386
387 if (pci_request_regions(pdev, DRV_NAME))
388 goto err_out_netdev;
42eab567
GG		 389
390 ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
1da177e4
LT		 391 if (!ioaddr)
392 goto err_out_free_res;
393
394 for (i = 0; i < 3; i++)
c559a5bc 395 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(eeprom_read(ioaddr, i));
1da177e4
LT		 396
397 /* Reset the chip to erase previous misconfiguration.
398 No hold time required! */
399 iowrite32(0x00000001, ioaddr + PCIBusCfg);
400
401 dev->base_addr = (unsigned long)ioaddr;
402 dev->irq = irq;
403
404 np = netdev_priv(dev);
405 np->pci_dev = pdev;
406 np->chip_id = chip_idx;
407 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
408 spin_lock_init(&np->lock);
409 np->mii_if.dev = dev;
410 np->mii_if.mdio_read = mdio_read;
411 np->mii_if.mdio_write = mdio_write;
412 np->base_addr = ioaddr;
f3b197ac 413
1da177e4
LT		 414 pci_set_drvdata(pdev, dev);
415
416 if (dev->mem_start)
417 option = dev->mem_start;
418
419 /* The lower four bits are the media type. */
420 if (option > 0) {
421 if (option & 0x200)
422 np->mii_if.full_duplex = 1;
423 if (option & 15)
a1e37bc5
JP		 424 dev_info(&dev->dev,
425 "ignoring user supplied media type %d",
426 option & 15);
1da177e4
LT		 427 }
428 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
429 np->mii_if.full_duplex = 1;
430
431 if (np->mii_if.full_duplex)
432 np->mii_if.force_media = 1;
433
434 /* The chip-specific entries in the device structure. */
2a97e6b7 435 dev->netdev_ops = &netdev_ops;
1da177e4 436 dev->ethtool_ops = &netdev_ethtool_ops;
1da177e4
LT		 437 dev->watchdog_timeo = TX_TIMEOUT;
438
439 i = register_netdev(dev);
440 if (i)
441 goto err_out_cleardev;
442
a1e37bc5
JP		 443 dev_info(&dev->dev, "%s at %p, %pM, IRQ %d\n",
444 pci_id_tbl[chip_idx].name, ioaddr, dev->dev_addr, irq);
1da177e4
LT		 445
446 if (np->drv_flags & CanHaveMII) {
447 int phy, phy_idx = 0;
448 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
449 int mii_status = mdio_read(dev, phy, MII_BMSR);
450 if (mii_status != 0xffff && mii_status != 0x0000) {
451 np->phys[phy_idx++] = phy;
452 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
453 np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+
454 mdio_read(dev, phy, MII_PHYSID2);
a1e37bc5
JP		 455 dev_info(&dev->dev,
456 "MII PHY %08xh found at address %d, status 0x%04x advertising %04x\n",
457 np->mii, phy, mii_status,
458 np->mii_if.advertising);
1da177e4
LT		 459 }
460 }
461 np->mii_cnt = phy_idx;
462 np->mii_if.phy_id = np->phys[0];
463 if (phy_idx == 0) {
a1e37bc5
JP		 464 dev_warn(&dev->dev,
465 "MII PHY not found -- this device may not operate correctly\n");
1da177e4
LT		 466 }
467 }
468
469 find_cnt++;
470 return 0;
471
472err_out_cleardev:
473 pci_set_drvdata(pdev, NULL);
474 pci_iounmap(pdev, ioaddr);
475err_out_free_res:
476 pci_release_regions(pdev);
477err_out_netdev:
478 free_netdev (dev);
479 return -ENODEV;
480}
481
f3b197ac 482
1da177e4
LT		 483/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
484 often serial bit streams generated by the host processor.
485 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
486
487/* Delay between EEPROM clock transitions.
488 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
489 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
490 made udelay() unreliable.
491 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
405bbe9f 492 deprecated.
1da177e4
LT		 493*/
494#define eeprom_delay(ee_addr) ioread32(ee_addr)
495
496enum EEPROM_Ctrl_Bits {
497 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
498 EE_ChipSelect=0x801, EE_DataIn=0x08,
499};
500
501/* The EEPROM commands include the alway-set leading bit. */
502enum EEPROM_Cmds {
503 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
504};
505
506static int eeprom_read(void __iomem *addr, int location)
507{
508 int i;
509 int retval = 0;
510 void __iomem *ee_addr = addr + EECtrl;
511 int read_cmd = location | EE_ReadCmd;
512 iowrite32(EE_ChipSelect, ee_addr);
513
514 /* Shift the read command bits out. */
515 for (i = 10; i >= 0; i--) {
516 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
517 iowrite32(dataval, ee_addr);
518 eeprom_delay(ee_addr);
519 iowrite32(dataval | EE_ShiftClk, ee_addr);
520 eeprom_delay(ee_addr);
521 }
522 iowrite32(EE_ChipSelect, ee_addr);
523 eeprom_delay(ee_addr);
524
525 for (i = 16; i > 0; i--) {
526 iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr);
527 eeprom_delay(ee_addr);
528 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0);
529 iowrite32(EE_ChipSelect, ee_addr);
530 eeprom_delay(ee_addr);
531 }
532
533 /* Terminate the EEPROM access. */
534 iowrite32(0, ee_addr);
535 return retval;
536}
537
538/* MII transceiver control section.
539 Read and write the MII registers using software-generated serial
540 MDIO protocol. See the MII specifications or DP83840A data sheet
541 for details.
542
543 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
544 met by back-to-back 33Mhz PCI cycles. */
545#define mdio_delay(mdio_addr) ioread32(mdio_addr)
546
547/* Set iff a MII transceiver on any interface requires mdio preamble.
548 This only set with older transceivers, so the extra
549 code size of a per-interface flag is not worthwhile. */
550static char mii_preamble_required = 1;
551
552#define MDIO_WRITE0 (MDIO_EnbOutput)
553#define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
554
555/* Generate the preamble required for initial synchronization and
556 a few older transceivers. */
557static void mdio_sync(void __iomem *mdio_addr)
558{
559 int bits = 32;
560
561 /* Establish sync by sending at least 32 logic ones. */
562 while (--bits >= 0) {
563 iowrite32(MDIO_WRITE1, mdio_addr);
564 mdio_delay(mdio_addr);
565 iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
566 mdio_delay(mdio_addr);
567 }
568}
569
570static int mdio_read(struct net_device *dev, int phy_id, int location)
571{
572 struct netdev_private *np = netdev_priv(dev);
573 void __iomem *mdio_addr = np->base_addr + MIICtrl;
574 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
575 int i, retval = 0;
576
577 if (mii_preamble_required)
578 mdio_sync(mdio_addr);
579
580 /* Shift the read command bits out. */
581 for (i = 15; i >= 0; i--) {
582 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
583
584 iowrite32(dataval, mdio_addr);
585 mdio_delay(mdio_addr);
586 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
587 mdio_delay(mdio_addr);
588 }
589 /* Read the two transition, 16 data, and wire-idle bits. */
590 for (i = 20; i > 0; i--) {
591 iowrite32(MDIO_EnbIn, mdio_addr);
592 mdio_delay(mdio_addr);
593 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0);
594 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
595 mdio_delay(mdio_addr);
596 }
597 return (retval>>1) & 0xffff;
598}
599
600static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
601{
602 struct netdev_private *np = netdev_priv(dev);
603 void __iomem *mdio_addr = np->base_addr + MIICtrl;
604 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
605 int i;
606
607 if (location == 4 && phy_id == np->phys[0])
608 np->mii_if.advertising = value;
609
610 if (mii_preamble_required)
611 mdio_sync(mdio_addr);
612
613 /* Shift the command bits out. */
614 for (i = 31; i >= 0; i--) {
615 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
616
617 iowrite32(dataval, mdio_addr);
618 mdio_delay(mdio_addr);
619 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
620 mdio_delay(mdio_addr);
621 }
622 /* Clear out extra bits. */
623 for (i = 2; i > 0; i--) {
624 iowrite32(MDIO_EnbIn, mdio_addr);
625 mdio_delay(mdio_addr);
626 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
627 mdio_delay(mdio_addr);
628 }
1da177e4
LT		 629}
630
f3b197ac 631
1da177e4
LT		 632static int netdev_open(struct net_device *dev)
633{
634 struct netdev_private *np = netdev_priv(dev);
635 void __iomem *ioaddr = np->base_addr;
636 int i;
637
638 iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
639
640 netif_device_detach(dev);
a0607fd3 641 i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 642 if (i)
643 goto out_err;
644
645 if (debug > 1)
a1e37bc5
JP		 646 printk(KERN_DEBUG "%s: w89c840_open() irq %d\n",
647 dev->name, dev->irq);
1da177e4
LT		 648
649 if((i=alloc_ringdesc(dev)))
650 goto out_err;
651
652 spin_lock_irq(&np->lock);
653 netif_device_attach(dev);
654 init_registers(dev);
655 spin_unlock_irq(&np->lock);
656
657 netif_start_queue(dev);
658 if (debug > 2)
a1e37bc5 659 printk(KERN_DEBUG "%s: Done netdev_open()\n", dev->name);
1da177e4
LT		 660
661 /* Set the timer to check for link beat. */
662 init_timer(&np->timer);
663 np->timer.expires = jiffies + 1*HZ;
664 np->timer.data = (unsigned long)dev;
c061b18d 665 np->timer.function = netdev_timer; /* timer handler */
1da177e4
LT		 666 add_timer(&np->timer);
667 return 0;
668out_err:
669 netif_device_attach(dev);
670 return i;
671}
672
673#define MII_DAVICOM_DM9101 0x0181b800
674
675static int update_link(struct net_device *dev)
676{
677 struct netdev_private *np = netdev_priv(dev);
678 int duplex, fasteth, result, mii_reg;
679
680 /* BSMR */
681 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
682
683 if (mii_reg == 0xffff)
684 return np->csr6;
685 /* reread: the link status bit is sticky */
686 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
687 if (!(mii_reg & 0x4)) {
688 if (netif_carrier_ok(dev)) {
689 if (debug)
a1e37bc5
JP		 690 dev_info(&dev->dev,
691 "MII #%d reports no link. Disabling watchdog\n",
692 np->phys[0]);
1da177e4
LT		 693 netif_carrier_off(dev);
694 }
695 return np->csr6;
696 }
697 if (!netif_carrier_ok(dev)) {
698 if (debug)
a1e37bc5
JP		 699 dev_info(&dev->dev,
700 "MII #%d link is back. Enabling watchdog\n",
701 np->phys[0]);
1da177e4
LT		 702 netif_carrier_on(dev);
703 }
f3b197ac 704
1da177e4
LT		 705 if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
706 /* If the link partner doesn't support autonegotiation
707 * the MII detects it's abilities with the "parallel detection".
708 * Some MIIs update the LPA register to the result of the parallel
709 * detection, some don't.
710 * The Davicom PHY [at least 0181b800] doesn't.
711 * Instead bit 9 and 13 of the BMCR are updated to the result
712 * of the negotiation..
713 */
714 mii_reg = mdio_read(dev, np->phys[0], MII_BMCR);
715 duplex = mii_reg & BMCR_FULLDPLX;
716 fasteth = mii_reg & BMCR_SPEED100;
717 } else {
718 int negotiated;
719 mii_reg = mdio_read(dev, np->phys[0], MII_LPA);
720 negotiated = mii_reg & np->mii_if.advertising;
721
722 duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL);
723 fasteth = negotiated & 0x380;
724 }
725 duplex |= np->mii_if.force_media;
726 /* remove fastether and fullduplex */
727 result = np->csr6 & ~0x20000200;
728 if (duplex)
729 result |= 0x200;
730 if (fasteth)
731 result |= 0x20000000;
732 if (result != np->csr6 && debug)
a1e37bc5
JP		 733 dev_info(&dev->dev,
734 "Setting %dMBit-%s-duplex based on MII#%d\n",
735 fasteth ? 100 : 10, duplex ? "full" : "half",
736 np->phys[0]);
1da177e4
LT		 737 return result;
738}
739
740#define RXTX_TIMEOUT 2000
741static inline void update_csr6(struct net_device *dev, int new)
742{
743 struct netdev_private *np = netdev_priv(dev);
744 void __iomem *ioaddr = np->base_addr;
745 int limit = RXTX_TIMEOUT;
746
747 if (!netif_device_present(dev))
748 new = 0;
749 if (new==np->csr6)
750 return;
751 /* stop both Tx and Rx processes */
752 iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
753 /* wait until they have really stopped */
754 for (;;) {
755 int csr5 = ioread32(ioaddr + IntrStatus);
756 int t;
757
758 t = (csr5 >> 17) & 0x07;
759 if (t==0||t==1) {
760 /* rx stopped */
761 t = (csr5 >> 20) & 0x07;
762 if (t==0||t==1)
763 break;
764 }
765
766 limit--;
767 if(!limit) {
a1e37bc5
JP		 768 dev_info(&dev->dev,
769 "couldn't stop rxtx, IntrStatus %xh\n", csr5);
1da177e4
LT		 770 break;
771 }
772 udelay(1);
773 }
774 np->csr6 = new;
775 /* and restart them with the new configuration */
776 iowrite32(np->csr6, ioaddr + NetworkConfig);
777 if (new & 0x200)
778 np->mii_if.full_duplex = 1;
779}
780
781static void netdev_timer(unsigned long data)
782{
783 struct net_device *dev = (struct net_device *)data;
784 struct netdev_private *np = netdev_priv(dev);
785 void __iomem *ioaddr = np->base_addr;
786
787 if (debug > 2)
a1e37bc5
JP		 788 printk(KERN_DEBUG "%s: Media selection timer tick, status %08x config %08x\n",
789 dev->name, ioread32(ioaddr + IntrStatus),
790 ioread32(ioaddr + NetworkConfig));
1da177e4
LT		 791 spin_lock_irq(&np->lock);
792 update_csr6(dev, update_link(dev));
793 spin_unlock_irq(&np->lock);
794 np->timer.expires = jiffies + 10*HZ;
795 add_timer(&np->timer);
796}
797
798static void init_rxtx_rings(struct net_device *dev)
799{
800 struct netdev_private *np = netdev_priv(dev);
801 int i;
802
803 np->rx_head_desc = &np->rx_ring[0];
804 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
805
806 /* Initial all Rx descriptors. */
807 for (i = 0; i < RX_RING_SIZE; i++) {
808 np->rx_ring[i].length = np->rx_buf_sz;
809 np->rx_ring[i].status = 0;
810 np->rx_skbuff[i] = NULL;
811 }
812 /* Mark the last entry as wrapping the ring. */
813 np->rx_ring[i-1].length |= DescEndRing;
814
815 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
816 for (i = 0; i < RX_RING_SIZE; i++) {
817 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
818 np->rx_skbuff[i] = skb;
819 if (skb == NULL)
820 break;
689be439 821 np->rx_addr[i] = pci_map_single(np->pci_dev,skb->data,
bb02aacc 822 np->rx_buf_sz,PCI_DMA_FROMDEVICE);
1da177e4
LT		 823
824 np->rx_ring[i].buffer1 = np->rx_addr[i];
42eab567 825 np->rx_ring[i].status = DescOwned;
1da177e4
LT		 826 }
827
828 np->cur_rx = 0;
829 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
830
831 /* Initialize the Tx descriptors */
832 for (i = 0; i < TX_RING_SIZE; i++) {
833 np->tx_skbuff[i] = NULL;
834 np->tx_ring[i].status = 0;
835 }
836 np->tx_full = 0;
837 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
838
839 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
840 iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
841 np->base_addr + TxRingPtr);
842
843}
844
845static void free_rxtx_rings(struct netdev_private* np)
846{
847 int i;
848 /* Free all the skbuffs in the Rx queue. */
849 for (i = 0; i < RX_RING_SIZE; i++) {
850 np->rx_ring[i].status = 0;
851 if (np->rx_skbuff[i]) {
852 pci_unmap_single(np->pci_dev,
853 np->rx_addr[i],
854 np->rx_skbuff[i]->len,
855 PCI_DMA_FROMDEVICE);
856 dev_kfree_skb(np->rx_skbuff[i]);
857 }
858 np->rx_skbuff[i] = NULL;
859 }
860 for (i = 0; i < TX_RING_SIZE; i++) {
861 if (np->tx_skbuff[i]) {
862 pci_unmap_single(np->pci_dev,
863 np->tx_addr[i],
864 np->tx_skbuff[i]->len,
865 PCI_DMA_TODEVICE);
866 dev_kfree_skb(np->tx_skbuff[i]);
867 }
868 np->tx_skbuff[i] = NULL;
869 }
870}
871
872static void init_registers(struct net_device *dev)
873{
874 struct netdev_private *np = netdev_priv(dev);
875 void __iomem *ioaddr = np->base_addr;
876 int i;
877
878 for (i = 0; i < 6; i++)
879 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
880
881 /* Initialize other registers. */
882#ifdef __BIG_ENDIAN
883 i = (1<<20); /* Big-endian descriptors */
884#else
885 i = 0;
886#endif
887 i |= (0x04<<2); /* skip length 4 u32 */
888 i |= 0x02; /* give Rx priority */
889
890 /* Configure the PCI bus bursts and FIFO thresholds.
891 486: Set 8 longword cache alignment, 8 longword burst.
892 586: Set 16 longword cache alignment, no burst limit.
893 Cache alignment bits 15:14 Burst length 13:8
894 0000 <not allowed> 0000 align to cache 0800 8 longwords
895 4000 8 longwords 0100 1 longword 1000 16 longwords
896 8000 16 longwords 0200 2 longwords 2000 32 longwords
897 C000 32 longwords 0400 4 longwords */
898
899#if defined (__i386__) && !defined(MODULE)
900 /* When not a module we can work around broken '486 PCI boards. */
901 if (boot_cpu_data.x86 <= 4) {
902 i |= 0x4800;
a1e37bc5
JP		 903 dev_info(&dev->dev,
904 "This is a 386/486 PCI system, setting cache alignment to 8 longwords\n");
1da177e4
LT		 905 } else {
906 i |= 0xE000;
907 }
908#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
909 i |= 0xE000;
49345103 910#elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC)
1da177e4
LT		 911 i |= 0x4800;
912#else
913#warning Processor architecture undefined
914 i |= 0x4800;
915#endif
916 iowrite32(i, ioaddr + PCIBusCfg);
917
918 np->csr6 = 0;
f3b197ac 919 /* 128 byte Tx threshold;
1da177e4
LT		 920 Transmit on; Receive on; */
921 update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
922
923 /* Clear and Enable interrupts by setting the interrupt mask. */
924 iowrite32(0x1A0F5, ioaddr + IntrStatus);
925 iowrite32(0x1A0F5, ioaddr + IntrEnable);
926
927 iowrite32(0, ioaddr + RxStartDemand);
928}
929
930static void tx_timeout(struct net_device *dev)
931{
932 struct netdev_private *np = netdev_priv(dev);
933 void __iomem *ioaddr = np->base_addr;
934
a1e37bc5
JP		 935 dev_warn(&dev->dev, "Transmit timed out, status %08x, resetting...\n",
936 ioread32(ioaddr + IntrStatus));
1da177e4
LT		 937
938 {
939 int i;
940 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
941 for (i = 0; i < RX_RING_SIZE; i++)
a1e37bc5
JP		 942 printk(KERN_CONT " %08x", (unsigned int)np->rx_ring[i].status);
943 printk(KERN_CONT "\n");
944 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1da177e4 945 for (i = 0; i < TX_RING_SIZE; i++)
a1e37bc5
JP		 946 printk(KERN_CONT " %08x", np->tx_ring[i].status);
947 printk(KERN_CONT "\n");
1da177e4 948 }
a1e37bc5
JP		 949 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d\n",
950 np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
951 printk(KERN_DEBUG "Tx Descriptor addr %xh\n", ioread32(ioaddr+0x4C));
1da177e4
LT		 952
953 disable_irq(dev->irq);
954 spin_lock_irq(&np->lock);
955 /*
956 * Under high load dirty_tx and the internal tx descriptor pointer
957 * come out of sync, thus perform a software reset and reinitialize
958 * everything.
959 */
960
961 iowrite32(1, np->base_addr+PCIBusCfg);
962 udelay(1);
963
964 free_rxtx_rings(np);
965 init_rxtx_rings(dev);
966 init_registers(dev);
967 spin_unlock_irq(&np->lock);
968 enable_irq(dev->irq);
969
970 netif_wake_queue(dev);
1ae5dc34 971 dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4 972 np->stats.tx_errors++;
1da177e4
LT		 973}
974
975/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
976static int alloc_ringdesc(struct net_device *dev)
977{
978 struct netdev_private *np = netdev_priv(dev);
979
980 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
981
982 np->rx_ring = pci_alloc_consistent(np->pci_dev,
983 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
984 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
985 &np->ring_dma_addr);
986 if(!np->rx_ring)
987 return -ENOMEM;
988 init_rxtx_rings(dev);
989 return 0;
990}
991
992static void free_ringdesc(struct netdev_private *np)
993{
994 pci_free_consistent(np->pci_dev,
995 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
996 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
997 np->rx_ring, np->ring_dma_addr);
998
999}
1000
ad096463 1001static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 1002{
1003 struct netdev_private *np = netdev_priv(dev);
1004 unsigned entry;
1005
1006 /* Caution: the write order is important here, set the field
1007 with the "ownership" bits last. */
1008
1009 /* Calculate the next Tx descriptor entry. */
1010 entry = np->cur_tx % TX_RING_SIZE;
1011
1012 np->tx_addr[entry] = pci_map_single(np->pci_dev,
1013 skb->data,skb->len, PCI_DMA_TODEVICE);
1014 np->tx_skbuff[entry] = skb;
1015
1016 np->tx_ring[entry].buffer1 = np->tx_addr[entry];
1017 if (skb->len < TX_BUFLIMIT) {
1018 np->tx_ring[entry].length = DescWholePkt | skb->len;
1019 } else {
1020 int len = skb->len - TX_BUFLIMIT;
1021
1022 np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
1023 np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
1024 }
1025 if(entry == TX_RING_SIZE-1)
1026 np->tx_ring[entry].length |= DescEndRing;
1027
1028 /* Now acquire the irq spinlock.
59c51591 1029 * The difficult race is the ordering between
42eab567 1030 * increasing np->cur_tx and setting DescOwned:
1da177e4
LT		 1031 * - if np->cur_tx is increased first the interrupt
1032 * handler could consider the packet as transmitted
42eab567
GG		 1033 * since DescOwned is cleared.
1034 * - If DescOwned is set first the NIC could report the
1da177e4
LT		 1035 * packet as sent, but the interrupt handler would ignore it
1036 * since the np->cur_tx was not yet increased.
1037 */
1038 spin_lock_irq(&np->lock);
1039 np->cur_tx++;
1040
1041 wmb(); /* flush length, buffer1, buffer2 */
42eab567 1042 np->tx_ring[entry].status = DescOwned;
1da177e4
LT		 1043 wmb(); /* flush status and kick the hardware */
1044 iowrite32(0, np->base_addr + TxStartDemand);
1045 np->tx_q_bytes += skb->len;
1046 /* Work around horrible bug in the chip by marking the queue as full
1047 when we do not have FIFO room for a maximum sized packet. */
1048 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
1049 ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
1050 netif_stop_queue(dev);
1051 wmb();
1052 np->tx_full = 1;
1053 }
1054 spin_unlock_irq(&np->lock);
1055
1da177e4 1056 if (debug > 4) {
a1e37bc5
JP		 1057 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d\n",
1058 dev->name, np->cur_tx, entry);
1da177e4 1059 }
6ed10654 1060 return NETDEV_TX_OK;
1da177e4
LT		 1061}
1062
1063static void netdev_tx_done(struct net_device *dev)
1064{
1065 struct netdev_private *np = netdev_priv(dev);
1066 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1067 int entry = np->dirty_tx % TX_RING_SIZE;
1068 int tx_status = np->tx_ring[entry].status;
1069
1070 if (tx_status < 0)
1071 break;
1072 if (tx_status & 0x8000) { /* There was an error, log it. */
1073#ifndef final_version
1074 if (debug > 1)
a1e37bc5
JP		 1075 printk(KERN_DEBUG "%s: Transmit error, Tx status %08x\n",
1076 dev->name, tx_status);
1da177e4
LT		 1077#endif
1078 np->stats.tx_errors++;
1079 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1080 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1081 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1082 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1083 if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0)
1084 np->stats.tx_heartbeat_errors++;
1085 } else {
1086#ifndef final_version
1087 if (debug > 3)
a1e37bc5
JP		 1088 printk(KERN_DEBUG "%s: Transmit slot %d ok, Tx status %08x\n",
1089 dev->name, entry, tx_status);
1da177e4
LT		 1090#endif
1091 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1092 np->stats.collisions += (tx_status >> 3) & 15;
1093 np->stats.tx_packets++;
1094 }
1095 /* Free the original skb. */
1096 pci_unmap_single(np->pci_dev,np->tx_addr[entry],
1097 np->tx_skbuff[entry]->len,
1098 PCI_DMA_TODEVICE);
1099 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1100 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1101 np->tx_skbuff[entry] = NULL;
1102 }
1103 if (np->tx_full &&
1104 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
1105 np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1106 /* The ring is no longer full, clear tbusy. */
1107 np->tx_full = 0;
1108 wmb();
1109 netif_wake_queue(dev);
1110 }
1111}
1112
1113/* The interrupt handler does all of the Rx thread work and cleans up
1114 after the Tx thread. */
7d12e780 1115static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 1116{
1117 struct net_device *dev = (struct net_device *)dev_instance;
1118 struct netdev_private *np = netdev_priv(dev);
1119 void __iomem *ioaddr = np->base_addr;
1120 int work_limit = max_interrupt_work;
1121 int handled = 0;
1122
1123 if (!netif_device_present(dev))
1124 return IRQ_NONE;
1125 do {
1126 u32 intr_status = ioread32(ioaddr + IntrStatus);
1127
1128 /* Acknowledge all of the current interrupt sources ASAP. */
1129 iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus);
1130
1131 if (debug > 4)
a1e37bc5
JP		 1132 printk(KERN_DEBUG "%s: Interrupt, status %04x\n",
1133 dev->name, intr_status);
1da177e4
LT		 1134
1135 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1136 break;
1137
1138 handled = 1;
1139
42eab567 1140 if (intr_status & (RxIntr | RxNoBuf))
1da177e4
LT		 1141 netdev_rx(dev);
1142 if (intr_status & RxNoBuf)
1143 iowrite32(0, ioaddr + RxStartDemand);
1144
42eab567 1145 if (intr_status & (TxNoBuf | TxIntr) &&
1da177e4
LT		 1146 np->cur_tx != np->dirty_tx) {
1147 spin_lock(&np->lock);
1148 netdev_tx_done(dev);
1149 spin_unlock(&np->lock);
1150 }
1151
1152 /* Abnormal error summary/uncommon events handlers. */
1ddb9861 1153 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError |
42eab567 1154 TimerInt | TxDied))
1da177e4
LT		 1155 netdev_error(dev, intr_status);
1156
1157 if (--work_limit < 0) {
a1e37bc5
JP		 1158 dev_warn(&dev->dev,
1159 "Too much work at interrupt, status=0x%04x\n",
1160 intr_status);
1da177e4
LT		 1161 /* Set the timer to re-enable the other interrupts after
1162 10*82usec ticks. */
1163 spin_lock(&np->lock);
1164 if (netif_device_present(dev)) {
1165 iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1166 iowrite32(10, ioaddr + GPTimer);
1167 }
1168 spin_unlock(&np->lock);
1169 break;
1170 }
1171 } while (1);
1172
1173 if (debug > 3)
a1e37bc5
JP		 1174 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x\n",
1175 dev->name, ioread32(ioaddr + IntrStatus));
1da177e4
LT		 1176 return IRQ_RETVAL(handled);
1177}
1178
1179/* This routine is logically part of the interrupt handler, but separated
1180 for clarity and better register allocation. */
1181static int netdev_rx(struct net_device *dev)
1182{
1183 struct netdev_private *np = netdev_priv(dev);
1184 int entry = np->cur_rx % RX_RING_SIZE;
1185 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1186
1187 if (debug > 4) {
a1e37bc5
JP		 1188 printk(KERN_DEBUG " In netdev_rx(), entry %d status %04x\n",
1189 entry, np->rx_ring[entry].status);
1da177e4
LT		 1190 }
1191
1192 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1193 while (--work_limit >= 0) {
1194 struct w840_rx_desc *desc = np->rx_head_desc;
1195 s32 status = desc->status;
1196
1197 if (debug > 4)
a1e37bc5
JP		 1198 printk(KERN_DEBUG " netdev_rx() status was %08x\n",
1199 status);
1da177e4
LT		 1200 if (status < 0)
1201 break;
1202 if ((status & 0x38008300) != 0x0300) {
1203 if ((status & 0x38000300) != 0x0300) {
1204 /* Ingore earlier buffers. */
1205 if ((status & 0xffff) != 0x7fff) {
a1e37bc5
JP		 1206 dev_warn(&dev->dev,
1207 "Oversized Ethernet frame spanned multiple buffers, entry %#x status %04x!\n",
1208 np->cur_rx, status);
1da177e4
LT		 1209 np->stats.rx_length_errors++;
1210 }
1211 } else if (status & 0x8000) {
1212 /* There was a fatal error. */
1213 if (debug > 2)
a1e37bc5
JP		 1214 printk(KERN_DEBUG "%s: Receive error, Rx status %08x\n",
1215 dev->name, status);
1da177e4
LT		 1216 np->stats.rx_errors++; /* end of a packet.*/
1217 if (status & 0x0890) np->stats.rx_length_errors++;
1218 if (status & 0x004C) np->stats.rx_frame_errors++;
1219 if (status & 0x0002) np->stats.rx_crc_errors++;
1220 }
1221 } else {
1222 struct sk_buff *skb;
1223 /* Omit the four octet CRC from the length. */
1224 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1225
1226#ifndef final_version
1227 if (debug > 4)
a1e37bc5
JP		 1228 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d status %x\n",
1229 pkt_len, status);
1da177e4
LT		 1230#endif
1231 /* Check if the packet is long enough to accept without copying
1232 to a minimally-sized skbuff. */
8e95a202
JP		 1233 if (pkt_len < rx_copybreak &&
1234 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 1235 skb_reserve(skb, 2); /* 16 byte align the IP header */
1236 pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry],
1237 np->rx_skbuff[entry]->len,
1238 PCI_DMA_FROMDEVICE);
8c7b7faa 1239 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 1240 skb_put(skb, pkt_len);
1241 pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry],
1242 np->rx_skbuff[entry]->len,
1243 PCI_DMA_FROMDEVICE);
1244 } else {
1245 pci_unmap_single(np->pci_dev,np->rx_addr[entry],
1246 np->rx_skbuff[entry]->len,
1247 PCI_DMA_FROMDEVICE);
1248 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1249 np->rx_skbuff[entry] = NULL;
1250 }
1251#ifndef final_version /* Remove after testing. */
1252 /* You will want this info for the initial debug. */
e174961c 1253 if (debug > 5)
a1e37bc5 1254 printk(KERN_DEBUG " Rx data %pM %pM %02x%02x %pI4\n",
e174961c 1255 &skb->data[0], &skb->data[6],
0795af57 1256 skb->data[12], skb->data[13],
a1e37bc5 1257 &skb->data[14]);
1da177e4
LT		 1258#endif
1259 skb->protocol = eth_type_trans(skb, dev);
1260 netif_rx(skb);
1da177e4
LT		 1261 np->stats.rx_packets++;
1262 np->stats.rx_bytes += pkt_len;
1263 }
1264 entry = (++np->cur_rx) % RX_RING_SIZE;
1265 np->rx_head_desc = &np->rx_ring[entry];
1266 }
1267
1268 /* Refill the Rx ring buffers. */
1269 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1270 struct sk_buff *skb;
1271 entry = np->dirty_rx % RX_RING_SIZE;
1272 if (np->rx_skbuff[entry] == NULL) {
1273 skb = dev_alloc_skb(np->rx_buf_sz);
1274 np->rx_skbuff[entry] = skb;
1275 if (skb == NULL)
1276 break; /* Better luck next round. */
1da177e4 1277 np->rx_addr[entry] = pci_map_single(np->pci_dev,
689be439 1278 skb->data,
bb02aacc 1279 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1280 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1281 }
1282 wmb();
42eab567 1283 np->rx_ring[entry].status = DescOwned;
1da177e4
LT		 1284 }
1285
1286 return 0;
1287}
1288
1289static void netdev_error(struct net_device *dev, int intr_status)
1290{
1291 struct netdev_private *np = netdev_priv(dev);
1292 void __iomem *ioaddr = np->base_addr;
1293
1294 if (debug > 2)
a1e37bc5
JP		 1295 printk(KERN_DEBUG "%s: Abnormal event, %08x\n",
1296 dev->name, intr_status);
1da177e4
LT		 1297 if (intr_status == 0xffffffff)
1298 return;
1299 spin_lock(&np->lock);
1300 if (intr_status & TxFIFOUnderflow) {
1301 int new;
1302 /* Bump up the Tx threshold */
1303#if 0
1304 /* This causes lots of dropped packets,
1305 * and under high load even tx_timeouts
1306 */
1307 new = np->csr6 + 0x4000;
1308#else
1309 new = (np->csr6 >> 14)&0x7f;
1310 if (new < 64)
1311 new *= 2;
1312 else
1313 new = 127; /* load full packet before starting */
1314 new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
1315#endif
a1e37bc5
JP		 1316 printk(KERN_DEBUG "%s: Tx underflow, new csr6 %08x\n",
1317 dev->name, new);
1da177e4
LT		 1318 update_csr6(dev, new);
1319 }
42eab567 1320 if (intr_status & RxDied) { /* Missed a Rx frame. */
1da177e4
LT		 1321 np->stats.rx_errors++;
1322 }
1323 if (intr_status & TimerInt) {
1324 /* Re-enable other interrupts. */
1325 if (netif_device_present(dev))
1326 iowrite32(0x1A0F5, ioaddr + IntrEnable);
1327 }
1328 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1329 iowrite32(0, ioaddr + RxStartDemand);
1330 spin_unlock(&np->lock);
1331}
1332
1333static struct net_device_stats *get_stats(struct net_device *dev)
1334{
1335 struct netdev_private *np = netdev_priv(dev);
1336 void __iomem *ioaddr = np->base_addr;
1337
1338 /* The chip only need report frame silently dropped. */
1339 spin_lock_irq(&np->lock);
1340 if (netif_running(dev) && netif_device_present(dev))
1341 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1342 spin_unlock_irq(&np->lock);
1343
1344 return &np->stats;
1345}
1346
1347
1348static u32 __set_rx_mode(struct net_device *dev)
1349{
1350 struct netdev_private *np = netdev_priv(dev);
1351 void __iomem *ioaddr = np->base_addr;
1352 u32 mc_filter[2]; /* Multicast hash filter */
1353 u32 rx_mode;
1354
1355 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4 1356 memset(mc_filter, 0xff, sizeof(mc_filter));
42eab567 1357 rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys
1da177e4 1358 | AcceptMyPhys;
4cd24eaf 1359 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 1360 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 1361 /* Too many to match, or accept all multicasts. */
1362 memset(mc_filter, 0xff, sizeof(mc_filter));
42eab567 1363 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1da177e4 1364 } else {
22bedad3 1365 struct netdev_hw_addr *ha;
4302b67e 1366
1da177e4 1367 memset(mc_filter, 0, sizeof(mc_filter));
22bedad3
JP		 1368 netdev_for_each_mc_addr(ha, dev) {
1369 int filbit;
1370
1371 filbit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1372 filbit &= 0x3f;
1373 mc_filter[filbit >> 5] |= 1 << (filbit & 31);
1da177e4 1374 }
42eab567 1375 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1da177e4
LT		 1376 }
1377 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1378 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1379 return rx_mode;
1380}
1381
1382static void set_rx_mode(struct net_device *dev)
1383{
1384 struct netdev_private *np = netdev_priv(dev);
1385 u32 rx_mode = __set_rx_mode(dev);
1386 spin_lock_irq(&np->lock);
1387 update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
1388 spin_unlock_irq(&np->lock);
1389}
1390
1391static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1392{
1393 struct netdev_private *np = netdev_priv(dev);
1394
1395 strcpy (info->driver, DRV_NAME);
1396 strcpy (info->version, DRV_VERSION);
1397 strcpy (info->bus_info, pci_name(np->pci_dev));
1398}
1399
1400static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1401{
1402 struct netdev_private *np = netdev_priv(dev);
1403 int rc;
1404
1405 spin_lock_irq(&np->lock);
1406 rc = mii_ethtool_gset(&np->mii_if, cmd);
1407 spin_unlock_irq(&np->lock);
1408
1409 return rc;
1410}
1411
1412static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1413{
1414 struct netdev_private *np = netdev_priv(dev);
1415 int rc;
1416
1417 spin_lock_irq(&np->lock);
1418 rc = mii_ethtool_sset(&np->mii_if, cmd);
1419 spin_unlock_irq(&np->lock);
1420
1421 return rc;
1422}
1423
1424static int netdev_nway_reset(struct net_device *dev)
1425{
1426 struct netdev_private *np = netdev_priv(dev);
1427 return mii_nway_restart(&np->mii_if);
1428}
1429
1430static u32 netdev_get_link(struct net_device *dev)
1431{
1432 struct netdev_private *np = netdev_priv(dev);
1433 return mii_link_ok(&np->mii_if);
1434}
1435
1436static u32 netdev_get_msglevel(struct net_device *dev)
1437{
1438 return debug;
1439}
1440
1441static void netdev_set_msglevel(struct net_device *dev, u32 value)
1442{
1443 debug = value;
1444}
1445
7282d491 1446static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 1447 .get_drvinfo = netdev_get_drvinfo,
1448 .get_settings = netdev_get_settings,
1449 .set_settings = netdev_set_settings,
1450 .nway_reset = netdev_nway_reset,
1451 .get_link = netdev_get_link,
1452 .get_msglevel = netdev_get_msglevel,
1453 .set_msglevel = netdev_set_msglevel,
1da177e4
LT		 1454};
1455
1456static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1457{
1458 struct mii_ioctl_data *data = if_mii(rq);
1459 struct netdev_private *np = netdev_priv(dev);
1460
1461 switch(cmd) {
1462 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1463 data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f;
1464 /* Fall Through */
1465
1466 case SIOCGMIIREG: /* Read MII PHY register. */
1467 spin_lock_irq(&np->lock);
1468 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1469 spin_unlock_irq(&np->lock);
1470 return 0;
1471
1472 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT		 1473 spin_lock_irq(&np->lock);
1474 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1475 spin_unlock_irq(&np->lock);
1476 return 0;
1477 default:
1478 return -EOPNOTSUPP;
1479 }
1480}
1481
1482static int netdev_close(struct net_device *dev)
1483{
1484 struct netdev_private *np = netdev_priv(dev);
1485 void __iomem *ioaddr = np->base_addr;
1486
1487 netif_stop_queue(dev);
1488
1489 if (debug > 1) {
a1e37bc5
JP		 1490 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %08x Config %08x\n",
1491 dev->name, ioread32(ioaddr + IntrStatus),
1492 ioread32(ioaddr + NetworkConfig));
1493 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d\n",
1494 dev->name,
1495 np->cur_tx, np->dirty_tx,
1496 np->cur_rx, np->dirty_rx);
1da177e4
LT		 1497 }
1498
1499 /* Stop the chip's Tx and Rx processes. */
1500 spin_lock_irq(&np->lock);
1501 netif_device_detach(dev);
1502 update_csr6(dev, 0);
1503 iowrite32(0x0000, ioaddr + IntrEnable);
1504 spin_unlock_irq(&np->lock);
1505
1506 free_irq(dev->irq, dev);
1507 wmb();
1508 netif_device_attach(dev);
1509
1510 if (ioread32(ioaddr + NetworkConfig) != 0xffffffff)
1511 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1512
1513#ifdef __i386__
1514 if (debug > 2) {
1515 int i;
1516
8aa06af4 1517 printk(KERN_DEBUG" Tx ring at %p:\n", np->tx_ring);
1da177e4 1518 for (i = 0; i < TX_RING_SIZE; i++)
a1e37bc5
JP		 1519 printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
1520 i, np->tx_ring[i].length,
1521 np->tx_ring[i].status, np->tx_ring[i].buffer1);
8aa06af4 1522 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring);
1da177e4 1523 for (i = 0; i < RX_RING_SIZE; i++) {
a1e37bc5
JP		 1524 printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
1525 i, np->rx_ring[i].length,
1526 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1da177e4
LT		 1527 }
1528 }
1529#endif /* __i386__ debugging only */
1530
1531 del_timer_sync(&np->timer);
1532
1533 free_rxtx_rings(np);
1534 free_ringdesc(np);
1535
1536 return 0;
1537}
1538
1539static void __devexit w840_remove1 (struct pci_dev *pdev)
1540{
1541 struct net_device *dev = pci_get_drvdata(pdev);
f3b197ac 1542
1da177e4
LT		 1543 if (dev) {
1544 struct netdev_private *np = netdev_priv(dev);
1545 unregister_netdev(dev);
1546 pci_release_regions(pdev);
1547 pci_iounmap(pdev, np->base_addr);
1548 free_netdev(dev);
1549 }
1550
1551 pci_set_drvdata(pdev, NULL);
1552}
1553
1554#ifdef CONFIG_PM
1555
1556/*
1557 * suspend/resume synchronization:
1558 * - open, close, do_ioctl:
1559 * rtnl_lock, & netif_device_detach after the rtnl_unlock.
1560 * - get_stats:
1561 * spin_lock_irq(np->lock), doesn't touch hw if not present
2a97e6b7 1562 * - start_xmit:
932ff279 1563 * synchronize_irq + netif_tx_disable;
1da177e4 1564 * - tx_timeout:
932ff279 1565 * netif_device_detach + netif_tx_disable;
1da177e4 1566 * - set_multicast_list
932ff279 1567 * netif_device_detach + netif_tx_disable;
1da177e4
LT		 1568 * - interrupt handler
1569 * doesn't touch hw if not present, synchronize_irq waits for
1570 * running instances of the interrupt handler.
1571 *
1572 * Disabling hw requires clearing csr6 & IntrEnable.
1573 * update_csr6 & all function that write IntrEnable check netif_device_present
1574 * before settings any bits.
1575 *
1576 * Detach must occur under spin_unlock_irq(), interrupts from a detached
1577 * device would cause an irq storm.
1578 */
05adc3b7 1579static int w840_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1580{
1581 struct net_device *dev = pci_get_drvdata (pdev);
1582 struct netdev_private *np = netdev_priv(dev);
1583 void __iomem *ioaddr = np->base_addr;
1584
1585 rtnl_lock();
1586 if (netif_running (dev)) {
1587 del_timer_sync(&np->timer);
1588
1589 spin_lock_irq(&np->lock);
1590 netif_device_detach(dev);
1591 update_csr6(dev, 0);
1592 iowrite32(0, ioaddr + IntrEnable);
1da177e4
LT		 1593 spin_unlock_irq(&np->lock);
1594
1da177e4 1595 synchronize_irq(dev->irq);
932ff279 1596 netif_tx_disable(dev);
6aa20a22 1597
1da177e4
LT		 1598 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1599
1600 /* no more hardware accesses behind this line. */
1601
0ee904c3 1602 BUG_ON(np->csr6 || ioread32(ioaddr + IntrEnable));
1da177e4
LT		 1603
1604 /* pci_power_off(pdev, -1); */
1605
1606 free_rxtx_rings(np);
1607 } else {
1608 netif_device_detach(dev);
1609 }
1610 rtnl_unlock();
1611 return 0;
1612}
1613
1614static int w840_resume (struct pci_dev *pdev)
1615{
1616 struct net_device *dev = pci_get_drvdata (pdev);
1617 struct netdev_private *np = netdev_priv(dev);
9f486ae1 1618 int retval = 0;
1da177e4
LT		 1619
1620 rtnl_lock();
1621 if (netif_device_present(dev))
1622 goto out; /* device not suspended */
1623 if (netif_running(dev)) {
9f486ae1 1624 if ((retval = pci_enable_device(pdev))) {
a1e37bc5
JP		 1625 dev_err(&dev->dev,
1626 "pci_enable_device failed in resume\n");
9f486ae1
VH		 1627 goto out;
1628 }
1da177e4
LT		 1629 spin_lock_irq(&np->lock);
1630 iowrite32(1, np->base_addr+PCIBusCfg);
1631 ioread32(np->base_addr+PCIBusCfg);
1632 udelay(1);
1633 netif_device_attach(dev);
1634 init_rxtx_rings(dev);
1635 init_registers(dev);
1636 spin_unlock_irq(&np->lock);
1637
1638 netif_wake_queue(dev);
1639
1640 mod_timer(&np->timer, jiffies + 1*HZ);
1641 } else {
1642 netif_device_attach(dev);
1643 }
1644out:
1645 rtnl_unlock();
9f486ae1 1646 return retval;
1da177e4
LT		 1647}
1648#endif
1649
1650static struct pci_driver w840_driver = {
1651 .name = DRV_NAME,
1652 .id_table = w840_pci_tbl,
1653 .probe = w840_probe1,
1654 .remove = __devexit_p(w840_remove1),
1655#ifdef CONFIG_PM
1656 .suspend = w840_suspend,
1657 .resume = w840_resume,
1658#endif
1659};
1660
1661static int __init w840_init(void)
1662{
1663 printk(version);
29917620 1664 return pci_register_driver(&w840_driver);
1da177e4
LT		 1665}
1666
1667static void __exit w840_exit(void)
1668{
1669 pci_unregister_driver(&w840_driver);
1670}
1671
1672module_init(w840_init);
1673module_exit(w840_exit);
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