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1da177e4
LT		 1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
113aa838 26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
1da177e4
LT		 27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
113aa838 52 Alan Cox <alan@lxorguk.ukuu.org.uk>
f3b197ac 53 Added new PCI identifiers provided by Clear Zhang at ALi
1da177e4
LT		 54 for their 1563 ethernet device.
55
56 TODO
57
1da177e4
LT		 58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62*/
63
64#define DRV_NAME "dmfe"
65#define DRV_VERSION "1.36.4"
66#define DRV_RELDATE "2002-01-17"
67
68#include <linux/module.h>
69#include <linux/kernel.h>
70#include <linux/string.h>
71#include <linux/timer.h>
72#include <linux/ptrace.h>
73#include <linux/errno.h>
74#include <linux/ioport.h>
75#include <linux/slab.h>
76#include <linux/interrupt.h>
77#include <linux/pci.h>
cb199d42 78#include <linux/dma-mapping.h>
1da177e4
LT		 79#include <linux/init.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/ethtool.h>
83#include <linux/skbuff.h>
84#include <linux/delay.h>
85#include <linux/spinlock.h>
86#include <linux/crc32.h>
87#include <linux/bitops.h>
88
89#include <asm/processor.h>
90#include <asm/io.h>
91#include <asm/dma.h>
92#include <asm/uaccess.h>
93#include <asm/irq.h>
94
95
96/* Board/System/Debug information/definition ---------------- */
97#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
98#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
99#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
100#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
101
102#define DM9102_IO_SIZE 0x80
103#define DM9102A_IO_SIZE 0x100
104#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
105#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
106#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
107#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
108#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
109#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
110#define TX_BUF_ALLOC 0x600
111#define RX_ALLOC_SIZE 0x620
112#define DM910X_RESET 1
113#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
114#define CR6_DEFAULT 0x00080000 /* HD */
115#define CR7_DEFAULT 0x180c1
116#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
117#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
118#define MAX_PACKET_SIZE 1514
119#define DMFE_MAX_MULTICAST 14
120#define RX_COPY_SIZE 100
121#define MAX_CHECK_PACKET 0x8000
122#define DM9801_NOISE_FLOOR 8
123#define DM9802_NOISE_FLOOR 5
124
f1069046
ML		 125#define DMFE_WOL_LINKCHANGE 0x20000000
126#define DMFE_WOL_SAMPLEPACKET 0x10000000
127#define DMFE_WOL_MAGICPACKET 0x08000000
128
129
1da177e4
LT		 130#define DMFE_10MHF 0
131#define DMFE_100MHF 1
132#define DMFE_10MFD 4
133#define DMFE_100MFD 5
134#define DMFE_AUTO 8
135#define DMFE_1M_HPNA 0x10
136
137#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
138#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
139#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
140#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
141#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
142#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
143
144#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
145#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
146#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
147
f67ba792
ML		 148#define DMFE_DBUG(dbug_now, msg, value) \
149 do { \
150 if (dmfe_debug || (dbug_now)) \
151 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
152 (msg), (long) (value)); \
153 } while (0)
1da177e4 154
f67ba792
ML		 155#define SHOW_MEDIA_TYPE(mode) \
156 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
157 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
1da177e4
LT		 158
159
160/* CR9 definition: SROM/MII */
161#define CR9_SROM_READ 0x4800
162#define CR9_SRCS 0x1
163#define CR9_SRCLK 0x2
164#define CR9_CRDOUT 0x8
165#define SROM_DATA_0 0x0
166#define SROM_DATA_1 0x4
167#define PHY_DATA_1 0x20000
168#define PHY_DATA_0 0x00000
169#define MDCLKH 0x10000
170
171#define PHY_POWER_DOWN 0x800
172
173#define SROM_V41_CODE 0x14
174
f67ba792
ML		 175#define SROM_CLK_WRITE(data, ioaddr) \
176 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
177 udelay(5); \
178 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
179 udelay(5); \
180 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
181 udelay(5);
182
183#define __CHK_IO_SIZE(pci_id, dev_rev) \
44c10138 184 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
f67ba792 185 DM9102A_IO_SIZE: DM9102_IO_SIZE)
1da177e4 186
44c10138
AK		 187#define CHK_IO_SIZE(pci_dev) \
188 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
189 (pci_dev)->revision))
1da177e4
LT		 190
191/* Sten Check */
192#define DEVICE net_device
193
194/* Structure/enum declaration ------------------------------- */
195struct tx_desc {
a31e40f6 196 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
1da177e4
LT		 197 char *tx_buf_ptr; /* Data for us */
198 struct tx_desc *next_tx_desc;
199} __attribute__(( aligned(32) ));
200
201struct rx_desc {
a31e40f6 202 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
1da177e4
LT		 203 struct sk_buff *rx_skb_ptr; /* Data for us */
204 struct rx_desc *next_rx_desc;
205} __attribute__(( aligned(32) ));
206
207struct dmfe_board_info {
208 u32 chip_id; /* Chip vendor/Device ID */
44c10138 209 u8 chip_revision; /* Chip revision */
ead9bffb 210 struct DEVICE *next_dev; /* next device */
1da177e4
LT		 211 struct pci_dev *pdev; /* PCI device */
212 spinlock_t lock;
213
214 long ioaddr; /* I/O base address */
215 u32 cr0_data;
216 u32 cr5_data;
217 u32 cr6_data;
218 u32 cr7_data;
219 u32 cr15_data;
220
221 /* pointer for memory physical address */
222 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
223 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
224 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
225 dma_addr_t first_tx_desc_dma;
226 dma_addr_t first_rx_desc_dma;
227
228 /* descriptor pointer */
229 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
230 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
231 unsigned char *desc_pool_ptr; /* descriptor pool memory */
232 struct tx_desc *first_tx_desc;
233 struct tx_desc *tx_insert_ptr;
234 struct tx_desc *tx_remove_ptr;
235 struct rx_desc *first_rx_desc;
236 struct rx_desc *rx_insert_ptr;
237 struct rx_desc *rx_ready_ptr; /* packet come pointer */
238 unsigned long tx_packet_cnt; /* transmitted packet count */
239 unsigned long tx_queue_cnt; /* wait to send packet count */
240 unsigned long rx_avail_cnt; /* available rx descriptor count */
241 unsigned long interval_rx_cnt; /* rx packet count a callback time */
242
243 u16 HPNA_command; /* For HPNA register 16 */
244 u16 HPNA_timer; /* For HPNA remote device check */
245 u16 dbug_cnt;
246 u16 NIC_capability; /* NIC media capability */
247 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
248
249 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
250 u8 chip_type; /* Keep DM9102A chip type */
251 u8 media_mode; /* user specify media mode */
252 u8 op_mode; /* real work media mode */
253 u8 phy_addr;
1da177e4
LT		 254 u8 wait_reset; /* Hardware failed, need to reset */
255 u8 dm910x_chk_mode; /* Operating mode check */
256 u8 first_in_callback; /* Flag to record state */
f1069046 257 u8 wol_mode; /* user WOL settings */
1da177e4
LT		 258 struct timer_list timer;
259
260 /* System defined statistic counter */
261 struct net_device_stats stats;
262
263 /* Driver defined statistic counter */
264 unsigned long tx_fifo_underrun;
265 unsigned long tx_loss_carrier;
266 unsigned long tx_no_carrier;
267 unsigned long tx_late_collision;
268 unsigned long tx_excessive_collision;
269 unsigned long tx_jabber_timeout;
270 unsigned long reset_count;
271 unsigned long reset_cr8;
272 unsigned long reset_fatal;
273 unsigned long reset_TXtimeout;
274
275 /* NIC SROM data */
276 unsigned char srom[128];
277};
278
279enum dmfe_offsets {
280 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
281 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
282 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
283 DCR15 = 0x78
284};
285
286enum dmfe_CR6_bits {
287 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
288 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
289 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
290};
291
292/* Global variable declaration ----------------------------- */
293static int __devinitdata printed_version;
294static char version[] __devinitdata =
295 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
296 DRV_VERSION " (" DRV_RELDATE ")\n";
297
298static int dmfe_debug;
299static unsigned char dmfe_media_mode = DMFE_AUTO;
300static u32 dmfe_cr6_user_set;
301
302/* For module input parameter */
303static int debug;
304static u32 cr6set;
305static unsigned char mode = 8;
306static u8 chkmode = 1;
307static u8 HPNA_mode; /* Default: Low Power/High Speed */
308static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
309static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
310static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
311static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
312 4: TX pause packet */
313
314
315/* function declaration ------------------------------------- */
316static int dmfe_open(struct DEVICE *);
317static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
318static int dmfe_stop(struct DEVICE *);
319static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
320static void dmfe_set_filter_mode(struct DEVICE *);
7282d491 321static const struct ethtool_ops netdev_ethtool_ops;
1da177e4 322static u16 read_srom_word(long ,int);
7d12e780 323static irqreturn_t dmfe_interrupt(int , void *);
1da177e4
LT		 324#ifdef CONFIG_NET_POLL_CONTROLLER
325static void poll_dmfe (struct net_device *dev);
326#endif
327static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
328static void allocate_rx_buffer(struct dmfe_board_info *);
329static void update_cr6(u32, unsigned long);
330static void send_filter_frame(struct DEVICE * ,int);
331static void dm9132_id_table(struct DEVICE * ,int);
332static u16 phy_read(unsigned long, u8, u8, u32);
333static void phy_write(unsigned long, u8, u8, u16, u32);
334static void phy_write_1bit(unsigned long, u32);
335static u16 phy_read_1bit(unsigned long);
336static u8 dmfe_sense_speed(struct dmfe_board_info *);
337static void dmfe_process_mode(struct dmfe_board_info *);
338static void dmfe_timer(unsigned long);
339static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
340static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
341static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
342static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
343static void dmfe_dynamic_reset(struct DEVICE *);
344static void dmfe_free_rxbuffer(struct dmfe_board_info *);
345static void dmfe_init_dm910x(struct DEVICE *);
346static void dmfe_parse_srom(struct dmfe_board_info *);
347static void dmfe_program_DM9801(struct dmfe_board_info *, int);
348static void dmfe_program_DM9802(struct dmfe_board_info *);
349static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
350static void dmfe_set_phyxcer(struct dmfe_board_info *);
351
f67ba792 352/* DM910X network board routine ---------------------------- */
1da177e4
LT		 353
354/*
355 * Search DM910X board ,allocate space and register it
356 */
357
358static int __devinit dmfe_init_one (struct pci_dev *pdev,
359 const struct pci_device_id *ent)
360{
361 struct dmfe_board_info *db; /* board information structure */
362 struct net_device *dev;
44c10138 363 u32 pci_pmr;
1da177e4
LT		 364 int i, err;
365
366 DMFE_DBUG(0, "dmfe_init_one()", 0);
367
368 if (!printed_version++)
369 printk(version);
370
371 /* Init network device */
372 dev = alloc_etherdev(sizeof(*db));
373 if (dev == NULL)
374 return -ENOMEM;
1da177e4
LT		 375 SET_NETDEV_DEV(dev, &pdev->dev);
376
cb199d42 377 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
f67ba792
ML		 378 printk(KERN_WARNING DRV_NAME
379 ": 32-bit PCI DMA not available.\n");
1da177e4
LT		 380 err = -ENODEV;
381 goto err_out_free;
382 }
383
384 /* Enable Master/IO access, Disable memory access */
385 err = pci_enable_device(pdev);
386 if (err)
387 goto err_out_free;
388
389 if (!pci_resource_start(pdev, 0)) {
390 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
391 err = -ENODEV;
392 goto err_out_disable;
393 }
394
44c10138 395 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
1da177e4
LT		 396 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
397 err = -ENODEV;
398 goto err_out_disable;
399 }
400
401#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
402
403 /* Set Latency Timer 80h */
404 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
405 Need a PCI quirk.. */
406
407 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
408#endif
409
410 if (pci_request_regions(pdev, DRV_NAME)) {
411 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
412 err = -ENODEV;
413 goto err_out_disable;
414 }
415
416 /* Init system & device */
417 db = netdev_priv(dev);
418
419 /* Allocate Tx/Rx descriptor memory */
f67ba792
ML		 420 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
421 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
422
423 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
424 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
1da177e4
LT		 425
426 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
427 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
428 db->buf_pool_start = db->buf_pool_ptr;
429 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
430
431 db->chip_id = ent->driver_data;
432 db->ioaddr = pci_resource_start(pdev, 0);
44c10138 433 db->chip_revision = pdev->revision;
f1069046 434 db->wol_mode = 0;
1da177e4
LT		 435
436 db->pdev = pdev;
437
438 dev->base_addr = db->ioaddr;
439 dev->irq = pdev->irq;
440 pci_set_drvdata(pdev, dev);
441 dev->open = &dmfe_open;
442 dev->hard_start_xmit = &dmfe_start_xmit;
443 dev->stop = &dmfe_stop;
444 dev->get_stats = &dmfe_get_stats;
445 dev->set_multicast_list = &dmfe_set_filter_mode;
446#ifdef CONFIG_NET_POLL_CONTROLLER
447 dev->poll_controller = &poll_dmfe;
448#endif
449 dev->ethtool_ops = &netdev_ethtool_ops;
cfa51b9d 450 netif_carrier_off(dev);
1da177e4
LT		 451 spin_lock_init(&db->lock);
452
453 pci_read_config_dword(pdev, 0x50, &pci_pmr);
454 pci_pmr &= 0x70000;
44c10138 455 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
1da177e4
LT		 456 db->chip_type = 1; /* DM9102A E3 */
457 else
458 db->chip_type = 0;
459
460 /* read 64 word srom data */
461 for (i = 0; i < 64; i++)
a31e40f6 462 ((__le16 *) db->srom)[i] =
f67ba792 463 cpu_to_le16(read_srom_word(db->ioaddr, i));
1da177e4
LT		 464
465 /* Set Node address */
466 for (i = 0; i < 6; i++)
467 dev->dev_addr[i] = db->srom[20 + i];
468
469 err = register_netdev (dev);
470 if (err)
471 goto err_out_res;
472
e174961c 473 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s, %pM, irq %d.\n",
0795af57
JP		 474 dev->name,
475 ent->driver_data >> 16,
476 pci_name(pdev),
e174961c 477 dev->dev_addr,
0795af57 478 dev->irq);
1da177e4
LT		 479
480 pci_set_master(pdev);
481
482 return 0;
483
484err_out_res:
485 pci_release_regions(pdev);
486err_out_disable:
487 pci_disable_device(pdev);
488err_out_free:
489 pci_set_drvdata(pdev, NULL);
490 free_netdev(dev);
491
492 return err;
493}
494
495
496static void __devexit dmfe_remove_one (struct pci_dev *pdev)
497{
498 struct net_device *dev = pci_get_drvdata(pdev);
499 struct dmfe_board_info *db = netdev_priv(dev);
500
501 DMFE_DBUG(0, "dmfe_remove_one()", 0);
502
503 if (dev) {
4dc68f3d
ML		 504
505 unregister_netdev(dev);
506
1da177e4
LT		 507 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
508 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
509 db->desc_pool_dma_ptr);
510 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
511 db->buf_pool_ptr, db->buf_pool_dma_ptr);
1da177e4
LT		 512 pci_release_regions(pdev);
513 free_netdev(dev); /* free board information */
4dc68f3d 514
1da177e4
LT		 515 pci_set_drvdata(pdev, NULL);
516 }
517
518 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
519}
520
521
522/*
523 * Open the interface.
524 * The interface is opened whenever "ifconfig" actives it.
525 */
526
527static int dmfe_open(struct DEVICE *dev)
528{
529 int ret;
530 struct dmfe_board_info *db = netdev_priv(dev);
531
532 DMFE_DBUG(0, "dmfe_open", 0);
533
f67ba792
ML		 534 ret = request_irq(dev->irq, &dmfe_interrupt,
535 IRQF_SHARED, dev->name, dev);
1da177e4
LT		 536 if (ret)
537 return ret;
538
539 /* system variable init */
540 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
541 db->tx_packet_cnt = 0;
542 db->tx_queue_cnt = 0;
543 db->rx_avail_cnt = 0;
1da177e4
LT		 544 db->wait_reset = 0;
545
546 db->first_in_callback = 0;
547 db->NIC_capability = 0xf; /* All capability*/
548 db->PHY_reg4 = 0x1e0;
549
550 /* CR6 operation mode decision */
551 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
44c10138 552 (db->chip_revision >= 0x30) ) {
1da177e4
LT		 553 db->cr6_data |= DMFE_TXTH_256;
554 db->cr0_data = CR0_DEFAULT;
555 db->dm910x_chk_mode=4; /* Enter the normal mode */
556 } else {
557 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
558 db->cr0_data = 0;
559 db->dm910x_chk_mode = 1; /* Enter the check mode */
560 }
561
562 /* Initilize DM910X board */
563 dmfe_init_dm910x(dev);
564
565 /* Active System Interface */
566 netif_wake_queue(dev);
567
568 /* set and active a timer process */
569 init_timer(&db->timer);
570 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
571 db->timer.data = (unsigned long)dev;
572 db->timer.function = &dmfe_timer;
573 add_timer(&db->timer);
574
575 return 0;
576}
577
578
579/* Initilize DM910X board
580 * Reset DM910X board
581 * Initilize TX/Rx descriptor chain structure
582 * Send the set-up frame
583 * Enable Tx/Rx machine
584 */
585
586static void dmfe_init_dm910x(struct DEVICE *dev)
587{
588 struct dmfe_board_info *db = netdev_priv(dev);
589 unsigned long ioaddr = db->ioaddr;
590
591 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
592
593 /* Reset DM910x MAC controller */
594 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
595 udelay(100);
596 outl(db->cr0_data, ioaddr + DCR0);
597 udelay(5);
598
599 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
600 db->phy_addr = 1;
601
602 /* Parser SROM and media mode */
603 dmfe_parse_srom(db);
604 db->media_mode = dmfe_media_mode;
605
606 /* RESET Phyxcer Chip by GPR port bit 7 */
607 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
608 if (db->chip_id == PCI_DM9009_ID) {
609 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
610 mdelay(300); /* Delay 300 ms */
611 }
612 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
613
614 /* Process Phyxcer Media Mode */
615 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
616 dmfe_set_phyxcer(db);
617
618 /* Media Mode Process */
619 if ( !(db->media_mode & DMFE_AUTO) )
620 db->op_mode = db->media_mode; /* Force Mode */
621
622 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
623 dmfe_descriptor_init(db, ioaddr);
624
625 /* Init CR6 to program DM910x operation */
626 update_cr6(db->cr6_data, ioaddr);
627
628 /* Send setup frame */
629 if (db->chip_id == PCI_DM9132_ID)
630 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
631 else
632 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
633
634 /* Init CR7, interrupt active bit */
635 db->cr7_data = CR7_DEFAULT;
636 outl(db->cr7_data, ioaddr + DCR7);
637
638 /* Init CR15, Tx jabber and Rx watchdog timer */
639 outl(db->cr15_data, ioaddr + DCR15);
640
641 /* Enable DM910X Tx/Rx function */
642 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
643 update_cr6(db->cr6_data, ioaddr);
644}
645
646
647/*
648 * Hardware start transmission.
649 * Send a packet to media from the upper layer.
650 */
651
652static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
653{
654 struct dmfe_board_info *db = netdev_priv(dev);
655 struct tx_desc *txptr;
656 unsigned long flags;
657
658 DMFE_DBUG(0, "dmfe_start_xmit", 0);
659
660 /* Resource flag check */
661 netif_stop_queue(dev);
662
663 /* Too large packet check */
664 if (skb->len > MAX_PACKET_SIZE) {
665 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
666 dev_kfree_skb(skb);
667 return 0;
668 }
669
670 spin_lock_irqsave(&db->lock, flags);
671
672 /* No Tx resource check, it never happen nromally */
673 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
674 spin_unlock_irqrestore(&db->lock, flags);
f67ba792
ML		 675 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
676 db->tx_queue_cnt);
1da177e4
LT		 677 return 1;
678 }
679
680 /* Disable NIC interrupt */
681 outl(0, dev->base_addr + DCR7);
682
683 /* transmit this packet */
684 txptr = db->tx_insert_ptr;
d626f62b 685 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
1da177e4
LT		 686 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
687
688 /* Point to next transmit free descriptor */
689 db->tx_insert_ptr = txptr->next_tx_desc;
690
691 /* Transmit Packet Process */
692 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
693 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
694 db->tx_packet_cnt++; /* Ready to send */
695 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
696 dev->trans_start = jiffies; /* saved time stamp */
697 } else {
698 db->tx_queue_cnt++; /* queue TX packet */
699 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
700 }
701
702 /* Tx resource check */
703 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
704 netif_wake_queue(dev);
705
706 /* Restore CR7 to enable interrupt */
707 spin_unlock_irqrestore(&db->lock, flags);
708 outl(db->cr7_data, dev->base_addr + DCR7);
709
710 /* free this SKB */
711 dev_kfree_skb(skb);
712
713 return 0;
714}
715
716
717/*
718 * Stop the interface.
719 * The interface is stopped when it is brought.
720 */
721
722static int dmfe_stop(struct DEVICE *dev)
723{
724 struct dmfe_board_info *db = netdev_priv(dev);
725 unsigned long ioaddr = dev->base_addr;
726
727 DMFE_DBUG(0, "dmfe_stop", 0);
728
729 /* disable system */
730 netif_stop_queue(dev);
731
732 /* deleted timer */
733 del_timer_sync(&db->timer);
734
735 /* Reset & stop DM910X board */
736 outl(DM910X_RESET, ioaddr + DCR0);
737 udelay(5);
738 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
739
740 /* free interrupt */
741 free_irq(dev->irq, dev);
742
743 /* free allocated rx buffer */
744 dmfe_free_rxbuffer(db);
745
746#if 0
747 /* show statistic counter */
f67ba792
ML		 748 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
749 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
1da177e4
LT		 750 db->tx_fifo_underrun, db->tx_excessive_collision,
751 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
752 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
753 db->reset_fatal, db->reset_TXtimeout);
754#endif
755
756 return 0;
757}
758
759
760/*
761 * DM9102 insterrupt handler
762 * receive the packet to upper layer, free the transmitted packet
763 */
764
7d12e780 765static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
1da177e4
LT		 766{
767 struct DEVICE *dev = dev_id;
768 struct dmfe_board_info *db = netdev_priv(dev);
769 unsigned long ioaddr = dev->base_addr;
770 unsigned long flags;
771
772 DMFE_DBUG(0, "dmfe_interrupt()", 0);
773
1da177e4
LT		 774 spin_lock_irqsave(&db->lock, flags);
775
776 /* Got DM910X status */
777 db->cr5_data = inl(ioaddr + DCR5);
778 outl(db->cr5_data, ioaddr + DCR5);
779 if ( !(db->cr5_data & 0xc1) ) {
780 spin_unlock_irqrestore(&db->lock, flags);
781 return IRQ_HANDLED;
782 }
783
784 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
785 outl(0, ioaddr + DCR7);
786
787 /* Check system status */
788 if (db->cr5_data & 0x2000) {
789 /* system bus error happen */
790 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
791 db->reset_fatal++;
792 db->wait_reset = 1; /* Need to RESET */
793 spin_unlock_irqrestore(&db->lock, flags);
794 return IRQ_HANDLED;
795 }
796
797 /* Received the coming packet */
798 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
799 dmfe_rx_packet(dev, db);
800
801 /* reallocate rx descriptor buffer */
802 if (db->rx_avail_cnt<RX_DESC_CNT)
803 allocate_rx_buffer(db);
804
805 /* Free the transmitted descriptor */
806 if ( db->cr5_data & 0x01)
807 dmfe_free_tx_pkt(dev, db);
808
809 /* Mode Check */
810 if (db->dm910x_chk_mode & 0x2) {
811 db->dm910x_chk_mode = 0x4;
812 db->cr6_data |= 0x100;
813 update_cr6(db->cr6_data, db->ioaddr);
814 }
815
816 /* Restore CR7 to enable interrupt mask */
817 outl(db->cr7_data, ioaddr + DCR7);
818
819 spin_unlock_irqrestore(&db->lock, flags);
820 return IRQ_HANDLED;
821}
822
823
824#ifdef CONFIG_NET_POLL_CONTROLLER
825/*
826 * Polling 'interrupt' - used by things like netconsole to send skbs
827 * without having to re-enable interrupts. It's not called while
828 * the interrupt routine is executing.
829 */
830
831static void poll_dmfe (struct net_device *dev)
832{
833 /* disable_irq here is not very nice, but with the lockless
834 interrupt handler we have no other choice. */
835 disable_irq(dev->irq);
7d12e780 836 dmfe_interrupt (dev->irq, dev);
1da177e4
LT		 837 enable_irq(dev->irq);
838}
839#endif
840
841/*
842 * Free TX resource after TX complete
843 */
844
845static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
846{
847 struct tx_desc *txptr;
848 unsigned long ioaddr = dev->base_addr;
849 u32 tdes0;
850
851 txptr = db->tx_remove_ptr;
852 while(db->tx_packet_cnt) {
853 tdes0 = le32_to_cpu(txptr->tdes0);
854 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
855 if (tdes0 & 0x80000000)
856 break;
857
858 /* A packet sent completed */
859 db->tx_packet_cnt--;
860 db->stats.tx_packets++;
861
862 /* Transmit statistic counter */
863 if ( tdes0 != 0x7fffffff ) {
864 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
865 db->stats.collisions += (tdes0 >> 3) & 0xf;
866 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
867 if (tdes0 & TDES0_ERR_MASK) {
868 db->stats.tx_errors++;
869
870 if (tdes0 & 0x0002) { /* UnderRun */
871 db->tx_fifo_underrun++;
872 if ( !(db->cr6_data & CR6_SFT) ) {
873 db->cr6_data = db->cr6_data | CR6_SFT;
874 update_cr6(db->cr6_data, db->ioaddr);
875 }
876 }
877 if (tdes0 & 0x0100)
878 db->tx_excessive_collision++;
879 if (tdes0 & 0x0200)
880 db->tx_late_collision++;
881 if (tdes0 & 0x0400)
882 db->tx_no_carrier++;
883 if (tdes0 & 0x0800)
884 db->tx_loss_carrier++;
885 if (tdes0 & 0x4000)
886 db->tx_jabber_timeout++;
887 }
888 }
889
890 txptr = txptr->next_tx_desc;
891 }/* End of while */
892
893 /* Update TX remove pointer to next */
894 db->tx_remove_ptr = txptr;
895
896 /* Send the Tx packet in queue */
897 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
898 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
899 db->tx_packet_cnt++; /* Ready to send */
900 db->tx_queue_cnt--;
901 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
902 dev->trans_start = jiffies; /* saved time stamp */
903 }
904
905 /* Resource available check */
906 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
907 netif_wake_queue(dev); /* Active upper layer, send again */
908}
909
910
911/*
912 * Calculate the CRC valude of the Rx packet
913 * flag = 1 : return the reverse CRC (for the received packet CRC)
914 * 0 : return the normal CRC (for Hash Table index)
915 */
916
917static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
918{
919 u32 crc = crc32(~0, Data, Len);
920 if (flag) crc = ~crc;
921 return crc;
922}
923
924
925/*
926 * Receive the come packet and pass to upper layer
927 */
928
929static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
930{
931 struct rx_desc *rxptr;
4dc68f3d 932 struct sk_buff *skb, *newskb;
1da177e4
LT		 933 int rxlen;
934 u32 rdes0;
935
936 rxptr = db->rx_ready_ptr;
937
938 while(db->rx_avail_cnt) {
939 rdes0 = le32_to_cpu(rxptr->rdes0);
940 if (rdes0 & 0x80000000) /* packet owner check */
941 break;
942
943 db->rx_avail_cnt--;
944 db->interval_rx_cnt++;
945
f67ba792
ML		 946 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
947 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
948
1da177e4
LT		 949 if ( (rdes0 & 0x300) != 0x300) {
950 /* A packet without First/Last flag */
951 /* reuse this SKB */
952 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
953 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
954 } else {
955 /* A packet with First/Last flag */
956 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
957
958 /* error summary bit check */
959 if (rdes0 & 0x8000) {
960 /* This is a error packet */
961 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
962 db->stats.rx_errors++;
963 if (rdes0 & 1)
964 db->stats.rx_fifo_errors++;
965 if (rdes0 & 2)
966 db->stats.rx_crc_errors++;
967 if (rdes0 & 0x80)
968 db->stats.rx_length_errors++;
969 }
970
971 if ( !(rdes0 & 0x8000) ||
972 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
973 skb = rxptr->rx_skb_ptr;
974
975 /* Received Packet CRC check need or not */
976 if ( (db->dm910x_chk_mode & 1) &&
689be439
DM		 977 (cal_CRC(skb->data, rxlen, 1) !=
978 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1da177e4
LT		 979 /* Found a error received packet */
980 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
981 db->dm910x_chk_mode = 3;
982 } else {
983 /* Good packet, send to upper layer */
984 /* Shorst packet used new SKB */
4dc68f3d
ML		 985 if ((rxlen < RX_COPY_SIZE) &&
986 ((newskb = dev_alloc_skb(rxlen + 2))
987 != NULL)) {
988
989 skb = newskb;
1da177e4 990 /* size less than COPY_SIZE, allocate a rxlen SKB */
1da177e4 991 skb_reserve(skb, 2); /* 16byte align */
d626f62b
ACM		 992 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
993 skb_put(skb, rxlen),
994 rxlen);
1da177e4 995 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 996 } else
1da177e4 997 skb_put(skb, rxlen);
4c13eb66 998
1da177e4
LT		 999 skb->protocol = eth_type_trans(skb, dev);
1000 netif_rx(skb);
1001 dev->last_rx = jiffies;
1002 db->stats.rx_packets++;
1003 db->stats.rx_bytes += rxlen;
1004 }
1005 } else {
1006 /* Reuse SKB buffer when the packet is error */
1007 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1008 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1009 }
1010 }
1011
1012 rxptr = rxptr->next_rx_desc;
1013 }
1014
1015 db->rx_ready_ptr = rxptr;
1016}
1017
1018
1019/*
1020 * Get statistics from driver.
1021 */
1022
1023static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
1024{
1025 struct dmfe_board_info *db = netdev_priv(dev);
1026
1027 DMFE_DBUG(0, "dmfe_get_stats", 0);
1028 return &db->stats;
1029}
1030
1031
1032/*
1033 * Set DM910X multicast address
1034 */
1035
1036static void dmfe_set_filter_mode(struct DEVICE * dev)
1037{
1038 struct dmfe_board_info *db = netdev_priv(dev);
1039 unsigned long flags;
1040
1041 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1042 spin_lock_irqsave(&db->lock, flags);
1043
1044 if (dev->flags & IFF_PROMISC) {
1045 DMFE_DBUG(0, "Enable PROM Mode", 0);
1046 db->cr6_data |= CR6_PM | CR6_PBF;
1047 update_cr6(db->cr6_data, db->ioaddr);
1048 spin_unlock_irqrestore(&db->lock, flags);
1049 return;
1050 }
1051
1052 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1053 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1054 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1055 db->cr6_data |= CR6_PAM;
1056 spin_unlock_irqrestore(&db->lock, flags);
1057 return;
1058 }
1059
1060 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1061 if (db->chip_id == PCI_DM9132_ID)
1062 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1063 else
1064 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1065 spin_unlock_irqrestore(&db->lock, flags);
1066}
1067
f1069046
ML		 1068/*
1069 * Ethtool interace
1070 */
1071
1072static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1da177e4
LT		 1073 struct ethtool_drvinfo *info)
1074{
1075 struct dmfe_board_info *np = netdev_priv(dev);
1076
1077 strcpy(info->driver, DRV_NAME);
1078 strcpy(info->version, DRV_VERSION);
1079 if (np->pdev)
1080 strcpy(info->bus_info, pci_name(np->pdev));
1081 else
1082 sprintf(info->bus_info, "EISA 0x%lx %d",
1083 dev->base_addr, dev->irq);
1084}
1085
f1069046
ML		 1086static int dmfe_ethtool_set_wol(struct net_device *dev,
1087 struct ethtool_wolinfo *wolinfo)
1088{
1089 struct dmfe_board_info *db = netdev_priv(dev);
1090
1091 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1092 WAKE_ARP | WAKE_MAGICSECURE))
1093 return -EOPNOTSUPP;
1094
1095 db->wol_mode = wolinfo->wolopts;
1096 return 0;
1097}
1098
1099static void dmfe_ethtool_get_wol(struct net_device *dev,
1100 struct ethtool_wolinfo *wolinfo)
1101{
1102 struct dmfe_board_info *db = netdev_priv(dev);
1103
1104 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1105 wolinfo->wolopts = db->wol_mode;
1106 return;
1107}
1108
1109
7282d491 1110static const struct ethtool_ops netdev_ethtool_ops = {
f1069046 1111 .get_drvinfo = dmfe_ethtool_get_drvinfo,
cfa51b9d 1112 .get_link = ethtool_op_get_link,
f1069046
ML		 1113 .set_wol = dmfe_ethtool_set_wol,
1114 .get_wol = dmfe_ethtool_get_wol,
1da177e4
LT		 1115};
1116
1117/*
1118 * A periodic timer routine
1119 * Dynamic media sense, allocate Rx buffer...
1120 */
1121
1122static void dmfe_timer(unsigned long data)
1123{
1124 u32 tmp_cr8;
1125 unsigned char tmp_cr12;
1126 struct DEVICE *dev = (struct DEVICE *) data;
1127 struct dmfe_board_info *db = netdev_priv(dev);
1128 unsigned long flags;
1129
cfa51b9d
ML		 1130 int link_ok, link_ok_phy;
1131
1da177e4
LT		 1132 DMFE_DBUG(0, "dmfe_timer()", 0);
1133 spin_lock_irqsave(&db->lock, flags);
1134
1135 /* Media mode process when Link OK before enter this route */
1136 if (db->first_in_callback == 0) {
1137 db->first_in_callback = 1;
1138 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1139 db->cr6_data &= ~0x40000;
1140 update_cr6(db->cr6_data, db->ioaddr);
f67ba792
ML		 1141 phy_write(db->ioaddr,
1142 db->phy_addr, 0, 0x1000, db->chip_id);
1da177e4
LT		 1143 db->cr6_data |= 0x40000;
1144 update_cr6(db->cr6_data, db->ioaddr);
1145 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1146 add_timer(&db->timer);
1147 spin_unlock_irqrestore(&db->lock, flags);
1148 return;
1149 }
1150 }
1151
1152
1153 /* Operating Mode Check */
1154 if ( (db->dm910x_chk_mode & 0x1) &&
1155 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1156 db->dm910x_chk_mode = 0x4;
1157
1158 /* Dynamic reset DM910X : system error or transmit time-out */
1159 tmp_cr8 = inl(db->ioaddr + DCR8);
1160 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1161 db->reset_cr8++;
1162 db->wait_reset = 1;
1163 }
1164 db->interval_rx_cnt = 0;
1165
1166 /* TX polling kick monitor */
1167 if ( db->tx_packet_cnt &&
1168 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1169 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1170
1171 /* TX Timeout */
1172 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1173 db->reset_TXtimeout++;
1174 db->wait_reset = 1;
1175 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1176 dev->name);
1177 }
1178 }
1179
1180 if (db->wait_reset) {
1181 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1182 db->reset_count++;
1183 dmfe_dynamic_reset(dev);
1184 db->first_in_callback = 0;
1185 db->timer.expires = DMFE_TIMER_WUT;
1186 add_timer(&db->timer);
1187 spin_unlock_irqrestore(&db->lock, flags);
1188 return;
1189 }
1190
1191 /* Link status check, Dynamic media type change */
1192 if (db->chip_id == PCI_DM9132_ID)
1193 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1194 else
1195 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1196
1197 if ( ((db->chip_id == PCI_DM9102_ID) &&
44c10138 1198 (db->chip_revision == 0x30)) ||
1da177e4 1199 ((db->chip_id == PCI_DM9132_ID) &&
44c10138 1200 (db->chip_revision == 0x10)) ) {
1da177e4
LT		 1201 /* DM9102A Chip */
1202 if (tmp_cr12 & 2)
cfa51b9d 1203 link_ok = 0;
1da177e4 1204 else
cfa51b9d 1205 link_ok = 1;
1da177e4 1206 }
cfa51b9d
ML		 1207 else
1208 /*0x43 is used instead of 0x3 because bit 6 should represent
1209 link status of external PHY */
1210 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1211
1212
1213 /* If chip reports that link is failed it could be because external
1214 PHY link status pin is not conected correctly to chip
1215 To be sure ask PHY too.
1216 */
1217
1218 /* need a dummy read because of PHY's register latch*/
1219 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1220 link_ok_phy = (phy_read (db->ioaddr,
1221 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1da177e4 1222
cfa51b9d
ML		 1223 if (link_ok_phy != link_ok) {
1224 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1225 link_ok = link_ok | link_ok_phy;
1226 }
1227
1228 if ( !link_ok && netif_carrier_ok(dev)) {
1da177e4
LT		 1229 /* Link Failed */
1230 DMFE_DBUG(0, "Link Failed", tmp_cr12);
cfa51b9d 1231 netif_carrier_off(dev);
1da177e4
LT		 1232
1233 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1234 /* AUTO or force 1M Homerun/Longrun don't need */
1235 if ( !(db->media_mode & 0x38) )
f67ba792
ML		 1236 phy_write(db->ioaddr, db->phy_addr,
1237 0, 0x1000, db->chip_id);
1da177e4
LT		 1238
1239 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1240 if (db->media_mode & DMFE_AUTO) {
1241 /* 10/100M link failed, used 1M Home-Net */
1242 db->cr6_data|=0x00040000; /* bit18=1, MII */
1243 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1244 update_cr6(db->cr6_data, db->ioaddr);
1245 }
cfa51b9d
ML		 1246 } else if (!netif_carrier_ok(dev)) {
1247
1248 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1249
1250 /* Auto Sense Speed */
1251 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1252 netif_carrier_on(dev);
1253 SHOW_MEDIA_TYPE(db->op_mode);
1da177e4
LT		 1254 }
1255
cfa51b9d
ML		 1256 dmfe_process_mode(db);
1257 }
1258
1da177e4
LT		 1259 /* HPNA remote command check */
1260 if (db->HPNA_command & 0xf00) {
1261 db->HPNA_timer--;
1262 if (!db->HPNA_timer)
1263 dmfe_HPNA_remote_cmd_chk(db);
1264 }
1265
1266 /* Timer active again */
1267 db->timer.expires = DMFE_TIMER_WUT;
1268 add_timer(&db->timer);
1269 spin_unlock_irqrestore(&db->lock, flags);
1270}
1271
1272
1273/*
1274 * Dynamic reset the DM910X board
1275 * Stop DM910X board
1276 * Free Tx/Rx allocated memory
1277 * Reset DM910X board
1278 * Re-initilize DM910X board
1279 */
1280
1281static void dmfe_dynamic_reset(struct DEVICE *dev)
1282{
1283 struct dmfe_board_info *db = netdev_priv(dev);
1284
1285 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1286
1287 /* Sopt MAC controller */
1288 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1289 update_cr6(db->cr6_data, dev->base_addr);
1290 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1291 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1292
1293 /* Disable upper layer interface */
1294 netif_stop_queue(dev);
1295
1296 /* Free Rx Allocate buffer */
1297 dmfe_free_rxbuffer(db);
1298
1299 /* system variable init */
1300 db->tx_packet_cnt = 0;
1301 db->tx_queue_cnt = 0;
1302 db->rx_avail_cnt = 0;
cfa51b9d 1303 netif_carrier_off(dev);
1da177e4
LT		 1304 db->wait_reset = 0;
1305
1306 /* Re-initilize DM910X board */
1307 dmfe_init_dm910x(dev);
1308
1309 /* Restart upper layer interface */
1310 netif_wake_queue(dev);
1311}
1312
1313
1314/*
1315 * free all allocated rx buffer
1316 */
1317
1318static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1319{
1320 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1321
1322 /* free allocated rx buffer */
1323 while (db->rx_avail_cnt) {
1324 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1325 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1326 db->rx_avail_cnt--;
1327 }
1328}
1329
1330
1331/*
1332 * Reuse the SK buffer
1333 */
1334
1335static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1336{
1337 struct rx_desc *rxptr = db->rx_insert_ptr;
1338
1339 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1340 rxptr->rx_skb_ptr = skb;
f67ba792
ML		 1341 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1342 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1343 wmb();
1344 rxptr->rdes0 = cpu_to_le32(0x80000000);
1345 db->rx_avail_cnt++;
1346 db->rx_insert_ptr = rxptr->next_rx_desc;
1347 } else
1348 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1349}
1350
1351
1352/*
1353 * Initialize transmit/Receive descriptor
1354 * Using Chain structure, and allocate Tx/Rx buffer
1355 */
1356
1357static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1358{
1359 struct tx_desc *tmp_tx;
1360 struct rx_desc *tmp_rx;
1361 unsigned char *tmp_buf;
1362 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1363 dma_addr_t tmp_buf_dma;
1364 int i;
1365
1366 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1367
1368 /* tx descriptor start pointer */
1369 db->tx_insert_ptr = db->first_tx_desc;
1370 db->tx_remove_ptr = db->first_tx_desc;
1371 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1372
1373 /* rx descriptor start pointer */
f67ba792
ML		 1374 db->first_rx_desc = (void *)db->first_tx_desc +
1375 sizeof(struct tx_desc) * TX_DESC_CNT;
1376
1377 db->first_rx_desc_dma = db->first_tx_desc_dma +
1378 sizeof(struct tx_desc) * TX_DESC_CNT;
1da177e4
LT		 1379 db->rx_insert_ptr = db->first_rx_desc;
1380 db->rx_ready_ptr = db->first_rx_desc;
1381 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1382
1383 /* Init Transmit chain */
1384 tmp_buf = db->buf_pool_start;
1385 tmp_buf_dma = db->buf_pool_dma_start;
1386 tmp_tx_dma = db->first_tx_desc_dma;
1387 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1388 tmp_tx->tx_buf_ptr = tmp_buf;
1389 tmp_tx->tdes0 = cpu_to_le32(0);
1390 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1391 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1392 tmp_tx_dma += sizeof(struct tx_desc);
1393 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1394 tmp_tx->next_tx_desc = tmp_tx + 1;
1395 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1396 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1397 }
1398 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1399 tmp_tx->next_tx_desc = db->first_tx_desc;
1400
1401 /* Init Receive descriptor chain */
1402 tmp_rx_dma=db->first_rx_desc_dma;
1403 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1404 tmp_rx->rdes0 = cpu_to_le32(0);
1405 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1406 tmp_rx_dma += sizeof(struct rx_desc);
1407 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1408 tmp_rx->next_rx_desc = tmp_rx + 1;
1409 }
1410 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1411 tmp_rx->next_rx_desc = db->first_rx_desc;
1412
1413 /* pre-allocate Rx buffer */
1414 allocate_rx_buffer(db);
1415}
1416
1417
1418/*
1419 * Update CR6 value
1420 * Firstly stop DM910X , then written value and start
1421 */
1422
1423static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1424{
1425 u32 cr6_tmp;
1426
1427 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1428 outl(cr6_tmp, ioaddr + DCR6);
1429 udelay(5);
1430 outl(cr6_data, ioaddr + DCR6);
1431 udelay(5);
1432}
1433
1434
1435/*
1436 * Send a setup frame for DM9132
1437 * This setup frame initilize DM910X address filter mode
1438*/
1439
1440static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1441{
1442 struct dev_mc_list *mcptr;
1443 u16 * addrptr;
1444 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1445 u32 hash_val;
1446 u16 i, hash_table[4];
1447
1448 DMFE_DBUG(0, "dm9132_id_table()", 0);
1449
1450 /* Node address */
1451 addrptr = (u16 *) dev->dev_addr;
1452 outw(addrptr[0], ioaddr);
1453 ioaddr += 4;
1454 outw(addrptr[1], ioaddr);
1455 ioaddr += 4;
1456 outw(addrptr[2], ioaddr);
1457 ioaddr += 4;
1458
1459 /* Clear Hash Table */
1460 for (i = 0; i < 4; i++)
1461 hash_table[i] = 0x0;
1462
1463 /* broadcast address */
1464 hash_table[3] = 0x8000;
1465
1466 /* the multicast address in Hash Table : 64 bits */
1467 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1468 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1469 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1470 }
1471
1472 /* Write the hash table to MAC MD table */
1473 for (i = 0; i < 4; i++, ioaddr += 4)
1474 outw(hash_table[i], ioaddr);
1475}
1476
1477
1478/*
1479 * Send a setup frame for DM9102/DM9102A
1480 * This setup frame initilize DM910X address filter mode
1481 */
1482
1483static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1484{
1485 struct dmfe_board_info *db = netdev_priv(dev);
1486 struct dev_mc_list *mcptr;
1487 struct tx_desc *txptr;
1488 u16 * addrptr;
1489 u32 * suptr;
1490 int i;
1491
1492 DMFE_DBUG(0, "send_filter_frame()", 0);
1493
1494 txptr = db->tx_insert_ptr;
1495 suptr = (u32 *) txptr->tx_buf_ptr;
1496
1497 /* Node address */
1498 addrptr = (u16 *) dev->dev_addr;
1499 *suptr++ = addrptr[0];
1500 *suptr++ = addrptr[1];
1501 *suptr++ = addrptr[2];
1502
1503 /* broadcast address */
1504 *suptr++ = 0xffff;
1505 *suptr++ = 0xffff;
1506 *suptr++ = 0xffff;
1507
1508 /* fit the multicast address */
1509 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1510 addrptr = (u16 *) mcptr->dmi_addr;
1511 *suptr++ = addrptr[0];
1512 *suptr++ = addrptr[1];
1513 *suptr++ = addrptr[2];
1514 }
1515
1516 for (; i<14; i++) {
1517 *suptr++ = 0xffff;
1518 *suptr++ = 0xffff;
1519 *suptr++ = 0xffff;
1520 }
1521
1522 /* prepare the setup frame */
1523 db->tx_insert_ptr = txptr->next_tx_desc;
1524 txptr->tdes1 = cpu_to_le32(0x890000c0);
1525
1526 /* Resource Check and Send the setup packet */
1527 if (!db->tx_packet_cnt) {
1528 /* Resource Empty */
1529 db->tx_packet_cnt++;
1530 txptr->tdes0 = cpu_to_le32(0x80000000);
1531 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1532 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1533 update_cr6(db->cr6_data, dev->base_addr);
1534 dev->trans_start = jiffies;
1535 } else
1536 db->tx_queue_cnt++; /* Put in TX queue */
1537}
1538
1539
1540/*
1541 * Allocate rx buffer,
1542 * As possible as allocate maxiumn Rx buffer
1543 */
1544
1545static void allocate_rx_buffer(struct dmfe_board_info *db)
1546{
1547 struct rx_desc *rxptr;
1548 struct sk_buff *skb;
1549
1550 rxptr = db->rx_insert_ptr;
1551
1552 while(db->rx_avail_cnt < RX_DESC_CNT) {
1553 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1554 break;
1555 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
f67ba792
ML		 1556 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1557 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1558 wmb();
1559 rxptr->rdes0 = cpu_to_le32(0x80000000);
1560 rxptr = rxptr->next_rx_desc;
1561 db->rx_avail_cnt++;
1562 }
1563
1564 db->rx_insert_ptr = rxptr;
1565}
1566
1567
1568/*
1569 * Read one word data from the serial ROM
1570 */
1571
1572static u16 read_srom_word(long ioaddr, int offset)
1573{
1574 int i;
1575 u16 srom_data = 0;
1576 long cr9_ioaddr = ioaddr + DCR9;
1577
1578 outl(CR9_SROM_READ, cr9_ioaddr);
1579 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1580
1581 /* Send the Read Command 110b */
1582 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1583 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1584 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1585
1586 /* Send the offset */
1587 for (i = 5; i >= 0; i--) {
1588 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1589 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1590 }
1591
1592 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1593
1594 for (i = 16; i > 0; i--) {
1595 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1596 udelay(5);
f67ba792
ML		 1597 srom_data = (srom_data << 1) |
1598 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1da177e4
LT		 1599 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1600 udelay(5);
1601 }
1602
1603 outl(CR9_SROM_READ, cr9_ioaddr);
1604 return srom_data;
1605}
1606
1607
1608/*
1609 * Auto sense the media mode
1610 */
1611
1612static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1613{
1614 u8 ErrFlag = 0;
1615 u16 phy_mode;
1616
1617 /* CR6 bit18=0, select 10/100M */
1618 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1619
1620 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1621 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1622
1623 if ( (phy_mode & 0x24) == 0x24 ) {
1624 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
f67ba792
ML		 1625 phy_mode = phy_read(db->ioaddr,
1626 db->phy_addr, 7, db->chip_id) & 0xf000;
1da177e4 1627 else /* DM9102/DM9102A */
f67ba792
ML		 1628 phy_mode = phy_read(db->ioaddr,
1629 db->phy_addr, 17, db->chip_id) & 0xf000;
1da177e4
LT		 1630 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1631 switch (phy_mode) {
1632 case 0x1000: db->op_mode = DMFE_10MHF; break;
1633 case 0x2000: db->op_mode = DMFE_10MFD; break;
1634 case 0x4000: db->op_mode = DMFE_100MHF; break;
1635 case 0x8000: db->op_mode = DMFE_100MFD; break;
1636 default: db->op_mode = DMFE_10MHF;
1637 ErrFlag = 1;
1638 break;
1639 }
1640 } else {
1641 db->op_mode = DMFE_10MHF;
1642 DMFE_DBUG(0, "Link Failed :", phy_mode);
1643 ErrFlag = 1;
1644 }
1645
1646 return ErrFlag;
1647}
1648
1649
1650/*
1651 * Set 10/100 phyxcer capability
1652 * AUTO mode : phyxcer register4 is NIC capability
1653 * Force mode: phyxcer register4 is the force media
1654 */
1655
1656static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1657{
1658 u16 phy_reg;
1659
1660 /* Select 10/100M phyxcer */
1661 db->cr6_data &= ~0x40000;
1662 update_cr6(db->cr6_data, db->ioaddr);
1663
1664 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1665 if (db->chip_id == PCI_DM9009_ID) {
f67ba792
ML		 1666 phy_reg = phy_read(db->ioaddr,
1667 db->phy_addr, 18, db->chip_id) & ~0x1000;
1668
1669 phy_write(db->ioaddr,
1670 db->phy_addr, 18, phy_reg, db->chip_id);
1da177e4
LT		 1671 }
1672
1673 /* Phyxcer capability setting */
1674 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1675
1676 if (db->media_mode & DMFE_AUTO) {
1677 /* AUTO Mode */
1678 phy_reg |= db->PHY_reg4;
1679 } else {
1680 /* Force Mode */
1681 switch(db->media_mode) {
1682 case DMFE_10MHF: phy_reg |= 0x20; break;
1683 case DMFE_10MFD: phy_reg |= 0x40; break;
1684 case DMFE_100MHF: phy_reg |= 0x80; break;
1685 case DMFE_100MFD: phy_reg |= 0x100; break;
1686 }
1687 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1688 }
1689
1690 /* Write new capability to Phyxcer Reg4 */
1691 if ( !(phy_reg & 0x01e0)) {
1692 phy_reg|=db->PHY_reg4;
1693 db->media_mode|=DMFE_AUTO;
1694 }
1695 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1696
1697 /* Restart Auto-Negotiation */
1698 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1699 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1700 if ( !db->chip_type )
1701 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1702}
1703
1704
1705/*
1706 * Process op-mode
1707 * AUTO mode : PHY controller in Auto-negotiation Mode
1708 * Force mode: PHY controller in force mode with HUB
1709 * N-way force capability with SWITCH
1710 */
1711
1712static void dmfe_process_mode(struct dmfe_board_info *db)
1713{
1714 u16 phy_reg;
1715
1716 /* Full Duplex Mode Check */
1717 if (db->op_mode & 0x4)
1718 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1719 else
1720 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1721
1722 /* Transciver Selection */
1723 if (db->op_mode & 0x10) /* 1M HomePNA */
1724 db->cr6_data |= 0x40000;/* External MII select */
1725 else
1726 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1727
1728 update_cr6(db->cr6_data, db->ioaddr);
1729
1730 /* 10/100M phyxcer force mode need */
1731 if ( !(db->media_mode & 0x18)) {
1732 /* Forece Mode */
1733 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1734 if ( !(phy_reg & 0x1) ) {
1735 /* parter without N-Way capability */
1736 phy_reg = 0x0;
1737 switch(db->op_mode) {
1738 case DMFE_10MHF: phy_reg = 0x0; break;
1739 case DMFE_10MFD: phy_reg = 0x100; break;
1740 case DMFE_100MHF: phy_reg = 0x2000; break;
1741 case DMFE_100MFD: phy_reg = 0x2100; break;
1742 }
f67ba792
ML		 1743 phy_write(db->ioaddr,
1744 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1745 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1746 mdelay(20);
f67ba792
ML		 1747 phy_write(db->ioaddr,
1748 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1749 }
1750 }
1751}
1752
1753
1754/*
1755 * Write a word to Phy register
1756 */
1757
f67ba792
ML		 1758static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1759 u16 phy_data, u32 chip_id)
1da177e4
LT		 1760{
1761 u16 i;
1762 unsigned long ioaddr;
1763
1764 if (chip_id == PCI_DM9132_ID) {
1765 ioaddr = iobase + 0x80 + offset * 4;
1766 outw(phy_data, ioaddr);
1767 } else {
1768 /* DM9102/DM9102A Chip */
1769 ioaddr = iobase + DCR9;
1770
1771 /* Send 33 synchronization clock to Phy controller */
1772 for (i = 0; i < 35; i++)
1773 phy_write_1bit(ioaddr, PHY_DATA_1);
1774
1775 /* Send start command(01) to Phy */
1776 phy_write_1bit(ioaddr, PHY_DATA_0);
1777 phy_write_1bit(ioaddr, PHY_DATA_1);
1778
1779 /* Send write command(01) to Phy */
1780 phy_write_1bit(ioaddr, PHY_DATA_0);
1781 phy_write_1bit(ioaddr, PHY_DATA_1);
1782
1783 /* Send Phy address */
1784 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1785 phy_write_1bit(ioaddr,
1786 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1787
1788 /* Send register address */
1789 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1790 phy_write_1bit(ioaddr,
1791 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1792
1793 /* written trasnition */
1794 phy_write_1bit(ioaddr, PHY_DATA_1);
1795 phy_write_1bit(ioaddr, PHY_DATA_0);
1796
1797 /* Write a word data to PHY controller */
1798 for ( i = 0x8000; i > 0; i >>= 1)
f67ba792
ML		 1799 phy_write_1bit(ioaddr,
1800 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1801 }
1802}
1803
1804
1805/*
1806 * Read a word data from phy register
1807 */
1808
1809static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1810{
1811 int i;
1812 u16 phy_data;
1813 unsigned long ioaddr;
1814
1815 if (chip_id == PCI_DM9132_ID) {
1816 /* DM9132 Chip */
1817 ioaddr = iobase + 0x80 + offset * 4;
1818 phy_data = inw(ioaddr);
1819 } else {
1820 /* DM9102/DM9102A Chip */
1821 ioaddr = iobase + DCR9;
1822
1823 /* Send 33 synchronization clock to Phy controller */
1824 for (i = 0; i < 35; i++)
1825 phy_write_1bit(ioaddr, PHY_DATA_1);
1826
1827 /* Send start command(01) to Phy */
1828 phy_write_1bit(ioaddr, PHY_DATA_0);
1829 phy_write_1bit(ioaddr, PHY_DATA_1);
1830
1831 /* Send read command(10) to Phy */
1832 phy_write_1bit(ioaddr, PHY_DATA_1);
1833 phy_write_1bit(ioaddr, PHY_DATA_0);
1834
1835 /* Send Phy address */
1836 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1837 phy_write_1bit(ioaddr,
1838 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1839
1840 /* Send register address */
1841 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1842 phy_write_1bit(ioaddr,
1843 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1844
1845 /* Skip transition state */
1846 phy_read_1bit(ioaddr);
1847
1848 /* read 16bit data */
1849 for (phy_data = 0, i = 0; i < 16; i++) {
1850 phy_data <<= 1;
1851 phy_data |= phy_read_1bit(ioaddr);
1852 }
1853 }
1854
1855 return phy_data;
1856}
1857
1858
1859/*
1860 * Write one bit data to Phy Controller
1861 */
1862
1863static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1864{
1865 outl(phy_data, ioaddr); /* MII Clock Low */
1866 udelay(1);
1867 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1868 udelay(1);
1869 outl(phy_data, ioaddr); /* MII Clock Low */
1870 udelay(1);
1871}
1872
1873
1874/*
1875 * Read one bit phy data from PHY controller
1876 */
1877
1878static u16 phy_read_1bit(unsigned long ioaddr)
1879{
1880 u16 phy_data;
1881
1882 outl(0x50000, ioaddr);
1883 udelay(1);
1884 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1885 outl(0x40000, ioaddr);
1886 udelay(1);
1887
1888 return phy_data;
1889}
1890
1891
1892/*
1893 * Parser SROM and media mode
1894 */
1895
1896static void dmfe_parse_srom(struct dmfe_board_info * db)
1897{
1898 char * srom = db->srom;
1899 int dmfe_mode, tmp_reg;
1900
1901 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1902
1903 /* Init CR15 */
1904 db->cr15_data = CR15_DEFAULT;
1905
1906 /* Check SROM Version */
1907 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1908 /* SROM V4.01 */
1909 /* Get NIC support media mode */
4c93566e 1910 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1da177e4
LT		 1911 db->PHY_reg4 = 0;
1912 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1913 switch( db->NIC_capability & tmp_reg ) {
1914 case 0x1: db->PHY_reg4 |= 0x0020; break;
1915 case 0x2: db->PHY_reg4 |= 0x0040; break;
1916 case 0x4: db->PHY_reg4 |= 0x0080; break;
1917 case 0x8: db->PHY_reg4 |= 0x0100; break;
1918 }
1919 }
1920
1921 /* Media Mode Force or not check */
4c93566e
DM		 1922 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1923 le32_to_cpup((__le32 *) (srom + 36)));
1da177e4
LT		 1924 switch(dmfe_mode) {
1925 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1926 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1927 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1928 case 0x100:
1929 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1930 }
1931
1932 /* Special Function setting */
1933 /* VLAN function */
1934 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1935 db->cr15_data |= 0x40;
1936
1937 /* Flow Control */
1938 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1939 db->cr15_data |= 0x400;
1940
1941 /* TX pause packet */
1942 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1943 db->cr15_data |= 0x9800;
1944 }
1945
1946 /* Parse HPNA parameter */
1947 db->HPNA_command = 1;
1948
1949 /* Accept remote command or not */
1950 if (HPNA_rx_cmd == 0)
1951 db->HPNA_command |= 0x8000;
1952
1953 /* Issue remote command & operation mode */
1954 if (HPNA_tx_cmd == 1)
1955 switch(HPNA_mode) { /* Issue Remote Command */
1956 case 0: db->HPNA_command |= 0x0904; break;
1957 case 1: db->HPNA_command |= 0x0a00; break;
1958 case 2: db->HPNA_command |= 0x0506; break;
1959 case 3: db->HPNA_command |= 0x0602; break;
1960 }
1961 else
1962 switch(HPNA_mode) { /* Don't Issue */
1963 case 0: db->HPNA_command |= 0x0004; break;
1964 case 1: db->HPNA_command |= 0x0000; break;
1965 case 2: db->HPNA_command |= 0x0006; break;
1966 case 3: db->HPNA_command |= 0x0002; break;
1967 }
1968
1969 /* Check DM9801 or DM9802 present or not */
1970 db->HPNA_present = 0;
1971 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1972 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1973 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1974 /* DM9801 or DM9802 present */
1975 db->HPNA_timer = 8;
1976 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1977 /* DM9801 HomeRun */
1978 db->HPNA_present = 1;
1979 dmfe_program_DM9801(db, tmp_reg);
1980 } else {
1981 /* DM9802 LongRun */
1982 db->HPNA_present = 2;
1983 dmfe_program_DM9802(db);
1984 }
1985 }
1986
1987}
1988
1989
1990/*
1991 * Init HomeRun DM9801
1992 */
1993
1994static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1995{
1996 uint reg17, reg25;
1997
1998 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1999 switch(HPNA_rev) {
2000 case 0xb900: /* DM9801 E3 */
2001 db->HPNA_command |= 0x1000;
2002 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2003 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2004 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2005 break;
2006 case 0xb901: /* DM9801 E4 */
2007 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2008 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2009 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2010 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2011 break;
2012 case 0xb902: /* DM9801 E5 */
2013 case 0xb903: /* DM9801 E6 */
2014 default:
2015 db->HPNA_command |= 0x1000;
2016 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2017 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2018 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2019 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2020 break;
2021 }
2022 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2023 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2024 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2025}
2026
2027
2028/*
2029 * Init HomeRun DM9802
2030 */
2031
2032static void dmfe_program_DM9802(struct dmfe_board_info * db)
2033{
2034 uint phy_reg;
2035
2036 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2037 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2038 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2039 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2040 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2041}
2042
2043
2044/*
2045 * Check remote HPNA power and speed status. If not correct,
2046 * issue command again.
2047*/
2048
2049static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2050{
2051 uint phy_reg;
2052
2053 /* Got remote device status */
2054 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2055 switch(phy_reg) {
2056 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2057 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2058 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2059 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2060 }
2061
2062 /* Check remote device status match our setting ot not */
2063 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
f67ba792
ML		 2064 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2065 db->chip_id);
1da177e4
LT		 2066 db->HPNA_timer=8;
2067 } else
2068 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2069}
2070
2071
2072
2073static struct pci_device_id dmfe_pci_tbl[] = {
2074 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2075 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2076 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2077 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2078 { 0, }
2079};
2080MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2081
2082
bc8a8387
ML		 2083#ifdef CONFIG_PM
2084static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2085{
2086 struct net_device *dev = pci_get_drvdata(pci_dev);
2087 struct dmfe_board_info *db = netdev_priv(dev);
f1069046 2088 u32 tmp;
bc8a8387
ML		 2089
2090 /* Disable upper layer interface */
2091 netif_device_detach(dev);
2092
2093 /* Disable Tx/Rx */
2094 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2095 update_cr6(db->cr6_data, dev->base_addr);
2096
2097 /* Disable Interrupt */
2098 outl(0, dev->base_addr + DCR7);
2099 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2100
2101 /* Fre RX buffers */
2102 dmfe_free_rxbuffer(db);
2103
f1069046
ML		 2104 /* Enable WOL */
2105 pci_read_config_dword(pci_dev, 0x40, &tmp);
2106 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2107
2108 if (db->wol_mode & WAKE_PHY)
2109 tmp |= DMFE_WOL_LINKCHANGE;
2110 if (db->wol_mode & WAKE_MAGIC)
2111 tmp |= DMFE_WOL_MAGICPACKET;
2112
2113 pci_write_config_dword(pci_dev, 0x40, tmp);
2114
2115 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2116 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2117
bc8a8387 2118 /* Power down device*/
bc8a8387 2119 pci_save_state(pci_dev);
a31e23e1 2120 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
bc8a8387
ML		 2121
2122 return 0;
2123}
2124
2125static int dmfe_resume(struct pci_dev *pci_dev)
2126{
2127 struct net_device *dev = pci_get_drvdata(pci_dev);
f1069046 2128 u32 tmp;
bc8a8387 2129
bc8a8387 2130 pci_set_power_state(pci_dev, PCI_D0);
65809b51 2131 pci_restore_state(pci_dev);
bc8a8387
ML		 2132
2133 /* Re-initilize DM910X board */
2134 dmfe_init_dm910x(dev);
2135
f1069046
ML		 2136 /* Disable WOL */
2137 pci_read_config_dword(pci_dev, 0x40, &tmp);
2138
2139 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2140 pci_write_config_dword(pci_dev, 0x40, tmp);
2141
2142 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2143 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2144
bc8a8387
ML		 2145 /* Restart upper layer interface */
2146 netif_device_attach(dev);
2147
2148 return 0;
2149}
2150#else
2151#define dmfe_suspend NULL
2152#define dmfe_resume NULL
2153#endif
2154
1da177e4
LT		 2155static struct pci_driver dmfe_driver = {
2156 .name = "dmfe",
2157 .id_table = dmfe_pci_tbl,
2158 .probe = dmfe_init_one,
2159 .remove = __devexit_p(dmfe_remove_one),
bc8a8387
ML		 2160 .suspend = dmfe_suspend,
2161 .resume = dmfe_resume
1da177e4
LT		 2162};
2163
2164MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2165MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2166MODULE_LICENSE("GPL");
2167MODULE_VERSION(DRV_VERSION);
2168
2169module_param(debug, int, 0);
2170module_param(mode, byte, 0);
2171module_param(cr6set, int, 0);
2172module_param(chkmode, byte, 0);
2173module_param(HPNA_mode, byte, 0);
2174module_param(HPNA_rx_cmd, byte, 0);
2175module_param(HPNA_tx_cmd, byte, 0);
2176module_param(HPNA_NoiseFloor, byte, 0);
2177module_param(SF_mode, byte, 0);
2178MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
f67ba792
ML		 2179MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2180 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2181
2182MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2183 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
1da177e4
LT		 2184
2185/* Description:
2186 * when user used insmod to add module, system invoked init_module()
2187 * to initilize and register.
2188 */
2189
2190static int __init dmfe_init_module(void)
2191{
2192 int rc;
2193
2194 printk(version);
2195 printed_version = 1;
2196
2197 DMFE_DBUG(0, "init_module() ", debug);
2198
2199 if (debug)
2200 dmfe_debug = debug; /* set debug flag */
2201 if (cr6set)
2202 dmfe_cr6_user_set = cr6set;
2203
2204 switch(mode) {
2205 case DMFE_10MHF:
2206 case DMFE_100MHF:
2207 case DMFE_10MFD:
2208 case DMFE_100MFD:
2209 case DMFE_1M_HPNA:
2210 dmfe_media_mode = mode;
2211 break;
2212 default:dmfe_media_mode = DMFE_AUTO;
2213 break;
2214 }
2215
2216 if (HPNA_mode > 4)
2217 HPNA_mode = 0; /* Default: LP/HS */
2218 if (HPNA_rx_cmd > 1)
2219 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2220 if (HPNA_tx_cmd > 1)
2221 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2222 if (HPNA_NoiseFloor > 15)
2223 HPNA_NoiseFloor = 0;
2224
29917620 2225 rc = pci_register_driver(&dmfe_driver);
1da177e4
LT		 2226 if (rc < 0)
2227 return rc;
2228
2229 return 0;
2230}
2231
2232
2233/*
2234 * Description:
2235 * when user used rmmod to delete module, system invoked clean_module()
2236 * to un-register all registered services.
2237 */
2238
2239static void __exit dmfe_cleanup_module(void)
2240{
2241 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2242 pci_unregister_driver(&dmfe_driver);
2243}
2244
2245module_init(dmfe_init_module);
2246module_exit(dmfe_cleanup_module);
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