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[net-next-2.6.git] / drivers / net / tulip / dmfe.c
CommitLineData
1da177e4
LT		 1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
113aa838 26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
1da177e4
LT		 27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
113aa838 52 Alan Cox <alan@lxorguk.ukuu.org.uk>
f3b197ac 53 Added new PCI identifiers provided by Clear Zhang at ALi
1da177e4
LT		 54 for their 1563 ethernet device.
55
56 TODO
57
1da177e4
LT		 58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62*/
63
64#define DRV_NAME "dmfe"
65#define DRV_VERSION "1.36.4"
66#define DRV_RELDATE "2002-01-17"
67
68#include <linux/module.h>
69#include <linux/kernel.h>
70#include <linux/string.h>
71#include <linux/timer.h>
72#include <linux/ptrace.h>
73#include <linux/errno.h>
74#include <linux/ioport.h>
75#include <linux/slab.h>
76#include <linux/interrupt.h>
77#include <linux/pci.h>
cb199d42 78#include <linux/dma-mapping.h>
1da177e4
LT		 79#include <linux/init.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/ethtool.h>
83#include <linux/skbuff.h>
84#include <linux/delay.h>
85#include <linux/spinlock.h>
86#include <linux/crc32.h>
87#include <linux/bitops.h>
88
89#include <asm/processor.h>
90#include <asm/io.h>
91#include <asm/dma.h>
92#include <asm/uaccess.h>
93#include <asm/irq.h>
94
95
96/* Board/System/Debug information/definition ---------------- */
97#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
98#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
99#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
100#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
101
102#define DM9102_IO_SIZE 0x80
103#define DM9102A_IO_SIZE 0x100
104#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
105#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
106#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
107#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
108#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
109#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
110#define TX_BUF_ALLOC 0x600
111#define RX_ALLOC_SIZE 0x620
112#define DM910X_RESET 1
113#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
114#define CR6_DEFAULT 0x00080000 /* HD */
115#define CR7_DEFAULT 0x180c1
116#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
117#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
118#define MAX_PACKET_SIZE 1514
119#define DMFE_MAX_MULTICAST 14
120#define RX_COPY_SIZE 100
121#define MAX_CHECK_PACKET 0x8000
122#define DM9801_NOISE_FLOOR 8
123#define DM9802_NOISE_FLOOR 5
124
f1069046
ML		 125#define DMFE_WOL_LINKCHANGE 0x20000000
126#define DMFE_WOL_SAMPLEPACKET 0x10000000
127#define DMFE_WOL_MAGICPACKET 0x08000000
128
129
1da177e4
LT		 130#define DMFE_10MHF 0
131#define DMFE_100MHF 1
132#define DMFE_10MFD 4
133#define DMFE_100MFD 5
134#define DMFE_AUTO 8
135#define DMFE_1M_HPNA 0x10
136
137#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
138#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
139#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
140#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
141#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
142#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
143
144#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
145#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
146#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
147
f67ba792
ML		 148#define DMFE_DBUG(dbug_now, msg, value) \
149 do { \
150 if (dmfe_debug || (dbug_now)) \
151 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
152 (msg), (long) (value)); \
153 } while (0)
1da177e4 154
f67ba792
ML		 155#define SHOW_MEDIA_TYPE(mode) \
156 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
157 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
1da177e4
LT		 158
159
160/* CR9 definition: SROM/MII */
161#define CR9_SROM_READ 0x4800
162#define CR9_SRCS 0x1
163#define CR9_SRCLK 0x2
164#define CR9_CRDOUT 0x8
165#define SROM_DATA_0 0x0
166#define SROM_DATA_1 0x4
167#define PHY_DATA_1 0x20000
168#define PHY_DATA_0 0x00000
169#define MDCLKH 0x10000
170
171#define PHY_POWER_DOWN 0x800
172
173#define SROM_V41_CODE 0x14
174
f67ba792
ML		 175#define SROM_CLK_WRITE(data, ioaddr) \
176 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
177 udelay(5); \
178 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
179 udelay(5); \
180 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
181 udelay(5);
182
183#define __CHK_IO_SIZE(pci_id, dev_rev) \
44c10138 184 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
f67ba792 185 DM9102A_IO_SIZE: DM9102_IO_SIZE)
1da177e4 186
44c10138
AK		 187#define CHK_IO_SIZE(pci_dev) \
188 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
189 (pci_dev)->revision))
1da177e4
LT		 190
191/* Sten Check */
192#define DEVICE net_device
193
194/* Structure/enum declaration ------------------------------- */
195struct tx_desc {
a31e40f6 196 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
1da177e4
LT		 197 char *tx_buf_ptr; /* Data for us */
198 struct tx_desc *next_tx_desc;
199} __attribute__(( aligned(32) ));
200
201struct rx_desc {
a31e40f6 202 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
1da177e4
LT		 203 struct sk_buff *rx_skb_ptr; /* Data for us */
204 struct rx_desc *next_rx_desc;
205} __attribute__(( aligned(32) ));
206
207struct dmfe_board_info {
208 u32 chip_id; /* Chip vendor/Device ID */
44c10138 209 u8 chip_revision; /* Chip revision */
ead9bffb 210 struct DEVICE *next_dev; /* next device */
1da177e4
LT		 211 struct pci_dev *pdev; /* PCI device */
212 spinlock_t lock;
213
214 long ioaddr; /* I/O base address */
215 u32 cr0_data;
216 u32 cr5_data;
217 u32 cr6_data;
218 u32 cr7_data;
219 u32 cr15_data;
220
221 /* pointer for memory physical address */
222 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
223 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
224 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
225 dma_addr_t first_tx_desc_dma;
226 dma_addr_t first_rx_desc_dma;
227
228 /* descriptor pointer */
229 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
230 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
231 unsigned char *desc_pool_ptr; /* descriptor pool memory */
232 struct tx_desc *first_tx_desc;
233 struct tx_desc *tx_insert_ptr;
234 struct tx_desc *tx_remove_ptr;
235 struct rx_desc *first_rx_desc;
236 struct rx_desc *rx_insert_ptr;
237 struct rx_desc *rx_ready_ptr; /* packet come pointer */
238 unsigned long tx_packet_cnt; /* transmitted packet count */
239 unsigned long tx_queue_cnt; /* wait to send packet count */
240 unsigned long rx_avail_cnt; /* available rx descriptor count */
241 unsigned long interval_rx_cnt; /* rx packet count a callback time */
242
243 u16 HPNA_command; /* For HPNA register 16 */
244 u16 HPNA_timer; /* For HPNA remote device check */
245 u16 dbug_cnt;
246 u16 NIC_capability; /* NIC media capability */
247 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
248
249 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
250 u8 chip_type; /* Keep DM9102A chip type */
251 u8 media_mode; /* user specify media mode */
252 u8 op_mode; /* real work media mode */
253 u8 phy_addr;
1da177e4
LT		 254 u8 wait_reset; /* Hardware failed, need to reset */
255 u8 dm910x_chk_mode; /* Operating mode check */
256 u8 first_in_callback; /* Flag to record state */
f1069046 257 u8 wol_mode; /* user WOL settings */
1da177e4
LT		 258 struct timer_list timer;
259
1da177e4
LT		 260 /* Driver defined statistic counter */
261 unsigned long tx_fifo_underrun;
262 unsigned long tx_loss_carrier;
263 unsigned long tx_no_carrier;
264 unsigned long tx_late_collision;
265 unsigned long tx_excessive_collision;
266 unsigned long tx_jabber_timeout;
267 unsigned long reset_count;
268 unsigned long reset_cr8;
269 unsigned long reset_fatal;
270 unsigned long reset_TXtimeout;
271
272 /* NIC SROM data */
273 unsigned char srom[128];
274};
275
276enum dmfe_offsets {
277 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
278 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
279 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
280 DCR15 = 0x78
281};
282
283enum dmfe_CR6_bits {
284 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
285 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
286 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
287};
288
289/* Global variable declaration ----------------------------- */
290static int __devinitdata printed_version;
03f54b3d 291static const char version[] __devinitconst =
1da177e4
LT		 292 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
293 DRV_VERSION " (" DRV_RELDATE ")\n";
294
295static int dmfe_debug;
296static unsigned char dmfe_media_mode = DMFE_AUTO;
297static u32 dmfe_cr6_user_set;
298
299/* For module input parameter */
300static int debug;
301static u32 cr6set;
302static unsigned char mode = 8;
303static u8 chkmode = 1;
304static u8 HPNA_mode; /* Default: Low Power/High Speed */
305static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
306static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
307static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
308static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
309 4: TX pause packet */
310
311
312/* function declaration ------------------------------------- */
313static int dmfe_open(struct DEVICE *);
ad096463 314static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
1da177e4 315static int dmfe_stop(struct DEVICE *);
1da177e4 316static void dmfe_set_filter_mode(struct DEVICE *);
7282d491 317static const struct ethtool_ops netdev_ethtool_ops;
1da177e4 318static u16 read_srom_word(long ,int);
7d12e780 319static irqreturn_t dmfe_interrupt(int , void *);
1da177e4
LT		 320#ifdef CONFIG_NET_POLL_CONTROLLER
321static void poll_dmfe (struct net_device *dev);
322#endif
323static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
324static void allocate_rx_buffer(struct dmfe_board_info *);
325static void update_cr6(u32, unsigned long);
326static void send_filter_frame(struct DEVICE * ,int);
327static void dm9132_id_table(struct DEVICE * ,int);
328static u16 phy_read(unsigned long, u8, u8, u32);
329static void phy_write(unsigned long, u8, u8, u16, u32);
330static void phy_write_1bit(unsigned long, u32);
331static u16 phy_read_1bit(unsigned long);
332static u8 dmfe_sense_speed(struct dmfe_board_info *);
333static void dmfe_process_mode(struct dmfe_board_info *);
334static void dmfe_timer(unsigned long);
335static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
336static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
337static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
338static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
339static void dmfe_dynamic_reset(struct DEVICE *);
340static void dmfe_free_rxbuffer(struct dmfe_board_info *);
341static void dmfe_init_dm910x(struct DEVICE *);
342static void dmfe_parse_srom(struct dmfe_board_info *);
343static void dmfe_program_DM9801(struct dmfe_board_info *, int);
344static void dmfe_program_DM9802(struct dmfe_board_info *);
345static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
346static void dmfe_set_phyxcer(struct dmfe_board_info *);
347
f67ba792 348/* DM910X network board routine ---------------------------- */
1da177e4 349
2765df58
SH		 350static const struct net_device_ops netdev_ops = {
351 .ndo_open = dmfe_open,
352 .ndo_stop = dmfe_stop,
353 .ndo_start_xmit = dmfe_start_xmit,
354 .ndo_set_multicast_list = dmfe_set_filter_mode,
355 .ndo_change_mtu = eth_change_mtu,
356 .ndo_set_mac_address = eth_mac_addr,
357 .ndo_validate_addr = eth_validate_addr,
358#ifdef CONFIG_NET_POLL_CONTROLLER
359 .ndo_poll_controller = poll_dmfe,
360#endif
361};
362
1da177e4
LT		 363/*
364 * Search DM910X board ,allocate space and register it
365 */
366
367static int __devinit dmfe_init_one (struct pci_dev *pdev,
368 const struct pci_device_id *ent)
369{
370 struct dmfe_board_info *db; /* board information structure */
371 struct net_device *dev;
44c10138 372 u32 pci_pmr;
1da177e4
LT		 373 int i, err;
374
375 DMFE_DBUG(0, "dmfe_init_one()", 0);
376
377 if (!printed_version++)
378 printk(version);
379
380 /* Init network device */
381 dev = alloc_etherdev(sizeof(*db));
382 if (dev == NULL)
383 return -ENOMEM;
1da177e4
LT		 384 SET_NETDEV_DEV(dev, &pdev->dev);
385
284901a9 386 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
f67ba792
ML		 387 printk(KERN_WARNING DRV_NAME
388 ": 32-bit PCI DMA not available.\n");
1da177e4
LT		 389 err = -ENODEV;
390 goto err_out_free;
391 }
392
393 /* Enable Master/IO access, Disable memory access */
394 err = pci_enable_device(pdev);
395 if (err)
396 goto err_out_free;
397
398 if (!pci_resource_start(pdev, 0)) {
399 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
400 err = -ENODEV;
401 goto err_out_disable;
402 }
403
44c10138 404 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
1da177e4
LT		 405 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
406 err = -ENODEV;
407 goto err_out_disable;
408 }
409
410#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
411
412 /* Set Latency Timer 80h */
413 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
414 Need a PCI quirk.. */
415
416 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
417#endif
418
419 if (pci_request_regions(pdev, DRV_NAME)) {
420 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
421 err = -ENODEV;
422 goto err_out_disable;
423 }
424
425 /* Init system & device */
426 db = netdev_priv(dev);
427
428 /* Allocate Tx/Rx descriptor memory */
f67ba792
ML		 429 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
430 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
74d5e8ac
FT		 431 if (!db->desc_pool_ptr)
432 goto err_out_res;
f67ba792
ML		 433
434 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
435 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
74d5e8ac
FT		 436 if (!db->buf_pool_ptr)
437 goto err_out_free_desc;
1da177e4
LT		 438
439 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
440 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
441 db->buf_pool_start = db->buf_pool_ptr;
442 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
443
444 db->chip_id = ent->driver_data;
445 db->ioaddr = pci_resource_start(pdev, 0);
44c10138 446 db->chip_revision = pdev->revision;
f1069046 447 db->wol_mode = 0;
1da177e4
LT		 448
449 db->pdev = pdev;
450
451 dev->base_addr = db->ioaddr;
452 dev->irq = pdev->irq;
453 pci_set_drvdata(pdev, dev);
2765df58 454 dev->netdev_ops = &netdev_ops;
1da177e4 455 dev->ethtool_ops = &netdev_ethtool_ops;
cfa51b9d 456 netif_carrier_off(dev);
1da177e4
LT		 457 spin_lock_init(&db->lock);
458
459 pci_read_config_dword(pdev, 0x50, &pci_pmr);
460 pci_pmr &= 0x70000;
44c10138 461 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
1da177e4
LT		 462 db->chip_type = 1; /* DM9102A E3 */
463 else
464 db->chip_type = 0;
465
466 /* read 64 word srom data */
467 for (i = 0; i < 64; i++)
a31e40f6 468 ((__le16 *) db->srom)[i] =
f67ba792 469 cpu_to_le16(read_srom_word(db->ioaddr, i));
1da177e4
LT		 470
471 /* Set Node address */
472 for (i = 0; i < 6; i++)
473 dev->dev_addr[i] = db->srom[20 + i];
474
475 err = register_netdev (dev);
476 if (err)
74d5e8ac 477 goto err_out_free_buf;
1da177e4 478
e174961c 479 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s, %pM, irq %d.\n",
0795af57
JP		 480 dev->name,
481 ent->driver_data >> 16,
482 pci_name(pdev),
e174961c 483 dev->dev_addr,
0795af57 484 dev->irq);
1da177e4
LT		 485
486 pci_set_master(pdev);
487
488 return 0;
489
74d5e8ac
FT		 490err_out_free_buf:
491 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
492 db->buf_pool_ptr, db->buf_pool_dma_ptr);
493err_out_free_desc:
494 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
495 db->desc_pool_ptr, db->desc_pool_dma_ptr);
1da177e4
LT		 496err_out_res:
497 pci_release_regions(pdev);
498err_out_disable:
499 pci_disable_device(pdev);
500err_out_free:
501 pci_set_drvdata(pdev, NULL);
502 free_netdev(dev);
503
504 return err;
505}
506
507
508static void __devexit dmfe_remove_one (struct pci_dev *pdev)
509{
510 struct net_device *dev = pci_get_drvdata(pdev);
511 struct dmfe_board_info *db = netdev_priv(dev);
512
513 DMFE_DBUG(0, "dmfe_remove_one()", 0);
514
515 if (dev) {
4dc68f3d
ML		 516
517 unregister_netdev(dev);
518
1da177e4
LT		 519 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
520 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
521 db->desc_pool_dma_ptr);
522 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
523 db->buf_pool_ptr, db->buf_pool_dma_ptr);
1da177e4
LT		 524 pci_release_regions(pdev);
525 free_netdev(dev); /* free board information */
4dc68f3d 526
1da177e4
LT		 527 pci_set_drvdata(pdev, NULL);
528 }
529
530 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
531}
532
533
534/*
535 * Open the interface.
536 * The interface is opened whenever "ifconfig" actives it.
537 */
538
539static int dmfe_open(struct DEVICE *dev)
540{
541 int ret;
542 struct dmfe_board_info *db = netdev_priv(dev);
543
544 DMFE_DBUG(0, "dmfe_open", 0);
545
a0607fd3 546 ret = request_irq(dev->irq, dmfe_interrupt,
f67ba792 547 IRQF_SHARED, dev->name, dev);
1da177e4
LT		 548 if (ret)
549 return ret;
550
551 /* system variable init */
552 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
553 db->tx_packet_cnt = 0;
554 db->tx_queue_cnt = 0;
555 db->rx_avail_cnt = 0;
1da177e4
LT		 556 db->wait_reset = 0;
557
558 db->first_in_callback = 0;
559 db->NIC_capability = 0xf; /* All capability*/
560 db->PHY_reg4 = 0x1e0;
561
562 /* CR6 operation mode decision */
563 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
44c10138 564 (db->chip_revision >= 0x30) ) {
1da177e4
LT		 565 db->cr6_data |= DMFE_TXTH_256;
566 db->cr0_data = CR0_DEFAULT;
567 db->dm910x_chk_mode=4; /* Enter the normal mode */
568 } else {
569 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
570 db->cr0_data = 0;
571 db->dm910x_chk_mode = 1; /* Enter the check mode */
572 }
573
574 /* Initilize DM910X board */
575 dmfe_init_dm910x(dev);
576
577 /* Active System Interface */
578 netif_wake_queue(dev);
579
580 /* set and active a timer process */
581 init_timer(&db->timer);
582 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
583 db->timer.data = (unsigned long)dev;
584 db->timer.function = &dmfe_timer;
585 add_timer(&db->timer);
586
587 return 0;
588}
589
590
591/* Initilize DM910X board
592 * Reset DM910X board
593 * Initilize TX/Rx descriptor chain structure
594 * Send the set-up frame
595 * Enable Tx/Rx machine
596 */
597
598static void dmfe_init_dm910x(struct DEVICE *dev)
599{
600 struct dmfe_board_info *db = netdev_priv(dev);
601 unsigned long ioaddr = db->ioaddr;
602
603 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
604
605 /* Reset DM910x MAC controller */
606 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
607 udelay(100);
608 outl(db->cr0_data, ioaddr + DCR0);
609 udelay(5);
610
611 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
612 db->phy_addr = 1;
613
614 /* Parser SROM and media mode */
615 dmfe_parse_srom(db);
616 db->media_mode = dmfe_media_mode;
617
618 /* RESET Phyxcer Chip by GPR port bit 7 */
619 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
620 if (db->chip_id == PCI_DM9009_ID) {
621 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
622 mdelay(300); /* Delay 300 ms */
623 }
624 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
625
626 /* Process Phyxcer Media Mode */
627 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
628 dmfe_set_phyxcer(db);
629
630 /* Media Mode Process */
631 if ( !(db->media_mode & DMFE_AUTO) )
632 db->op_mode = db->media_mode; /* Force Mode */
633
634 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
635 dmfe_descriptor_init(db, ioaddr);
636
637 /* Init CR6 to program DM910x operation */
638 update_cr6(db->cr6_data, ioaddr);
639
640 /* Send setup frame */
641 if (db->chip_id == PCI_DM9132_ID)
642 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
643 else
644 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
645
646 /* Init CR7, interrupt active bit */
647 db->cr7_data = CR7_DEFAULT;
648 outl(db->cr7_data, ioaddr + DCR7);
649
650 /* Init CR15, Tx jabber and Rx watchdog timer */
651 outl(db->cr15_data, ioaddr + DCR15);
652
653 /* Enable DM910X Tx/Rx function */
654 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
655 update_cr6(db->cr6_data, ioaddr);
656}
657
658
659/*
660 * Hardware start transmission.
661 * Send a packet to media from the upper layer.
662 */
663
ad096463
SH		 664static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
665 struct DEVICE *dev)
1da177e4
LT		 666{
667 struct dmfe_board_info *db = netdev_priv(dev);
668 struct tx_desc *txptr;
669 unsigned long flags;
670
671 DMFE_DBUG(0, "dmfe_start_xmit", 0);
672
673 /* Resource flag check */
674 netif_stop_queue(dev);
675
676 /* Too large packet check */
677 if (skb->len > MAX_PACKET_SIZE) {
678 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
679 dev_kfree_skb(skb);
ec634fe3 680 return NETDEV_TX_OK;
1da177e4
LT		 681 }
682
683 spin_lock_irqsave(&db->lock, flags);
684
685 /* No Tx resource check, it never happen nromally */
686 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
687 spin_unlock_irqrestore(&db->lock, flags);
f67ba792
ML		 688 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
689 db->tx_queue_cnt);
5b548140 690 return NETDEV_TX_BUSY;
1da177e4
LT		 691 }
692
693 /* Disable NIC interrupt */
694 outl(0, dev->base_addr + DCR7);
695
696 /* transmit this packet */
697 txptr = db->tx_insert_ptr;
d626f62b 698 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
1da177e4
LT		 699 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
700
701 /* Point to next transmit free descriptor */
702 db->tx_insert_ptr = txptr->next_tx_desc;
703
704 /* Transmit Packet Process */
705 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
706 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
707 db->tx_packet_cnt++; /* Ready to send */
708 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
709 dev->trans_start = jiffies; /* saved time stamp */
710 } else {
711 db->tx_queue_cnt++; /* queue TX packet */
712 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
713 }
714
715 /* Tx resource check */
716 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
717 netif_wake_queue(dev);
718
719 /* Restore CR7 to enable interrupt */
720 spin_unlock_irqrestore(&db->lock, flags);
721 outl(db->cr7_data, dev->base_addr + DCR7);
722
723 /* free this SKB */
724 dev_kfree_skb(skb);
725
ec634fe3 726 return NETDEV_TX_OK;
1da177e4
LT		 727}
728
729
730/*
731 * Stop the interface.
732 * The interface is stopped when it is brought.
733 */
734
735static int dmfe_stop(struct DEVICE *dev)
736{
737 struct dmfe_board_info *db = netdev_priv(dev);
738 unsigned long ioaddr = dev->base_addr;
739
740 DMFE_DBUG(0, "dmfe_stop", 0);
741
742 /* disable system */
743 netif_stop_queue(dev);
744
745 /* deleted timer */
746 del_timer_sync(&db->timer);
747
748 /* Reset & stop DM910X board */
749 outl(DM910X_RESET, ioaddr + DCR0);
750 udelay(5);
751 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
752
753 /* free interrupt */
754 free_irq(dev->irq, dev);
755
756 /* free allocated rx buffer */
757 dmfe_free_rxbuffer(db);
758
759#if 0
760 /* show statistic counter */
f67ba792
ML		 761 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
762 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
1da177e4
LT		 763 db->tx_fifo_underrun, db->tx_excessive_collision,
764 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
765 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
766 db->reset_fatal, db->reset_TXtimeout);
767#endif
768
769 return 0;
770}
771
772
773/*
774 * DM9102 insterrupt handler
775 * receive the packet to upper layer, free the transmitted packet
776 */
777
7d12e780 778static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
1da177e4
LT		 779{
780 struct DEVICE *dev = dev_id;
781 struct dmfe_board_info *db = netdev_priv(dev);
782 unsigned long ioaddr = dev->base_addr;
783 unsigned long flags;
784
785 DMFE_DBUG(0, "dmfe_interrupt()", 0);
786
1da177e4
LT		 787 spin_lock_irqsave(&db->lock, flags);
788
789 /* Got DM910X status */
790 db->cr5_data = inl(ioaddr + DCR5);
791 outl(db->cr5_data, ioaddr + DCR5);
792 if ( !(db->cr5_data & 0xc1) ) {
793 spin_unlock_irqrestore(&db->lock, flags);
794 return IRQ_HANDLED;
795 }
796
797 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
798 outl(0, ioaddr + DCR7);
799
800 /* Check system status */
801 if (db->cr5_data & 0x2000) {
802 /* system bus error happen */
803 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
804 db->reset_fatal++;
805 db->wait_reset = 1; /* Need to RESET */
806 spin_unlock_irqrestore(&db->lock, flags);
807 return IRQ_HANDLED;
808 }
809
810 /* Received the coming packet */
811 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
812 dmfe_rx_packet(dev, db);
813
814 /* reallocate rx descriptor buffer */
815 if (db->rx_avail_cnt<RX_DESC_CNT)
816 allocate_rx_buffer(db);
817
818 /* Free the transmitted descriptor */
819 if ( db->cr5_data & 0x01)
820 dmfe_free_tx_pkt(dev, db);
821
822 /* Mode Check */
823 if (db->dm910x_chk_mode & 0x2) {
824 db->dm910x_chk_mode = 0x4;
825 db->cr6_data |= 0x100;
826 update_cr6(db->cr6_data, db->ioaddr);
827 }
828
829 /* Restore CR7 to enable interrupt mask */
830 outl(db->cr7_data, ioaddr + DCR7);
831
832 spin_unlock_irqrestore(&db->lock, flags);
833 return IRQ_HANDLED;
834}
835
836
837#ifdef CONFIG_NET_POLL_CONTROLLER
838/*
839 * Polling 'interrupt' - used by things like netconsole to send skbs
840 * without having to re-enable interrupts. It's not called while
841 * the interrupt routine is executing.
842 */
843
844static void poll_dmfe (struct net_device *dev)
845{
846 /* disable_irq here is not very nice, but with the lockless
847 interrupt handler we have no other choice. */
848 disable_irq(dev->irq);
7d12e780 849 dmfe_interrupt (dev->irq, dev);
1da177e4
LT		 850 enable_irq(dev->irq);
851}
852#endif
853
854/*
855 * Free TX resource after TX complete
856 */
857
858static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
859{
860 struct tx_desc *txptr;
861 unsigned long ioaddr = dev->base_addr;
862 u32 tdes0;
863
864 txptr = db->tx_remove_ptr;
865 while(db->tx_packet_cnt) {
866 tdes0 = le32_to_cpu(txptr->tdes0);
867 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
868 if (tdes0 & 0x80000000)
869 break;
870
871 /* A packet sent completed */
872 db->tx_packet_cnt--;
2765df58 873 dev->stats.tx_packets++;
1da177e4
LT		 874
875 /* Transmit statistic counter */
876 if ( tdes0 != 0x7fffffff ) {
877 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
2765df58
SH		 878 dev->stats.collisions += (tdes0 >> 3) & 0xf;
879 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
1da177e4 880 if (tdes0 & TDES0_ERR_MASK) {
2765df58 881 dev->stats.tx_errors++;
1da177e4
LT		 882
883 if (tdes0 & 0x0002) { /* UnderRun */
884 db->tx_fifo_underrun++;
885 if ( !(db->cr6_data & CR6_SFT) ) {
886 db->cr6_data = db->cr6_data | CR6_SFT;
887 update_cr6(db->cr6_data, db->ioaddr);
888 }
889 }
890 if (tdes0 & 0x0100)
891 db->tx_excessive_collision++;
892 if (tdes0 & 0x0200)
893 db->tx_late_collision++;
894 if (tdes0 & 0x0400)
895 db->tx_no_carrier++;
896 if (tdes0 & 0x0800)
897 db->tx_loss_carrier++;
898 if (tdes0 & 0x4000)
899 db->tx_jabber_timeout++;
900 }
901 }
902
903 txptr = txptr->next_tx_desc;
904 }/* End of while */
905
906 /* Update TX remove pointer to next */
907 db->tx_remove_ptr = txptr;
908
909 /* Send the Tx packet in queue */
910 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
911 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
912 db->tx_packet_cnt++; /* Ready to send */
913 db->tx_queue_cnt--;
914 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
915 dev->trans_start = jiffies; /* saved time stamp */
916 }
917
918 /* Resource available check */
919 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
920 netif_wake_queue(dev); /* Active upper layer, send again */
921}
922
923
924/*
925 * Calculate the CRC valude of the Rx packet
926 * flag = 1 : return the reverse CRC (for the received packet CRC)
927 * 0 : return the normal CRC (for Hash Table index)
928 */
929
930static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
931{
932 u32 crc = crc32(~0, Data, Len);
933 if (flag) crc = ~crc;
934 return crc;
935}
936
937
938/*
939 * Receive the come packet and pass to upper layer
940 */
941
942static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
943{
944 struct rx_desc *rxptr;
4dc68f3d 945 struct sk_buff *skb, *newskb;
1da177e4
LT		 946 int rxlen;
947 u32 rdes0;
948
949 rxptr = db->rx_ready_ptr;
950
951 while(db->rx_avail_cnt) {
952 rdes0 = le32_to_cpu(rxptr->rdes0);
953 if (rdes0 & 0x80000000) /* packet owner check */
954 break;
955
956 db->rx_avail_cnt--;
957 db->interval_rx_cnt++;
958
f67ba792
ML		 959 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
960 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
961
1da177e4
LT		 962 if ( (rdes0 & 0x300) != 0x300) {
963 /* A packet without First/Last flag */
964 /* reuse this SKB */
965 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
966 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
967 } else {
968 /* A packet with First/Last flag */
969 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
970
971 /* error summary bit check */
972 if (rdes0 & 0x8000) {
973 /* This is a error packet */
974 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
2765df58 975 dev->stats.rx_errors++;
1da177e4 976 if (rdes0 & 1)
2765df58 977 dev->stats.rx_fifo_errors++;
1da177e4 978 if (rdes0 & 2)
2765df58 979 dev->stats.rx_crc_errors++;
1da177e4 980 if (rdes0 & 0x80)
2765df58 981 dev->stats.rx_length_errors++;
1da177e4
LT		 982 }
983
984 if ( !(rdes0 & 0x8000) ||
985 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
986 skb = rxptr->rx_skb_ptr;
987
988 /* Received Packet CRC check need or not */
989 if ( (db->dm910x_chk_mode & 1) &&
689be439
DM		 990 (cal_CRC(skb->data, rxlen, 1) !=
991 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1da177e4
LT		 992 /* Found a error received packet */
993 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
994 db->dm910x_chk_mode = 3;
995 } else {
996 /* Good packet, send to upper layer */
997 /* Shorst packet used new SKB */
4dc68f3d
ML		 998 if ((rxlen < RX_COPY_SIZE) &&
999 ((newskb = dev_alloc_skb(rxlen + 2))
1000 != NULL)) {
1001
1002 skb = newskb;
1da177e4 1003 /* size less than COPY_SIZE, allocate a rxlen SKB */
1da177e4 1004 skb_reserve(skb, 2); /* 16byte align */
d626f62b
ACM		 1005 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1006 skb_put(skb, rxlen),
1007 rxlen);
1da177e4 1008 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 1009 } else
1da177e4 1010 skb_put(skb, rxlen);
4c13eb66 1011
1da177e4
LT		 1012 skb->protocol = eth_type_trans(skb, dev);
1013 netif_rx(skb);
2765df58
SH		 1014 dev->stats.rx_packets++;
1015 dev->stats.rx_bytes += rxlen;
1da177e4
LT		 1016 }
1017 } else {
1018 /* Reuse SKB buffer when the packet is error */
1019 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1020 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1021 }
1022 }
1023
1024 rxptr = rxptr->next_rx_desc;
1025 }
1026
1027 db->rx_ready_ptr = rxptr;
1028}
1029
1da177e4
LT		 1030/*
1031 * Set DM910X multicast address
1032 */
1033
1034static void dmfe_set_filter_mode(struct DEVICE * dev)
1035{
1036 struct dmfe_board_info *db = netdev_priv(dev);
1037 unsigned long flags;
1038
1039 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1040 spin_lock_irqsave(&db->lock, flags);
1041
1042 if (dev->flags & IFF_PROMISC) {
1043 DMFE_DBUG(0, "Enable PROM Mode", 0);
1044 db->cr6_data |= CR6_PM | CR6_PBF;
1045 update_cr6(db->cr6_data, db->ioaddr);
1046 spin_unlock_irqrestore(&db->lock, flags);
1047 return;
1048 }
1049
1050 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1051 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1052 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1053 db->cr6_data |= CR6_PAM;
1054 spin_unlock_irqrestore(&db->lock, flags);
1055 return;
1056 }
1057
1058 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1059 if (db->chip_id == PCI_DM9132_ID)
1060 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1061 else
1062 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1063 spin_unlock_irqrestore(&db->lock, flags);
1064}
1065
f1069046
ML		 1066/*
1067 * Ethtool interace
1068 */
1069
1070static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1da177e4
LT		 1071 struct ethtool_drvinfo *info)
1072{
1073 struct dmfe_board_info *np = netdev_priv(dev);
1074
1075 strcpy(info->driver, DRV_NAME);
1076 strcpy(info->version, DRV_VERSION);
1077 if (np->pdev)
1078 strcpy(info->bus_info, pci_name(np->pdev));
1079 else
1080 sprintf(info->bus_info, "EISA 0x%lx %d",
1081 dev->base_addr, dev->irq);
1082}
1083
f1069046
ML		 1084static int dmfe_ethtool_set_wol(struct net_device *dev,
1085 struct ethtool_wolinfo *wolinfo)
1086{
1087 struct dmfe_board_info *db = netdev_priv(dev);
1088
1089 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1090 WAKE_ARP | WAKE_MAGICSECURE))
1091 return -EOPNOTSUPP;
1092
1093 db->wol_mode = wolinfo->wolopts;
1094 return 0;
1095}
1096
1097static void dmfe_ethtool_get_wol(struct net_device *dev,
1098 struct ethtool_wolinfo *wolinfo)
1099{
1100 struct dmfe_board_info *db = netdev_priv(dev);
1101
1102 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1103 wolinfo->wolopts = db->wol_mode;
1104 return;
1105}
1106
1107
7282d491 1108static const struct ethtool_ops netdev_ethtool_ops = {
f1069046 1109 .get_drvinfo = dmfe_ethtool_get_drvinfo,
cfa51b9d 1110 .get_link = ethtool_op_get_link,
f1069046
ML		 1111 .set_wol = dmfe_ethtool_set_wol,
1112 .get_wol = dmfe_ethtool_get_wol,
1da177e4
LT		 1113};
1114
1115/*
1116 * A periodic timer routine
1117 * Dynamic media sense, allocate Rx buffer...
1118 */
1119
1120static void dmfe_timer(unsigned long data)
1121{
1122 u32 tmp_cr8;
1123 unsigned char tmp_cr12;
1124 struct DEVICE *dev = (struct DEVICE *) data;
1125 struct dmfe_board_info *db = netdev_priv(dev);
1126 unsigned long flags;
1127
cfa51b9d
ML		 1128 int link_ok, link_ok_phy;
1129
1da177e4
LT		 1130 DMFE_DBUG(0, "dmfe_timer()", 0);
1131 spin_lock_irqsave(&db->lock, flags);
1132
1133 /* Media mode process when Link OK before enter this route */
1134 if (db->first_in_callback == 0) {
1135 db->first_in_callback = 1;
1136 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1137 db->cr6_data &= ~0x40000;
1138 update_cr6(db->cr6_data, db->ioaddr);
f67ba792
ML		 1139 phy_write(db->ioaddr,
1140 db->phy_addr, 0, 0x1000, db->chip_id);
1da177e4
LT		 1141 db->cr6_data |= 0x40000;
1142 update_cr6(db->cr6_data, db->ioaddr);
1143 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1144 add_timer(&db->timer);
1145 spin_unlock_irqrestore(&db->lock, flags);
1146 return;
1147 }
1148 }
1149
1150
1151 /* Operating Mode Check */
1152 if ( (db->dm910x_chk_mode & 0x1) &&
2765df58 1153 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1da177e4
LT		 1154 db->dm910x_chk_mode = 0x4;
1155
1156 /* Dynamic reset DM910X : system error or transmit time-out */
1157 tmp_cr8 = inl(db->ioaddr + DCR8);
1158 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1159 db->reset_cr8++;
1160 db->wait_reset = 1;
1161 }
1162 db->interval_rx_cnt = 0;
1163
1164 /* TX polling kick monitor */
1165 if ( db->tx_packet_cnt &&
1166 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1167 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1168
1169 /* TX Timeout */
1170 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1171 db->reset_TXtimeout++;
1172 db->wait_reset = 1;
1173 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1174 dev->name);
1175 }
1176 }
1177
1178 if (db->wait_reset) {
1179 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1180 db->reset_count++;
1181 dmfe_dynamic_reset(dev);
1182 db->first_in_callback = 0;
1183 db->timer.expires = DMFE_TIMER_WUT;
1184 add_timer(&db->timer);
1185 spin_unlock_irqrestore(&db->lock, flags);
1186 return;
1187 }
1188
1189 /* Link status check, Dynamic media type change */
1190 if (db->chip_id == PCI_DM9132_ID)
1191 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1192 else
1193 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1194
1195 if ( ((db->chip_id == PCI_DM9102_ID) &&
44c10138 1196 (db->chip_revision == 0x30)) ||
1da177e4 1197 ((db->chip_id == PCI_DM9132_ID) &&
44c10138 1198 (db->chip_revision == 0x10)) ) {
1da177e4
LT		 1199 /* DM9102A Chip */
1200 if (tmp_cr12 & 2)
cfa51b9d 1201 link_ok = 0;
1da177e4 1202 else
cfa51b9d 1203 link_ok = 1;
1da177e4 1204 }
cfa51b9d
ML		 1205 else
1206 /*0x43 is used instead of 0x3 because bit 6 should represent
1207 link status of external PHY */
1208 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1209
1210
1211 /* If chip reports that link is failed it could be because external
1212 PHY link status pin is not conected correctly to chip
1213 To be sure ask PHY too.
1214 */
1215
1216 /* need a dummy read because of PHY's register latch*/
1217 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1218 link_ok_phy = (phy_read (db->ioaddr,
1219 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1da177e4 1220
cfa51b9d
ML		 1221 if (link_ok_phy != link_ok) {
1222 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1223 link_ok = link_ok | link_ok_phy;
1224 }
1225
1226 if ( !link_ok && netif_carrier_ok(dev)) {
1da177e4
LT		 1227 /* Link Failed */
1228 DMFE_DBUG(0, "Link Failed", tmp_cr12);
cfa51b9d 1229 netif_carrier_off(dev);
1da177e4
LT		 1230
1231 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1232 /* AUTO or force 1M Homerun/Longrun don't need */
1233 if ( !(db->media_mode & 0x38) )
f67ba792
ML		 1234 phy_write(db->ioaddr, db->phy_addr,
1235 0, 0x1000, db->chip_id);
1da177e4
LT		 1236
1237 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1238 if (db->media_mode & DMFE_AUTO) {
1239 /* 10/100M link failed, used 1M Home-Net */
1240 db->cr6_data|=0x00040000; /* bit18=1, MII */
1241 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1242 update_cr6(db->cr6_data, db->ioaddr);
1243 }
cfa51b9d
ML		 1244 } else if (!netif_carrier_ok(dev)) {
1245
1246 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1247
1248 /* Auto Sense Speed */
1249 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1250 netif_carrier_on(dev);
1251 SHOW_MEDIA_TYPE(db->op_mode);
1da177e4
LT		 1252 }
1253
cfa51b9d
ML		 1254 dmfe_process_mode(db);
1255 }
1256
1da177e4
LT		 1257 /* HPNA remote command check */
1258 if (db->HPNA_command & 0xf00) {
1259 db->HPNA_timer--;
1260 if (!db->HPNA_timer)
1261 dmfe_HPNA_remote_cmd_chk(db);
1262 }
1263
1264 /* Timer active again */
1265 db->timer.expires = DMFE_TIMER_WUT;
1266 add_timer(&db->timer);
1267 spin_unlock_irqrestore(&db->lock, flags);
1268}
1269
1270
1271/*
1272 * Dynamic reset the DM910X board
1273 * Stop DM910X board
1274 * Free Tx/Rx allocated memory
1275 * Reset DM910X board
1276 * Re-initilize DM910X board
1277 */
1278
1279static void dmfe_dynamic_reset(struct DEVICE *dev)
1280{
1281 struct dmfe_board_info *db = netdev_priv(dev);
1282
1283 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1284
1285 /* Sopt MAC controller */
1286 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1287 update_cr6(db->cr6_data, dev->base_addr);
1288 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1289 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1290
1291 /* Disable upper layer interface */
1292 netif_stop_queue(dev);
1293
1294 /* Free Rx Allocate buffer */
1295 dmfe_free_rxbuffer(db);
1296
1297 /* system variable init */
1298 db->tx_packet_cnt = 0;
1299 db->tx_queue_cnt = 0;
1300 db->rx_avail_cnt = 0;
cfa51b9d 1301 netif_carrier_off(dev);
1da177e4
LT		 1302 db->wait_reset = 0;
1303
1304 /* Re-initilize DM910X board */
1305 dmfe_init_dm910x(dev);
1306
1307 /* Restart upper layer interface */
1308 netif_wake_queue(dev);
1309}
1310
1311
1312/*
1313 * free all allocated rx buffer
1314 */
1315
1316static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1317{
1318 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1319
1320 /* free allocated rx buffer */
1321 while (db->rx_avail_cnt) {
1322 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1323 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1324 db->rx_avail_cnt--;
1325 }
1326}
1327
1328
1329/*
1330 * Reuse the SK buffer
1331 */
1332
1333static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1334{
1335 struct rx_desc *rxptr = db->rx_insert_ptr;
1336
1337 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1338 rxptr->rx_skb_ptr = skb;
f67ba792
ML		 1339 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1340 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1341 wmb();
1342 rxptr->rdes0 = cpu_to_le32(0x80000000);
1343 db->rx_avail_cnt++;
1344 db->rx_insert_ptr = rxptr->next_rx_desc;
1345 } else
1346 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1347}
1348
1349
1350/*
1351 * Initialize transmit/Receive descriptor
1352 * Using Chain structure, and allocate Tx/Rx buffer
1353 */
1354
1355static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1356{
1357 struct tx_desc *tmp_tx;
1358 struct rx_desc *tmp_rx;
1359 unsigned char *tmp_buf;
1360 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1361 dma_addr_t tmp_buf_dma;
1362 int i;
1363
1364 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1365
1366 /* tx descriptor start pointer */
1367 db->tx_insert_ptr = db->first_tx_desc;
1368 db->tx_remove_ptr = db->first_tx_desc;
1369 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1370
1371 /* rx descriptor start pointer */
f67ba792
ML		 1372 db->first_rx_desc = (void *)db->first_tx_desc +
1373 sizeof(struct tx_desc) * TX_DESC_CNT;
1374
1375 db->first_rx_desc_dma = db->first_tx_desc_dma +
1376 sizeof(struct tx_desc) * TX_DESC_CNT;
1da177e4
LT		 1377 db->rx_insert_ptr = db->first_rx_desc;
1378 db->rx_ready_ptr = db->first_rx_desc;
1379 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1380
1381 /* Init Transmit chain */
1382 tmp_buf = db->buf_pool_start;
1383 tmp_buf_dma = db->buf_pool_dma_start;
1384 tmp_tx_dma = db->first_tx_desc_dma;
1385 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1386 tmp_tx->tx_buf_ptr = tmp_buf;
1387 tmp_tx->tdes0 = cpu_to_le32(0);
1388 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1389 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1390 tmp_tx_dma += sizeof(struct tx_desc);
1391 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1392 tmp_tx->next_tx_desc = tmp_tx + 1;
1393 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1394 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1395 }
1396 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1397 tmp_tx->next_tx_desc = db->first_tx_desc;
1398
1399 /* Init Receive descriptor chain */
1400 tmp_rx_dma=db->first_rx_desc_dma;
1401 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1402 tmp_rx->rdes0 = cpu_to_le32(0);
1403 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1404 tmp_rx_dma += sizeof(struct rx_desc);
1405 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1406 tmp_rx->next_rx_desc = tmp_rx + 1;
1407 }
1408 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1409 tmp_rx->next_rx_desc = db->first_rx_desc;
1410
1411 /* pre-allocate Rx buffer */
1412 allocate_rx_buffer(db);
1413}
1414
1415
1416/*
1417 * Update CR6 value
1418 * Firstly stop DM910X , then written value and start
1419 */
1420
1421static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1422{
1423 u32 cr6_tmp;
1424
1425 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1426 outl(cr6_tmp, ioaddr + DCR6);
1427 udelay(5);
1428 outl(cr6_data, ioaddr + DCR6);
1429 udelay(5);
1430}
1431
1432
1433/*
1434 * Send a setup frame for DM9132
1435 * This setup frame initilize DM910X address filter mode
1436*/
1437
1438static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1439{
1440 struct dev_mc_list *mcptr;
1441 u16 * addrptr;
1442 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1443 u32 hash_val;
1444 u16 i, hash_table[4];
1445
1446 DMFE_DBUG(0, "dm9132_id_table()", 0);
1447
1448 /* Node address */
1449 addrptr = (u16 *) dev->dev_addr;
1450 outw(addrptr[0], ioaddr);
1451 ioaddr += 4;
1452 outw(addrptr[1], ioaddr);
1453 ioaddr += 4;
1454 outw(addrptr[2], ioaddr);
1455 ioaddr += 4;
1456
1457 /* Clear Hash Table */
1458 for (i = 0; i < 4; i++)
1459 hash_table[i] = 0x0;
1460
1461 /* broadcast address */
1462 hash_table[3] = 0x8000;
1463
1464 /* the multicast address in Hash Table : 64 bits */
1465 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1466 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1467 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1468 }
1469
1470 /* Write the hash table to MAC MD table */
1471 for (i = 0; i < 4; i++, ioaddr += 4)
1472 outw(hash_table[i], ioaddr);
1473}
1474
1475
1476/*
1477 * Send a setup frame for DM9102/DM9102A
1478 * This setup frame initilize DM910X address filter mode
1479 */
1480
1481static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1482{
1483 struct dmfe_board_info *db = netdev_priv(dev);
1484 struct dev_mc_list *mcptr;
1485 struct tx_desc *txptr;
1486 u16 * addrptr;
1487 u32 * suptr;
1488 int i;
1489
1490 DMFE_DBUG(0, "send_filter_frame()", 0);
1491
1492 txptr = db->tx_insert_ptr;
1493 suptr = (u32 *) txptr->tx_buf_ptr;
1494
1495 /* Node address */
1496 addrptr = (u16 *) dev->dev_addr;
1497 *suptr++ = addrptr[0];
1498 *suptr++ = addrptr[1];
1499 *suptr++ = addrptr[2];
1500
1501 /* broadcast address */
1502 *suptr++ = 0xffff;
1503 *suptr++ = 0xffff;
1504 *suptr++ = 0xffff;
1505
1506 /* fit the multicast address */
1507 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1508 addrptr = (u16 *) mcptr->dmi_addr;
1509 *suptr++ = addrptr[0];
1510 *suptr++ = addrptr[1];
1511 *suptr++ = addrptr[2];
1512 }
1513
1514 for (; i<14; i++) {
1515 *suptr++ = 0xffff;
1516 *suptr++ = 0xffff;
1517 *suptr++ = 0xffff;
1518 }
1519
1520 /* prepare the setup frame */
1521 db->tx_insert_ptr = txptr->next_tx_desc;
1522 txptr->tdes1 = cpu_to_le32(0x890000c0);
1523
1524 /* Resource Check and Send the setup packet */
1525 if (!db->tx_packet_cnt) {
1526 /* Resource Empty */
1527 db->tx_packet_cnt++;
1528 txptr->tdes0 = cpu_to_le32(0x80000000);
1529 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1530 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1531 update_cr6(db->cr6_data, dev->base_addr);
1532 dev->trans_start = jiffies;
1533 } else
1534 db->tx_queue_cnt++; /* Put in TX queue */
1535}
1536
1537
1538/*
1539 * Allocate rx buffer,
1540 * As possible as allocate maxiumn Rx buffer
1541 */
1542
1543static void allocate_rx_buffer(struct dmfe_board_info *db)
1544{
1545 struct rx_desc *rxptr;
1546 struct sk_buff *skb;
1547
1548 rxptr = db->rx_insert_ptr;
1549
1550 while(db->rx_avail_cnt < RX_DESC_CNT) {
1551 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1552 break;
1553 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
f67ba792
ML		 1554 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1555 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1556 wmb();
1557 rxptr->rdes0 = cpu_to_le32(0x80000000);
1558 rxptr = rxptr->next_rx_desc;
1559 db->rx_avail_cnt++;
1560 }
1561
1562 db->rx_insert_ptr = rxptr;
1563}
1564
1565
1566/*
1567 * Read one word data from the serial ROM
1568 */
1569
1570static u16 read_srom_word(long ioaddr, int offset)
1571{
1572 int i;
1573 u16 srom_data = 0;
1574 long cr9_ioaddr = ioaddr + DCR9;
1575
1576 outl(CR9_SROM_READ, cr9_ioaddr);
1577 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1578
1579 /* Send the Read Command 110b */
1580 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1581 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1582 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1583
1584 /* Send the offset */
1585 for (i = 5; i >= 0; i--) {
1586 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1587 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1588 }
1589
1590 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1591
1592 for (i = 16; i > 0; i--) {
1593 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1594 udelay(5);
f67ba792
ML		 1595 srom_data = (srom_data << 1) |
1596 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1da177e4
LT		 1597 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1598 udelay(5);
1599 }
1600
1601 outl(CR9_SROM_READ, cr9_ioaddr);
1602 return srom_data;
1603}
1604
1605
1606/*
1607 * Auto sense the media mode
1608 */
1609
1610static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1611{
1612 u8 ErrFlag = 0;
1613 u16 phy_mode;
1614
1615 /* CR6 bit18=0, select 10/100M */
1616 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1617
1618 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1619 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1620
1621 if ( (phy_mode & 0x24) == 0x24 ) {
1622 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
f67ba792
ML		 1623 phy_mode = phy_read(db->ioaddr,
1624 db->phy_addr, 7, db->chip_id) & 0xf000;
1da177e4 1625 else /* DM9102/DM9102A */
f67ba792
ML		 1626 phy_mode = phy_read(db->ioaddr,
1627 db->phy_addr, 17, db->chip_id) & 0xf000;
1da177e4
LT		 1628 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1629 switch (phy_mode) {
1630 case 0x1000: db->op_mode = DMFE_10MHF; break;
1631 case 0x2000: db->op_mode = DMFE_10MFD; break;
1632 case 0x4000: db->op_mode = DMFE_100MHF; break;
1633 case 0x8000: db->op_mode = DMFE_100MFD; break;
1634 default: db->op_mode = DMFE_10MHF;
1635 ErrFlag = 1;
1636 break;
1637 }
1638 } else {
1639 db->op_mode = DMFE_10MHF;
1640 DMFE_DBUG(0, "Link Failed :", phy_mode);
1641 ErrFlag = 1;
1642 }
1643
1644 return ErrFlag;
1645}
1646
1647
1648/*
1649 * Set 10/100 phyxcer capability
1650 * AUTO mode : phyxcer register4 is NIC capability
1651 * Force mode: phyxcer register4 is the force media
1652 */
1653
1654static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1655{
1656 u16 phy_reg;
1657
1658 /* Select 10/100M phyxcer */
1659 db->cr6_data &= ~0x40000;
1660 update_cr6(db->cr6_data, db->ioaddr);
1661
1662 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1663 if (db->chip_id == PCI_DM9009_ID) {
f67ba792
ML		 1664 phy_reg = phy_read(db->ioaddr,
1665 db->phy_addr, 18, db->chip_id) & ~0x1000;
1666
1667 phy_write(db->ioaddr,
1668 db->phy_addr, 18, phy_reg, db->chip_id);
1da177e4
LT		 1669 }
1670
1671 /* Phyxcer capability setting */
1672 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1673
1674 if (db->media_mode & DMFE_AUTO) {
1675 /* AUTO Mode */
1676 phy_reg |= db->PHY_reg4;
1677 } else {
1678 /* Force Mode */
1679 switch(db->media_mode) {
1680 case DMFE_10MHF: phy_reg |= 0x20; break;
1681 case DMFE_10MFD: phy_reg |= 0x40; break;
1682 case DMFE_100MHF: phy_reg |= 0x80; break;
1683 case DMFE_100MFD: phy_reg |= 0x100; break;
1684 }
1685 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1686 }
1687
1688 /* Write new capability to Phyxcer Reg4 */
1689 if ( !(phy_reg & 0x01e0)) {
1690 phy_reg|=db->PHY_reg4;
1691 db->media_mode|=DMFE_AUTO;
1692 }
1693 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1694
1695 /* Restart Auto-Negotiation */
1696 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1697 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1698 if ( !db->chip_type )
1699 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1700}
1701
1702
1703/*
1704 * Process op-mode
1705 * AUTO mode : PHY controller in Auto-negotiation Mode
1706 * Force mode: PHY controller in force mode with HUB
1707 * N-way force capability with SWITCH
1708 */
1709
1710static void dmfe_process_mode(struct dmfe_board_info *db)
1711{
1712 u16 phy_reg;
1713
1714 /* Full Duplex Mode Check */
1715 if (db->op_mode & 0x4)
1716 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1717 else
1718 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1719
1720 /* Transciver Selection */
1721 if (db->op_mode & 0x10) /* 1M HomePNA */
1722 db->cr6_data |= 0x40000;/* External MII select */
1723 else
1724 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1725
1726 update_cr6(db->cr6_data, db->ioaddr);
1727
1728 /* 10/100M phyxcer force mode need */
1729 if ( !(db->media_mode & 0x18)) {
1730 /* Forece Mode */
1731 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1732 if ( !(phy_reg & 0x1) ) {
1733 /* parter without N-Way capability */
1734 phy_reg = 0x0;
1735 switch(db->op_mode) {
1736 case DMFE_10MHF: phy_reg = 0x0; break;
1737 case DMFE_10MFD: phy_reg = 0x100; break;
1738 case DMFE_100MHF: phy_reg = 0x2000; break;
1739 case DMFE_100MFD: phy_reg = 0x2100; break;
1740 }
f67ba792
ML		 1741 phy_write(db->ioaddr,
1742 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1743 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1744 mdelay(20);
f67ba792
ML		 1745 phy_write(db->ioaddr,
1746 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1747 }
1748 }
1749}
1750
1751
1752/*
1753 * Write a word to Phy register
1754 */
1755
f67ba792
ML		 1756static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1757 u16 phy_data, u32 chip_id)
1da177e4
LT		 1758{
1759 u16 i;
1760 unsigned long ioaddr;
1761
1762 if (chip_id == PCI_DM9132_ID) {
1763 ioaddr = iobase + 0x80 + offset * 4;
1764 outw(phy_data, ioaddr);
1765 } else {
1766 /* DM9102/DM9102A Chip */
1767 ioaddr = iobase + DCR9;
1768
1769 /* Send 33 synchronization clock to Phy controller */
1770 for (i = 0; i < 35; i++)
1771 phy_write_1bit(ioaddr, PHY_DATA_1);
1772
1773 /* Send start command(01) to Phy */
1774 phy_write_1bit(ioaddr, PHY_DATA_0);
1775 phy_write_1bit(ioaddr, PHY_DATA_1);
1776
1777 /* Send write command(01) to Phy */
1778 phy_write_1bit(ioaddr, PHY_DATA_0);
1779 phy_write_1bit(ioaddr, PHY_DATA_1);
1780
1781 /* Send Phy address */
1782 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1783 phy_write_1bit(ioaddr,
1784 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1785
1786 /* Send register address */
1787 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1788 phy_write_1bit(ioaddr,
1789 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1790
1791 /* written trasnition */
1792 phy_write_1bit(ioaddr, PHY_DATA_1);
1793 phy_write_1bit(ioaddr, PHY_DATA_0);
1794
1795 /* Write a word data to PHY controller */
1796 for ( i = 0x8000; i > 0; i >>= 1)
f67ba792
ML		 1797 phy_write_1bit(ioaddr,
1798 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1799 }
1800}
1801
1802
1803/*
1804 * Read a word data from phy register
1805 */
1806
1807static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1808{
1809 int i;
1810 u16 phy_data;
1811 unsigned long ioaddr;
1812
1813 if (chip_id == PCI_DM9132_ID) {
1814 /* DM9132 Chip */
1815 ioaddr = iobase + 0x80 + offset * 4;
1816 phy_data = inw(ioaddr);
1817 } else {
1818 /* DM9102/DM9102A Chip */
1819 ioaddr = iobase + DCR9;
1820
1821 /* Send 33 synchronization clock to Phy controller */
1822 for (i = 0; i < 35; i++)
1823 phy_write_1bit(ioaddr, PHY_DATA_1);
1824
1825 /* Send start command(01) to Phy */
1826 phy_write_1bit(ioaddr, PHY_DATA_0);
1827 phy_write_1bit(ioaddr, PHY_DATA_1);
1828
1829 /* Send read command(10) to Phy */
1830 phy_write_1bit(ioaddr, PHY_DATA_1);
1831 phy_write_1bit(ioaddr, PHY_DATA_0);
1832
1833 /* Send Phy address */
1834 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1835 phy_write_1bit(ioaddr,
1836 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1837
1838 /* Send register address */
1839 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1840 phy_write_1bit(ioaddr,
1841 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1842
1843 /* Skip transition state */
1844 phy_read_1bit(ioaddr);
1845
1846 /* read 16bit data */
1847 for (phy_data = 0, i = 0; i < 16; i++) {
1848 phy_data <<= 1;
1849 phy_data |= phy_read_1bit(ioaddr);
1850 }
1851 }
1852
1853 return phy_data;
1854}
1855
1856
1857/*
1858 * Write one bit data to Phy Controller
1859 */
1860
1861static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1862{
1863 outl(phy_data, ioaddr); /* MII Clock Low */
1864 udelay(1);
1865 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1866 udelay(1);
1867 outl(phy_data, ioaddr); /* MII Clock Low */
1868 udelay(1);
1869}
1870
1871
1872/*
1873 * Read one bit phy data from PHY controller
1874 */
1875
1876static u16 phy_read_1bit(unsigned long ioaddr)
1877{
1878 u16 phy_data;
1879
1880 outl(0x50000, ioaddr);
1881 udelay(1);
1882 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1883 outl(0x40000, ioaddr);
1884 udelay(1);
1885
1886 return phy_data;
1887}
1888
1889
1890/*
1891 * Parser SROM and media mode
1892 */
1893
1894static void dmfe_parse_srom(struct dmfe_board_info * db)
1895{
1896 char * srom = db->srom;
1897 int dmfe_mode, tmp_reg;
1898
1899 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1900
1901 /* Init CR15 */
1902 db->cr15_data = CR15_DEFAULT;
1903
1904 /* Check SROM Version */
1905 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1906 /* SROM V4.01 */
1907 /* Get NIC support media mode */
4c93566e 1908 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1da177e4
LT		 1909 db->PHY_reg4 = 0;
1910 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1911 switch( db->NIC_capability & tmp_reg ) {
1912 case 0x1: db->PHY_reg4 |= 0x0020; break;
1913 case 0x2: db->PHY_reg4 |= 0x0040; break;
1914 case 0x4: db->PHY_reg4 |= 0x0080; break;
1915 case 0x8: db->PHY_reg4 |= 0x0100; break;
1916 }
1917 }
1918
1919 /* Media Mode Force or not check */
4c93566e
DM		 1920 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1921 le32_to_cpup((__le32 *) (srom + 36)));
1da177e4
LT		 1922 switch(dmfe_mode) {
1923 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1924 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1925 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1926 case 0x100:
1927 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1928 }
1929
1930 /* Special Function setting */
1931 /* VLAN function */
1932 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1933 db->cr15_data |= 0x40;
1934
1935 /* Flow Control */
1936 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1937 db->cr15_data |= 0x400;
1938
1939 /* TX pause packet */
1940 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1941 db->cr15_data |= 0x9800;
1942 }
1943
1944 /* Parse HPNA parameter */
1945 db->HPNA_command = 1;
1946
1947 /* Accept remote command or not */
1948 if (HPNA_rx_cmd == 0)
1949 db->HPNA_command |= 0x8000;
1950
1951 /* Issue remote command & operation mode */
1952 if (HPNA_tx_cmd == 1)
1953 switch(HPNA_mode) { /* Issue Remote Command */
1954 case 0: db->HPNA_command |= 0x0904; break;
1955 case 1: db->HPNA_command |= 0x0a00; break;
1956 case 2: db->HPNA_command |= 0x0506; break;
1957 case 3: db->HPNA_command |= 0x0602; break;
1958 }
1959 else
1960 switch(HPNA_mode) { /* Don't Issue */
1961 case 0: db->HPNA_command |= 0x0004; break;
1962 case 1: db->HPNA_command |= 0x0000; break;
1963 case 2: db->HPNA_command |= 0x0006; break;
1964 case 3: db->HPNA_command |= 0x0002; break;
1965 }
1966
1967 /* Check DM9801 or DM9802 present or not */
1968 db->HPNA_present = 0;
1969 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1970 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1971 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1972 /* DM9801 or DM9802 present */
1973 db->HPNA_timer = 8;
1974 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1975 /* DM9801 HomeRun */
1976 db->HPNA_present = 1;
1977 dmfe_program_DM9801(db, tmp_reg);
1978 } else {
1979 /* DM9802 LongRun */
1980 db->HPNA_present = 2;
1981 dmfe_program_DM9802(db);
1982 }
1983 }
1984
1985}
1986
1987
1988/*
1989 * Init HomeRun DM9801
1990 */
1991
1992static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1993{
1994 uint reg17, reg25;
1995
1996 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
1997 switch(HPNA_rev) {
1998 case 0xb900: /* DM9801 E3 */
1999 db->HPNA_command |= 0x1000;
2000 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2001 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2002 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2003 break;
2004 case 0xb901: /* DM9801 E4 */
2005 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2006 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2007 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2008 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2009 break;
2010 case 0xb902: /* DM9801 E5 */
2011 case 0xb903: /* DM9801 E6 */
2012 default:
2013 db->HPNA_command |= 0x1000;
2014 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2015 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2016 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2017 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2018 break;
2019 }
2020 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2021 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2022 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2023}
2024
2025
2026/*
2027 * Init HomeRun DM9802
2028 */
2029
2030static void dmfe_program_DM9802(struct dmfe_board_info * db)
2031{
2032 uint phy_reg;
2033
2034 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2035 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2036 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2037 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2038 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2039}
2040
2041
2042/*
2043 * Check remote HPNA power and speed status. If not correct,
2044 * issue command again.
2045*/
2046
2047static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2048{
2049 uint phy_reg;
2050
2051 /* Got remote device status */
2052 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2053 switch(phy_reg) {
2054 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2055 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2056 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2057 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2058 }
2059
2060 /* Check remote device status match our setting ot not */
2061 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
f67ba792
ML		 2062 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2063 db->chip_id);
1da177e4
LT		 2064 db->HPNA_timer=8;
2065 } else
2066 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2067}
2068
2069
2070
a3aa1884 2071static DEFINE_PCI_DEVICE_TABLE(dmfe_pci_tbl) = {
1da177e4
LT		 2072 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2073 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2074 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2075 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2076 { 0, }
2077};
2078MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2079
2080
bc8a8387
ML		 2081#ifdef CONFIG_PM
2082static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2083{
2084 struct net_device *dev = pci_get_drvdata(pci_dev);
2085 struct dmfe_board_info *db = netdev_priv(dev);
f1069046 2086 u32 tmp;
bc8a8387
ML		 2087
2088 /* Disable upper layer interface */
2089 netif_device_detach(dev);
2090
2091 /* Disable Tx/Rx */
2092 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2093 update_cr6(db->cr6_data, dev->base_addr);
2094
2095 /* Disable Interrupt */
2096 outl(0, dev->base_addr + DCR7);
2097 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2098
2099 /* Fre RX buffers */
2100 dmfe_free_rxbuffer(db);
2101
f1069046
ML		 2102 /* Enable WOL */
2103 pci_read_config_dword(pci_dev, 0x40, &tmp);
2104 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2105
2106 if (db->wol_mode & WAKE_PHY)
2107 tmp |= DMFE_WOL_LINKCHANGE;
2108 if (db->wol_mode & WAKE_MAGIC)
2109 tmp |= DMFE_WOL_MAGICPACKET;
2110
2111 pci_write_config_dword(pci_dev, 0x40, tmp);
2112
2113 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2114 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2115
bc8a8387 2116 /* Power down device*/
bc8a8387 2117 pci_save_state(pci_dev);
a31e23e1 2118 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
bc8a8387
ML		 2119
2120 return 0;
2121}
2122
2123static int dmfe_resume(struct pci_dev *pci_dev)
2124{
2125 struct net_device *dev = pci_get_drvdata(pci_dev);
f1069046 2126 u32 tmp;
bc8a8387 2127
bc8a8387 2128 pci_set_power_state(pci_dev, PCI_D0);
65809b51 2129 pci_restore_state(pci_dev);
bc8a8387
ML		 2130
2131 /* Re-initilize DM910X board */
2132 dmfe_init_dm910x(dev);
2133
f1069046
ML		 2134 /* Disable WOL */
2135 pci_read_config_dword(pci_dev, 0x40, &tmp);
2136
2137 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2138 pci_write_config_dword(pci_dev, 0x40, tmp);
2139
2140 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2141 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2142
bc8a8387
ML		 2143 /* Restart upper layer interface */
2144 netif_device_attach(dev);
2145
2146 return 0;
2147}
2148#else
2149#define dmfe_suspend NULL
2150#define dmfe_resume NULL
2151#endif
2152
1da177e4
LT		 2153static struct pci_driver dmfe_driver = {
2154 .name = "dmfe",
2155 .id_table = dmfe_pci_tbl,
2156 .probe = dmfe_init_one,
2157 .remove = __devexit_p(dmfe_remove_one),
bc8a8387
ML		 2158 .suspend = dmfe_suspend,
2159 .resume = dmfe_resume
1da177e4
LT		 2160};
2161
2162MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2163MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2164MODULE_LICENSE("GPL");
2165MODULE_VERSION(DRV_VERSION);
2166
2167module_param(debug, int, 0);
2168module_param(mode, byte, 0);
2169module_param(cr6set, int, 0);
2170module_param(chkmode, byte, 0);
2171module_param(HPNA_mode, byte, 0);
2172module_param(HPNA_rx_cmd, byte, 0);
2173module_param(HPNA_tx_cmd, byte, 0);
2174module_param(HPNA_NoiseFloor, byte, 0);
2175module_param(SF_mode, byte, 0);
2176MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
f67ba792
ML		 2177MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2178 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2179
2180MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2181 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
1da177e4
LT		 2182
2183/* Description:
2184 * when user used insmod to add module, system invoked init_module()
2185 * to initilize and register.
2186 */
2187
2188static int __init dmfe_init_module(void)
2189{
2190 int rc;
2191
2192 printk(version);
2193 printed_version = 1;
2194
2195 DMFE_DBUG(0, "init_module() ", debug);
2196
2197 if (debug)
2198 dmfe_debug = debug; /* set debug flag */
2199 if (cr6set)
2200 dmfe_cr6_user_set = cr6set;
2201
2202 switch(mode) {
2203 case DMFE_10MHF:
2204 case DMFE_100MHF:
2205 case DMFE_10MFD:
2206 case DMFE_100MFD:
2207 case DMFE_1M_HPNA:
2208 dmfe_media_mode = mode;
2209 break;
2210 default:dmfe_media_mode = DMFE_AUTO;
2211 break;
2212 }
2213
2214 if (HPNA_mode > 4)
2215 HPNA_mode = 0; /* Default: LP/HS */
2216 if (HPNA_rx_cmd > 1)
2217 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2218 if (HPNA_tx_cmd > 1)
2219 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2220 if (HPNA_NoiseFloor > 15)
2221 HPNA_NoiseFloor = 0;
2222
29917620 2223 rc = pci_register_driver(&dmfe_driver);
1da177e4
LT		 2224 if (rc < 0)
2225 return rc;
2226
2227 return 0;
2228}
2229
2230
2231/*
2232 * Description:
2233 * when user used rmmod to delete module, system invoked clean_module()
2234 * to un-register all registered services.
2235 */
2236
2237static void __exit dmfe_cleanup_module(void)
2238{
2239 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2240 pci_unregister_driver(&dmfe_driver);
2241}
2242
2243module_init(dmfe_init_module);
2244module_exit(dmfe_cleanup_module);
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