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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / tulip / dmfe.c
CommitLineData
1da177e4
LT		 1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
113aa838 26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
1da177e4
LT		 27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
113aa838 52 Alan Cox <alan@lxorguk.ukuu.org.uk>
f3b197ac 53 Added new PCI identifiers provided by Clear Zhang at ALi
1da177e4
LT		 54 for their 1563 ethernet device.
55
56 TODO
57
1da177e4
LT		 58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62*/
63
dde7c8ef
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65
1da177e4
LT		 66#define DRV_NAME "dmfe"
67#define DRV_VERSION "1.36.4"
68#define DRV_RELDATE "2002-01-17"
69
70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/string.h>
73#include <linux/timer.h>
74#include <linux/ptrace.h>
75#include <linux/errno.h>
76#include <linux/ioport.h>
1da177e4
LT		 77#include <linux/interrupt.h>
78#include <linux/pci.h>
cb199d42 79#include <linux/dma-mapping.h>
1da177e4
LT		 80#include <linux/init.h>
81#include <linux/netdevice.h>
82#include <linux/etherdevice.h>
83#include <linux/ethtool.h>
84#include <linux/skbuff.h>
85#include <linux/delay.h>
86#include <linux/spinlock.h>
87#include <linux/crc32.h>
88#include <linux/bitops.h>
89
90#include <asm/processor.h>
91#include <asm/io.h>
92#include <asm/dma.h>
93#include <asm/uaccess.h>
94#include <asm/irq.h>
95
4d907069
BH		 96#ifdef CONFIG_TULIP_DM910X
97#include <linux/of.h>
98#endif
99
1da177e4
LT		 100
101/* Board/System/Debug information/definition ---------------- */
102#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
103#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
104#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
105#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
106
107#define DM9102_IO_SIZE 0x80
108#define DM9102A_IO_SIZE 0x100
109#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
110#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
111#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
112#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
113#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
114#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
115#define TX_BUF_ALLOC 0x600
116#define RX_ALLOC_SIZE 0x620
117#define DM910X_RESET 1
118#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
119#define CR6_DEFAULT 0x00080000 /* HD */
120#define CR7_DEFAULT 0x180c1
121#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
122#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
123#define MAX_PACKET_SIZE 1514
124#define DMFE_MAX_MULTICAST 14
125#define RX_COPY_SIZE 100
126#define MAX_CHECK_PACKET 0x8000
127#define DM9801_NOISE_FLOOR 8
128#define DM9802_NOISE_FLOOR 5
129
f1069046
ML		 130#define DMFE_WOL_LINKCHANGE 0x20000000
131#define DMFE_WOL_SAMPLEPACKET 0x10000000
132#define DMFE_WOL_MAGICPACKET 0x08000000
133
134
1da177e4
LT		 135#define DMFE_10MHF 0
136#define DMFE_100MHF 1
137#define DMFE_10MFD 4
138#define DMFE_100MFD 5
139#define DMFE_AUTO 8
140#define DMFE_1M_HPNA 0x10
141
142#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
143#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
144#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
145#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
146#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
147#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
148
149#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
150#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
151#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
152
dde7c8ef
JP		 153#define DMFE_DBUG(dbug_now, msg, value) \
154 do { \
155 if (dmfe_debug || (dbug_now)) \
156 pr_err("%s %lx\n", \
157 (msg), (long) (value)); \
f67ba792 158 } while (0)
1da177e4 159
dde7c8ef
JP		 160#define SHOW_MEDIA_TYPE(mode) \
161 pr_info("Change Speed to %sMhz %s duplex\n" , \
162 (mode & 1) ? "100":"10", \
163 (mode & 4) ? "full":"half");
1da177e4
LT		 164
165
166/* CR9 definition: SROM/MII */
167#define CR9_SROM_READ 0x4800
168#define CR9_SRCS 0x1
169#define CR9_SRCLK 0x2
170#define CR9_CRDOUT 0x8
171#define SROM_DATA_0 0x0
172#define SROM_DATA_1 0x4
173#define PHY_DATA_1 0x20000
174#define PHY_DATA_0 0x00000
175#define MDCLKH 0x10000
176
177#define PHY_POWER_DOWN 0x800
178
179#define SROM_V41_CODE 0x14
180
f67ba792
ML		 181#define SROM_CLK_WRITE(data, ioaddr) \
182 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
183 udelay(5); \
184 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
185 udelay(5); \
186 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
187 udelay(5);
188
189#define __CHK_IO_SIZE(pci_id, dev_rev) \
44c10138 190 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
f67ba792 191 DM9102A_IO_SIZE: DM9102_IO_SIZE)
1da177e4 192
44c10138
AK		 193#define CHK_IO_SIZE(pci_dev) \
194 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
195 (pci_dev)->revision))
1da177e4
LT		 196
197/* Sten Check */
198#define DEVICE net_device
199
200/* Structure/enum declaration ------------------------------- */
201struct tx_desc {
a31e40f6 202 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
1da177e4
LT		 203 char *tx_buf_ptr; /* Data for us */
204 struct tx_desc *next_tx_desc;
205} __attribute__(( aligned(32) ));
206
207struct rx_desc {
a31e40f6 208 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
1da177e4
LT		 209 struct sk_buff *rx_skb_ptr; /* Data for us */
210 struct rx_desc *next_rx_desc;
211} __attribute__(( aligned(32) ));
212
213struct dmfe_board_info {
214 u32 chip_id; /* Chip vendor/Device ID */
44c10138 215 u8 chip_revision; /* Chip revision */
ead9bffb 216 struct DEVICE *next_dev; /* next device */
1da177e4
LT		 217 struct pci_dev *pdev; /* PCI device */
218 spinlock_t lock;
219
220 long ioaddr; /* I/O base address */
221 u32 cr0_data;
222 u32 cr5_data;
223 u32 cr6_data;
224 u32 cr7_data;
225 u32 cr15_data;
226
227 /* pointer for memory physical address */
228 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
229 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
230 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
231 dma_addr_t first_tx_desc_dma;
232 dma_addr_t first_rx_desc_dma;
233
234 /* descriptor pointer */
235 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
236 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
237 unsigned char *desc_pool_ptr; /* descriptor pool memory */
238 struct tx_desc *first_tx_desc;
239 struct tx_desc *tx_insert_ptr;
240 struct tx_desc *tx_remove_ptr;
241 struct rx_desc *first_rx_desc;
242 struct rx_desc *rx_insert_ptr;
243 struct rx_desc *rx_ready_ptr; /* packet come pointer */
244 unsigned long tx_packet_cnt; /* transmitted packet count */
245 unsigned long tx_queue_cnt; /* wait to send packet count */
246 unsigned long rx_avail_cnt; /* available rx descriptor count */
247 unsigned long interval_rx_cnt; /* rx packet count a callback time */
248
249 u16 HPNA_command; /* For HPNA register 16 */
250 u16 HPNA_timer; /* For HPNA remote device check */
251 u16 dbug_cnt;
252 u16 NIC_capability; /* NIC media capability */
253 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
254
255 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
256 u8 chip_type; /* Keep DM9102A chip type */
257 u8 media_mode; /* user specify media mode */
258 u8 op_mode; /* real work media mode */
259 u8 phy_addr;
1da177e4
LT		 260 u8 wait_reset; /* Hardware failed, need to reset */
261 u8 dm910x_chk_mode; /* Operating mode check */
262 u8 first_in_callback; /* Flag to record state */
f1069046 263 u8 wol_mode; /* user WOL settings */
1da177e4
LT		 264 struct timer_list timer;
265
1da177e4
LT		 266 /* Driver defined statistic counter */
267 unsigned long tx_fifo_underrun;
268 unsigned long tx_loss_carrier;
269 unsigned long tx_no_carrier;
270 unsigned long tx_late_collision;
271 unsigned long tx_excessive_collision;
272 unsigned long tx_jabber_timeout;
273 unsigned long reset_count;
274 unsigned long reset_cr8;
275 unsigned long reset_fatal;
276 unsigned long reset_TXtimeout;
277
278 /* NIC SROM data */
279 unsigned char srom[128];
280};
281
282enum dmfe_offsets {
283 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
284 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
285 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
286 DCR15 = 0x78
287};
288
289enum dmfe_CR6_bits {
290 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
291 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
292 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
293};
294
295/* Global variable declaration ----------------------------- */
296static int __devinitdata printed_version;
03f54b3d 297static const char version[] __devinitconst =
1da177e4
LT		 298 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
299 DRV_VERSION " (" DRV_RELDATE ")\n";
300
301static int dmfe_debug;
302static unsigned char dmfe_media_mode = DMFE_AUTO;
303static u32 dmfe_cr6_user_set;
304
305/* For module input parameter */
306static int debug;
307static u32 cr6set;
308static unsigned char mode = 8;
309static u8 chkmode = 1;
310static u8 HPNA_mode; /* Default: Low Power/High Speed */
311static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
312static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
313static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
314static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
315 4: TX pause packet */
316
317
318/* function declaration ------------------------------------- */
319static int dmfe_open(struct DEVICE *);
ad096463 320static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
1da177e4 321static int dmfe_stop(struct DEVICE *);
1da177e4 322static void dmfe_set_filter_mode(struct DEVICE *);
7282d491 323static const struct ethtool_ops netdev_ethtool_ops;
1da177e4 324static u16 read_srom_word(long ,int);
7d12e780 325static irqreturn_t dmfe_interrupt(int , void *);
1da177e4
LT		 326#ifdef CONFIG_NET_POLL_CONTROLLER
327static void poll_dmfe (struct net_device *dev);
328#endif
329static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
330static void allocate_rx_buffer(struct dmfe_board_info *);
331static void update_cr6(u32, unsigned long);
4302b67e
JP		 332static void send_filter_frame(struct DEVICE *);
333static void dm9132_id_table(struct DEVICE *);
1da177e4
LT		 334static u16 phy_read(unsigned long, u8, u8, u32);
335static void phy_write(unsigned long, u8, u8, u16, u32);
336static void phy_write_1bit(unsigned long, u32);
337static u16 phy_read_1bit(unsigned long);
338static u8 dmfe_sense_speed(struct dmfe_board_info *);
339static void dmfe_process_mode(struct dmfe_board_info *);
340static void dmfe_timer(unsigned long);
341static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
342static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
343static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
344static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
345static void dmfe_dynamic_reset(struct DEVICE *);
346static void dmfe_free_rxbuffer(struct dmfe_board_info *);
347static void dmfe_init_dm910x(struct DEVICE *);
348static void dmfe_parse_srom(struct dmfe_board_info *);
349static void dmfe_program_DM9801(struct dmfe_board_info *, int);
350static void dmfe_program_DM9802(struct dmfe_board_info *);
351static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
352static void dmfe_set_phyxcer(struct dmfe_board_info *);
353
f67ba792 354/* DM910X network board routine ---------------------------- */
1da177e4 355
2765df58
SH		 356static const struct net_device_ops netdev_ops = {
357 .ndo_open = dmfe_open,
358 .ndo_stop = dmfe_stop,
359 .ndo_start_xmit = dmfe_start_xmit,
360 .ndo_set_multicast_list = dmfe_set_filter_mode,
361 .ndo_change_mtu = eth_change_mtu,
362 .ndo_set_mac_address = eth_mac_addr,
363 .ndo_validate_addr = eth_validate_addr,
364#ifdef CONFIG_NET_POLL_CONTROLLER
365 .ndo_poll_controller = poll_dmfe,
366#endif
367};
368
1da177e4
LT		 369/*
370 * Search DM910X board ,allocate space and register it
371 */
372
373static int __devinit dmfe_init_one (struct pci_dev *pdev,
374 const struct pci_device_id *ent)
375{
376 struct dmfe_board_info *db; /* board information structure */
377 struct net_device *dev;
44c10138 378 u32 pci_pmr;
1da177e4
LT		 379 int i, err;
380
381 DMFE_DBUG(0, "dmfe_init_one()", 0);
382
383 if (!printed_version++)
384 printk(version);
385
4d907069
BH		 386 /*
387 * SPARC on-board DM910x chips should be handled by the main
388 * tulip driver, except for early DM9100s.
389 */
390#ifdef CONFIG_TULIP_DM910X
391 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
392 ent->driver_data == PCI_DM9102_ID) {
393 struct device_node *dp = pci_device_to_OF_node(pdev);
394
395 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
dde7c8ef 396 pr_info("skipping on-board DM910x (use tulip)\n");
4d907069
BH		 397 return -ENODEV;
398 }
399 }
400#endif
401
1da177e4
LT		 402 /* Init network device */
403 dev = alloc_etherdev(sizeof(*db));
404 if (dev == NULL)
405 return -ENOMEM;
1da177e4
LT		 406 SET_NETDEV_DEV(dev, &pdev->dev);
407
284901a9 408 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
dde7c8ef 409 pr_warning("32-bit PCI DMA not available\n");
1da177e4
LT		 410 err = -ENODEV;
411 goto err_out_free;
412 }
413
414 /* Enable Master/IO access, Disable memory access */
415 err = pci_enable_device(pdev);
416 if (err)
417 goto err_out_free;
418
419 if (!pci_resource_start(pdev, 0)) {
dde7c8ef 420 pr_err("I/O base is zero\n");
1da177e4
LT		 421 err = -ENODEV;
422 goto err_out_disable;
423 }
424
44c10138 425 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
dde7c8ef 426 pr_err("Allocated I/O size too small\n");
1da177e4
LT		 427 err = -ENODEV;
428 goto err_out_disable;
429 }
430
431#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
432
433 /* Set Latency Timer 80h */
434 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
435 Need a PCI quirk.. */
436
437 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
438#endif
439
440 if (pci_request_regions(pdev, DRV_NAME)) {
dde7c8ef 441 pr_err("Failed to request PCI regions\n");
1da177e4
LT		 442 err = -ENODEV;
443 goto err_out_disable;
444 }
445
446 /* Init system & device */
447 db = netdev_priv(dev);
448
449 /* Allocate Tx/Rx descriptor memory */
f67ba792
ML		 450 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
451 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
74d5e8ac
FT		 452 if (!db->desc_pool_ptr)
453 goto err_out_res;
f67ba792
ML		 454
455 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
456 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
74d5e8ac
FT		 457 if (!db->buf_pool_ptr)
458 goto err_out_free_desc;
1da177e4
LT		 459
460 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
461 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
462 db->buf_pool_start = db->buf_pool_ptr;
463 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
464
465 db->chip_id = ent->driver_data;
466 db->ioaddr = pci_resource_start(pdev, 0);
44c10138 467 db->chip_revision = pdev->revision;
f1069046 468 db->wol_mode = 0;
1da177e4
LT		 469
470 db->pdev = pdev;
471
472 dev->base_addr = db->ioaddr;
473 dev->irq = pdev->irq;
474 pci_set_drvdata(pdev, dev);
2765df58 475 dev->netdev_ops = &netdev_ops;
1da177e4 476 dev->ethtool_ops = &netdev_ethtool_ops;
cfa51b9d 477 netif_carrier_off(dev);
1da177e4
LT		 478 spin_lock_init(&db->lock);
479
480 pci_read_config_dword(pdev, 0x50, &pci_pmr);
481 pci_pmr &= 0x70000;
44c10138 482 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
1da177e4
LT		 483 db->chip_type = 1; /* DM9102A E3 */
484 else
485 db->chip_type = 0;
486
487 /* read 64 word srom data */
488 for (i = 0; i < 64; i++)
a31e40f6 489 ((__le16 *) db->srom)[i] =
f67ba792 490 cpu_to_le16(read_srom_word(db->ioaddr, i));
1da177e4
LT		 491
492 /* Set Node address */
493 for (i = 0; i < 6; i++)
494 dev->dev_addr[i] = db->srom[20 + i];
495
496 err = register_netdev (dev);
497 if (err)
74d5e8ac 498 goto err_out_free_buf;
1da177e4 499
dde7c8ef
JP		 500 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
501 ent->driver_data >> 16,
502 pci_name(pdev), dev->dev_addr, dev->irq);
1da177e4
LT		 503
504 pci_set_master(pdev);
505
506 return 0;
507
74d5e8ac
FT		 508err_out_free_buf:
509 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
510 db->buf_pool_ptr, db->buf_pool_dma_ptr);
511err_out_free_desc:
512 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
513 db->desc_pool_ptr, db->desc_pool_dma_ptr);
1da177e4
LT		 514err_out_res:
515 pci_release_regions(pdev);
516err_out_disable:
517 pci_disable_device(pdev);
518err_out_free:
519 pci_set_drvdata(pdev, NULL);
520 free_netdev(dev);
521
522 return err;
523}
524
525
526static void __devexit dmfe_remove_one (struct pci_dev *pdev)
527{
528 struct net_device *dev = pci_get_drvdata(pdev);
529 struct dmfe_board_info *db = netdev_priv(dev);
530
531 DMFE_DBUG(0, "dmfe_remove_one()", 0);
532
533 if (dev) {
4dc68f3d
ML		 534
535 unregister_netdev(dev);
536
1da177e4
LT		 537 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
538 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
539 db->desc_pool_dma_ptr);
540 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
541 db->buf_pool_ptr, db->buf_pool_dma_ptr);
1da177e4
LT		 542 pci_release_regions(pdev);
543 free_netdev(dev); /* free board information */
4dc68f3d 544
1da177e4
LT		 545 pci_set_drvdata(pdev, NULL);
546 }
547
548 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
549}
550
551
552/*
553 * Open the interface.
554 * The interface is opened whenever "ifconfig" actives it.
555 */
556
557static int dmfe_open(struct DEVICE *dev)
558{
559 int ret;
560 struct dmfe_board_info *db = netdev_priv(dev);
561
562 DMFE_DBUG(0, "dmfe_open", 0);
563
a0607fd3 564 ret = request_irq(dev->irq, dmfe_interrupt,
f67ba792 565 IRQF_SHARED, dev->name, dev);
1da177e4
LT		 566 if (ret)
567 return ret;
568
569 /* system variable init */
570 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
571 db->tx_packet_cnt = 0;
572 db->tx_queue_cnt = 0;
573 db->rx_avail_cnt = 0;
1da177e4
LT		 574 db->wait_reset = 0;
575
576 db->first_in_callback = 0;
577 db->NIC_capability = 0xf; /* All capability*/
578 db->PHY_reg4 = 0x1e0;
579
580 /* CR6 operation mode decision */
581 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
44c10138 582 (db->chip_revision >= 0x30) ) {
1da177e4
LT		 583 db->cr6_data |= DMFE_TXTH_256;
584 db->cr0_data = CR0_DEFAULT;
585 db->dm910x_chk_mode=4; /* Enter the normal mode */
586 } else {
587 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
588 db->cr0_data = 0;
589 db->dm910x_chk_mode = 1; /* Enter the check mode */
590 }
591
421f91d2 592 /* Initialize DM910X board */
1da177e4
LT		 593 dmfe_init_dm910x(dev);
594
595 /* Active System Interface */
596 netif_wake_queue(dev);
597
598 /* set and active a timer process */
599 init_timer(&db->timer);
600 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
601 db->timer.data = (unsigned long)dev;
c061b18d 602 db->timer.function = dmfe_timer;
1da177e4
LT		 603 add_timer(&db->timer);
604
605 return 0;
606}
607
608
421f91d2 609/* Initialize DM910X board
1da177e4 610 * Reset DM910X board
421f91d2 611 * Initialize TX/Rx descriptor chain structure
1da177e4
LT		 612 * Send the set-up frame
613 * Enable Tx/Rx machine
614 */
615
616static void dmfe_init_dm910x(struct DEVICE *dev)
617{
618 struct dmfe_board_info *db = netdev_priv(dev);
619 unsigned long ioaddr = db->ioaddr;
620
621 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
622
623 /* Reset DM910x MAC controller */
624 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
625 udelay(100);
626 outl(db->cr0_data, ioaddr + DCR0);
627 udelay(5);
628
629 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
630 db->phy_addr = 1;
631
632 /* Parser SROM and media mode */
633 dmfe_parse_srom(db);
634 db->media_mode = dmfe_media_mode;
635
636 /* RESET Phyxcer Chip by GPR port bit 7 */
637 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
638 if (db->chip_id == PCI_DM9009_ID) {
639 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
640 mdelay(300); /* Delay 300 ms */
641 }
642 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
643
644 /* Process Phyxcer Media Mode */
645 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
646 dmfe_set_phyxcer(db);
647
648 /* Media Mode Process */
649 if ( !(db->media_mode & DMFE_AUTO) )
650 db->op_mode = db->media_mode; /* Force Mode */
651
421f91d2 652 /* Initialize Transmit/Receive decriptor and CR3/4 */
1da177e4
LT		 653 dmfe_descriptor_init(db, ioaddr);
654
655 /* Init CR6 to program DM910x operation */
656 update_cr6(db->cr6_data, ioaddr);
657
658 /* Send setup frame */
659 if (db->chip_id == PCI_DM9132_ID)
4302b67e 660 dm9132_id_table(dev); /* DM9132 */
1da177e4 661 else
4302b67e 662 send_filter_frame(dev); /* DM9102/DM9102A */
1da177e4
LT		 663
664 /* Init CR7, interrupt active bit */
665 db->cr7_data = CR7_DEFAULT;
666 outl(db->cr7_data, ioaddr + DCR7);
667
668 /* Init CR15, Tx jabber and Rx watchdog timer */
669 outl(db->cr15_data, ioaddr + DCR15);
670
671 /* Enable DM910X Tx/Rx function */
672 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
673 update_cr6(db->cr6_data, ioaddr);
674}
675
676
677/*
678 * Hardware start transmission.
679 * Send a packet to media from the upper layer.
680 */
681
ad096463
SH		 682static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
683 struct DEVICE *dev)
1da177e4
LT		 684{
685 struct dmfe_board_info *db = netdev_priv(dev);
686 struct tx_desc *txptr;
687 unsigned long flags;
688
689 DMFE_DBUG(0, "dmfe_start_xmit", 0);
690
691 /* Resource flag check */
692 netif_stop_queue(dev);
693
694 /* Too large packet check */
695 if (skb->len > MAX_PACKET_SIZE) {
dde7c8ef 696 pr_err("big packet = %d\n", (u16)skb->len);
1da177e4 697 dev_kfree_skb(skb);
ec634fe3 698 return NETDEV_TX_OK;
1da177e4
LT		 699 }
700
701 spin_lock_irqsave(&db->lock, flags);
702
703 /* No Tx resource check, it never happen nromally */
704 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
705 spin_unlock_irqrestore(&db->lock, flags);
dde7c8ef 706 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
5b548140 707 return NETDEV_TX_BUSY;
1da177e4
LT		 708 }
709
710 /* Disable NIC interrupt */
711 outl(0, dev->base_addr + DCR7);
712
713 /* transmit this packet */
714 txptr = db->tx_insert_ptr;
d626f62b 715 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
1da177e4
LT		 716 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
717
718 /* Point to next transmit free descriptor */
719 db->tx_insert_ptr = txptr->next_tx_desc;
720
721 /* Transmit Packet Process */
722 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
723 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
724 db->tx_packet_cnt++; /* Ready to send */
725 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
726 dev->trans_start = jiffies; /* saved time stamp */
727 } else {
728 db->tx_queue_cnt++; /* queue TX packet */
729 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
730 }
731
732 /* Tx resource check */
733 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
734 netif_wake_queue(dev);
735
736 /* Restore CR7 to enable interrupt */
737 spin_unlock_irqrestore(&db->lock, flags);
738 outl(db->cr7_data, dev->base_addr + DCR7);
739
740 /* free this SKB */
741 dev_kfree_skb(skb);
742
ec634fe3 743 return NETDEV_TX_OK;
1da177e4
LT		 744}
745
746
747/*
748 * Stop the interface.
749 * The interface is stopped when it is brought.
750 */
751
752static int dmfe_stop(struct DEVICE *dev)
753{
754 struct dmfe_board_info *db = netdev_priv(dev);
755 unsigned long ioaddr = dev->base_addr;
756
757 DMFE_DBUG(0, "dmfe_stop", 0);
758
759 /* disable system */
760 netif_stop_queue(dev);
761
762 /* deleted timer */
763 del_timer_sync(&db->timer);
764
765 /* Reset & stop DM910X board */
766 outl(DM910X_RESET, ioaddr + DCR0);
767 udelay(5);
768 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
769
770 /* free interrupt */
771 free_irq(dev->irq, dev);
772
773 /* free allocated rx buffer */
774 dmfe_free_rxbuffer(db);
775
776#if 0
777 /* show statistic counter */
dde7c8ef
JP		 778 printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
779 db->tx_fifo_underrun, db->tx_excessive_collision,
780 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
781 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
782 db->reset_fatal, db->reset_TXtimeout);
1da177e4
LT		 783#endif
784
785 return 0;
786}
787
788
789/*
790 * DM9102 insterrupt handler
791 * receive the packet to upper layer, free the transmitted packet
792 */
793
7d12e780 794static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
1da177e4
LT		 795{
796 struct DEVICE *dev = dev_id;
797 struct dmfe_board_info *db = netdev_priv(dev);
798 unsigned long ioaddr = dev->base_addr;
799 unsigned long flags;
800
801 DMFE_DBUG(0, "dmfe_interrupt()", 0);
802
1da177e4
LT		 803 spin_lock_irqsave(&db->lock, flags);
804
805 /* Got DM910X status */
806 db->cr5_data = inl(ioaddr + DCR5);
807 outl(db->cr5_data, ioaddr + DCR5);
808 if ( !(db->cr5_data & 0xc1) ) {
809 spin_unlock_irqrestore(&db->lock, flags);
810 return IRQ_HANDLED;
811 }
812
813 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
814 outl(0, ioaddr + DCR7);
815
816 /* Check system status */
817 if (db->cr5_data & 0x2000) {
818 /* system bus error happen */
819 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
820 db->reset_fatal++;
821 db->wait_reset = 1; /* Need to RESET */
822 spin_unlock_irqrestore(&db->lock, flags);
823 return IRQ_HANDLED;
824 }
825
826 /* Received the coming packet */
827 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
828 dmfe_rx_packet(dev, db);
829
830 /* reallocate rx descriptor buffer */
831 if (db->rx_avail_cnt<RX_DESC_CNT)
832 allocate_rx_buffer(db);
833
834 /* Free the transmitted descriptor */
835 if ( db->cr5_data & 0x01)
836 dmfe_free_tx_pkt(dev, db);
837
838 /* Mode Check */
839 if (db->dm910x_chk_mode & 0x2) {
840 db->dm910x_chk_mode = 0x4;
841 db->cr6_data |= 0x100;
842 update_cr6(db->cr6_data, db->ioaddr);
843 }
844
845 /* Restore CR7 to enable interrupt mask */
846 outl(db->cr7_data, ioaddr + DCR7);
847
848 spin_unlock_irqrestore(&db->lock, flags);
849 return IRQ_HANDLED;
850}
851
852
853#ifdef CONFIG_NET_POLL_CONTROLLER
854/*
855 * Polling 'interrupt' - used by things like netconsole to send skbs
856 * without having to re-enable interrupts. It's not called while
857 * the interrupt routine is executing.
858 */
859
860static void poll_dmfe (struct net_device *dev)
861{
862 /* disable_irq here is not very nice, but with the lockless
863 interrupt handler we have no other choice. */
864 disable_irq(dev->irq);
7d12e780 865 dmfe_interrupt (dev->irq, dev);
1da177e4
LT		 866 enable_irq(dev->irq);
867}
868#endif
869
870/*
871 * Free TX resource after TX complete
872 */
873
874static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
875{
876 struct tx_desc *txptr;
877 unsigned long ioaddr = dev->base_addr;
878 u32 tdes0;
879
880 txptr = db->tx_remove_ptr;
881 while(db->tx_packet_cnt) {
882 tdes0 = le32_to_cpu(txptr->tdes0);
dde7c8ef 883 pr_debug("tdes0=%x\n", tdes0);
1da177e4
LT		 884 if (tdes0 & 0x80000000)
885 break;
886
887 /* A packet sent completed */
888 db->tx_packet_cnt--;
2765df58 889 dev->stats.tx_packets++;
1da177e4
LT		 890
891 /* Transmit statistic counter */
892 if ( tdes0 != 0x7fffffff ) {
dde7c8ef 893 pr_debug("tdes0=%x\n", tdes0);
2765df58
SH		 894 dev->stats.collisions += (tdes0 >> 3) & 0xf;
895 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
1da177e4 896 if (tdes0 & TDES0_ERR_MASK) {
2765df58 897 dev->stats.tx_errors++;
1da177e4
LT		 898
899 if (tdes0 & 0x0002) { /* UnderRun */
900 db->tx_fifo_underrun++;
901 if ( !(db->cr6_data & CR6_SFT) ) {
902 db->cr6_data = db->cr6_data | CR6_SFT;
903 update_cr6(db->cr6_data, db->ioaddr);
904 }
905 }
906 if (tdes0 & 0x0100)
907 db->tx_excessive_collision++;
908 if (tdes0 & 0x0200)
909 db->tx_late_collision++;
910 if (tdes0 & 0x0400)
911 db->tx_no_carrier++;
912 if (tdes0 & 0x0800)
913 db->tx_loss_carrier++;
914 if (tdes0 & 0x4000)
915 db->tx_jabber_timeout++;
916 }
917 }
918
919 txptr = txptr->next_tx_desc;
920 }/* End of while */
921
922 /* Update TX remove pointer to next */
923 db->tx_remove_ptr = txptr;
924
925 /* Send the Tx packet in queue */
926 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
927 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
928 db->tx_packet_cnt++; /* Ready to send */
929 db->tx_queue_cnt--;
930 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
931 dev->trans_start = jiffies; /* saved time stamp */
932 }
933
934 /* Resource available check */
935 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
936 netif_wake_queue(dev); /* Active upper layer, send again */
937}
938
939
940/*
941 * Calculate the CRC valude of the Rx packet
942 * flag = 1 : return the reverse CRC (for the received packet CRC)
943 * 0 : return the normal CRC (for Hash Table index)
944 */
945
946static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
947{
948 u32 crc = crc32(~0, Data, Len);
949 if (flag) crc = ~crc;
950 return crc;
951}
952
953
954/*
955 * Receive the come packet and pass to upper layer
956 */
957
958static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
959{
960 struct rx_desc *rxptr;
4dc68f3d 961 struct sk_buff *skb, *newskb;
1da177e4
LT		 962 int rxlen;
963 u32 rdes0;
964
965 rxptr = db->rx_ready_ptr;
966
967 while(db->rx_avail_cnt) {
968 rdes0 = le32_to_cpu(rxptr->rdes0);
969 if (rdes0 & 0x80000000) /* packet owner check */
970 break;
971
972 db->rx_avail_cnt--;
973 db->interval_rx_cnt++;
974
f67ba792
ML		 975 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
976 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
977
1da177e4
LT		 978 if ( (rdes0 & 0x300) != 0x300) {
979 /* A packet without First/Last flag */
980 /* reuse this SKB */
981 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
982 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
983 } else {
984 /* A packet with First/Last flag */
985 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
986
987 /* error summary bit check */
988 if (rdes0 & 0x8000) {
989 /* This is a error packet */
dde7c8ef 990 pr_debug("rdes0: %x\n", rdes0);
2765df58 991 dev->stats.rx_errors++;
1da177e4 992 if (rdes0 & 1)
2765df58 993 dev->stats.rx_fifo_errors++;
1da177e4 994 if (rdes0 & 2)
2765df58 995 dev->stats.rx_crc_errors++;
1da177e4 996 if (rdes0 & 0x80)
2765df58 997 dev->stats.rx_length_errors++;
1da177e4
LT		 998 }
999
1000 if ( !(rdes0 & 0x8000) ||
1001 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
1002 skb = rxptr->rx_skb_ptr;
1003
1004 /* Received Packet CRC check need or not */
1005 if ( (db->dm910x_chk_mode & 1) &&
689be439
DM		 1006 (cal_CRC(skb->data, rxlen, 1) !=
1007 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1da177e4
LT		 1008 /* Found a error received packet */
1009 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1010 db->dm910x_chk_mode = 3;
1011 } else {
1012 /* Good packet, send to upper layer */
1013 /* Shorst packet used new SKB */
4dc68f3d
ML		 1014 if ((rxlen < RX_COPY_SIZE) &&
1015 ((newskb = dev_alloc_skb(rxlen + 2))
1016 != NULL)) {
1017
1018 skb = newskb;
1da177e4 1019 /* size less than COPY_SIZE, allocate a rxlen SKB */
1da177e4 1020 skb_reserve(skb, 2); /* 16byte align */
d626f62b
ACM		 1021 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1022 skb_put(skb, rxlen),
1023 rxlen);
1da177e4 1024 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 1025 } else
1da177e4 1026 skb_put(skb, rxlen);
4c13eb66 1027
1da177e4
LT		 1028 skb->protocol = eth_type_trans(skb, dev);
1029 netif_rx(skb);
2765df58
SH		 1030 dev->stats.rx_packets++;
1031 dev->stats.rx_bytes += rxlen;
1da177e4
LT		 1032 }
1033 } else {
1034 /* Reuse SKB buffer when the packet is error */
1035 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1036 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1037 }
1038 }
1039
1040 rxptr = rxptr->next_rx_desc;
1041 }
1042
1043 db->rx_ready_ptr = rxptr;
1044}
1045
1da177e4
LT		 1046/*
1047 * Set DM910X multicast address
1048 */
1049
1050static void dmfe_set_filter_mode(struct DEVICE * dev)
1051{
1052 struct dmfe_board_info *db = netdev_priv(dev);
1053 unsigned long flags;
4cd24eaf 1054 int mc_count = netdev_mc_count(dev);
1da177e4
LT		 1055
1056 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1057 spin_lock_irqsave(&db->lock, flags);
1058
1059 if (dev->flags & IFF_PROMISC) {
1060 DMFE_DBUG(0, "Enable PROM Mode", 0);
1061 db->cr6_data |= CR6_PM | CR6_PBF;
1062 update_cr6(db->cr6_data, db->ioaddr);
1063 spin_unlock_irqrestore(&db->lock, flags);
1064 return;
1065 }
1066
4cd24eaf
JP		 1067 if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
1068 DMFE_DBUG(0, "Pass all multicast address", mc_count);
1da177e4
LT		 1069 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1070 db->cr6_data |= CR6_PAM;
1071 spin_unlock_irqrestore(&db->lock, flags);
1072 return;
1073 }
1074
4cd24eaf 1075 DMFE_DBUG(0, "Set multicast address", mc_count);
1da177e4 1076 if (db->chip_id == PCI_DM9132_ID)
4302b67e 1077 dm9132_id_table(dev); /* DM9132 */
1da177e4 1078 else
4302b67e 1079 send_filter_frame(dev); /* DM9102/DM9102A */
1da177e4
LT		 1080 spin_unlock_irqrestore(&db->lock, flags);
1081}
1082
f1069046
ML		 1083/*
1084 * Ethtool interace
1085 */
1086
1087static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1da177e4
LT		 1088 struct ethtool_drvinfo *info)
1089{
1090 struct dmfe_board_info *np = netdev_priv(dev);
1091
1092 strcpy(info->driver, DRV_NAME);
1093 strcpy(info->version, DRV_VERSION);
1094 if (np->pdev)
1095 strcpy(info->bus_info, pci_name(np->pdev));
1096 else
1097 sprintf(info->bus_info, "EISA 0x%lx %d",
1098 dev->base_addr, dev->irq);
1099}
1100
f1069046
ML		 1101static int dmfe_ethtool_set_wol(struct net_device *dev,
1102 struct ethtool_wolinfo *wolinfo)
1103{
1104 struct dmfe_board_info *db = netdev_priv(dev);
1105
1106 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1107 WAKE_ARP | WAKE_MAGICSECURE))
1108 return -EOPNOTSUPP;
1109
1110 db->wol_mode = wolinfo->wolopts;
1111 return 0;
1112}
1113
1114static void dmfe_ethtool_get_wol(struct net_device *dev,
1115 struct ethtool_wolinfo *wolinfo)
1116{
1117 struct dmfe_board_info *db = netdev_priv(dev);
1118
1119 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1120 wolinfo->wolopts = db->wol_mode;
f1069046
ML		 1121}
1122
1123
7282d491 1124static const struct ethtool_ops netdev_ethtool_ops = {
f1069046 1125 .get_drvinfo = dmfe_ethtool_get_drvinfo,
cfa51b9d 1126 .get_link = ethtool_op_get_link,
f1069046
ML		 1127 .set_wol = dmfe_ethtool_set_wol,
1128 .get_wol = dmfe_ethtool_get_wol,
1da177e4
LT		 1129};
1130
1131/*
1132 * A periodic timer routine
1133 * Dynamic media sense, allocate Rx buffer...
1134 */
1135
1136static void dmfe_timer(unsigned long data)
1137{
1138 u32 tmp_cr8;
1139 unsigned char tmp_cr12;
1140 struct DEVICE *dev = (struct DEVICE *) data;
1141 struct dmfe_board_info *db = netdev_priv(dev);
1142 unsigned long flags;
1143
cfa51b9d
ML		 1144 int link_ok, link_ok_phy;
1145
1da177e4
LT		 1146 DMFE_DBUG(0, "dmfe_timer()", 0);
1147 spin_lock_irqsave(&db->lock, flags);
1148
1149 /* Media mode process when Link OK before enter this route */
1150 if (db->first_in_callback == 0) {
1151 db->first_in_callback = 1;
1152 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1153 db->cr6_data &= ~0x40000;
1154 update_cr6(db->cr6_data, db->ioaddr);
f67ba792
ML		 1155 phy_write(db->ioaddr,
1156 db->phy_addr, 0, 0x1000, db->chip_id);
1da177e4
LT		 1157 db->cr6_data |= 0x40000;
1158 update_cr6(db->cr6_data, db->ioaddr);
1159 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1160 add_timer(&db->timer);
1161 spin_unlock_irqrestore(&db->lock, flags);
1162 return;
1163 }
1164 }
1165
1166
1167 /* Operating Mode Check */
1168 if ( (db->dm910x_chk_mode & 0x1) &&
2765df58 1169 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1da177e4
LT		 1170 db->dm910x_chk_mode = 0x4;
1171
1172 /* Dynamic reset DM910X : system error or transmit time-out */
1173 tmp_cr8 = inl(db->ioaddr + DCR8);
1174 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1175 db->reset_cr8++;
1176 db->wait_reset = 1;
1177 }
1178 db->interval_rx_cnt = 0;
1179
1180 /* TX polling kick monitor */
1181 if ( db->tx_packet_cnt &&
1ae5dc34 1182 time_after(jiffies, dev_trans_start(dev) + DMFE_TX_KICK) ) {
1da177e4
LT		 1183 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1184
1185 /* TX Timeout */
1ae5dc34 1186 if (time_after(jiffies, dev_trans_start(dev) + DMFE_TX_TIMEOUT) ) {
1da177e4
LT		 1187 db->reset_TXtimeout++;
1188 db->wait_reset = 1;
dde7c8ef 1189 dev_warn(&dev->dev, "Tx timeout - resetting\n");
1da177e4
LT		 1190 }
1191 }
1192
1193 if (db->wait_reset) {
1194 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1195 db->reset_count++;
1196 dmfe_dynamic_reset(dev);
1197 db->first_in_callback = 0;
1198 db->timer.expires = DMFE_TIMER_WUT;
1199 add_timer(&db->timer);
1200 spin_unlock_irqrestore(&db->lock, flags);
1201 return;
1202 }
1203
1204 /* Link status check, Dynamic media type change */
1205 if (db->chip_id == PCI_DM9132_ID)
1206 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1207 else
1208 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1209
1210 if ( ((db->chip_id == PCI_DM9102_ID) &&
44c10138 1211 (db->chip_revision == 0x30)) ||
1da177e4 1212 ((db->chip_id == PCI_DM9132_ID) &&
44c10138 1213 (db->chip_revision == 0x10)) ) {
1da177e4
LT		 1214 /* DM9102A Chip */
1215 if (tmp_cr12 & 2)
cfa51b9d 1216 link_ok = 0;
1da177e4 1217 else
cfa51b9d 1218 link_ok = 1;
1da177e4 1219 }
cfa51b9d
ML		 1220 else
1221 /*0x43 is used instead of 0x3 because bit 6 should represent
1222 link status of external PHY */
1223 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1224
1225
1226 /* If chip reports that link is failed it could be because external
1227 PHY link status pin is not conected correctly to chip
1228 To be sure ask PHY too.
1229 */
1230
1231 /* need a dummy read because of PHY's register latch*/
1232 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1233 link_ok_phy = (phy_read (db->ioaddr,
1234 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1da177e4 1235
cfa51b9d
ML		 1236 if (link_ok_phy != link_ok) {
1237 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1238 link_ok = link_ok | link_ok_phy;
1239 }
1240
1241 if ( !link_ok && netif_carrier_ok(dev)) {
1da177e4
LT		 1242 /* Link Failed */
1243 DMFE_DBUG(0, "Link Failed", tmp_cr12);
cfa51b9d 1244 netif_carrier_off(dev);
1da177e4
LT		 1245
1246 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1247 /* AUTO or force 1M Homerun/Longrun don't need */
1248 if ( !(db->media_mode & 0x38) )
f67ba792
ML		 1249 phy_write(db->ioaddr, db->phy_addr,
1250 0, 0x1000, db->chip_id);
1da177e4
LT		 1251
1252 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1253 if (db->media_mode & DMFE_AUTO) {
1254 /* 10/100M link failed, used 1M Home-Net */
1255 db->cr6_data|=0x00040000; /* bit18=1, MII */
1256 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1257 update_cr6(db->cr6_data, db->ioaddr);
1258 }
cfa51b9d
ML		 1259 } else if (!netif_carrier_ok(dev)) {
1260
1261 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1262
1263 /* Auto Sense Speed */
1264 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1265 netif_carrier_on(dev);
1266 SHOW_MEDIA_TYPE(db->op_mode);
1da177e4
LT		 1267 }
1268
cfa51b9d
ML		 1269 dmfe_process_mode(db);
1270 }
1271
1da177e4
LT		 1272 /* HPNA remote command check */
1273 if (db->HPNA_command & 0xf00) {
1274 db->HPNA_timer--;
1275 if (!db->HPNA_timer)
1276 dmfe_HPNA_remote_cmd_chk(db);
1277 }
1278
1279 /* Timer active again */
1280 db->timer.expires = DMFE_TIMER_WUT;
1281 add_timer(&db->timer);
1282 spin_unlock_irqrestore(&db->lock, flags);
1283}
1284
1285
1286/*
1287 * Dynamic reset the DM910X board
1288 * Stop DM910X board
1289 * Free Tx/Rx allocated memory
1290 * Reset DM910X board
421f91d2 1291 * Re-initialize DM910X board
1da177e4
LT		 1292 */
1293
1294static void dmfe_dynamic_reset(struct DEVICE *dev)
1295{
1296 struct dmfe_board_info *db = netdev_priv(dev);
1297
1298 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1299
1300 /* Sopt MAC controller */
1301 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1302 update_cr6(db->cr6_data, dev->base_addr);
1303 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1304 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1305
1306 /* Disable upper layer interface */
1307 netif_stop_queue(dev);
1308
1309 /* Free Rx Allocate buffer */
1310 dmfe_free_rxbuffer(db);
1311
1312 /* system variable init */
1313 db->tx_packet_cnt = 0;
1314 db->tx_queue_cnt = 0;
1315 db->rx_avail_cnt = 0;
cfa51b9d 1316 netif_carrier_off(dev);
1da177e4
LT		 1317 db->wait_reset = 0;
1318
421f91d2 1319 /* Re-initialize DM910X board */
1da177e4
LT		 1320 dmfe_init_dm910x(dev);
1321
1322 /* Restart upper layer interface */
1323 netif_wake_queue(dev);
1324}
1325
1326
1327/*
1328 * free all allocated rx buffer
1329 */
1330
1331static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1332{
1333 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1334
1335 /* free allocated rx buffer */
1336 while (db->rx_avail_cnt) {
1337 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1338 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1339 db->rx_avail_cnt--;
1340 }
1341}
1342
1343
1344/*
1345 * Reuse the SK buffer
1346 */
1347
1348static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1349{
1350 struct rx_desc *rxptr = db->rx_insert_ptr;
1351
1352 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1353 rxptr->rx_skb_ptr = skb;
f67ba792
ML		 1354 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1355 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1356 wmb();
1357 rxptr->rdes0 = cpu_to_le32(0x80000000);
1358 db->rx_avail_cnt++;
1359 db->rx_insert_ptr = rxptr->next_rx_desc;
1360 } else
1361 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1362}
1363
1364
1365/*
1366 * Initialize transmit/Receive descriptor
1367 * Using Chain structure, and allocate Tx/Rx buffer
1368 */
1369
1370static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1371{
1372 struct tx_desc *tmp_tx;
1373 struct rx_desc *tmp_rx;
1374 unsigned char *tmp_buf;
1375 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1376 dma_addr_t tmp_buf_dma;
1377 int i;
1378
1379 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1380
1381 /* tx descriptor start pointer */
1382 db->tx_insert_ptr = db->first_tx_desc;
1383 db->tx_remove_ptr = db->first_tx_desc;
1384 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1385
1386 /* rx descriptor start pointer */
f67ba792
ML		 1387 db->first_rx_desc = (void *)db->first_tx_desc +
1388 sizeof(struct tx_desc) * TX_DESC_CNT;
1389
1390 db->first_rx_desc_dma = db->first_tx_desc_dma +
1391 sizeof(struct tx_desc) * TX_DESC_CNT;
1da177e4
LT		 1392 db->rx_insert_ptr = db->first_rx_desc;
1393 db->rx_ready_ptr = db->first_rx_desc;
1394 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1395
1396 /* Init Transmit chain */
1397 tmp_buf = db->buf_pool_start;
1398 tmp_buf_dma = db->buf_pool_dma_start;
1399 tmp_tx_dma = db->first_tx_desc_dma;
1400 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1401 tmp_tx->tx_buf_ptr = tmp_buf;
1402 tmp_tx->tdes0 = cpu_to_le32(0);
1403 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1404 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1405 tmp_tx_dma += sizeof(struct tx_desc);
1406 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1407 tmp_tx->next_tx_desc = tmp_tx + 1;
1408 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1409 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1410 }
1411 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1412 tmp_tx->next_tx_desc = db->first_tx_desc;
1413
1414 /* Init Receive descriptor chain */
1415 tmp_rx_dma=db->first_rx_desc_dma;
1416 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1417 tmp_rx->rdes0 = cpu_to_le32(0);
1418 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1419 tmp_rx_dma += sizeof(struct rx_desc);
1420 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1421 tmp_rx->next_rx_desc = tmp_rx + 1;
1422 }
1423 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1424 tmp_rx->next_rx_desc = db->first_rx_desc;
1425
1426 /* pre-allocate Rx buffer */
1427 allocate_rx_buffer(db);
1428}
1429
1430
1431/*
1432 * Update CR6 value
1433 * Firstly stop DM910X , then written value and start
1434 */
1435
1436static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1437{
1438 u32 cr6_tmp;
1439
1440 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1441 outl(cr6_tmp, ioaddr + DCR6);
1442 udelay(5);
1443 outl(cr6_data, ioaddr + DCR6);
1444 udelay(5);
1445}
1446
1447
1448/*
1449 * Send a setup frame for DM9132
421f91d2 1450 * This setup frame initialize DM910X address filter mode
1da177e4
LT		 1451*/
1452
4302b67e 1453static void dm9132_id_table(struct DEVICE *dev)
1da177e4 1454{
22bedad3 1455 struct netdev_hw_addr *ha;
1da177e4
LT		 1456 u16 * addrptr;
1457 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1458 u32 hash_val;
1459 u16 i, hash_table[4];
1460
1461 DMFE_DBUG(0, "dm9132_id_table()", 0);
1462
1463 /* Node address */
1464 addrptr = (u16 *) dev->dev_addr;
1465 outw(addrptr[0], ioaddr);
1466 ioaddr += 4;
1467 outw(addrptr[1], ioaddr);
1468 ioaddr += 4;
1469 outw(addrptr[2], ioaddr);
1470 ioaddr += 4;
1471
1472 /* Clear Hash Table */
4302b67e 1473 memset(hash_table, 0, sizeof(hash_table));
1da177e4
LT		 1474
1475 /* broadcast address */
1476 hash_table[3] = 0x8000;
1477
1478 /* the multicast address in Hash Table : 64 bits */
22bedad3
JP		 1479 netdev_for_each_mc_addr(ha, dev) {
1480 hash_val = cal_CRC((char *) ha->addr, 6, 0) & 0x3f;
1da177e4
LT		 1481 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1482 }
1483
1484 /* Write the hash table to MAC MD table */
1485 for (i = 0; i < 4; i++, ioaddr += 4)
1486 outw(hash_table[i], ioaddr);
1487}
1488
1489
1490/*
1491 * Send a setup frame for DM9102/DM9102A
421f91d2 1492 * This setup frame initialize DM910X address filter mode
1da177e4
LT		 1493 */
1494
4302b67e 1495static void send_filter_frame(struct DEVICE *dev)
1da177e4
LT		 1496{
1497 struct dmfe_board_info *db = netdev_priv(dev);
22bedad3 1498 struct netdev_hw_addr *ha;
1da177e4
LT		 1499 struct tx_desc *txptr;
1500 u16 * addrptr;
1501 u32 * suptr;
1502 int i;
1503
1504 DMFE_DBUG(0, "send_filter_frame()", 0);
1505
1506 txptr = db->tx_insert_ptr;
1507 suptr = (u32 *) txptr->tx_buf_ptr;
1508
1509 /* Node address */
1510 addrptr = (u16 *) dev->dev_addr;
1511 *suptr++ = addrptr[0];
1512 *suptr++ = addrptr[1];
1513 *suptr++ = addrptr[2];
1514
1515 /* broadcast address */
1516 *suptr++ = 0xffff;
1517 *suptr++ = 0xffff;
1518 *suptr++ = 0xffff;
1519
1520 /* fit the multicast address */
22bedad3
JP		 1521 netdev_for_each_mc_addr(ha, dev) {
1522 addrptr = (u16 *) ha->addr;
1da177e4
LT		 1523 *suptr++ = addrptr[0];
1524 *suptr++ = addrptr[1];
1525 *suptr++ = addrptr[2];
1526 }
1527
4302b67e 1528 for (i = netdev_mc_count(dev); i < 14; i++) {
1da177e4
LT		 1529 *suptr++ = 0xffff;
1530 *suptr++ = 0xffff;
1531 *suptr++ = 0xffff;
1532 }
1533
1534 /* prepare the setup frame */
1535 db->tx_insert_ptr = txptr->next_tx_desc;
1536 txptr->tdes1 = cpu_to_le32(0x890000c0);
1537
1538 /* Resource Check and Send the setup packet */
1539 if (!db->tx_packet_cnt) {
1540 /* Resource Empty */
1541 db->tx_packet_cnt++;
1542 txptr->tdes0 = cpu_to_le32(0x80000000);
1543 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1544 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1545 update_cr6(db->cr6_data, dev->base_addr);
1546 dev->trans_start = jiffies;
1547 } else
1548 db->tx_queue_cnt++; /* Put in TX queue */
1549}
1550
1551
1552/*
1553 * Allocate rx buffer,
1554 * As possible as allocate maxiumn Rx buffer
1555 */
1556
1557static void allocate_rx_buffer(struct dmfe_board_info *db)
1558{
1559 struct rx_desc *rxptr;
1560 struct sk_buff *skb;
1561
1562 rxptr = db->rx_insert_ptr;
1563
1564 while(db->rx_avail_cnt < RX_DESC_CNT) {
1565 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1566 break;
1567 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
f67ba792
ML		 1568 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1569 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1570 wmb();
1571 rxptr->rdes0 = cpu_to_le32(0x80000000);
1572 rxptr = rxptr->next_rx_desc;
1573 db->rx_avail_cnt++;
1574 }
1575
1576 db->rx_insert_ptr = rxptr;
1577}
1578
1579
1580/*
1581 * Read one word data from the serial ROM
1582 */
1583
1584static u16 read_srom_word(long ioaddr, int offset)
1585{
1586 int i;
1587 u16 srom_data = 0;
1588 long cr9_ioaddr = ioaddr + DCR9;
1589
1590 outl(CR9_SROM_READ, cr9_ioaddr);
1591 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1592
1593 /* Send the Read Command 110b */
1594 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1595 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1596 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1597
1598 /* Send the offset */
1599 for (i = 5; i >= 0; i--) {
1600 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1601 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1602 }
1603
1604 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1605
1606 for (i = 16; i > 0; i--) {
1607 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1608 udelay(5);
f67ba792
ML		 1609 srom_data = (srom_data << 1) |
1610 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1da177e4
LT		 1611 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1612 udelay(5);
1613 }
1614
1615 outl(CR9_SROM_READ, cr9_ioaddr);
1616 return srom_data;
1617}
1618
1619
1620/*
1621 * Auto sense the media mode
1622 */
1623
1624static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1625{
1626 u8 ErrFlag = 0;
1627 u16 phy_mode;
1628
1629 /* CR6 bit18=0, select 10/100M */
1630 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1631
1632 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1633 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1634
1635 if ( (phy_mode & 0x24) == 0x24 ) {
1636 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
f67ba792
ML		 1637 phy_mode = phy_read(db->ioaddr,
1638 db->phy_addr, 7, db->chip_id) & 0xf000;
1da177e4 1639 else /* DM9102/DM9102A */
f67ba792
ML		 1640 phy_mode = phy_read(db->ioaddr,
1641 db->phy_addr, 17, db->chip_id) & 0xf000;
dde7c8ef 1642 pr_debug("Phy_mode %x\n", phy_mode);
1da177e4
LT		 1643 switch (phy_mode) {
1644 case 0x1000: db->op_mode = DMFE_10MHF; break;
1645 case 0x2000: db->op_mode = DMFE_10MFD; break;
1646 case 0x4000: db->op_mode = DMFE_100MHF; break;
1647 case 0x8000: db->op_mode = DMFE_100MFD; break;
1648 default: db->op_mode = DMFE_10MHF;
1649 ErrFlag = 1;
1650 break;
1651 }
1652 } else {
1653 db->op_mode = DMFE_10MHF;
1654 DMFE_DBUG(0, "Link Failed :", phy_mode);
1655 ErrFlag = 1;
1656 }
1657
1658 return ErrFlag;
1659}
1660
1661
1662/*
1663 * Set 10/100 phyxcer capability
1664 * AUTO mode : phyxcer register4 is NIC capability
1665 * Force mode: phyxcer register4 is the force media
1666 */
1667
1668static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1669{
1670 u16 phy_reg;
1671
1672 /* Select 10/100M phyxcer */
1673 db->cr6_data &= ~0x40000;
1674 update_cr6(db->cr6_data, db->ioaddr);
1675
1676 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1677 if (db->chip_id == PCI_DM9009_ID) {
f67ba792
ML		 1678 phy_reg = phy_read(db->ioaddr,
1679 db->phy_addr, 18, db->chip_id) & ~0x1000;
1680
1681 phy_write(db->ioaddr,
1682 db->phy_addr, 18, phy_reg, db->chip_id);
1da177e4
LT		 1683 }
1684
1685 /* Phyxcer capability setting */
1686 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1687
1688 if (db->media_mode & DMFE_AUTO) {
1689 /* AUTO Mode */
1690 phy_reg |= db->PHY_reg4;
1691 } else {
1692 /* Force Mode */
1693 switch(db->media_mode) {
1694 case DMFE_10MHF: phy_reg |= 0x20; break;
1695 case DMFE_10MFD: phy_reg |= 0x40; break;
1696 case DMFE_100MHF: phy_reg |= 0x80; break;
1697 case DMFE_100MFD: phy_reg |= 0x100; break;
1698 }
1699 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1700 }
1701
1702 /* Write new capability to Phyxcer Reg4 */
1703 if ( !(phy_reg & 0x01e0)) {
1704 phy_reg|=db->PHY_reg4;
1705 db->media_mode|=DMFE_AUTO;
1706 }
1707 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1708
1709 /* Restart Auto-Negotiation */
1710 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1711 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1712 if ( !db->chip_type )
1713 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1714}
1715
1716
1717/*
1718 * Process op-mode
1719 * AUTO mode : PHY controller in Auto-negotiation Mode
1720 * Force mode: PHY controller in force mode with HUB
1721 * N-way force capability with SWITCH
1722 */
1723
1724static void dmfe_process_mode(struct dmfe_board_info *db)
1725{
1726 u16 phy_reg;
1727
1728 /* Full Duplex Mode Check */
1729 if (db->op_mode & 0x4)
1730 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1731 else
1732 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1733
1734 /* Transciver Selection */
1735 if (db->op_mode & 0x10) /* 1M HomePNA */
1736 db->cr6_data |= 0x40000;/* External MII select */
1737 else
1738 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1739
1740 update_cr6(db->cr6_data, db->ioaddr);
1741
1742 /* 10/100M phyxcer force mode need */
1743 if ( !(db->media_mode & 0x18)) {
1744 /* Forece Mode */
1745 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1746 if ( !(phy_reg & 0x1) ) {
1747 /* parter without N-Way capability */
1748 phy_reg = 0x0;
1749 switch(db->op_mode) {
1750 case DMFE_10MHF: phy_reg = 0x0; break;
1751 case DMFE_10MFD: phy_reg = 0x100; break;
1752 case DMFE_100MHF: phy_reg = 0x2000; break;
1753 case DMFE_100MFD: phy_reg = 0x2100; break;
1754 }
f67ba792
ML		 1755 phy_write(db->ioaddr,
1756 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1757 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1758 mdelay(20);
f67ba792
ML		 1759 phy_write(db->ioaddr,
1760 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1761 }
1762 }
1763}
1764
1765
1766/*
1767 * Write a word to Phy register
1768 */
1769
f67ba792
ML		 1770static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1771 u16 phy_data, u32 chip_id)
1da177e4
LT		 1772{
1773 u16 i;
1774 unsigned long ioaddr;
1775
1776 if (chip_id == PCI_DM9132_ID) {
1777 ioaddr = iobase + 0x80 + offset * 4;
1778 outw(phy_data, ioaddr);
1779 } else {
1780 /* DM9102/DM9102A Chip */
1781 ioaddr = iobase + DCR9;
1782
1783 /* Send 33 synchronization clock to Phy controller */
1784 for (i = 0; i < 35; i++)
1785 phy_write_1bit(ioaddr, PHY_DATA_1);
1786
1787 /* Send start command(01) to Phy */
1788 phy_write_1bit(ioaddr, PHY_DATA_0);
1789 phy_write_1bit(ioaddr, PHY_DATA_1);
1790
1791 /* Send write command(01) to Phy */
1792 phy_write_1bit(ioaddr, PHY_DATA_0);
1793 phy_write_1bit(ioaddr, PHY_DATA_1);
1794
1795 /* Send Phy address */
1796 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1797 phy_write_1bit(ioaddr,
1798 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1799
1800 /* Send register address */
1801 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1802 phy_write_1bit(ioaddr,
1803 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1804
1805 /* written trasnition */
1806 phy_write_1bit(ioaddr, PHY_DATA_1);
1807 phy_write_1bit(ioaddr, PHY_DATA_0);
1808
1809 /* Write a word data to PHY controller */
1810 for ( i = 0x8000; i > 0; i >>= 1)
f67ba792
ML		 1811 phy_write_1bit(ioaddr,
1812 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1813 }
1814}
1815
1816
1817/*
1818 * Read a word data from phy register
1819 */
1820
1821static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1822{
1823 int i;
1824 u16 phy_data;
1825 unsigned long ioaddr;
1826
1827 if (chip_id == PCI_DM9132_ID) {
1828 /* DM9132 Chip */
1829 ioaddr = iobase + 0x80 + offset * 4;
1830 phy_data = inw(ioaddr);
1831 } else {
1832 /* DM9102/DM9102A Chip */
1833 ioaddr = iobase + DCR9;
1834
1835 /* Send 33 synchronization clock to Phy controller */
1836 for (i = 0; i < 35; i++)
1837 phy_write_1bit(ioaddr, PHY_DATA_1);
1838
1839 /* Send start command(01) to Phy */
1840 phy_write_1bit(ioaddr, PHY_DATA_0);
1841 phy_write_1bit(ioaddr, PHY_DATA_1);
1842
1843 /* Send read command(10) to Phy */
1844 phy_write_1bit(ioaddr, PHY_DATA_1);
1845 phy_write_1bit(ioaddr, PHY_DATA_0);
1846
1847 /* Send Phy address */
1848 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1849 phy_write_1bit(ioaddr,
1850 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1851
1852 /* Send register address */
1853 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1854 phy_write_1bit(ioaddr,
1855 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1856
1857 /* Skip transition state */
1858 phy_read_1bit(ioaddr);
1859
1860 /* read 16bit data */
1861 for (phy_data = 0, i = 0; i < 16; i++) {
1862 phy_data <<= 1;
1863 phy_data |= phy_read_1bit(ioaddr);
1864 }
1865 }
1866
1867 return phy_data;
1868}
1869
1870
1871/*
1872 * Write one bit data to Phy Controller
1873 */
1874
1875static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1876{
1877 outl(phy_data, ioaddr); /* MII Clock Low */
1878 udelay(1);
1879 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1880 udelay(1);
1881 outl(phy_data, ioaddr); /* MII Clock Low */
1882 udelay(1);
1883}
1884
1885
1886/*
1887 * Read one bit phy data from PHY controller
1888 */
1889
1890static u16 phy_read_1bit(unsigned long ioaddr)
1891{
1892 u16 phy_data;
1893
1894 outl(0x50000, ioaddr);
1895 udelay(1);
1896 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1897 outl(0x40000, ioaddr);
1898 udelay(1);
1899
1900 return phy_data;
1901}
1902
1903
1904/*
1905 * Parser SROM and media mode
1906 */
1907
1908static void dmfe_parse_srom(struct dmfe_board_info * db)
1909{
1910 char * srom = db->srom;
1911 int dmfe_mode, tmp_reg;
1912
1913 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1914
1915 /* Init CR15 */
1916 db->cr15_data = CR15_DEFAULT;
1917
1918 /* Check SROM Version */
1919 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1920 /* SROM V4.01 */
1921 /* Get NIC support media mode */
4c93566e 1922 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1da177e4
LT		 1923 db->PHY_reg4 = 0;
1924 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1925 switch( db->NIC_capability & tmp_reg ) {
1926 case 0x1: db->PHY_reg4 |= 0x0020; break;
1927 case 0x2: db->PHY_reg4 |= 0x0040; break;
1928 case 0x4: db->PHY_reg4 |= 0x0080; break;
1929 case 0x8: db->PHY_reg4 |= 0x0100; break;
1930 }
1931 }
1932
1933 /* Media Mode Force or not check */
4c93566e
DM		 1934 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1935 le32_to_cpup((__le32 *) (srom + 36)));
1da177e4
LT		 1936 switch(dmfe_mode) {
1937 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1938 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1939 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1940 case 0x100:
1941 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1942 }
1943
1944 /* Special Function setting */
1945 /* VLAN function */
1946 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1947 db->cr15_data |= 0x40;
1948
1949 /* Flow Control */
1950 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1951 db->cr15_data |= 0x400;
1952
1953 /* TX pause packet */
1954 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1955 db->cr15_data |= 0x9800;
1956 }
1957
1958 /* Parse HPNA parameter */
1959 db->HPNA_command = 1;
1960
1961 /* Accept remote command or not */
1962 if (HPNA_rx_cmd == 0)
1963 db->HPNA_command |= 0x8000;
1964
1965 /* Issue remote command & operation mode */
1966 if (HPNA_tx_cmd == 1)
1967 switch(HPNA_mode) { /* Issue Remote Command */
1968 case 0: db->HPNA_command |= 0x0904; break;
1969 case 1: db->HPNA_command |= 0x0a00; break;
1970 case 2: db->HPNA_command |= 0x0506; break;
1971 case 3: db->HPNA_command |= 0x0602; break;
1972 }
1973 else
1974 switch(HPNA_mode) { /* Don't Issue */
1975 case 0: db->HPNA_command |= 0x0004; break;
1976 case 1: db->HPNA_command |= 0x0000; break;
1977 case 2: db->HPNA_command |= 0x0006; break;
1978 case 3: db->HPNA_command |= 0x0002; break;
1979 }
1980
1981 /* Check DM9801 or DM9802 present or not */
1982 db->HPNA_present = 0;
1983 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1984 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1985 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1986 /* DM9801 or DM9802 present */
1987 db->HPNA_timer = 8;
1988 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1989 /* DM9801 HomeRun */
1990 db->HPNA_present = 1;
1991 dmfe_program_DM9801(db, tmp_reg);
1992 } else {
1993 /* DM9802 LongRun */
1994 db->HPNA_present = 2;
1995 dmfe_program_DM9802(db);
1996 }
1997 }
1998
1999}
2000
2001
2002/*
2003 * Init HomeRun DM9801
2004 */
2005
2006static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2007{
2008 uint reg17, reg25;
2009
2010 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2011 switch(HPNA_rev) {
2012 case 0xb900: /* DM9801 E3 */
2013 db->HPNA_command |= 0x1000;
2014 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2015 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2016 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2017 break;
2018 case 0xb901: /* DM9801 E4 */
2019 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2020 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2021 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2022 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2023 break;
2024 case 0xb902: /* DM9801 E5 */
2025 case 0xb903: /* DM9801 E6 */
2026 default:
2027 db->HPNA_command |= 0x1000;
2028 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2029 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2030 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2031 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2032 break;
2033 }
2034 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2035 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2036 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2037}
2038
2039
2040/*
2041 * Init HomeRun DM9802
2042 */
2043
2044static void dmfe_program_DM9802(struct dmfe_board_info * db)
2045{
2046 uint phy_reg;
2047
2048 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2049 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2050 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2051 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2052 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2053}
2054
2055
2056/*
2057 * Check remote HPNA power and speed status. If not correct,
2058 * issue command again.
2059*/
2060
2061static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2062{
2063 uint phy_reg;
2064
2065 /* Got remote device status */
2066 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2067 switch(phy_reg) {
2068 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2069 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2070 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2071 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2072 }
2073
2074 /* Check remote device status match our setting ot not */
2075 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
f67ba792
ML		 2076 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2077 db->chip_id);
1da177e4
LT		 2078 db->HPNA_timer=8;
2079 } else
2080 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2081}
2082
2083
2084
a3aa1884 2085static DEFINE_PCI_DEVICE_TABLE(dmfe_pci_tbl) = {
1da177e4
LT		 2086 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2087 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2088 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2089 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2090 { 0, }
2091};
2092MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2093
2094
bc8a8387
ML		 2095#ifdef CONFIG_PM
2096static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2097{
2098 struct net_device *dev = pci_get_drvdata(pci_dev);
2099 struct dmfe_board_info *db = netdev_priv(dev);
f1069046 2100 u32 tmp;
bc8a8387
ML		 2101
2102 /* Disable upper layer interface */
2103 netif_device_detach(dev);
2104
2105 /* Disable Tx/Rx */
2106 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2107 update_cr6(db->cr6_data, dev->base_addr);
2108
2109 /* Disable Interrupt */
2110 outl(0, dev->base_addr + DCR7);
2111 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2112
2113 /* Fre RX buffers */
2114 dmfe_free_rxbuffer(db);
2115
f1069046
ML		 2116 /* Enable WOL */
2117 pci_read_config_dword(pci_dev, 0x40, &tmp);
2118 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2119
2120 if (db->wol_mode & WAKE_PHY)
2121 tmp |= DMFE_WOL_LINKCHANGE;
2122 if (db->wol_mode & WAKE_MAGIC)
2123 tmp |= DMFE_WOL_MAGICPACKET;
2124
2125 pci_write_config_dword(pci_dev, 0x40, tmp);
2126
2127 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2128 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2129
bc8a8387 2130 /* Power down device*/
bc8a8387 2131 pci_save_state(pci_dev);
a31e23e1 2132 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
bc8a8387
ML		 2133
2134 return 0;
2135}
2136
2137static int dmfe_resume(struct pci_dev *pci_dev)
2138{
2139 struct net_device *dev = pci_get_drvdata(pci_dev);
f1069046 2140 u32 tmp;
bc8a8387 2141
bc8a8387 2142 pci_set_power_state(pci_dev, PCI_D0);
65809b51 2143 pci_restore_state(pci_dev);
bc8a8387 2144
421f91d2 2145 /* Re-initialize DM910X board */
bc8a8387
ML		 2146 dmfe_init_dm910x(dev);
2147
f1069046
ML		 2148 /* Disable WOL */
2149 pci_read_config_dword(pci_dev, 0x40, &tmp);
2150
2151 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2152 pci_write_config_dword(pci_dev, 0x40, tmp);
2153
2154 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2155 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2156
bc8a8387
ML		 2157 /* Restart upper layer interface */
2158 netif_device_attach(dev);
2159
2160 return 0;
2161}
2162#else
2163#define dmfe_suspend NULL
2164#define dmfe_resume NULL
2165#endif
2166
1da177e4
LT		 2167static struct pci_driver dmfe_driver = {
2168 .name = "dmfe",
2169 .id_table = dmfe_pci_tbl,
2170 .probe = dmfe_init_one,
2171 .remove = __devexit_p(dmfe_remove_one),
bc8a8387
ML		 2172 .suspend = dmfe_suspend,
2173 .resume = dmfe_resume
1da177e4
LT		 2174};
2175
2176MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2177MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2178MODULE_LICENSE("GPL");
2179MODULE_VERSION(DRV_VERSION);
2180
2181module_param(debug, int, 0);
2182module_param(mode, byte, 0);
2183module_param(cr6set, int, 0);
2184module_param(chkmode, byte, 0);
2185module_param(HPNA_mode, byte, 0);
2186module_param(HPNA_rx_cmd, byte, 0);
2187module_param(HPNA_tx_cmd, byte, 0);
2188module_param(HPNA_NoiseFloor, byte, 0);
2189module_param(SF_mode, byte, 0);
2190MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
f67ba792
ML		 2191MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2192 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2193
2194MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2195 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
1da177e4
LT		 2196
2197/* Description:
2198 * when user used insmod to add module, system invoked init_module()
421f91d2 2199 * to initialize and register.
1da177e4
LT		 2200 */
2201
2202static int __init dmfe_init_module(void)
2203{
2204 int rc;
2205
2206 printk(version);
2207 printed_version = 1;
2208
2209 DMFE_DBUG(0, "init_module() ", debug);
2210
2211 if (debug)
2212 dmfe_debug = debug; /* set debug flag */
2213 if (cr6set)
2214 dmfe_cr6_user_set = cr6set;
2215
2216 switch(mode) {
2217 case DMFE_10MHF:
2218 case DMFE_100MHF:
2219 case DMFE_10MFD:
2220 case DMFE_100MFD:
2221 case DMFE_1M_HPNA:
2222 dmfe_media_mode = mode;
2223 break;
2224 default:dmfe_media_mode = DMFE_AUTO;
2225 break;
2226 }
2227
2228 if (HPNA_mode > 4)
2229 HPNA_mode = 0; /* Default: LP/HS */
2230 if (HPNA_rx_cmd > 1)
2231 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2232 if (HPNA_tx_cmd > 1)
2233 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2234 if (HPNA_NoiseFloor > 15)
2235 HPNA_NoiseFloor = 0;
2236
29917620 2237 rc = pci_register_driver(&dmfe_driver);
1da177e4
LT		 2238 if (rc < 0)
2239 return rc;
2240
2241 return 0;
2242}
2243
2244
2245/*
2246 * Description:
2247 * when user used rmmod to delete module, system invoked clean_module()
2248 * to un-register all registered services.
2249 */
2250
2251static void __exit dmfe_cleanup_module(void)
2252{
2253 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2254 pci_unregister_driver(&dmfe_driver);
2255}
2256
2257module_init(dmfe_init_module);
2258module_exit(dmfe_cleanup_module);
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