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1da177e4
LT		 1/* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
f3b197ac
JG		 44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
1da177e4
LT		 49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
f3b197ac 58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
1da177e4
LT		 59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
f3b197ac 109 hh = device number
1da177e4
LT		 110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
f3b197ac
JG		 123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
1da177e4
LT		 125 7) enjoy!
126
f3b197ac 127 To unload a module, turn off the associated interface(s)
1da177e4
LT		 128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
f3b197ac 138 'dec_only=1' parameter.
1da177e4
LT		 139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
f3b197ac 207 autosense to set the media/speed; with the following
1da177e4
LT		 208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
f3b197ac 238 TO DO:
1da177e4
LT		 239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
f3b197ac 245
1da177e4
LT		 246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
f3b197ac 254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
1da177e4
LT		 255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
f3b197ac 283 Add new autosense algorithms for media/mode
1da177e4
LT		 284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
1fb9df5d 295 Duh, put the IRQF_SHARED flag into request_interrupt().
1da177e4
LT		 296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
f3b197ac 310 reported by <koen.gadeyne@barco.com> and
1da177e4
LT		 311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
f3b197ac 313 reported by <csd@microplex.com> and
1da177e4
LT		 314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
f3b197ac 325 0.45 8-Dec-96 Include endian functions for PPC use, from work
1da177e4
LT		 326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
f3b197ac
JG		 349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
1da177e4
LT		 351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
1fb9df5d 356 Added IRQF_DISABLED temporary fix from
1da177e4
LT		 357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
f3b197ac 366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
1da177e4
LT		 367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
f3b197ac 369 problem reports by
1da177e4
LT		 370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
f3b197ac 377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
1da177e4
LT		 378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
f3b197ac 401 Fix is_anc_capable() bug reported by
1da177e4
LT		 402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
f3b197ac 416 kernels and modules from bug report by
1da177e4
LT		 417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
f3b197ac 428 0.545 28-Nov-99 Further Moto SROM bug fix from
1da177e4
LT		 429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
f3b197ac
JG		 437 present.
438 <france@handhelds.org>
1da177e4
LT		 439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444*/
445
1da177e4
LT		 446#include <linux/module.h>
447#include <linux/kernel.h>
448#include <linux/string.h>
449#include <linux/interrupt.h>
450#include <linux/ptrace.h>
451#include <linux/errno.h>
452#include <linux/ioport.h>
453#include <linux/slab.h>
454#include <linux/pci.h>
455#include <linux/eisa.h>
456#include <linux/delay.h>
457#include <linux/init.h>
458#include <linux/spinlock.h>
459#include <linux/crc32.h>
460#include <linux/netdevice.h>
461#include <linux/etherdevice.h>
462#include <linux/skbuff.h>
463#include <linux/time.h>
464#include <linux/types.h>
465#include <linux/unistd.h>
466#include <linux/ctype.h>
467#include <linux/dma-mapping.h>
468#include <linux/moduleparam.h>
469#include <linux/bitops.h>
470
471#include <asm/io.h>
472#include <asm/dma.h>
473#include <asm/byteorder.h>
474#include <asm/unaligned.h>
475#include <asm/uaccess.h>
bfaadcad 476#ifdef CONFIG_PPC_PMAC
1da177e4 477#include <asm/machdep.h>
bfaadcad 478#endif /* CONFIG_PPC_PMAC */
1da177e4
LT		 479
480#include "de4x5.h"
481
03f54b3d 482static const char version[] __devinitconst =
65d9b8b1 483 KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
1da177e4
LT		 484
485#define c_char const char
1da177e4
LT		 486
487/*
488** MII Information
489*/
490struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499};
500
501struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
7f927fcc 515 u_int fdx; /* Full DupleX capabilities for each media */
1da177e4
LT		 516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518};
519
520#define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
521
522struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530};
531
532/*
533** Define the know universe of PHY devices that can be
534** recognised by this driver.
535*/
536static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542};
543
544/*
545** These GENERIC values assumes that the PHY devices follow 802.3u and
546** allow parallel detection to set the link partner ability register.
547** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548*/
549#define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550#define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551#define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553/*
554** Define special SROM detection cases
555*/
556static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559};
560
561#define SMC 1
562#define ACCTON 2
563
564/*
565** SROM Repair definitions. If a broken SROM is detected a card may
566** use this information to help figure out what to do. This is a
567** "stab in the dark" and so far for SMC9332's only.
568*/
569static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574};
575
576
577#ifdef DE4X5_DEBUG
578static int de4x5_debug = DE4X5_DEBUG;
579#else
580/*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582#endif
583
584/*
585** Allow per adapter set up. For modules this is simply a command line
f3b197ac 586** parameter, e.g.:
1da177e4
LT		 587** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588**
589** For a compiled in driver, place e.g.
590** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591** here
592*/
593#ifdef DE4X5_PARM
594static char *args = DE4X5_PARM;
595#else
596static char *args;
597#endif
598
599struct parameters {
eb034a79 600 bool fdx;
1da177e4
LT		 601 int autosense;
602};
603
604#define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606#define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608/*
609** Ethernet PROM defines
610*/
611#define PROBE_LENGTH 32
612#define ETH_PROM_SIG 0xAA5500FFUL
613
614/*
615** Ethernet Info
616*/
617#define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618#define IEEE802_3_SZ 1518 /* Packet + CRC */
619#define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620#define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621#define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622#define PKT_HDR_LEN 14 /* Addresses and data length info */
623#define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624#define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627/*
628** EISA bus defines
629*/
630#define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631#define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633#define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636#define DE4X5_NAME_LENGTH 8
637
638static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640/*
641** Ethernet PROM defines for DC21040
642*/
643#define PROBE_LENGTH 32
644#define ETH_PROM_SIG 0xAA5500FFUL
645
646/*
647** PCI Bus defines
648*/
649#define PCI_MAX_BUS_NUM 8
650#define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651#define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653/*
654** Memory Alignment. Each descriptor is 4 longwords long. To force a
655** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656** DESC_ALIGN. ALIGN aligns the start address of the private memory area
f3b197ac 657** and hence the RX descriptor ring's first entry.
1da177e4
LT		 658*/
659#define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660#define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661#define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662#define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663#define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664#define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666#define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667#define DE4X5_CACHE_ALIGN CAL_16LONG
668#define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669/*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670#define DESC_ALIGN
671
672#ifndef DEC_ONLY /* See README.de4x5 for using this */
673static int dec_only;
674#else
675static int dec_only = 1;
676#endif
677
678/*
679** DE4X5 IRQ ENABLE/DISABLE
680*/
681#define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684}
685
686#define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690}
691
692#define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695}
696
697#define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701}
702
703/*
704** DE4X5 START/STOP
705*/
706#define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710}
711
712#define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716}
717
718/*
719** DE4X5 SIA RESET
720*/
721#define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723/*
724** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725*/
726#define DE4X5_AUTOSENSE_MS 250
727
728/*
729** SROM Structure
730*/
731struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742};
743#define SUB_VENDOR_ID 0x500a
744
745/*
746** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747** and have sizes of both a power of 2 and a multiple of 4.
748** A size of 256 bytes for each buffer could be chosen because over 90% of
749** all packets in our network are <256 bytes long and 64 longword alignment
750** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751** descriptors are needed for machines with an ALPHA CPU.
752*/
753#define NUM_RX_DESC 8 /* Number of RX descriptors */
754#define NUM_TX_DESC 32 /* Number of TX descriptors */
755#define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758struct de4x5_desc {
c559a5bc
AV		 759 volatile __le32 status;
760 __le32 des1;
761 __le32 buf;
762 __le32 next;
1da177e4
LT		 763 DESC_ALIGN
764};
765
766/*
767** The DE4X5 private structure
768*/
769#define DE4X5_PKT_STAT_SZ 16
770#define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785};
786
787struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
eb034a79 812 bool fdx; /* media full duplex flag */
1da177e4
LT		 813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
eb034a79 815 bool tx_enable; /* Enable descriptor polling */
1da177e4
LT		 816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
2aad7c8e 836 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
1da177e4
LT		 837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
eb034a79
RK		 841 bool useSROM; /* For non-DEC card use SROM */
842 bool useMII; /* Infoblock using the MII */
1da177e4
LT		 843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860};
861
862/*
863** To get around certain poxy cards that don't provide an SROM
864** for the second and more DECchip, I have to key off the first
865** chip's address. I'll assume there's not a bad SROM iff:
866**
867** o the chipset is the same
868** o the bus number is the same and > 0
869** o the sum of all the returned hw address bytes is 0 or 0x5fa
870**
871** Also have to save the irq for those cards whose hardware designers
872** can't follow the PCI to PCI Bridge Architecture spec.
873*/
874static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879} last = {0,};
880
881/*
882** The transmit ring full condition is described by the tx_old and tx_new
883** pointers by:
884** tx_old = tx_new Empty ring
885** tx_old = tx_new+1 Full ring
886** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887*/
888#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894/*
895** Public Functions
896*/
897static int de4x5_open(struct net_device *dev);
ad096463
SH		 898static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
899 struct net_device *dev);
7d12e780 900static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
1da177e4
LT		 901static int de4x5_close(struct net_device *dev);
902static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904static void set_multicast_list(struct net_device *dev);
905static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
906
907/*
908** Private functions
909*/
910static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911static int de4x5_init(struct net_device *dev);
912static int de4x5_sw_reset(struct net_device *dev);
913static int de4x5_rx(struct net_device *dev);
914static int de4x5_tx(struct net_device *dev);
561b4fbf 915static void de4x5_ast(struct net_device *dev);
1da177e4
LT		 916static int de4x5_txur(struct net_device *dev);
917static int de4x5_rx_ovfc(struct net_device *dev);
918
919static int autoconf_media(struct net_device *dev);
920static void create_packet(struct net_device *dev, char *frame, int len);
921static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922static int dc21040_autoconf(struct net_device *dev);
923static int dc21041_autoconf(struct net_device *dev);
924static int dc21140m_autoconf(struct net_device *dev);
925static int dc2114x_autoconf(struct net_device *dev);
926static int srom_autoconf(struct net_device *dev);
927static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930static int test_for_100Mb(struct net_device *dev, int msec);
931static int wait_for_link(struct net_device *dev);
eb034a79 932static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
1da177e4
LT		 933static int is_spd_100(struct net_device *dev);
934static int is_100_up(struct net_device *dev);
935static int is_10_up(struct net_device *dev);
936static int is_anc_capable(struct net_device *dev);
937static int ping_media(struct net_device *dev, int msec);
938static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939static void de4x5_free_rx_buffs(struct net_device *dev);
940static void de4x5_free_tx_buffs(struct net_device *dev);
941static void de4x5_save_skbs(struct net_device *dev);
942static void de4x5_rst_desc_ring(struct net_device *dev);
943static void de4x5_cache_state(struct net_device *dev, int flag);
944static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947static void de4x5_setup_intr(struct net_device *dev);
948static void de4x5_init_connection(struct net_device *dev);
949static int de4x5_reset_phy(struct net_device *dev);
950static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952static int test_tp(struct net_device *dev, s32 msec);
953static int EISA_signature(char *name, struct device *device);
954static int PCI_signature(char *name, struct de4x5_private *lp);
955static void DevicePresent(struct net_device *dev, u_long iobase);
956static void enet_addr_rst(u_long aprom_addr);
957static int de4x5_bad_srom(struct de4x5_private *lp);
958static short srom_rd(u_long address, u_char offset);
959static void srom_latch(u_int command, u_long address);
960static void srom_command(u_int command, u_long address);
961static void srom_address(u_int command, u_long address, u_char offset);
962static short srom_data(u_int command, u_long address);
963/*static void srom_busy(u_int command, u_long address);*/
964static void sendto_srom(u_int command, u_long addr);
965static int getfrom_srom(u_long addr);
966static int srom_map_media(struct net_device *dev);
967static int srom_infoleaf_info(struct net_device *dev);
968static void srom_init(struct net_device *dev);
969static void srom_exec(struct net_device *dev, u_char *p);
970static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972static int mii_rdata(u_long ioaddr);
973static void mii_wdata(int data, int len, u_long ioaddr);
974static void mii_ta(u_long rw, u_long ioaddr);
975static int mii_swap(int data, int len);
976static void mii_address(u_char addr, u_long ioaddr);
977static void sendto_mii(u32 command, int data, u_long ioaddr);
978static int getfrom_mii(u32 command, u_long ioaddr);
979static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980static int mii_get_phy(struct net_device *dev);
981static void SetMulticastFilter(struct net_device *dev);
982static int get_hw_addr(struct net_device *dev);
983static void srom_repair(struct net_device *dev, int card);
984static int test_bad_enet(struct net_device *dev, int status);
985static int an_exception(struct de4x5_private *lp);
986static char *build_setup_frame(struct net_device *dev, int mode);
987static void disable_ast(struct net_device *dev);
1da177e4
LT		 988static long de4x5_switch_mac_port(struct net_device *dev);
989static int gep_rd(struct net_device *dev);
990static void gep_wr(s32 data, struct net_device *dev);
1da177e4
LT		 991static void yawn(struct net_device *dev, int state);
992static void de4x5_parse_params(struct net_device *dev);
993static void de4x5_dbg_open(struct net_device *dev);
994static void de4x5_dbg_mii(struct net_device *dev, int k);
995static void de4x5_dbg_media(struct net_device *dev);
996static void de4x5_dbg_srom(struct de4x5_srom *p);
997static void de4x5_dbg_rx(struct sk_buff *skb, int len);
998static int de4x5_strncmp(char *a, char *b, int n);
999static int dc21041_infoleaf(struct net_device *dev);
1000static int dc21140_infoleaf(struct net_device *dev);
1001static int dc21142_infoleaf(struct net_device *dev);
1002static int dc21143_infoleaf(struct net_device *dev);
1003static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1004static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1005static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1006static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1007static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1008static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1009static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1010
1011/*
1012** Note now that module autoprobing is allowed under EISA and PCI. The
1013** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1014** to "do the right thing".
1015*/
1016
1017static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1018
1019module_param(io, int, 0);
1020module_param(de4x5_debug, int, 0);
1021module_param(dec_only, int, 0);
1022module_param(args, charp, 0);
1023
1024MODULE_PARM_DESC(io, "de4x5 I/O base address");
1025MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1026MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1027MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1028MODULE_LICENSE("GPL");
1029
1030/*
1031** List the SROM infoleaf functions and chipsets
1032*/
1033struct InfoLeaf {
1034 int chipset;
1035 int (*fn)(struct net_device *);
1036};
1037static struct InfoLeaf infoleaf_array[] = {
1038 {DC21041, dc21041_infoleaf},
1039 {DC21140, dc21140_infoleaf},
1040 {DC21142, dc21142_infoleaf},
1041 {DC21143, dc21143_infoleaf}
1042};
e9edda69 1043#define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1da177e4
LT		 1044
1045/*
1046** List the SROM info block functions
1047*/
1048static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1049 type0_infoblock,
1050 type1_infoblock,
1051 type2_infoblock,
1052 type3_infoblock,
1053 type4_infoblock,
1054 type5_infoblock,
1055 compact_infoblock
1056};
1057
e9edda69 1058#define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1da177e4
LT		 1059
1060/*
1061** Miscellaneous defines...
1062*/
1063#define RESET_DE4X5 {\
1064 int i;\
1065 i=inl(DE4X5_BMR);\
1066 mdelay(1);\
1067 outl(i | BMR_SWR, DE4X5_BMR);\
1068 mdelay(1);\
1069 outl(i, DE4X5_BMR);\
1070 mdelay(1);\
1071 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1072 mdelay(1);\
1073}
1074
1075#define PHY_HARD_RESET {\
1076 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1077 mdelay(1); /* Assert for 1ms */\
1078 outl(0x00, DE4X5_GEP);\
1079 mdelay(2); /* Wait for 2ms */\
1080}
1081
0b9a5b05
SH		 1082static const struct net_device_ops de4x5_netdev_ops = {
1083 .ndo_open = de4x5_open,
1084 .ndo_stop = de4x5_close,
1085 .ndo_start_xmit = de4x5_queue_pkt,
1086 .ndo_get_stats = de4x5_get_stats,
1087 .ndo_set_multicast_list = set_multicast_list,
1088 .ndo_do_ioctl = de4x5_ioctl,
1089 .ndo_change_mtu = eth_change_mtu,
1090 .ndo_set_mac_address= eth_mac_addr,
1091 .ndo_validate_addr = eth_validate_addr,
1092};
1093
f3b197ac
JG		 1094
1095static int __devinit
1da177e4
LT		 1096de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1097{
1098 char name[DE4X5_NAME_LENGTH + 1];
1099 struct de4x5_private *lp = netdev_priv(dev);
1100 struct pci_dev *pdev = NULL;
1101 int i, status=0;
1102
1aec5bdf 1103 dev_set_drvdata(gendev, dev);
1da177e4
LT		 1104
1105 /* Ensure we're not sleeping */
1106 if (lp->bus == EISA) {
1107 outb(WAKEUP, PCI_CFPM);
1108 } else {
1109 pdev = to_pci_dev (gendev);
1110 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1111 }
1112 mdelay(10);
1113
1114 RESET_DE4X5;
f3b197ac 1115
1da177e4
LT		 1116 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1117 return -ENXIO; /* Hardware could not reset */
1118 }
f3b197ac
JG		 1119
1120 /*
1da177e4
LT		 1121 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1122 */
eb034a79 1123 lp->useSROM = false;
1da177e4
LT		 1124 if (lp->bus == PCI) {
1125 PCI_signature(name, lp);
1126 } else {
1127 EISA_signature(name, gendev);
1128 }
f3b197ac 1129
1da177e4
LT		 1130 if (*name == '\0') { /* Not found a board signature */
1131 return -ENXIO;
1132 }
f3b197ac 1133
1da177e4 1134 dev->base_addr = iobase;
fb28ad35 1135 printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
f3b197ac 1136
1da177e4 1137 status = get_hw_addr(dev);
e174961c 1138 printk(", h/w address %pM\n", dev->dev_addr);
f3b197ac 1139
1da177e4
LT		 1140 if (status != 0) {
1141 printk(" which has an Ethernet PROM CRC error.\n");
1142 return -ENXIO;
1143 } else {
2aad7c8e 1144 skb_queue_head_init(&lp->cache.queue);
1da177e4
LT		 1145 lp->cache.gepc = GEP_INIT;
1146 lp->asBit = GEP_SLNK;
1147 lp->asPolarity = GEP_SLNK;
eb034a79 1148 lp->asBitValid = ~0;
1da177e4
LT		 1149 lp->timeout = -1;
1150 lp->gendev = gendev;
1151 spin_lock_init(&lp->lock);
1152 init_timer(&lp->timer);
561b4fbf
AV		 1153 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1154 lp->timer.data = (unsigned long)dev;
1da177e4
LT		 1155 de4x5_parse_params(dev);
1156
1157 /*
1158 ** Choose correct autosensing in case someone messed up
1159 */
1160 lp->autosense = lp->params.autosense;
1161 if (lp->chipset != DC21140) {
1162 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1163 lp->params.autosense = TP;
1164 }
1165 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1166 lp->params.autosense = BNC;
1167 }
1168 }
1169 lp->fdx = lp->params.fdx;
fb28ad35 1170 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1da177e4
LT		 1171
1172 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
49345103 1173#if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1da177e4
LT		 1174 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1175#endif
1176 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1177 &lp->dma_rings, GFP_ATOMIC);
1178 if (lp->rx_ring == NULL) {
1179 return -ENOMEM;
1180 }
1181
1182 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
f3b197ac 1183
1da177e4
LT		 1184 /*
1185 ** Set up the RX descriptor ring (Intels)
f3b197ac 1186 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1da177e4 1187 */
49345103 1188#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1da177e4
LT		 1189 for (i=0; i<NUM_RX_DESC; i++) {
1190 lp->rx_ring[i].status = 0;
1191 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1192 lp->rx_ring[i].buf = 0;
1193 lp->rx_ring[i].next = 0;
1194 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1195 }
1196
1197#else
1198 {
1199 dma_addr_t dma_rx_bufs;
1200
1201 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1202 * sizeof(struct de4x5_desc);
1203 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1204 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1205 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1206 for (i=0; i<NUM_RX_DESC; i++) {
1207 lp->rx_ring[i].status = 0;
1208 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1209 lp->rx_ring[i].buf =
1210 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1211 lp->rx_ring[i].next = 0;
1212 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1213 }
1214
1215 }
1216#endif
1217
1218 barrier();
1219
1220 lp->rxRingSize = NUM_RX_DESC;
1221 lp->txRingSize = NUM_TX_DESC;
f3b197ac 1222
1da177e4
LT		 1223 /* Write the end of list marker to the descriptor lists */
1224 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1225 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1226
1227 /* Tell the adapter where the TX/RX rings are located. */
1228 outl(lp->dma_rings, DE4X5_RRBA);
1229 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1230 DE4X5_TRBA);
f3b197ac 1231
1da177e4
LT		 1232 /* Initialise the IRQ mask and Enable/Disable */
1233 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1234 lp->irq_en = IMR_NIM | IMR_AIM;
1235
1236 /* Create a loopback packet frame for later media probing */
1237 create_packet(dev, lp->frame, sizeof(lp->frame));
1238
1239 /* Check if the RX overflow bug needs testing for */
1240 i = lp->cfrv & 0x000000fe;
1241 if ((lp->chipset == DC21140) && (i == 0x20)) {
1242 lp->rx_ovf = 1;
1243 }
1244
1245 /* Initialise the SROM pointers if possible */
1246 if (lp->useSROM) {
1247 lp->state = INITIALISED;
1248 if (srom_infoleaf_info(dev)) {
1249 dma_free_coherent (gendev, lp->dma_size,
1250 lp->rx_ring, lp->dma_rings);
1251 return -ENXIO;
1252 }
1253 srom_init(dev);
1254 }
1255
1256 lp->state = CLOSED;
1257
1258 /*
1259 ** Check for an MII interface
1260 */
1261 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1262 mii_get_phy(dev);
1263 }
f3b197ac 1264
1da177e4 1265 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1da177e4
LT		 1266 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1267 }
f3b197ac 1268
1da177e4
LT		 1269 if (de4x5_debug & DEBUG_VERSION) {
1270 printk(version);
1271 }
f3b197ac 1272
1da177e4 1273 /* The DE4X5-specific entries in the device structure. */
1da177e4 1274 SET_NETDEV_DEV(dev, gendev);
0b9a5b05 1275 dev->netdev_ops = &de4x5_netdev_ops;
1da177e4 1276 dev->mem_start = 0;
f3b197ac 1277
1da177e4
LT		 1278 /* Fill in the generic fields of the device structure. */
1279 if ((status = register_netdev (dev))) {
1280 dma_free_coherent (gendev, lp->dma_size,
1281 lp->rx_ring, lp->dma_rings);
1282 return status;
1283 }
f3b197ac 1284
1da177e4
LT		 1285 /* Let the adapter sleep to save power */
1286 yawn(dev, SLEEP);
f3b197ac 1287
1da177e4
LT		 1288 return status;
1289}
1290
f3b197ac 1291
1da177e4
LT		 1292static int
1293de4x5_open(struct net_device *dev)
1294{
1295 struct de4x5_private *lp = netdev_priv(dev);
1296 u_long iobase = dev->base_addr;
1297 int i, status = 0;
1298 s32 omr;
1299
1300 /* Allocate the RX buffers */
1301 for (i=0; i<lp->rxRingSize; i++) {
1302 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1303 de4x5_free_rx_buffs(dev);
1304 return -EAGAIN;
1305 }
1306 }
1307
1308 /*
1309 ** Wake up the adapter
1310 */
1311 yawn(dev, WAKEUP);
1312
f3b197ac
JG		 1313 /*
1314 ** Re-initialize the DE4X5...
1da177e4
LT		 1315 */
1316 status = de4x5_init(dev);
1317 spin_lock_init(&lp->lock);
1318 lp->state = OPEN;
1319 de4x5_dbg_open(dev);
f3b197ac 1320
561b4fbf 1321 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1da177e4
LT		 1322 lp->adapter_name, dev)) {
1323 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1fb9df5d 1324 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1da177e4
LT		 1325 lp->adapter_name, dev)) {
1326 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1327 disable_ast(dev);
1328 de4x5_free_rx_buffs(dev);
1329 de4x5_free_tx_buffs(dev);
1330 yawn(dev, SLEEP);
1331 lp->state = CLOSED;
1332 return -EAGAIN;
1333 } else {
1334 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1335 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1336 }
1337 }
1338
1339 lp->interrupt = UNMASK_INTERRUPTS;
1340 dev->trans_start = jiffies;
f3b197ac 1341
1da177e4 1342 START_DE4X5;
f3b197ac 1343
1da177e4 1344 de4x5_setup_intr(dev);
f3b197ac 1345
1da177e4
LT		 1346 if (de4x5_debug & DEBUG_OPEN) {
1347 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1348 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1349 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1350 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1351 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1352 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1353 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1354 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1355 }
f3b197ac 1356
1da177e4
LT		 1357 return status;
1358}
1359
1360/*
1361** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1362** DC21140 requires using perfect filtering mode for that chip. Since I can't
1363** see why I'd want > 14 multicast addresses, I have changed all chips to use
1364** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1365** to be data corruption problems if it is larger (UDP errors seen from a
1366** ttcp source).
1367*/
1368static int
1369de4x5_init(struct net_device *dev)
f3b197ac 1370{
1da177e4
LT		 1371 /* Lock out other processes whilst setting up the hardware */
1372 netif_stop_queue(dev);
f3b197ac 1373
1da177e4 1374 de4x5_sw_reset(dev);
f3b197ac 1375
1da177e4
LT		 1376 /* Autoconfigure the connected port */
1377 autoconf_media(dev);
f3b197ac 1378
1da177e4
LT		 1379 return 0;
1380}
1381
1382static int
1383de4x5_sw_reset(struct net_device *dev)
1384{
1385 struct de4x5_private *lp = netdev_priv(dev);
1386 u_long iobase = dev->base_addr;
1387 int i, j, status = 0;
1388 s32 bmr, omr;
f3b197ac 1389
1da177e4
LT		 1390 /* Select the MII or SRL port now and RESET the MAC */
1391 if (!lp->useSROM) {
1392 if (lp->phy[lp->active].id != 0) {
1393 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1394 } else {
1395 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1396 }
1397 de4x5_switch_mac_port(dev);
1398 }
1399
f3b197ac 1400 /*
1da177e4
LT		 1401 ** Set the programmable burst length to 8 longwords for all the DC21140
1402 ** Fasternet chips and 4 longwords for all others: DMA errors result
1403 ** without these values. Cache align 16 long.
1404 */
1405 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1406 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1407 outl(bmr, DE4X5_BMR);
1408
1409 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1410 if (lp->chipset == DC21140) {
1411 omr |= (OMR_SDP | OMR_SB);
1412 }
1413 lp->setup_f = PERFECT;
1414 outl(lp->dma_rings, DE4X5_RRBA);
1415 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1416 DE4X5_TRBA);
f3b197ac 1417
1da177e4
LT		 1418 lp->rx_new = lp->rx_old = 0;
1419 lp->tx_new = lp->tx_old = 0;
f3b197ac 1420
1da177e4
LT		 1421 for (i = 0; i < lp->rxRingSize; i++) {
1422 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1423 }
f3b197ac 1424
1da177e4
LT		 1425 for (i = 0; i < lp->txRingSize; i++) {
1426 lp->tx_ring[i].status = cpu_to_le32(0);
1427 }
f3b197ac 1428
1da177e4
LT		 1429 barrier();
1430
1431 /* Build the setup frame depending on filtering mode */
1432 SetMulticastFilter(dev);
f3b197ac 1433
1da177e4
LT		 1434 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1435 outl(omr|OMR_ST, DE4X5_OMR);
1436
1437 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1438
1439 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1440 mdelay(1);
1441 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1442 }
1443 outl(omr, DE4X5_OMR); /* Stop everything! */
1444
1445 if (j == 0) {
f3b197ac 1446 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1da177e4
LT		 1447 inl(DE4X5_STS));
1448 status = -EIO;
1449 }
f3b197ac 1450
1da177e4
LT		 1451 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1452 lp->tx_old = lp->tx_new;
1453
1454 return status;
1455}
1456
f3b197ac 1457/*
1da177e4
LT		 1458** Writes a socket buffer address to the next available transmit descriptor.
1459*/
ad096463 1460static netdev_tx_t
1da177e4
LT		 1461de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1462{
1463 struct de4x5_private *lp = netdev_priv(dev);
1464 u_long iobase = dev->base_addr;
1da177e4
LT		 1465 u_long flags = 0;
1466
1467 netif_stop_queue(dev);
ad096463 1468 if (!lp->tx_enable) /* Cannot send for now */
5b548140 1469 return NETDEV_TX_LOCKED;
f3b197ac 1470
1da177e4
LT		 1471 /*
1472 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1473 ** interrupts are lost by delayed descriptor status updates relative to
1474 ** the irq assertion, especially with a busy PCI bus.
1475 */
1476 spin_lock_irqsave(&lp->lock, flags);
1477 de4x5_tx(dev);
1478 spin_unlock_irqrestore(&lp->lock, flags);
1479
1480 /* Test if cache is already locked - requeue skb if so */
f3b197ac 1481 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
5b548140 1482 return NETDEV_TX_LOCKED;
1da177e4
LT		 1483
1484 /* Transmit descriptor ring full or stale skb */
1485 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1486 if (lp->interrupt) {
1487 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1488 } else {
1489 de4x5_put_cache(dev, skb);
1490 }
1491 if (de4x5_debug & DEBUG_TX) {
1492 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1493 }
1494 } else if (skb->len > 0) {
1495 /* If we already have stuff queued locally, use that first */
2aad7c8e 1496 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1da177e4
LT		 1497 de4x5_put_cache(dev, skb);
1498 skb = de4x5_get_cache(dev);
1499 }
1500
1501 while (skb && !netif_queue_stopped(dev) &&
1502 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1503 spin_lock_irqsave(&lp->lock, flags);
1504 netif_stop_queue(dev);
1505 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1506 lp->stats.tx_bytes += skb->len;
1507 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
f3b197ac 1508
1da177e4
LT		 1509 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1510 dev->trans_start = jiffies;
f3b197ac 1511
1da177e4
LT		 1512 if (TX_BUFFS_AVAIL) {
1513 netif_start_queue(dev); /* Another pkt may be queued */
1514 }
1515 skb = de4x5_get_cache(dev);
1516 spin_unlock_irqrestore(&lp->lock, flags);
1517 }
1518 if (skb) de4x5_putb_cache(dev, skb);
1519 }
f3b197ac 1520
1da177e4
LT		 1521 lp->cache.lock = 0;
1522
ad096463 1523 return NETDEV_TX_OK;
1da177e4
LT		 1524}
1525
1526/*
f3b197ac
JG		 1527** The DE4X5 interrupt handler.
1528**
1da177e4
LT		 1529** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1530** so that the asserted interrupt always has some real data to work with -
1531** if these I/O accesses are ever changed to memory accesses, ensure the
1532** STS write is read immediately to complete the transaction if the adapter
1533** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1534** is high and descriptor status bits cannot be set before the associated
1535** interrupt is asserted and this routine entered.
1536*/
1537static irqreturn_t
7d12e780 1538de4x5_interrupt(int irq, void *dev_id)
1da177e4 1539{
c31f28e7 1540 struct net_device *dev = dev_id;
1da177e4
LT		 1541 struct de4x5_private *lp;
1542 s32 imr, omr, sts, limit;
1543 u_long iobase;
1544 unsigned int handled = 0;
f3b197ac 1545
1da177e4
LT		 1546 lp = netdev_priv(dev);
1547 spin_lock(&lp->lock);
1548 iobase = dev->base_addr;
f3b197ac 1549
1da177e4
LT		 1550 DISABLE_IRQs; /* Ensure non re-entrancy */
1551
1552 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1553 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1554
1555 synchronize_irq(dev->irq);
f3b197ac 1556
1da177e4
LT		 1557 for (limit=0; limit<8; limit++) {
1558 sts = inl(DE4X5_STS); /* Read IRQ status */
1559 outl(sts, DE4X5_STS); /* Reset the board interrupts */
f3b197ac 1560
1da177e4
LT		 1561 if (!(sts & lp->irq_mask)) break;/* All done */
1562 handled = 1;
f3b197ac 1563
1da177e4
LT		 1564 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1565 de4x5_rx(dev);
f3b197ac 1566
1da177e4 1567 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
f3b197ac
JG		 1568 de4x5_tx(dev);
1569
1da177e4
LT		 1570 if (sts & STS_LNF) { /* TP Link has failed */
1571 lp->irq_mask &= ~IMR_LFM;
1572 }
f3b197ac 1573
1da177e4
LT		 1574 if (sts & STS_UNF) { /* Transmit underrun */
1575 de4x5_txur(dev);
1576 }
f3b197ac 1577
1da177e4
LT		 1578 if (sts & STS_SE) { /* Bus Error */
1579 STOP_DE4X5;
1580 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1581 dev->name, sts);
1582 spin_unlock(&lp->lock);
1583 return IRQ_HANDLED;
1584 }
1585 }
1586
1587 /* Load the TX ring with any locally stored packets */
1588 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
2aad7c8e 1589 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1da177e4
LT		 1590 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1591 }
1592 lp->cache.lock = 0;
1593 }
1594
1595 lp->interrupt = UNMASK_INTERRUPTS;
1596 ENABLE_IRQs;
1597 spin_unlock(&lp->lock);
f3b197ac 1598
1da177e4
LT		 1599 return IRQ_RETVAL(handled);
1600}
1601
1602static int
1603de4x5_rx(struct net_device *dev)
1604{
1605 struct de4x5_private *lp = netdev_priv(dev);
1606 u_long iobase = dev->base_addr;
1607 int entry;
1608 s32 status;
f3b197ac 1609
1da177e4
LT		 1610 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1611 entry=lp->rx_new) {
1612 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
f3b197ac 1613
1da177e4
LT		 1614 if (lp->rx_ovf) {
1615 if (inl(DE4X5_MFC) & MFC_FOCM) {
1616 de4x5_rx_ovfc(dev);
1617 break;
1618 }
1619 }
1620
1621 if (status & RD_FS) { /* Remember the start of frame */
1622 lp->rx_old = entry;
1623 }
f3b197ac 1624
1da177e4
LT		 1625 if (status & RD_LS) { /* Valid frame status */
1626 if (lp->tx_enable) lp->linkOK++;
1627 if (status & RD_ES) { /* There was an error. */
1628 lp->stats.rx_errors++; /* Update the error stats. */
1629 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1630 if (status & RD_CE) lp->stats.rx_crc_errors++;
1631 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1632 if (status & RD_TL) lp->stats.rx_length_errors++;
1633 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1634 if (status & RD_CS) lp->pktStats.rx_collision++;
1635 if (status & RD_DB) lp->pktStats.rx_dribble++;
1636 if (status & RD_OF) lp->pktStats.rx_overflow++;
1637 } else { /* A valid frame received */
1638 struct sk_buff *skb;
1639 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1640 >> 16) - 4;
f3b197ac 1641
1da177e4 1642 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
f3b197ac 1643 printk("%s: Insufficient memory; nuking packet.\n",
1da177e4
LT		 1644 dev->name);
1645 lp->stats.rx_dropped++;
1646 } else {
1647 de4x5_dbg_rx(skb, pkt_len);
1648
1649 /* Push up the protocol stack */
1650 skb->protocol=eth_type_trans(skb,dev);
1651 de4x5_local_stats(dev, skb->data, pkt_len);
1652 netif_rx(skb);
f3b197ac 1653
1da177e4 1654 /* Update stats */
1da177e4
LT		 1655 lp->stats.rx_packets++;
1656 lp->stats.rx_bytes += pkt_len;
1657 }
1658 }
f3b197ac 1659
1da177e4
LT		 1660 /* Change buffer ownership for this frame, back to the adapter */
1661 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1662 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1663 barrier();
1664 }
1665 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1666 barrier();
1667 }
f3b197ac 1668
1da177e4
LT		 1669 /*
1670 ** Update entry information
1671 */
1672 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1673 }
f3b197ac 1674
1da177e4
LT		 1675 return 0;
1676}
1677
1678static inline void
1679de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1680{
1681 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1682 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1683 DMA_TO_DEVICE);
1684 if ((u_long) lp->tx_skb[entry] > 1)
1685 dev_kfree_skb_irq(lp->tx_skb[entry]);
1686 lp->tx_skb[entry] = NULL;
1687}
1688
1689/*
1690** Buffer sent - check for TX buffer errors.
1691*/
1692static int
1693de4x5_tx(struct net_device *dev)
1694{
1695 struct de4x5_private *lp = netdev_priv(dev);
1696 u_long iobase = dev->base_addr;
1697 int entry;
1698 s32 status;
f3b197ac 1699
1da177e4
LT		 1700 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1701 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1702 if (status < 0) { /* Buffer not sent yet */
1703 break;
1704 } else if (status != 0x7fffffff) { /* Not setup frame */
1705 if (status & TD_ES) { /* An error happened */
f3b197ac 1706 lp->stats.tx_errors++;
1da177e4
LT		 1707 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1708 if (status & TD_LC) lp->stats.tx_window_errors++;
1709 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1710 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1711 if (status & TD_DE) lp->stats.tx_aborted_errors++;
f3b197ac 1712
1da177e4
LT		 1713 if (TX_PKT_PENDING) {
1714 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1715 }
1716 } else { /* Packet sent */
1717 lp->stats.tx_packets++;
1718 if (lp->tx_enable) lp->linkOK++;
1719 }
1720 /* Update the collision counter */
f3b197ac 1721 lp->stats.collisions += ((status & TD_EC) ? 16 :
1da177e4
LT		 1722 ((status & TD_CC) >> 3));
1723
1724 /* Free the buffer. */
1725 if (lp->tx_skb[entry] != NULL)
1726 de4x5_free_tx_buff(lp, entry);
1727 }
f3b197ac 1728
1da177e4
LT		 1729 /* Update all the pointers */
1730 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1731 }
1732
1733 /* Any resources available? */
1734 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1735 if (lp->interrupt)
1736 netif_wake_queue(dev);
1737 else
1738 netif_start_queue(dev);
1739 }
f3b197ac 1740
1da177e4
LT		 1741 return 0;
1742}
1743
561b4fbf 1744static void
1da177e4
LT		 1745de4x5_ast(struct net_device *dev)
1746{
561b4fbf
AV		 1747 struct de4x5_private *lp = netdev_priv(dev);
1748 int next_tick = DE4X5_AUTOSENSE_MS;
1749 int dt;
f3b197ac 1750
561b4fbf
AV		 1751 if (lp->useSROM)
1752 next_tick = srom_autoconf(dev);
1753 else if (lp->chipset == DC21140)
1754 next_tick = dc21140m_autoconf(dev);
1755 else if (lp->chipset == DC21041)
1756 next_tick = dc21041_autoconf(dev);
1757 else if (lp->chipset == DC21040)
1758 next_tick = dc21040_autoconf(dev);
1759 lp->linkOK = 0;
f3b197ac 1760
561b4fbf 1761 dt = (next_tick * HZ) / 1000;
f3b197ac 1762
561b4fbf
AV		 1763 if (!dt)
1764 dt = 1;
1765
1766 mod_timer(&lp->timer, jiffies + dt);
1da177e4
LT		 1767}
1768
1769static int
1770de4x5_txur(struct net_device *dev)
1771{
1772 struct de4x5_private *lp = netdev_priv(dev);
1773 u_long iobase = dev->base_addr;
1774 int omr;
1775
1776 omr = inl(DE4X5_OMR);
1777 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1778 omr &= ~(OMR_ST|OMR_SR);
1779 outl(omr, DE4X5_OMR);
1780 while (inl(DE4X5_STS) & STS_TS);
1781 if ((omr & OMR_TR) < OMR_TR) {
1782 omr += 0x4000;
1783 } else {
1784 omr |= OMR_SF;
1785 }
1786 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1787 }
f3b197ac 1788
1da177e4
LT		 1789 return 0;
1790}
1791
f3b197ac 1792static int
1da177e4
LT		 1793de4x5_rx_ovfc(struct net_device *dev)
1794{
1795 struct de4x5_private *lp = netdev_priv(dev);
1796 u_long iobase = dev->base_addr;
1797 int omr;
1798
1799 omr = inl(DE4X5_OMR);
1800 outl(omr & ~OMR_SR, DE4X5_OMR);
1801 while (inl(DE4X5_STS) & STS_RS);
1802
1803 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1804 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1805 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1806 }
1807
1808 outl(omr, DE4X5_OMR);
f3b197ac 1809
1da177e4
LT		 1810 return 0;
1811}
1812
1813static int
1814de4x5_close(struct net_device *dev)
1815{
1816 struct de4x5_private *lp = netdev_priv(dev);
1817 u_long iobase = dev->base_addr;
1818 s32 imr, omr;
f3b197ac 1819
1da177e4
LT		 1820 disable_ast(dev);
1821
1822 netif_stop_queue(dev);
f3b197ac 1823
1da177e4
LT		 1824 if (de4x5_debug & DEBUG_CLOSE) {
1825 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1826 dev->name, inl(DE4X5_STS));
1827 }
f3b197ac
JG		 1828
1829 /*
1da177e4
LT		 1830 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1831 */
1832 DISABLE_IRQs;
1833 STOP_DE4X5;
f3b197ac 1834
1da177e4
LT		 1835 /* Free the associated irq */
1836 free_irq(dev->irq, dev);
1837 lp->state = CLOSED;
1838
1839 /* Free any socket buffers */
1840 de4x5_free_rx_buffs(dev);
1841 de4x5_free_tx_buffs(dev);
f3b197ac 1842
1da177e4
LT		 1843 /* Put the adapter to sleep to save power */
1844 yawn(dev, SLEEP);
f3b197ac 1845
1da177e4
LT		 1846 return 0;
1847}
1848
1849static struct net_device_stats *
1850de4x5_get_stats(struct net_device *dev)
1851{
1852 struct de4x5_private *lp = netdev_priv(dev);
1853 u_long iobase = dev->base_addr;
f3b197ac 1854
1da177e4 1855 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
f3b197ac 1856
1da177e4
LT		 1857 return &lp->stats;
1858}
1859
1860static void
1861de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1862{
1863 struct de4x5_private *lp = netdev_priv(dev);
1864 int i;
1865
1866 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1867 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1868 lp->pktStats.bins[i]++;
1869 i = DE4X5_PKT_STAT_SZ;
1870 }
1871 }
1872 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1873 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1874 lp->pktStats.broadcast++;
1875 } else {
1876 lp->pktStats.multicast++;
1877 }
1878 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1879 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1880 lp->pktStats.unicast++;
1881 }
f3b197ac 1882
1da177e4
LT		 1883 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1884 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1885 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1886 }
1887
1888 return;
1889}
1890
1891/*
1892** Removes the TD_IC flag from previous descriptor to improve TX performance.
1893** If the flag is changed on a descriptor that is being read by the hardware,
1894** I assume PCI transaction ordering will mean you are either successful or
1895** just miss asserting the change to the hardware. Anyway you're messing with
1896** a descriptor you don't own, but this shouldn't kill the chip provided
1897** the descriptor register is read only to the hardware.
1898*/
1899static void
1900load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1901{
1902 struct de4x5_private *lp = netdev_priv(dev);
1903 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1904 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1905
1906 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1907 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1908 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1909 lp->tx_skb[lp->tx_new] = skb;
1910 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1911 barrier();
1912
1913 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1914 barrier();
1915}
1916
1917/*
1918** Set or clear the multicast filter for this adaptor.
1919*/
1920static void
1921set_multicast_list(struct net_device *dev)
1922{
1923 struct de4x5_private *lp = netdev_priv(dev);
1924 u_long iobase = dev->base_addr;
1925
1926 /* First, double check that the adapter is open */
1927 if (lp->state == OPEN) {
1928 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1929 u32 omr;
1930 omr = inl(DE4X5_OMR);
1931 omr |= OMR_PR;
1932 outl(omr, DE4X5_OMR);
f3b197ac 1933 } else {
1da177e4 1934 SetMulticastFilter(dev);
f3b197ac 1935 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1da177e4 1936 SETUP_FRAME_LEN, (struct sk_buff *)1);
f3b197ac 1937
1da177e4
LT		 1938 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1939 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1940 dev->trans_start = jiffies;
1941 }
1942 }
1943}
1944
1945/*
1946** Calculate the hash code and update the logical address filter
1947** from a list of ethernet multicast addresses.
1948** Little endian crc one liner from Matt Thomas, DEC.
1949*/
1950static void
1951SetMulticastFilter(struct net_device *dev)
1952{
1953 struct de4x5_private *lp = netdev_priv(dev);
4302b67e 1954 struct dev_mc_list *dmi;
1da177e4 1955 u_long iobase = dev->base_addr;
4302b67e 1956 int i, bit, byte;
1da177e4
LT		 1957 u16 hashcode;
1958 u32 omr, crc;
1959 char *pa;
1960 unsigned char *addrs;
1961
1962 omr = inl(DE4X5_OMR);
1963 omr &= ~(OMR_PR | OMR_PM);
1964 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
f3b197ac 1965
4cd24eaf 1966 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) {
1da177e4
LT		 1967 omr |= OMR_PM; /* Pass all multicasts */
1968 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
4302b67e
JP		 1969 netdev_for_each_mc_addr(dmi, dev) {
1970 addrs = dmi->dmi_addr;
f3b197ac 1971 if ((*addrs & 0x01) == 1) { /* multicast address? */
1da177e4
LT		 1972 crc = ether_crc_le(ETH_ALEN, addrs);
1973 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
f3b197ac 1974
1da177e4
LT		 1975 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1976 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
f3b197ac 1977
1da177e4
LT		 1978 byte <<= 1; /* calc offset into setup frame */
1979 if (byte & 0x02) {
1980 byte -= 1;
1981 }
1982 lp->setup_frame[byte] |= bit;
1983 }
1984 }
1985 } else { /* Perfect filtering */
4302b67e
JP		 1986 netdev_for_each_mc_addr(dmi, dev) {
1987 addrs = dmi->dmi_addr;
f3b197ac 1988 for (i=0; i<ETH_ALEN; i++) {
1da177e4
LT		 1989 *(pa + (i&1)) = *addrs++;
1990 if (i & 0x01) pa += 4;
1991 }
1992 }
1993 }
1994 outl(omr, DE4X5_OMR);
f3b197ac 1995
1da177e4
LT		 1996 return;
1997}
1998
1999#ifdef CONFIG_EISA
2000
2001static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2002
2003static int __init de4x5_eisa_probe (struct device *gendev)
2004{
2005 struct eisa_device *edev;
2006 u_long iobase;
2007 u_char irq, regval;
2008 u_short vendor;
2009 u32 cfid;
2010 int status, device;
2011 struct net_device *dev;
2012 struct de4x5_private *lp;
2013
2014 edev = to_eisa_device (gendev);
2015 iobase = edev->base_addr;
2016
2017 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2018 return -EBUSY;
2019
2020 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2021 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2022 status = -EBUSY;
2023 goto release_reg_1;
2024 }
f3b197ac 2025
1da177e4
LT		 2026 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2027 status = -ENOMEM;
2028 goto release_reg_2;
2029 }
2030 lp = netdev_priv(dev);
f3b197ac 2031
1da177e4
LT		 2032 cfid = (u32) inl(PCI_CFID);
2033 lp->cfrv = (u_short) inl(PCI_CFRV);
2034 device = (cfid >> 8) & 0x00ffff00;
2035 vendor = (u_short) cfid;
f3b197ac 2036
1da177e4
LT		 2037 /* Read the EISA Configuration Registers */
2038 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2039#ifdef CONFIG_ALPHA
2040 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2041 * care about the EISA configuration, and thus doesn't
2042 * configure the PLX bridge properly. Oh well... Simply mimic
2043 * the EISA config file to sort it out. */
f3b197ac 2044
1da177e4
LT		 2045 /* EISA REG1: Assert DecChip 21040 HW Reset */
2046 outb (ER1_IAM | 1, EISA_REG1);
2047 mdelay (1);
2048
2049 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2050 outb (ER1_IAM, EISA_REG1);
2051 mdelay (1);
2052
2053 /* EISA REG3: R/W Burst Transfer Enable */
2054 outb (ER3_BWE | ER3_BRE, EISA_REG3);
f3b197ac 2055
1da177e4
LT		 2056 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2057 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2058#endif
2059 irq = de4x5_irq[(regval >> 1) & 0x03];
f3b197ac 2060
1da177e4
LT		 2061 if (is_DC2114x) {
2062 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2063 }
2064 lp->chipset = device;
2065 lp->bus = EISA;
2066
2067 /* Write the PCI Configuration Registers */
2068 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2069 outl(0x00006000, PCI_CFLT);
2070 outl(iobase, PCI_CBIO);
f3b197ac 2071
1da177e4
LT		 2072 DevicePresent(dev, EISA_APROM);
2073
2074 dev->irq = irq;
2075
2076 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2077 return 0;
2078 }
2079
2080 free_netdev (dev);
2081 release_reg_2:
2082 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2083 release_reg_1:
2084 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2085
2086 return status;
2087}
2088
2089static int __devexit de4x5_eisa_remove (struct device *device)
2090{
2091 struct net_device *dev;
2092 u_long iobase;
2093
1aec5bdf 2094 dev = dev_get_drvdata(device);
1da177e4 2095 iobase = dev->base_addr;
f3b197ac 2096
1da177e4
LT		 2097 unregister_netdev (dev);
2098 free_netdev (dev);
2099 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2100 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2101
2102 return 0;
2103}
2104
2105static struct eisa_device_id de4x5_eisa_ids[] = {
2106 { "DEC4250", 0 }, /* 0 is the board name index... */
2107 { "" }
2108};
07563c71 2109MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
1da177e4
LT		 2110
2111static struct eisa_driver de4x5_eisa_driver = {
2112 .id_table = de4x5_eisa_ids,
2113 .driver = {
2114 .name = "de4x5",
2115 .probe = de4x5_eisa_probe,
2116 .remove = __devexit_p (de4x5_eisa_remove),
2117 }
2118};
2119MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2120#endif
2121
2122#ifdef CONFIG_PCI
2123
2124/*
2125** This function searches the current bus (which is >0) for a DECchip with an
f3b197ac 2126** SROM, so that in multiport cards that have one SROM shared between multiple
1da177e4
LT		 2127** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2128** For single port cards this is a time waster...
2129*/
f3b197ac 2130static void __devinit
1da177e4
LT		 2131srom_search(struct net_device *dev, struct pci_dev *pdev)
2132{
2133 u_char pb;
2134 u_short vendor, status;
2135 u_int irq = 0, device;
2136 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
44c10138 2137 int i, j;
1da177e4 2138 struct de4x5_private *lp = netdev_priv(dev);
0c5719c4 2139 struct list_head *walk;
1da177e4 2140
0c5719c4 2141 list_for_each(walk, &pdev->bus_list) {
1da177e4
LT		 2142 struct pci_dev *this_dev = pci_dev_b(walk);
2143
2144 /* Skip the pci_bus list entry */
2145 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2146
2147 vendor = this_dev->vendor;
2148 device = this_dev->device << 8;
2149 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2150
2151 /* Get the chip configuration revision register */
2152 pb = this_dev->bus->number;
1da177e4
LT		 2153
2154 /* Set the device number information */
2155 lp->device = PCI_SLOT(this_dev->devfn);
2156 lp->bus_num = pb;
f3b197ac 2157
1da177e4
LT		 2158 /* Set the chipset information */
2159 if (is_DC2114x) {
44c10138
AK		 2160 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2161 ? DC21142 : DC21143);
1da177e4
LT		 2162 }
2163 lp->chipset = device;
2164
2165 /* Get the board I/O address (64 bits on sparc64) */
2166 iobase = pci_resource_start(this_dev, 0);
2167
2168 /* Fetch the IRQ to be used */
2169 irq = this_dev->irq;
2170 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
f3b197ac 2171
1da177e4
LT		 2172 /* Check if I/O accesses are enabled */
2173 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2174 if (!(status & PCI_COMMAND_IO)) continue;
2175
2176 /* Search for a valid SROM attached to this DECchip */
2177 DevicePresent(dev, DE4X5_APROM);
2178 for (j=0, i=0; i<ETH_ALEN; i++) {
2179 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2180 }
561b4fbf 2181 if (j != 0 && j != 6 * 0xff) {
1da177e4
LT		 2182 last.chipset = device;
2183 last.bus = pb;
2184 last.irq = irq;
2185 for (i=0; i<ETH_ALEN; i++) {
2186 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2187 }
2188 return;
2189 }
2190 }
2191
2192 return;
2193}
2194
2195/*
2196** PCI bus I/O device probe
2197** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2198** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2199** enabled by the user first in the set up utility. Hence we just check for
2200** enabled features and silently ignore the card if they're not.
2201**
2202** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2203** bit. Here, check for I/O accesses and then set BM. If you put the card in
2204** a non BM slot, you're on your own (and complain to the PC vendor that your
2205** PC doesn't conform to the PCI standard)!
2206**
2207** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2208** kernels use the V0.535[n] drivers.
2209*/
2210
2211static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2212 const struct pci_device_id *ent)
2213{
2214 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2215 u_short vendor, status;
2216 u_int irq = 0, device;
2217 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2218 int error;
2219 struct net_device *dev;
2220 struct de4x5_private *lp;
2221
2222 dev_num = PCI_SLOT(pdev->devfn);
2223 pb = pdev->bus->number;
2224
2225 if (io) { /* probe a single PCI device */
2226 pbus = (u_short)(io >> 8);
2227 dnum = (u_short)(io & 0xff);
2228 if ((pbus != pb) || (dnum != dev_num))
2229 return -ENODEV;
2230 }
2231
2232 vendor = pdev->vendor;
2233 device = pdev->device << 8;
2234 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2235 return -ENODEV;
2236
2237 /* Ok, the device seems to be for us. */
2238 if ((error = pci_enable_device (pdev)))
2239 return error;
2240
2241 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2242 error = -ENOMEM;
2243 goto disable_dev;
2244 }
2245
2246 lp = netdev_priv(dev);
2247 lp->bus = PCI;
2248 lp->bus_num = 0;
f3b197ac 2249
1da177e4
LT		 2250 /* Search for an SROM on this bus */
2251 if (lp->bus_num != pb) {
2252 lp->bus_num = pb;
2253 srom_search(dev, pdev);
2254 }
2255
2256 /* Get the chip configuration revision register */
44c10138 2257 lp->cfrv = pdev->revision;
1da177e4
LT		 2258
2259 /* Set the device number information */
2260 lp->device = dev_num;
2261 lp->bus_num = pb;
f3b197ac 2262
1da177e4
LT		 2263 /* Set the chipset information */
2264 if (is_DC2114x) {
2265 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2266 }
2267 lp->chipset = device;
2268
2269 /* Get the board I/O address (64 bits on sparc64) */
2270 iobase = pci_resource_start(pdev, 0);
2271
2272 /* Fetch the IRQ to be used */
2273 irq = pdev->irq;
2274 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2275 error = -ENODEV;
2276 goto free_dev;
2277 }
f3b197ac 2278
1da177e4
LT		 2279 /* Check if I/O accesses and Bus Mastering are enabled */
2280 pci_read_config_word(pdev, PCI_COMMAND, &status);
2281#ifdef __powerpc__
2282 if (!(status & PCI_COMMAND_IO)) {
2283 status |= PCI_COMMAND_IO;
2284 pci_write_config_word(pdev, PCI_COMMAND, status);
2285 pci_read_config_word(pdev, PCI_COMMAND, &status);
2286 }
2287#endif /* __powerpc__ */
2288 if (!(status & PCI_COMMAND_IO)) {
2289 error = -ENODEV;
2290 goto free_dev;
2291 }
2292
2293 if (!(status & PCI_COMMAND_MASTER)) {
2294 status |= PCI_COMMAND_MASTER;
2295 pci_write_config_word(pdev, PCI_COMMAND, status);
2296 pci_read_config_word(pdev, PCI_COMMAND, &status);
2297 }
2298 if (!(status & PCI_COMMAND_MASTER)) {
2299 error = -ENODEV;
2300 goto free_dev;
2301 }
2302
2303 /* Check the latency timer for values >= 0x60 */
2304 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2305 if (timer < 0x60) {
2306 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2307 }
2308
2309 DevicePresent(dev, DE4X5_APROM);
2310
2311 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2312 error = -EBUSY;
2313 goto free_dev;
2314 }
2315
2316 dev->irq = irq;
f3b197ac 2317
1da177e4
LT		 2318 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2319 goto release;
2320 }
2321
2322 return 0;
2323
2324 release:
2325 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2326 free_dev:
2327 free_netdev (dev);
2328 disable_dev:
2329 pci_disable_device (pdev);
2330 return error;
2331}
2332
2333static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2334{
2335 struct net_device *dev;
2336 u_long iobase;
2337
1aec5bdf 2338 dev = dev_get_drvdata(&pdev->dev);
1da177e4
LT		 2339 iobase = dev->base_addr;
2340
2341 unregister_netdev (dev);
2342 free_netdev (dev);
2343 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2344 pci_disable_device (pdev);
2345}
2346
2347static struct pci_device_id de4x5_pci_tbl[] = {
2348 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2350 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2352 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2354 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2356 { },
2357};
2358
2359static struct pci_driver de4x5_pci_driver = {
2360 .name = "de4x5",
2361 .id_table = de4x5_pci_tbl,
2362 .probe = de4x5_pci_probe,
2363 .remove = __devexit_p (de4x5_pci_remove),
2364};
2365
2366#endif
2367
2368/*
2369** Auto configure the media here rather than setting the port at compile
2370** time. This routine is called by de4x5_init() and when a loss of media is
2371** detected (excessive collisions, loss of carrier, no carrier or link fail
f3b197ac 2372** [TP] or no recent receive activity) to check whether the user has been
1da177e4
LT		 2373** sneaky and changed the port on us.
2374*/
2375static int
2376autoconf_media(struct net_device *dev)
2377{
561b4fbf
AV		 2378 struct de4x5_private *lp = netdev_priv(dev);
2379 u_long iobase = dev->base_addr;
1da177e4 2380
561b4fbf 2381 disable_ast(dev);
1da177e4 2382
561b4fbf
AV		 2383 lp->c_media = AUTO; /* Bogus last media */
2384 inl(DE4X5_MFC); /* Zero the lost frames counter */
2385 lp->media = INIT;
2386 lp->tcount = 0;
1da177e4 2387
561b4fbf 2388 de4x5_ast(dev);
f3b197ac 2389
561b4fbf 2390 return lp->media;
1da177e4
LT		 2391}
2392
2393/*
2394** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2395** from BNC as the port has a jumper to set thick or thin wire. When set for
2396** BNC, the BNC port will indicate activity if it's not terminated correctly.
2397** The only way to test for that is to place a loopback packet onto the
2398** network and watch for errors. Since we're messing with the interrupt mask
2399** register, disable the board interrupts and do not allow any more packets to
2400** be queued to the hardware. Re-enable everything only when the media is
2401** found.
2402** I may have to "age out" locally queued packets so that the higher layer
2403** timeouts don't effectively duplicate packets on the network.
2404*/
2405static int
2406dc21040_autoconf(struct net_device *dev)
2407{
2408 struct de4x5_private *lp = netdev_priv(dev);
2409 u_long iobase = dev->base_addr;
2410 int next_tick = DE4X5_AUTOSENSE_MS;
2411 s32 imr;
f3b197ac 2412
1da177e4
LT		 2413 switch (lp->media) {
2414 case INIT:
2415 DISABLE_IRQs;
eb034a79 2416 lp->tx_enable = false;
1da177e4
LT		 2417 lp->timeout = -1;
2418 de4x5_save_skbs(dev);
2419 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2420 lp->media = TP;
2421 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2422 lp->media = BNC_AUI;
2423 } else if (lp->autosense == EXT_SIA) {
2424 lp->media = EXT_SIA;
2425 } else {
2426 lp->media = NC;
2427 }
2428 lp->local_state = 0;
2429 next_tick = dc21040_autoconf(dev);
2430 break;
f3b197ac 2431
1da177e4 2432 case TP:
f3b197ac 2433 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
1da177e4
LT		 2434 TP_SUSPECT, test_tp);
2435 break;
f3b197ac 2436
1da177e4
LT		 2437 case TP_SUSPECT:
2438 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2439 break;
f3b197ac 2440
1da177e4
LT		 2441 case BNC:
2442 case AUI:
2443 case BNC_AUI:
f3b197ac 2444 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
1da177e4
LT		 2445 BNC_AUI_SUSPECT, ping_media);
2446 break;
f3b197ac 2447
1da177e4
LT		 2448 case BNC_AUI_SUSPECT:
2449 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2450 break;
f3b197ac 2451
1da177e4 2452 case EXT_SIA:
f3b197ac 2453 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
1da177e4
LT		 2454 NC, EXT_SIA_SUSPECT, ping_media);
2455 break;
f3b197ac 2456
1da177e4
LT		 2457 case EXT_SIA_SUSPECT:
2458 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2459 break;
f3b197ac 2460
1da177e4
LT		 2461 case NC:
2462 /* default to TP for all */
2463 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2464 if (lp->media != lp->c_media) {
2465 de4x5_dbg_media(dev);
2466 lp->c_media = lp->media;
2467 }
2468 lp->media = INIT;
eb034a79 2469 lp->tx_enable = false;
1da177e4
LT		 2470 break;
2471 }
f3b197ac 2472
1da177e4
LT		 2473 return next_tick;
2474}
2475
2476static int
2477dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
f3b197ac 2478 int next_state, int suspect_state,
1da177e4
LT		 2479 int (*fn)(struct net_device *, int))
2480{
2481 struct de4x5_private *lp = netdev_priv(dev);
2482 int next_tick = DE4X5_AUTOSENSE_MS;
2483 int linkBad;
2484
2485 switch (lp->local_state) {
2486 case 0:
2487 reset_init_sia(dev, csr13, csr14, csr15);
2488 lp->local_state++;
2489 next_tick = 500;
2490 break;
f3b197ac 2491
1da177e4
LT		 2492 case 1:
2493 if (!lp->tx_enable) {
2494 linkBad = fn(dev, timeout);
2495 if (linkBad < 0) {
2496 next_tick = linkBad & ~TIMER_CB;
2497 } else {
2498 if (linkBad && (lp->autosense == AUTO)) {
2499 lp->local_state = 0;
2500 lp->media = next_state;
2501 } else {
2502 de4x5_init_connection(dev);
2503 }
2504 }
2505 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2506 lp->media = suspect_state;
2507 next_tick = 3000;
2508 }
2509 break;
2510 }
f3b197ac 2511
1da177e4
LT		 2512 return next_tick;
2513}
2514
2515static int
2516de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2517 int (*fn)(struct net_device *, int),
2518 int (*asfn)(struct net_device *))
2519{
2520 struct de4x5_private *lp = netdev_priv(dev);
2521 int next_tick = DE4X5_AUTOSENSE_MS;
2522 int linkBad;
2523
2524 switch (lp->local_state) {
2525 case 1:
2526 if (lp->linkOK) {
2527 lp->media = prev_state;
2528 } else {
2529 lp->local_state++;
2530 next_tick = asfn(dev);
2531 }
2532 break;
2533
2534 case 2:
2535 linkBad = fn(dev, timeout);
2536 if (linkBad < 0) {
2537 next_tick = linkBad & ~TIMER_CB;
2538 } else if (!linkBad) {
2539 lp->local_state--;
2540 lp->media = prev_state;
2541 } else {
2542 lp->media = INIT;
2543 lp->tcount++;
2544 }
2545 }
2546
2547 return next_tick;
2548}
2549
2550/*
2551** Autoconfigure the media when using the DC21041. AUI needs to be tested
2552** before BNC, because the BNC port will indicate activity if it's not
2553** terminated correctly. The only way to test for that is to place a loopback
2554** packet onto the network and watch for errors. Since we're messing with
2555** the interrupt mask register, disable the board interrupts and do not allow
2556** any more packets to be queued to the hardware. Re-enable everything only
2557** when the media is found.
2558*/
2559static int
2560dc21041_autoconf(struct net_device *dev)
2561{
2562 struct de4x5_private *lp = netdev_priv(dev);
2563 u_long iobase = dev->base_addr;
2564 s32 sts, irqs, irq_mask, imr, omr;
2565 int next_tick = DE4X5_AUTOSENSE_MS;
f3b197ac 2566
1da177e4
LT		 2567 switch (lp->media) {
2568 case INIT:
2569 DISABLE_IRQs;
eb034a79 2570 lp->tx_enable = false;
1da177e4
LT		 2571 lp->timeout = -1;
2572 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2573 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2574 lp->media = TP; /* On chip auto negotiation is broken */
2575 } else if (lp->autosense == TP) {
2576 lp->media = TP;
2577 } else if (lp->autosense == BNC) {
2578 lp->media = BNC;
2579 } else if (lp->autosense == AUI) {
2580 lp->media = AUI;
2581 } else {
2582 lp->media = NC;
2583 }
2584 lp->local_state = 0;
2585 next_tick = dc21041_autoconf(dev);
2586 break;
f3b197ac 2587
1da177e4
LT		 2588 case TP_NW:
2589 if (lp->timeout < 0) {
2590 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2591 outl(omr | OMR_FDX, DE4X5_OMR);
2592 }
2593 irqs = STS_LNF | STS_LNP;
2594 irq_mask = IMR_LFM | IMR_LPM;
2595 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2596 if (sts < 0) {
2597 next_tick = sts & ~TIMER_CB;
2598 } else {
2599 if (sts & STS_LNP) {
2600 lp->media = ANS;
2601 } else {
2602 lp->media = AUI;
2603 }
2604 next_tick = dc21041_autoconf(dev);
2605 }
2606 break;
f3b197ac 2607
1da177e4
LT		 2608 case ANS:
2609 if (!lp->tx_enable) {
2610 irqs = STS_LNP;
2611 irq_mask = IMR_LPM;
2612 sts = test_ans(dev, irqs, irq_mask, 3000);
2613 if (sts < 0) {
2614 next_tick = sts & ~TIMER_CB;
2615 } else {
2616 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2617 lp->media = TP;
2618 next_tick = dc21041_autoconf(dev);
2619 } else {
2620 lp->local_state = 1;
2621 de4x5_init_connection(dev);
2622 }
2623 }
2624 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2625 lp->media = ANS_SUSPECT;
2626 next_tick = 3000;
2627 }
2628 break;
f3b197ac 2629
1da177e4
LT		 2630 case ANS_SUSPECT:
2631 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2632 break;
f3b197ac 2633
1da177e4
LT		 2634 case TP:
2635 if (!lp->tx_enable) {
2636 if (lp->timeout < 0) {
2637 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2638 outl(omr & ~OMR_FDX, DE4X5_OMR);
2639 }
2640 irqs = STS_LNF | STS_LNP;
2641 irq_mask = IMR_LFM | IMR_LPM;
2642 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2643 if (sts < 0) {
2644 next_tick = sts & ~TIMER_CB;
2645 } else {
2646 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2647 if (inl(DE4X5_SISR) & SISR_NRA) {
2648 lp->media = AUI; /* Non selected port activity */
2649 } else {
2650 lp->media = BNC;
2651 }
2652 next_tick = dc21041_autoconf(dev);
2653 } else {
2654 lp->local_state = 1;
2655 de4x5_init_connection(dev);
2656 }
2657 }
2658 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2659 lp->media = TP_SUSPECT;
2660 next_tick = 3000;
2661 }
2662 break;
f3b197ac 2663
1da177e4
LT		 2664 case TP_SUSPECT:
2665 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2666 break;
f3b197ac 2667
1da177e4
LT		 2668 case AUI:
2669 if (!lp->tx_enable) {
2670 if (lp->timeout < 0) {
2671 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2672 outl(omr & ~OMR_FDX, DE4X5_OMR);
2673 }
2674 irqs = 0;
2675 irq_mask = 0;
2676 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2677 if (sts < 0) {
2678 next_tick = sts & ~TIMER_CB;
2679 } else {
2680 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2681 lp->media = BNC;
2682 next_tick = dc21041_autoconf(dev);
2683 } else {
2684 lp->local_state = 1;
2685 de4x5_init_connection(dev);
2686 }
2687 }
2688 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2689 lp->media = AUI_SUSPECT;
2690 next_tick = 3000;
2691 }
2692 break;
f3b197ac 2693
1da177e4
LT		 2694 case AUI_SUSPECT:
2695 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2696 break;
f3b197ac 2697
1da177e4
LT		 2698 case BNC:
2699 switch (lp->local_state) {
2700 case 0:
2701 if (lp->timeout < 0) {
2702 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2703 outl(omr & ~OMR_FDX, DE4X5_OMR);
2704 }
2705 irqs = 0;
2706 irq_mask = 0;
2707 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2708 if (sts < 0) {
2709 next_tick = sts & ~TIMER_CB;
2710 } else {
2711 lp->local_state++; /* Ensure media connected */
2712 next_tick = dc21041_autoconf(dev);
2713 }
2714 break;
f3b197ac 2715
1da177e4
LT		 2716 case 1:
2717 if (!lp->tx_enable) {
2718 if ((sts = ping_media(dev, 3000)) < 0) {
2719 next_tick = sts & ~TIMER_CB;
2720 } else {
2721 if (sts) {
2722 lp->local_state = 0;
2723 lp->media = NC;
2724 } else {
2725 de4x5_init_connection(dev);
2726 }
2727 }
2728 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2729 lp->media = BNC_SUSPECT;
2730 next_tick = 3000;
2731 }
2732 break;
2733 }
2734 break;
f3b197ac 2735
1da177e4
LT		 2736 case BNC_SUSPECT:
2737 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2738 break;
f3b197ac 2739
1da177e4
LT		 2740 case NC:
2741 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2742 outl(omr | OMR_FDX, DE4X5_OMR);
2743 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2744 if (lp->media != lp->c_media) {
2745 de4x5_dbg_media(dev);
2746 lp->c_media = lp->media;
2747 }
2748 lp->media = INIT;
eb034a79 2749 lp->tx_enable = false;
1da177e4
LT		 2750 break;
2751 }
f3b197ac 2752
1da177e4
LT		 2753 return next_tick;
2754}
2755
2756/*
2757** Some autonegotiation chips are broken in that they do not return the
2758** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2759** register, except at the first power up negotiation.
2760*/
2761static int
2762dc21140m_autoconf(struct net_device *dev)
2763{
2764 struct de4x5_private *lp = netdev_priv(dev);
2765 int ana, anlpa, cap, cr, slnk, sr;
2766 int next_tick = DE4X5_AUTOSENSE_MS;
2767 u_long imr, omr, iobase = dev->base_addr;
f3b197ac 2768
1da177e4 2769 switch(lp->media) {
f3b197ac 2770 case INIT:
1da177e4
LT		 2771 if (lp->timeout < 0) {
2772 DISABLE_IRQs;
eb034a79 2773 lp->tx_enable = false;
1da177e4
LT		 2774 lp->linkOK = 0;
2775 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2776 }
2777 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2778 next_tick &= ~TIMER_CB;
2779 } else {
2780 if (lp->useSROM) {
2781 if (srom_map_media(dev) < 0) {
2782 lp->tcount++;
2783 return next_tick;
2784 }
2785 srom_exec(dev, lp->phy[lp->active].gep);
2786 if (lp->infoblock_media == ANS) {
2787 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2788 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2789 }
2790 } else {
2791 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2792 SET_10Mb;
2793 if (lp->autosense == _100Mb) {
2794 lp->media = _100Mb;
2795 } else if (lp->autosense == _10Mb) {
2796 lp->media = _10Mb;
f3b197ac 2797 } else if ((lp->autosense == AUTO) &&
1da177e4
LT		 2798 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2799 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2800 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2801 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2802 lp->media = ANS;
2803 } else if (lp->autosense == AUTO) {
2804 lp->media = SPD_DET;
2805 } else if (is_spd_100(dev) && is_100_up(dev)) {
2806 lp->media = _100Mb;
2807 } else {
2808 lp->media = NC;
2809 }
2810 }
2811 lp->local_state = 0;
2812 next_tick = dc21140m_autoconf(dev);
2813 }
2814 break;
f3b197ac 2815
1da177e4
LT		 2816 case ANS:
2817 switch (lp->local_state) {
2818 case 0:
2819 if (lp->timeout < 0) {
2820 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2821 }
eb034a79 2822 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
1da177e4
LT		 2823 if (cr < 0) {
2824 next_tick = cr & ~TIMER_CB;
2825 } else {
2826 if (cr) {
2827 lp->local_state = 0;
2828 lp->media = SPD_DET;
2829 } else {
2830 lp->local_state++;
2831 }
2832 next_tick = dc21140m_autoconf(dev);
2833 }
2834 break;
f3b197ac 2835
1da177e4 2836 case 1:
eb034a79 2837 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
1da177e4
LT		 2838 next_tick = sr & ~TIMER_CB;
2839 } else {
2840 lp->media = SPD_DET;
2841 lp->local_state = 0;
2842 if (sr) { /* Success! */
2843 lp->tmp = MII_SR_ASSC;
2844 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2845 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
f3b197ac 2846 if (!(anlpa & MII_ANLPA_RF) &&
1da177e4
LT		 2847 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2848 if (cap & MII_ANA_100M) {
eb034a79 2849 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
1da177e4
LT		 2850 lp->media = _100Mb;
2851 } else if (cap & MII_ANA_10M) {
eb034a79 2852 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
1da177e4
LT		 2853
2854 lp->media = _10Mb;
2855 }
2856 }
2857 } /* Auto Negotiation failed to finish */
2858 next_tick = dc21140m_autoconf(dev);
2859 } /* Auto Negotiation failed to start */
2860 break;
2861 }
2862 break;
f3b197ac 2863
1da177e4
LT		 2864 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2865 if (lp->timeout < 0) {
f3b197ac 2866 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
1da177e4
LT		 2867 (~gep_rd(dev) & GEP_LNP));
2868 SET_100Mb_PDET;
2869 }
2870 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2871 next_tick = slnk & ~TIMER_CB;
2872 } else {
2873 if (is_spd_100(dev) && is_100_up(dev)) {
2874 lp->media = _100Mb;
2875 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2876 lp->media = _10Mb;
2877 } else {
2878 lp->media = NC;
2879 }
2880 next_tick = dc21140m_autoconf(dev);
2881 }
2882 break;
f3b197ac 2883
1da177e4
LT		 2884 case _100Mb: /* Set 100Mb/s */
2885 next_tick = 3000;
2886 if (!lp->tx_enable) {
2887 SET_100Mb;
2888 de4x5_init_connection(dev);
2889 } else {
2890 if (!lp->linkOK && (lp->autosense == AUTO)) {
2891 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2892 lp->media = INIT;
2893 lp->tcount++;
2894 next_tick = DE4X5_AUTOSENSE_MS;
2895 }
2896 }
2897 }
2898 break;
2899
2900 case BNC:
2901 case AUI:
2902 case _10Mb: /* Set 10Mb/s */
2903 next_tick = 3000;
2904 if (!lp->tx_enable) {
2905 SET_10Mb;
2906 de4x5_init_connection(dev);
2907 } else {
2908 if (!lp->linkOK && (lp->autosense == AUTO)) {
2909 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2910 lp->media = INIT;
2911 lp->tcount++;
2912 next_tick = DE4X5_AUTOSENSE_MS;
2913 }
2914 }
2915 }
2916 break;
f3b197ac 2917
1da177e4
LT		 2918 case NC:
2919 if (lp->media != lp->c_media) {
2920 de4x5_dbg_media(dev);
2921 lp->c_media = lp->media;
2922 }
2923 lp->media = INIT;
eb034a79 2924 lp->tx_enable = false;
1da177e4
LT		 2925 break;
2926 }
f3b197ac 2927
1da177e4
LT		 2928 return next_tick;
2929}
2930
2931/*
2932** This routine may be merged into dc21140m_autoconf() sometime as I'm
2933** changing how I figure out the media - but trying to keep it backwards
2934** compatible with the de500-xa and de500-aa.
2935** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2936** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2937** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2938** active.
2939** When autonegotiation is working, the ANS part searches the SROM for
2940** the highest common speed (TP) link that both can run and if that can
2941** be full duplex. That infoblock is executed and then the link speed set.
2942**
2943** Only _10Mb and _100Mb are tested here.
2944*/
2945static int
2946dc2114x_autoconf(struct net_device *dev)
2947{
2948 struct de4x5_private *lp = netdev_priv(dev);
2949 u_long iobase = dev->base_addr;
2950 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2951 int next_tick = DE4X5_AUTOSENSE_MS;
2952
2953 switch (lp->media) {
2954 case INIT:
2955 if (lp->timeout < 0) {
2956 DISABLE_IRQs;
eb034a79 2957 lp->tx_enable = false;
1da177e4
LT		 2958 lp->linkOK = 0;
2959 lp->timeout = -1;
2960 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2961 if (lp->params.autosense & ~AUTO) {
2962 srom_map_media(dev); /* Fixed media requested */
2963 if (lp->media != lp->params.autosense) {
2964 lp->tcount++;
2965 lp->media = INIT;
2966 return next_tick;
2967 }
2968 lp->media = INIT;
2969 }
2970 }
2971 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2972 next_tick &= ~TIMER_CB;
2973 } else {
2974 if (lp->autosense == _100Mb) {
2975 lp->media = _100Mb;
2976 } else if (lp->autosense == _10Mb) {
2977 lp->media = _10Mb;
2978 } else if (lp->autosense == TP) {
2979 lp->media = TP;
2980 } else if (lp->autosense == BNC) {
2981 lp->media = BNC;
2982 } else if (lp->autosense == AUI) {
2983 lp->media = AUI;
2984 } else {
2985 lp->media = SPD_DET;
f3b197ac 2986 if ((lp->infoblock_media == ANS) &&
1da177e4
LT		 2987 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2988 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2989 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2990 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2991 lp->media = ANS;
2992 }
2993 }
2994 lp->local_state = 0;
2995 next_tick = dc2114x_autoconf(dev);
2996 }
2997 break;
f3b197ac 2998
1da177e4
LT		 2999 case ANS:
3000 switch (lp->local_state) {
3001 case 0:
3002 if (lp->timeout < 0) {
3003 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3004 }
eb034a79 3005 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
1da177e4
LT		 3006 if (cr < 0) {
3007 next_tick = cr & ~TIMER_CB;
3008 } else {
3009 if (cr) {
3010 lp->local_state = 0;
3011 lp->media = SPD_DET;
3012 } else {
3013 lp->local_state++;
3014 }
3015 next_tick = dc2114x_autoconf(dev);
3016 }
3017 break;
f3b197ac 3018
1da177e4 3019 case 1:
eb034a79
RK		 3020 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3021 if (sr < 0) {
1da177e4
LT		 3022 next_tick = sr & ~TIMER_CB;
3023 } else {
3024 lp->media = SPD_DET;
3025 lp->local_state = 0;
3026 if (sr) { /* Success! */
3027 lp->tmp = MII_SR_ASSC;
3028 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3029 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
f3b197ac 3030 if (!(anlpa & MII_ANLPA_RF) &&
1da177e4
LT		 3031 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3032 if (cap & MII_ANA_100M) {
eb034a79 3033 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
1da177e4
LT		 3034 lp->media = _100Mb;
3035 } else if (cap & MII_ANA_10M) {
eb034a79 3036 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
1da177e4
LT		 3037 lp->media = _10Mb;
3038 }
3039 }
3040 } /* Auto Negotiation failed to finish */
3041 next_tick = dc2114x_autoconf(dev);
3042 } /* Auto Negotiation failed to start */
3043 break;
3044 }
3045 break;
3046
3047 case AUI:
3048 if (!lp->tx_enable) {
3049 if (lp->timeout < 0) {
3050 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3051 outl(omr & ~OMR_FDX, DE4X5_OMR);
3052 }
3053 irqs = 0;
3054 irq_mask = 0;
3055 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3056 if (sts < 0) {
3057 next_tick = sts & ~TIMER_CB;
3058 } else {
3059 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3060 lp->media = BNC;
3061 next_tick = dc2114x_autoconf(dev);
3062 } else {
3063 lp->local_state = 1;
3064 de4x5_init_connection(dev);
3065 }
3066 }
3067 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3068 lp->media = AUI_SUSPECT;
3069 next_tick = 3000;
3070 }
3071 break;
f3b197ac 3072
1da177e4
LT		 3073 case AUI_SUSPECT:
3074 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3075 break;
f3b197ac 3076
1da177e4
LT		 3077 case BNC:
3078 switch (lp->local_state) {
3079 case 0:
3080 if (lp->timeout < 0) {
3081 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3082 outl(omr & ~OMR_FDX, DE4X5_OMR);
3083 }
3084 irqs = 0;
3085 irq_mask = 0;
3086 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3087 if (sts < 0) {
3088 next_tick = sts & ~TIMER_CB;
3089 } else {
3090 lp->local_state++; /* Ensure media connected */
3091 next_tick = dc2114x_autoconf(dev);
3092 }
3093 break;
f3b197ac 3094
1da177e4
LT		 3095 case 1:
3096 if (!lp->tx_enable) {
3097 if ((sts = ping_media(dev, 3000)) < 0) {
3098 next_tick = sts & ~TIMER_CB;
3099 } else {
3100 if (sts) {
3101 lp->local_state = 0;
3102 lp->tcount++;
3103 lp->media = INIT;
3104 } else {
3105 de4x5_init_connection(dev);
3106 }
3107 }
3108 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3109 lp->media = BNC_SUSPECT;
3110 next_tick = 3000;
3111 }
3112 break;
3113 }
3114 break;
f3b197ac 3115
1da177e4
LT		 3116 case BNC_SUSPECT:
3117 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3118 break;
f3b197ac 3119
1da177e4
LT		 3120 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3121 if (srom_map_media(dev) < 0) {
3122 lp->tcount++;
3123 lp->media = INIT;
3124 return next_tick;
3125 }
3126 if (lp->media == _100Mb) {
3127 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3128 lp->media = SPD_DET;
3129 return (slnk & ~TIMER_CB);
3130 }
3131 } else {
3132 if (wait_for_link(dev) < 0) {
3133 lp->media = SPD_DET;
3134 return PDET_LINK_WAIT;
3135 }
3136 }
3137 if (lp->media == ANS) { /* Do MII parallel detection */
3138 if (is_spd_100(dev)) {
3139 lp->media = _100Mb;
3140 } else {
3141 lp->media = _10Mb;
3142 }
3143 next_tick = dc2114x_autoconf(dev);
3144 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3145 (((lp->media == _10Mb) || (lp->media == TP) ||
f3b197ac 3146 (lp->media == BNC) || (lp->media == AUI)) &&
1da177e4
LT		 3147 is_10_up(dev))) {
3148 next_tick = dc2114x_autoconf(dev);
3149 } else {
3150 lp->tcount++;
3151 lp->media = INIT;
3152 }
3153 break;
f3b197ac 3154
1da177e4
LT		 3155 case _10Mb:
3156 next_tick = 3000;
3157 if (!lp->tx_enable) {
3158 SET_10Mb;
3159 de4x5_init_connection(dev);
3160 } else {
3161 if (!lp->linkOK && (lp->autosense == AUTO)) {
3162 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3163 lp->media = INIT;
3164 lp->tcount++;
3165 next_tick = DE4X5_AUTOSENSE_MS;
3166 }
3167 }
3168 }
3169 break;
3170
3171 case _100Mb:
3172 next_tick = 3000;
3173 if (!lp->tx_enable) {
3174 SET_100Mb;
3175 de4x5_init_connection(dev);
3176 } else {
3177 if (!lp->linkOK && (lp->autosense == AUTO)) {
3178 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3179 lp->media = INIT;
3180 lp->tcount++;
3181 next_tick = DE4X5_AUTOSENSE_MS;
3182 }
3183 }
3184 }
3185 break;
3186
3187 default:
3188 lp->tcount++;
3189printk("Huh?: media:%02x\n", lp->media);
3190 lp->media = INIT;
3191 break;
3192 }
f3b197ac 3193
1da177e4
LT		 3194 return next_tick;
3195}
3196
3197static int
3198srom_autoconf(struct net_device *dev)
3199{
3200 struct de4x5_private *lp = netdev_priv(dev);
3201
3202 return lp->infoleaf_fn(dev);
3203}
3204
3205/*
3206** This mapping keeps the original media codes and FDX flag unchanged.
3207** While it isn't strictly necessary, it helps me for the moment...
3208** The early return avoids a media state / SROM media space clash.
3209*/
3210static int
3211srom_map_media(struct net_device *dev)
3212{
3213 struct de4x5_private *lp = netdev_priv(dev);
3214
eb034a79 3215 lp->fdx = false;
f3b197ac 3216 if (lp->infoblock_media == lp->media)
1da177e4
LT		 3217 return 0;
3218
3219 switch(lp->infoblock_media) {
3220 case SROM_10BASETF:
3221 if (!lp->params.fdx) return -1;
eb034a79 3222 lp->fdx = true;
1da177e4
LT		 3223 case SROM_10BASET:
3224 if (lp->params.fdx && !lp->fdx) return -1;
3225 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3226 lp->media = _10Mb;
3227 } else {
3228 lp->media = TP;
3229 }
3230 break;
3231
3232 case SROM_10BASE2:
3233 lp->media = BNC;
3234 break;
3235
3236 case SROM_10BASE5:
3237 lp->media = AUI;
3238 break;
3239
3240 case SROM_100BASETF:
3241 if (!lp->params.fdx) return -1;
eb034a79 3242 lp->fdx = true;
1da177e4
LT		 3243 case SROM_100BASET:
3244 if (lp->params.fdx && !lp->fdx) return -1;
3245 lp->media = _100Mb;
3246 break;
3247
3248 case SROM_100BASET4:
3249 lp->media = _100Mb;
3250 break;
3251
3252 case SROM_100BASEFF:
3253 if (!lp->params.fdx) return -1;
eb034a79 3254 lp->fdx = true;
f3b197ac 3255 case SROM_100BASEF:
1da177e4
LT		 3256 if (lp->params.fdx && !lp->fdx) return -1;
3257 lp->media = _100Mb;
3258 break;
3259
3260 case ANS:
3261 lp->media = ANS;
3262 lp->fdx = lp->params.fdx;
3263 break;
3264
f3b197ac
JG		 3265 default:
3266 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
1da177e4
LT		 3267 lp->infoblock_media);
3268 return -1;
3269 break;
3270 }
3271
3272 return 0;
3273}
3274
3275static void
3276de4x5_init_connection(struct net_device *dev)
3277{
3278 struct de4x5_private *lp = netdev_priv(dev);
3279 u_long iobase = dev->base_addr;
3280 u_long flags = 0;
3281
3282 if (lp->media != lp->c_media) {
3283 de4x5_dbg_media(dev);
3284 lp->c_media = lp->media; /* Stop scrolling media messages */
3285 }
3286
3287 spin_lock_irqsave(&lp->lock, flags);
3288 de4x5_rst_desc_ring(dev);
3289 de4x5_setup_intr(dev);
eb034a79 3290 lp->tx_enable = true;
1da177e4
LT		 3291 spin_unlock_irqrestore(&lp->lock, flags);
3292 outl(POLL_DEMAND, DE4X5_TPD);
3293
3294 netif_wake_queue(dev);
3295
3296 return;
3297}
3298
3299/*
3300** General PHY reset function. Some MII devices don't reset correctly
3301** since their MII address pins can float at voltages that are dependent
3302** on the signal pin use. Do a double reset to ensure a reset.
3303*/
3304static int
3305de4x5_reset_phy(struct net_device *dev)
3306{
3307 struct de4x5_private *lp = netdev_priv(dev);
3308 u_long iobase = dev->base_addr;
3309 int next_tick = 0;
3310
3311 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3312 if (lp->timeout < 0) {
3313 if (lp->useSROM) {
3314 if (lp->phy[lp->active].rst) {
3315 srom_exec(dev, lp->phy[lp->active].rst);
3316 srom_exec(dev, lp->phy[lp->active].rst);
3317 } else if (lp->rst) { /* Type 5 infoblock reset */
3318 srom_exec(dev, lp->rst);
3319 srom_exec(dev, lp->rst);
3320 }
3321 } else {
3322 PHY_HARD_RESET;
3323 }
3324 if (lp->useMII) {
3325 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3326 }
3327 }
3328 if (lp->useMII) {
eb034a79 3329 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
1da177e4
LT		 3330 }
3331 } else if (lp->chipset == DC21140) {
3332 PHY_HARD_RESET;
3333 }
3334
3335 return next_tick;
3336}
3337
3338static int
3339test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3340{
3341 struct de4x5_private *lp = netdev_priv(dev);
3342 u_long iobase = dev->base_addr;
3343 s32 sts, csr12;
f3b197ac 3344
1da177e4
LT		 3345 if (lp->timeout < 0) {
3346 lp->timeout = msec/100;
3347 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3348 reset_init_sia(dev, csr13, csr14, csr15);
3349 }
3350
3351 /* set up the interrupt mask */
3352 outl(irq_mask, DE4X5_IMR);
3353
3354 /* clear all pending interrupts */
3355 sts = inl(DE4X5_STS);
3356 outl(sts, DE4X5_STS);
f3b197ac 3357
1da177e4
LT		 3358 /* clear csr12 NRA and SRA bits */
3359 if ((lp->chipset == DC21041) || lp->useSROM) {
3360 csr12 = inl(DE4X5_SISR);
3361 outl(csr12, DE4X5_SISR);
3362 }
3363 }
f3b197ac 3364
1da177e4 3365 sts = inl(DE4X5_STS) & ~TIMER_CB;
f3b197ac 3366
1da177e4
LT		 3367 if (!(sts & irqs) && --lp->timeout) {
3368 sts = 100 | TIMER_CB;
3369 } else {
3370 lp->timeout = -1;
3371 }
f3b197ac 3372
1da177e4
LT		 3373 return sts;
3374}
3375
3376static int
3377test_tp(struct net_device *dev, s32 msec)
3378{
3379 struct de4x5_private *lp = netdev_priv(dev);
3380 u_long iobase = dev->base_addr;
3381 int sisr;
f3b197ac 3382
1da177e4
LT		 3383 if (lp->timeout < 0) {
3384 lp->timeout = msec/100;
3385 }
f3b197ac 3386
1da177e4
LT		 3387 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3388
3389 if (sisr && --lp->timeout) {
3390 sisr = 100 | TIMER_CB;
3391 } else {
3392 lp->timeout = -1;
3393 }
f3b197ac 3394
1da177e4
LT		 3395 return sisr;
3396}
3397
3398/*
3399** Samples the 100Mb Link State Signal. The sample interval is important
3400** because too fast a rate can give erroneous results and confuse the
3401** speed sense algorithm.
3402*/
3403#define SAMPLE_INTERVAL 500 /* ms */
3404#define SAMPLE_DELAY 2000 /* ms */
3405static int
3406test_for_100Mb(struct net_device *dev, int msec)
3407{
3408 struct de4x5_private *lp = netdev_priv(dev);
3409 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3410
3411 if (lp->timeout < 0) {
3412 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3413 if (msec > SAMPLE_DELAY) {
3414 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3415 gep = SAMPLE_DELAY | TIMER_CB;
3416 return gep;
3417 } else {
3418 lp->timeout = msec/SAMPLE_INTERVAL;
3419 }
3420 }
f3b197ac 3421
1da177e4
LT		 3422 if (lp->phy[lp->active].id || lp->useSROM) {
3423 gep = is_100_up(dev) | is_spd_100(dev);
3424 } else {
3425 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3426 }
3427 if (!(gep & ret) && --lp->timeout) {
3428 gep = SAMPLE_INTERVAL | TIMER_CB;
3429 } else {
3430 lp->timeout = -1;
3431 }
f3b197ac 3432
1da177e4
LT		 3433 return gep;
3434}
3435
3436static int
3437wait_for_link(struct net_device *dev)
3438{
3439 struct de4x5_private *lp = netdev_priv(dev);
3440
3441 if (lp->timeout < 0) {
3442 lp->timeout = 1;
3443 }
f3b197ac 3444
1da177e4
LT		 3445 if (lp->timeout--) {
3446 return TIMER_CB;
3447 } else {
3448 lp->timeout = -1;
3449 }
f3b197ac 3450
1da177e4
LT		 3451 return 0;
3452}
3453
3454/*
3455**
3456**
3457*/
3458static int
eb034a79 3459test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
1da177e4
LT		 3460{
3461 struct de4x5_private *lp = netdev_priv(dev);
3462 int test;
3463 u_long iobase = dev->base_addr;
f3b197ac 3464
1da177e4
LT		 3465 if (lp->timeout < 0) {
3466 lp->timeout = msec/100;
3467 }
f3b197ac 3468
1da177e4 3469 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
eb034a79 3470 test = (reg ^ (pol ? ~0 : 0)) & mask;
f3b197ac 3471
1da177e4
LT		 3472 if (test && --lp->timeout) {
3473 reg = 100 | TIMER_CB;
3474 } else {
3475 lp->timeout = -1;
3476 }
f3b197ac 3477
1da177e4
LT		 3478 return reg;
3479}
3480
3481static int
3482is_spd_100(struct net_device *dev)
3483{
3484 struct de4x5_private *lp = netdev_priv(dev);
3485 u_long iobase = dev->base_addr;
3486 int spd;
f3b197ac 3487
1da177e4
LT		 3488 if (lp->useMII) {
3489 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3490 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3491 spd &= lp->phy[lp->active].spd.mask;
3492 } else if (!lp->useSROM) { /* de500-xa */
3493 spd = ((~gep_rd(dev)) & GEP_SLNK);
3494 } else {
3495 if ((lp->ibn == 2) || !lp->asBitValid)
3496 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3497
3498 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3499 (lp->linkOK & ~lp->asBitValid);
3500 }
f3b197ac 3501
1da177e4
LT		 3502 return spd;
3503}
3504
3505static int
3506is_100_up(struct net_device *dev)
3507{
3508 struct de4x5_private *lp = netdev_priv(dev);
3509 u_long iobase = dev->base_addr;
f3b197ac 3510
1da177e4
LT		 3511 if (lp->useMII) {
3512 /* Double read for sticky bits & temporary drops */
3513 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3514 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3515 } else if (!lp->useSROM) { /* de500-xa */
3516 return ((~gep_rd(dev)) & GEP_SLNK);
3517 } else {
3518 if ((lp->ibn == 2) || !lp->asBitValid)
3519 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3520
3521 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3522 (lp->linkOK & ~lp->asBitValid));
3523 }
3524}
3525
3526static int
3527is_10_up(struct net_device *dev)
3528{
3529 struct de4x5_private *lp = netdev_priv(dev);
3530 u_long iobase = dev->base_addr;
f3b197ac 3531
1da177e4
LT		 3532 if (lp->useMII) {
3533 /* Double read for sticky bits & temporary drops */
3534 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3535 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3536 } else if (!lp->useSROM) { /* de500-xa */
3537 return ((~gep_rd(dev)) & GEP_LNP);
3538 } else {
3539 if ((lp->ibn == 2) || !lp->asBitValid)
3540 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3541 (~inl(DE4X5_SISR)&SISR_LS10):
3542 0);
3543
3544 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3545 (lp->linkOK & ~lp->asBitValid));
3546 }
3547}
3548
3549static int
3550is_anc_capable(struct net_device *dev)
3551{
3552 struct de4x5_private *lp = netdev_priv(dev);
3553 u_long iobase = dev->base_addr;
f3b197ac 3554
1da177e4
LT		 3555 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3556 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3557 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3558 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3559 } else {
3560 return 0;
3561 }
3562}
3563
3564/*
3565** Send a packet onto the media and watch for send errors that indicate the
3566** media is bad or unconnected.
3567*/
3568static int
3569ping_media(struct net_device *dev, int msec)
3570{
3571 struct de4x5_private *lp = netdev_priv(dev);
3572 u_long iobase = dev->base_addr;
3573 int sisr;
f3b197ac 3574
1da177e4
LT		 3575 if (lp->timeout < 0) {
3576 lp->timeout = msec/100;
f3b197ac 3577
1da177e4
LT		 3578 lp->tmp = lp->tx_new; /* Remember the ring position */
3579 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3580 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3581 outl(POLL_DEMAND, DE4X5_TPD);
3582 }
f3b197ac 3583
1da177e4
LT		 3584 sisr = inl(DE4X5_SISR);
3585
f3b197ac
JG		 3586 if ((!(sisr & SISR_NCR)) &&
3587 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
1da177e4
LT		 3588 (--lp->timeout)) {
3589 sisr = 100 | TIMER_CB;
3590 } else {
f3b197ac 3591 if ((!(sisr & SISR_NCR)) &&
1da177e4
LT		 3592 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3593 lp->timeout) {
3594 sisr = 0;
3595 } else {
3596 sisr = 1;
3597 }
3598 lp->timeout = -1;
3599 }
f3b197ac 3600
1da177e4
LT		 3601 return sisr;
3602}
3603
3604/*
3605** This function does 2 things: on Intels it kmalloc's another buffer to
3606** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3607** into which the packet is copied.
3608*/
3609static struct sk_buff *
3610de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3611{
3612 struct de4x5_private *lp = netdev_priv(dev);
3613 struct sk_buff *p;
3614
49345103 3615#if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1da177e4
LT		 3616 struct sk_buff *ret;
3617 u_long i=0, tmp;
3618
3619 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3620 if (!p) return NULL;
3621
1da177e4
LT		 3622 tmp = virt_to_bus(p->data);
3623 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3624 skb_reserve(p, i);
3625 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3626
3627 ret = lp->rx_skb[index];
3628 lp->rx_skb[index] = p;
3629
3630 if ((u_long) ret > 1) {
3631 skb_put(ret, len);
3632 }
3633
3634 return ret;
3635
3636#else
3637 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3638
3639 p = dev_alloc_skb(len + 2);
3640 if (!p) return NULL;
3641
1da177e4
LT		 3642 skb_reserve(p, 2); /* Align */
3643 if (index < lp->rx_old) { /* Wrapped buffer */
3644 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3645 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3646 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3647 } else { /* Linear buffer */
3648 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3649 }
f3b197ac 3650
1da177e4
LT		 3651 return p;
3652#endif
3653}
3654
3655static void
3656de4x5_free_rx_buffs(struct net_device *dev)
3657{
3658 struct de4x5_private *lp = netdev_priv(dev);
3659 int i;
3660
3661 for (i=0; i<lp->rxRingSize; i++) {
3662 if ((u_long) lp->rx_skb[i] > 1) {
3663 dev_kfree_skb(lp->rx_skb[i]);
3664 }
3665 lp->rx_ring[i].status = 0;
3666 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3667 }
3668
3669 return;
3670}
3671
3672static void
3673de4x5_free_tx_buffs(struct net_device *dev)
3674{
3675 struct de4x5_private *lp = netdev_priv(dev);
3676 int i;
3677
3678 for (i=0; i<lp->txRingSize; i++) {
3679 if (lp->tx_skb[i])
3680 de4x5_free_tx_buff(lp, i);
3681 lp->tx_ring[i].status = 0;
3682 }
3683
3684 /* Unload the locally queued packets */
2aad7c8e 3685 __skb_queue_purge(&lp->cache.queue);
1da177e4
LT		 3686}
3687
3688/*
3689** When a user pulls a connection, the DECchip can end up in a
3690** 'running - waiting for end of transmission' state. This means that we
3691** have to perform a chip soft reset to ensure that we can synchronize
3692** the hardware and software and make any media probes using a loopback
3693** packet meaningful.
3694*/
3695static void
3696de4x5_save_skbs(struct net_device *dev)
3697{
3698 struct de4x5_private *lp = netdev_priv(dev);
3699 u_long iobase = dev->base_addr;
3700 s32 omr;
3701
3702 if (!lp->cache.save_cnt) {
3703 STOP_DE4X5;
3704 de4x5_tx(dev); /* Flush any sent skb's */
3705 de4x5_free_tx_buffs(dev);
3706 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3707 de4x5_sw_reset(dev);
3708 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3709 lp->cache.save_cnt++;
3710 START_DE4X5;
3711 }
3712
3713 return;
3714}
3715
3716static void
3717de4x5_rst_desc_ring(struct net_device *dev)
3718{
3719 struct de4x5_private *lp = netdev_priv(dev);
3720 u_long iobase = dev->base_addr;
3721 int i;
3722 s32 omr;
3723
3724 if (lp->cache.save_cnt) {
3725 STOP_DE4X5;
3726 outl(lp->dma_rings, DE4X5_RRBA);
3727 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3728 DE4X5_TRBA);
f3b197ac 3729
1da177e4
LT		 3730 lp->rx_new = lp->rx_old = 0;
3731 lp->tx_new = lp->tx_old = 0;
f3b197ac 3732
1da177e4
LT		 3733 for (i = 0; i < lp->rxRingSize; i++) {
3734 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3735 }
f3b197ac 3736
1da177e4
LT		 3737 for (i = 0; i < lp->txRingSize; i++) {
3738 lp->tx_ring[i].status = cpu_to_le32(0);
3739 }
f3b197ac 3740
1da177e4
LT		 3741 barrier();
3742 lp->cache.save_cnt--;
3743 START_DE4X5;
3744 }
f3b197ac 3745
1da177e4
LT		 3746 return;
3747}
3748
3749static void
3750de4x5_cache_state(struct net_device *dev, int flag)
3751{
3752 struct de4x5_private *lp = netdev_priv(dev);
3753 u_long iobase = dev->base_addr;
3754
3755 switch(flag) {
3756 case DE4X5_SAVE_STATE:
3757 lp->cache.csr0 = inl(DE4X5_BMR);
3758 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3759 lp->cache.csr7 = inl(DE4X5_IMR);
3760 break;
3761
3762 case DE4X5_RESTORE_STATE:
3763 outl(lp->cache.csr0, DE4X5_BMR);
3764 outl(lp->cache.csr6, DE4X5_OMR);
3765 outl(lp->cache.csr7, DE4X5_IMR);
3766 if (lp->chipset == DC21140) {
3767 gep_wr(lp->cache.gepc, dev);
3768 gep_wr(lp->cache.gep, dev);
3769 } else {
f3b197ac 3770 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
1da177e4
LT		 3771 lp->cache.csr15);
3772 }
3773 break;
3774 }
3775
3776 return;
3777}
3778
3779static void
3780de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3781{
3782 struct de4x5_private *lp = netdev_priv(dev);
1da177e4 3783
2aad7c8e 3784 __skb_queue_tail(&lp->cache.queue, skb);
1da177e4
LT		 3785}
3786
3787static void
3788de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3789{
3790 struct de4x5_private *lp = netdev_priv(dev);
1da177e4 3791
2aad7c8e 3792 __skb_queue_head(&lp->cache.queue, skb);
1da177e4
LT		 3793}
3794
3795static struct sk_buff *
3796de4x5_get_cache(struct net_device *dev)
3797{
3798 struct de4x5_private *lp = netdev_priv(dev);
1da177e4 3799
2aad7c8e 3800 return __skb_dequeue(&lp->cache.queue);
1da177e4
LT		 3801}
3802
3803/*
3804** Check the Auto Negotiation State. Return OK when a link pass interrupt
3805** is received and the auto-negotiation status is NWAY OK.
3806*/
3807static int
3808test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3809{
3810 struct de4x5_private *lp = netdev_priv(dev);
3811 u_long iobase = dev->base_addr;
3812 s32 sts, ans;
f3b197ac 3813
1da177e4
LT		 3814 if (lp->timeout < 0) {
3815 lp->timeout = msec/100;
3816 outl(irq_mask, DE4X5_IMR);
f3b197ac 3817
1da177e4
LT		 3818 /* clear all pending interrupts */
3819 sts = inl(DE4X5_STS);
3820 outl(sts, DE4X5_STS);
3821 }
f3b197ac 3822
1da177e4
LT		 3823 ans = inl(DE4X5_SISR) & SISR_ANS;
3824 sts = inl(DE4X5_STS) & ~TIMER_CB;
f3b197ac 3825
1da177e4
LT		 3826 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3827 sts = 100 | TIMER_CB;
3828 } else {
3829 lp->timeout = -1;
3830 }
f3b197ac 3831
1da177e4
LT		 3832 return sts;
3833}
3834
3835static void
3836de4x5_setup_intr(struct net_device *dev)
3837{
3838 struct de4x5_private *lp = netdev_priv(dev);
3839 u_long iobase = dev->base_addr;
3840 s32 imr, sts;
f3b197ac 3841
1da177e4
LT		 3842 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3843 imr = 0;
3844 UNMASK_IRQs;
3845 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3846 outl(sts, DE4X5_STS);
3847 ENABLE_IRQs;
3848 }
f3b197ac 3849
1da177e4
LT		 3850 return;
3851}
3852
3853/*
3854**
3855*/
3856static void
3857reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3858{
3859 struct de4x5_private *lp = netdev_priv(dev);
3860 u_long iobase = dev->base_addr;
3861
3862 RESET_SIA;
3863 if (lp->useSROM) {
3864 if (lp->ibn == 3) {
3865 srom_exec(dev, lp->phy[lp->active].rst);
3866 srom_exec(dev, lp->phy[lp->active].gep);
3867 outl(1, DE4X5_SICR);
3868 return;
3869 } else {
3870 csr15 = lp->cache.csr15;
3871 csr14 = lp->cache.csr14;
3872 csr13 = lp->cache.csr13;
3873 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3874 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3875 }
3876 } else {
3877 outl(csr15, DE4X5_SIGR);
3878 }
3879 outl(csr14, DE4X5_STRR);
3880 outl(csr13, DE4X5_SICR);
3881
3882 mdelay(10);
3883
3884 return;
3885}
3886
3887/*
3888** Create a loopback ethernet packet
3889*/
3890static void
3891create_packet(struct net_device *dev, char *frame, int len)
3892{
3893 int i;
3894 char *buf = frame;
f3b197ac 3895
1da177e4
LT		 3896 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3897 *buf++ = dev->dev_addr[i];
3898 }
3899 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3900 *buf++ = dev->dev_addr[i];
3901 }
f3b197ac 3902
1da177e4
LT		 3903 *buf++ = 0; /* Packet length (2 bytes) */
3904 *buf++ = 1;
f3b197ac 3905
1da177e4
LT		 3906 return;
3907}
3908
3909/*
3910** Look for a particular board name in the EISA configuration space
3911*/
3912static int
3913EISA_signature(char *name, struct device *device)
3914{
ff8ac609 3915 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
1da177e4
LT		 3916 struct eisa_device *edev;
3917
3918 *name = '\0';
3919 edev = to_eisa_device (device);
3920 i = edev->id.driver_data;
3921
3922 if (i >= 0 && i < siglen) {
3923 strcpy (name, de4x5_signatures[i]);
3924 status = 1;
3925 }
3926
3927 return status; /* return the device name string */
3928}
3929
3930/*
3931** Look for a particular board name in the PCI configuration space
3932*/
3933static int
3934PCI_signature(char *name, struct de4x5_private *lp)
3935{
ff8ac609 3936 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
f3b197ac 3937
1da177e4
LT		 3938 if (lp->chipset == DC21040) {
3939 strcpy(name, "DE434/5");
3940 return status;
3941 } else { /* Search for a DEC name in the SROM */
de2f19da
HE		 3942 int tmp = *((char *)&lp->srom + 19) * 3;
3943 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
1da177e4
LT		 3944 }
3945 name[8] = '\0';
3946 for (i=0; i<siglen; i++) {
3947 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3948 }
3949 if (i == siglen) {
3950 if (dec_only) {
3951 *name = '\0';
3952 } else { /* Use chip name to avoid confusion */
3953 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3954 ((lp->chipset == DC21041) ? "DC21041" :
3955 ((lp->chipset == DC21140) ? "DC21140" :
3956 ((lp->chipset == DC21142) ? "DC21142" :
3957 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3958 )))))));
3959 }
3960 if (lp->chipset != DC21041) {
eb034a79 3961 lp->useSROM = true; /* card is not recognisably DEC */
1da177e4
LT		 3962 }
3963 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
eb034a79 3964 lp->useSROM = true;
1da177e4 3965 }
f3b197ac 3966
1da177e4
LT		 3967 return status;
3968}
3969
3970/*
3971** Set up the Ethernet PROM counter to the start of the Ethernet address on
3972** the DC21040, else read the SROM for the other chips.
3973** The SROM may not be present in a multi-MAC card, so first read the
3974** MAC address and check for a bad address. If there is a bad one then exit
3975** immediately with the prior srom contents intact (the h/w address will
3976** be fixed up later).
3977*/
3978static void
3979DevicePresent(struct net_device *dev, u_long aprom_addr)
3980{
3981 int i, j=0;
3982 struct de4x5_private *lp = netdev_priv(dev);
f3b197ac 3983
1da177e4
LT		 3984 if (lp->chipset == DC21040) {
3985 if (lp->bus == EISA) {
3986 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3987 } else {
3988 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
3989 }
3990 } else { /* Read new srom */
561b4fbf
AV		 3991 u_short tmp;
3992 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
1da177e4
LT		 3993 for (i=0; i<(ETH_ALEN>>1); i++) {
3994 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
561b4fbf
AV		 3995 j += tmp; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3996 *p = cpu_to_le16(tmp);
1da177e4 3997 }
561b4fbf
AV		 3998 if (j == 0 || j == 3 * 0xffff) {
3999 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
4000 return;
1da177e4
LT		 4001 }
4002
561b4fbf 4003 p = (__le16 *)&lp->srom;
1da177e4
LT		 4004 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4005 tmp = srom_rd(aprom_addr, i);
561b4fbf 4006 *p++ = cpu_to_le16(tmp);
1da177e4
LT		 4007 }
4008 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4009 }
f3b197ac 4010
1da177e4
LT		 4011 return;
4012}
4013
4014/*
4015** Since the write on the Enet PROM register doesn't seem to reset the PROM
4016** pointer correctly (at least on my DE425 EISA card), this routine should do
4017** it...from depca.c.
4018*/
4019static void
4020enet_addr_rst(u_long aprom_addr)
4021{
4022 union {
4023 struct {
4024 u32 a;
4025 u32 b;
4026 } llsig;
4027 char Sig[sizeof(u32) << 1];
4028 } dev;
4029 short sigLength=0;
4030 s8 data;
4031 int i, j;
f3b197ac 4032
1da177e4
LT		 4033 dev.llsig.a = ETH_PROM_SIG;
4034 dev.llsig.b = ETH_PROM_SIG;
4035 sigLength = sizeof(u32) << 1;
f3b197ac 4036
1da177e4
LT		 4037 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4038 data = inb(aprom_addr);
4039 if (dev.Sig[j] == data) { /* track signature */
4040 j++;
4041 } else { /* lost signature; begin search again */
4042 if (data == dev.Sig[0]) { /* rare case.... */
4043 j=1;
4044 } else {
4045 j=0;
4046 }
4047 }
4048 }
f3b197ac 4049
1da177e4
LT		 4050 return;
4051}
4052
4053/*
4054** For the bad status case and no SROM, then add one to the previous
4055** address. However, need to add one backwards in case we have 0xff
4056** as one or more of the bytes. Only the last 3 bytes should be checked
4057** as the first three are invariant - assigned to an organisation.
4058*/
4059static int
4060get_hw_addr(struct net_device *dev)
4061{
4062 u_long iobase = dev->base_addr;
4063 int broken, i, k, tmp, status = 0;
4064 u_short j,chksum;
4065 struct de4x5_private *lp = netdev_priv(dev);
4066
4067 broken = de4x5_bad_srom(lp);
4068
4069 for (i=0,k=0,j=0;j<3;j++) {
4070 k <<= 1;
4071 if (k > 0xffff) k-=0xffff;
f3b197ac 4072
1da177e4
LT		 4073 if (lp->bus == PCI) {
4074 if (lp->chipset == DC21040) {
4075 while ((tmp = inl(DE4X5_APROM)) < 0);
4076 k += (u_char) tmp;
4077 dev->dev_addr[i++] = (u_char) tmp;
4078 while ((tmp = inl(DE4X5_APROM)) < 0);
4079 k += (u_short) (tmp << 8);
4080 dev->dev_addr[i++] = (u_char) tmp;
4081 } else if (!broken) {
4082 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4083 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4084 } else if ((broken == SMC) || (broken == ACCTON)) {
4085 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4086 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4087 }
4088 } else {
4089 k += (u_char) (tmp = inb(EISA_APROM));
4090 dev->dev_addr[i++] = (u_char) tmp;
4091 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4092 dev->dev_addr[i++] = (u_char) tmp;
4093 }
f3b197ac 4094
1da177e4
LT		 4095 if (k > 0xffff) k-=0xffff;
4096 }
4097 if (k == 0xffff) k=0;
f3b197ac 4098
1da177e4
LT		 4099 if (lp->bus == PCI) {
4100 if (lp->chipset == DC21040) {
4101 while ((tmp = inl(DE4X5_APROM)) < 0);
4102 chksum = (u_char) tmp;
4103 while ((tmp = inl(DE4X5_APROM)) < 0);
4104 chksum |= (u_short) (tmp << 8);
4105 if ((k != chksum) && (dec_only)) status = -1;
4106 }
4107 } else {
4108 chksum = (u_char) inb(EISA_APROM);
4109 chksum |= (u_short) (inb(EISA_APROM) << 8);
4110 if ((k != chksum) && (dec_only)) status = -1;
4111 }
4112
4113 /* If possible, try to fix a broken card - SMC only so far */
4114 srom_repair(dev, broken);
4115
bfaadcad 4116#ifdef CONFIG_PPC_PMAC
f3b197ac 4117 /*
1da177e4
LT		 4118 ** If the address starts with 00 a0, we have to bit-reverse
4119 ** each byte of the address.
4120 */
e8222502 4121 if ( machine_is(powermac) &&
1da177e4
LT		 4122 (dev->dev_addr[0] == 0) &&
4123 (dev->dev_addr[1] == 0xa0) )
4124 {
4125 for (i = 0; i < ETH_ALEN; ++i)
4126 {
4127 int x = dev->dev_addr[i];
4128 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4129 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4130 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4131 }
4132 }
bfaadcad 4133#endif /* CONFIG_PPC_PMAC */
1da177e4
LT		 4134
4135 /* Test for a bad enet address */
4136 status = test_bad_enet(dev, status);
4137
4138 return status;
4139}
4140
4141/*
4142** Test for enet addresses in the first 32 bytes. The built-in strncmp
4143** didn't seem to work here...?
4144*/
4145static int
4146de4x5_bad_srom(struct de4x5_private *lp)
4147{
4148 int i, status = 0;
4149
cba0516d 4150 for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
1da177e4
LT		 4151 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4152 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4153 if (i == 0) {
4154 status = SMC;
4155 } else if (i == 1) {
4156 status = ACCTON;
4157 }
4158 break;
4159 }
4160 }
4161
4162 return status;
4163}
4164
4165static int
4166de4x5_strncmp(char *a, char *b, int n)
4167{
4168 int ret=0;
4169
cba0516d 4170 for (;n && !ret; n--) {
1da177e4
LT		 4171 ret = *a++ - *b++;
4172 }
4173
4174 return ret;
4175}
4176
4177static void
4178srom_repair(struct net_device *dev, int card)
4179{
4180 struct de4x5_private *lp = netdev_priv(dev);
4181
4182 switch(card) {
4183 case SMC:
4184 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4185 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4186 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
eb034a79 4187 lp->useSROM = true;
1da177e4
LT		 4188 break;
4189 }
4190
4191 return;
4192}
4193
4194/*
4195** Assume that the irq's do not follow the PCI spec - this is seems
4196** to be true so far (2 for 2).
4197*/
4198static int
4199test_bad_enet(struct net_device *dev, int status)
4200{
4201 struct de4x5_private *lp = netdev_priv(dev);
4202 int i, tmp;
4203
4204 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4205 if ((tmp == 0) || (tmp == 0x5fa)) {
f3b197ac 4206 if ((lp->chipset == last.chipset) &&
1da177e4
LT		 4207 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4208 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4209 for (i=ETH_ALEN-1; i>2; --i) {
4210 dev->dev_addr[i] += 1;
4211 if (dev->dev_addr[i] != 0) break;
4212 }
4213 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4214 if (!an_exception(lp)) {
4215 dev->irq = last.irq;
4216 }
4217
4218 status = 0;
4219 }
4220 } else if (!status) {
4221 last.chipset = lp->chipset;
4222 last.bus = lp->bus_num;
4223 last.irq = dev->irq;
4224 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4225 }
4226
4227 return status;
4228}
4229
4230/*
4231** List of board exceptions with correctly wired IRQs
4232*/
4233static int
4234an_exception(struct de4x5_private *lp)
4235{
f3b197ac 4236 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
1da177e4
LT		 4237 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4238 return -1;
4239 }
4240
4241 return 0;
4242}
4243
4244/*
4245** SROM Read
4246*/
4247static short
4248srom_rd(u_long addr, u_char offset)
4249{
4250 sendto_srom(SROM_RD | SROM_SR, addr);
f3b197ac 4251
1da177e4
LT		 4252 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4253 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4254 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
f3b197ac 4255
1da177e4
LT		 4256 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4257}
4258
4259static void
4260srom_latch(u_int command, u_long addr)
4261{
4262 sendto_srom(command, addr);
4263 sendto_srom(command | DT_CLK, addr);
4264 sendto_srom(command, addr);
f3b197ac 4265
1da177e4
LT		 4266 return;
4267}
4268
4269static void
4270srom_command(u_int command, u_long addr)
4271{
4272 srom_latch(command, addr);
4273 srom_latch(command, addr);
4274 srom_latch((command & 0x0000ff00) | DT_CS, addr);
f3b197ac 4275
1da177e4
LT		 4276 return;
4277}
4278
4279static void
4280srom_address(u_int command, u_long addr, u_char offset)
4281{
4282 int i, a;
f3b197ac 4283
1da177e4
LT		 4284 a = offset << 2;
4285 for (i=0; i<6; i++, a <<= 1) {
4286 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4287 }
4288 udelay(1);
f3b197ac 4289
1da177e4 4290 i = (getfrom_srom(addr) >> 3) & 0x01;
f3b197ac 4291
1da177e4
LT		 4292 return;
4293}
4294
4295static short
4296srom_data(u_int command, u_long addr)
4297{
4298 int i;
4299 short word = 0;
4300 s32 tmp;
f3b197ac 4301
1da177e4
LT		 4302 for (i=0; i<16; i++) {
4303 sendto_srom(command | DT_CLK, addr);
4304 tmp = getfrom_srom(addr);
4305 sendto_srom(command, addr);
f3b197ac 4306
1da177e4
LT		 4307 word = (word << 1) | ((tmp >> 3) & 0x01);
4308 }
f3b197ac 4309
1da177e4 4310 sendto_srom(command & 0x0000ff00, addr);
f3b197ac 4311
1da177e4
LT		 4312 return word;
4313}
4314
4315/*
4316static void
4317srom_busy(u_int command, u_long addr)
4318{
4319 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
f3b197ac 4320
1da177e4
LT		 4321 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4322 mdelay(1);
4323 }
f3b197ac 4324
1da177e4 4325 sendto_srom(command & 0x0000ff00, addr);
f3b197ac 4326
1da177e4
LT		 4327 return;
4328}
4329*/
4330
4331static void
4332sendto_srom(u_int command, u_long addr)
4333{
4334 outl(command, addr);
4335 udelay(1);
f3b197ac 4336
1da177e4
LT		 4337 return;
4338}
4339
4340static int
4341getfrom_srom(u_long addr)
4342{
4343 s32 tmp;
f3b197ac 4344
1da177e4
LT		 4345 tmp = inl(addr);
4346 udelay(1);
f3b197ac 4347
1da177e4
LT		 4348 return tmp;
4349}
4350
4351static int
4352srom_infoleaf_info(struct net_device *dev)
4353{
4354 struct de4x5_private *lp = netdev_priv(dev);
4355 int i, count;
4356 u_char *p;
4357
4358 /* Find the infoleaf decoder function that matches this chipset */
4359 for (i=0; i<INFOLEAF_SIZE; i++) {
4360 if (lp->chipset == infoleaf_array[i].chipset) break;
4361 }
4362 if (i == INFOLEAF_SIZE) {
eb034a79 4363 lp->useSROM = false;
f3b197ac 4364 printk("%s: Cannot find correct chipset for SROM decoding!\n",
1da177e4
LT		 4365 dev->name);
4366 return -ENXIO;
4367 }
4368
4369 lp->infoleaf_fn = infoleaf_array[i].fn;
4370
4371 /* Find the information offset that this function should use */
4372 count = *((u_char *)&lp->srom + 19);
4373 p = (u_char *)&lp->srom + 26;
4374
4375 if (count > 1) {
4376 for (i=count; i; --i, p+=3) {
4377 if (lp->device == *p) break;
4378 }
4379 if (i == 0) {
eb034a79 4380 lp->useSROM = false;
f3b197ac 4381 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
1da177e4
LT		 4382 dev->name, lp->device);
4383 return -ENXIO;
4384 }
4385 }
4386
6caf52a4 4387 lp->infoleaf_offset = get_unaligned_le16(p + 1);
1da177e4
LT		 4388
4389 return 0;
4390}
4391
4392/*
4393** This routine loads any type 1 or 3 MII info into the mii device
4394** struct and executes any type 5 code to reset PHY devices for this
4395** controller.
4396** The info for the MII devices will be valid since the index used
4397** will follow the discovery process from MII address 1-31 then 0.
4398*/
4399static void
4400srom_init(struct net_device *dev)
4401{
4402 struct de4x5_private *lp = netdev_priv(dev);
4403 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4404 u_char count;
4405
4406 p+=2;
4407 if (lp->chipset == DC21140) {
4408 lp->cache.gepc = (*p++ | GEP_CTRL);
4409 gep_wr(lp->cache.gepc, dev);
4410 }
4411
4412 /* Block count */
4413 count = *p++;
4414
4415 /* Jump the infoblocks to find types */
4416 for (;count; --count) {
4417 if (*p < 128) {
4418 p += COMPACT_LEN;
4419 } else if (*(p+1) == 5) {
4420 type5_infoblock(dev, 1, p);
4421 p += ((*p & BLOCK_LEN) + 1);
4422 } else if (*(p+1) == 4) {
4423 p += ((*p & BLOCK_LEN) + 1);
4424 } else if (*(p+1) == 3) {
4425 type3_infoblock(dev, 1, p);
4426 p += ((*p & BLOCK_LEN) + 1);
4427 } else if (*(p+1) == 2) {
4428 p += ((*p & BLOCK_LEN) + 1);
4429 } else if (*(p+1) == 1) {
4430 type1_infoblock(dev, 1, p);
4431 p += ((*p & BLOCK_LEN) + 1);
4432 } else {
4433 p += ((*p & BLOCK_LEN) + 1);
4434 }
4435 }
4436
4437 return;
4438}
4439
4440/*
4441** A generic routine that writes GEP control, data and reset information
4442** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4443*/
4444static void
4445srom_exec(struct net_device *dev, u_char *p)
4446{
4447 struct de4x5_private *lp = netdev_priv(dev);
4448 u_long iobase = dev->base_addr;
4449 u_char count = (p ? *p++ : 0);
4450 u_short *w = (u_short *)p;
4451
4452 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4453
4454 if (lp->chipset != DC21140) RESET_SIA;
f3b197ac 4455
1da177e4 4456 while (count--) {
f3b197ac 4457 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
6caf52a4 4458 *p++ : get_unaligned_le16(w++)), dev);
1da177e4
LT		 4459 mdelay(2); /* 2ms per action */
4460 }
4461
4462 if (lp->chipset != DC21140) {
4463 outl(lp->cache.csr14, DE4X5_STRR);
4464 outl(lp->cache.csr13, DE4X5_SICR);
4465 }
4466
4467 return;
4468}
4469
4470/*
4471** Basically this function is a NOP since it will never be called,
4472** unless I implement the DC21041 SROM functions. There's no need
4473** since the existing code will be satisfactory for all boards.
4474*/
f3b197ac 4475static int
1da177e4
LT		 4476dc21041_infoleaf(struct net_device *dev)
4477{
4478 return DE4X5_AUTOSENSE_MS;
4479}
4480
f3b197ac 4481static int
1da177e4
LT		 4482dc21140_infoleaf(struct net_device *dev)
4483{
4484 struct de4x5_private *lp = netdev_priv(dev);
4485 u_char count = 0;
4486 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4487 int next_tick = DE4X5_AUTOSENSE_MS;
4488
4489 /* Read the connection type */
4490 p+=2;
4491
4492 /* GEP control */
4493 lp->cache.gepc = (*p++ | GEP_CTRL);
4494
4495 /* Block count */
4496 count = *p++;
4497
4498 /* Recursively figure out the info blocks */
4499 if (*p < 128) {
4500 next_tick = dc_infoblock[COMPACT](dev, count, p);
4501 } else {
4502 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4503 }
4504
4505 if (lp->tcount == count) {
4506 lp->media = NC;
4507 if (lp->media != lp->c_media) {
4508 de4x5_dbg_media(dev);
4509 lp->c_media = lp->media;
4510 }
4511 lp->media = INIT;
4512 lp->tcount = 0;
eb034a79 4513 lp->tx_enable = false;
1da177e4
LT		 4514 }
4515
4516 return next_tick & ~TIMER_CB;
4517}
4518
f3b197ac 4519static int
1da177e4
LT		 4520dc21142_infoleaf(struct net_device *dev)
4521{
4522 struct de4x5_private *lp = netdev_priv(dev);
4523 u_char count = 0;
4524 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4525 int next_tick = DE4X5_AUTOSENSE_MS;
4526
4527 /* Read the connection type */
4528 p+=2;
4529
4530 /* Block count */
4531 count = *p++;
4532
4533 /* Recursively figure out the info blocks */
4534 if (*p < 128) {
4535 next_tick = dc_infoblock[COMPACT](dev, count, p);
4536 } else {
4537 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4538 }
4539
4540 if (lp->tcount == count) {
4541 lp->media = NC;
4542 if (lp->media != lp->c_media) {
4543 de4x5_dbg_media(dev);
4544 lp->c_media = lp->media;
4545 }
4546 lp->media = INIT;
4547 lp->tcount = 0;
eb034a79 4548 lp->tx_enable = false;
1da177e4
LT		 4549 }
4550
4551 return next_tick & ~TIMER_CB;
4552}
4553
f3b197ac 4554static int
1da177e4
LT		 4555dc21143_infoleaf(struct net_device *dev)
4556{
4557 struct de4x5_private *lp = netdev_priv(dev);
4558 u_char count = 0;
4559 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4560 int next_tick = DE4X5_AUTOSENSE_MS;
4561
4562 /* Read the connection type */
4563 p+=2;
4564
4565 /* Block count */
4566 count = *p++;
4567
4568 /* Recursively figure out the info blocks */
4569 if (*p < 128) {
4570 next_tick = dc_infoblock[COMPACT](dev, count, p);
4571 } else {
4572 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4573 }
4574 if (lp->tcount == count) {
4575 lp->media = NC;
4576 if (lp->media != lp->c_media) {
4577 de4x5_dbg_media(dev);
4578 lp->c_media = lp->media;
4579 }
4580 lp->media = INIT;
4581 lp->tcount = 0;
eb034a79 4582 lp->tx_enable = false;
1da177e4
LT		 4583 }
4584
4585 return next_tick & ~TIMER_CB;
4586}
4587
4588/*
4589** The compact infoblock is only designed for DC21140[A] chips, so
4590** we'll reuse the dc21140m_autoconf function. Non MII media only.
4591*/
f3b197ac 4592static int
1da177e4
LT		 4593compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4594{
4595 struct de4x5_private *lp = netdev_priv(dev);
4596 u_char flags, csr6;
4597
4598 /* Recursively figure out the info blocks */
4599 if (--count > lp->tcount) {
4600 if (*(p+COMPACT_LEN) < 128) {
4601 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4602 } else {
4603 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4604 }
4605 }
4606
4607 if ((lp->media == INIT) && (lp->timeout < 0)) {
4608 lp->ibn = COMPACT;
4609 lp->active = 0;
4610 gep_wr(lp->cache.gepc, dev);
4611 lp->infoblock_media = (*p++) & COMPACT_MC;
4612 lp->cache.gep = *p++;
4613 csr6 = *p++;
4614 flags = *p++;
4615
4616 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4617 lp->defMedium = (flags & 0x40) ? -1 : 0;
4618 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4619 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4620 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
eb034a79 4621 lp->useMII = false;
1da177e4
LT		 4622
4623 de4x5_switch_mac_port(dev);
4624 }
4625
4626 return dc21140m_autoconf(dev);
4627}
4628
4629/*
4630** This block describes non MII media for the DC21140[A] only.
4631*/
f3b197ac 4632static int
1da177e4
LT		 4633type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4634{
4635 struct de4x5_private *lp = netdev_priv(dev);
4636 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4637
4638 /* Recursively figure out the info blocks */
4639 if (--count > lp->tcount) {
4640 if (*(p+len) < 128) {
4641 return dc_infoblock[COMPACT](dev, count, p+len);
4642 } else {
4643 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4644 }
4645 }
4646
4647 if ((lp->media == INIT) && (lp->timeout < 0)) {
4648 lp->ibn = 0;
4649 lp->active = 0;
4650 gep_wr(lp->cache.gepc, dev);
4651 p+=2;
4652 lp->infoblock_media = (*p++) & BLOCK0_MC;
4653 lp->cache.gep = *p++;
4654 csr6 = *p++;
4655 flags = *p++;
4656
4657 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4658 lp->defMedium = (flags & 0x40) ? -1 : 0;
4659 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4660 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4661 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
eb034a79 4662 lp->useMII = false;
1da177e4
LT		 4663
4664 de4x5_switch_mac_port(dev);
4665 }
4666
4667 return dc21140m_autoconf(dev);
4668}
4669
4670/* These functions are under construction! */
4671
f3b197ac 4672static int
1da177e4
LT		 4673type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4674{
4675 struct de4x5_private *lp = netdev_priv(dev);
4676 u_char len = (*p & BLOCK_LEN)+1;
4677
4678 /* Recursively figure out the info blocks */
4679 if (--count > lp->tcount) {
4680 if (*(p+len) < 128) {
4681 return dc_infoblock[COMPACT](dev, count, p+len);
4682 } else {
4683 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4684 }
4685 }
4686
4687 p += 2;
4688 if (lp->state == INITIALISED) {
4689 lp->ibn = 1;
4690 lp->active = *p++;
4691 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4692 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
6caf52a4
HH		 4693 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4694 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4695 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4696 lp->phy[lp->active].ttm = get_unaligned_le16(p);
1da177e4
LT		 4697 return 0;
4698 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4699 lp->ibn = 1;
4700 lp->active = *p;
4701 lp->infoblock_csr6 = OMR_MII_100;
eb034a79 4702 lp->useMII = true;
1da177e4
LT		 4703 lp->infoblock_media = ANS;
4704
4705 de4x5_switch_mac_port(dev);
4706 }
4707
4708 return dc21140m_autoconf(dev);
4709}
4710
f3b197ac 4711static int
1da177e4
LT		 4712type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4713{
4714 struct de4x5_private *lp = netdev_priv(dev);
4715 u_char len = (*p & BLOCK_LEN)+1;
4716
4717 /* Recursively figure out the info blocks */
4718 if (--count > lp->tcount) {
4719 if (*(p+len) < 128) {
4720 return dc_infoblock[COMPACT](dev, count, p+len);
4721 } else {
4722 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4723 }
4724 }
4725
4726 if ((lp->media == INIT) && (lp->timeout < 0)) {
4727 lp->ibn = 2;
4728 lp->active = 0;
4729 p += 2;
4730 lp->infoblock_media = (*p) & MEDIA_CODE;
4731
4732 if ((*p++) & EXT_FIELD) {
6caf52a4
HH		 4733 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4734 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4735 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
1da177e4
LT		 4736 } else {
4737 lp->cache.csr13 = CSR13;
4738 lp->cache.csr14 = CSR14;
4739 lp->cache.csr15 = CSR15;
4740 }
6caf52a4
HH		 4741 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4742 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
1da177e4 4743 lp->infoblock_csr6 = OMR_SIA;
eb034a79 4744 lp->useMII = false;
1da177e4
LT		 4745
4746 de4x5_switch_mac_port(dev);
4747 }
4748
4749 return dc2114x_autoconf(dev);
4750}
4751
f3b197ac 4752static int
1da177e4
LT		 4753type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4754{
4755 struct de4x5_private *lp = netdev_priv(dev);
4756 u_char len = (*p & BLOCK_LEN)+1;
4757
4758 /* Recursively figure out the info blocks */
4759 if (--count > lp->tcount) {
4760 if (*(p+len) < 128) {
4761 return dc_infoblock[COMPACT](dev, count, p+len);
4762 } else {
4763 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4764 }
4765 }
4766
4767 p += 2;
4768 if (lp->state == INITIALISED) {
4769 lp->ibn = 3;
4770 lp->active = *p++;
4771 if (MOTO_SROM_BUG) lp->active = 0;
4772 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4773 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
6caf52a4
HH		 4774 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4775 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4776 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4777 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
1da177e4
LT		 4778 lp->phy[lp->active].mci = *p;
4779 return 0;
4780 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4781 lp->ibn = 3;
4782 lp->active = *p;
4783 if (MOTO_SROM_BUG) lp->active = 0;
4784 lp->infoblock_csr6 = OMR_MII_100;
eb034a79 4785 lp->useMII = true;
1da177e4
LT		 4786 lp->infoblock_media = ANS;
4787
4788 de4x5_switch_mac_port(dev);
4789 }
4790
4791 return dc2114x_autoconf(dev);
4792}
4793
f3b197ac 4794static int
1da177e4
LT		 4795type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4796{
4797 struct de4x5_private *lp = netdev_priv(dev);
4798 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4799
4800 /* Recursively figure out the info blocks */
4801 if (--count > lp->tcount) {
4802 if (*(p+len) < 128) {
4803 return dc_infoblock[COMPACT](dev, count, p+len);
4804 } else {
4805 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4806 }
4807 }
4808
4809 if ((lp->media == INIT) && (lp->timeout < 0)) {
4810 lp->ibn = 4;
4811 lp->active = 0;
4812 p+=2;
4813 lp->infoblock_media = (*p++) & MEDIA_CODE;
4814 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4815 lp->cache.csr14 = CSR14;
4816 lp->cache.csr15 = CSR15;
6caf52a4
HH		 4817 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4818 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
1da177e4
LT		 4819 csr6 = *p++;
4820 flags = *p++;
4821
4822 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4823 lp->defMedium = (flags & 0x40) ? -1 : 0;
4824 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4825 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4826 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
eb034a79 4827 lp->useMII = false;
1da177e4
LT		 4828
4829 de4x5_switch_mac_port(dev);
4830 }
4831
4832 return dc2114x_autoconf(dev);
4833}
4834
4835/*
4836** This block type provides information for resetting external devices
4837** (chips) through the General Purpose Register.
4838*/
f3b197ac 4839static int
1da177e4
LT		 4840type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4841{
4842 struct de4x5_private *lp = netdev_priv(dev);
4843 u_char len = (*p & BLOCK_LEN)+1;
4844
4845 /* Recursively figure out the info blocks */
4846 if (--count > lp->tcount) {
4847 if (*(p+len) < 128) {
4848 return dc_infoblock[COMPACT](dev, count, p+len);
4849 } else {
4850 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4851 }
4852 }
4853
4854 /* Must be initializing to run this code */
4855 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4856 p+=2;
4857 lp->rst = p;
4858 srom_exec(dev, lp->rst);
4859 }
4860
4861 return DE4X5_AUTOSENSE_MS;
4862}
4863
4864/*
4865** MII Read/Write
4866*/
4867
4868static int
4869mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4870{
4871 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4872 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4873 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4874 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4875 mii_address(phyreg, ioaddr); /* PHY Register to read */
4876 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
f3b197ac 4877
1da177e4
LT		 4878 return mii_rdata(ioaddr); /* Read data */
4879}
4880
4881static void
4882mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4883{
4884 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4885 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4886 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4887 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4888 mii_address(phyreg, ioaddr); /* PHY Register to write */
4889 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4890 data = mii_swap(data, 16); /* Swap data bit ordering */
4891 mii_wdata(data, 16, ioaddr); /* Write data */
f3b197ac 4892
1da177e4
LT		 4893 return;
4894}
4895
4896static int
4897mii_rdata(u_long ioaddr)
4898{
4899 int i;
4900 s32 tmp = 0;
f3b197ac 4901
1da177e4
LT		 4902 for (i=0; i<16; i++) {
4903 tmp <<= 1;
4904 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4905 }
f3b197ac 4906
1da177e4
LT		 4907 return tmp;
4908}
4909
4910static void
4911mii_wdata(int data, int len, u_long ioaddr)
4912{
4913 int i;
f3b197ac 4914
1da177e4
LT		 4915 for (i=0; i<len; i++) {
4916 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4917 data >>= 1;
4918 }
f3b197ac 4919
1da177e4
LT		 4920 return;
4921}
4922
4923static void
4924mii_address(u_char addr, u_long ioaddr)
4925{
4926 int i;
f3b197ac 4927
1da177e4
LT		 4928 addr = mii_swap(addr, 5);
4929 for (i=0; i<5; i++) {
4930 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4931 addr >>= 1;
4932 }
f3b197ac 4933
1da177e4
LT		 4934 return;
4935}
4936
4937static void
4938mii_ta(u_long rw, u_long ioaddr)
4939{
4940 if (rw == MII_STWR) {
f3b197ac
JG		 4941 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4942 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
1da177e4
LT		 4943 } else {
4944 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4945 }
f3b197ac 4946
1da177e4
LT		 4947 return;
4948}
4949
4950static int
4951mii_swap(int data, int len)
4952{
4953 int i, tmp = 0;
f3b197ac 4954
1da177e4
LT		 4955 for (i=0; i<len; i++) {
4956 tmp <<= 1;
4957 tmp |= (data & 1);
4958 data >>= 1;
4959 }
f3b197ac 4960
1da177e4
LT		 4961 return tmp;
4962}
4963
4964static void
4965sendto_mii(u32 command, int data, u_long ioaddr)
4966{
4967 u32 j;
f3b197ac 4968
1da177e4
LT		 4969 j = (data & 1) << 17;
4970 outl(command | j, ioaddr);
4971 udelay(1);
4972 outl(command | MII_MDC | j, ioaddr);
4973 udelay(1);
f3b197ac 4974
1da177e4
LT		 4975 return;
4976}
4977
4978static int
4979getfrom_mii(u32 command, u_long ioaddr)
4980{
4981 outl(command, ioaddr);
4982 udelay(1);
4983 outl(command | MII_MDC, ioaddr);
4984 udelay(1);
f3b197ac 4985
1da177e4
LT		 4986 return ((inl(ioaddr) >> 19) & 1);
4987}
4988
4989/*
4990** Here's 3 ways to calculate the OUI from the ID registers.
4991*/
4992static int
4993mii_get_oui(u_char phyaddr, u_long ioaddr)
4994{
4995/*
4996 union {
4997 u_short reg;
4998 u_char breg[2];
4999 } a;
5000 int i, r2, r3, ret=0;*/
5001 int r2, r3;
5002
5003 /* Read r2 and r3 */
5004 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5005 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5006 /* SEEQ and Cypress way * /
5007 / * Shuffle r2 and r3 * /
5008 a.reg=0;
5009 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5010 r2 = ((r2>>2)&0x3fff);
5011
5012 / * Bit reverse r3 * /
5013 for (i=0;i<8;i++) {
5014 ret<<=1;
5015 ret |= (r3&1);
5016 r3>>=1;
5017 }
5018
5019 / * Bit reverse r2 * /
5020 for (i=0;i<16;i++) {
5021 a.reg<<=1;
5022 a.reg |= (r2&1);
5023 r2>>=1;
5024 }
5025
5026 / * Swap r2 bytes * /
5027 i=a.breg[0];
5028 a.breg[0]=a.breg[1];
5029 a.breg[1]=i;
5030
5031 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5032/* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5033 return r2; /* (I did it) My way */
5034}
5035
5036/*
5037** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5038*/
5039static int
5040mii_get_phy(struct net_device *dev)
5041{
5042 struct de4x5_private *lp = netdev_priv(dev);
5043 u_long iobase = dev->base_addr;
ff8ac609 5044 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
1da177e4 5045 int id;
f3b197ac 5046
1da177e4 5047 lp->active = 0;
eb034a79 5048 lp->useMII = true;
1da177e4
LT		 5049
5050 /* Search the MII address space for possible PHY devices */
5051 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5052 lp->phy[lp->active].addr = i;
5053 if (i==0) n++; /* Count cycles */
5054 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
f3b197ac 5055 id = mii_get_oui(i, DE4X5_MII);
1da177e4
LT		 5056 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5057 for (j=0; j<limit; j++) { /* Search PHY table */
5058 if (id != phy_info[j].id) continue; /* ID match? */
1b994b5a 5059 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
1da177e4
LT		 5060 if (k < DE4X5_MAX_PHY) {
5061 memcpy((char *)&lp->phy[k],
5062 (char *)&phy_info[j], sizeof(struct phy_table));
5063 lp->phy[k].addr = i;
5064 lp->mii_cnt++;
5065 lp->active++;
5066 } else {
5067 goto purgatory; /* Stop the search */
5068 }
5069 break;
5070 }
5071 if ((j == limit) && (i < DE4X5_MAX_MII)) {
1b994b5a 5072 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
1da177e4
LT		 5073 lp->phy[k].addr = i;
5074 lp->phy[k].id = id;
5075 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5076 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5077 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5078 lp->mii_cnt++;
5079 lp->active++;
c2bb1b9c 5080 printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name);
1da177e4
LT		 5081 j = de4x5_debug;
5082 de4x5_debug |= DEBUG_MII;
5083 de4x5_dbg_mii(dev, k);
5084 de4x5_debug = j;
5085 printk("\n");
5086 }
5087 }
5088 purgatory:
5089 lp->active = 0;
5090 if (lp->phy[0].id) { /* Reset the PHY devices */
1b994b5a 5091 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
1da177e4
LT		 5092 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5093 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
f3b197ac 5094
1da177e4
LT		 5095 de4x5_dbg_mii(dev, k);
5096 }
5097 }
eb034a79 5098 if (!lp->mii_cnt) lp->useMII = false;
1da177e4
LT		 5099
5100 return lp->mii_cnt;
5101}
5102
5103static char *
5104build_setup_frame(struct net_device *dev, int mode)
5105{
5106 struct de4x5_private *lp = netdev_priv(dev);
5107 int i;
5108 char *pa = lp->setup_frame;
f3b197ac 5109
1da177e4
LT		 5110 /* Initialise the setup frame */
5111 if (mode == ALL) {
5112 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5113 }
f3b197ac 5114
1da177e4
LT		 5115 if (lp->setup_f == HASH_PERF) {
5116 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5117 *(pa + i) = dev->dev_addr[i]; /* Host address */
5118 if (i & 0x01) pa += 2;
5119 }
5120 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5121 } else {
5122 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5123 *(pa + (i&1)) = dev->dev_addr[i];
5124 if (i & 0x01) pa += 4;
5125 }
5126 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5127 *(pa + (i&1)) = (char) 0xff;
5128 if (i & 0x01) pa += 4;
5129 }
5130 }
f3b197ac 5131
1da177e4
LT		 5132 return pa; /* Points to the next entry */
5133}
5134
1da177e4
LT		 5135static void
5136disable_ast(struct net_device *dev)
5137{
561b4fbf
AV		 5138 struct de4x5_private *lp = netdev_priv(dev);
5139 del_timer_sync(&lp->timer);
1da177e4
LT		 5140}
5141
5142static long
5143de4x5_switch_mac_port(struct net_device *dev)
5144{
5145 struct de4x5_private *lp = netdev_priv(dev);
5146 u_long iobase = dev->base_addr;
5147 s32 omr;
5148
5149 STOP_DE4X5;
5150
5151 /* Assert the OMR_PS bit in CSR6 */
5152 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5153 OMR_FDX));
5154 omr |= lp->infoblock_csr6;
5155 if (omr & OMR_PS) omr |= OMR_HBD;
5156 outl(omr, DE4X5_OMR);
f3b197ac 5157
1da177e4
LT		 5158 /* Soft Reset */
5159 RESET_DE4X5;
f3b197ac 5160
1da177e4
LT		 5161 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5162 if (lp->chipset == DC21140) {
5163 gep_wr(lp->cache.gepc, dev);
5164 gep_wr(lp->cache.gep, dev);
5165 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5166 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5167 }
5168
5169 /* Restore CSR6 */
5170 outl(omr, DE4X5_OMR);
5171
5172 /* Reset CSR8 */
5173 inl(DE4X5_MFC);
5174
5175 return omr;
5176}
5177
5178static void
5179gep_wr(s32 data, struct net_device *dev)
5180{
5181 struct de4x5_private *lp = netdev_priv(dev);
5182 u_long iobase = dev->base_addr;
5183
5184 if (lp->chipset == DC21140) {
5185 outl(data, DE4X5_GEP);
5186 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5187 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5188 }
5189
5190 return;
5191}
5192
5193static int
5194gep_rd(struct net_device *dev)
5195{
5196 struct de4x5_private *lp = netdev_priv(dev);
5197 u_long iobase = dev->base_addr;
5198
5199 if (lp->chipset == DC21140) {
5200 return inl(DE4X5_GEP);
5201 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5202 return (inl(DE4X5_SIGR) & 0x000fffff);
5203 }
5204
5205 return 0;
5206}
5207
1da177e4
LT		 5208static void
5209yawn(struct net_device *dev, int state)
5210{
5211 struct de4x5_private *lp = netdev_priv(dev);
5212 u_long iobase = dev->base_addr;
5213
5214 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5215
5216 if(lp->bus == EISA) {
5217 switch(state) {
5218 case WAKEUP:
5219 outb(WAKEUP, PCI_CFPM);
5220 mdelay(10);
5221 break;
5222
5223 case SNOOZE:
5224 outb(SNOOZE, PCI_CFPM);
5225 break;
5226
5227 case SLEEP:
5228 outl(0, DE4X5_SICR);
5229 outb(SLEEP, PCI_CFPM);
5230 break;
5231 }
5232 } else {
5233 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5234 switch(state) {
5235 case WAKEUP:
5236 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5237 mdelay(10);
5238 break;
5239
5240 case SNOOZE:
5241 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5242 break;
5243
5244 case SLEEP:
5245 outl(0, DE4X5_SICR);
5246 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5247 break;
5248 }
5249 }
5250
5251 return;
5252}
5253
5254static void
5255de4x5_parse_params(struct net_device *dev)
5256{
5257 struct de4x5_private *lp = netdev_priv(dev);
5258 char *p, *q, t;
5259
5260 lp->params.fdx = 0;
5261 lp->params.autosense = AUTO;
5262
5263 if (args == NULL) return;
5264
5265 if ((p = strstr(args, dev->name))) {
5266 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5267 t = *q;
5268 *q = '\0';
5269
5270 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5271
5272 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5273 if (strstr(p, "TP")) {
5274 lp->params.autosense = TP;
5275 } else if (strstr(p, "TP_NW")) {
5276 lp->params.autosense = TP_NW;
5277 } else if (strstr(p, "BNC")) {
5278 lp->params.autosense = BNC;
5279 } else if (strstr(p, "AUI")) {
5280 lp->params.autosense = AUI;
5281 } else if (strstr(p, "BNC_AUI")) {
5282 lp->params.autosense = BNC;
5283 } else if (strstr(p, "10Mb")) {
5284 lp->params.autosense = _10Mb;
5285 } else if (strstr(p, "100Mb")) {
5286 lp->params.autosense = _100Mb;
5287 } else if (strstr(p, "AUTO")) {
5288 lp->params.autosense = AUTO;
5289 }
5290 }
5291 *q = t;
5292 }
5293
5294 return;
5295}
5296
5297static void
5298de4x5_dbg_open(struct net_device *dev)
5299{
5300 struct de4x5_private *lp = netdev_priv(dev);
5301 int i;
f3b197ac 5302
1da177e4
LT		 5303 if (de4x5_debug & DEBUG_OPEN) {
5304 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5305 printk("\tphysical address: ");
5306 for (i=0;i<6;i++) {
5307 printk("%2.2x:",(short)dev->dev_addr[i]);
5308 }
5309 printk("\n");
5310 printk("Descriptor head addresses:\n");
5311 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5312 printk("Descriptor addresses:\nRX: ");
5313 for (i=0;i<lp->rxRingSize-1;i++){
5314 if (i < 3) {
5315 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5316 }
5317 }
5318 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5319 printk("TX: ");
5320 for (i=0;i<lp->txRingSize-1;i++){
5321 if (i < 3) {
5322 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5323 }
5324 }
5325 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5326 printk("Descriptor buffers:\nRX: ");
5327 for (i=0;i<lp->rxRingSize-1;i++){
5328 if (i < 3) {
5329 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5330 }
5331 }
5332 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5333 printk("TX: ");
5334 for (i=0;i<lp->txRingSize-1;i++){
5335 if (i < 3) {
5336 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5337 }
5338 }
5339 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
c2bb1b9c 5340 printk("Ring size:\nRX: %d\nTX: %d\n",
f3b197ac
JG		 5341 (short)lp->rxRingSize,
5342 (short)lp->txRingSize);
1da177e4 5343 }
f3b197ac 5344
1da177e4
LT		 5345 return;
5346}
5347
5348static void
5349de4x5_dbg_mii(struct net_device *dev, int k)
5350{
5351 struct de4x5_private *lp = netdev_priv(dev);
5352 u_long iobase = dev->base_addr;
f3b197ac 5353
1da177e4
LT		 5354 if (de4x5_debug & DEBUG_MII) {
5355 printk("\nMII device address: %d\n", lp->phy[k].addr);
5356 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5357 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5358 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5359 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5360 if (lp->phy[k].id != BROADCOM_T4) {
5361 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5362 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5363 }
5364 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5365 if (lp->phy[k].id != BROADCOM_T4) {
5366 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5367 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5368 } else {
5369 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5370 }
5371 }
f3b197ac 5372
1da177e4
LT		 5373 return;
5374}
5375
5376static void
5377de4x5_dbg_media(struct net_device *dev)
5378{
5379 struct de4x5_private *lp = netdev_priv(dev);
f3b197ac 5380
1da177e4
LT		 5381 if (lp->media != lp->c_media) {
5382 if (de4x5_debug & DEBUG_MEDIA) {
5383 printk("%s: media is %s%s\n", dev->name,
5384 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5385 (lp->media == TP ? "TP" :
5386 (lp->media == ANS ? "TP/Nway" :
f3b197ac
JG		 5387 (lp->media == BNC ? "BNC" :
5388 (lp->media == AUI ? "AUI" :
5389 (lp->media == BNC_AUI ? "BNC/AUI" :
5390 (lp->media == EXT_SIA ? "EXT SIA" :
1da177e4
LT		 5391 (lp->media == _100Mb ? "100Mb/s" :
5392 (lp->media == _10Mb ? "10Mb/s" :
5393 "???"
5394 ))))))))), (lp->fdx?" full duplex.":"."));
5395 }
5396 lp->c_media = lp->media;
5397 }
f3b197ac 5398
1da177e4
LT		 5399 return;
5400}
5401
5402static void
5403de4x5_dbg_srom(struct de4x5_srom *p)
5404{
5405 int i;
5406
5407 if (de4x5_debug & DEBUG_SROM) {
5408 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5409 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5410 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5411 printk("SROM version: %02x\n", (u_char)(p->version));
0795af57 5412 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
1da177e4 5413
e174961c 5414 printk("Hardware Address: %pM\n", p->ieee_addr);
1da177e4
LT		 5415 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5416 for (i=0; i<64; i++) {
5417 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5418 }
5419 }
5420
5421 return;
5422}
5423
5424static void
5425de4x5_dbg_rx(struct sk_buff *skb, int len)
5426{
5427 int i, j;
5428
5429 if (de4x5_debug & DEBUG_RX) {
e174961c
JB		 5430 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5431 skb->data, &skb->data[6],
1da177e4
LT		 5432 (u_char)skb->data[12],
5433 (u_char)skb->data[13],
5434 len);
5435 for (j=0; len>0;j+=16, len-=16) {
5436 printk(" %03x: ",j);
5437 for (i=0; i<16 && i<len; i++) {
5438 printk("%02x ",(u_char)skb->data[i+j]);
5439 }
5440 printk("\n");
5441 }
5442 }
5443
5444 return;
5445}
5446
5447/*
5448** Perform IOCTL call functions here. Some are privileged operations and the
5449** effective uid is checked in those cases. In the normal course of events
5450** this function is only used for my testing.
5451*/
5452static int
5453de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5454{
5455 struct de4x5_private *lp = netdev_priv(dev);
5456 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5457 u_long iobase = dev->base_addr;
5458 int i, j, status = 0;
5459 s32 omr;
5460 union {
5461 u8 addr[144];
5462 u16 sval[72];
5463 u32 lval[36];
5464 } tmp;
5465 u_long flags = 0;
f3b197ac 5466
1da177e4
LT		 5467 switch(ioc->cmd) {
5468 case DE4X5_GET_HWADDR: /* Get the hardware address */
5469 ioc->len = ETH_ALEN;
5470 for (i=0; i<ETH_ALEN; i++) {
5471 tmp.addr[i] = dev->dev_addr[i];
5472 }
5473 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5474 break;
5475
5476 case DE4X5_SET_HWADDR: /* Set the hardware address */
5477 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5478 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5479 if (netif_queue_stopped(dev))
5480 return -EBUSY;
5481 netif_stop_queue(dev);
5482 for (i=0; i<ETH_ALEN; i++) {
5483 dev->dev_addr[i] = tmp.addr[i];
5484 }
5485 build_setup_frame(dev, PHYS_ADDR_ONLY);
5486 /* Set up the descriptor and give ownership to the card */
f3b197ac 5487 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1da177e4
LT		 5488 SETUP_FRAME_LEN, (struct sk_buff *)1);
5489 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5490 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5491 netif_wake_queue(dev); /* Unlock the TX ring */
5492 break;
5493
1da177e4
LT		 5494 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5495 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5496 printk("%s: Boo!\n", dev->name);
5497 break;
5498
5499 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5500 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5501 omr = inl(DE4X5_OMR);
5502 omr |= OMR_PM;
5503 outl(omr, DE4X5_OMR);
5504 break;
5505
5506 case DE4X5_GET_STATS: /* Get the driver statistics */
5507 {
5508 struct pkt_stats statbuf;
5509 ioc->len = sizeof(statbuf);
5510 spin_lock_irqsave(&lp->lock, flags);
5511 memcpy(&statbuf, &lp->pktStats, ioc->len);
5512 spin_unlock_irqrestore(&lp->lock, flags);
f3b197ac
JG		 5513 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5514 return -EFAULT;
1da177e4
LT		 5515 break;
5516 }
5517 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5518 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5519 spin_lock_irqsave(&lp->lock, flags);
5520 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5521 spin_unlock_irqrestore(&lp->lock, flags);
5522 break;
5523
5524 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5525 tmp.addr[0] = inl(DE4X5_OMR);
5526 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5527 break;
5528
5529 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5530 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5531 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5532 outl(tmp.addr[0], DE4X5_OMR);
5533 break;
5534
5535 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5536 j = 0;
5537 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5538 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5539 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5540 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5541 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5542 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5543 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5544 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5545 ioc->len = j;
5546 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5547 break;
f3b197ac 5548
1da177e4 5549#define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
f3b197ac 5550/*
1da177e4
LT		 5551 case DE4X5_DUMP:
5552 j = 0;
5553 tmp.addr[j++] = dev->irq;
5554 for (i=0; i<ETH_ALEN; i++) {
5555 tmp.addr[j++] = dev->dev_addr[i];
5556 }
5557 tmp.addr[j++] = lp->rxRingSize;
5558 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5559 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
f3b197ac 5560
1da177e4
LT		 5561 for (i=0;i<lp->rxRingSize-1;i++){
5562 if (i < 3) {
5563 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5564 }
5565 }
5566 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5567 for (i=0;i<lp->txRingSize-1;i++){
5568 if (i < 3) {
5569 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5570 }
5571 }
5572 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
f3b197ac 5573
1da177e4
LT		 5574 for (i=0;i<lp->rxRingSize-1;i++){
5575 if (i < 3) {
5576 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5577 }
5578 }
5579 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5580 for (i=0;i<lp->txRingSize-1;i++){
5581 if (i < 3) {
5582 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5583 }
5584 }
5585 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
f3b197ac 5586
1da177e4
LT		 5587 for (i=0;i<lp->rxRingSize;i++){
5588 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5589 }
5590 for (i=0;i<lp->txRingSize;i++){
5591 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5592 }
f3b197ac 5593
1da177e4
LT		 5594 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5595 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5596 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5597 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5598 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5599 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5600 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5601 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
f3b197ac 5602 tmp.lval[j>>2] = lp->chipset; j+=4;
1da177e4
LT		 5603 if (lp->chipset == DC21140) {
5604 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5605 } else {
5606 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5607 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5608 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
f3b197ac 5609 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
1da177e4 5610 }
f3b197ac 5611 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
1da177e4 5612 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
f3b197ac 5613 tmp.lval[j>>2] = lp->active; j+=4;
1da177e4
LT		 5614 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5615 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5616 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5617 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5618 if (lp->phy[lp->active].id != BROADCOM_T4) {
5619 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5620 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5621 }
5622 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5623 if (lp->phy[lp->active].id != BROADCOM_T4) {
5624 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5625 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5626 } else {
5627 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5628 }
5629 }
f3b197ac 5630
1da177e4
LT		 5631 tmp.addr[j++] = lp->txRingSize;
5632 tmp.addr[j++] = netif_queue_stopped(dev);
f3b197ac 5633
1da177e4
LT		 5634 ioc->len = j;
5635 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5636 break;
5637
5638*/
5639 default:
5640 return -EOPNOTSUPP;
5641 }
f3b197ac 5642
1da177e4
LT		 5643 return status;
5644}
5645
5646static int __init de4x5_module_init (void)
5647{
5648 int err = 0;
5649
5650#ifdef CONFIG_PCI
29917620 5651 err = pci_register_driver(&de4x5_pci_driver);
1da177e4
LT		 5652#endif
5653#ifdef CONFIG_EISA
5654 err |= eisa_driver_register (&de4x5_eisa_driver);
5655#endif
5656
5657 return err;
5658}
5659
5660static void __exit de4x5_module_exit (void)
5661{
5662#ifdef CONFIG_PCI
5663 pci_unregister_driver (&de4x5_pci_driver);
5664#endif
5665#ifdef CONFIG_EISA
5666 eisa_driver_unregister (&de4x5_eisa_driver);
5667#endif
5668}
5669
5670module_init (de4x5_module_init);
5671module_exit (de4x5_module_exit);
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